2 * linux/arch/armnommu/mach-s5c7375/head.S
4 * Copyright (C) 2003 Hyok S. Choi
5 * <hyok.choi@samsung.com>
7 * uClinux kernel startup code for s5c7375
8 * which has no proper bootloader for linux startup
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 #include <linux/linkage.h>
26 #include <linux/init.h>
28 #include <asm/assembler.h>
29 #include <asm/mach-types.h>
30 #include <asm/procinfo.h>
31 #include <asm/ptrace.h>
32 #include <asm/mach/arch.h>
34 #define MACHINFO_TYPE 0
35 #define MACHINFO_PHYSRAM 4
36 #define MACHINFO_PHYSIO 8
37 #define MACHINFO_PGOFFIO 12
38 #define MACHINFO_NAME 16
42 * Kernel startup entry point.
45 .type stext, #function
48 mov r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ make sure svc mode
49 msr cpsr_c, r0 @ and all irqs disabled
52 * ARM920T need MMU enable for D-cache.
53 * we just make the identical table before the MMU enabling.
55 #ifdef CONFIG_CPU_MXU_ENABLE
56 /* Write domain id (cp15_r3) */
57 mvn r0, #0 /* Domains 0, 1 = client */
58 mcr p15, 0, r0, c3, c0, 0 /* load domain access register */
59 /* Set control register v4 */
62 mcr p15, 0, r0, c13, c0, 0 /* zero PID */
63 mcr p15, 0, r0, c7, c7, 0 /* invalidate I,D caches */
64 mcr p15, 0, r0, c7, c10, 4 /* drain write buffer */
65 mcr p15, 0, r0, c8, c7, 0 /* invalidate I,D TLBs */
66 mrc p15, 0, r0, c1, c0, 0 /* get control register */
67 bic r0, r0, #0x0001 /* disable MMU */
68 mcr p15, 0, r0, c1, c0, 0 /* write control register */
70 ldr r0,=0x00004000 @ set start of Translation Table base (16k Boundary)
71 mcr p15, 0, r0, c2, c0, 0 @ write to CP15 register 2
74 * Create translation table for flat mapping
75 * Top 12 bits of VA is pointer into table
76 * Create 4096 entries from 000xxxxx to fffxxxxx
81 mov r2,#0b110000000000 @ set access permissions (AP) for full access SVC/USR (11:10)
82 orr r2,r2,#0b000111100000 @ set for domain 15 (8:5)
83 orr r2,r2,#0b000000010000 @ must be 1 (4)
84 orr r2,r2,#0b000000000000 @ set non cachable non bufferable (CB) (3:2)
85 orr r2,r2,#0b000000000010 @ set for 1Mb section (1:0)
87 orr r3,r2,r1,lsl#20 @ use loop counter to create individual table entries
88 str r3,[r0,r1,lsl#2] @ str r3 at TTB base + loopcount*4
89 subs r1,r1,#1 @ decrement loop counter
92 /* resetting the SDRAM area to cacheable*/
93 mov r1, #0x003 @ loop counter
95 mov r2,#0b110000000000 @ set access permissions (AP) for full access SVC/USR (11:10)
96 orr r2,r2,#0b000111100000 @ set for domain 15 (8:5)
97 orr r2,r2,#0b000000010000 @ must be 1 (4)
98 orr r2,r2,#0b000000001100 @ set cachable but unbufferable (CB) (3:2)
99 orr r2,r2,#0b000000000010 @ set for 1Mb section (1:0)
102 orr r3,r2,r1,lsl#20 @ use loop counter to create individual table entries
103 str r3,[r0,r1,lsl#2] @ str r3 at TTB base + loopcount*4
104 subs r1,r1,#1 @ decrement loop counter
106 @init_domains : we define all domains are manager. so no access permission check is occured.
107 mvn r0, #0 @ trick. 0 -1 == 0xFFFFFFFF
108 mcr p15, 0, r0, c3, c0, 0 @ write to CP15 register 5
110 * set global core configurations
112 mrc p15, 0, r0, c1, c0, 0 @ read CP15 register 1 into r0
114 orr r0, r0, #(0x1 <<12) @ enable I Cache
115 orr r0, r0, #(0x1 <<2) @ enable D Cache
116 orr r0, r0, #(0b11 <<30) @ enable asynchronous clocking mode
117 orr r0, r0, #0x1 @ enable MMU
119 mcr p15, 0, r0, c1, c0, 0 @ write cp15 register 1
124 * stuffs for cache are done.
125 * Now we setup the stack and machine id, and start the kernel!
129 ldmia r5, {r5, r6, r8, r9, sp} @ Setup stack
131 /* Copy data sections to their new home. */
140 /* Pretend we know what our processor code is (for arm_id) */
142 ldr r2, S5C7375_PROCESSOR_TYPE
145 ldr r2, S5C7375_MACH_TYPE
151 LC0: .long __bss_start
154 .long __machine_arch_type
155 .long init_thread_union+8192
157 S5C7375_PROCESSOR_TYPE:
160 .long MACH_TYPE_S5C7375
162 #include "../kernel/head-common.S"