arch/arm/mach-moxart/dma.h

   1 #ifndef ARCH_CPE_RTC_H
   2 #define ARCH_CPE_RTC_H
   3
   4  /* registers */
   5 #define DMA_INT                                         0x0
   6 #define DMA_INT_TC                                      0x4
   7 #define DMA_INT_TC_CLR                          0x8
   8 #define DMA_INT_ERR                                     0xC
   9 #define DMA_INT_ERR_CLR                         0x10
  10 #define DMA_TC                                          0x14
  11 #define DMA_ERR                                         0x18
  12 #define DMA_CH_EN                                       0x1C
  13 #define DMA_CH_BUSY                                     0x20
  14 #define DMA_CSR                                         0x24
  15 #define DMA_SYNC                                        0x28
  16
  17 #define DMA_C0_DevRegBase                       0x40
  18 #define DMA_C0_DevDtBase                        0x80
  19
  20 #define DMA_CH_CFG_REG_OFFSET           0x20
  21 #define DMA_C0_CSR                                      0x100
  22 #define DMA_C0_CFG                                      0x104
  23 #define DMA_C0_SrcAddr                          0x108
  24 #define DMA_C0_DstAddr                          0x10C
  25 #define DMA_C0_LLP                                      0x110
  26 #define DMA_C0_SIZE                                     0x114
  27
  28 /* bit mapping of main configuration status register(CSR) */
  29 #define DMA_CSR_M1ENDIAN                        0x00000004
  30 #define DMA_CSR_M0ENDIAN                        0x00000002
  31 #define DMA_CSR_DMACEN                          0x00000001
  32
  33 /* bit mapping of channel control register */
  34 #define DMA_CSR_TC_MSK                          0x80000000
  35 #define DMA_CSR_CHPRJ_HIGHEST           0x00C00000
  36 #define DMA_CSR_CHPRJ_2ND                       0x00800000
  37 #define DMA_CSR_CHPRJ_3RD                       0x00400000
  38 #define DMA_CSR_PRTO3                           0x00200000
  39 #define DMA_CSR_PRTO2                           0x00100000
  40 #define DMA_CSR_PRTO1                           0x00080000
  41 #define DMA_CSR_SRC_BURST_SIZE_1        0x00000000
  42 #define DMA_CSR_SRC_BURST_SIZE_4        0x00010000
  43 #define DMA_CSR_SRC_BURST_SIZE_8        0x00020000
  44 #define DMA_CSR_SRC_BURST_SIZE_16       0x00030000
  45 #define DMA_CSR_SRC_BURST_SIZE_32       0x00040000
  46 #define DMA_CSR_SRC_BURST_SIZE_64       0x00050000
  47 #define DMA_CSR_SRC_BURST_SIZE_128      0x00060000
  48 #define DMA_CSR_SRC_BURST_SIZE_256      0x00070000
  49
  50 #define DMA_CSR_ABT                                     0x00008000
  51 #define DMA_CSR_SRC_WIDTH_8                     0x00000000
  52 #define DMA_CSR_SRC_WIDTH_16            0x00000800
  53 #define DMA_CSR_SRC_WIDTH_32            0x00001000
  54
  55 #define DMA_CSR_DST_WIDTH_8                     0x00000000
  56 #define DMA_CSR_DST_WIDTH_16            0x00000100
  57 #define DMA_CSR_DST_WIDTH_32            0x00000200
  58
  59 #define DMA_CSR_MODE_NORMAL                     0x00000000
  60 #define DMA_CSR_MODE_HANDSHAKE          0x00000080
  61
  62 #define DMA_CSR_SRC_INCREMENT           0x00000000
  63 #define DMA_CSR_SRC_DECREMENT           0x00000020
  64 #define DMA_CSR_SRC_FIX                         0x00000040
  65
  66 #define DMA_CSR_DST_INCREMENT           0x00000000
  67 #define DMA_CSR_DST_DECREMENT           0x00000008
  68 #define DMA_CSR_DST_FIX                         0x00000010
  69
  70 #define DMA_CSR_SRC_SEL                         0x00000004
  71 #define DMA_CSR_DST_SEL                         0x00000002
  72 #define DMA_CSR_CH_ENABLE                       0x00000001
  73
  74
  75 #define DMA_MAX_SIZE                            0x10000
  76 #define DAM_CHANNEL_NUMBER                      8
  77
  78
  79 typedef struct
  80 {
  81         UINT32 enable:1;
  82         UINT32 dst_sel:1;
  83         UINT32 src_sel:1;
  84         UINT32 dst_ctrl:2;
  85         UINT32 src_ctrl:2;
  86         UINT32 mode:1;
  87         UINT32 dst_width:3;
  88         UINT32 src_width:3;
  89         UINT32 reserved1:1;
  90         UINT32 abt:1;
  91         UINT32 src_size:3;
  92         UINT32 prot:3;
  93         UINT32 priority:2;
  94         UINT32 reserved0:7;
  95         UINT32 tc_msk:1;
  96 }fLib_DMA_CH_CSR_t;
  97
  98 typedef struct
  99 {
 100         UINT32 int_tc_msk:1;
 101         UINT32 int_err_msk:1;
 102         UINT32 reserved0:30;
 103 }fLib_DMA_CH_CFG_t;
 104
 105 typedef struct
 106 {
 107         UINT32 master_id:1;
 108         UINT32 reserved:1;
 109         UINT32 link_list_addr:30;
 110 }fLib_DMA_CH_LLP_t;
 111
 112 typedef struct
 113 {
 114         UINT32 size:12;
 115         UINT32 reserved:4;
 116
 117         UINT32 dst_sel:1;
 118         UINT32 src_sel:1;
 119         UINT32 dst_ctrl:2;
 120         UINT32 src_ctrl:2;
 121         UINT32 dst_width:3;
 122         UINT32 src_width:3;
 123         UINT32 tc_msk:1;
 124         UINT32 reserved1:3;
 125 }fLib_DMA_LLP_CTRL_t;
 126
 127 typedef struct
 128 {
 129         fLib_DMA_CH_CSR_t csr;
 130         fLib_DMA_CH_CFG_t cfg;
 131         UINT32 src_addr;
 132         UINT32 dst_addr;
 133         fLib_DMA_CH_LLP_t llp;
 134         UINT32 size;
 135         UINT32 dummy[2];
 136 }fLib_DMA_CH_t;
 137
 138 typedef struct
 139 {
 140         UINT32 src_addr;
 141         UINT32 dst_addr;
 142         fLib_DMA_CH_LLP_t llp;
 143         fLib_DMA_LLP_CTRL_t llp_ctrl;
 144 }fLib_DMA_LLD_t;
 145
 146
 147 typedef struct
 148 {
 149         UINT32 dma_int;
 150         UINT32 dma_int_tc;
 151         UINT32 dma_int_tc_clr;
 152         UINT32 dma_int_err;
 153         UINT32 dma_int_err_clr;
 154         UINT32 dma_tc;
 155         UINT32 dma_err;
 156         UINT32 dma_ch_enable;
 157         UINT32 dma_ch_busy;
 158         UINT32 dma_csr;
 159         UINT32 dma_sync;
 160         UINT32 dummy0[5];
 161
 162         UINT32 dma_ch_dev_reg_base[8];
 163         UINT32 dummy1[8];
 164
 165         UINT32 dma_ch_dev_dt_base[8];
 166
 167         UINT32 dummy2[24];
 168
 169         fLib_DMA_CH_t dma_ch[7];
 170 }fLib_DMA_Reg_t;
 171
 172
 173 #ifdef not_complete_yet
 174 /*  -------------------------------------------------------------------------------
 175  *   API
 176  *  -------------------------------------------------------------------------------
 177  */
 178
 179 extern int    fLib_IsDMAChannelBusy(INT32 Channel);
 180 extern int    fLib_IsDMAChannelEnable(INT32 Channel);
 181 extern UINT32 fLib_GetDMAIntStatus(void);
 182 extern UINT32 fLib_GetDMAChannelIntStatus(INT32 Channel);
 183 extern int    fLib_GetDMABusyStatus(void);
 184 extern int    fLib_GetDMAEnableStatus(void);
 185
 186 extern void   fLib_InitDMA(UINT32 M0_BigEndian, UINT32 M1_BigEndian, UINT32 Sync);
 187 extern void   fLib_EnableDMAChannel(INT32 Channel);
 188 extern void   fLib_ClearDMAChannelIntStatus(INT32 Channel);
 189
 190 extern void   fLib_SetDMAChannelCfg(INT32 Channel, fLib_DMA_CH_CSR_t Csr);
 191 extern fLib_DMA_CH_CSR_t fLib_GetDMAChannelCfg(INT32 Channel);
 192 extern void   fLib_DMA_CHIntMask(INT32 Channel, fLib_DMA_CH_CFG_t Mask);
 193 extern void   fLib_DMA_CHLinkList(INT32 Channel, fLib_DMA_CH_LLP_t LLP);
 194 extern void   fLib_DMA_CHDataCtrl(INT32 Channel, UINT32 SrcAddr, UINT32 DstAddr, UINT32 Size);
 195 #endif /* end_of_not */
 196
 197 #endif