7 #define DMA_INT_TC_CLR 0x8
8 #define DMA_INT_ERR 0xC
9 #define DMA_INT_ERR_CLR 0x10
12 #define DMA_CH_EN 0x1C
13 #define DMA_CH_BUSY 0x20
17 #define DMA_C0_DevRegBase 0x40
18 #define DMA_C0_DevDtBase 0x80
20 #define DMA_CH_CFG_REG_OFFSET 0x20
21 #define DMA_C0_CSR 0x100
22 #define DMA_C0_CFG 0x104
23 #define DMA_C0_SrcAddr 0x108
24 #define DMA_C0_DstAddr 0x10C
25 #define DMA_C0_LLP 0x110
26 #define DMA_C0_SIZE 0x114
28 /* bit mapping of main configuration status register(CSR) */
29 #define DMA_CSR_M1ENDIAN 0x00000004
30 #define DMA_CSR_M0ENDIAN 0x00000002
31 #define DMA_CSR_DMACEN 0x00000001
33 /* bit mapping of channel control register */
34 #define DMA_CSR_TC_MSK 0x80000000
35 #define DMA_CSR_CHPRJ_HIGHEST 0x00C00000
36 #define DMA_CSR_CHPRJ_2ND 0x00800000
37 #define DMA_CSR_CHPRJ_3RD 0x00400000
38 #define DMA_CSR_PRTO3 0x00200000
39 #define DMA_CSR_PRTO2 0x00100000
40 #define DMA_CSR_PRTO1 0x00080000
41 #define DMA_CSR_SRC_BURST_SIZE_1 0x00000000
42 #define DMA_CSR_SRC_BURST_SIZE_4 0x00010000
43 #define DMA_CSR_SRC_BURST_SIZE_8 0x00020000
44 #define DMA_CSR_SRC_BURST_SIZE_16 0x00030000
45 #define DMA_CSR_SRC_BURST_SIZE_32 0x00040000
46 #define DMA_CSR_SRC_BURST_SIZE_64 0x00050000
47 #define DMA_CSR_SRC_BURST_SIZE_128 0x00060000
48 #define DMA_CSR_SRC_BURST_SIZE_256 0x00070000
50 #define DMA_CSR_ABT 0x00008000
51 #define DMA_CSR_SRC_WIDTH_8 0x00000000
52 #define DMA_CSR_SRC_WIDTH_16 0x00000800
53 #define DMA_CSR_SRC_WIDTH_32 0x00001000
55 #define DMA_CSR_DST_WIDTH_8 0x00000000
56 #define DMA_CSR_DST_WIDTH_16 0x00000100
57 #define DMA_CSR_DST_WIDTH_32 0x00000200
59 #define DMA_CSR_MODE_NORMAL 0x00000000
60 #define DMA_CSR_MODE_HANDSHAKE 0x00000080
62 #define DMA_CSR_SRC_INCREMENT 0x00000000
63 #define DMA_CSR_SRC_DECREMENT 0x00000020
64 #define DMA_CSR_SRC_FIX 0x00000040
66 #define DMA_CSR_DST_INCREMENT 0x00000000
67 #define DMA_CSR_DST_DECREMENT 0x00000008
68 #define DMA_CSR_DST_FIX 0x00000010
70 #define DMA_CSR_SRC_SEL 0x00000004
71 #define DMA_CSR_DST_SEL 0x00000002
72 #define DMA_CSR_CH_ENABLE 0x00000001
75 #define DMA_MAX_SIZE 0x10000
76 #define DAM_CHANNEL_NUMBER 8
101 UINT32 int_err_msk
:1;
109 UINT32 link_list_addr
:30;
125 }fLib_DMA_LLP_CTRL_t
;
129 fLib_DMA_CH_CSR_t csr
;
130 fLib_DMA_CH_CFG_t cfg
;
133 fLib_DMA_CH_LLP_t llp
;
142 fLib_DMA_CH_LLP_t llp
;
143 fLib_DMA_LLP_CTRL_t llp_ctrl
;
151 UINT32 dma_int_tc_clr
;
153 UINT32 dma_int_err_clr
;
156 UINT32 dma_ch_enable
;
162 UINT32 dma_ch_dev_reg_base
[8];
165 UINT32 dma_ch_dev_dt_base
[8];
169 fLib_DMA_CH_t dma_ch
[7];
173 #ifdef not_complete_yet
174 /* -------------------------------------------------------------------------------
176 * -------------------------------------------------------------------------------
179 extern int fLib_IsDMAChannelBusy(INT32 Channel
);
180 extern int fLib_IsDMAChannelEnable(INT32 Channel
);
181 extern UINT32
fLib_GetDMAIntStatus(void);
182 extern UINT32
fLib_GetDMAChannelIntStatus(INT32 Channel
);
183 extern int fLib_GetDMABusyStatus(void);
184 extern int fLib_GetDMAEnableStatus(void);
186 extern void fLib_InitDMA(UINT32 M0_BigEndian
, UINT32 M1_BigEndian
, UINT32 Sync
);
187 extern void fLib_EnableDMAChannel(INT32 Channel
);
188 extern void fLib_ClearDMAChannelIntStatus(INT32 Channel
);
190 extern void fLib_SetDMAChannelCfg(INT32 Channel
, fLib_DMA_CH_CSR_t Csr
);
191 extern fLib_DMA_CH_CSR_t
fLib_GetDMAChannelCfg(INT32 Channel
);
192 extern void fLib_DMA_CHIntMask(INT32 Channel
, fLib_DMA_CH_CFG_t Mask
);
193 extern void fLib_DMA_CHLinkList(INT32 Channel
, fLib_DMA_CH_LLP_t LLP
);
194 extern void fLib_DMA_CHDataCtrl(INT32 Channel
, UINT32 SrcAddr
, UINT32 DstAddr
, UINT32 Size
);
195 #endif /* end_of_not */