arch/arm/mach-lpc22xx/head.S

   1 /*
   2  *  linux/arch/arm/mach-lpc22xx/head.S
   3  *
   4  *  uClinux kernel startup code for lpc22xx
   5  *  which has no proper bootloader for linux startup
   6  *  because of XIP.
   7  */
   8 #include <linux/linkage.h>
   9 #include <linux/init.h>
  10
  11 #include <asm/assembler.h>
  12 #include <asm/mach-types.h>
  13 #include <asm/procinfo.h>
  14 #include <asm/ptrace.h>
  15 #include <asm/mach/arch.h>
  16 #include <asm/arch/hardware.h>
  17 /*
  18  * Kernel startup entry point.
  19  */
  20         __INIT
  21         .type   stext, #function
  22 ENTRY(stext)
  23
  24         mov     r12, r0
  25         mov     r0, #PSR_F_BIT | PSR_I_BIT | SVC_MODE   @ make sure svc mode
  26         msr     cpsr_c, r0                      @ and all irqs disabled
  27
  28 /* Do basic initialization */
  29 /* Set the parameters of PLL, PINSEL, and MEMMAP carefully according to your board */
  30 /* These settings can be done in your bootloader instead. */
  31
  32                 ldr     r2,rREG_VPBDIV
  33 #if((LPC22xx_Fcclk /4)/LPC22xx_Fpclk)==1
  34                 mov     r1,#0x0
  35 #endif
  36 #if((LPC22xx_Fcclk /4)/LPC22xx_Fpclk)==2
  37                 mov     r1,#0x2
  38 #endif
  39 #if((LPC22xx_Fcclk /4)/LPC22xx_Fpclk)==4
  40                 mov     r1,#0x1
  41 #endif
  42                 str     r1,[r2]
  43
  44                 ldr     r2,rREG_PLLCFG
  45
  46 #if(LPC22xx_Fcco/LPC22xx_Fcclk/2)==1
  47                 mov     r1,#(((LPC22xx_Fcclk/CONFIG_LPC22xx_Fosc)-1))
  48 #endif
  49 #if(LPC22xx_Fcco/LPC22xx_Fcclk/2)==2
  50                 mov     r1,#(((LPC22xx_Fcclk/CONFIG_LPC22xx_Fosc)-1)|(1<<5))
  51 #endif
  52 #if(LPC22xx_Fcco/LPC22xx_Fcclk/2)==4
  53                 mov     r1,#(((LPC22xx_Fcclk/CONFIG_LPC22xx_Fosc)-1)|(2<<5))
  54 #endif
  55 #if(LPC22xx_Fcco/LPC22xx_Fcclk/2)==8
  56                 mov     r1,#(((LPC22xx_Fcclk/CONFIG_LPC22xx_Fosc)-1)|(3<<5))
  57 #endif
  58
  59                 str     r1,[r2]
  60
  61                 ldr     r2,rREG_PLLCON
  62                 mov     r1,#0x01
  63                 str     r1,[r2]
  64
  65                 ldr     r2,rREG_PLLFEED
  66                 mov     r1,#0xAA
  67                 str     r1,[r2]
  68                 mov     r1,#0x55
  69                 str     r1,[r2]
  70
  71 1:              ldr     r2,rREG_PLLSTAT
  72                 ldr     r1,[r2]
  73                 ands    r1,r1,#0x400
  74                 beq     1b
  75
  76                 ldr     r2,rREG_PLLCON
  77                 mov     r1,#0x03
  78                 str     r1,[r2]
  79
  80                 ldr     r2,rREG_PLLFEED
  81                 mov     r1,#0xAA
  82                 str     r1,[r2]
  83                 mov     r1,#0x55
  84                 str     r1,[r2]
  85
  86                 ldr     r2,rREG_PINSEL0
  87                 ldr     r1,[r2]
  88                 and     r1,r1,#~0x0f
  89                 orr     r1,r1,#0x05
  90                 str     r1,[r2]
  91
  92                 ldr     r2,rREG_MEMMAP
  93                 mov     r1,#0x03
  94                 str     r1,[r2]
  95
  96                 b       8f
  97
  98 rREG_PLLCFG:
  99         .long   REG_PLLCFG
 100 rREG_PLLCON:
 101         .long   REG_PLLCON
 102 rREG_PLLFEED:
 103         .long   REG_PLLFEED
 104 rREG_VPBDIV:
 105         .long   REG_VPBDIV
 106 rREG_PINSEL0:
 107         .long   REG_PINSEL0
 108 rREG_MEMMAP:
 109         .long   REG_MEMMAP
 110 rREG_PLLSTAT:
 111         .long   REG_PLLSTAT
 112
 113 VPBDIV_DAT:
 114         .long           0x00                    /* one fourth of cclk */
 115 PLLCFG_DAT:
 116         .long           0x23                    /* Fosc=10Mhz cclk=40Mhz*/
 117 PLLCON_DAT:
 118         .long           0x03                    /* PLL enable & connecte*/
 119
 120 8:
 121
 122     adr r5, LC0
 123     ldmia       r5, {r5, r6, r8, r9, sp}                        @ Setup stack
 124
 125     /*  Copy data sections to their new home.  */
 126
 127
 128     /*  Clear BSS */
 129     mov r4, #0
 130 1:  cmp r5, r8
 131     strcc       r4, [r5],#4
 132     bcc 1b
 133
 134   /*  Pretend we know what our processor code is (for arm_id)   */
 135
 136         ldr     r2, LPC22xx_PROCESSOR_TYPE
 137
 138         str     r2, [r6]
 139         ldr     r2, LPC22xx_MACH_TYPE
 140         str     r2, [r9]
 141
 142         mov fp, #0
 143         b       start_kernel
 144
 145 LC0:
 146         .long   __bss_start
 147         .long   processor_id
 148         .long   _end
 149         .long   __machine_arch_type
 150         .long   init_thread_union+8192
 151
 152         .align  8
 153
 154 LPC22xx_PROCESSOR_TYPE:
 155         .long   0x22000000
 156 LPC22xx_MACH_TYPE:
 157         .long   MACH_TYPE_LPC22xx
 158