2 * linux/arch/arm/kernel/head.S
4 * Copyright (C) 1994-2002 Russell King
5 * Copyright (c) 2003 ARM Limited
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * Kernel startup code for all 32-bit CPUs
14 #include <linux/linkage.h>
15 #include <linux/init.h>
17 #include <asm/assembler.h>
18 #include <asm/domain.h>
19 #include <asm/procinfo.h>
20 #include <asm/ptrace.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/memory.h>
23 #include <asm/thread_info.h>
24 #include <asm/system.h>
26 #define KERNEL_RAM_ADDR (PAGE_OFFSET + TEXT_OFFSET)
29 * swapper_pg_dir is the virtual address of the initial page table.
30 * We place the page tables 16K below KERNEL_RAM_ADDR. Therefore, we must
31 * make sure that KERNEL_RAM_ADDR is correctly set. Currently, we expect
32 * the least significant 16 bits to be 0x8000, but we could probably
33 * relax this restriction to KERNEL_RAM_ADDR >= PAGE_OFFSET + 0x4000.
35 #if (KERNEL_RAM_ADDR & 0xffff) != 0x8000
36 #error KERNEL_RAM_ADDR must start at 0xXXXX8000
40 .equ swapper_pg_dir, KERNEL_RAM_ADDR - 0x4000
43 ldr \rd, =(__virt_to_phys(KERNEL_RAM_ADDR - 0x4000))
46 #ifdef CONFIG_XIP_KERNEL
47 #define TEXTADDR XIP_VIRT_ADDR(CONFIG_XIP_PHYS_ADDR)
49 #define TEXTADDR KERNEL_RAM_ADDR
53 * Kernel startup entry point.
54 * ---------------------------
56 * This is normally called from the decompressor code. The requirements
57 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0,
60 * This code is mostly position independent, so if you link the kernel at
61 * 0xc0008000, you call this at __pa(0xc0008000).
63 * See linux/arch/arm/tools/mach-types for the complete list of machine
66 * We're trying to keep crap to a minimum; DO NOT add any machine specific
67 * crap here - that's what the boot loader (or in extreme, well justified
68 * circumstances, zImage) is for.
71 .type stext, %function
73 #if 1 /* add by Victor Yu. 02-08-2007 */
74 mov r1, #MACH_TYPE_MOXART
76 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE @ ensure svc mode
78 mrc p15, 0, r9, c0, c0 @ get processor id
79 bl __lookup_processor_type @ r5=procinfo r9=cpuid
80 movs r10, r5 @ invalid processor (r5=0)?
81 beq __error_p @ yes, error 'p'
82 bl __lookup_machine_type @ r5=machinfo
83 movs r8, r5 @ invalid machine (r5=0)?
84 beq __error_a @ yes, error 'a'
85 bl __create_page_tables
88 * The following calls CPU specific code in a position independent
89 * manner. See arch/arm/mm/proc-*.S for details. r10 = base of
90 * xxx_proc_info structure selected by __lookup_machine_type
91 * above. On return, the CPU will be ready for the MMU to be
92 * turned on, and r0 will hold the CPU control register value.
94 ldr r13, __switch_data @ address to jump to after
95 @ mmu has been enabled
96 adr lr, __enable_mmu @ return (PIC) address
97 add pc, r10, #PROCINFO_INITFUNC
99 #if defined(CONFIG_SMP)
100 .type secondary_startup, #function
101 ENTRY(secondary_startup)
103 * Common entry point for secondary CPUs.
105 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup
106 * the processor type - there is no need to check the machine type
107 * as it has already been validated by the primary processor.
109 msr cpsr_c, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
110 mrc p15, 0, r9, c0, c0 @ get processor id
111 bl __lookup_processor_type
112 movs r10, r5 @ invalid processor?
113 moveq r0, #'p' @ yes, error 'p'
117 * Use the page tables supplied from __cpu_up.
119 adr r4, __secondary_data
120 ldmia r4, {r5, r7, r13} @ address to jump to after
121 sub r4, r4, r5 @ mmu has been enabled
122 ldr r4, [r7, r4] @ get secondary_data.pgdir
123 adr lr, __enable_mmu @ return address
124 add pc, r10, #PROCINFO_INITFUNC @ initialise processor
125 @ (return control reg)
128 * r6 = &secondary_data
130 ENTRY(__secondary_switched)
131 ldr sp, [r7, #4] @ get secondary_data.stack
133 b secondary_start_kernel
135 .type __secondary_data, %object
139 .long __secondary_switched
140 #endif /* defined(CONFIG_SMP) */
145 * Setup common bits before finally enabling the MMU. Essentially
146 * this is just loading the page table pointer and domain access
149 .type __enable_mmu, %function
151 #ifdef CONFIG_ALIGNMENT_TRAP
156 #ifdef CONFIG_CPU_DCACHE_DISABLE
159 #ifdef CONFIG_CPU_BPREDICT_DISABLE
162 #ifdef CONFIG_CPU_ICACHE_DISABLE
165 mov r5, #(domain_val(DOMAIN_USER, DOMAIN_MANAGER) | \
166 domain_val(DOMAIN_KERNEL, DOMAIN_MANAGER) | \
167 domain_val(DOMAIN_TABLE, DOMAIN_MANAGER) | \
168 domain_val(DOMAIN_IO, DOMAIN_CLIENT))
169 mcr p15, 0, r5, c3, c0, 0 @ load domain access register
170 mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
174 * Enable the MMU. This completely changes the structure of the visible
175 * memory space. You will not be able to trace execution through this.
176 * If you have an enquiry about this, *please* check the linux-arm-kernel
177 * mailing list archives BEFORE sending another post to the list.
179 * r0 = cp#15 control register
180 * r13 = *virtual* address to jump to upon completion
182 * other registers depend on the function called upon completion
185 .type __turn_mmu_on, %function
188 mcr p15, 0, r0, c1, c0, 0 @ write control reg
189 mrc p15, 0, r3, c0, c0, 0 @ read id reg
197 * Setup the initial page tables. We only setup the barest
198 * amount which are required to get the kernel running, which
199 * generally means mapping in the kernel code.
206 * r0, r3, r6, r7 corrupted
207 * r4 = physical page table address
209 .type __create_page_tables, %function
210 __create_page_tables:
211 pgtbl r4 @ page table address
214 * Clear the 16K level 1 swapper page table
226 ldr r7, [r10, #PROCINFO_MM_MMUFLAGS] @ mm_mmuflags
229 * Create identity mapping for first MB of kernel to
230 * cater for the MMU enable. This identity mapping
231 * will be removed by paging_init(). We use our current program
232 * counter to determine corresponding section base address.
234 mov r6, pc, lsr #20 @ start of kernel section
235 orr r3, r7, r6, lsl #20 @ flags + kernel base
236 str r3, [r4, r6, lsl #2] @ identity mapping
239 * Now setup the pagetables for our kernel direct
242 add r0, r4, #(TEXTADDR & 0xff000000) >> 18 @ start of kernel
243 str r3, [r0, #(TEXTADDR & 0x00f00000) >> 18]!
245 ldr r6, =(_end - PAGE_OFFSET - 1) @ r6 = number of sections
246 mov r6, r6, lsr #20 @ needed for kernel minus 1
248 1: add r3, r3, #1 << 20
254 * Then map first 1MB of ram in case it contains our boot params.
256 add r0, r4, #PAGE_OFFSET >> 18
257 orr r6, r7, #PHYS_OFFSET
260 #ifdef CONFIG_XIP_KERNEL
262 * Map some ram to cover our .data and .bss areas.
263 * Mapping 3MB should be plenty.
265 sub r3, r4, #PHYS_OFFSET
267 add r0, r0, r3, lsl #2
268 add r6, r6, r3, lsl #20
270 add r6, r6, #(1 << 20)
272 add r6, r6, #(1 << 20)
276 #ifdef CONFIG_DEBUG_LL
277 ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags
279 * Map in IO space for serial debugging.
280 * This allows debug messages to be output
281 * via a serial console before paging_init.
283 ldr r3, [r8, #MACHINFO_PGOFFIO]
285 rsb r3, r3, #0x4000 @ PTRS_PER_PGD*sizeof(long)
286 cmp r3, #0x0800 @ limit to 512MB
289 ldr r3, [r8, #MACHINFO_PHYSIO]
295 #if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS)
297 * If we're using the NetWinder or CATS, we also need to map
298 * in the 16550-type serial port for the debug messages
300 add r0, r4, #0xff000000 >> 18
301 orr r3, r7, #0x7c000000
304 #ifdef CONFIG_ARCH_RPC
306 * Map in screen at 0x02000000 & SCREEN2_BASE
307 * Similar reasons here - for debug. This is
308 * only for Acorn RiscPC architectures.
310 add r0, r4, #0x02000000 >> 18
311 orr r3, r7, #0x02000000
313 add r0, r4, #0xd8000000 >> 18
320 #include "head-common.S"