qemu/hw/pci.c

   1 /*
   2  * QEMU PCI bus manager
   3  *
   4  * Copyright (c) 2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "monitor.h"
  27 #include "net.h"
  28 #include "virtio-net.h"
  29 #include "sysemu.h"
  30 #include "pc.h"
  31 #include "qemu-kvm.h"
  32 #include "device-assignment.h"
  33
  34 //#define DEBUG_PCI
  35
  36 struct PCIBus {
  37     int bus_num;
  38     int devfn_min;
  39     pci_set_irq_fn set_irq;
  40     pci_map_irq_fn map_irq;
  41     uint32_t config_reg; /* XXX: suppress */
  42     /* low level pic */
  43     SetIRQFunc *low_set_irq;
  44     qemu_irq *irq_opaque;
  45     PCIDevice *devices[256];
  46     PCIDevice *parent_dev;
  47     PCIBus *next;
  48     /* The bus IRQ state is the logical OR of the connected devices.
  49        Keep a count of the number of devices with raised IRQs.  */
  50     int nirq;
  51     int irq_count[];
  52 };
  53
  54 static void pci_update_mappings(PCIDevice *d);
  55 static void pci_set_irq(void *opaque, int irq_num, int level);
  56
  57 target_phys_addr_t pci_mem_base;
  58 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
  59 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
  60 static int pci_irq_index;
  61 static PCIBus *first_bus;
  62
  63 static void pcibus_save(QEMUFile *f, void *opaque)
  64 {
  65     PCIBus *bus = (PCIBus *)opaque;
  66     int i;
  67
  68     qemu_put_be32(f, bus->nirq);
  69     for (i = 0; i < bus->nirq; i++)
  70         qemu_put_be32(f, bus->irq_count[i]);
  71 }
  72
  73 static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
  74 {
  75     PCIBus *bus = (PCIBus *)opaque;
  76     int i, nirq;
  77
  78     if (version_id != 1)
  79         return -EINVAL;
  80
  81     nirq = qemu_get_be32(f);
  82     if (bus->nirq != nirq) {
  83         fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
  84                 nirq, bus->nirq);
  85         return -EINVAL;
  86     }
  87
  88     for (i = 0; i < nirq; i++)
  89         bus->irq_count[i] = qemu_get_be32(f);
  90
  91     return 0;
  92 }
  93
  94 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  95                          qemu_irq *pic, int devfn_min, int nirq)
  96 {
  97     PCIBus *bus;
  98     static int nbus = 0;
  99
 100     bus = qemu_mallocz(sizeof(PCIBus) + (nirq * sizeof(int)));
 101     bus->set_irq = set_irq;
 102     bus->map_irq = map_irq;
 103     bus->irq_opaque = pic;
 104     bus->devfn_min = devfn_min;
 105     bus->nirq = nirq;
 106     first_bus = bus;
 107     register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
 108     return bus;
 109 }
 110
 111 static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
 112 {
 113     PCIBus *bus;
 114     bus = qemu_mallocz(sizeof(PCIBus));
 115     bus->map_irq = map_irq;
 116     bus->parent_dev = dev;
 117     bus->next = dev->bus->next;
 118     dev->bus->next = bus;
 119     return bus;
 120 }
 121
 122 int pci_bus_num(PCIBus *s)
 123 {
 124     return s->bus_num;
 125 }
 126
 127 void pci_device_save(PCIDevice *s, QEMUFile *f)
 128 {
 129     int i;
 130
 131     qemu_put_be32(f, 2); /* PCI device version */
 132     qemu_put_buffer(f, s->config, 256);
 133     for (i = 0; i < 4; i++)
 134         qemu_put_be32(f, s->irq_state[i]);
 135 }
 136
 137 int pci_device_load(PCIDevice *s, QEMUFile *f)
 138 {
 139     uint32_t version_id;
 140     int i;
 141
 142     version_id = qemu_get_be32(f);
 143     if (version_id > 2)
 144         return -EINVAL;
 145     qemu_get_buffer(f, s->config, 256);
 146     pci_update_mappings(s);
 147
 148     if (version_id >= 2)
 149         for (i = 0; i < 4; i ++)
 150             s->irq_state[i] = qemu_get_be32(f);
 151
 152     return 0;
 153 }
 154
 155 static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
 156 {
 157     uint16_t *id;
 158
 159     id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
 160     id[0] = cpu_to_le16(pci_default_sub_vendor_id);
 161     id[1] = cpu_to_le16(pci_default_sub_device_id);
 162     return 0;
 163 }
 164
 165 /*
 166  * Parse pci address in qemu command
 167  * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
 168  */
 169 static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 170 {
 171     const char *p;
 172     char *e;
 173     unsigned long val;
 174     unsigned long dom = 0, bus = 0;
 175     unsigned slot = 0;
 176
 177     p = addr;
 178     val = strtoul(p, &e, 16);
 179     if (e == p)
 180         return -1;
 181     if (*e == ':') {
 182         bus = val;
 183         p = e + 1;
 184         val = strtoul(p, &e, 16);
 185         if (e == p)
 186             return -1;
 187         if (*e == ':') {
 188             dom = bus;
 189             bus = val;
 190             p = e + 1;
 191             val = strtoul(p, &e, 16);
 192             if (e == p)
 193                 return -1;
 194         }
 195     }
 196
 197     if (dom > 0xffff || bus > 0xff || val > 0x1f)
 198         return -1;
 199
 200     slot = val;
 201
 202     if (*e)
 203         return -1;
 204
 205     /* Note: QEMU doesn't implement domains other than 0 */
 206     if (dom != 0 || pci_find_bus(bus) == NULL)
 207         return -1;
 208
 209     *domp = dom;
 210     *busp = bus;
 211     *slotp = slot;
 212     return 0;
 213 }
 214
 215 /*
 216  * Parse device bdf in device assignment command:
 217  *
 218  * -pcidevice host=bus:dev.func
 219  *
 220  * Parse <bus>:<slot>.<func> return -1 on error
 221  */
 222 int pci_parse_host_devaddr(const char *addr, int *busp,
 223                            int *slotp, int *funcp)
 224 {
 225     const char *p;
 226     char *e;
 227     int val;
 228     int bus = 0, slot = 0, func = 0;
 229
 230     p = addr;
 231     val = strtoul(p, &e, 16);
 232     if (e == p)
 233         return -1;
 234     if (*e == ':') {
 235         bus = val;
 236         p = e + 1;
 237         val = strtoul(p, &e, 16);
 238         if (e == p)
 239             return -1;
 240         if (*e == '.') {
 241             slot = val;
 242             p = e + 1;
 243             val = strtoul(p, &e, 16);
 244             if (e == p)
 245                 return -1;
 246             func = val;
 247         } else
 248             return -1;
 249     } else
 250         return -1;
 251
 252     if (bus > 0xff || slot > 0x1f || func > 0x7)
 253         return -1;
 254
 255     if (*e)
 256         return -1;
 257
 258     *busp = bus;
 259     *slotp = slot;
 260     *funcp = func;
 261     return 0;
 262 }
 263
 264 int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 265 {
 266     char devaddr[32];
 267
 268     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 269         return -1;
 270
 271     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 272 }
 273
 274 int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
 275 {
 276     char devaddr[32];
 277
 278     if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
 279         return -1;
 280
 281     if (!strcmp(devaddr, "auto")) {
 282         *domp = *busp = 0;
 283         *slotp = -1;
 284         /* want to support dom/bus auto-assign at some point */
 285         return 0;
 286     }
 287
 288     return pci_parse_devaddr(devaddr, domp, busp, slotp);
 289 }
 290
 291 /* -1 for devfn means auto assign */
 292 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
 293                                int instance_size, int devfn,
 294                                PCIConfigReadFunc *config_read,
 295                                PCIConfigWriteFunc *config_write)
 296 {
 297     PCIDevice *pci_dev;
 298
 299     if (pci_irq_index >= PCI_DEVICES_MAX)
 300         return NULL;
 301
 302     if (devfn < 0) {
 303         for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
 304             if (!bus->devices[devfn])
 305                 goto found;
 306         }
 307         return NULL;
 308     found: ;
 309     }
 310     pci_dev = qemu_mallocz(instance_size);
 311     pci_dev->bus = bus;
 312     pci_dev->devfn = devfn;
 313     pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
 314     memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
 315     pci_set_default_subsystem_id(pci_dev);
 316
 317     if (!config_read)
 318         config_read = pci_default_read_config;
 319     if (!config_write)
 320         config_write = pci_default_write_config;
 321     pci_dev->config_read = config_read;
 322     pci_dev->config_write = config_write;
 323     pci_dev->irq_index = pci_irq_index++;
 324     bus->devices[devfn] = pci_dev;
 325     pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
 326     return pci_dev;
 327 }
 328
 329 static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
 330 {
 331     return addr + pci_mem_base;
 332 }
 333
 334 static void pci_unregister_io_regions(PCIDevice *pci_dev)
 335 {
 336     PCIIORegion *r;
 337     int i;
 338
 339     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 340         r = &pci_dev->io_regions[i];
 341         if (!r->size || r->addr == -1)
 342             continue;
 343         if (r->type == PCI_ADDRESS_SPACE_IO) {
 344             isa_unassign_ioport(r->addr, r->size);
 345         } else {
 346             cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 347                                                      r->size,
 348                                                      IO_MEM_UNASSIGNED);
 349         }
 350     }
 351 }
 352
 353 int pci_unregister_device(PCIDevice *pci_dev)
 354 {
 355     int ret = 0;
 356
 357     if (pci_dev->unregister)
 358         ret = pci_dev->unregister(pci_dev);
 359     if (ret)
 360         return ret;
 361
 362     pci_unregister_io_regions(pci_dev);
 363
 364     qemu_free_irqs(pci_dev->irq);
 365     pci_irq_index--;
 366     pci_dev->bus->devices[pci_dev->devfn] = NULL;
 367     qemu_free(pci_dev);
 368     return 0;
 369 }
 370
 371 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
 372                             uint32_t size, int type,
 373                             PCIMapIORegionFunc *map_func)
 374 {
 375     PCIIORegion *r;
 376     uint32_t addr;
 377
 378     if ((unsigned int)region_num >= PCI_NUM_REGIONS)
 379         return;
 380
 381     if (size & (size-1)) {
 382         fprintf(stderr, "ERROR: PCI region size must be pow2 "
 383                     "type=0x%x, size=0x%x\n", type, size);
 384         exit(1);
 385     }
 386
 387     r = &pci_dev->io_regions[region_num];
 388     r->addr = -1;
 389     r->size = size;
 390     r->type = type;
 391     r->map_func = map_func;
 392     if (region_num == PCI_ROM_SLOT) {
 393         addr = 0x30;
 394     } else {
 395         addr = 0x10 + region_num * 4;
 396     }
 397     *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
 398 }
 399
 400 static void pci_update_mappings(PCIDevice *d)
 401 {
 402     PCIIORegion *r;
 403     int cmd, i;
 404     uint32_t last_addr, new_addr, config_ofs;
 405
 406     cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
 407     for(i = 0; i < PCI_NUM_REGIONS; i++) {
 408         r = &d->io_regions[i];
 409         if (i == PCI_ROM_SLOT) {
 410             config_ofs = 0x30;
 411         } else {
 412             config_ofs = 0x10 + i * 4;
 413         }
 414         if (r->size != 0) {
 415             if (r->type & PCI_ADDRESS_SPACE_IO) {
 416                 if (cmd & PCI_COMMAND_IO) {
 417                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 418                                                          config_ofs));
 419                     new_addr = new_addr & ~(r->size - 1);
 420                     last_addr = new_addr + r->size - 1;
 421                     /* NOTE: we have only 64K ioports on PC */
 422                     if (last_addr <= new_addr || new_addr == 0 ||
 423                         last_addr >= 0x10000) {
 424                         new_addr = -1;
 425                     }
 426                 } else {
 427                     new_addr = -1;
 428                 }
 429             } else {
 430                 if (cmd & PCI_COMMAND_MEMORY) {
 431                     new_addr = le32_to_cpu(*(uint32_t *)(d->config +
 432                                                          config_ofs));
 433                     /* the ROM slot has a specific enable bit */
 434                     if (i == PCI_ROM_SLOT && !(new_addr & 1))
 435                         goto no_mem_map;
 436                     new_addr = new_addr & ~(r->size - 1);
 437                     last_addr = new_addr + r->size - 1;
 438                     /* NOTE: we do not support wrapping */
 439                     /* XXX: as we cannot support really dynamic
 440                        mappings, we handle specific values as invalid
 441                        mappings. */
 442                     if (last_addr <= new_addr || new_addr == 0 ||
 443                         last_addr == -1) {
 444                         new_addr = -1;
 445                     }
 446                 } else {
 447                 no_mem_map:
 448                     new_addr = -1;
 449                 }
 450             }
 451             /* now do the real mapping */
 452             if (new_addr != r->addr) {
 453                 if (r->addr != -1) {
 454                     if (r->type & PCI_ADDRESS_SPACE_IO) {
 455                         int class;
 456                         /* NOTE: specific hack for IDE in PC case:
 457                            only one byte must be mapped. */
 458                         class = d->config[0x0a] | (d->config[0x0b] << 8);
 459                         if (class == 0x0101 && r->size == 4) {
 460                             isa_unassign_ioport(r->addr + 2, 1);
 461                         } else {
 462                             isa_unassign_ioport(r->addr, r->size);
 463                         }
 464                     } else {
 465                         cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
 466                                                      r->size,
 467                                                      IO_MEM_UNASSIGNED);
 468                         qemu_unregister_coalesced_mmio(r->addr, r->size);
 469                     }
 470                 }
 471                 r->addr = new_addr;
 472                 if (r->addr != -1) {
 473                     r->map_func(d, i, r->addr, r->size, r->type);
 474                 }
 475             }
 476         }
 477     }
 478 }
 479
 480 static uint32_t pci_read_config(PCIDevice *d,
 481                                 uint32_t address, int len)
 482 {
 483     uint32_t val;
 484
 485     switch(len) {
 486     default:
 487     case 4:
 488         if (address <= 0xfc) {
 489             val = le32_to_cpu(*(uint32_t *)(d->config + address));
 490             break;
 491         }
 492         /* fall through */
 493     case 2:
 494         if (address <= 0xfe) {
 495             val = le16_to_cpu(*(uint16_t *)(d->config + address));
 496             break;
 497         }
 498         /* fall through */
 499     case 1:
 500         val = d->config[address];
 501         break;
 502     }
 503     return val;
 504 }
 505
 506 static void pci_write_config(PCIDevice *pci_dev,
 507                              uint32_t address, uint32_t val, int len)
 508 {
 509     int i;
 510     for (i = 0; i < len; i++) {
 511         pci_dev->config[address + i] = val & 0xff;
 512         val >>= 8;
 513     }
 514 }
 515
 516 int pci_access_cap_config(PCIDevice *pci_dev, uint32_t address, int len)
 517 {
 518     if (pci_dev->cap.supported && address >= pci_dev->cap.start &&
 519             (address + len) < pci_dev->cap.start + pci_dev->cap.length)
 520         return 1;
 521     return 0;
 522 }
 523
 524 uint32_t pci_default_cap_read_config(PCIDevice *pci_dev,
 525                                      uint32_t address, int len)
 526 {
 527     return pci_read_config(pci_dev, address, len);
 528 }
 529
 530 void pci_default_cap_write_config(PCIDevice *pci_dev,
 531                                   uint32_t address, uint32_t val, int len)
 532 {
 533     pci_write_config(pci_dev, address, val, len);
 534 }
 535
 536 uint32_t pci_default_read_config(PCIDevice *d,
 537                                  uint32_t address, int len)
 538 {
 539     if (pci_access_cap_config(d, address, len))
 540         return d->cap.config_read(d, address, len);
 541
 542     return pci_read_config(d, address, len);
 543 }
 544
 545 void pci_default_write_config(PCIDevice *d,
 546                               uint32_t address, uint32_t val, int len)
 547 {
 548     int can_write, i;
 549     uint32_t end, addr;
 550
 551     if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
 552                      (address >= 0x30 && address < 0x34))) {
 553         PCIIORegion *r;
 554         int reg;
 555
 556         if ( address >= 0x30 ) {
 557             reg = PCI_ROM_SLOT;
 558         }else{
 559             reg = (address - 0x10) >> 2;
 560         }
 561         r = &d->io_regions[reg];
 562         if (r->size == 0)
 563             goto default_config;
 564         /* compute the stored value */
 565         if (reg == PCI_ROM_SLOT) {
 566             /* keep ROM enable bit */
 567             val &= (~(r->size - 1)) | 1;
 568         } else {
 569             val &= ~(r->size - 1);
 570             val |= r->type;
 571         }
 572         *(uint32_t *)(d->config + address) = cpu_to_le32(val);
 573         pci_update_mappings(d);
 574         return;
 575     }
 576  default_config:
 577     if (pci_access_cap_config(d, address, len)) {
 578         d->cap.config_write(d, address, val, len);
 579         return;
 580     }
 581
 582     /* not efficient, but simple */
 583     addr = address;
 584     for(i = 0; i < len; i++) {
 585         /* default read/write accesses */
 586         switch(d->config[0x0e]) {
 587         case 0x00:
 588         case 0x80:
 589             switch(addr) {
 590             case 0x00:
 591             case 0x01:
 592             case 0x02:
 593             case 0x03:
 594             case 0x08:
 595             case 0x09:
 596             case 0x0a:
 597             case 0x0b:
 598             case 0x0e:
 599             case 0x10 ... 0x27: /* base */
 600             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 601             case 0x30 ... 0x33: /* rom */
 602             case 0x3d:
 603                 can_write = 0;
 604                 break;
 605             default:
 606                 can_write = 1;
 607                 break;
 608             }
 609             break;
 610         default:
 611         case 0x01:
 612             switch(addr) {
 613             case 0x00:
 614             case 0x01:
 615             case 0x02:
 616             case 0x03:
 617             case 0x08:
 618             case 0x09:
 619             case 0x0a:
 620             case 0x0b:
 621             case 0x0e:
 622             case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
 623             case 0x38 ... 0x3b: /* rom */
 624             case 0x3d:
 625                 can_write = 0;
 626                 break;
 627             default:
 628                 can_write = 1;
 629                 break;
 630             }
 631             break;
 632         }
 633         if (can_write) {
 634             /* Mask out writes to reserved bits in registers */
 635             switch (addr) {
 636             case 0x05:
 637                 val &= ~PCI_COMMAND_RESERVED_MASK_HI;
 638                 break;
 639             case 0x06:
 640                 val &= ~PCI_STATUS_RESERVED_MASK_LO;
 641                 break;
 642             case 0x07:
 643                 val &= ~PCI_STATUS_RESERVED_MASK_HI;
 644                 break;
 645             }
 646             d->config[addr] = val;
 647         }
 648         if (++addr > 0xff)
 649                 break;
 650         val >>= 8;
 651     }
 652
 653 #ifdef USE_KVM_DEVICE_ASSIGNMENT
 654     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel() &&
 655         address >= PIIX_CONFIG_IRQ_ROUTE &&
 656         address < PIIX_CONFIG_IRQ_ROUTE + 4)
 657         assigned_dev_update_irqs();
 658 #endif /* USE_KVM_DEVICE_ASSIGNMENT */
 659
 660     end = address + len;
 661     if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
 662         /* if the command register is modified, we must modify the mappings */
 663         pci_update_mappings(d);
 664     }
 665 }
 666
 667 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
 668 {
 669     PCIBus *s = opaque;
 670     PCIDevice *pci_dev;
 671     int config_addr, bus_num;
 672
 673 #if defined(DEBUG_PCI) && 0
 674     printf("pci_data_write: addr=%08x val=%08x len=%d\n",
 675            addr, val, len);
 676 #endif
 677     bus_num = (addr >> 16) & 0xff;
 678     while (s && s->bus_num != bus_num)
 679         s = s->next;
 680     if (!s)
 681         return;
 682     pci_dev = s->devices[(addr >> 8) & 0xff];
 683     if (!pci_dev)
 684         return;
 685     config_addr = addr & 0xff;
 686 #if defined(DEBUG_PCI)
 687     printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
 688            pci_dev->name, config_addr, val, len);
 689 #endif
 690     pci_dev->config_write(pci_dev, config_addr, val, len);
 691 }
 692
 693 uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
 694 {
 695     PCIBus *s = opaque;
 696     PCIDevice *pci_dev;
 697     int config_addr, bus_num;
 698     uint32_t val;
 699
 700     bus_num = (addr >> 16) & 0xff;
 701     while (s && s->bus_num != bus_num)
 702         s= s->next;
 703     if (!s)
 704         goto fail;
 705     pci_dev = s->devices[(addr >> 8) & 0xff];
 706     if (!pci_dev) {
 707     fail:
 708         switch(len) {
 709         case 1:
 710             val = 0xff;
 711             break;
 712         case 2:
 713             val = 0xffff;
 714             break;
 715         default:
 716         case 4:
 717             val = 0xffffffff;
 718             break;
 719         }
 720         goto the_end;
 721     }
 722     config_addr = addr & 0xff;
 723     val = pci_dev->config_read(pci_dev, config_addr, len);
 724 #if defined(DEBUG_PCI)
 725     printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
 726            pci_dev->name, config_addr, val, len);
 727 #endif
 728  the_end:
 729 #if defined(DEBUG_PCI) && 0
 730     printf("pci_data_read: addr=%08x val=%08x len=%d\n",
 731            addr, val, len);
 732 #endif
 733     return val;
 734 }
 735
 736 /***********************************************************/
 737 /* generic PCI irq support */
 738
 739 /* 0 <= irq_num <= 3. level must be 0 or 1 */
 740 static void pci_set_irq(void *opaque, int irq_num, int level)
 741 {
 742     PCIDevice *pci_dev = (PCIDevice *)opaque;
 743     PCIBus *bus;
 744     int change;
 745
 746     change = level - pci_dev->irq_state[irq_num];
 747     if (!change)
 748         return;
 749
 750     pci_dev->irq_state[irq_num] = level;
 751
 752 #if defined(TARGET_IA64)
 753     ioapic_set_irq(pci_dev, irq_num, level);
 754 #endif
 755
 756     for (;;) {
 757         bus = pci_dev->bus;
 758         irq_num = bus->map_irq(pci_dev, irq_num);
 759         if (bus->set_irq)
 760             break;
 761         pci_dev = bus->parent_dev;
 762     }
 763     bus->irq_count[irq_num] += change;
 764     bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
 765 }
 766
 767 int pci_map_irq(PCIDevice *pci_dev, int pin)
 768 {
 769     return pci_dev->bus->map_irq(pci_dev, pin);
 770 }
 771
 772 /***********************************************************/
 773 /* monitor info on PCI */
 774
 775 typedef struct {
 776     uint16_t class;
 777     const char *desc;
 778 } pci_class_desc;
 779
 780 static const pci_class_desc pci_class_descriptions[] =
 781 {
 782     { 0x0100, "SCSI controller"},
 783     { 0x0101, "IDE controller"},
 784     { 0x0102, "Floppy controller"},
 785     { 0x0103, "IPI controller"},
 786     { 0x0104, "RAID controller"},
 787     { 0x0106, "SATA controller"},
 788     { 0x0107, "SAS controller"},
 789     { 0x0180, "Storage controller"},
 790     { 0x0200, "Ethernet controller"},
 791     { 0x0201, "Token Ring controller"},
 792     { 0x0202, "FDDI controller"},
 793     { 0x0203, "ATM controller"},
 794     { 0x0280, "Network controller"},
 795     { 0x0300, "VGA controller"},
 796     { 0x0301, "XGA controller"},
 797     { 0x0302, "3D controller"},
 798     { 0x0380, "Display controller"},
 799     { 0x0400, "Video controller"},
 800     { 0x0401, "Audio controller"},
 801     { 0x0402, "Phone"},
 802     { 0x0480, "Multimedia controller"},
 803     { 0x0500, "RAM controller"},
 804     { 0x0501, "Flash controller"},
 805     { 0x0580, "Memory controller"},
 806     { 0x0600, "Host bridge"},
 807     { 0x0601, "ISA bridge"},
 808     { 0x0602, "EISA bridge"},
 809     { 0x0603, "MC bridge"},
 810     { 0x0604, "PCI bridge"},
 811     { 0x0605, "PCMCIA bridge"},
 812     { 0x0606, "NUBUS bridge"},
 813     { 0x0607, "CARDBUS bridge"},
 814     { 0x0608, "RACEWAY bridge"},
 815     { 0x0680, "Bridge"},
 816     { 0x0c03, "USB controller"},
 817     { 0, NULL}
 818 };
 819
 820 static void pci_info_device(PCIDevice *d)
 821 {
 822     Monitor *mon = cur_mon;
 823     int i, class;
 824     PCIIORegion *r;
 825     const pci_class_desc *desc;
 826
 827     monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
 828                    d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
 829     class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
 830     monitor_printf(mon, "    ");
 831     desc = pci_class_descriptions;
 832     while (desc->desc && class != desc->class)
 833         desc++;
 834     if (desc->desc) {
 835         monitor_printf(mon, "%s", desc->desc);
 836     } else {
 837         monitor_printf(mon, "Class %04x", class);
 838     }
 839     monitor_printf(mon, ": PCI device %04x:%04x\n",
 840            le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
 841            le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
 842
 843     if (d->config[PCI_INTERRUPT_PIN] != 0) {
 844         monitor_printf(mon, "      IRQ %d.\n",
 845                        d->config[PCI_INTERRUPT_LINE]);
 846     }
 847     if (class == 0x0604) {
 848         monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
 849     }
 850     for(i = 0;i < PCI_NUM_REGIONS; i++) {
 851         r = &d->io_regions[i];
 852         if (r->size != 0) {
 853             monitor_printf(mon, "      BAR%d: ", i);
 854             if (r->type & PCI_ADDRESS_SPACE_IO) {
 855                 monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
 856                                r->addr, r->addr + r->size - 1);
 857             } else {
 858                 monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
 859                                r->addr, r->addr + r->size - 1);
 860             }
 861         }
 862     }
 863     if (class == 0x0604 && d->config[0x19] != 0) {
 864         pci_for_each_device(d->config[0x19], pci_info_device);
 865     }
 866 }
 867
 868 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
 869 {
 870     PCIBus *bus = first_bus;
 871     PCIDevice *d;
 872     int devfn;
 873
 874     while (bus && bus->bus_num != bus_num)
 875         bus = bus->next;
 876     if (bus) {
 877         for(devfn = 0; devfn < 256; devfn++) {
 878             d = bus->devices[devfn];
 879             if (d)
 880                 fn(d);
 881         }
 882     }
 883 }
 884
 885 void pci_info(Monitor *mon)
 886 {
 887     pci_for_each_device(0, pci_info_device);
 888 }
 889
 890 static const char * const pci_nic_models[] = {
 891     "ne2k_pci",
 892     "i82551",
 893     "i82557b",
 894     "i82559er",
 895     "rtl8139",
 896     "e1000",
 897     "pcnet",
 898     "virtio",
 899     NULL
 900 };
 901
 902 typedef PCIDevice *(*PCINICInitFn)(PCIBus *, NICInfo *, int);
 903
 904 static PCINICInitFn pci_nic_init_fns[] = {
 905     pci_ne2000_init,
 906     pci_i82551_init,
 907     pci_i82557b_init,
 908     pci_i82559er_init,
 909     pci_rtl8139_init,
 910     pci_e1000_init,
 911     pci_pcnet_init,
 912     virtio_net_init,
 913     NULL
 914 };
 915
 916 /* Initialize a PCI NIC.  */
 917 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
 918                   const char *default_model)
 919 {
 920     PCIDevice *pci_dev;
 921     int i;
 922
 923     qemu_check_nic_model_list(nd, pci_nic_models, default_model);
 924
 925     for (i = 0; pci_nic_models[i]; i++)
 926         if (strcmp(nd->model, pci_nic_models[i]) == 0) {
 927             pci_dev = pci_nic_init_fns[i](bus, nd, devfn);
 928             if (pci_dev)
 929                 nd->private = pci_dev;
 930             return pci_dev;
 931         }
 932
 933     return NULL;
 934 }
 935
 936 typedef struct {
 937     PCIDevice dev;
 938     PCIBus *bus;
 939 } PCIBridge;
 940
 941 static void pci_bridge_write_config(PCIDevice *d,
 942                              uint32_t address, uint32_t val, int len)
 943 {
 944     PCIBridge *s = (PCIBridge *)d;
 945
 946     if (address == 0x19 || (address == 0x18 && len > 1)) {
 947         if (address == 0x19)
 948             s->bus->bus_num = val & 0xff;
 949         else
 950             s->bus->bus_num = (val >> 8) & 0xff;
 951 #if defined(DEBUG_PCI)
 952         printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
 953 #endif
 954     }
 955     pci_default_write_config(d, address, val, len);
 956 }
 957
 958 PCIBus *pci_find_bus(int bus_num)
 959 {
 960     PCIBus *bus = first_bus;
 961
 962     while (bus && bus->bus_num != bus_num)
 963         bus = bus->next;
 964
 965     return bus;
 966 }
 967
 968 PCIDevice *pci_find_device(int bus_num, int slot, int function)
 969 {
 970     PCIBus *bus = pci_find_bus(bus_num);
 971
 972     if (!bus)
 973         return NULL;
 974
 975     return bus->devices[PCI_DEVFN(slot, function)];
 976 }
 977
 978 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
 979                         pci_map_irq_fn map_irq, const char *name)
 980 {
 981     PCIBridge *s;
 982     s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
 983                                          devfn, NULL, pci_bridge_write_config);
 984
 985     pci_config_set_vendor_id(s->dev.config, vid);
 986     pci_config_set_device_id(s->dev.config, did);
 987
 988     s->dev.config[0x04] = 0x06; // command = bus master, pci mem
 989     s->dev.config[0x05] = 0x00;
 990     s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 991     s->dev.config[0x07] = 0x00; // status = fast devsel
 992     s->dev.config[0x08] = 0x00; // revision
 993     s->dev.config[0x09] = 0x00; // programming i/f
 994     pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
 995     s->dev.config[0x0D] = 0x10; // latency_timer
 996     s->dev.config[0x0E] = 0x81; // header_type
 997     s->dev.config[0x1E] = 0xa0; // secondary status
 998
 999     s->bus = pci_register_secondary_bus(&s->dev, map_irq);
1000     return s->bus;
1001 }
1002
1003 int pci_enable_capability_support(PCIDevice *pci_dev,
1004                                   uint32_t config_start,
1005                                   PCICapConfigReadFunc *config_read,
1006                                   PCICapConfigWriteFunc *config_write,
1007                                   PCICapConfigInitFunc *config_init)
1008 {
1009     if (!pci_dev)
1010         return -ENODEV;
1011
1012     pci_dev->config[0x06] |= 0x10; // status = capabilities
1013
1014     if (config_start == 0)
1015         pci_dev->cap.start = PCI_CAPABILITY_CONFIG_DEFAULT_START_ADDR;
1016     else if (config_start >= 0x40 && config_start < 0xff)
1017         pci_dev->cap.start = config_start;
1018     else
1019         return -EINVAL;
1020
1021     if (config_read)
1022         pci_dev->cap.config_read = config_read;
1023     else
1024         pci_dev->cap.config_read = pci_default_cap_read_config;
1025     if (config_write)
1026         pci_dev->cap.config_write = config_write;
1027     else
1028         pci_dev->cap.config_write = pci_default_cap_write_config;
1029     pci_dev->cap.supported = 1;
1030     pci_dev->config[PCI_CAPABILITY_LIST] = pci_dev->cap.start;
1031     return config_init(pci_dev);
1032 }