1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2006 Daniel Ankers
11 * Copyright © 2008-2009 Rafaël Carré
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
36 #include "pl180.h" /* SD controller */
37 #include "pl081.h" /* DMA controller */
38 #include "dma-target.h" /* DMA request lines */
39 #include "clock-target.h"
41 #ifdef HAVE_BUTTON_LIGHT
42 #include "backlight-target.h"
45 #include "ata_idle_notify.h"
53 #define VERIFY_WRITE 1
56 #define MCI_NO_RESP (0<<0)
57 #define MCI_RESP (1<<0)
58 #define MCI_LONG_RESP (1<<1)
60 /* ARM PL180 registers */
61 #define MCI_POWER(i) (*(volatile unsigned char *) (pl180_base[i]+0x00))
62 #define MCI_CLOCK(i) (*(volatile unsigned long *) (pl180_base[i]+0x04))
63 #define MCI_ARGUMENT(i) (*(volatile unsigned long *) (pl180_base[i]+0x08))
64 #define MCI_COMMAND(i) (*(volatile unsigned long *) (pl180_base[i]+0x0C))
65 #define MCI_RESPCMD(i) (*(volatile unsigned long *) (pl180_base[i]+0x10))
66 #define MCI_RESP0(i) (*(volatile unsigned long *) (pl180_base[i]+0x14))
67 #define MCI_RESP1(i) (*(volatile unsigned long *) (pl180_base[i]+0x18))
68 #define MCI_RESP2(i) (*(volatile unsigned long *) (pl180_base[i]+0x1C))
69 #define MCI_RESP3(i) (*(volatile unsigned long *) (pl180_base[i]+0x20))
70 #define MCI_DATA_TIMER(i) (*(volatile unsigned long *) (pl180_base[i]+0x24))
71 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
72 #define MCI_DATA_CTRL(i) (*(volatile unsigned char *) (pl180_base[i]+0x2C))
73 #define MCI_DATA_CNT(i) (*(volatile unsigned short*) (pl180_base[i]+0x30))
74 #define MCI_STATUS(i) (*(volatile unsigned long *) (pl180_base[i]+0x34))
75 #define MCI_CLEAR(i) (*(volatile unsigned long *) (pl180_base[i]+0x38))
76 #define MCI_MASK0(i) (*(volatile unsigned long *) (pl180_base[i]+0x3C))
77 #define MCI_MASK1(i) (*(volatile unsigned long *) (pl180_base[i]+0x40))
78 #define MCI_SELECT(i) (*(volatile unsigned long *) (pl180_base[i]+0x44))
79 #define MCI_FIFO_CNT(i) (*(volatile unsigned long *) (pl180_base[i]+0x48))
81 #define MCI_DATA_ERROR \
88 #define MCI_RESPONSE_ERROR \
92 #define MCI_FIFO(i) ((unsigned long *) (pl180_base[i]+0x80))
94 #define INTERNAL_AS3525 0 /* embedded SD card */
95 #define SD_SLOT_AS3525 1 /* SD slot if present */
97 static const int pl180_base
[NUM_DRIVES
] = {
99 #ifdef HAVE_MULTIDRIVE
104 static int sd_wait_for_tran_state(const int drive
);
105 static int sd_select_bank(signed char bank
);
106 static int sd_init_card(const int drive
);
107 static void init_pl180_controller(const int drive
);
109 #define BLOCKS_PER_BANK 0x7a7800u
111 static tCardInfo card_info
[NUM_DRIVES
];
113 /* maximum timeouts recommanded in the SD Specification v2.00 */
114 #define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
115 #define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
117 /* for compatibility */
118 static long last_disk_activity
= -1;
120 #define MIN_YIELD_PERIOD 5 /* ticks */
121 static long next_yield
= 0;
123 static long sd_stack
[(DEFAULT_STACK_SIZE
*2 + 0x200)/sizeof(long)];
124 static const char sd_thread_name
[] = "ata/sd";
125 static struct mutex sd_mtx
;
126 static struct event_queue sd_queue
;
127 bool sd_enabled
= false;
129 #if defined(HAVE_MULTIDRIVE)
130 static bool hs_card
= false;
131 #define EXT_SD_BITS (1<<2)
134 static struct wakeup transfer_completion_signal
;
135 static volatile unsigned int transfer_error
[NUM_VOLUMES
];
136 #define PL180_MAX_TRANSFER_ERRORS 10
138 #define UNALIGNED_NUM_SECTORS 10
139 static unsigned char aligned_buffer
[UNALIGNED_NUM_SECTORS
* SD_BLOCK_SIZE
] __attribute__((aligned(32))); /* align on cache line size */
140 static unsigned char *uncached_buffer
= AS3525_UNCACHED_ADDR(&aligned_buffer
[0]);
143 static inline void mci_delay(void) { udelay(1000) ; }
146 static inline bool card_detect_target(void)
148 #if defined(HAVE_MULTIDRIVE)
149 return !(GPIOA_PIN(2));
157 static int sd1_oneshot_callback(struct timeout
*tmo
)
161 /* This is called only if the state was stable for 300ms - check state
162 * and post appropriate event. */
163 if (card_detect_target())
165 queue_broadcast(SYS_HOTSWAP_INSERTED
, 0);
168 queue_broadcast(SYS_HOTSWAP_EXTRACTED
, 0);
173 void sd_gpioa_isr(void)
175 static struct timeout sd1_oneshot
;
176 if (GPIOA_MIS
& EXT_SD_BITS
)
177 timeout_register(&sd1_oneshot
, sd1_oneshot_callback
, (3*HZ
/10), 0);
178 /* acknowledge interrupt */
179 GPIOA_IC
= EXT_SD_BITS
;
181 #endif /* HAVE_HOTSWAP */
185 const int status
= MCI_STATUS(INTERNAL_AS3525
);
187 transfer_error
[INTERNAL_AS3525
] = status
& MCI_DATA_ERROR
;
189 wakeup_signal(&transfer_completion_signal
);
190 MCI_CLEAR(INTERNAL_AS3525
) = status
;
193 #ifdef HAVE_MULTIDRIVE
196 const int status
= MCI_STATUS(SD_SLOT_AS3525
);
198 transfer_error
[SD_SLOT_AS3525
] = status
& MCI_DATA_ERROR
;
200 wakeup_signal(&transfer_completion_signal
);
201 MCI_CLEAR(SD_SLOT_AS3525
) = status
;
205 static bool send_cmd(const int drive
, const int cmd
, const int arg
,
206 const int flags
, long *response
)
210 unsigned cmd_retries
= 6;
213 /* Clear old status flags */
214 MCI_CLEAR(drive
) = 0x7ff;
216 /* Load command argument or clear if none */
217 MCI_ARGUMENT(drive
) = arg
;
219 /* Construct MCI_COMMAND & enable CPSM */
222 /* b6 */| ((flags
& (MCI_RESP
|MCI_LONG_RESP
)) ? MCI_COMMAND_RESPONSE
: 0)
223 /* b7 */| ((flags
& MCI_LONG_RESP
) ? MCI_COMMAND_LONG_RESPONSE
: 0)
224 /* b8 | MCI_COMMAND_INTERRUPT */
225 /* b9 | MCI_COMMAND_PENDING */ /*Only used with stream data transfer*/
226 /* b10*/| MCI_COMMAND_ENABLE
; /* Enables CPSM */
228 /* Wait while cmd completes then disable CPSM */
229 while(MCI_STATUS(drive
) & MCI_CMD_ACTIVE
);
230 MCI_COMMAND(drive
) = 0;
232 status
= MCI_STATUS(drive
);
234 /* Handle command responses */
235 if(flags
& MCI_RESP
) /* CMD expects response */
237 response
[0] = MCI_RESP0(drive
); /* Always prepare short response */
239 if(status
& MCI_RESPONSE_ERROR
) /* timeout or crc failure */
242 if(status
& MCI_CMD_RESP_END
) /* Response passed CRC check */
244 if(flags
& MCI_LONG_RESP
)
245 { /* response[0] has already been read */
246 response
[1] = MCI_RESP1(drive
);
247 response
[2] = MCI_RESP2(drive
);
248 response
[3] = MCI_RESP3(drive
);
253 else if(status
& MCI_CMD_SENT
) /* CMD sent, no response required */
260 #define MCI_FULLSPEED (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS) /* MCLK */
261 #define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */
262 #define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */
263 #define MCI_IDENTSPEED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV) /* IDENT */
265 static int sd_init_card(const int drive
)
267 unsigned long response
;
271 /* MCLCK on and set to 400kHz ident frequency */
272 MCI_CLOCK(drive
) = MCI_IDENTSPEED
;
274 /* 100 - 400kHz clock required for Identification Mode */
275 /* Start of Card Identification Mode ************************************/
278 if(!send_cmd(drive
, SD_GO_IDLE_STATE
, 0, MCI_NO_RESP
, NULL
))
282 /* CMD8 Check for v2 sd card. Must be sent before using ACMD41
283 Non v2 cards will not respond to this command*/
284 if(send_cmd(drive
, SD_SEND_IF_COND
, 0x1AA, MCI_RESP
, &response
))
285 if((response
& 0xFFF) == 0x1AA)
288 /* timeout for initialization is 1sec, from SD Specification 2.00 */
289 init_timeout
= current_tick
+ HZ
;
292 /* this timeout is the only valid error for this loop*/
293 if(TIME_AFTER(current_tick
, init_timeout
))
297 send_cmd(drive
, SD_APP_CMD
, 0, MCI_RESP
, &response
);
299 /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
300 send_cmd(drive
, SD_APP_OP_COND
, (0x00FF8000 | (sd_v2
? 1<<30 : 0)),
301 MCI_RESP
, &card_info
[drive
].ocr
);
303 } while(!(card_info
[drive
].ocr
& (1<<31)));
306 if(!send_cmd(drive
, SD_ALL_SEND_CID
, 0, MCI_RESP
|MCI_LONG_RESP
,
307 card_info
[drive
].cid
))
311 if(!send_cmd(drive
, SD_SEND_RELATIVE_ADDR
, 0, MCI_RESP
,
312 &card_info
[drive
].rca
))
315 /* End of Card Identification Mode ************************************/
317 #ifdef HAVE_MULTIDRIVE /* The internal SDs are v1 */
319 /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
322 /* CMD7 w/rca: Select card to put it in TRAN state */
323 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_RESP
, &response
))
326 if(sd_wait_for_tran_state(drive
))
329 if(!send_cmd(drive
, SD_SWITCH_FUNC
, 0x80fffff1, MCI_NO_RESP
, NULL
))
333 /* go back to STBY state so we can read csd */
334 /* CMD7 w/rca=0: Deselect card to put it in STBY state */
335 if(!send_cmd(drive
, SD_DESELECT_CARD
, 0, MCI_NO_RESP
, NULL
))
339 #endif /* HAVE_MULTIDRIVE */
342 if(!send_cmd(drive
, SD_SEND_CSD
, card_info
[drive
].rca
,
343 MCI_RESP
|MCI_LONG_RESP
, card_info
[drive
].csd
))
346 sd_parse_csd(&card_info
[drive
]);
348 #if defined(HAVE_MULTIDRIVE)
349 hs_card
= (card_info
[drive
].speed
== 50000000);
352 /* Boost MCICLK to operating speed */
353 if(drive
== INTERNAL_AS3525
)
354 MCI_CLOCK(drive
) = MCI_HALFSPEED
; /* MCICLK = IDE_CLK/2 = 25 MHz */
355 #if defined(HAVE_MULTIDRIVE)
357 /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
358 MCI_CLOCK(drive
) = (hs_card
? MCI_HALFSPEED
: MCI_QUARTERSPEED
);
361 /* CMD7 w/rca: Select card to put it in TRAN state */
362 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_RESP
, &response
))
365 /* Switch to to 4 bit widebus mode */
366 if(sd_wait_for_tran_state(drive
) < 0)
368 /* CMD55 */ /* Response is requested due to timing issue */
369 if(!send_cmd(drive
, SD_APP_CMD
, card_info
[drive
].rca
, MCI_RESP
, &response
))
372 if(!send_cmd(drive
, SD_SET_CLR_CARD_DETECT
, 0, MCI_RESP
, &response
))
374 /* CMD55 */ /* Response is requested due to timing issue */
375 if(!send_cmd(drive
, SD_APP_CMD
, card_info
[drive
].rca
, MCI_RESP
, &response
))
378 if(!send_cmd(drive
, SD_SET_BUS_WIDTH
, 2, MCI_RESP
, &response
))
380 /* Now that card is widebus make controller aware */
381 MCI_CLOCK(drive
) |= MCI_CLOCK_WIDEBUS
;
384 * enable bank switching
385 * without issuing this command, we only have access to 1/4 of the blocks
386 * of the first bank (0x1E9E00 blocks, which is the size reported in the
389 if(drive
== INTERNAL_AS3525
)
391 const int ret
= sd_select_bank(-1);
395 /* CMD7 w/rca = 0: Unselect card to put it in STBY state */
396 if(!send_cmd(drive
, SD_SELECT_CARD
, 0, MCI_NO_RESP
, NULL
))
400 /* CMD9 send CSD again, so we got the correct number of blocks */
401 if(!send_cmd(drive
, SD_SEND_CSD
, card_info
[drive
].rca
,
402 MCI_RESP
|MCI_LONG_RESP
, card_info
[drive
].csd
))
405 sd_parse_csd(&card_info
[drive
]);
406 /* The OF is stored in the first blocks */
407 card_info
[INTERNAL_AS3525
].numblocks
-= AMS_OF_SIZE
;
409 /* CMD7 w/rca: Select card to put it in TRAN state */
410 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_RESP
, &response
))
414 card_info
[drive
].initialized
= 1;
419 static void sd_thread(void) __attribute__((noreturn
));
420 static void sd_thread(void)
422 struct queue_event ev
;
423 bool idle_notified
= false;
427 queue_wait_w_tmo(&sd_queue
, &ev
, HZ
);
432 case SYS_HOTSWAP_INSERTED
:
433 case SYS_HOTSWAP_EXTRACTED
:
435 int microsd_init
= 1;
436 fat_lock(); /* lock-out FAT activity first -
437 prevent deadlocking via disk_mount that
438 would cause a reverse-order attempt with
440 mutex_lock(&sd_mtx
); /* lock-out card activity - direct calls
441 into driver that bypass the fat cache */
443 /* We now have exclusive control of fat cache and ata */
445 disk_unmount(SD_SLOT_AS3525
); /* release "by force", ensure file
446 descriptors aren't leaked and any busy
447 ones are invalid if mounting */
449 /* Force card init for new card, re-init for re-inserted one or
450 * clear if the last attempt to init failed with an error. */
451 card_info
[SD_SLOT_AS3525
].initialized
= 0;
453 if (ev
.id
== SYS_HOTSWAP_INSERTED
)
456 init_pl180_controller(SD_SLOT_AS3525
);
457 microsd_init
= sd_init_card(SD_SLOT_AS3525
);
458 if (microsd_init
< 0) /* initialisation failed */
459 panicf("microSD init failed : %d", microsd_init
);
461 microsd_init
= disk_mount(SD_SLOT_AS3525
); /* 0 if fail */
465 * Mount succeeded, or this was an EXTRACTED event,
466 * in both cases notify the system about the changed filesystems
469 queue_broadcast(SYS_FS_CHANGED
, 0);
471 /* Access is now safe */
472 mutex_unlock(&sd_mtx
);
479 if (TIME_BEFORE(current_tick
, last_disk_activity
+(3*HZ
)))
481 idle_notified
= false;
485 /* never let a timer wrap confuse us */
486 next_yield
= current_tick
;
490 call_storage_idle_notifys(false);
491 idle_notified
= true;
496 case SYS_USB_CONNECTED
:
497 usb_acknowledge(SYS_USB_CONNECTED_ACK
);
498 /* Wait until the USB cable is extracted again */
499 usb_wait_for_disconnect(&sd_queue
);
502 case SYS_USB_DISCONNECTED
:
503 usb_acknowledge(SYS_USB_DISCONNECTED_ACK
);
509 static void init_pl180_controller(const int drive
)
511 MCI_COMMAND(drive
) = MCI_DATA_CTRL(drive
) = 0;
512 MCI_CLEAR(drive
) = 0x7ff;
514 MCI_MASK0(drive
) = MCI_DATA_ERROR
| MCI_DATA_END
;
515 MCI_MASK1(drive
) = 0;
516 #ifdef HAVE_MULTIDRIVE
518 (drive
== INTERNAL_AS3525
) ? INTERRUPT_NAND
: INTERRUPT_MCI0
;
519 /* clear previous irq */
520 GPIOA_IC
= EXT_SD_BITS
;
521 /* enable edge detecting */
522 GPIOA_IS
&= ~EXT_SD_BITS
;
523 /* detect both raising and falling edges */
524 GPIOA_IBE
|= EXT_SD_BITS
;
525 /* enable the card detect interrupt */
526 GPIOA_IE
|= EXT_SD_BITS
;
529 VIC_INT_ENABLE
= INTERRUPT_NAND
;
532 MCI_POWER(drive
) = MCI_POWER_UP
| (MCI_VDD_3_0
); /* OF Setting */
535 MCI_POWER(drive
) |= MCI_POWER_ON
;
538 MCI_SELECT(drive
) = 0;
540 /* Pl180 clocks get turned on at start of card init */
546 CGU_IDE
= (1<<6) /* enable non AHB interface*/
547 | (AS3525_IDE_DIV
<< 2)
548 | AS3525_CLK_PLLA
; /* clock source = PLLA */
550 CGU_PERI
|= CGU_NAF_CLOCK_ENABLE
;
551 #ifdef HAVE_MULTIDRIVE
552 CGU_PERI
|= CGU_MCI_CLOCK_ENABLE
;
553 CCU_IO
&= ~(1<<3); /* bits 3:2 = 01, xpd is SD interface */
557 wakeup_init(&transfer_completion_signal
);
559 init_pl180_controller(INTERNAL_AS3525
);
560 ret
= sd_init_card(INTERNAL_AS3525
);
563 #ifdef HAVE_MULTIDRIVE
564 init_pl180_controller(SD_SLOT_AS3525
);
570 queue_init(&sd_queue
, true);
571 create_thread(sd_thread
, sd_stack
, sizeof(sd_stack
), 0,
572 sd_thread_name
IF_PRIO(, PRIORITY_USER_INTERFACE
) IF_COP(, CPU
));
581 bool sd_removable(IF_MD_NONVOID(int drive
))
586 bool sd_present(IF_MD_NONVOID(int drive
))
588 return (drive
== 0) ? true : card_detect_target();
590 #endif /* HAVE_HOTSWAP */
592 static int sd_wait_for_tran_state(const int drive
)
594 unsigned long response
= 0;
595 unsigned int timeout
= current_tick
+ 5 * HZ
;
599 if(!send_cmd(drive
, SD_SEND_STATUS
, card_info
[drive
].rca
, MCI_RESP
,
603 if (((response
>> 9) & 0xf) == SD_TRAN
)
606 if(TIME_AFTER(current_tick
, timeout
))
609 if (TIME_AFTER(current_tick
, next_yield
))
612 next_yield
= current_tick
+ MIN_YIELD_PERIOD
;
617 static int sd_select_bank(signed char bank
)
622 memset(uncached_buffer
, 0, 512);
624 { /* enable bank switching */
625 uncached_buffer
[0] = 16;
626 uncached_buffer
[1] = 1;
627 uncached_buffer
[2] = 10;
630 uncached_buffer
[0] = bank
;
633 if(loops
++ > PL180_MAX_TRANSFER_ERRORS
)
634 panicf("SD bank %d error : 0x%x", bank
,
635 transfer_error
[INTERNAL_AS3525
]);
637 ret
= sd_wait_for_tran_state(INTERNAL_AS3525
);
641 if(!send_cmd(INTERNAL_AS3525
, SD_SWITCH_FUNC
, 0x80ffffef, MCI_NO_RESP
,
647 if(!send_cmd(INTERNAL_AS3525
, 35, 0, MCI_NO_RESP
, NULL
))
653 /* we don't use the uncached buffer here, because we need the
654 * physical memory address for DMA transfers */
655 dma_enable_channel(0, aligned_buffer
, MCI_FIFO(INTERNAL_AS3525
),
656 DMA_PERI_SD
, DMAC_FLOWCTRL_PERI_MEM_TO_PERI
, true, false, 0, DMA_S8
,
659 MCI_DATA_TIMER(INTERNAL_AS3525
) = SD_MAX_WRITE_TIMEOUT
;
660 MCI_DATA_LENGTH(INTERNAL_AS3525
) = 512;
661 MCI_DATA_CTRL(INTERNAL_AS3525
) = (1<<0) /* enable */ |
662 (0<<1) /* transfer direction */ |
664 (9<<4) /* 2^9 = 512 */ ;
666 /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
667 wakeup_wait(&transfer_completion_signal
, TIMEOUT_BLOCK
);
669 /* Wait for FIFO to empty, card may still be in PRG state */
670 while(MCI_STATUS(INTERNAL_AS3525
) & MCI_TX_ACTIVE
);
674 } while(transfer_error
[INTERNAL_AS3525
]);
676 card_info
[INTERNAL_AS3525
].current_bank
= (bank
== -1) ? 0 : bank
;
681 static int sd_transfer_sectors(IF_MD2(int drive
,) unsigned long start
,
682 int count
, void* buf
, const bool write
)
684 #ifndef HAVE_MULTIDRIVE
689 unsigned long response
;
690 bool aligned
= !((uintptr_t)buf
& (CACHEALIGN_SIZE
- 1));
696 if (card_info
[drive
].initialized
<= 0)
698 ret
= sd_init_card(drive
);
699 if (!(card_info
[drive
].initialized
))
700 goto sd_transfer_error_nodma
;
703 if(count
< 0) /* XXX: why is it signed ? */
706 goto sd_transfer_error_nodma
;
708 if((start
+count
) > card_info
[drive
].numblocks
)
711 goto sd_transfer_error_nodma
;
714 /* skip SanDisk OF */
715 if (drive
== INTERNAL_AS3525
)
716 start
+= AMS_OF_SIZE
;
718 last_disk_activity
= current_tick
;
725 clean_dcache_range(buf
, count
* SECTOR_SIZE
);
727 dump_dcache_range(buf
, count
* SECTOR_SIZE
);
732 /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
733 * register, so we have to transfer maximum 127 sectors at a time. */
734 unsigned int transfer
= (count
>= 128) ? 127 : count
; /* sectors */
737 write
? SD_WRITE_MULTIPLE_BLOCK
: SD_READ_MULTIPLE_BLOCK
;
738 unsigned long bank_start
= start
;
739 unsigned long status
;
741 /* Only switch banks for internal storage */
742 if(drive
== INTERNAL_AS3525
)
744 unsigned int bank
= 0;
745 while(bank_start
>= BLOCKS_PER_BANK
)
747 bank_start
-= BLOCKS_PER_BANK
;
751 /* Switch bank if needed */
752 if(card_info
[INTERNAL_AS3525
].current_bank
!= bank
)
754 ret
= sd_select_bank(bank
);
758 goto sd_transfer_error
;
762 /* Do not cross a bank boundary in a single transfer loop */
763 if((transfer
+ bank_start
) > BLOCKS_PER_BANK
)
764 transfer
= BLOCKS_PER_BANK
- bank_start
;
767 /* Set bank_start to the correct unit (blocks or bytes) */
768 if(!(card_info
[drive
].ocr
& (1<<30))) /* not SDHC */
769 bank_start
*= SD_BLOCK_SIZE
;
773 dma_buf
= AS3525_PHYSICAL_ADDR(buf
);
777 dma_buf
= aligned_buffer
;
778 if(transfer
> UNALIGNED_NUM_SECTORS
)
779 transfer
= UNALIGNED_NUM_SECTORS
;
782 memcpy(uncached_buffer
, buf
, transfer
* SD_BLOCK_SIZE
);
785 ret
= sd_wait_for_tran_state(drive
);
789 goto sd_transfer_error
;
792 if(!send_cmd(drive
, cmd
, bank_start
, MCI_RESP
, &response
))
795 goto sd_transfer_error
;
800 dma_enable_channel(0, dma_buf
, MCI_FIFO(drive
),
801 (drive
== INTERNAL_AS3525
) ? DMA_PERI_SD
: DMA_PERI_SD_SLOT
,
802 DMAC_FLOWCTRL_PERI_MEM_TO_PERI
, true, false, 0, DMA_S8
, NULL
);
804 /*Small delay for writes prevents data crc failures at lower freqs*/
805 #ifdef HAVE_MULTIDRIVE
806 if((drive
== SD_SLOT_AS3525
) && !hs_card
)
808 int write_delay
= 125;
809 while(write_delay
--);
814 dma_enable_channel(0, MCI_FIFO(drive
), dma_buf
,
815 (drive
== INTERNAL_AS3525
) ? DMA_PERI_SD
: DMA_PERI_SD_SLOT
,
816 DMAC_FLOWCTRL_PERI_PERI_TO_MEM
, false, true, 0, DMA_S8
, NULL
);
818 MCI_DATA_TIMER(drive
) = write
?
819 SD_MAX_WRITE_TIMEOUT
: SD_MAX_READ_TIMEOUT
;
820 MCI_DATA_LENGTH(drive
) = transfer
* SD_BLOCK_SIZE
;
821 MCI_DATA_CTRL(drive
) = (1<<0) /* enable */ |
822 (!write
<<1) /* transfer direction */ |
824 (9<<4) /* 2^9 = 512 */ ;
826 /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
827 wakeup_wait(&transfer_completion_signal
, TIMEOUT_BLOCK
);
829 /* Wait for FIFO to empty, card may still be in PRG state for writes */
830 while(MCI_STATUS(drive
) & MCI_TX_ACTIVE
);
833 * If the write aborted early due to a tx underrun, disable the
834 * dma channel here, otherwise there are still 4 words in the fifo
835 * and the retried write will get corrupted.
837 dma_disable_channel(0);
839 last_disk_activity
= current_tick
;
841 if(!send_cmd(drive
, SD_STOP_TRANSMISSION
, 0, MCI_RESP
, &status
))
844 goto sd_transfer_error
;
847 if(!transfer_error
[drive
])
849 if(!write
&& !aligned
)
850 memcpy(buf
, uncached_buffer
, transfer
* SD_BLOCK_SIZE
);
851 buf
+= transfer
* SD_BLOCK_SIZE
;
854 loops
= 0; /* reset errors counter */
856 else if(loops
++ > PL180_MAX_TRANSFER_ERRORS
)
857 panicf("SD Xfer %s err:0x%x Disk%d", (write
? "write": "read"),
858 transfer_error
[drive
], drive
);
865 sd_transfer_error_nodma
:
871 card_info
[drive
].initialized
= 0;
873 mutex_unlock(&sd_mtx
);
877 int sd_read_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
880 return sd_transfer_sectors(IF_MD2(drive
,) start
, count
, buf
, false);
883 int sd_write_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
887 unsigned long saved_start
= start
;
888 int saved_count
= count
;
889 void *saved_buf
= (void*)buf
;
893 ret
= sd_transfer_sectors(IF_MD2(drive
,) start
, count
, (void*)buf
, true);
896 if (ret
) /* write failed, no point in verifying */
903 int transfer
= count
;
904 if(transfer
> UNALIGNED_NUM_SECTORS
)
905 transfer
= UNALIGNED_NUM_SECTORS
;
907 sd_transfer_sectors(IF_MD2(drive
,) start
, transfer
, aligned_buffer
, false);
908 if (memcmp(buf
, aligned_buffer
, transfer
* 512) != 0) {
909 /* try the write again in the hope to repair the damage */
910 sd_transfer_sectors(IF_MD2(drive
,) saved_start
, saved_count
, saved_buf
, true);
911 panicf("sd: verify failed: sec=%ld n=%d!", start
, transfer
);
914 buf
+= transfer
* 512;
922 long sd_last_disk_activity(void)
924 return last_disk_activity
;
927 void sd_enable(bool on
)
929 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
930 extern int buttonlight_is_on
;
933 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
934 static bool cpu_boosted
= false;
937 if (sd_enabled
== on
)
938 return; /* nothing to do */
944 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
945 /* buttonlight AMSes need a bit of special handling for the buttonlight
946 * here due to the dual mapping of GPIOD and XPD */
947 CCU_IO
|= (1<<2); /* XPD is SD-MCI interface (b3:2 = 01) */
948 if (buttonlight_is_on
)
949 GPIOD_DIR
&= ~(1<<7);
954 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
955 if(card_detect_target()) /* If SD card present Boost cpu for voltage */
960 #endif /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
964 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
970 #endif /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
972 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
973 CCU_IO
&= ~(1<<2); /* XPD is general purpose IO (b3:2 = 00) */
974 if (buttonlight_is_on
)
980 tCardInfo
*card_get_info_target(int card_no
)
982 return &card_info
[card_no
];
985 #ifdef CONFIG_STORAGE_MULTI
986 int sd_num_drives(int first_drive
)
988 /* We don't care which logical drive number(s) we have been assigned */
993 #endif /* CONFIG_STORAGE_MULTI */