firmware/target/arm/as3525/debug-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include <stdbool.h>
  23 #include "debug-target.h"
  24 #include "button.h"
  25 #include "lcd.h"
  26 #include "font.h"
  27 #include "system.h"
  28 #include "cpu.h"
  29 #include "pl180.h"
  30 #include "ascodec-target.h"
  31 #include "adc.h"
  32 #include "storage.h"
  33
  34 #define ON "Enabled"
  35 #define OFF "Disabled"
  36
  37 #define CP15_MMU (1<<0)            /* mmu off/on */
  38 #define CP15_DC  (1<<2)            /* dcache off/on */
  39 #define CP15_IC  (1<<12)           /* icache off/on */
  40
  41 #define CLK_MAIN         24000000     /* 24 MHz  */
  42
  43 #define CLK_PLLA             0
  44 #define CLK_PLLB             1
  45 #define CLK_PROC             2
  46 #define CLK_FCLK             3
  47 #define CLK_EXTMEM           4
  48 #define CLK_PCLK             5
  49 #define CLK_IDE              6
  50 #define CLK_I2C              7
  51 #define CLK_I2SI             8
  52 #define CLK_I2SO             9
  53 #define CLK_DBOP             10
  54 #define CLK_SD_MCLK_NAND     11
  55 #define CLK_SD_MCLK_MSD      12
  56 #define CLK_USB              13
  57
  58 #define I2C2_CPSR0      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x1C))
  59 #define I2C2_CPSR1      *((volatile unsigned int *)(I2C_AUDIO_BASE + 0x20))
  60 #define MCI_NAND        *((volatile unsigned long *)(NAND_FLASH_BASE + 0x04))
  61 #define MCI_SD          *((volatile unsigned long *)(SD_MCI_BASE + 0x04))
  62
  63 extern bool sd_enabled;
  64
  65 /* FIXME: target tree is including ./debug-target.h rather than the one in
  66  * sansa-fuze/, even though deps contains the correct one
  67  * if I put the below into a sansa-fuze/debug-target.h, it doesn't work*/
  68 #if defined(SANSA_FUZE) || defined(SANSA_E200V2) || defined(SANSA_C200V2)
  69 #define DEBUG_DBOP
  70 #include "dbop-as3525.h"
  71 #endif
  72
  73 static inline unsigned read_cp15 (void)
  74 {
  75     unsigned cp15_value;
  76     asm volatile (
  77         "mrc p15, 0, %0, c1, c0, 0   @ read control reg\n" : "=r"(cp15_value));
  78     return (cp15_value);
  79 }
  80
  81 static int calc_freq(int clk)
  82 {
  83     unsigned int prediv = ((unsigned int)CGU_PROC>>2) & 0x3;
  84     unsigned int postdiv = ((unsigned int)CGU_PROC>>4) & 0xf;
  85 #if CONFIG_CPU == AS3525
  86     int out_div;
  87
  88     switch(clk) {
  89         /* clk_main = clk_int = 24MHz oscillator */
  90         case CLK_PLLA:
  91             if(CGU_PLLASUP & (1<<3))
  92                 return 0;
  93
  94                  /*assume 24MHz oscillator only input available */
  95             out_div = ((CGU_PLLA>>13) & 0x3);         /* bits 13:14 */
  96             if (out_div == 3)                         /* for 11 NO=4  */
  97                 out_div=4;
  98             if(out_div)                               /*  NO = 0 not allowed */
  99                 return ((2 * (CGU_PLLA & 0xff))*CLK_MAIN)/
 100                                                (((CGU_PLLA>>8) & 0x1f)*out_div);
 101             return 0;
 102        case CLK_PLLB:
 103             if(CGU_PLLBSUP & (1<<3))
 104                 return 0;
 105
 106                  /*assume 24MHz oscillator only input available */
 107             out_div = ((CGU_PLLB>>13) & 0x3);         /* bits 13:14 */
 108             if (out_div == 3)                         /* for 11 NO=4  */
 109                 out_div=4;
 110             if(out_div)                               /*  NO = 0 not allowed */
 111                 return ((2 * (CGU_PLLB & 0xff))*CLK_MAIN)/
 112                                                (((CGU_PLLB>>8) & 0x1f)*out_div);
 113             return 0;
 114 #else
 115     int od, f, r;
 116
 117     /* AS3525v2  */
 118     switch(clk) {
 119         case CLK_PLLA:
 120             if(CGU_PLLASUP & (1<<3))
 121                 return 0;
 122
 123             f = (CGU_PLLA & 0x7F) + 1;
 124             r = ((CGU_PLLA >> 7) & 0x7) + 1;
 125             od = (CGU_PLLA >> 10) & 1 ? 2 : 1;
 126             return (CLK_MAIN / 2) * f / (r * od);
 127
 128         case CLK_PLLB:
 129             if(CGU_PLLBSUP & (1<<3))
 130                 return 0;
 131
 132             f = (CGU_PLLB & 0x7F) + 1;
 133             r = ((CGU_PLLB >> 7) & 0x7) + 1;
 134             od = (CGU_PLLB >> 10) & 1 ? 2 : 1;
 135             return (CLK_MAIN / 2) * f / (r * od);
 136 #endif
 137         case CLK_PROC:
 138 #if CONFIG_CPU == AS3525 /* not in arm926-ejs */
 139             if (!(read_cp15()>>30))                 /* fastbus */
 140                 return calc_freq(CLK_PCLK);
 141             else                                    /* Synch or Asynch bus*/
 142 #endif /* CONFIG_CPU == AS3525 */
 143                 return calc_freq(CLK_FCLK);
 144         case CLK_FCLK:
 145             switch(CGU_PROC & 3) {
 146                 case 0:
 147                     return (CLK_MAIN * (8 - prediv)) / (8 * (postdiv + 1));
 148                 case 1:
 149                     return (calc_freq(CLK_PLLA) * (8 - prediv)) /
 150                                                             (8 * (postdiv + 1));
 151                 case 2:
 152                     return (calc_freq(CLK_PLLB) * (8 - prediv)) /
 153                                                             (8 * (postdiv + 1));
 154                 default:
 155                     return 0;
 156             }
 157         case CLK_EXTMEM:
 158 #if CONFIG_CPU == AS3525
 159             switch(CGU_PERI & 3) {
 160 #else
 161             /* bits 1:0 of CGU_PERI always read as 0 and source = FCLK */
 162             switch(3) {
 163 #endif
 164                 case 0:
 165                     return CLK_MAIN/(((CGU_PERI>>2)& 0xf)+1);
 166                 case 1:
 167                     return calc_freq(CLK_PLLA)/(((CGU_PERI>>2)& 0xf)+1);
 168                 case 2:
 169                     return calc_freq(CLK_PLLB)/(((CGU_PERI>>2)& 0xf)+1);
 170                 case 3:
 171                 default:
 172                     return calc_freq(CLK_FCLK)/(((CGU_PERI>>2)& 0xf)+1);
 173             }
 174         case CLK_PCLK:
 175             return calc_freq(CLK_EXTMEM)/(((CGU_PERI>>6)& 0x1)+1);
 176         case CLK_IDE:
 177             switch(CGU_IDE & 3) {
 178                 case 0:
 179                     return CLK_MAIN/(((CGU_IDE>>2)& 0xf)+1);
 180                 case 1:
 181                     return calc_freq(CLK_PLLA)/(((CGU_IDE>>2)& 0xf)+1);
 182                 case 2:
 183                     return calc_freq(CLK_PLLB)/(((CGU_IDE>>2)& 0xf)+1);
 184                 default:
 185                     return 0;
 186             }
 187         case CLK_I2C:
 188             return calc_freq(CLK_PCLK)/AS3525_I2C_PRESCALER;
 189         case CLK_I2SI:
 190             switch((CGU_AUDIO>>12) & 3) {
 191                 case 0:
 192                     return CLK_MAIN/(((CGU_AUDIO>>14) & 0x1ff)+1);
 193                 case 1:
 194                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 195                 case 2:
 196                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>14) & 0x1ff)+1);
 197                 default:
 198                     return 0;
 199             }
 200         case CLK_I2SO:
 201             switch(CGU_AUDIO & 3) {
 202                 case 0:
 203                     return CLK_MAIN/(((CGU_AUDIO>>2) & 0x1ff)+1);
 204                 case 1:
 205                     return calc_freq(CLK_PLLA)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 206                 case 2:
 207                     return calc_freq(CLK_PLLB)/(((CGU_AUDIO>>2) & 0x1ff)+1);
 208                 default:
 209                     return 0;
 210             }
 211         case CLK_DBOP:
 212             return calc_freq(CLK_PCLK)/((CGU_DBOP & 7)+1);
 213 #if CONFIG_CPU == AS3525
 214         case CLK_SD_MCLK_NAND:
 215             if(!(MCI_NAND & (1<<8)))
 216                 return 0;
 217             else if(MCI_NAND & (1<<10))
 218                 return calc_freq(CLK_IDE);
 219             else
 220                 return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
 221         case CLK_SD_MCLK_MSD:
 222             if(!(MCI_SD & (1<<8)))
 223                 return 0;
 224             else if(MCI_SD & (1<<10))
 225                 return calc_freq(CLK_PCLK);
 226             else
 227             return calc_freq(CLK_PCLK)/(((MCI_SD & 0xff)+1)*2);
 228 #endif
 229         case CLK_USB:
 230             switch(CGU_USB & 3) {     /* 0-> div=1  other->div=1/(2*n)  */
 231                 case 0:
 232                     if (!((CGU_USB>>2) & 0x7))
 233                         return CLK_MAIN;
 234                     else
 235                         return CLK_MAIN/(2*((CGU_USB>>2) & 0x7));
 236                 case 1:
 237                     if (!((CGU_USB>>2) & 0x7))
 238                         return calc_freq(CLK_PLLA);
 239                     else
 240                         return calc_freq(CLK_PLLA)/(2*((CGU_USB>>2) & 0x7));
 241                 case 2:
 242                     if (!((CGU_USB>>2) & 0x7))
 243                         return calc_freq(CLK_PLLB);
 244                     else
 245                         return calc_freq(CLK_PLLB)/(2*((CGU_USB>>2) & 0x7));
 246                 default:
 247                     return 0;
 248             }
 249         default:
 250             return 0;
 251         }
 252 }
 253
 254 bool __dbg_hw_info(void)
 255 {
 256     int line;
 257 #if CONFIG_CPU == AS3525
 258     int last_nand = 0;
 259 #ifdef HAVE_MULTIDRIVE
 260     int last_sd = 0;
 261 #endif
 262 #endif /* CONFIG_CPU == AS3525 */
 263
 264     lcd_clear_display();
 265     lcd_setfont(FONT_SYSFIXED);
 266
 267     while(1)
 268     {
 269         while(1)
 270         {
 271 #ifdef SANSA_C200V2
 272         lcd_clear_display();
 273         line = 0;
 274         lcd_puts(0, line++, "[Submodel:]");
 275         lcd_putsf(0, line++, "C200v2 variant %d", c200v2_variant);
 276         lcd_update();
 277         int btn = button_get_w_tmo(HZ/10);
 278         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 279             goto end;
 280         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 281             break;
 282         }
 283         while(1)
 284         {
 285 #endif
 286         lcd_clear_display();
 287         line = 0;
 288         lcd_puts(0, line++, "[Clock Frequencies:]");
 289         lcd_puts(0, line++, "     SET       ACTUAL");
 290 #if CONFIG_CPU == AS3525
 291         lcd_putsf(0, line++, "922T:%s     %3dMHz",
 292                                         (!(read_cp15()>>30)) ? "FAST " :
 293                                         (read_cp15()>>31) ? "ASYNC" : "SYNC ",
 294 #else
 295         lcd_putsf(0, line++, "926ejs:        %3dMHz",
 296 #endif
 297                                          calc_freq(CLK_PROC)/1000000);
 298         lcd_putsf(0, line++, "PLLA:%3dMHz    %3dMHz", AS3525_PLLA_FREQ/1000000,
 299                                                    calc_freq(CLK_PLLA)/1000000);
 300         lcd_putsf(0, line++, "PLLB:          %3dMHz", calc_freq(CLK_PLLB)/1000000);
 301         lcd_putsf(0, line++, "FCLK:          %3dMHz", calc_freq(CLK_FCLK)/1000000);
 302         lcd_putsf(0, line++, "DRAM:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 303                                                  calc_freq(CLK_EXTMEM)/1000000);
 304         lcd_putsf(0, line++, "PCLK:%3dMHz    %3dMHz", AS3525_PCLK_FREQ/1000000,
 305                                                    calc_freq(CLK_PCLK)/1000000);
 306
 307 #if LCD_HEIGHT < 176  /* clip  */
 308         lcd_update();
 309         int btn = button_get_w_tmo(HZ/10);
 310         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 311             goto end;
 312         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 313             break;
 314         }
 315         while(1)
 316         {
 317         lcd_clear_display();
 318         line = 0;
 319 #endif  /*  LCD_HEIGHT < 176 */
 320
 321         lcd_putsf(0, line++, "IDE :%3dMHz    %3dMHz", AS3525_IDE_FREQ/1000000,
 322                                                     calc_freq(CLK_IDE)/1000000);
 323         lcd_putsf(0, line++, "DBOP:%3dMHz    %3dMHz", AS3525_DBOP_FREQ/1000000,
 324                                                    calc_freq(CLK_DBOP)/1000000);
 325         lcd_putsf(0, line++, "I2C :%3dkHz    %3dkHz", AS3525_I2C_FREQ/1000,
 326                                                        calc_freq(CLK_I2C)/1000);
 327         lcd_putsf(0, line++, "I2SI: %s      %3dMHz", (CGU_AUDIO & (1<<23)) ?
 328                                    "on " : "off" , calc_freq(CLK_I2SI)/1000000);
 329         lcd_putsf(0, line++, "I2SO: %s      %3dMHz", (CGU_AUDIO & (1<<11)) ?
 330                                     "on " : "off", calc_freq(CLK_I2SO)/1000000);
 331 #if CONFIG_CPU == AS3525
 332         /* If disabled, enable SD cards so we can read the registers */
 333         if(sd_enabled == false)
 334         {
 335             sd_enable(true);
 336             last_nand = MCI_NAND;
 337 #ifdef HAVE_MULTIDRIVE
 338             last_sd = MCI_SD;
 339 #endif
 340             sd_enable(false);
 341         }
 342
 343         lcd_putsf(0, line++, "SD  :%3dMHz    %3dMHz",
 344             ((AS3525_IDE_FREQ/ 1000000) /
 345             ((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))),
 346             calc_freq(CLK_SD_MCLK_NAND)/1000000);
 347 #ifdef HAVE_MULTIDRIVE
 348         lcd_putsf(0, line++, "uSD :%3dMHz    %3dMHz",
 349             ((AS3525_PCLK_FREQ/ 1000000) /
 350             ((last_sd & MCI_CLOCK_BYPASS) ? 1: (((last_sd & 0xff) + 1) * 2))),
 351             calc_freq(CLK_SD_MCLK_MSD)/1000000);
 352 #endif
 353 #endif  /* CONFIG_CPU == AS3525 */
 354         lcd_putsf(0, line++, "USB :          %3dMHz", calc_freq(CLK_USB)/1000000);
 355
 356 #if LCD_HEIGHT < 176  /* clip  */
 357         lcd_update();
 358         int btn = button_get_w_tmo(HZ/10);
 359         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 360             goto end;
 361         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 362             break;
 363         }
 364         while(1)
 365         {
 366         lcd_clear_display();
 367         line = 0;
 368 #endif  /*  LCD_HEIGHT < 176 */
 369
 370         lcd_putsf(0, line++, "MMU :  %s CVDDP:%4d", (read_cp15() & CP15_MMU) ?
 371                                         " on" : "off", adc_read(ADC_CVDD) * 25);
 372         lcd_putsf(0, line++, "Icache:%s Dcache:%s",
 373                                       (read_cp15() & CP15_IC)  ? " on" : "off",
 374                                       (read_cp15() & CP15_DC)  ? " on" : "off");
 375
 376         lcd_update();
 377         int btn = button_get_w_tmo(HZ/10);
 378         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 379             goto end;
 380         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 381             break;
 382         }
 383         while(1)
 384         {
 385         lcd_clear_display();
 386         line = 0;
 387
 388         lcd_putsf(0, line++, "CGU_PLLA  :%8x", (unsigned int)(CGU_PLLA));
 389         lcd_putsf(0, line++, "CGU_PLLB  :%8x", (unsigned int)(CGU_PLLB));
 390         lcd_putsf(0, line++, "CGU_PROC  :%8x", (unsigned int)(CGU_PROC));
 391         lcd_putsf(0, line++, "CGU_PERI  :%8x", (unsigned int)(CGU_PERI));
 392         lcd_putsf(0, line++, "CGU_IDE   :%8x", (unsigned int)(CGU_IDE));
 393         lcd_putsf(0, line++, "CGU_DBOP  :%8x", (unsigned int)(CGU_DBOP));
 394         lcd_putsf(0, line++, "CGU_AUDIO :%8x", (unsigned int)(CGU_AUDIO));
 395         lcd_putsf(0, line++, "CGU_USB   :%8x", (unsigned int)(CGU_USB));
 396
 397 #if LCD_HEIGHT < 176  /* clip  */
 398         lcd_update();
 399         int btn = button_get_w_tmo(HZ/10);
 400         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 401             goto end;
 402         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 403             break;
 404         }
 405         while(1)
 406         {
 407         lcd_clear_display();
 408         line = 0;
 409 #endif  /*  LCD_HEIGHT < 176 */
 410
 411         lcd_putsf(0, line++, "I2C2_CPSR :%8x", (unsigned int)(I2C2_CPSR1<<8 |
 412                                                        I2C2_CPSR0));
 413 #if CONFIG_CPU == AS3525
 414         lcd_putsf(0, line++, "MCI_NAND  :%8x", (unsigned int)(MCI_NAND));
 415         lcd_putsf(0, line++, "MCI_SD    :%8x", (unsigned int)(MCI_SD));
 416 #else
 417         lcd_putsf(0, line++, "CGU_MEMSTK:%8x", (unsigned int)(CGU_MEMSTICK));
 418         lcd_putsf(0, line++, "CGU_SDSLOT:%8x", (unsigned int)(CGU_SDSLOT));
 419 #endif
 420
 421         lcd_update();
 422         int btn = button_get_w_tmo(HZ/10);
 423         if(btn == (DEBUG_CANCEL|BUTTON_REL))
 424             goto end;
 425         else if(btn == (BUTTON_DOWN|BUTTON_REL))
 426             break;
 427         }
 428     }
 429
 430 end:
 431     lcd_setfont(FONT_UI);
 432     return false;
 433 }
 434
 435 bool __dbg_ports(void)
 436 {
 437     int line, btn, i;
 438
 439     lcd_setfont(FONT_SYSFIXED);
 440
 441     while(1)
 442     {
 443         lcd_clear_display();
 444
 445         while(1)
 446         {
 447             line = 0;
 448             lcd_puts(0, line++, "[GPIO Vals and Dirs]");
 449             lcd_putsf(0, line++, "GPIOA: %2x DIR: %2x", GPIOA_DATA, GPIOA_DIR);
 450             lcd_putsf(0, line++, "GPIOB: %2x DIR: %2x", GPIOB_DATA, GPIOB_DIR);
 451             lcd_putsf(0, line++, "GPIOC: %2x DIR: %2x", GPIOC_DATA, GPIOC_DIR);
 452             lcd_putsf(0, line++, "GPIOD: %2x DIR: %2x", GPIOD_DATA, GPIOD_DIR);
 453 #ifdef DEBUG_DBOP
 454             line++;
 455             lcd_puts(0, line++, "[DBOP_DIN]");
 456             lcd_putsf(0, line++, "DBOP_DIN: %4x", dbop_debug());
 457 #endif
 458             line++;
 459             lcd_puts(0, line++, "[CP15]");
 460             lcd_putsf(0, line++, "CP15: 0x%8x", read_cp15());
 461             lcd_update();
 462             if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
 463                 break;
 464
 465             btn = button_get_w_tmo(HZ/10);
 466             if(btn == (DEBUG_CANCEL|BUTTON_REL))
 467                 goto end;
 468             else if(btn == (BUTTON_DOWN|BUTTON_REL))
 469                 break;
 470         }
 471
 472 #if CONFIG_CPU == AS3525 /* as3525v2 channels are different */
 473 #define BATTEMP_UNIT 5/2 /* 2.5mV */
 474         static const char *adc_name[13] = {
 475             "CHG_OUT  ",
 476             "RTCSUP   ",
 477             "VBUS     ",
 478             "CHG_IN   ",
 479             "CVDD     ",
 480             "BatTemp  ",
 481             "MicSup1  ",
 482             "MicSup2  ",
 483             "VBE1     ",
 484             "VBE2     ",
 485             "I_MicSup1",
 486             "I_MicSup2",
 487             "VBAT     ",
 488         };
 489 #elif CONFIG_CPU == AS3525v2
 490 #define BATTEMP_UNIT 2 /* 2mV */
 491         static const char *adc_name[16] = {
 492             "BVDD    ",
 493             "BVDDR   ",
 494             "CHGIN   ",
 495             "CHGOUT  ",
 496             "VBUS    ",
 497             NULL,
 498             "BatTemp ",
 499             NULL,
 500             "MicSup  ",
 501             NULL,
 502             "I_MiSsup",
 503             NULL,
 504             "VBE_1uA ",
 505             "VBE_2uA ",
 506             "I_CHGact",
 507             "I_CHGref",
 508         };
 509 #endif
 510
 511         lcd_clear_display();
 512
 513         while(1)
 514         {
 515             line = 0;
 516
 517             for(i=0; i<5; i++)
 518                 lcd_putsf(0, line++, "%s: %d mV", adc_name[i], adc_read(i) * 5);
 519             for(; i<8; i++)
 520                 if(adc_name[i])
 521                     lcd_putsf(0, line++, "%s: %d mV", adc_name[i],
 522                               adc_read(i) * BATTEMP_UNIT);
 523 #if LCD_HEIGHT < 176  /* clip  */
 524             lcd_update();
 525
 526             btn = button_get_w_tmo(HZ/10);
 527             if(btn == (DEBUG_CANCEL|BUTTON_REL))
 528                 goto end;
 529             else if(btn == (BUTTON_DOWN|BUTTON_REL))
 530                 break;
 531         }
 532         lcd_clear_display();
 533         while(1)
 534         {
 535             line = 0;
 536 #endif /* LCD_HEIGHT < 176 */
 537             for(i=8; i<10; i++)
 538                 if(adc_name[i])
 539                     lcd_putsf(0, line++, "%s: %d mV", adc_name[i], adc_read(i));
 540             for(; i<12; i++)
 541                 if(adc_name[i])
 542                     lcd_putsf(0, line++, "%s: %d uA", adc_name[i], adc_read(i));
 543 #if CONFIG_CPU == AS3525 /* different units */
 544             lcd_putsf(0, line++, "%s: %d mV", adc_name[i], adc_read(i)*5/2);
 545 #elif CONFIG_CPU == AS3525v2
 546             for(; i<16; i++)
 547                 lcd_putsf(0, line++, "%s: %d mV", adc_name[i], adc_read(i));
 548 #endif
 549             lcd_update();
 550
 551             btn = button_get_w_tmo(HZ/10);
 552             if(btn == (DEBUG_CANCEL|BUTTON_REL))
 553                 goto end;
 554             else if(btn == (BUTTON_DOWN|BUTTON_REL))
 555                 break;
 556         }
 557     }
 558
 559 end:
 560     lcd_setfont(FONT_UI);
 561     return false;
 562 }