1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright © 2008-2009 Rafaël Carré
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
26 #include "dma-target.h"
27 #include "clock-target.h"
33 #define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA
34 * i.e. 32 bits at once (size of I2SO_DATA)
35 * and the number of 32bits words has to
36 * fit in 11 bits of DMA register */
38 static unsigned char *dma_start_addr
;
39 static size_t dma_size
; /* in 4*32 bits */
40 static void dma_callback(void);
41 static int locked
= 0;
43 /* Mask the DMA interrupt */
44 void pcm_play_lock(void)
47 VIC_INT_EN_CLEAR
= INTERRUPT_DMAC
;
50 /* Unmask the DMA interrupt if enabled */
51 void pcm_play_unlock(void)
54 VIC_INT_ENABLE
= INTERRUPT_DMAC
;
57 static void play_start_pcm(void)
59 const unsigned char* addr
= dma_start_addr
;
60 size_t size
= dma_size
;
61 if(size
> MAX_TRANSFER
)
65 dma_start_addr
+= size
;
67 clean_dcache_range((void*)addr
, size
); /* force write back */
68 dma_enable_channel(1, (void*)addr
, (void*)I2SOUT_DATA
, DMA_PERI_I2SOUT
,
69 DMAC_FLOWCTRL_DMAC_MEM_TO_PERI
, true, false, size
>> 2, DMA_S1
,
73 static void dma_callback(void)
77 register pcm_more_callback_type get_more
= pcm_callback_for_more
;
79 get_more(&dma_start_addr
, &dma_size
);
85 pcm_play_dma_stopped_callback();
91 void pcm_play_dma_start(const void *addr
, size_t size
)
94 dma_start_addr
= (unsigned char*)addr
;
96 CGU_PERI
|= CGU_I2SOUT_APB_CLOCK_ENABLE
;
104 void pcm_play_dma_stop(void)
106 dma_disable_channel(1);
111 CGU_PERI
&= ~CGU_I2SOUT_APB_CLOCK_ENABLE
;
112 CGU_AUDIO
&= ~(1<<11);
115 void pcm_play_dma_pause(bool pause
)
118 dma_disable_channel(1);
123 void pcm_play_dma_init(void)
125 CGU_PERI
|= CGU_I2SOUT_APB_CLOCK_ENABLE
;
127 I2SOUT_CONTROL
= (1<<6)|(1<<3) /* enable dma, stereo */;
132 void pcm_postinit(void)
137 /* divider is 9 bits but the highest one (for 8kHz) fit in 8 bits */
138 static const unsigned char divider
[SAMPR_NUM_FREQ
] = {
139 [HW_FREQ_96
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_96
/2) / SAMPR_96
) - 1,
140 [HW_FREQ_88
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_88
/2) / SAMPR_88
) - 1,
141 [HW_FREQ_64
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_64
/2) / SAMPR_64
) - 1,
142 [HW_FREQ_48
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_48
/2) / SAMPR_48
) - 1,
143 [HW_FREQ_44
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_44
/2) / SAMPR_44
) - 1,
144 [HW_FREQ_32
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_32
/2) / SAMPR_32
) - 1,
145 [HW_FREQ_24
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_24
/2) / SAMPR_24
) - 1,
146 [HW_FREQ_22
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_22
/2) / SAMPR_22
) - 1,
147 [HW_FREQ_16
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_16
/2) / SAMPR_16
) - 1,
148 [HW_FREQ_12
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_12
/2) / SAMPR_12
) - 1,
149 [HW_FREQ_11
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_11
/2) / SAMPR_11
) - 1,
150 [HW_FREQ_8
] = ((AS3525_MCLK_FREQ
/128 + SAMPR_8
/2) / SAMPR_8
) - 1,
153 static inline unsigned char mclk_divider(void)
155 return divider
[pcm_fsel
];
158 void pcm_dma_apply_settings(void)
160 int cgu_audio
= CGU_AUDIO
; /* read register */
161 cgu_audio
&= ~(3 << 0); /* clear i2sout MCLK_SEL */
162 cgu_audio
|= (AS3525_MCLK_SEL
<< 0); /* set i2sout MCLK_SEL */
163 cgu_audio
&= ~(0x1ff << 2); /* clear i2sout divider */
164 cgu_audio
|= mclk_divider() << 2; /* set new i2sout divider */
165 CGU_AUDIO
= cgu_audio
; /* write back register */
168 size_t pcm_get_bytes_waiting(void)
173 const void * pcm_play_dma_get_peak_buffer(int *count
)
175 *count
= dma_size
>> 2;
176 return (const void*)dma_start_addr
;
179 #ifdef HAVE_PCM_DMA_ADDRESS
180 void * pcm_dma_addr(void *addr
)
183 addr
= UNCACHED_ADDR(addr
);
189 /****************************************************************************
190 ** Recording DMA transfer
192 #ifdef HAVE_RECORDING
194 static int rec_locked
= 0;
195 static unsigned char *rec_dma_start_addr
;
196 static size_t rec_dma_size
;
197 static void rec_dma_callback(void);
200 void pcm_rec_lock(void)
202 if(++rec_locked
== 1)
203 VIC_INT_EN_CLEAR
= INTERRUPT_DMAC
;
207 void pcm_rec_unlock(void)
209 if(--rec_locked
== 0)
210 VIC_INT_ENABLE
= INTERRUPT_DMAC
;
214 static void rec_dma_start(void)
216 void* addr
= rec_dma_start_addr
;
217 size_t size
= rec_dma_size
;
219 /* We are limited to 8188 DMA transfers, and the recording core asks for
220 * 8192 bytes. Avoid splitting 8192 bytes transfers in 8188 + 4 */
224 rec_dma_size
-= size
;
225 rec_dma_start_addr
+= size
;
227 dma_enable_channel(1, (void*)I2SIN_DATA
, addr
, DMA_PERI_I2SIN
,
228 DMAC_FLOWCTRL_DMAC_PERI_TO_MEM
, false, true, size
>> 2, DMA_S4
,
233 static void rec_dma_callback(void)
237 register pcm_more_callback_type2 more_ready
= pcm_callback_more_ready
;
238 if (!more_ready
|| more_ready(0) < 0)
240 /* Finished recording */
242 pcm_rec_dma_stopped_callback();
251 void pcm_rec_dma_record_more(void *start
, size_t size
)
253 dump_dcache_range(start
, size
);
254 rec_dma_start_addr
= start
;
259 void pcm_rec_dma_stop(void)
261 dma_disable_channel(1);
265 I2SOUT_CONTROL
&= ~(1<<5); /* source = i2soutif fifo */
266 I2SIN_CONTROL
&= ~(1<<11); /* disable dma */
268 CGU_AUDIO
&= ~((1<<23)|(1<<11));
269 CGU_PERI
&= ~(CGU_I2SIN_APB_CLOCK_ENABLE
|CGU_I2SOUT_APB_CLOCK_ENABLE
);
273 void pcm_rec_dma_start(void *addr
, size_t size
)
275 dump_dcache_range(addr
, size
);
276 rec_dma_start_addr
= addr
;
281 CGU_PERI
|= CGU_I2SIN_APB_CLOCK_ENABLE
|CGU_I2SOUT_APB_CLOCK_ENABLE
;
282 CGU_AUDIO
|= ((1<<23)|(1<<11));
284 I2SOUT_CONTROL
|= 1<<5; /* source = loopback from i2sin fifo */
286 I2SIN_CONTROL
|= (1<<11)|(1<<5); /* enable dma, 14bits samples */
292 void pcm_rec_dma_close(void)
297 void pcm_rec_dma_init(void)
299 int cgu_audio
= CGU_AUDIO
; /* read register */
300 cgu_audio
&= ~(3 << 12); /* clear i2sin MCLK_SEL */
301 cgu_audio
|= (AS3525_MCLK_SEL
<< 12); /* set i2sin MCLK_SEL */
302 cgu_audio
&= ~(0x1ff << 14); /* clear i2sin divider */
303 cgu_audio
|= mclk_divider() << 14; /* set new i2sin divider */
304 CGU_AUDIO
= cgu_audio
; /* write back register */
306 /* i2c clk src = I2SOUTIF, sdata src = AFE,
307 * data valid at positive edge of SCLK */
308 I2SIN_CONTROL
= (1<<2);
312 const void * pcm_rec_dma_get_peak_buffer(void)
314 return UNCACHED_ADDR((void*)DMAC_CH_DST_ADDR(1));
317 #endif /* HAVE_RECORDING */