firmware/target/arm/as3525/pcm-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008-2009 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "audio.h"
  23 #include "string.h"
  24 #include "as3525.h"
  25 #include "pl081.h"
  26 #include "dma-target.h"
  27 #include "clock-target.h"
  28 #include "panic.h"
  29 #include "as3514.h"
  30 #include "audiohw.h"
  31 #include "mmu-arm.h"
  32
  33 #define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA
  34                                       * i.e. 32 bits at once (size of I2SO_DATA)
  35                                       * and the number of 32bits words has to
  36                                       * fit in 11 bits of DMA register */
  37
  38 static unsigned char *dma_start_addr;
  39 static size_t      dma_size;   /* in 4*32 bits */
  40 static void dma_callback(void);
  41 static int locked = 0;
  42
  43 /* Mask the DMA interrupt */
  44 void pcm_play_lock(void)
  45 {
  46     if(++locked == 1)
  47         VIC_INT_EN_CLEAR = INTERRUPT_DMAC;
  48 }
  49
  50 /* Unmask the DMA interrupt if enabled */
  51 void pcm_play_unlock(void)
  52 {
  53     if(--locked == 0)
  54         VIC_INT_ENABLE = INTERRUPT_DMAC;
  55 }
  56
  57 static void play_start_pcm(void)
  58 {
  59     const unsigned char* addr = dma_start_addr;
  60     size_t size = dma_size;
  61     if(size > MAX_TRANSFER)
  62         size = MAX_TRANSFER;
  63
  64     dma_size -= size;
  65     dma_start_addr += size;
  66
  67     clean_dcache_range((void*)addr, size);  /* force write back */
  68     dma_enable_channel(1, (void*)addr, (void*)I2SOUT_DATA, DMA_PERI_I2SOUT,
  69                 DMAC_FLOWCTRL_DMAC_MEM_TO_PERI, true, false, size >> 2, DMA_S1,
  70                 dma_callback);
  71 }
  72
  73 static void dma_callback(void)
  74 {
  75     if(!dma_size)
  76     {
  77         register pcm_more_callback_type get_more = pcm_callback_for_more;
  78         if(get_more)
  79             get_more(&dma_start_addr, &dma_size);
  80     }
  81
  82     if(!dma_size)
  83     {
  84         pcm_play_dma_stop();
  85         pcm_play_dma_stopped_callback();
  86     }
  87     else
  88         play_start_pcm();
  89 }
  90
  91 void pcm_play_dma_start(const void *addr, size_t size)
  92 {
  93     dma_size = size;
  94     dma_start_addr = (unsigned char*)addr;
  95
  96     CGU_PERI |= CGU_I2SOUT_APB_CLOCK_ENABLE;
  97     CGU_AUDIO |= (1<<11);
  98
  99     dma_retain();
 100
 101     play_start_pcm();
 102 }
 103
 104 void pcm_play_dma_stop(void)
 105 {
 106     dma_disable_channel(1);
 107     dma_size = 0;
 108
 109     dma_release();
 110
 111     CGU_PERI &= ~CGU_I2SOUT_APB_CLOCK_ENABLE;
 112     CGU_AUDIO &= ~(1<<11);
 113 }
 114
 115 void pcm_play_dma_pause(bool pause)
 116 {
 117     if(pause)
 118         dma_disable_channel(1);
 119     else
 120         play_start_pcm();
 121 }
 122
 123 void pcm_play_dma_init(void)
 124 {
 125     CGU_PERI |= CGU_I2SOUT_APB_CLOCK_ENABLE;
 126
 127     I2SOUT_CONTROL = (1<<6)|(1<<3)  /* enable dma, stereo */;
 128
 129     audiohw_preinit();
 130 }
 131
 132 void pcm_postinit(void)
 133 {
 134     audiohw_postinit();
 135 }
 136
 137 /* divider is 9 bits but the highest one (for 8kHz) fit in 8 bits */
 138 static const unsigned char divider[SAMPR_NUM_FREQ] = {
 139     [HW_FREQ_96] = ((AS3525_MCLK_FREQ/128 + SAMPR_96/2) / SAMPR_96) - 1,
 140     [HW_FREQ_88] = ((AS3525_MCLK_FREQ/128 + SAMPR_88/2) / SAMPR_88) - 1,
 141     [HW_FREQ_64] = ((AS3525_MCLK_FREQ/128 + SAMPR_64/2) / SAMPR_64) - 1,
 142     [HW_FREQ_48] = ((AS3525_MCLK_FREQ/128 + SAMPR_48/2) / SAMPR_48) - 1,
 143     [HW_FREQ_44] = ((AS3525_MCLK_FREQ/128 + SAMPR_44/2) / SAMPR_44) - 1,
 144     [HW_FREQ_32] = ((AS3525_MCLK_FREQ/128 + SAMPR_32/2) / SAMPR_32) - 1,
 145     [HW_FREQ_24] = ((AS3525_MCLK_FREQ/128 + SAMPR_24/2) / SAMPR_24) - 1,
 146     [HW_FREQ_22] = ((AS3525_MCLK_FREQ/128 + SAMPR_22/2) / SAMPR_22) - 1,
 147     [HW_FREQ_16] = ((AS3525_MCLK_FREQ/128 + SAMPR_16/2) / SAMPR_16) - 1,
 148     [HW_FREQ_12] = ((AS3525_MCLK_FREQ/128 + SAMPR_12/2) / SAMPR_12) - 1,
 149     [HW_FREQ_11] = ((AS3525_MCLK_FREQ/128 + SAMPR_11/2) / SAMPR_11) - 1,
 150     [HW_FREQ_8 ] = ((AS3525_MCLK_FREQ/128 + SAMPR_8 /2) / SAMPR_8 ) - 1,
 151 };
 152
 153 static inline unsigned char mclk_divider(void)
 154 {
 155     return divider[pcm_fsel];
 156 }
 157
 158 void pcm_dma_apply_settings(void)
 159 {
 160     int cgu_audio = CGU_AUDIO;              /* read register */
 161     cgu_audio &= ~(3 << 0);                 /* clear i2sout MCLK_SEL */
 162     cgu_audio |=  (AS3525_MCLK_SEL << 0);   /* set i2sout MCLK_SEL */
 163     cgu_audio &= ~(0x1ff << 2);             /* clear i2sout divider */
 164     cgu_audio |= mclk_divider() << 2;       /* set new i2sout divider */
 165     CGU_AUDIO = cgu_audio;                  /* write back register */
 166 }
 167
 168 size_t pcm_get_bytes_waiting(void)
 169 {
 170     return dma_size;
 171 }
 172
 173 const void * pcm_play_dma_get_peak_buffer(int *count)
 174 {
 175     *count = dma_size >> 2;
 176     return (const void*)dma_start_addr;
 177 }
 178
 179 #ifdef HAVE_PCM_DMA_ADDRESS
 180 void * pcm_dma_addr(void *addr)
 181 {
 182     if (addr != NULL)
 183         addr = UNCACHED_ADDR(addr);
 184     return addr;
 185 }
 186 #endif
 187
 188
 189 /****************************************************************************
 190  ** Recording DMA transfer
 191  **/
 192 #ifdef HAVE_RECORDING
 193
 194 static int rec_locked = 0;
 195 static unsigned char *rec_dma_start_addr;
 196 static size_t rec_dma_size;
 197 static void rec_dma_callback(void);
 198
 199
 200 void pcm_rec_lock(void)
 201 {
 202     if(++rec_locked == 1)
 203         VIC_INT_EN_CLEAR = INTERRUPT_DMAC;
 204 }
 205
 206
 207 void pcm_rec_unlock(void)
 208 {
 209     if(--rec_locked == 0)
 210         VIC_INT_ENABLE = INTERRUPT_DMAC;
 211 }
 212
 213
 214 static void rec_dma_start(void)
 215 {
 216     void* addr = rec_dma_start_addr;
 217     size_t size = rec_dma_size;
 218
 219     /* We are limited to 8188 DMA transfers, and the recording core asks for
 220      * 8192 bytes. Avoid splitting 8192 bytes transfers in 8188 + 4 */
 221     if(size > 4096)
 222         size = 4096;
 223
 224     rec_dma_size -= size;
 225     rec_dma_start_addr += size;
 226
 227     dma_enable_channel(1, (void*)I2SIN_DATA, addr, DMA_PERI_I2SIN,
 228                 DMAC_FLOWCTRL_DMAC_PERI_TO_MEM, false, true, size >> 2, DMA_S4,
 229                 rec_dma_callback);
 230 }
 231
 232
 233 static void rec_dma_callback(void)
 234 {
 235     if(!rec_dma_size)
 236     {
 237         register pcm_more_callback_type2 more_ready = pcm_callback_more_ready;
 238         if (!more_ready || more_ready(0) < 0)
 239         {
 240             /* Finished recording */
 241             pcm_rec_dma_stop();
 242             pcm_rec_dma_stopped_callback();
 243             return;
 244         }
 245     }
 246
 247     rec_dma_start();
 248 }
 249
 250
 251 void pcm_rec_dma_record_more(void *start, size_t size)
 252 {
 253     dump_dcache_range(start, size);
 254     rec_dma_start_addr = start;
 255     rec_dma_size = size;
 256 }
 257
 258
 259 void pcm_rec_dma_stop(void)
 260 {
 261     dma_disable_channel(1);
 262     rec_dma_size = 0;
 263     dma_release();
 264
 265     I2SOUT_CONTROL &= ~(1<<5); /* source = i2soutif fifo */
 266     I2SIN_CONTROL &= ~(1<<11); /* disable dma */
 267
 268     CGU_AUDIO &= ~((1<<23)|(1<<11));
 269     CGU_PERI &= ~(CGU_I2SIN_APB_CLOCK_ENABLE|CGU_I2SOUT_APB_CLOCK_ENABLE);
 270 }
 271
 272
 273 void pcm_rec_dma_start(void *addr, size_t size)
 274 {
 275     dump_dcache_range(addr, size);
 276     rec_dma_start_addr = addr;
 277     rec_dma_size = size;
 278
 279     dma_retain();
 280
 281     CGU_PERI |= CGU_I2SIN_APB_CLOCK_ENABLE|CGU_I2SOUT_APB_CLOCK_ENABLE;
 282     CGU_AUDIO |= ((1<<23)|(1<<11));
 283
 284     I2SOUT_CONTROL |= 1<<5; /* source = loopback from i2sin fifo */
 285
 286     I2SIN_CONTROL |= (1<<11)|(1<<5); /* enable dma, 14bits samples */
 287
 288     rec_dma_start();
 289 }
 290
 291
 292 void pcm_rec_dma_close(void)
 293 {
 294 }
 295
 296
 297 void pcm_rec_dma_init(void)
 298 {
 299     int cgu_audio = CGU_AUDIO;              /* read register */
 300     cgu_audio &= ~(3 << 12);                /* clear i2sin MCLK_SEL */
 301     cgu_audio |=  (AS3525_MCLK_SEL << 12);  /* set i2sin MCLK_SEL */
 302     cgu_audio &= ~(0x1ff << 14);            /* clear i2sin divider */
 303     cgu_audio |= mclk_divider() << 14;      /* set new i2sin divider */
 304     CGU_AUDIO = cgu_audio;                  /* write back register */
 305
 306     /* i2c clk src = I2SOUTIF, sdata src = AFE,
 307      * data valid at positive edge of SCLK */
 308     I2SIN_CONTROL = (1<<2);
 309 }
 310
 311
 312 const void * pcm_rec_dma_get_peak_buffer(void)
 313 {
 314     return rec_dma_start_addr;
 315 }
 316
 317 #endif /* HAVE_RECORDING */