firmware/target/arm/as3525/pcm-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2008-2009 Rafaël Carré
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "audio.h"
  23 #include "string.h"
  24 #include "as3525.h"
  25 #include "pl081.h"
  26 #include "dma-target.h"
  27 #include "clock-target.h"
  28 #include "panic.h"
  29 #include "as3514.h"
  30 #include "audiohw.h"
  31 #include "mmu-arm.h"
  32
  33 #define MAX_TRANSFER (4*((1<<11)-1)) /* maximum data we can transfer via DMA
  34                                       * i.e. 32 bits at once (size of I2SO_DATA)
  35                                       * and the number of 32bits words has to
  36                                       * fit in 11 bits of DMA register */
  37
  38 static unsigned char *dma_start_addr;
  39 static size_t      dma_size;   /* in 4*32 bits */
  40 static void dma_callback(void);
  41 static int locked = 0;
  42
  43 /* Mask the DMA interrupt */
  44 void pcm_play_lock(void)
  45 {
  46     if(++locked == 1)
  47         VIC_INT_EN_CLEAR = INTERRUPT_DMAC;
  48 }
  49
  50 /* Unmask the DMA interrupt if enabled */
  51 void pcm_play_unlock(void)
  52 {
  53     if(--locked == 0)
  54         VIC_INT_ENABLE = INTERRUPT_DMAC;
  55 }
  56
  57 static void play_start_pcm(void)
  58 {
  59     const unsigned char* addr = dma_start_addr;
  60     size_t size = dma_size;
  61     if(size > MAX_TRANSFER)
  62         size = MAX_TRANSFER;
  63
  64     dma_size -= size;
  65     dma_start_addr += size;
  66
  67     clean_dcache_range((void*)addr, size);  /* force write back */
  68     dma_enable_channel(1, (void*)addr, (void*)I2SOUT_DATA, DMA_PERI_I2SOUT,
  69                 DMAC_FLOWCTRL_DMAC_MEM_TO_PERI, true, false, size >> 2, DMA_S1,
  70                 dma_callback);
  71 }
  72
  73 static void dma_callback(void)
  74 {
  75     if(!dma_size)
  76     {
  77         register pcm_more_callback_type get_more = pcm_callback_for_more;
  78         if(get_more)
  79             get_more(&dma_start_addr, &dma_size);
  80     }
  81
  82     if(!dma_size)
  83     {
  84         pcm_play_dma_stop();
  85         pcm_play_dma_stopped_callback();
  86     }
  87     else
  88         play_start_pcm();
  89 }
  90
  91 void pcm_play_dma_start(const void *addr, size_t size)
  92 {
  93     dma_size = size;
  94     dma_start_addr = (unsigned char*)addr;
  95
  96     CGU_PERI |= CGU_I2SOUT_APB_CLOCK_ENABLE;
  97     CGU_AUDIO |= (1<<11);
  98
  99     dma_retain();
 100
 101     play_start_pcm();
 102 }
 103
 104 void pcm_play_dma_stop(void)
 105 {
 106     dma_disable_channel(1);
 107     dma_size = 0;
 108
 109     dma_release();
 110
 111     CGU_PERI &= ~CGU_I2SOUT_APB_CLOCK_ENABLE;
 112     CGU_AUDIO &= ~(1<<11);
 113 }
 114
 115 void pcm_play_dma_pause(bool pause)
 116 {
 117     if(pause)
 118         dma_disable_channel(1);
 119     else
 120         play_start_pcm();
 121 }
 122
 123 void pcm_play_dma_init(void)
 124 {
 125     CGU_PERI |= CGU_I2SOUT_APB_CLOCK_ENABLE;
 126
 127     I2SOUT_CONTROL = (1<<6)|(1<<3)  /* enable dma, stereo */;
 128
 129     audiohw_preinit();
 130 }
 131
 132 void pcm_postinit(void)
 133 {
 134     audiohw_postinit();
 135 }
 136
 137 static unsigned mclk_divider(void)
 138 {
 139     /* TODO : use a table ? */
 140     return (((AS3525_MCLK_FREQ/128) + (pcm_sampr/2)) / pcm_sampr) - 1;
 141 }
 142
 143 void pcm_dma_apply_settings(void)
 144 {
 145     int cgu_audio = CGU_AUDIO;  /* read register */
 146     cgu_audio &= ~(3 << 0);     /* clear i2sout MCLK_SEL */
 147     cgu_audio |=  (AS3525_MCLK_SEL << 0);  /* set i2sout MCLK_SEL */
 148     cgu_audio &= ~(511 << 2);   /* clear i2sout divider */
 149     cgu_audio |= mclk_divider() << 2; /* set new i2sout divider */
 150     CGU_AUDIO = cgu_audio;      /* write back register */
 151 }
 152
 153 size_t pcm_get_bytes_waiting(void)
 154 {
 155     return dma_size;
 156 }
 157
 158 const void * pcm_play_dma_get_peak_buffer(int *count)
 159 {
 160     *count = dma_size >> 2;
 161     return (const void*)dma_start_addr;
 162 }
 163
 164 #ifdef HAVE_PCM_DMA_ADDRESS
 165 void * pcm_dma_addr(void *addr)
 166 {
 167     if (addr != NULL)
 168         addr = UNCACHED_ADDR(addr);
 169     return addr;
 170 }
 171 #endif
 172
 173
 174 /****************************************************************************
 175  ** Recording DMA transfer
 176  **/
 177 #ifdef HAVE_RECORDING
 178
 179 static int rec_locked = 0;
 180 static unsigned char *rec_dma_start_addr;
 181 static size_t rec_dma_size;
 182 static void rec_dma_callback(void);
 183
 184
 185 void pcm_rec_lock(void)
 186 {
 187     if(++rec_locked == 1)
 188         VIC_INT_EN_CLEAR = INTERRUPT_DMAC;
 189 }
 190
 191
 192 void pcm_rec_unlock(void)
 193 {
 194     if(--rec_locked == 0)
 195         VIC_INT_ENABLE = INTERRUPT_DMAC;
 196 }
 197
 198
 199 static void rec_dma_start(void)
 200 {
 201     void* addr = rec_dma_start_addr;
 202     size_t size = rec_dma_size;
 203
 204     /* We are limited to 8188 DMA transfers, and the recording core asks for
 205      * 8192 bytes. Avoid splitting 8192 bytes transfers in 8188 + 4 */
 206     if(size > 4096)
 207         size = 4096;
 208
 209     rec_dma_size -= size;
 210     rec_dma_start_addr += size;
 211
 212     dma_enable_channel(1, (void*)I2SIN_DATA, addr, DMA_PERI_I2SIN,
 213                 DMAC_FLOWCTRL_DMAC_PERI_TO_MEM, false, true, size >> 2, DMA_S4,
 214                 rec_dma_callback);
 215 }
 216
 217
 218 static void rec_dma_callback(void)
 219 {
 220     if(!rec_dma_size)
 221     {
 222         register pcm_more_callback_type2 more_ready = pcm_callback_more_ready;
 223         if (!more_ready || more_ready(0) < 0)
 224         {
 225             /* Finished recording */
 226             pcm_rec_dma_stop();
 227             pcm_rec_dma_stopped_callback();
 228             return;
 229         }
 230     }
 231
 232     rec_dma_start();
 233 }
 234
 235
 236 void pcm_rec_dma_record_more(void *start, size_t size)
 237 {
 238     dump_dcache_range(start, size);
 239     rec_dma_start_addr = start;
 240     rec_dma_size = size;
 241 }
 242
 243
 244 void pcm_rec_dma_stop(void)
 245 {
 246     dma_disable_channel(1);
 247     rec_dma_size = 0;
 248     dma_release();
 249
 250     I2SOUT_CONTROL &= ~(1<<5); /* source = i2soutif fifo */
 251     I2SIN_CONTROL &= ~(1<<11); /* disable dma */
 252
 253     CGU_AUDIO &= ~((1<<23)|(1<<11));
 254     CGU_PERI &= ~(CGU_I2SIN_APB_CLOCK_ENABLE|CGU_I2SOUT_APB_CLOCK_ENABLE);
 255 }
 256
 257
 258 void pcm_rec_dma_start(void *addr, size_t size)
 259 {
 260     dump_dcache_range(addr, size);
 261     rec_dma_start_addr = addr;
 262     rec_dma_size = size;
 263
 264     dma_retain();
 265
 266     CGU_PERI |= CGU_I2SIN_APB_CLOCK_ENABLE|CGU_I2SOUT_APB_CLOCK_ENABLE;
 267     CGU_AUDIO |= ((1<<23)|(1<<11));
 268
 269     I2SOUT_CONTROL |= 1<<5; /* source = loopback from i2sin fifo */
 270
 271     I2SIN_CONTROL |= (1<<11)|(1<<5); /* enable dma, 14bits samples */
 272
 273     rec_dma_start();
 274 }
 275
 276
 277 void pcm_rec_dma_close(void)
 278 {
 279 }
 280
 281
 282 void pcm_rec_dma_init(void)
 283 {
 284     int cgu_audio = CGU_AUDIO;  /* read register */
 285     cgu_audio &= ~(3 << 12);    /* clear i2sin MCLK_SEL */
 286     cgu_audio |=  (AS3525_MCLK_SEL << 12);  /* set i2sin MCLK_SEL */
 287     cgu_audio &= ~(511 << 14);  /* clear i2sin divider */
 288     cgu_audio |= mclk_divider() << 14; /* set new i2sin divider */
 289     CGU_AUDIO = cgu_audio;      /* write back register */
 290
 291     /* i2c clk src = I2SOUTIF, sdata src = AFE,
 292      * data valid at positive edge of SCLK */
 293     I2SIN_CONTROL = (1<<2);
 294 }
 295
 296
 297 const void * pcm_rec_dma_get_peak_buffer(void)
 298 {
 299     return rec_dma_start_addr;
 300 }
 301
 302 #endif /* HAVE_RECORDING */