firmware/target/arm/as3525/sd-as3525.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
  24
  25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
  26 #include "fat.h"
  27 #include "thread.h"
  28 #include "led.h"
  29 #include "sdmmc.h"
  30 #include "system.h"
  31 #include "cpu.h"
  32 #include <stdio.h>
  33 #include <stdlib.h>
  34 #include <string.h>
  35 #include "as3525.h"
  36 #include "pl180.h"  /* SD controller */
  37 #include "pl081.h"  /* DMA controller */
  38 #include "dma-target.h" /* DMA request lines */
  39 #include "clock-target.h"
  40 #include "panic.h"
  41 #ifdef HAVE_BUTTON_LIGHT
  42 #include "backlight-target.h"
  43 #endif
  44 #include "stdbool.h"
  45 #include "ata_idle_notify.h"
  46 #include "sd.h"
  47 #include "usb.h"
  48
  49 #ifdef HAVE_HOTSWAP
  50 #include "disk.h"
  51 #endif
  52
  53 #define VERIFY_WRITE 1
  54
  55 /* command flags */
  56 #define MCI_NO_RESP     (0<<0)
  57 #define MCI_RESP        (1<<0)
  58 #define MCI_LONG_RESP   (1<<1)
  59
  60 /* ARM PL180 registers */
  61 #define MCI_POWER(i)       (*(volatile unsigned char *) (pl180_base[i]+0x00))
  62 #define MCI_CLOCK(i)       (*(volatile unsigned long *) (pl180_base[i]+0x04))
  63 #define MCI_ARGUMENT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x08))
  64 #define MCI_COMMAND(i)     (*(volatile unsigned long *) (pl180_base[i]+0x0C))
  65 #define MCI_RESPCMD(i)     (*(volatile unsigned long *) (pl180_base[i]+0x10))
  66 #define MCI_RESP0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x14))
  67 #define MCI_RESP1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x18))
  68 #define MCI_RESP2(i)       (*(volatile unsigned long *) (pl180_base[i]+0x1C))
  69 #define MCI_RESP3(i)       (*(volatile unsigned long *) (pl180_base[i]+0x20))
  70 #define MCI_DATA_TIMER(i)  (*(volatile unsigned long *) (pl180_base[i]+0x24))
  71 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
  72 #define MCI_DATA_CTRL(i)   (*(volatile unsigned char *) (pl180_base[i]+0x2C))
  73 #define MCI_DATA_CNT(i)    (*(volatile unsigned short*) (pl180_base[i]+0x30))
  74 #define MCI_STATUS(i)      (*(volatile unsigned long *) (pl180_base[i]+0x34))
  75 #define MCI_CLEAR(i)       (*(volatile unsigned long *) (pl180_base[i]+0x38))
  76 #define MCI_MASK0(i)       (*(volatile unsigned long *) (pl180_base[i]+0x3C))
  77 #define MCI_MASK1(i)       (*(volatile unsigned long *) (pl180_base[i]+0x40))
  78 #define MCI_SELECT(i)      (*(volatile unsigned long *) (pl180_base[i]+0x44))
  79 #define MCI_FIFO_CNT(i)    (*(volatile unsigned long *) (pl180_base[i]+0x48))
  80
  81 #define MCI_DATA_ERROR    \
  82     ( MCI_DATA_CRC_FAIL   \
  83     | MCI_DATA_TIMEOUT    \
  84     | MCI_TX_UNDERRUN     \
  85     | MCI_RX_OVERRUN      \
  86     | MCI_START_BIT_ERR)
  87
  88 #define MCI_RESPONSE_ERROR    \
  89     ( MCI_CMD_TIMEOUT         \
  90     | MCI_CMD_CRC_FAIL)
  91
  92 #define MCI_FIFO(i)        ((unsigned long *) (pl180_base[i]+0x80))
  93 /* volumes */
  94 #define     INTERNAL_AS3525 0   /* embedded SD card */
  95 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  96
  97 static const int pl180_base[NUM_DRIVES] = {
  98             NAND_FLASH_BASE
  99 #ifdef HAVE_MULTIDRIVE
 100             , SD_MCI_BASE
 101 #endif
 102 };
 103
 104 static int sd_wait_for_tran_state(const int drive);
 105 static int sd_select_bank(signed char bank);
 106 static int sd_init_card(const int drive);
 107 static void init_pl180_controller(const int drive);
 108
 109 #define BLOCKS_PER_BANK 0x7a7800u
 110
 111 static tCardInfo card_info[NUM_DRIVES];
 112
 113 /* maximum timeouts recommanded in the SD Specification v2.00 */
 114 #define SD_MAX_READ_TIMEOUT     ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
 115 #define SD_MAX_WRITE_TIMEOUT    ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
 116
 117 /* for compatibility */
 118 static long last_disk_activity = -1;
 119
 120 #define MIN_YIELD_PERIOD 5  /* ticks */
 121 static long next_yield = 0;
 122
 123 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 124 static const char         sd_thread_name[] = "ata/sd";
 125 static struct mutex       sd_mtx;
 126 static struct event_queue sd_queue;
 127 bool sd_enabled = false;
 128
 129 #if defined(HAVE_MULTIDRIVE)
 130 static bool hs_card = false;
 131 #define EXT_SD_BITS (1<<2)
 132 #endif
 133
 134 static struct wakeup transfer_completion_signal;
 135 static volatile unsigned int transfer_error[NUM_VOLUMES];
 136 #define PL180_MAX_TRANSFER_ERRORS 10
 137
 138 #define UNALIGNED_NUM_SECTORS 10
 139 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 140 static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0]);
 141
 142
 143 static inline void mci_delay(void) { udelay(1000) ; }
 144
 145
 146 static inline bool card_detect_target(void)
 147 {
 148 #if defined(HAVE_MULTIDRIVE)
 149     return !(GPIOA_PIN(2));
 150 #else
 151     return false;
 152 #endif
 153 }
 154
 155
 156 #ifdef HAVE_HOTSWAP
 157 static int sd1_oneshot_callback(struct timeout *tmo)
 158 {
 159     (void)tmo;
 160
 161     /* This is called only if the state was stable for 300ms - check state
 162      * and post appropriate event. */
 163     if (card_detect_target())
 164     {
 165         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 166     }
 167     else
 168         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 169
 170     return 0;
 171 }
 172
 173 void sd_gpioa_isr(void)
 174 {
 175     static struct timeout sd1_oneshot;
 176     if (GPIOA_MIS & EXT_SD_BITS)
 177         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
 178     /* acknowledge interrupt */
 179     GPIOA_IC = EXT_SD_BITS;
 180 }
 181 #endif  /* HAVE_HOTSWAP */
 182
 183 void INT_NAND(void)
 184 {
 185     const int status = MCI_STATUS(INTERNAL_AS3525);
 186
 187     transfer_error[INTERNAL_AS3525] = status & MCI_DATA_ERROR;
 188
 189     wakeup_signal(&transfer_completion_signal);
 190     MCI_CLEAR(INTERNAL_AS3525) = status;
 191 }
 192
 193 #ifdef HAVE_MULTIDRIVE
 194 void INT_MCI0(void)
 195 {
 196     const int status = MCI_STATUS(SD_SLOT_AS3525);
 197
 198     transfer_error[SD_SLOT_AS3525] = status & MCI_DATA_ERROR;
 199
 200     wakeup_signal(&transfer_completion_signal);
 201     MCI_CLEAR(SD_SLOT_AS3525) = status;
 202 }
 203 #endif
 204
 205 static bool send_cmd(const int drive, const int cmd, const int arg,
 206                      const int flags, long *response)
 207 {
 208     int status;
 209
 210     unsigned cmd_retries = 6;
 211     while(cmd_retries--)
 212     {
 213         /* Clear old status flags */
 214         MCI_CLEAR(drive) = 0x7ff;
 215
 216         /* Load command argument or clear if none */
 217         MCI_ARGUMENT(drive) = arg;
 218
 219         /* Construct MCI_COMMAND & enable CPSM */
 220         MCI_COMMAND(drive) =
 221            /*b0:5*/  cmd
 222            /* b6 */| ((flags & (MCI_RESP|MCI_LONG_RESP)) ? MCI_COMMAND_RESPONSE : 0)
 223            /* b7 */| ((flags & MCI_LONG_RESP) ? MCI_COMMAND_LONG_RESPONSE : 0)
 224            /* b8   | MCI_COMMAND_INTERRUPT */
 225            /* b9   | MCI_COMMAND_PENDING */  /*Only used with stream data transfer*/
 226            /* b10*/| MCI_COMMAND_ENABLE;     /* Enables CPSM */
 227
 228         /* Wait while cmd completes then disable CPSM */
 229         while(MCI_STATUS(drive) & MCI_CMD_ACTIVE);
 230         MCI_COMMAND(drive) = 0;
 231
 232         status = MCI_STATUS(drive);
 233
 234         /*  Handle command responses */
 235         if(flags & MCI_RESP)                /* CMD expects response */
 236         {
 237             response[0] = MCI_RESP0(drive); /* Always prepare short response */
 238
 239             if(status & MCI_RESPONSE_ERROR) /* timeout or crc failure */
 240                 continue;
 241
 242             if(status & MCI_CMD_RESP_END)   /* Response passed CRC check */
 243             {
 244                 if(flags & MCI_LONG_RESP)
 245                 {   /* response[0] has already been read */
 246                     response[1] = MCI_RESP1(drive);
 247                     response[2] = MCI_RESP2(drive);
 248                     response[3] = MCI_RESP3(drive);
 249                 }
 250                 return true;
 251             }
 252         }
 253         else if(status & MCI_CMD_SENT)  /* CMD sent, no response required */
 254             return true;
 255     }
 256
 257     return false;
 258 }
 259
 260 #define MCI_FULLSPEED     (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS)     /* MCLK   */
 261 #define MCI_HALFSPEED     (MCI_CLOCK_ENABLE)                        /* MCLK/2 */
 262 #define MCI_QUARTERSPEED  (MCI_CLOCK_ENABLE | 1)                    /* MCLK/4 */
 263 #define MCI_IDENTSPEED    (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV)  /* IDENT  */
 264
 265 static int sd_init_card(const int drive)
 266 {
 267     unsigned long response;
 268     long init_timeout;
 269     bool sd_v2 = false;
 270
 271     /* MCLCK on and set to 400kHz ident frequency  */
 272     MCI_CLOCK(drive) = MCI_IDENTSPEED;
 273
 274     /* 100 - 400kHz clock required for Identification Mode  */
 275     /*  Start of Card Identification Mode ************************************/
 276
 277     /* CMD0 Go Idle  */
 278     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 279         return -1;
 280     mci_delay();
 281
 282     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 283       Non v2 cards will not respond to this command*/
 284     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 285         if((response & 0xFFF) == 0x1AA)
 286             sd_v2 = true;
 287
 288     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 289     init_timeout = current_tick + HZ;
 290
 291     do {
 292         /* this timeout is the only valid error for this loop*/
 293         if(TIME_AFTER(current_tick, init_timeout))
 294             return -2;
 295
 296         /* app_cmd */
 297         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 298
 299         /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 300         send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 301                         MCI_RESP, &card_info[drive].ocr);
 302
 303     } while(!(card_info[drive].ocr & (1<<31)));
 304
 305     /* CMD2 send CID */
 306     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP,
 307                             card_info[drive].cid))
 308         return -3;
 309
 310     /* CMD3 send RCA */
 311     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP,
 312                 &card_info[drive].rca))
 313         return -4;
 314
 315     /*  End of Card Identification Mode   ************************************/
 316
 317 #ifdef HAVE_MULTIDRIVE        /*  The internal SDs are v1 */
 318
 319     /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
 320     if(sd_v2)
 321     {
 322         /*  CMD7 w/rca: Select card to put it in TRAN state */
 323         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 324             return -5;
 325
 326         if(sd_wait_for_tran_state(drive))
 327             return -6;
 328         /* CMD6 */
 329         if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 330             return -7;
 331         mci_delay();
 332
 333         /*  go back to STBY state so we can read csd */
 334         /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 335         if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 336             return -8;
 337         mci_delay();
 338     }
 339 #endif /*  HAVE_MULTIDRIVE  */
 340
 341     /* CMD9 send CSD */
 342     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 343                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 344         return -9;
 345
 346     sd_parse_csd(&card_info[drive]);
 347
 348 #if defined(HAVE_MULTIDRIVE)
 349     hs_card = (card_info[drive].speed == 50000000);
 350 #endif
 351
 352     /* Boost MCICLK to operating speed */
 353     if(drive == INTERNAL_AS3525)
 354         MCI_CLOCK(drive) = MCI_HALFSPEED;  /* MCICLK = IDE_CLK/2 = 25 MHz  */
 355 #if defined(HAVE_MULTIDRIVE)
 356     else
 357         /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
 358         MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
 359 #endif
 360
 361     /*  CMD7 w/rca: Select card to put it in TRAN state */
 362     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 363         return -10;
 364
 365     /*  Switch to to 4 bit widebus mode  */
 366     if(sd_wait_for_tran_state(drive) < 0)
 367         return -11;
 368     /* CMD55 */             /*  Response is requested due to timing issue  */
 369     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 370         return -14;
 371     /* ACMD42  */
 372     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_RESP, &response))
 373         return -15;
 374     /* CMD55 */              /*  Response is requested due to timing issue  */
 375     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 376         return -12;
 377     /* ACMD6  */
 378     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_RESP, &response))
 379         return -13;
 380     /* Now that card is widebus make controller aware */
 381     MCI_CLOCK(drive) |= MCI_CLOCK_WIDEBUS;
 382
 383     /*
 384      * enable bank switching
 385      * without issuing this command, we only have access to 1/4 of the blocks
 386      * of the first bank (0x1E9E00 blocks, which is the size reported in the
 387      * CSD register)
 388      */
 389     if(drive == INTERNAL_AS3525)
 390     {
 391         const int ret = sd_select_bank(-1);
 392         if(ret < 0)
 393             return ret -16;
 394
 395         /*  CMD7 w/rca = 0: Unselect card to put it in STBY state */
 396         if(!send_cmd(drive, SD_SELECT_CARD, 0, MCI_NO_RESP, NULL))
 397             return -17;
 398         mci_delay();
 399
 400         /* CMD9 send CSD again, so we got the correct number of blocks */
 401         if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 402                      MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 403             return -18;
 404
 405         sd_parse_csd(&card_info[drive]);
 406         /* The OF is stored in the first blocks */
 407         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 408
 409         /*  CMD7 w/rca: Select card to put it in TRAN state */
 410         if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_RESP, &response))
 411             return -19;
 412     }
 413
 414     card_info[drive].initialized = 1;
 415
 416     return 0;
 417 }
 418
 419 static void sd_thread(void) __attribute__((noreturn));
 420 static void sd_thread(void)
 421 {
 422     struct queue_event ev;
 423     bool idle_notified = false;
 424
 425     while (1)
 426     {
 427         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 428
 429         switch ( ev.id )
 430         {
 431 #ifdef HAVE_HOTSWAP
 432         case SYS_HOTSWAP_INSERTED:
 433         case SYS_HOTSWAP_EXTRACTED:
 434         {
 435             int microsd_init = 1;
 436             fat_lock();          /* lock-out FAT activity first -
 437                                     prevent deadlocking via disk_mount that
 438                                     would cause a reverse-order attempt with
 439                                     another thread */
 440             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 441                                     into driver that bypass the fat cache */
 442
 443             /* We now have exclusive control of fat cache and ata */
 444
 445             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 446                                     descriptors aren't leaked and any busy
 447                                     ones are invalid if mounting */
 448
 449             /* Force card init for new card, re-init for re-inserted one or
 450              * clear if the last attempt to init failed with an error. */
 451             card_info[SD_SLOT_AS3525].initialized = 0;
 452
 453             if (ev.id == SYS_HOTSWAP_INSERTED)
 454             {
 455                 sd_enable(true);
 456                 init_pl180_controller(SD_SLOT_AS3525);
 457                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 458                 if (microsd_init < 0) /* initialisation failed */
 459                     panicf("microSD init failed : %d", microsd_init);
 460
 461                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 462             }
 463
 464             /*
 465              * Mount succeeded, or this was an EXTRACTED event,
 466              * in both cases notify the system about the changed filesystems
 467              */
 468             if (microsd_init)
 469                 queue_broadcast(SYS_FS_CHANGED, 0);
 470
 471             /* Access is now safe */
 472             mutex_unlock(&sd_mtx);
 473             fat_unlock();
 474             sd_enable(false);
 475         }
 476             break;
 477 #endif
 478         case SYS_TIMEOUT:
 479             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 480             {
 481                 idle_notified = false;
 482             }
 483             else
 484             {
 485                 /* never let a timer wrap confuse us */
 486                 next_yield = current_tick;
 487
 488                 if (!idle_notified)
 489                 {
 490                     call_storage_idle_notifys(false);
 491                     idle_notified = true;
 492                 }
 493             }
 494             break;
 495
 496         case SYS_USB_CONNECTED:
 497             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 498             /* Wait until the USB cable is extracted again */
 499             usb_wait_for_disconnect(&sd_queue);
 500
 501             break;
 502         case SYS_USB_DISCONNECTED:
 503             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 504             break;
 505         }
 506     }
 507 }
 508
 509 static void init_pl180_controller(const int drive)
 510 {
 511     MCI_COMMAND(drive) = MCI_DATA_CTRL(drive) = 0;
 512     MCI_CLEAR(drive) = 0x7ff;
 513
 514     MCI_MASK0(drive) = MCI_DATA_ERROR | MCI_DATA_END;
 515     MCI_MASK1(drive) = 0;
 516 #ifdef HAVE_MULTIDRIVE
 517     VIC_INT_ENABLE =
 518         (drive == INTERNAL_AS3525) ? INTERRUPT_NAND : INTERRUPT_MCI0;
 519     /* clear previous irq */
 520     GPIOA_IC = EXT_SD_BITS;
 521     /* enable edge detecting */
 522     GPIOA_IS &= ~EXT_SD_BITS;
 523     /* detect both raising and falling edges */
 524     GPIOA_IBE |= EXT_SD_BITS;
 525     /* enable the card detect interrupt */
 526     GPIOA_IE |= EXT_SD_BITS;
 527
 528 #else
 529     VIC_INT_ENABLE = INTERRUPT_NAND;
 530 #endif
 531
 532     MCI_POWER(drive) = MCI_POWER_UP | (MCI_VDD_3_0);  /*  OF Setting  */
 533     mci_delay();
 534
 535     MCI_POWER(drive) |= MCI_POWER_ON;
 536     mci_delay();
 537
 538     MCI_SELECT(drive) = 0;
 539
 540     /* Pl180 clocks get turned on at start of card init */
 541 }
 542
 543 int sd_init(void)
 544 {
 545     int ret;
 546     CGU_IDE =   (1<<6)                  /*  enable non AHB interface*/
 547             |   (AS3525_IDE_DIV << 2)
 548             |    AS3525_CLK_PLLA;       /* clock source = PLLA */
 549
 550     CGU_PERI |= CGU_NAF_CLOCK_ENABLE;
 551 #ifdef HAVE_MULTIDRIVE
 552     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 553     CCU_IO &= ~(1<<3);           /* bits 3:2 = 01, xpd is SD interface */
 554     CCU_IO |= (1<<2);
 555 #endif
 556
 557     wakeup_init(&transfer_completion_signal);
 558
 559     init_pl180_controller(INTERNAL_AS3525);
 560     ret = sd_init_card(INTERNAL_AS3525);
 561     if(ret < 0)
 562         return ret;
 563 #ifdef HAVE_MULTIDRIVE
 564     init_pl180_controller(SD_SLOT_AS3525);
 565 #endif
 566
 567     /* init mutex */
 568     mutex_init(&sd_mtx);
 569
 570     queue_init(&sd_queue, true);
 571     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 572             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 573
 574     sd_enabled = true;
 575     sd_enable(false);
 576
 577     return 0;
 578 }
 579
 580 #ifdef HAVE_HOTSWAP
 581 bool sd_removable(IF_MD_NONVOID(int drive))
 582 {
 583     return (drive==1);
 584 }
 585
 586 bool sd_present(IF_MD_NONVOID(int drive))
 587 {
 588     return (drive == 0) ? true : card_detect_target();
 589 }
 590 #endif /* HAVE_HOTSWAP */
 591
 592 static int sd_wait_for_tran_state(const int drive)
 593 {
 594     unsigned long response = 0;
 595     unsigned int timeout = current_tick + 5 * HZ;
 596
 597     while (1)
 598     {
 599         if(!send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP,
 600                     &response))
 601             return -1;
 602
 603         if (((response >> 9) & 0xf) == SD_TRAN)
 604             return 0;
 605
 606         if(TIME_AFTER(current_tick, timeout))
 607             return -2;
 608
 609         if (TIME_AFTER(current_tick, next_yield))
 610         {
 611             yield();
 612             next_yield = current_tick + MIN_YIELD_PERIOD;
 613         }
 614     }
 615 }
 616
 617 static int sd_select_bank(signed char bank)
 618 {
 619     int ret;
 620     unsigned loops = 0;
 621
 622     memset(uncached_buffer, 0, 512);
 623     if(bank == -1)
 624     {   /* enable bank switching */
 625         uncached_buffer[0] = 16;
 626         uncached_buffer[1] = 1;
 627         uncached_buffer[2] = 10;
 628     }
 629     else
 630         uncached_buffer[0] = bank;
 631
 632     do {
 633         if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 634             panicf("SD bank %d error : 0x%x", bank,
 635                     transfer_error[INTERNAL_AS3525]);
 636
 637         ret = sd_wait_for_tran_state(INTERNAL_AS3525);
 638         if (ret < 0)
 639             return ret - 2;
 640
 641         if(!send_cmd(INTERNAL_AS3525, SD_SWITCH_FUNC, 0x80ffffef, MCI_NO_RESP,
 642                      NULL))
 643             return -1;
 644
 645         mci_delay();
 646
 647         if(!send_cmd(INTERNAL_AS3525, 35, 0, MCI_NO_RESP, NULL))
 648             return -2;
 649
 650         mci_delay();
 651
 652         dma_retain();
 653         /* we don't use the uncached buffer here, because we need the
 654          * physical memory address for DMA transfers */
 655         dma_enable_channel(0, aligned_buffer, MCI_FIFO(INTERNAL_AS3525),
 656             DMA_PERI_SD, DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8,
 657             NULL);
 658
 659         MCI_DATA_TIMER(INTERNAL_AS3525) = SD_MAX_WRITE_TIMEOUT;
 660         MCI_DATA_LENGTH(INTERNAL_AS3525) = 512;
 661         MCI_DATA_CTRL(INTERNAL_AS3525) =  (1<<0) /* enable */   |
 662                                 (0<<1) /* transfer direction */ |
 663                                 (1<<3) /* DMA */                |
 664                                 (9<<4) /* 2^9 = 512 */ ;
 665
 666         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 667         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 668
 669         /*  Wait for FIFO to empty, card may still be in PRG state  */
 670         while(MCI_STATUS(INTERNAL_AS3525) & MCI_TX_ACTIVE );
 671
 672         dma_release();
 673
 674     } while(transfer_error[INTERNAL_AS3525]);
 675
 676     card_info[INTERNAL_AS3525].current_bank = (bank == -1) ? 0 : bank;
 677
 678     return 0;
 679 }
 680
 681 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 682                                int count, void* buf, const bool write)
 683 {
 684 #ifndef HAVE_MULTIDRIVE
 685     const int drive = 0;
 686 #endif
 687     int ret = 0;
 688     unsigned loops = 0;
 689     unsigned long response;
 690     bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
 691
 692     mutex_lock(&sd_mtx);
 693     sd_enable(true);
 694     led(true);
 695
 696     if (card_info[drive].initialized <= 0)
 697     {
 698         ret = sd_init_card(drive);
 699         if (!(card_info[drive].initialized))
 700             goto sd_transfer_error_nodma;
 701     }
 702
 703     if(count < 0) /* XXX: why is it signed ? */
 704     {
 705         ret = -20;
 706         goto sd_transfer_error_nodma;
 707     }
 708     if((start+count) > card_info[drive].numblocks)
 709     {
 710         ret = -21;
 711         goto sd_transfer_error_nodma;
 712     }
 713
 714     /* skip SanDisk OF */
 715     if (drive == INTERNAL_AS3525)
 716         start += AMS_OF_SIZE;
 717
 718     last_disk_activity = current_tick;
 719
 720     dma_retain();
 721
 722     if(aligned)
 723     {
 724         if(write)
 725             clean_dcache_range(buf, count * SECTOR_SIZE);
 726         else
 727             dump_dcache_range(buf, count * SECTOR_SIZE);
 728     }
 729
 730     while(count)
 731     {
 732         /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
 733          * register, so we have to transfer maximum 127 sectors at a time. */
 734         unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
 735         void *dma_buf;
 736         const int cmd =
 737             write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 738         unsigned long bank_start = start;
 739         unsigned long status;
 740
 741         /* Only switch banks for internal storage */
 742         if(drive == INTERNAL_AS3525)
 743         {
 744             unsigned int bank = 0;
 745             while(bank_start >= BLOCKS_PER_BANK)
 746             {
 747                 bank_start -= BLOCKS_PER_BANK;
 748                 bank++;
 749             }
 750
 751             /* Switch bank if needed */
 752             if(card_info[INTERNAL_AS3525].current_bank != bank)
 753             {
 754                 ret = sd_select_bank(bank);
 755                 if (ret < 0)
 756                 {
 757                     ret -= 20;
 758                     goto sd_transfer_error;
 759                 }
 760             }
 761
 762             /* Do not cross a bank boundary in a single transfer loop */
 763             if((transfer + bank_start) > BLOCKS_PER_BANK)
 764                 transfer = BLOCKS_PER_BANK - bank_start;
 765         }
 766
 767         /* Set bank_start to the correct unit (blocks or bytes) */
 768         if(!(card_info[drive].ocr & (1<<30)))   /* not SDHC */
 769             bank_start *= SD_BLOCK_SIZE;
 770
 771         if(aligned)
 772         {
 773             dma_buf = AS3525_PHYSICAL_ADDR(buf);
 774         }
 775         else
 776         {
 777             dma_buf = aligned_buffer;
 778             if(transfer > UNALIGNED_NUM_SECTORS)
 779                 transfer = UNALIGNED_NUM_SECTORS;
 780
 781             if(write)
 782                 memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 783         }
 784
 785         ret = sd_wait_for_tran_state(drive);
 786         if (ret < 0)
 787         {
 788             ret -= 2*20;
 789             goto sd_transfer_error;
 790         }
 791
 792         if(!send_cmd(drive, cmd, bank_start, MCI_RESP, &response))
 793         {
 794             ret -= 3*20;
 795             goto sd_transfer_error;
 796         }
 797
 798         if(write)
 799         {
 800             dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
 801                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 802                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 803
 804             /*Small delay for writes prevents data crc failures at lower freqs*/
 805 #ifdef HAVE_MULTIDRIVE
 806             if((drive == SD_SLOT_AS3525) && !hs_card)
 807             {
 808                 int write_delay = 125;
 809                 while(write_delay--);
 810             }
 811 #endif
 812         }
 813         else
 814             dma_enable_channel(0, MCI_FIFO(drive), dma_buf,
 815                 (drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
 816                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 817
 818         MCI_DATA_TIMER(drive) = write ?
 819                 SD_MAX_WRITE_TIMEOUT : SD_MAX_READ_TIMEOUT;
 820         MCI_DATA_LENGTH(drive) = transfer * SD_BLOCK_SIZE;
 821         MCI_DATA_CTRL(drive) =  (1<<0) /* enable */                     |
 822                                 (!write<<1) /* transfer direction */    |
 823                                 (1<<3) /* DMA */                        |
 824                                 (9<<4) /* 2^9 = 512 */ ;
 825
 826         /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
 827         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 828
 829         /*  Wait for FIFO to empty, card may still be in PRG state for writes */
 830         while(MCI_STATUS(drive) & MCI_TX_ACTIVE);
 831
 832         /*
 833          * If the write aborted early due to a tx underrun, disable the
 834          * dma channel here, otherwise there are still 4 words in the fifo
 835          * and the retried write will get corrupted.
 836          */
 837         dma_disable_channel(0);
 838
 839         last_disk_activity = current_tick;
 840
 841         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status))
 842         {
 843             ret = -4*20;
 844             goto sd_transfer_error;
 845         }
 846
 847         if(!transfer_error[drive])
 848         {
 849             if(!write && !aligned)
 850                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 851             buf += transfer * SD_BLOCK_SIZE;
 852             start += transfer;
 853             count -= transfer;
 854             loops = 0;  /* reset errors counter */
 855         }
 856         else if(loops++ > PL180_MAX_TRANSFER_ERRORS)
 857                 panicf("SD Xfer %s err:0x%x Disk%d", (write? "write": "read"),
 858                                                   transfer_error[drive], drive);
 859     }
 860
 861 sd_transfer_error:
 862
 863     dma_release();
 864
 865 sd_transfer_error_nodma:
 866
 867     led(false);
 868     sd_enable(false);
 869
 870     if (ret)    /* error */
 871         card_info[drive].initialized = 0;
 872
 873     mutex_unlock(&sd_mtx);
 874     return ret;
 875 }
 876
 877 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 878                      void* buf)
 879 {
 880     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 881 }
 882
 883 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 884                      const void* buf)
 885 {
 886 #ifdef VERIFY_WRITE
 887     unsigned long saved_start = start;
 888     int saved_count = count;
 889     void *saved_buf = (void*)buf;
 890 #endif
 891     int ret;
 892
 893     ret = sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 894
 895 #ifdef VERIFY_WRITE
 896     if (ret) /* write failed, no point in verifying */
 897         return ret;
 898
 899     count = saved_count;
 900     buf = saved_buf;
 901     start = saved_start;
 902     while (count) {
 903         int transfer = count;
 904         if(transfer > UNALIGNED_NUM_SECTORS)
 905             transfer = UNALIGNED_NUM_SECTORS;
 906
 907         sd_transfer_sectors(drive, start, transfer, aligned_buffer, false);
 908         if (memcmp(buf, aligned_buffer, transfer * 512) != 0) {
 909             /* try the write again in the hope to repair the damage */
 910             sd_transfer_sectors(drive, saved_start, saved_count, saved_buf, true);
 911             panicf("sd: verify failed: sec=%ld n=%d!", start, transfer);
 912         }
 913
 914         buf   += transfer * 512;
 915         count -= transfer;
 916         start += transfer;
 917     }
 918 #endif
 919     return ret;
 920 }
 921
 922 long sd_last_disk_activity(void)
 923 {
 924     return last_disk_activity;
 925 }
 926
 927 void sd_enable(bool on)
 928 {
 929 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 930     extern int buttonlight_is_on;
 931 #endif
 932
 933 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 934     static bool cpu_boosted = false;
 935 #endif
 936
 937     if (sd_enabled == on)
 938         return; /* nothing to do */
 939
 940     sd_enabled = on;
 941
 942     if(on)
 943     {
 944 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 945         /* buttonlight AMSes need a bit of special handling for the buttonlight
 946          * here due to the dual mapping of GPIOD and XPD */
 947         CCU_IO |= (1<<2);              /* XPD is SD-MCI interface (b3:2 = 01) */
 948         if (buttonlight_is_on)
 949             GPIOD_DIR &= ~(1<<7);
 950         else
 951             _buttonlight_off();
 952 #endif
 953
 954 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 955         if(card_detect_target())  /* If SD card present Boost cpu for voltage */
 956         {
 957             cpu_boosted = true;
 958             cpu_boost(true);
 959         }
 960 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 961     }
 962     else
 963     {
 964 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
 965         if(cpu_boosted)
 966         {
 967             cpu_boost(false);
 968             cpu_boosted = false;
 969         }
 970 #endif  /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
 971
 972 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
 973         CCU_IO &= ~(1<<2);           /* XPD is general purpose IO (b3:2 = 00) */
 974         if (buttonlight_is_on)
 975             _buttonlight_on();
 976 #endif
 977     }
 978 }
 979
 980 tCardInfo *card_get_info_target(int card_no)
 981 {
 982     return &card_info[card_no];
 983 }
 984
 985 #ifdef CONFIG_STORAGE_MULTI
 986 int sd_num_drives(int first_drive)
 987 {
 988     /* We don't care which logical drive number(s) we have been assigned */
 989     (void)first_drive;
 990
 991     return NUM_DRIVES;
 992 }
 993 #endif /* CONFIG_STORAGE_MULTI */