firmware/target/arm/as3525/sd-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2006 Daniel Ankers
  11  * Copyright © 2008-2009 Rafaël Carré
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version 2
  16  * of the License, or (at your option) any later version.
  17  *
  18  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  19  * KIND, either express or implied.
  20  *
  21  ****************************************************************************/
  22
  23 #include "config.h" /* for HAVE_MULTIVOLUME */
  24 #include "fat.h"
  25 #include "thread.h"
  26 #include "led.h"
  27 #include "hotswap.h"
  28 #include "system.h"
  29 #include "kernel.h"
  30 #include "cpu.h"
  31 #include <stdio.h>
  32 #include <stdlib.h>
  33 #include <string.h>
  34 #include "as3525v2.h"
  35 #include "pl081.h"  /* DMA controller */
  36 #include "dma-target.h" /* DMA request lines */
  37 #include "clock-target.h"
  38 #include "panic.h"
  39 #include "stdbool.h"
  40 #include "ata_idle_notify.h"
  41 #include "sd.h"
  42 #include "usb.h"
  43
  44 #ifdef HAVE_HOTSWAP
  45 #include "disk.h"
  46 #endif
  47
  48 #ifdef SANSA_FUZEV2
  49 #include "backlight-target.h"
  50 #endif
  51
  52 #include "lcd.h"
  53 #include <stdarg.h>
  54 #include "sysfont.h"
  55
  56 #define     INTERNAL_AS3525  0   /* embedded SD card */
  57 #define     SD_SLOT_AS3525   1   /* SD slot if present */
  58
  59 /* Clipv2 Clip+ and Fuzev2 OF all occupy the same size */
  60 #define AMS_OF_SIZE 0xf000
  61
  62 /* command flags */
  63 #define MCI_NO_RESP     (0<<0)
  64 #define MCI_RESP        (1<<0)
  65 #define MCI_LONG_RESP   (1<<1)
  66
  67 /* controller registers */
  68 #define SD_BASE 0xC6070000
  69
  70 #define SD_REG(x)       (*(volatile unsigned long *) (SD_BASE+x))
  71
  72 #define MCI_CTRL        SD_REG(0x00)
  73
  74 /* control bits */
  75 #define CTRL_RESET      (1<<0)
  76 #define FIFO_RESET      (1<<1)
  77 #define DMA_RESET       (1<<2)
  78 #define INT_ENABLE      (1<<4)
  79 #define DMA_ENABLE      (1<<5)
  80 #define READ_WAIT       (1<<6)
  81 #define SEND_IRQ_RESP   (1<<7)
  82 #define ABRT_READ_DATA  (1<<8)
  83 #define SEND_CCSD       (1<<9)
  84 #define SEND_AS_CCSD    (1<<10)
  85 #define EN_OD_PULLUP    (1<<24)
  86
  87
  88 #define MCI_PWREN       SD_REG(0x04)    /* power enable */
  89
  90 #define PWR_CRD_0       (1<<0)
  91 #define PWR_CRD_1       (1<<1)
  92 #define PWR_CRD_2       (1<<2)
  93 #define PWR_CRD_3       (1<<3)
  94
  95 #define MCI_CLKDIV      SD_REG(0x08)    /* clock divider */
  96 /* CLK_DIV_0 :    bits 7:0
  97  * CLK_DIV_1 :    bits 15:8
  98  * CLK_DIV_2 :    bits 23:16
  99  * CLK_DIV_3 :    bits 31:24
 100  */
 101
 102 #define MCI_CLKSRC      SD_REG(0x0C)    /* clock source */
 103 /* CLK_SRC_CRD0:  bits 1:0
 104  * CLK_SRC_CRD1:  bits 3:2
 105  * CLK_SRC_CRD2:  bits 5:4
 106  * CLK_SRC_CRD3:  bits 7:6
 107  */
 108
 109 #define MCI_CLKENA      SD_REG(0x10)    /* clock enable */
 110
 111 #define CCLK_ENA_CRD0   (1<<0)
 112 #define CCLK_ENA_CRD1   (1<<1)
 113 #define CCLK_ENA_CRD2   (1<<2)
 114 #define CCLK_ENA_CRD3   (1<<3)
 115 #define CCLK_LP_CRD0    (1<<16)         /* LP --> Low Power Mode? */
 116 #define CCLK_LP_CRD1    (1<<17)
 117 #define CCLK_LP_CRD2    (1<<18)
 118 #define CCLK_LP_CRD3    (1<<19)
 119
 120 #define MCI_TMOUT       SD_REG(0x14)    /* timeout */
 121 /* response timeout bits 0:7
 122  * data timeout bits     8:31
 123  */
 124
 125 #define MCI_CTYPE       SD_REG(0x18)    /* card type */
 126                                         /* 1 bit per card, set = wide bus */
 127 #define WIDTH4_CRD0     (1<<0)
 128 #define WIDTH4_CRD1     (1<<1)
 129 #define WIDTH4_CRD2     (1<<2)
 130 #define WIDTH4_CRD3     (1<<3)
 131
 132 #define MCI_BLKSIZ      SD_REG(0x1C)    /* block size  bits 0:15*/
 133 #define MCI_BYTCNT      SD_REG(0x20)    /* byte count  bits 0:31*/
 134 #define MCI_MASK        SD_REG(0x24)    /* interrupt mask */
 135
 136
 137
 138 #define MCI_ARGUMENT    SD_REG(0x28)
 139 #define MCI_COMMAND     SD_REG(0x2C)
 140
 141 /* command bits (bits 5:0 are the command index) */
 142 #define CMD_RESP_EXP_BIT        (1<<6)
 143 #define CMD_RESP_LENGTH_BIT     (1<<7)
 144 #define CMD_CHECK_CRC_BIT       (1<<8)
 145 #define CMD_DATA_EXP_BIT        (1<<9)
 146 #define CMD_RW_BIT              (1<<10)
 147 #define CMD_TRANSMODE_BIT       (1<<11)
 148 #define CMD_SENT_AUTO_STOP_BIT  (1<<12)
 149 #define CMD_WAIT_PRV_DAT_BIT    (1<<13)
 150 #define CMD_ABRT_CMD_BIT        (1<<14)
 151 #define CMD_SEND_INIT_BIT       (1<<15)
 152 #define CMD_CARD_NO(x)          ((x)<<16)         /* 5 bits wide  */
 153 #define CMD_SEND_CLK_ONLY       (1<<21)
 154 #define CMD_READ_CEATA          (1<<22)
 155 #define CMD_CCS_EXPECTED        (1<<23)
 156 #define CMD_DONE_BIT            (1<<31)
 157
 158 #define TRANSFER_CMD  (cmd == SD_READ_MULTIPLE_BLOCK ||   \
 159                        cmd == SD_WRITE_MULTIPLE_BLOCK)
 160
 161 #define MCI_RESP0       SD_REG(0x30)
 162 #define MCI_RESP1       SD_REG(0x34)
 163 #define MCI_RESP2       SD_REG(0x38)
 164 #define MCI_RESP3       SD_REG(0x3C)
 165
 166 #define MCI_MASK_STATUS SD_REG(0x40)    /* masked interrupt status */
 167 #define MCI_RAW_STATUS  SD_REG(0x44)    /* raw interrupt status, also used as
 168                                          * status clear */
 169
 170 /* interrupt bits */                /* C D E   (Cmd) (Data) (End) */
 171 #define MCI_INT_CRDDET  (1<<0)      /*          card detect */
 172 #define MCI_INT_RE      (1<<1)      /* x         response error */
 173 #define MCI_INT_CD      (1<<2)      /*     x     command done */
 174 #define MCI_INT_DTO     (1<<3)      /*     x     data transfer over */
 175 #define MCI_INT_TXDR    (1<<4)      /*          tx fifo data request */
 176 #define MCI_INT_RXDR    (1<<5)      /*          rx fifo data request */
 177 #define MCI_INT_RCRC    (1<<6)      /* x         response crc error */
 178 #define MCI_INT_DCRC    (1<<7)      /*   x       data crc error */
 179 #define MCI_INT_RTO     (1<<8)      /* x         response timeout */
 180 #define MCI_INT_DRTO    (1<<9)      /*   x       data read timeout */
 181 #define MCI_INT_HTO     (1<<10)     /*   x       data starv timeout */
 182 #define MCI_INT_FRUN    (1<<11)     /*   x       fifo over/underrun */
 183 #define MCI_INT_HLE     (1<<12)     /* x x        hw locked while error */
 184 #define MCI_INT_SBE     (1<<13)     /*   x       start bit error */
 185 #define MCI_INT_ACD     (1<<14)     /*          auto command done */
 186 #define MCI_INT_EBE     (1<<15)     /*   x       end bit error */
 187 #define MCI_INT_SDIO    (0xf<<16)
 188
 189 /*
 190  *  STATUS register
 191  *  & 0xBA80    = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
 192  *                  MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
 193  *  & 8         = MCI_INT_DTO
 194  *  & 0x428     = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
 195  *  & 0x418     = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
 196  */
 197
 198 #define MCI_CMD_ERROR    \
 199          (MCI_INT_RE   | \
 200           MCI_INT_RCRC | \
 201           MCI_INT_RTO  | \
 202           MCI_INT_HLE)
 203
 204 #define MCI_DATA_ERROR    \
 205         ( MCI_INT_DCRC  | \
 206           MCI_INT_DRTO  | \
 207           MCI_INT_HTO   | \
 208           MCI_INT_FRUN  | \
 209           MCI_INT_HLE   | \
 210           MCI_INT_SBE   | \
 211           MCI_INT_EBE)
 212
 213 #define MCI_STATUS      SD_REG(0x48)
 214
 215 #define FIFO_RX_WM              (1<<0)
 216 #define FIFO_TX_WM              (1<<1)
 217 #define FIFO_EMPTY              (1<<2)
 218 #define FIFO_FULL               (1<<3)
 219 #define CMD_FSM_STATE_B0        (1<<4)
 220 #define CMD_FSM_STATE_B1        (1<<5)
 221 #define CMD_FSM_STATE_B2        (1<<6)
 222 #define CMD_FSM_STATE_B3        (1<<7)
 223 #define DATA_3_STAT             (1<<8)
 224 #define DATA_BUSY               (1<<9)
 225 #define DATA_STAT_MC_BUSY       (1<<10)
 226 #define RESP_IDX_B0             (1<<11)
 227 #define RESP_IDX_B1             (1<<12)
 228 #define RESP_IDX_B2             (1<<13)
 229 #define RESP_IDX_B3             (1<<14)
 230 #define RESP_IDX_B4             (1<<15)
 231 #define RESP_IDX_B5             (1<<16)
 232 #define FIFO_CNT_B00            (1<<17)
 233 #define FIFO_CNT_B01            (1<<18)
 234 #define FIFO_CNT_B02            (1<<19)
 235 #define FIFO_CNT_B03            (1<<20)
 236 #define FIFO_CNT_B04            (1<<21)
 237 #define FIFO_CNT_B05            (1<<22)
 238 #define FIFO_CNT_B06            (1<<23)
 239 #define FIFO_CNT_B07            (1<<24)
 240 #define FIFO_CNT_B08            (1<<25)
 241 #define FIFO_CNT_B09            (1<<26)
 242 #define FIFO_CNT_B10            (1<<27)
 243 #define FIFO_CNT_B11            (1<<28)
 244 #define FIFO_CNT_B12            (1<<29)
 245 #define DMA_ACK                 (1<<30)
 246 #define START_CMD               (1<<31)
 247
 248 #define MCI_FIFOTH      SD_REG(0x4C)    /* FIFO threshold */
 249 /* TX watermark :    bits 11:0
 250  * RX watermark :    bits 27:16
 251  * DMA MTRANS SIZE : bits 30:28
 252  * bits 31, 15:12 : unused
 253  */
 254 #define MCI_FIFOTH_MASK 0x8000f000
 255
 256 #define MCI_CDETECT     SD_REG(0x50)    /* card detect */
 257
 258 #define CDETECT_CRD_0   (1<<0)
 259 #define CDETECT_CRD_1   (1<<1)
 260 #define CDETECT_CRD_2   (1<<2)
 261 #define CDETECT_CRD_3   (1<<3)
 262
 263 #define MCI_WRTPRT      SD_REG(0x54)    /* write protect */
 264 #define MCI_GPIO        SD_REG(0x58)
 265 #define MCI_TCBCNT      SD_REG(0x5C)    /* transferred CIU byte count (card)*/
 266 #define MCI_TBBCNT      SD_REG(0x60)    /* transferred host/DMA to/from bytes (FIFO)*/
 267 #define MCI_DEBNCE      SD_REG(0x64)    /* card detect debounce  bits 23:0*/
 268 #define MCI_USRID       SD_REG(0x68)    /* user id */
 269 #define MCI_VERID       SD_REG(0x6C)    /* version id */
 270
 271 #define MCI_HCON        SD_REG(0x70)    /* hardware config */
 272 /* bit  0       : card type
 273  * bits 5:1     : maximum card index
 274  * bit  6       : BUS TYPE
 275  * bits 9:7     : DATA WIDTH
 276  * bits 15:10   : ADDR WIDTH
 277  * bits 17:16   : DMA IF
 278  * bits 20:18   : DMA WIDTH
 279  * bit  21      : FIFO RAM INSIDE
 280  * bit  22      : IMPL HOLD REG
 281  * bit  23      : SET CLK FALSE
 282  * bits 25:24   : MAX CLK DIV IDX
 283  * bit  26      : AREA OPTIM
 284  */
 285
 286 #define MCI_BMOD        SD_REG(0x80)    /* bus mode */
 287 /* bit  0       : SWR
 288  * bit  1       : FB
 289  * bits 6:2     : DSL
 290  * bit  7       : DE
 291  * bit  10:8    : PBL
 292  */
 293
 294 #define MCI_PLDMND      SD_REG(0x84)    /* poll demand */
 295 #define MCI_DBADDR      SD_REG(0x88)    /* descriptor base address */
 296 #define MCI_IDSTS       SD_REG(0x8C)    /* internal DMAC status */
 297 /* bit  0       : TI
 298  * bit  1       : RI
 299  * bit  2       : FBE
 300  * bit  3       : unused
 301  * bit  4       : DU
 302  * bit  5       : CES
 303  * bits 7:6     : unused
 304  * bits 8       : NIS
 305  * bit  9       : AIS
 306  * bits 12:10   : EB
 307  * bits 16:13   : FSM
 308  */
 309
 310 #define MCI_IDINTEN     SD_REG(0x90)    /* internal DMAC interrupt enable */
 311 /* bit  0       : TI
 312  * bit  1       : RI
 313  * bit  2       : FBE
 314  * bit  3       : unused
 315  * bit  4       : DU
 316  * bit  5       : CES
 317  * bits 7:6     : unused
 318  * bits 8       : NI
 319  * bit  9       : AI
 320  */
 321 #define MCI_DSCADDR     SD_REG(0x94)    /* current host descriptor address */
 322 #define MCI_BUFADDR     SD_REG(0x98)    /* current host buffer address */
 323
 324 #define MCI_FIFO        ((unsigned long *) (SD_BASE+0x100))
 325
 326 #define UNALIGNED_NUM_SECTORS 10
 327 static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32)));   /* align on cache line size */
 328 static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
 329
 330 static void init_controller(void);
 331 static int sd_wait_for_state(const int drive, unsigned int state);
 332
 333 static tCardInfo card_info[NUM_DRIVES];
 334
 335 /* for compatibility */
 336 static long last_disk_activity = -1;
 337
 338 #define MIN_YIELD_PERIOD 5  /* ticks */
 339 static long next_yield = 0;
 340
 341 static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
 342 static const char         sd_thread_name[] = "ata/sd";
 343 static struct mutex       sd_mtx SHAREDBSS_ATTR;
 344 static struct event_queue sd_queue;
 345 #ifndef BOOTLOADER
 346 bool sd_enabled = false;
 347 #endif
 348
 349 static struct wakeup transfer_completion_signal;
 350 static struct wakeup command_completion_signal;
 351 static volatile bool retry;
 352 static volatile int cmd_error;
 353
 354 #if defined(HAVE_MULTIDRIVE)
 355 #define EXT_SD_BITS (1<<2)
 356 #endif
 357
 358 static inline void mci_delay(void) { udelay(1000); }
 359
 360 void INT_NAND(void)
 361 {
 362     MCI_CTRL &= ~INT_ENABLE;
 363     /* use raw status here as we need to check some Ints that are masked */
 364     const int status = MCI_RAW_STATUS;
 365
 366     MCI_RAW_STATUS = status;    /* clear status */
 367
 368     if(status & MCI_DATA_ERROR)
 369         retry = true;
 370
 371     if( status & (MCI_INT_DTO|MCI_DATA_ERROR))
 372         wakeup_signal(&transfer_completion_signal);
 373
 374     cmd_error = status & MCI_CMD_ERROR;
 375
 376     if(status & MCI_INT_CD)
 377         wakeup_signal(&command_completion_signal);
 378
 379     MCI_CTRL |= INT_ENABLE;
 380 }
 381
 382 static inline bool card_detect_target(void)
 383 {
 384 #if defined(HAVE_MULTIDRIVE)
 385 #if defined(SANSA_FUZEV2)
 386     return GPIOA_PIN(2);
 387 #elif defined(SANSA_CLIPPLUS)
 388     return !(GPIOA_PIN(2));
 389 #else
 390 #error "microSD pin not defined for your target"
 391 #endif
 392 #else
 393     return false;
 394 #endif
 395 }
 396
 397 static bool send_cmd(const int drive, const int cmd, const int arg, const int flags,
 398         unsigned long *response)
 399 {
 400 #if defined(HAVE_MULTIDRIVE)
 401     if(sd_present(SD_SLOT_AS3525))
 402         GPIOB_PIN(5) = (1-drive) << 5;
 403 #endif
 404
 405 /*  RCRC & RTO interrupts should be set together with the CD interrupt but
 406  *  in practice sometimes incorrectly precede the CD interrupt.  If we leave
 407  *  them masked for now we can check them in the isr by reading raw status when
 408  *  the CD int is triggered.
 409  */
 410     MCI_MASK |= MCI_INT_CD;
 411     MCI_ARGUMENT = arg;
 412
 413     /* Construct MCI_COMMAND  */
 414     MCI_COMMAND =
 415       /*b5:0*/    cmd
 416       /*b6  */  | ((flags & MCI_RESP)                ? CMD_RESP_EXP_BIT:      0)
 417       /*b7  */  | ((flags & MCI_LONG_RESP)           ? CMD_RESP_LENGTH_BIT:   0)
 418       /*b8      | CMD_CHECK_CRC_BIT       unused  */
 419       /*b9  */  | (TRANSFER_CMD                      ? CMD_DATA_EXP_BIT:      0)
 420       /*b10 */  | ((cmd == SD_WRITE_MULTIPLE_BLOCK)  ? CMD_RW_BIT:            0)
 421       /*b11     | CMD_TRANSMODE_BIT       unused  */
 422       /*b12     | CMD_SENT_AUTO_STOP_BIT  unused  */
 423       /*b13 */  | (TRANSFER_CMD                      ? CMD_WAIT_PRV_DAT_BIT:  0)
 424       /*b14     | CMD_ABRT_CMD_BIT        unused  */
 425       /*b15     | CMD_SEND_INIT_BIT       unused  */
 426    /*b20:16 */  |                                      CMD_CARD_NO(drive)
 427       /*b21     | CMD_SEND_CLK_ONLY       unused  */
 428       /*b22     | CMD_READ_CEATA          unused  */
 429       /*b23     | CMD_CCS_EXPECTED        unused  */
 430       /*b31 */  |                                      CMD_DONE_BIT;
 431
 432 #ifdef SANSA_FUZEV2
 433     extern int buttonlight_is_on;
 434     if(buttonlight_is_on)
 435         _buttonlight_on();
 436     else
 437         _buttonlight_off();
 438 #endif
 439     wakeup_wait(&command_completion_signal, TIMEOUT_BLOCK);
 440
 441     MCI_MASK &= ~MCI_INT_CD;
 442
 443     /*  Handle command responses & errors */
 444     if(flags & MCI_RESP)
 445     {
 446         if(cmd_error & (MCI_INT_RCRC | MCI_INT_RTO))
 447             return false;
 448
 449         if(flags & MCI_LONG_RESP)
 450         {
 451             response[0] = MCI_RESP3;
 452             response[1] = MCI_RESP2;
 453             response[2] = MCI_RESP1;
 454             response[3] = MCI_RESP0;
 455         }
 456         else
 457             response[0] = MCI_RESP0;
 458     }
 459     return true;
 460 }
 461
 462 static int sd_init_card(const int drive)
 463 {
 464     unsigned long response;
 465     long init_timeout;
 466     bool sd_v2 = false;
 467
 468     /*  assume 24 MHz clock / 60 = 400 kHz  */
 469     MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C;    /* CLK_DIV_0 : bits 7:0  */
 470
 471     /* 100 - 400kHz clock required for Identification Mode  */
 472     /*  Start of Card Identification Mode ************************************/
 473
 474     /* CMD0 Go Idle  */
 475     if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
 476         return -1;
 477     mci_delay();
 478
 479     /* CMD8 Check for v2 sd card.  Must be sent before using ACMD41
 480       Non v2 cards will not respond to this command*/
 481     if(send_cmd(drive, SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
 482         if((response & 0xFFF) == 0x1AA)
 483             sd_v2 = true;
 484
 485     /* timeout for initialization is 1sec, from SD Specification 2.00 */
 486     init_timeout = current_tick + HZ;
 487
 488     do {
 489         /* this timeout is the only valid error for this loop*/
 490         if(TIME_AFTER(current_tick, init_timeout))
 491             return -2;
 492
 493         /* app_cmd */
 494         send_cmd(drive, SD_APP_CMD, 0, MCI_RESP, &response);
 495
 496          /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
 497         if(!send_cmd(drive, SD_APP_OP_COND, (0x00FF8000 | (sd_v2 ? 1<<30 : 0)),
 498                         MCI_RESP, &card_info[drive].ocr))
 499             return -3;
 500     } while(!(card_info[drive].ocr & (1<<31)) );
 501
 502     /* CMD2 send CID */
 503     if(!send_cmd(drive, SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info[drive].cid))
 504         return -4;
 505
 506     /* CMD3 send RCA */
 507     if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 508         return -5;
 509
 510 #ifdef HAVE_MULTIDRIVE
 511     /* Make sure we have 2 unique rca numbers */
 512     if(card_info[INTERNAL_AS3525].rca == card_info[SD_SLOT_AS3525].rca)
 513         if(!send_cmd(drive, SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info[drive].rca))
 514             return -6;
 515 #endif
 516     /*  End of Card Identification Mode   ************************************/
 517
 518     /* Attempt to switch cards to HS timings, non HS cards just ignore this */
 519     /*  CMD7 w/rca: Select card to put it in TRAN state */
 520     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 521         return -7;
 522
 523     if(sd_wait_for_state(drive, SD_TRAN))
 524         return -8;
 525
 526     /* CMD6 */
 527     if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
 528         return -9;
 529     mci_delay();
 530
 531     /*  We need to go back to STBY state now so we can read csd */
 532     /*  CMD7 w/rca=0:  Deselect card to put it in STBY state */
 533     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 534         return -10;
 535
 536     /* CMD9 send CSD */
 537     if(!send_cmd(drive, SD_SEND_CSD, card_info[drive].rca,
 538                  MCI_RESP|MCI_LONG_RESP, card_info[drive].csd))
 539         return -11;
 540
 541     sd_parse_csd(&card_info[drive]);
 542
 543     if(drive == INTERNAL_AS3525) /* The OF is stored in the first blocks */
 544         card_info[INTERNAL_AS3525].numblocks -= AMS_OF_SIZE;
 545
 546     /*  Card back to full speed  */
 547     MCI_CLKDIV &= ~(0xFF);    /* CLK_DIV_0 : bits 7:0 = 0x00 */
 548
 549     /*  CMD7 w/rca: Select card to put it in TRAN state */
 550     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 551         return -12;
 552
 553 #ifndef BOOTLOADER
 554     /*  Switch to to 4 bit widebus mode  */
 555     if(sd_wait_for_state(drive, SD_TRAN) < 0)
 556         return -13;
 557     /* CMD55 */              /*  Response is requested due to timing issue  */
 558     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 559         return -14;
 560     /* ACMD6  */
 561     if(!send_cmd(drive, SD_SET_BUS_WIDTH, 2, MCI_NO_RESP, NULL))
 562         return -15;
 563     mci_delay();
 564     /* CMD55 */             /*  Response is requested due to timing issue  */
 565     if(!send_cmd(drive, SD_APP_CMD, card_info[drive].rca, MCI_RESP, &response))
 566         return -16;
 567     /* ACMD42  */
 568     if(!send_cmd(drive, SD_SET_CLR_CARD_DETECT, 0, MCI_NO_RESP, NULL))
 569         return -17;
 570     /* Now that card is widebus make controller aware */
 571     MCI_CTYPE |= (1<<drive);
 572 #endif
 573
 574     card_info[drive].initialized = 1;
 575
 576     MCI_CLKENA |= 1<<(drive + 16);      /*  Set low power mode  */
 577
 578     return 0;
 579 }
 580
 581 static void sd_thread(void) __attribute__((noreturn));
 582 static void sd_thread(void)
 583 {
 584     struct queue_event ev;
 585     bool idle_notified = false;
 586
 587     while (1)
 588     {
 589         queue_wait_w_tmo(&sd_queue, &ev, HZ);
 590
 591         switch ( ev.id )
 592         {
 593 #ifdef HAVE_HOTSWAP
 594         case SYS_HOTSWAP_INSERTED:
 595         case SYS_HOTSWAP_EXTRACTED:
 596         {
 597             int microsd_init = 1;
 598             fat_lock();          /* lock-out FAT activity first -
 599                                     prevent deadlocking via disk_mount that
 600                                     would cause a reverse-order attempt with
 601                                     another thread */
 602             mutex_lock(&sd_mtx); /* lock-out card activity - direct calls
 603                                     into driver that bypass the fat cache */
 604
 605             /* We now have exclusive control of fat cache and ata */
 606
 607             disk_unmount(SD_SLOT_AS3525);     /* release "by force", ensure file
 608                                     descriptors aren't leaked and any busy
 609                                     ones are invalid if mounting */
 610             /* Force card init for new card, re-init for re-inserted one or
 611              * clear if the last attempt to init failed with an error. */
 612             card_info[SD_SLOT_AS3525].initialized = 0;
 613
 614             if (ev.id == SYS_HOTSWAP_INSERTED)
 615             {
 616                 sd_enable(true);
 617                 microsd_init = sd_init_card(SD_SLOT_AS3525);
 618                 if (microsd_init < 0) /* initialisation failed */
 619                     panicf("microSD init failed : %d", microsd_init);
 620
 621                 microsd_init = disk_mount(SD_SLOT_AS3525); /* 0 if fail */
 622             }
 623
 624             /*
 625              * Mount succeeded, or this was an EXTRACTED event,
 626              * in both cases notify the system about the changed filesystems
 627              */
 628             if (microsd_init)
 629                 queue_broadcast(SYS_FS_CHANGED, 0);
 630             /* Access is now safe */
 631             mutex_unlock(&sd_mtx);
 632             fat_unlock();
 633             sd_enable(false);
 634         }
 635             break;
 636 #endif
 637         case SYS_TIMEOUT:
 638             if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
 639             {
 640                 idle_notified = false;
 641             }
 642             else
 643             {
 644                 /* never let a timer wrap confuse us */
 645                 next_yield = current_tick;
 646
 647                 if (!idle_notified)
 648                 {
 649                     call_storage_idle_notifys(false);
 650                     idle_notified = true;
 651                 }
 652             }
 653             break;
 654
 655         case SYS_USB_CONNECTED:
 656             usb_acknowledge(SYS_USB_CONNECTED_ACK);
 657             /* Wait until the USB cable is extracted again */
 658             usb_wait_for_disconnect(&sd_queue);
 659
 660             break;
 661         case SYS_USB_DISCONNECTED:
 662             usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
 663             break;
 664         }
 665     }
 666 }
 667
 668 static void init_controller(void)
 669 {
 670     int hcon_numcards = ((MCI_HCON>>1) & 0x1F) + 1;
 671     int card_mask = (1 << hcon_numcards) - 1;
 672
 673     MCI_PWREN &= ~card_mask;            /*  power off all cards  */
 674
 675     MCI_CLKSRC = 0x00;                  /* All CLK_SRC_CRD set to 0*/
 676     MCI_CLKDIV = 0x00;                  /* CLK_DIV_0 : bits 7:0  */
 677
 678     MCI_PWREN |= card_mask;             /*  power up cards  */
 679     mci_delay();
 680
 681     MCI_CTRL |= CTRL_RESET;
 682     while(MCI_CTRL & CTRL_RESET)
 683         ;
 684
 685     MCI_RAW_STATUS = 0xffffffff;        /* Clear all MCI Interrupts  */
 686
 687     MCI_TMOUT = 0xffffffff;             /*  data b31:8, response b7:0 */
 688
 689     MCI_CTYPE = 0x0;                    /*  all cards 1 bit bus for now */
 690
 691     MCI_CLKENA = card_mask;             /*  Enables card clocks  */
 692
 693     MCI_ARGUMENT = 0;
 694     MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
 695     while(MCI_COMMAND & CMD_DONE_BIT)
 696         ;
 697
 698     MCI_DEBNCE = 0xfffff;               /* default value */
 699
 700     /* Rx watermark = 63(sd reads)  Tx watermark = 128 (sd writes) */
 701     MCI_FIFOTH = (MCI_FIFOTH & MCI_FIFOTH_MASK) | 0x503f0080;
 702
 703     GPIOB_DIR |= (1<<5);                 /* Set pin B5 to output  */
 704
 705     /* Mask all MCI Interrupts initially  */
 706     MCI_MASK = 0;
 707
 708     MCI_CTRL |= INT_ENABLE;
 709 }
 710
 711 int sd_init(void)
 712 {
 713     int ret;
 714
 715     CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
 716
 717     CGU_IDE =   (1<<7)          /* AHB interface enable */
 718             |   (AS3525_IDE_DIV << 2)
 719             |   1;              /* clock source = PLLA */
 720
 721     CGU_MEMSTICK =  (1<<7)      /* interface enable */
 722                  |  (AS3525_MS_DIV << 2)
 723                  |  1;          /* clock source = PLLA */
 724
 725     CGU_SDSLOT = (1<<7)         /* interface enable */
 726                | (AS3525_SDSLOT_DIV << 2)
 727                | 1;             /* clock source = PLLA */
 728
 729     wakeup_init(&transfer_completion_signal);
 730     wakeup_init(&command_completion_signal);
 731 #ifdef HAVE_MULTIDRIVE
 732     /* clear previous irq */
 733     GPIOA_IC = EXT_SD_BITS;
 734     /* enable edge detecting */
 735     GPIOA_IS &= ~EXT_SD_BITS;
 736     /* detect both raising and falling edges */
 737     GPIOA_IBE |= EXT_SD_BITS;
 738     /* Configure XPD for SD-MCI interface */
 739     CCU_IO |= (1<<2);
 740 #endif
 741
 742     VIC_INT_ENABLE = INTERRUPT_NAND;
 743
 744     init_controller();
 745     ret = sd_init_card(INTERNAL_AS3525);
 746     if(ret < 0)
 747         return ret;
 748
 749     /* init mutex */
 750     mutex_init(&sd_mtx);
 751
 752     queue_init(&sd_queue, true);
 753     create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
 754             sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
 755
 756 #ifndef BOOTLOADER
 757     sd_enabled = true;
 758     sd_enable(false);
 759 #endif
 760     return 0;
 761 }
 762
 763 static int sd_wait_for_state(const int drive, unsigned int state)
 764 {
 765     unsigned long response;
 766     unsigned int timeout = 100; /* ticks */
 767     long t = current_tick;
 768
 769     while (1)
 770     {
 771         long tick;
 772
 773         while(!(send_cmd(drive, SD_SEND_STATUS, card_info[drive].rca, MCI_RESP, &response)));
 774
 775         if (((response >> 9) & 0xf) == state)
 776             return 0;
 777
 778         if(TIME_AFTER(current_tick, t + timeout))
 779             return -10 * ((response >> 9) & 0xf);
 780
 781         if (TIME_AFTER((tick = current_tick), next_yield))
 782         {
 783             yield();
 784             timeout += current_tick - tick;
 785             next_yield = tick + MIN_YIELD_PERIOD;
 786         }
 787     }
 788 }
 789
 790 static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
 791                                 int count, void* buf, bool write)
 792 {
 793     int ret = 0;
 794 #ifndef HAVE_MULTIDRIVE
 795     const int drive = 0;
 796 #endif
 797
 798     mutex_lock(&sd_mtx);
 799 #ifndef BOOTLOADER
 800     sd_enable(true);
 801     led(true);
 802 #endif
 803
 804     if (card_info[drive].initialized <= 0)
 805     {
 806         ret = sd_init_card(drive);
 807         if (!(card_info[drive].initialized))
 808         {
 809             panicf("card not initialised (%d)", ret);
 810             goto sd_transfer_error;
 811         }
 812     }
 813
 814     if((start+count) > card_info[drive].numblocks)
 815     {
 816         ret = -18;
 817         goto sd_transfer_error;
 818     }
 819
 820     /* skip SanDisk OF */
 821     if (drive == INTERNAL_AS3525)
 822         start += AMS_OF_SIZE;
 823
 824     /*  CMD7 w/rca: Select card to put it in TRAN state */
 825     if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_NO_RESP, NULL))
 826         return -19;
 827
 828     last_disk_activity = current_tick;
 829     dma_retain();
 830
 831     const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
 832
 833     do
 834     {
 835         void *dma_buf = aligned_buffer;
 836         unsigned int transfer = count;
 837         if(transfer > UNALIGNED_NUM_SECTORS)
 838             transfer = UNALIGNED_NUM_SECTORS;
 839
 840         if(write)
 841             memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
 842
 843         /* Interrupt handler might set this to true during transfer */
 844         retry = false;
 845
 846         MCI_BLKSIZ = SD_BLOCK_SIZE;
 847         MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
 848
 849         ret = sd_wait_for_state(drive, SD_TRAN);
 850         if (ret < 0)
 851         {
 852             static const char *st[9] = {
 853                 "IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV",
 854                                                                 "PRG", "DIS"};
 855             if(ret <= -10)
 856                 panicf("wait for TRAN state failed (%s) %d",
 857                                                     st[(-ret / 10) % 9], drive);
 858             else
 859                 panicf("wait for state failed");
 860             goto sd_transfer_error;
 861         }
 862
 863         int arg = start;
 864         if(!(card_info[drive].ocr & (1<<30))) /* not SDHC */
 865             arg *= SD_BLOCK_SIZE;
 866
 867         if(write)
 868             dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
 869                 DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
 870         else
 871             dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
 872                 DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
 873
 874         MCI_MASK |= (MCI_DATA_ERROR | MCI_INT_DTO);
 875         MCI_CTRL |= DMA_ENABLE;
 876
 877         unsigned long dummy; /* if we don't ask for a response, writing fails */
 878         if(!send_cmd(drive, cmd, arg, MCI_RESP, &dummy))
 879             panicf("%s multiple blocks failed", write ? "write" : "read");
 880
 881         wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
 882
 883         MCI_MASK &= ~(MCI_DATA_ERROR | MCI_INT_DTO);
 884
 885         last_disk_activity = current_tick;
 886
 887         if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
 888         {
 889             ret = -666;
 890             panicf("STOP TRANSMISSION failed");
 891             goto sd_transfer_error;
 892         }
 893
 894         if(!retry)
 895         {
 896             if(!write)
 897                 memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
 898             buf += transfer * SD_BLOCK_SIZE;
 899             start += transfer;
 900             count -= transfer;
 901         }
 902         else   /*  reset controller if we had an error  */
 903         {
 904             MCI_CTRL |= (FIFO_RESET|DMA_RESET);
 905             while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
 906                 ;
 907         }
 908
 909     } while(retry || count);
 910
 911     dma_release();
 912
 913     /* CMD lines are separate, not common, so we need to actively deselect */
 914     /*  CMD7 w/rca =0 : deselects card & puts it in STBY state */
 915     if(!send_cmd(drive, SD_DESELECT_CARD, 0, MCI_NO_RESP, NULL))
 916         return -20;
 917
 918 #ifndef BOOTLOADER
 919     sd_enable(false);
 920     led(false);
 921 #endif
 922     mutex_unlock(&sd_mtx);
 923     return 0;
 924
 925 sd_transfer_error:
 926     panicf("transfer error : %d",ret);
 927     card_info[drive].initialized = 0;
 928     return ret;
 929 }
 930
 931 int sd_read_sectors(IF_MD2(int drive,) unsigned long start, int count,
 932                     void* buf)
 933 {
 934     return sd_transfer_sectors(IF_MD2(drive,) start, count, buf, false);
 935 }
 936
 937 int sd_write_sectors(IF_MD2(int drive,) unsigned long start, int count,
 938                      const void* buf)
 939 {
 940 #if defined(BOOTLOADER) /* we don't need write support in bootloader */
 941 #ifdef HAVE_MULTIDRIVE
 942     (void) drive;
 943 #endif
 944     (void) start;
 945     (void) count;
 946     (void) buf;
 947     return -1;
 948 #else
 949     return sd_transfer_sectors(IF_MD2(drive,) start, count, (void*)buf, true);
 950 #endif /* defined(BOOTLOADER) */
 951 }
 952
 953 #ifndef BOOTLOADER
 954 long sd_last_disk_activity(void)
 955 {
 956     return last_disk_activity;
 957 }
 958
 959 void sd_enable(bool on)
 960 {
 961     /* TODO */
 962     (void) on;
 963 }
 964
 965 tCardInfo *card_get_info_target(int card_no)
 966 {
 967     return &card_info[card_no];
 968 }
 969 #endif /* BOOTLOADER */
 970
 971 #ifdef HAVE_HOTSWAP
 972 bool sd_removable(IF_MD_NONVOID(int drive))
 973 {
 974     return (drive==1);
 975 }
 976
 977 bool sd_present(IF_MD_NONVOID(int drive))
 978 {
 979     return (drive == 0) ? true : card_detect_target();
 980 }
 981
 982 static int sd1_oneshot_callback(struct timeout *tmo)
 983 {
 984     (void)tmo;
 985
 986     /* This is called only if the state was stable for 300ms - check state
 987      * and post appropriate event. */
 988     if (card_detect_target())
 989     {
 990         queue_broadcast(SYS_HOTSWAP_INSERTED, 0);
 991     }
 992     else
 993         queue_broadcast(SYS_HOTSWAP_EXTRACTED, 0);
 994
 995     return 0;
 996 }
 997
 998 void sd_gpioa_isr(void)
 999 {
1000     static struct timeout sd1_oneshot;
1001     if (GPIOA_MIS & EXT_SD_BITS)
1002         timeout_register(&sd1_oneshot, sd1_oneshot_callback, (3*HZ/10), 0);
1003     /* acknowledge interrupt */
1004     GPIOA_IC = EXT_SD_BITS;
1005 }
1006
1007 void card_enable_monitoring_target(bool on)
1008 {
1009     if (on) /* enable interrupt */
1010         GPIOA_IE |= EXT_SD_BITS;
1011     else    /* disable interrupt */
1012         GPIOA_IE &= ~EXT_SD_BITS;
1013 }
1014 #endif /* HAVE_HOTSWAP */
1015
1016 #ifdef CONFIG_STORAGE_MULTI
1017 int sd_num_drives(int first_drive)
1018 {
1019     /* We don't care which logical drive number(s) we have been assigned */
1020     (void)first_drive;
1021
1022     return NUM_DRIVES;
1023 }
1024 #endif /* CONFIG_STORAGE_MULTI */