firmware/target/arm/as3525/usb-drv-as3525v2.h

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2010 Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #ifndef __USB_DRV_AS3525v2_H__
  22 #define __USB_DRV_AS3525v2_H__
  23
  24 #include "as3525v2.h"
  25
  26 /* All multi-bit fields in the driver use the following convention.
  27  * If the register name is NAME, then there is one define NAME_bitp
  28  * which holds the bit position and one define NAME_bits which holds
  29  * a mask of the bits within the register (after shift).
  30  * These macros allow easy access and construction of such fields */
  31 /* Usage:
  32  * - extract(reg_name,field_name)
  33  *   extract a field of the register
  34  * - bitm(reg_name,field_name)
  35  *   build a bitmask for the field
  36  * - make(reg_name,field_name,value)
  37  *   build the value of the field (doesn't mask)
  38  */
  39 #define extract(reg_name, field_name) \
  40     ((reg_name >> reg_name##_##field_name##_bitp) & reg_name##_##field_name##_bits)
  41
  42 #define bitm(reg_name, field_name) \
  43     (reg_name##_##field_name##_bits << reg_name##_##field_name##_bitp)
  44
  45 #define USB_DEVICE                  (USB_BASE + 0x0800)   /** USB Device base address */
  46
  47 /**
  48  * Core Global Registers
  49  */
  50 #define BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset))
  51
  52 /** OTG Control and Status Register */
  53 #define GOTGCTL     BASE_REG(0x000)
  54
  55 /** OTG Interrupt Register */
  56 #define GOTGINT     BASE_REG(0x004)
  57
  58 /** Core AHB Configuration Register */
  59 #define GAHBCFG                         BASE_REG(0x008)
  60 #define GAHBCFG_glblintrmsk             (1 << 0) /** Global interrupt mask */
  61 #define GAHBCFG_hburstlen_bitp          1
  62 #define GAHBCFG_hburstlen_bits          0xf
  63 #define GAHBCFG_INT_DMA_BURST_SINGLE    0
  64 #define GAHBCFG_INT_DMA_BURST_INCR      1 /** note: the linux patch has several other value, this is one picked for internal dma */
  65 #define GAHBCFG_INT_DMA_BURST_INCR4     3
  66 #define GAHBCFG_INT_DMA_BURST_INCR8     5
  67 #define GAHBCFG_INT_DMA_BURST_INCR16    7
  68 #define GAHBCFG_dma_enable              (1 << 5) /** Enable DMA */
  69
  70 /** Core USB Configuration Register */
  71 #define GUSBCFG                         BASE_REG(0x00C)
  72 #define GUSBCFG_toutcal_bitp            0
  73 #define GUSBCFG_toutcal_bits            0x7
  74 #define GUSBCFG_phy_if                  (1 << 3) /** select utmi bus width ? */
  75 #define GUSBCFG_ulpi_utmi_sel           (1 << 4) /** select ulpi:1 or utmi:0 */
  76 #define GUSBCFG_fsintf                  (1 << 5)
  77 #define GUSBCFG_physel                  (1 << 6)
  78 #define GUSBCFG_ddrsel                  (1 << 7)
  79 #define GUSBCFG_srpcap                  (1 << 8)
  80 #define GUSBCFG_hnpcapp                 (1 << 9)
  81 #define GUSBCFG_usbtrdtim_bitp          10
  82 #define GUSBCFG_usbtrdtim_bits          0xf
  83 #define GUSBCFG_nptxfrwnden             (1 << 14)
  84 #define GUSBCFG_phylpwrclksel           (1 << 15)
  85 #define GUSBCFG_otgutmifssel            (1 << 16)
  86 #define GUSBCFG_ulpi_fsls               (1 << 17)
  87 #define GUSBCFG_ulpi_auto_res           (1 << 18)
  88 #define GUSBCFG_ulpi_clk_sus_m          (1 << 19)
  89 #define GUSBCFG_ulpi_ext_vbus_drv       (1 << 20)
  90 #define GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
  91 #define GUSBCFG_term_sel_dl_pulse       (1 << 22)
  92 #define GUSBCFG_force_host_mode         (1 << 29)
  93 #define GUSBCFG_force_device_mode       (1 << 30)
  94 #define GUSBCFG_corrupt_tx_packet       (1 << 31)
  95
  96 /** Core Reset Register */
  97 #define GRSTCTL                 BASE_REG(0x010)
  98 #define GRSTCTL_csftrst         (1 << 0) /** Core soft reset */
  99 #define GRSTCTL_hsftrst         (1 << 1) /** Hclk soft reset */
 100 #define GRSTCTL_intknqflsh      (1 << 3) /** In Token Sequence Learning Queue Flush */
 101 #define GRSTCTL_rxfflsh_flush   (1 << 4) /** RxFIFO Flush */
 102 #define GRSTCTL_txfflsh_flush   (1 << 5) /** TxFIFO Flush */
 103 #define GRSTCTL_txfnum_bitp     6 /** TxFIFO Number */
 104 #define GRSTCTL_txfnum_bits     0x1f
 105 #define GRSTCTL_ahbidle         (1 << 31) /** AHB idle state*/
 106
 107 /** Core Interrupt Register */
 108 #define GINTSTS             BASE_REG(0x014)
 109 /* NOTE: GINTSTS bits are the same as in GINTMSK plus this one */
 110 #define GINTSTS_curmode     (1 << 0) /** Current mode, 0 for device */
 111
 112 /** Core Interrupt Mask Register */
 113 #define GINTMSK                 BASE_REG(0x018)
 114 #define GINTMSK_modemismatch    (1 << 1) /** mode mismatch ? */
 115 #define GINTMSK_otgintr         (1 << 2)
 116 #define GINTMSK_sofintr         (1 << 3)
 117 #define GINTMSK_rxstsqlvl       (1 << 4)
 118 #define GINTMSK_nptxfempty      (1 << 5) /** Non-periodic TX fifo empty ? */
 119 #define GINTMSK_ginnakeff       (1 << 6)
 120 #define GINTMSK_goutnakeff      (1 << 7)
 121 #define GINTMSK_i2cintr         (1 << 9)
 122 #define GINTMSK_erlysuspend     (1 << 10)
 123 #define GINTMSK_usbsuspend      (1 << 11) /** USB suspend */
 124 #define GINTMSK_usbreset        (1 << 12) /** USB reset */
 125 #define GINTMSK_enumdone        (1 << 13) /** Enumeration done */
 126 #define GINTMSK_isooutdrop      (1 << 14)
 127 #define GINTMSK_eopframe        (1 << 15)
 128 #define GINTMSK_epmismatch      (1 << 17) /** endpoint mismatch ? */
 129 #define GINTMSK_inepintr        (1 << 18) /** in pending ? */
 130 #define GINTMSK_outepintr       (1 << 19) /** out pending ? */
 131 #define GINTMSK_incomplisoin    (1 << 20) /** ISP in complete ? */
 132 #define GINTMSK_incomplisoout   (1 << 21) /** ISO out complete ? */
 133 #define GINTMSK_portintr        (1 << 24) /** Port status change ? */
 134 #define GINTMSK_hcintr          (1 << 25)
 135 #define GINTMSK_ptxfempty       (1 << 26) /** Periodic TX fifof empty ? */
 136 #define GINTMSK_conidstschng    (1 << 28)
 137 #define GINTMSK_disconnect      (1 << 29) /** Disconnect */
 138 #define GINTMSK_sessreqintr     (1 << 30) /** Session request */
 139 #define GINTMSK_wkupintr        (1 << 31) /** Wake up */
 140
 141 /** Receive Status Debug Read Register (Read Only) */
 142 #define GRXSTSR     BASE_REG(0x01C)
 143
 144 /** Receive Status Read /Pop Register (Read Only) */
 145 #define GRXSTSP     BASE_REG(0x020)
 146
 147 /** Receive FIFO Size Register */
 148 #define GRXFSIZ     BASE_REG(0x024)
 149
 150 /** Periodic Transmit FIFO Size Register */
 151 #define GNPTXFSIZ   BASE_REG(0x028)
 152
 153 /** Non-Periodic Transmit FIFO/Queue Status Register */
 154 #define GNPTXSTS    BASE_REG(0x02C)
 155
 156 /** I2C Access Register */
 157 #define GI2CCTL     BASE_REG(0x030)
 158
 159 /** PHY Vendor Control Register */
 160 #define GPVNDCTL    BASE_REG(0x034)
 161
 162 /** General Purpose Input/Output Register */
 163 #define GGPIO       BASE_REG(0x038)
 164
 165 /** User ID Register */
 166 #define GUID        BASE_REG(0x03C)
 167
 168 /** Synopsys ID Register */
 169 #define GSNPSID     BASE_REG(0x040)
 170
 171 /** User HW Config1 Register */
 172 #define GHWCFG1                 BASE_REG(0x044)
 173 #define GHWCFG1_epdir_bitp(ep)  (2 * (ep))
 174 #define GHWCFG1_epdir_bits      0x3
 175 #define GHWCFG1_EPDIR_BIDIR     0
 176 #define GHWCFG1_EPDIR_IN        1
 177 #define GHWCFG1_EPDIR_OUT       2
 178
 179 /** User HW Config2 Register */
 180 #define GHWCFG2                     BASE_REG(0x048)
 181 #define GHWCFG2_arch_bitp           3 /** Architecture */
 182 #define GHWCFG2_arch_bits           0x3
 183 #define GHWCFG2_hs_phy_type_bitp    6 /** High speed PHY type */
 184 #define GHWCFG2_hs_phy_type_bits    0x3
 185 #define GHWCFG2_fs_phy_type_bitp    8 /** Full speed PHY type */
 186 #define GHWCFG2_fs_phy_type_bits    0x3
 187 #define GHWCFG2_num_ep_bitp         10 /** Number of endpoints */
 188 #define GHWCFG2_num_ep_bits         0xf
 189 #define GHWCFG2_dyn_fifo            (1 << 19) /** Dynamic FIFO */
 190 /* For GHWCFG2_HS_PHY_TYPE and GHWCFG2_FS_PHY_TYPE */
 191 #define GHWCFG2_PHY_TYPE_UNSUPPORTED        0
 192 #define GHWCFG2_PHY_TYPE_UTMI               1
 193 #define GHWCFG2_ARCH_INTERNAL_DMA           2
 194
 195 /** User HW Config3 Register */
 196 #define GHWCFG3                 BASE_REG(0x04C)
 197 #define GHWCFG3_dfifo_len_bitp  16 /** Total fifo size */
 198 #define GHWCFG3_dfifo_len_bits  0xffff
 199
 200 /** User HW Config4 Register */
 201 #define GHWCFG4                             BASE_REG(0x050)
 202 #define GHWCFG4_utmi_phy_data_width_bitp    14 /** UTMI+ data bus width */
 203 #define GHWCFG4_utmi_phy_data_width_bits    0x3
 204 #define GHWCFG4_ded_fifo_en                 (1 << 25) /** Dedicated Tx FIFOs */
 205 #define GHWCFG4_num_in_ep_bitp              26 /** Number of IN endpoints */
 206 #define GHWCFG4_num_in_ep_bits              0xf
 207
 208 /* 1<=ep<=15, don't use ep=0 !!! */
 209 /** Device IN Endpoint Transmit FIFO (ep) Size Register */
 210 #define DIEPTXFSIZ(ep)  BASE_REG(0x100 + 4 * (ep))
 211
 212 /** Build the content of a FIFO size register like DIEPTXFSIZ(i) and GNPTXFSIZ*/
 213 #define MAKE_FIFOSIZE_DATA(startadr, depth) \
 214     (((startadr) & 0xffff) | ((depth) << 16))
 215 /** Retrieve fifo size for such registers */
 216 #define GET_FIFOSIZE_DEPTH(data) \
 217     ((data) >> 16)
 218 /** Retrieve fifo start address for such registers */
 219 #define GET_FIFOSIZE_START_ADR(data) \
 220     ((data) & 0xffff)
 221
 222 /**
 223  * Device Registers Base Addresses
 224  */
 225 #define DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
 226
 227 /** Device Configuration Register */
 228 #define DCFG                    DEV_REG(0x00)
 229 #define DCFG_devspd_bitp        0 /** Device Speed */
 230 #define DCFG_devspd_bits        0x3
 231 #define DCFG_devspd_hs_phy_hs   0 /** High speed PHY running at high speed */
 232 #define DCFG_devspd_hs_phy_fs   1 /** High speed PHY running at full speed */
 233 #define DCFG_nzstsouthshk       (1 << 2) /** Non Zero Length Status OUT Handshake */
 234 #define DCFG_devadr_bitp        4 /** Device Address */
 235 #define DCFG_devadr_bits        0x7f
 236 #define DCFG_perfrint_bitp      11 /** Periodic Frame Interval */
 237 #define DCFG_perfrint_bits      0x3
 238 #define DCFG_FRAME_INTERVAL_80  0
 239 #define DCFG_FRAME_INTERVAL_85  1
 240 #define DCFG_FRAME_INTERVAL_90  2
 241 #define DCFG_FRAME_INTERVAL_95  3
 242
 243 /** Device Control Register */
 244 #define DCTL                DEV_REG(0x04)
 245 #define DCTL_rmtwkupsig     (1 << 0) /** Remote Wakeup */
 246 #define DCTL_sftdiscon      (1 << 1) /** Soft Disconnect */
 247 #define DCTL_gnpinnaksts    (1 << 2) /** Global Non-Periodic IN NAK Status */
 248 #define DCTL_goutnaksts     (1 << 3) /** Global OUT NAK Status */
 249 #define DCTL_tstctl_bitp    4 /** Test Control */
 250 #define DCTL_tstctl_bits    0x7
 251 #define DCTL_sgnpinnak      (1 << 7) /** Set Global Non-Periodic IN NAK */
 252 #define DCTL_cgnpinnak      (1 << 8) /** Clear Global Non-Periodic IN NAK */
 253 #define DCTL_sgoutnak       (1 << 9) /** Set Global OUT NAK */
 254 #define DCTL_cgoutnak       (1 << 10) /** Clear Global OUT NAK */
 255 #define DCTL_pwronprgdone   (1 << 11) /** Power on Program Done ? */
 256
 257 /** Device Status Register */
 258 #define DSTS                DEV_REG(0x08)
 259 #define DSTS_suspsts        (1 << 0) /** Suspend status */
 260 #define DSTS_enumspd_bitp   1 /** Enumerated speed */
 261 #define DSTS_enumspd_bits   0x3
 262 #define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
 263 #define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
 264 #define DSTS_ENUMSPD_LS_PHY_6MHZ           2
 265 #define DSTS_ENUMSPD_FS_PHY_48MHZ          3
 266 #define DSTS_errticerr      (1 << 3) /** Erratic errors ? */
 267 #define DSTS_soffn_bitp     8 /** Frame or Microframe Number of the received SOF */
 268 #define DSTS_soffn_bits     0x3fff
 269
 270 /** Device IN Endpoint Common Interrupt Mask Register */
 271 #define DIEPMSK                 DEV_REG(0x10)
 272 /* the following apply to DIEPMSK and DIEPINT */
 273 #define DIEPINT_xfercompl       (1 << 0) /** Transfer complete */
 274 #define DIEPINT_epdisabled      (1 << 1) /** Endpoint disabled */
 275 #define DIEPINT_ahberr          (1 << 2) /** AHB error */
 276 #define DIEPINT_timeout         (1 << 3) /** Timeout handshake (non-iso TX) */
 277 #define DIEPINT_intktxfemp      (1 << 4) /** IN token received with tx fifo empty */
 278 #define DIEPINT_intknepmis      (1 << 5) /** IN token received with ep mismatch */
 279 #define DIEPINT_inepnakeff      (1 << 6) /** IN endpoint NAK effective */
 280 #define DIEPINT_emptyintr       (1 << 7) /** linux doc broken on this, empty fifo ? */
 281 #define DIEPINT_txfifoundrn     (1 << 8) /** linux doc void on this, tx fifo underrun ? */
 282
 283 /** Device OUT Endpoint Common Interrupt Mask Register */
 284 #define DOEPMSK                 DEV_REG(0x14)
 285 /* the following apply to DOEPMSK and DOEPINT */
 286 #define DOEPINT_xfercompl       (1 << 0) /** Transfer complete */
 287 #define DOEPINT_epdisabled      (1 << 1) /** Endpoint disabled */
 288 #define DOEPINT_ahberr          (1 << 2) /** AHB error */
 289 #define DOEPINT_setup           (1 << 3) /** Setup Phase Done (control EPs)*/
 290
 291 /** Device All Endpoints Interrupt Register */
 292 #define DAINT               DEV_REG(0x18)
 293 /* valid for DAINT and DAINTMSK, for 0<=ep<=15 */
 294 #define DAINT_IN_EP(i)      (1 << (i))
 295 #define DAINT_OUT_EP(i)     (1 << ((i) + 16))
 296
 297 /** Device Endpoints Interrupt Mask Register */
 298 #define DAINTMSK    DEV_REG(0x1C)
 299
 300 /** Device IN Token Sequence Learning Queue Read Register 1 */
 301 #define DTKNQR1     DEV_REG(0x20)
 302
 303 /** Device IN Token Sequence Learning Queue Register 2 */
 304 #define DTKNQR2     DEV_REG(0x24)
 305
 306 /** Device IN Token Queue Pop register */
 307 #define DTKNQP      DEV_REG(0x28)
 308
 309 /* fixme: those registers are not present in registers.h but are in dwc_otgh_regs.h.
 310  *        the previous registers exists but has a different name :( */
 311 /** Device VBUS discharge register*/
 312 #define DVBUSDIS    DEV_REG(0x28)
 313
 314 /** Device VBUS pulse register */
 315 #define DVBUSPULSE  DEV_REG(0x2C)
 316
 317 /** Device IN Token Queue Read Register 3 (RO) */
 318 #define DTKNQR3     DEV_REG(0x30)
 319
 320 /** Device Thresholding control register */
 321 #define DTHRCTL                     DEV_REG(0x30)
 322 #define DTHRCTL_non_iso_thr_en      (1 << 0)
 323 #define DTHRCTL_iso_thr_en          (1 << 1)
 324 #define DTHRCTL_tx_thr_len_bitp     2
 325 #define DTHRCTL_tx_thr_len_bits     0x1FF
 326 #define DTHRCTL_rx_thr_en           (1 << 16)
 327 #define DTHRCTL_rx_thr_len_bitp     17
 328 #define DTHRCTL_rx_thr_len_bits     0x1FF
 329
 330 /** Device IN Token Queue Read Register 4 (RO) */
 331 #define DTKNQR4     DEV_REG(0x34)
 332
 333 /** Device IN EPs empty Inr. Mask Register */
 334 #define FFEMPTYMSK  DEV_REG(0x34)
 335
 336 #define PCGCCTL         BASE_REG(0xE00) /** Power and Clock Gating Control Register */
 337
 338 /** Device IN Endpoint (ep) Control Register */
 339 #define DIEPCTL(ep)     DEV_REG(0x100 + (ep) * 0x20)
 340 /** Device OUT Endpoint (ep) Control Register */
 341 #define DOEPCTL(ep)     DEV_REG(0x300 + (ep) * 0x20)
 342
 343 /** Maximum Packet Size
 344  * IN/OUT EPn
 345  * IN/OUT EP0 - 2 bits
 346  *  2'b00: 64 Bytes
 347  *  2'b01: 32
 348  *  2'b10: 16
 349  *  2'b11: 8 */
 350 #define DEPCTL_mps_bitp         0
 351 #define DEPCTL_mps_bits         0x7ff
 352 #define DEPCTL_MPS_64           0
 353 #define DEPCTL_MPS_32           1
 354 #define DEPCTL_MPS_16           2
 355 #define DEPCTL_MPS_8            3
 356 /** Next Endpoint
 357  * IN EPn/IN EP0
 358  * OUT EPn/OUT EP0 - reserved */
 359 #define DEPCTL_nextep_bitp      11
 360 #define DEPCTL_nextep_bits      0xf
 361 #define DEPCTL_usbactep         (1 << 15) /** USB Active Endpoint */
 362 /** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
 363  * This field contains the PID of the packet going to
 364  * be received or transmitted on this endpoint. The
 365  * application should program the PID of the first
 366  * packet going to be received or transmitted on this
 367  * endpoint , after the endpoint is
 368  * activated. Application use the SetD1PID and
 369  * SetD0PID fields of this register to program either
 370  * D0 or D1 PID.
 371  *
 372  * The encoding for this field is
 373  * - 0: D0
 374  * - 1: D1
 375  */
 376 #define DEPCTL_dpid             (1 << 16)
 377 #define DEPCTL_naksts           (1 << 17) /** NAK Status */
 378 /** Endpoint Type
 379  *  2'b00: Control
 380  *  2'b01: Isochronous
 381  *  2'b10: Bulk
 382  *  2'b11: Interrupt */
 383 #define DEPCTL_eptype_bitp      18
 384 #define DEPCTL_eptype_bits      0x3
 385 /** Snoop Mode
 386  * OUT EPn/OUT EP0
 387  * IN EPn/IN EP0 - reserved */
 388 #define DEPCTL_snp              (1 << 20)
 389 #define DEPCTL_stall            (1 << 21) /** Stall Handshake */
 390 /** Tx Fifo Number
 391  * IN EPn/IN EP0
 392  * OUT EPn/OUT EP0 - reserved */
 393 #define DEPCTL_txfnum_bitp      22
 394 #define DEPCTL_txfnum_bits      0xf
 395
 396 #define DEPCTL_cnak             (1 << 26) /** Clear NAK */
 397 #define DEPCTL_snak             (1 << 27) /** Set NAK */
 398 /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
 399  * Writing to this field sets the Endpoint DPID (DPID)
 400  * field in this register to DATA0. Set Even
 401  * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
 402  * Writing to this field sets the Even/Odd
 403  * (micro)frame (EO_FrNum) field to even (micro)
 404  * frame.
 405  */
 406 #define DEPCTL_setd0pid         (1 << 28)
 407 /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
 408  * Writing to this field sets the Endpoint DPID (DPID)
 409  * field in this register to DATA1 Set Odd
 410  * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
 411  * Writing to this field sets the Even/Odd
 412  * (micro)frame (EO_FrNum) field to odd (micro) frame.
 413  */
 414 #define DEPCTL_setd1pid         (1 << 29)
 415 #define DEPCTL_epdis            (1 << 30) /** Endpoint disable */
 416 #define DEPCTL_epena            (1 << 31) /** Endpoint enable */
 417
 418 /** Device IN Endpoint (ep) Transfer Size Register */
 419 #define DIEPTSIZ(ep)    DEV_REG(0x100 + (ep) * 0x20 + 0x10)
 420 /** Device OUT Endpoint (ep) Transfer Size Register */
 421 #define DOEPTSIZ(ep)    DEV_REG(0x300 + (ep) * 0x20 + 0x10)
 422
 423 /* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
 424 #define DEPTSIZ_xfersize_bits   0x7ffff /** Transfer Size */
 425 #define DEPTSIZ_pkcnt_bitp      19 /** Packet Count */
 426 #define DEPTSIZ_pkcnt_bits      0x3ff
 427 #define DEPTSIZ_mc_bitp         29 /** Multi Count - Periodic IN endpoints */
 428 #define DEPTSIZ_mc_bits         0x3
 429
 430 /* idem but for i=0 */
 431 #define DEPTSIZ0_xfersize_bitp  0 /** Transfer Size */
 432 #define DEPTSIZ0_xfersize_bits  0x7f
 433 #define DEPTSIZ0_pkcnt_bitp     19 /** Packet Count */
 434 #define DEPTSIZ0_pkcnt_bits     0x3
 435 #define DEPTSIZ0_supcnt_bitp    29 /** Setup Packet Count (DOEPTSIZ0 Only) */
 436 #define DEPTSIZ0_supcnt_bits    0x3
 437
 438 /** Device IN Endpoint (ep) Interrupt Register */
 439 #define DIEPINT(ep)     DEV_REG(0x100 + (ep) * 0x20 + 0x8)
 440 /** Device IN Endpoint (ep) DMA Address Register */
 441 #define DIEPDMA(ep)     DEV_REG(0x100 + (ep) * 0x20 + 0x14)
 442 /** Device IN Endpoint (ep) Transmit FIFO Status Register */
 443 #define DTXFSTS(ep)     DEV_REG(0x100 + (ep) * 0x20 + 0x18)
 444
 445 /** Device OUT Endpoint (ep) Frame number Register */
 446 #define DOEPFN(ep)      DEV_REG(0x300 + (ep) * 0x20 + 0x4)
 447 /** Device Endpoint (ep) Interrupt Register */
 448 #define DOEPINT(ep)     DEV_REG(0x300 + (ep) * 0x20 + 0x8)
 449 /** Device Endpoint (ep) DMA Address Register */
 450 #define DOEPDMA(ep)     DEV_REG(0x300 + (ep) * 0x20 + 0x14)
 451
 452 /**
 453  * Parameters
 454  */
 455 #define USE_CUSTOM_FIFO_LAYOUT
 456
 457 #ifdef USE_CUSTOM_FIFO_LAYOUT
 458 /* Data fifo: includes RX fifo, non period TX fifo and periodic fifos
 459  * NOTE: this is a hardware parameter, it cannot be changed ! */
 460 #define DATA_FIFO_DEPTH     0x535
 461 /* size of the FX fifo */
 462 #define RX_FIFO_SIZE        0x100
 463 /* size of the non periodic TX fifo */
 464 #define NPTX_FIFO_SIZE      0x100
 465 /* size of each TX ep fifo size */
 466 #define EPTX_FIFO_SIZE      0x100
 467 #endif /* USE_CUSTOM_FIFO_LAYOUT */
 468
 469 /* Number of IN/OUT endpoints */
 470 #define NUM_IN_EP           3
 471 #define NUM_OUT_EP          2
 472
 473 /* List of IN enpoints */
 474 #define IN_EP_LIST          1, 3, 5
 475 #define OUT_EP_LIST         2, 4
 476
 477 #endif /* __USB_DRV_AS3525v2_H__ */