firmware/target/arm/as3525/usb-drv-as3525v2.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright © 2010 Amaury Pouly
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21
  22 #include "usb.h"
  23 #include "usb_drv.h"
  24 #include "as3525v2.h"
  25 #include "clock-target.h"
  26 #include "ascodec.h"
  27 #include "as3514.h"
  28 #include "stdbool.h"
  29 #include "string.h"
  30 #include "stdio.h"
  31 #include "panic.h"
  32 #include "mmu-arm.h"
  33 #include "system.h"
  34 #define LOGF_ENABLE
  35 #include "logf.h"
  36 #include "usb-drv-as3525v2.h"
  37 #include "usb_core.h"
  38
  39 static int __in_ep_list[NUM_IN_EP] = {IN_EP_LIST};
  40 static int __out_ep_list[NUM_OUT_EP] = {OUT_EP_LIST};
  41
  42 /* iterate through each in/out ep except EP0
  43  * 'counter' is the counter, 'ep' is the actual value */
  44 #define FOR_EACH_IN_EP(counter, ep) \
  45     for(counter = 0, ep = __in_ep_list[0]; counter < NUM_IN_EP; counter++, ep = __in_ep_list[counter])
  46
  47 #define FOR_EACH_OUT_EP(counter, ep) \
  48     for(counter = 0, ep = __out_ep_list[0]; counter < NUM_OUT_EP; counter++, ep = __out_ep_list[counter])
  49
  50 struct usb_endpoint
  51 {
  52     void *buf;
  53     unsigned int len;
  54     union
  55     {
  56         unsigned int sent;
  57         unsigned int received;
  58     };
  59     bool wait;
  60     bool busy;
  61 };
  62
  63 #if 0
  64 static struct usb_endpoint endpoints[USB_NUM_ENDPOINTS*2];
  65 #endif
  66 static struct usb_ctrlrequest ep0_setup_pkt __attribute__((aligned(16)));
  67
  68 void usb_attach(void)
  69 {
  70     logf("usb: attach");
  71     usb_enable(true);
  72 }
  73
  74 static void usb_delay(void)
  75 {
  76     int i = 0;
  77     while(i < 0x300)
  78     {
  79         asm volatile("nop");
  80         i++;
  81     }
  82 }
  83
  84 static void as3525v2_connect(void)
  85 {
  86     logf("usb: init as3525v2");
  87     /* 1) enable usb core clock */
  88     CGU_PERI |= CGU_USB_CLOCK_ENABLE;
  89     usb_delay();
  90     /* 2) enable usb phy clock */
  91     /* PHY clock */
  92     CGU_USB = 1<<5 /* enable */
  93         | (CLK_DIV(AS3525_PLLA_FREQ, 60000000)) << 2
  94         | 1; /* source = PLLA */
  95     usb_delay();
  96     /* 3) clear "stop pclk" */
  97     PCGCCTL &= ~0x1;
  98     usb_delay();
  99     /* 4) clear "power clamp" */
 100     PCGCCTL &= ~0x4;
 101     usb_delay();
 102     /* 5) clear "reset power down module" */
 103     PCGCCTL &= ~0x8;
 104     usb_delay();
 105     /* 6) set "power on program done" */
 106     DCTL |= DCTL_pwronprgdone;
 107     usb_delay();
 108     /* 7) core soft reset */
 109     GRSTCTL |= GRSTCTL_csftrst;
 110     usb_delay();
 111     /* 8) hclk soft reset */
 112     GRSTCTL |= GRSTCTL_hsftrst;
 113     usb_delay();
 114     /* 9) flush and reset everything */
 115     GRSTCTL |= 0x3f;
 116     usb_delay();
 117     /* 10) force device mode*/
 118     GUSBCFG &= ~GUSBCFG_force_host_mode;
 119     GUSBCFG |= GUSBCFG_force_device_mode;
 120     usb_delay();
 121     /* 11) Do something that is probably CCU related but undocumented*/
 122     CCU_USB_THINGY &= ~0x1000;
 123     usb_delay();
 124     CCU_USB_THINGY &= ~0x300000;
 125     usb_delay();
 126     /* 12) reset usb core parameters (dev addr, speed, ...) */
 127     DCFG = 0;
 128     usb_delay();
 129 }
 130
 131 static void enable_device_interrupts(void)
 132 {
 133     /* Clear any pending interrupt */
 134     GINTSTS = 0xffffffff;
 135     /* Clear any pending otg interrupt */
 136     GOTGINT = 0xffffffff;
 137     /* Enable interrupts */
 138     GINTMSK = GINTMSK_usbreset
 139                 | GINTMSK_enumdone
 140                 | GINTMSK_inepintr
 141                 | GINTMSK_outepintr
 142                 | GINTMSK_otgintr
 143                 | GINTMSK_disconnect;
 144 }
 145
 146 static void flush_tx_fifos(int nums)
 147 {
 148     unsigned int i = 0;
 149
 150     GRSTCTL = (nums << GRSTCTL_txfnum_bitp)
 151             | GRSTCTL_txfflsh_flush;
 152     while(GRSTCTL & GRSTCTL_txfflsh_flush && i < 0x300)
 153         i++;
 154     if(GRSTCTL & GRSTCTL_txfflsh_flush)
 155         panicf("usb: hang of flush tx fifos (%x)", nums);
 156     /* wait 3 phy clocks */
 157     udelay(1);
 158 }
 159
 160 static void reset_endpoints(void)
 161 {
 162     int i, ep;
 163     /* disable all endpoints except EP0 */
 164     FOR_EACH_IN_EP(i, ep)
 165         if(DIEPCTL(ep) & DEPCTL_epena)
 166             DIEPCTL(ep) =  DEPCTL_epdis | DEPCTL_snak;
 167         else
 168             DIEPCTL(ep) = 0;
 169
 170     FOR_EACH_OUT_EP(i, ep)
 171         if(DOEPCTL(ep) & DEPCTL_epena)
 172             DOEPCTL(ep) =  DEPCTL_epdis | DEPCTL_snak;
 173         else
 174             DOEPCTL(ep) = 0;
 175     /* Setup EP0 OUT with the following parameters:
 176      * packet count = 1
 177      * setup packet count = 1
 178      * transfer size = 64
 179      * Setup EP0 IN/OUT with 64 byte maximum packet size and activate both. Enable transfer on EP0 OUT
 180      */
 181
 182     DOEPTSIZ(0) = (1 << DEPTSIZ0_supcnt_bitp)
 183                 | (1 << DEPTSIZ0_pkcnt_bitp)
 184                 | 8;
 185
 186     /* setup DMA */
 187     clean_dcache_range((void*)&ep0_setup_pkt, sizeof ep0_setup_pkt);  /* force write back */
 188     DOEPDMA(0) = (unsigned long)&ep0_setup_pkt; /* virtual address=physical address */
 189
 190     /* Enable endpoint, clear nak */
 191     DOEPCTL(0) = DEPCTL_epena | DEPCTL_cnak | DEPCTL_usbactep
 192                 | (DEPCTL_MPS_64 << DEPCTL_mps_bitp);
 193
 194     /* 64 bytes packet size, active endpoint */
 195     DIEPCTL(0) = (DEPCTL_MPS_64 << DEPCTL_mps_bitp)
 196                 | DEPCTL_usbactep;
 197 }
 198
 199 static void core_dev_init(void)
 200 {
 201     unsigned int num_in_ep = 0;
 202     unsigned int num_out_ep = 0;
 203     unsigned int i;
 204     /* Restart the phy clock */
 205     PCGCCTL = 0;
 206     /* Set phy speed : high speed */
 207     DCFG = (DCFG & ~bitm(DCFG, devspd)) | DCFG_devspd_hs_phy_hs;
 208
 209     /* Check hardware capabilities */
 210     if(extract(GHWCFG2, arch) != GHWCFG2_ARCH_INTERNAL_DMA)
 211         panicf("usb: wrong architecture (%ld)", extract(GHWCFG2, arch));
 212     if(extract(GHWCFG2, hs_phy_type) != GHWCFG2_PHY_TYPE_UTMI)
 213         panicf("usb: wrong HS phy type (%ld)", extract(GHWCFG2, hs_phy_type));
 214     if(extract(GHWCFG2, fs_phy_type) != GHWCFG2_PHY_TYPE_UNSUPPORTED)
 215         panicf("usb: wrong FS phy type (%ld)", extract(GHWCFG2, fs_phy_type));
 216     if(extract(GHWCFG4, utmi_phy_data_width) != 0x2)
 217         panicf("usb: wrong utmi data width (%ld)", extract(GHWCFG4, utmi_phy_data_width));
 218     if(!(GHWCFG4 & GHWCFG4_ded_fifo_en)) /* it seems to be multiple tx fifo support */
 219         panicf("usb: no multiple tx fifo");
 220
 221     #ifdef USE_CUSTOM_FIFO_LAYOUT
 222     if(!(GHWCFG2 & GHWCFG2_dyn_fifo))
 223         panicf("usb: no dynamic fifo");
 224     if(GRXFSIZ != DATA_FIFO_DEPTH)
 225         panicf("usb: wrong data fifo size");
 226     #endif /* USE_CUSTOM_FIFO_LAYOUT */
 227
 228     /* do some logging */
 229     logf("hwcfg1: %08lx", GHWCFG1);
 230     logf("hwcfg2: %08lx", GHWCFG2);
 231     logf("hwcfg3: %08lx", GHWCFG3);
 232     logf("hwcfg4: %08lx", GHWCFG4);
 233
 234     logf("%ld endpoints", extract(GHWCFG2, num_ep));
 235     num_in_ep = 0;
 236     num_out_ep = 0;
 237     for(i = 0; i < extract(GHWCFG2, num_ep); i++)
 238     {
 239         bool in = false, out = false;
 240         switch((GHWCFG1 >> GHWCFG1_epdir_bitp(i)) & GHWCFG1_epdir_bits)
 241         {
 242             case GHWCFG1_EPDIR_BIDIR: in = out = true; break;
 243             case GHWCFG1_EPDIR_IN: in = true; break;
 244             case GHWCFG1_EPDIR_OUT: out = true; break;
 245             default: panicf("usb: invalid epdir");
 246         }
 247         /* don't count EP0 which is special and always bidirectional */
 248         if(in && i != 0)
 249             num_in_ep++;
 250         if(out && i != 0)
 251             num_out_ep++;
 252         logf("  EP%d: IN=%s OUT=%s", i, in ? "yes" : "no", out ? "yes" : "no");
 253     }
 254
 255     if(num_in_ep != extract(GHWCFG4, num_in_ep))
 256         panicf("usb: num in ep mismatch(%d,%lu)", num_in_ep, extract(GHWCFG4, num_in_ep));
 257     if(num_in_ep != NUM_IN_EP)
 258         panicf("usb: num in ep static mismatch(%u,%u)", num_in_ep, NUM_IN_EP);
 259     if(num_out_ep != NUM_OUT_EP)
 260         panicf("usb: num out ep static mismatch(%u,%u)", num_out_ep, NUM_OUT_EP);
 261
 262     logf("%d in ep, %d out ep", num_in_ep, num_out_ep);
 263
 264     logf("initial:");
 265     logf("  tot fifo sz: %lx", extract(GHWCFG3, dfifo_len));
 266     logf("  rx fifo: [%04x,+%4lx]", 0, GRXFSIZ);
 267     logf("  nptx fifo: [%04lx,+%4lx]", GET_FIFOSIZE_START_ADR(GNPTXFSIZ),
 268         GET_FIFOSIZE_DEPTH(GNPTXFSIZ));
 269
 270     #ifdef USE_CUSTOM_FIFO_LAYOUT
 271     /* Setup FIFOs */
 272     /* Organize FIFO as follow:
 273      *             0           ->         rxfsize         : RX fifo
 274      *          rxfsize        ->   rxfsize + nptxfsize   : TX fifo for first IN ep
 275      *   rxfsize + nptxfsize   -> rxfsize + 2 * nptxfsize : TX fifo for second IN ep
 276      * rxfsize + 2 * nptxfsize -> rxfsize + 3 * nptxfsize : TX fifo for third IN ep
 277      * ...
 278      */
 279
 280     unsigned short adr = 0;
 281     unsigned short depth = RX_FIFO_SIZE;
 282     GRXFSIZ = depth;
 283     adr += depth;
 284     depth = NPTX_FIFO_SIZE;
 285     GNPTXFSIZ = MAKE_FIFOSIZE_DATA(adr, depth);
 286     adr += depth;
 287
 288     for(i = 1; i <= NUM_IN_EP; i++)
 289     {
 290         depth = EPTX_FIFO_SIZE;
 291         DIEPTXFSIZ(i) = MAKE_FIFOSIZE_DATA(adr, depth);
 292         adr += depth;
 293     }
 294
 295     if(adr > DATA_FIFO_DEPTH)
 296         panicf("usb: total data fifo size exceeded");
 297     #endif /* USE_CUSTOM_FIFO_LAYOUT */
 298
 299     for(i = 1; i <= NUM_IN_EP; i++)
 300     {
 301         logf("  dieptx fifo(%2u): [%04lx,+%4lx]", i,
 302             GET_FIFOSIZE_START_ADR(DIEPTXFSIZ(i)),
 303             GET_FIFOSIZE_DEPTH(DIEPTXFSIZ(i)));
 304     }
 305
 306     /* Setup interrupt masks for endpoints */
 307     /* Setup interrupt masks */
 308     DOEPMSK = DOEPINT_setup | DOEPINT_xfercompl | DOEPINT_ahberr
 309                 | DOEPINT_epdisabled;
 310     DIEPMSK = DIEPINT_xfercompl | DIEPINT_timeout
 311                 | DIEPINT_epdisabled | DIEPINT_ahberr;
 312     DAINTMSK = 0xffffffff;
 313
 314     reset_endpoints();
 315
 316     /* fixme: threshold tweaking only takes place if we use multiple tx fifos it seems */
 317     /* only dump them for now, leave threshold disabled */
 318     /*
 319     logf("threshold control:");
 320     logf("  non_iso_thr_en: %d", (DTHRCTL & DTHRCTL_non_iso_thr_en) ? 1 : 0);
 321     logf("  iso_thr_en: %d", (DTHRCTL & DTHRCTL_iso_thr_en) ? 1 : 0);
 322     logf("  tx_thr_len: %lu", extract(DTHRCTL, tx_thr_len));
 323     logf("  rx_thr_en: %d", (DTHRCTL & DTHRCTL_rx_thr_en) ? 1 : 0);
 324     logf("  rx_thr_len: %lu", extract(DTHRCTL, rx_thr_len));
 325     */
 326
 327     /* enable USB interrupts */
 328     enable_device_interrupts();
 329 }
 330
 331 static void core_init(void)
 332 {
 333     /* Disconnect */
 334     DCTL |= DCTL_sftdiscon;
 335     /* Select UTMI+ 16 */
 336     GUSBCFG |= GUSBCFG_phy_if;
 337
 338     /* fixme: the current code is for internal DMA only, the clip+ architecture
 339      *        define the internal DMA model */
 340     /* Set burstlen and enable DMA*/
 341     GAHBCFG = (GAHBCFG_INT_DMA_BURST_INCR4 << GAHBCFG_hburstlen_bitp)
 342                 | GAHBCFG_dma_enable;
 343     /* Disable HNP and SRP, not sure it's useful because we already forced dev mode */
 344     GUSBCFG &= ~(GUSBCFG_srpcap | GUSBCFG_hnpcapp);
 345
 346     /* perform device model specific init */
 347     core_dev_init();
 348
 349     /* Reconnect */
 350     DCTL &= ~DCTL_sftdiscon;
 351 }
 352
 353 static void enable_global_interrupts(void)
 354 {
 355     VIC_INT_ENABLE = INTERRUPT_USB;
 356     GAHBCFG |= GAHBCFG_glblintrmsk;
 357 }
 358
 359 static void disable_global_interrupts(void)
 360 {
 361     GAHBCFG &= ~GAHBCFG_glblintrmsk;
 362     VIC_INT_EN_CLEAR = INTERRUPT_USB;
 363 }
 364
 365 void usb_drv_init(void)
 366 {
 367     logf("usb_drv_init");
 368     /* Enable PHY and clocks (but leave pullups disabled) */
 369     as3525v2_connect();
 370     logf("usb: synopsis id: %lx", GSNPSID);
 371     /* Core init */
 372     core_init();
 373     /* Enable global interrupts */
 374     enable_global_interrupts();
 375 }
 376
 377 void usb_drv_exit(void)
 378 {
 379     logf("usb_drv_exit");
 380
 381     disable_global_interrupts();
 382 }
 383
 384 static void dump_regs(void)
 385 {
 386     logf("DSTS: %lx", DSTS);
 387     logf("DOEPCTL0=%lx", DOEPCTL(0));
 388     logf("DOEPTSIZ=%lx", DOEPTSIZ(0));
 389     logf("DIEPCTL0=%lx", DIEPCTL(0));
 390     logf("DOEPMSK=%lx", DOEPMSK);
 391     logf("DIEPMSK=%lx", DIEPMSK);
 392     logf("DAINTMSK=%lx", DAINTMSK);
 393     logf("DAINT=%lx", DAINT);
 394     logf("GINTSTS=%lx", GINTSTS);
 395     logf("GINTMSK=%lx", GINTMSK);
 396     logf("DCTL=%lx", DCTL);
 397     logf("GAHBCFG=%lx", GAHBCFG);
 398     logf("GUSBCFG=%lx", GUSBCFG);
 399     logf("DCFG=%lx", DCFG);
 400     logf("DTHRCTL=%lx", DTHRCTL);
 401 }
 402
 403 static bool handle_reset(void)
 404 {
 405     logf("usb: bus reset");
 406
 407     dump_regs();
 408     /* Clear the Remote Wakeup Signalling */
 409     DCTL &= ~DCTL_rmtwkupsig;
 410
 411     /* Flush FIFOs */
 412     flush_tx_fifos(0x10);
 413
 414     reset_endpoints();
 415
 416     /* Reset Device Address */
 417     DCFG &= bitm(DCFG, devadr);
 418
 419     usb_core_bus_reset();
 420
 421     return true;
 422 }
 423
 424 static bool handle_enum_done(void)
 425 {
 426     logf("usb: enum done");
 427
 428     /* read speed */
 429     switch(extract(DSTS, enumspd))
 430     {
 431         case DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ:
 432             logf("usb: HS");
 433             break;
 434         case DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ:
 435         case DSTS_ENUMSPD_FS_PHY_48MHZ:
 436             logf("usb: FS");
 437             break;
 438         case DSTS_ENUMSPD_LS_PHY_6MHZ:
 439             panicf("usb: LS is not supported");
 440     }
 441
 442     /* fixme: change EP0 mps here */
 443     dump_regs();
 444
 445     return true;
 446 }
 447
 448 static bool handle_in_ep_int(void)
 449 {
 450     panicf("usb: in ep int");
 451     return false;
 452 }
 453
 454 static bool handle_out_ep_int(void)
 455 {
 456     panicf("usb: out ep int");
 457     return false;
 458 }
 459
 460 /* interrupt service routine */
 461 void INT_USB(void)
 462 {
 463     /* some bits in GINTSTS can be set even though we didn't enable the interrupt source
 464      * so AND it with the actual mask */
 465     unsigned long sts = GINTSTS & GINTMSK;
 466     unsigned long handled_one = 0; /* mask of all listed one (either handled or not) */
 467
 468     #define HANDLED_CASE(bitmask, callfn) \
 469         handled_one |= bitmask; \
 470         if(sts & bitmask) \
 471         { \
 472             if(!callfn()) \
 473                 goto Lerr; \
 474         }
 475
 476     #define UNHANDLED_CASE(bitmask) \
 477         handled_one |= bitmask; \
 478         if(sts & bitmask) \
 479             goto Lunhandled;
 480
 481     /* device part */
 482     HANDLED_CASE(GINTMSK_usbreset, handle_reset)
 483     HANDLED_CASE(GINTMSK_enumdone, handle_enum_done)
 484     HANDLED_CASE(GINTMSK_inepintr, handle_in_ep_int)
 485     HANDLED_CASE(GINTMSK_outepintr, handle_out_ep_int)
 486
 487     /* common part */
 488     UNHANDLED_CASE(GINTMSK_otgintr)
 489     UNHANDLED_CASE(GINTMSK_conidstschng)
 490     UNHANDLED_CASE(GINTMSK_disconnect)
 491
 492     /* unlisted ones */
 493     if(sts & ~handled_one)
 494         goto Lunhandled;
 495
 496     GINTSTS = GINTSTS;
 497
 498     return;
 499
 500     Lunhandled:
 501     panicf("unhandled usb int: %lx", sts);
 502
 503     Lerr:
 504     panicf("error in usb int: %lx", sts);
 505 }
 506
 507 int usb_drv_port_speed(void)
 508 {
 509     return 0;
 510 }
 511
 512 int usb_drv_request_endpoint(int type, int dir)
 513 {
 514     (void) type;
 515     (void) dir;
 516     return -1;
 517 }
 518
 519 void usb_drv_release_endpoint(int ep)
 520 {
 521     (void) ep;
 522 }
 523
 524 void usb_drv_cancel_all_transfers(void)
 525 {
 526 }
 527
 528 int usb_drv_recv(int ep, void *ptr, int len)
 529 {
 530     (void) ep;
 531     (void) ptr;
 532     (void) len;
 533     return -1;
 534 }
 535
 536 int usb_drv_send(int ep, void *ptr, int len)
 537 {
 538     (void) ep;
 539     (void) ptr;
 540     (void) len;
 541     return -1;
 542 }
 543
 544 int usb_drv_send_nonblocking(int ep, void *ptr, int len)
 545 {
 546     (void) ep;
 547     (void) ptr;
 548     (void) len;
 549     return -1;
 550 }
 551
 552
 553 void usb_drv_set_test_mode(int mode)
 554 {
 555     (void) mode;
 556 }
 557
 558 void usb_drv_set_address(int address)
 559 {
 560     (void) address;
 561 }
 562
 563 void usb_drv_stall(int ep, bool stall, bool in)
 564 {
 565     (void) ep;
 566     (void) stall;
 567     (void) in;
 568 }
 569
 570 bool usb_drv_stalled(int ep, bool in)
 571 {
 572     (void) ep;
 573     (void) in;
 574     return true;
 575 }
 576