1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2007 by Will Robertson
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation; either version 2
15 * of the License, or (at your option) any later version.
17 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
18 * KIND, either express or implied.
20 ****************************************************************************/
29 #include "ata-target.h"
30 #include "ccm-imx31.h"
32 #include "sdma-imx31.h"
33 #include "mmu-imx31.h"
36 /* PIO modes timing info */
37 static const struct ata_pio_timings
39 uint16_t time_2w
; /* t2 during write */
40 uint16_t time_2r
; /* t2 during read */
41 uint8_t time_ax
; /* tA */
42 uint8_t time_1
; /* t1 */
43 uint8_t time_4
; /* t4 */
44 uint8_t time_9
; /* t9 */
47 [0] = /* PIO mode 0 */
56 [1] = /* PIO mode 1 */
65 [2] = /* PIO mode 2 */
74 [3] = /* PIO mode 3 */
83 [4] = /* PIO mode 4 */
94 /* Track first init */
95 static bool initialized
= false;
98 /* One DMA channel for reads, the other for writes othewise one channel would
99 * have to be reinitialized every time the direction changed. (Different
100 * SDMA scripts are used for reading or writing) */
101 #define ATA_DMA_CH_NUM_RD 3
102 #define ATA_DMA_CH_NUM_WR 4
103 /* Use default priority for these channels (1) - ATA isn't realtime urgent. */
104 /* Maximum DMA size per buffer descriptor (32-byte aligned) */
105 #define ATA_MAX_BD_SIZE (65534 & ~31) /* 65504 */
107 /* Number of buffer descriptors required for a maximum sector count trasfer.
108 * NOTE: Assumes LBA28 and 512-byte sectors! */
109 #define ATA_BASE_BD_COUNT ((256*512 + (ATA_MAX_BD_SIZE-1)) / ATA_MAX_BD_SIZE)
110 #define ATA_BD_COUNT (ATA_BASE_BD_COUNT + 2)
112 static const struct ata_mdma_timings
114 uint8_t time_m
; /* tM */
115 uint8_t time_jn
; /* tH */
116 uint8_t time_d
; /* tD */
117 uint8_t time_k
; /* tKW */
120 [0] = /* MDMA mode 0 */
127 [1] = /* MDMA mode 1 */
134 [2] = /* MDMA mode 2 */
143 static const struct ata_udma_timings
145 uint8_t time_ack
; /* tACK */
146 uint8_t time_env
; /* tENV */
147 uint8_t time_rpx
; /* tRP */
148 uint8_t time_zah
; /* tZAH */
149 uint8_t time_mlix
; /* tMLI */
150 uint8_t time_dvh
; /* tDVH */
151 uint8_t time_dzfs
; /* tDVS+tDVH? */
152 uint8_t time_dvs
; /* tDVS */
153 uint8_t time_cvh
; /* ?? */
154 uint8_t time_ss
; /* tSS */
155 uint8_t time_cyc
; /* tCYC */
158 [0] = /* UDMA mode 0 */
172 [1] = /* UDMA mode 1 */
186 [2] = /* UDMA mode 2 */
200 [3] = /* UDMA mode 3 */
214 [4] = /* UDMA mode 4 */
229 [5] = /* UDMA mode 5 (bus clock 80MHz or higher only) */
247 /* Signal to tell thread when DMA is done */
248 static struct wakeup ata_dma_wakeup
;
251 /* Array of buffer descriptors for large transfers and alignnment */
252 static struct buffer_descriptor ata_bda
[ATA_BD_COUNT
] NOCACHEBSS_ATTR
;
253 /* ATA channel descriptors */
254 static struct channel_descriptor ata_cd_rd NOCACHEBSS_ATTR
; /* read channel */
255 static struct channel_descriptor ata_cd_wr NOCACHEBSS_ATTR
; /* write channel */
256 /* DMA channel to be started for transfer */
257 static unsigned int current_channel
= 0;
260 /* Scatter buffer for first and last 32 bytes of a non cache-aligned transfer
262 static uint32_t scatter_buffer
[32/4*2] NOCACHEBSS_ATTR
;
263 /* Address of ends in destination buffer for unaligned reads - copied after
265 static void *sb_dst
[2] = { NULL
, NULL
};
268 #define ATA_DMA_MWDMA 0x00000000 /* Using multiword DMA */
269 #define ATA_DMA_UDMA ATA_DMA_ULTRA_SELECTED /* Using Ultra DMA */
270 #define ATA_DMA_PIO 0x80000000 /* Using PIO */
271 #define ATA_DMA_DISABLED 0x80000001 /* DMA init error - use PIO */
272 static unsigned long ata_dma_selected
= ATA_DMA_PIO
;
273 #endif /* HAVE_ATA_DMA */
275 static unsigned int get_T(void)
277 /* T = ATA clock period in nanoseconds */
278 return 1000 * 1000 * 1000 / ccm_get_ata_clk();
281 static void ata_wait_for_idle(void)
283 while (!(ATA_INTERRUPT_PENDING
& ATA_CONTROLLER_IDLE
));
286 /* Route the INTRQ to either the MCU or SDMA depending upon whether there is
287 * a DMA transfer in progress. */
288 static inline void ata_set_intrq(bool to_dma
)
290 ATA_INTERRUPT_ENABLE
=
291 (ATA_INTERRUPT_ENABLE
& ~(ATA_INTRQ1
| ATA_INTRQ2
)) |
292 (to_dma
? ATA_INTRQ1
: ATA_INTRQ2
);
295 /* Setup the timing for PIO mode */
296 void ata_set_pio_timings(int mode
)
298 const struct ata_pio_timings
* const timings
= &pio_timings
[mode
];
299 unsigned int T
= get_T();
303 ATA_TIME_1
= (timings
->time_1
+ T
) / T
;
304 ATA_TIME_2W
= (timings
->time_2w
+ T
) / T
;
305 ATA_TIME_2R
= (timings
->time_2r
+ T
) / T
;
306 ATA_TIME_AX
= (timings
->time_ax
+ T
) / T
+ 2; /* 1.5 + tAX */
307 ATA_TIME_PIO_RDX
= 1;
308 ATA_TIME_4
= (timings
->time_4
+ T
) / T
;
309 ATA_TIME_9
= (timings
->time_9
+ T
) / T
;
314 /* Be sure we're not busy */
317 ATA_INTF_CONTROL
&= ~(ATA_ATA_RST
| ATA_FIFO_RST
);
319 ATA_INTF_CONTROL
= ATA_ATA_RST
| ATA_FIFO_RST
;
325 void ata_enable(bool on
)
327 /* Unconditionally clock module before writing regs */
328 ccm_module_clock_gating(CG_ATA
, CGM_ON_RUN_WAIT
);
333 ATA_INTF_CONTROL
= ATA_ATA_RST
| ATA_FIFO_RST
;
338 ATA_INTF_CONTROL
&= ~(ATA_ATA_RST
| ATA_FIFO_RST
);
341 /* Disable off - unclock ATA module */
342 ccm_module_clock_gating(CG_ATA
, CGM_OFF
);
346 bool ata_is_coldstart(void)
352 static void ata_set_mdma_timings(unsigned int mode
)
354 const struct ata_mdma_timings
* const timings
= &mdma_timings
[mode
];
355 unsigned int T
= get_T();
357 ATA_TIME_M
= (timings
->time_m
+ T
) / T
;
358 ATA_TIME_JN
= (timings
->time_jn
+ T
) / T
;
359 ATA_TIME_D
= (timings
->time_d
+ T
) / T
;
360 ATA_TIME_K
= (timings
->time_k
+ T
) / T
;
363 static void ata_set_udma_timings(unsigned int mode
)
365 const struct ata_udma_timings
* const timings
= &udma_timings
[mode
];
366 unsigned int T
= get_T();
368 ATA_TIME_ACK
= (timings
->time_ack
+ T
) / T
;
369 ATA_TIME_ENV
= (timings
->time_env
+ T
) / T
;
370 ATA_TIME_RPX
= (timings
->time_rpx
+ T
) / T
;
371 ATA_TIME_ZAH
= (timings
->time_zah
+ T
) / T
;
372 ATA_TIME_MLIX
= (timings
->time_mlix
+ T
) / T
;
373 ATA_TIME_DVH
= (timings
->time_dvh
+ T
) / T
+ 1;
374 ATA_TIME_DZFS
= (timings
->time_dzfs
+ T
) / T
;
375 ATA_TIME_DVS
= (timings
->time_dvs
+ T
) / T
;
376 ATA_TIME_CVH
= (timings
->time_cvh
+ T
) / T
;
377 ATA_TIME_SS
= (timings
->time_ss
+ T
) / T
;
378 ATA_TIME_CYC
= (timings
->time_cyc
+ T
) / T
;
381 void ata_dma_set_mode(unsigned char mode
)
383 unsigned int modeidx
= mode
& 0x07;
384 unsigned int dmamode
= mode
& 0xf8;
388 if (ata_dma_selected
== ATA_DMA_DISABLED
)
390 /* Configuration error - no DMA */
392 else if (dmamode
== 0x40 && modeidx
<= ATA_MAX_UDMA
)
394 /* Using Ultra DMA */
395 ata_set_udma_timings(dmamode
);
396 ata_dma_selected
= ATA_DMA_UDMA
;
398 else if (dmamode
== 0x20 && modeidx
<= ATA_MAX_MWDMA
)
400 /* Using Multiword DMA */
401 ata_set_mdma_timings(dmamode
);
402 ata_dma_selected
= ATA_DMA_MWDMA
;
406 /* Don't understand this - force PIO. */
407 ata_dma_selected
= ATA_DMA_PIO
;
411 /* Called by SDMA when transfer is complete */
412 static void ata_dma_callback(void)
414 /* Clear FIFO if not empty - shouldn't happen */
415 while (ATA_FIFO_FILL
!= 0)
418 /* Clear FIFO interrupts (the only ones that can be) */
419 ATA_INTERRUPT_CLEAR
= ATA_INTERRUPT_PENDING
;
421 ata_set_intrq(false); /* Return INTRQ to MCU */
422 wakeup_signal(&ata_dma_wakeup
); /* Signal waiting thread */
425 bool ata_dma_setup(void *addr
, unsigned long bytes
, bool write
)
427 struct buffer_descriptor
*bd_p
;
430 if (UNLIKELY(bytes
> ATA_BASE_BD_COUNT
*ATA_MAX_BD_SIZE
||
431 (ata_dma_selected
& ATA_DMA_PIO
)))
433 /* Too much? Implies BD count should be reevaluated since this
434 * shouldn't be reached based upon size. Otherwise we simply didn't
435 * understand the DMA mode setup. Force PIO in both cases. */
436 ATA_INTF_CONTROL
= ATA_FIFO_RST
| ATA_ATA_RST
;
441 buf
= (unsigned char *)addr_virt_to_phys((unsigned long)addr
);
442 sb_dst
[0] = NULL
; /* Assume not needed */
446 /* No cache alignment concerns */
447 current_channel
= ATA_DMA_CH_NUM_WR
;
449 if (LIKELY(buf
!= addr
))
451 /* addr is virtual */
452 clean_dcache_range(addr
, bytes
);
455 /* Setup ATA controller for DMA transmit */
456 ATA_INTF_CONTROL
= ATA_FIFO_RST
| ATA_ATA_RST
| ATA_FIFO_TX_EN
|
457 ATA_DMA_PENDING
| ata_dma_selected
| ATA_DMA_WRITE
;
458 ATA_FIFO_ALARM
= SDMA_ATA_WML
/ 2;
462 current_channel
= ATA_DMA_CH_NUM_RD
;
464 /* Setup ATA controller for DMA receive */
465 ATA_INTF_CONTROL
= ATA_FIFO_RST
| ATA_ATA_RST
| ATA_FIFO_RCV_EN
|
466 ATA_DMA_PENDING
| ata_dma_selected
;
467 ATA_FIFO_ALARM
= SDMA_ATA_WML
/ 2;
469 if (LIKELY(buf
!= addr
))
471 /* addr is virtual */
472 dump_dcache_range(addr
, bytes
);
474 if ((unsigned long)addr
& 31)
476 /* Not cache aligned, must use scatter buffers for first and
478 unsigned char *bufstart
= buf
;
481 bd_p
->buf_addr
= scatter_buffer
;
482 bd_p
->mode
.count
= 32;
483 bd_p
->mode
.status
= BD_DONE
| BD_CONT
;
489 while (bytes
> ATA_MAX_BD_SIZE
)
491 bd_p
->buf_addr
= buf
;
492 bd_p
->mode
.count
= ATA_MAX_BD_SIZE
;
493 bd_p
->mode
.status
= BD_DONE
| BD_CONT
;
494 buf
+= ATA_MAX_BD_SIZE
;
495 bytes
-= ATA_MAX_BD_SIZE
;
501 unsigned long size
= bytes
- 32;
502 bd_p
->buf_addr
= buf
;
503 bd_p
->mode
.count
= size
;
504 bd_p
->mode
.status
= BD_DONE
| BD_CONT
;
509 /* There will be exactly 32 bytes left */
511 /* Final buffer - wrap to base bd, interrupt */
512 sb_dst
[1] = addr
+ (buf
- bufstart
);
513 bd_p
->buf_addr
= &scatter_buffer
[32/4];
514 bd_p
->mode
.count
= 32;
515 bd_p
->mode
.status
= BD_DONE
| BD_WRAP
| BD_INTR
;
522 /* Setup buffer descriptors for both cache-aligned reads and all write
524 while (bytes
> ATA_MAX_BD_SIZE
)
526 bd_p
->buf_addr
= buf
;
527 bd_p
->mode
.count
= ATA_MAX_BD_SIZE
;
528 bd_p
->mode
.status
= BD_DONE
| BD_CONT
;
529 buf
+= ATA_MAX_BD_SIZE
;
530 bytes
-= ATA_MAX_BD_SIZE
;
534 /* Final buffer - wrap to base bd, interrupt */
535 bd_p
->buf_addr
= buf
;
536 bd_p
->mode
.count
= bytes
;
537 bd_p
->mode
.status
= BD_DONE
| BD_WRAP
| BD_INTR
;
542 bool ata_dma_finish(void)
544 unsigned int channel
= current_channel
;
545 long timeout
= current_tick
+ HZ
*10;
549 ata_set_intrq(true); /* Give INTRQ to DMA */
550 sdma_channel_run(channel
); /* Kick the channel to wait for events */
556 if (LIKELY(wakeup_wait(&ata_dma_wakeup
, HZ
/2) == OBJ_WAIT_SUCCEEDED
))
561 if (TIME_BEFORE(current_tick
, timeout
))
564 /* Epic fail - timed out - maybe. */
565 oldirq
= disable_irq_save();
566 ata_set_intrq(false); /* Strip INTRQ from DMA */
567 sdma_channel_stop(channel
); /* Stop DMA */
570 if (wakeup_wait(&ata_dma_wakeup
, TIMEOUT_NOBLOCK
) == OBJ_WAIT_SUCCEEDED
)
571 break; /* DMA really did finish after timeout */
573 sdma_channel_reset(channel
); /* Reset everything + clear error */
577 if (sdma_channel_is_error(channel
))
579 /* Channel error in one or more descriptors */
580 sdma_channel_reset(channel
); /* Reset everything + clear error */
584 if (sb_dst
[0] != NULL
)
586 /* NOTE: This requires that unaligned access support be enabled! */
587 register void *sbs
= scatter_buffer
;
588 register void *sbd0
= sb_dst
[0];
589 register void *sbd1
= sb_dst
[1];
591 "add r0, %1, #32 \n" /* Prefetch at DMA-direct boundaries */
592 "mcrr p15, 2, r0, r0, c12 \n"
593 "mcrr p15, 2, %2, %2, c12 \n"
594 "ldmia %0!, { r0-r3 } \n" /* Copy the 32-bytes to destination */
595 "str r0, [%1], #4 \n" /* stmia doesn't work unaligned */
596 "str r1, [%1], #4 \n"
597 "str r2, [%1], #4 \n"
598 "str r3, [%1], #4 \n"
599 "ldmia %0!, { r0-r3 } \n"
600 "str r0, [%1], #4 \n"
601 "str r1, [%1], #4 \n"
602 "str r2, [%1], #4 \n"
604 "ldmia %0!, { r0-r3 } \n" /* Copy the 32-bytes to destination */
605 "str r0, [%2], #4 \n" /* stmia doesn't work unaligned */
606 "str r1, [%2], #4 \n"
607 "str r2, [%2], #4 \n"
608 "str r3, [%2], #4 \n"
609 "ldmia %0!, { r0-r3 } \n"
610 "str r0, [%2], #4 \n"
611 "str r1, [%2], #4 \n"
612 "str r2, [%2], #4 \n"
614 : "+r"(sbs
), "+r"(sbd0
), "+r"(sbd1
)
616 : "r0", "r1", "r2", "r3");
621 #endif /* HAVE_ATA_DMA */
623 void ata_device_init(void)
625 /* Make sure we're not in reset mode */
630 ATA_INTERRUPT_ENABLE
= 0;
631 ATA_INTERRUPT_CLEAR
= ATA_INTERRUPT_PENDING
;
634 ata_set_intrq(false);
639 /* All modes use same tOFF/tON */
643 /* Setup mode 0 for all by default
644 * Mode may be switched later once identify info is ready in which
645 * case the main driver calls back */
646 ata_set_pio_timings(0);
649 ata_set_mdma_timings(0);
650 ata_set_udma_timings(0);
652 ata_dma_selected
= ATA_DMA_PIO
;
654 /* Called for first time at startup */
655 wakeup_init(&ata_dma_wakeup
);
657 /* Read/write channels share buffer descriptors */
658 ata_cd_rd
.bd_count
= ATA_BD_COUNT
;
659 ata_cd_rd
.callback
= ata_dma_callback
;
660 ata_cd_rd
.shp_addr
= SDMA_PER_ADDR_ATA_RX
;
661 ata_cd_rd
.wml
= SDMA_ATA_WML
;
662 ata_cd_rd
.per_type
= SDMA_PER_ATA
;
663 ata_cd_rd
.tran_type
= SDMA_TRAN_PER_2_EMI
;
664 ata_cd_rd
.event_id1
= SDMA_REQ_ATA_TXFER_END
;
665 ata_cd_rd
.event_id2
= SDMA_REQ_ATA_RX
;
667 ata_cd_wr
.bd_count
= ATA_BD_COUNT
;
668 ata_cd_wr
.callback
= ata_dma_callback
;
669 ata_cd_wr
.shp_addr
= SDMA_PER_ADDR_ATA_TX
;
670 ata_cd_wr
.wml
= SDMA_ATA_WML
;
671 ata_cd_wr
.per_type
= SDMA_PER_ATA
;
672 ata_cd_wr
.tran_type
= SDMA_TRAN_EMI_2_PER
;
673 ata_cd_wr
.event_id1
= SDMA_REQ_ATA_TXFER_END
;
674 ata_cd_wr
.event_id2
= SDMA_REQ_ATA_TX
;
676 if (!sdma_channel_init(ATA_DMA_CH_NUM_RD
, &ata_cd_rd
, ata_bda
) ||
677 !sdma_channel_init(ATA_DMA_CH_NUM_WR
, &ata_cd_wr
, ata_bda
))
679 /* Channel init error - disable DMA forever */
680 ata_dma_selected
= ATA_DMA_DISABLED
;
682 #endif /* HAVE_ATA_DMA */