1 /***************************************************************************
3 * Open \______ \ ____ ____ | | _\_ |__ _______ ___
4 * Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
5 * Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
6 * Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
10 * Copyright (C) 2006 Daniel Ankers
11 * Copyright © 2008-2009 Rafaël Carré
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License
15 * as published by the Free Software Foundation; either version 2
16 * of the License, or (at your option) any later version.
18 * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
19 * KIND, either express or implied.
21 ****************************************************************************/
23 /* Driver for the ARM PL180 SD/MMC controller inside AS3525 SoC */
25 #include "config.h" /* for HAVE_MULTIDRIVE & AMS_OF_SIZE */
36 #include "pl180.h" /* SD controller */
37 #include "pl081.h" /* DMA controller */
38 #include "dma-target.h" /* DMA request lines */
39 #include "clock-target.h"
41 #ifdef HAVE_BUTTON_LIGHT
42 #include "backlight-target.h"
45 #include "ata_idle_notify.h"
54 #define MCI_NO_FLAGS (0<<0)
55 #define MCI_RESP (1<<0)
56 #define MCI_LONG_RESP (1<<1)
57 #define MCI_ARG (1<<2)
59 /* ARM PL180 registers */
60 #define MCI_POWER(i) (*(volatile unsigned char *) (pl180_base[i]+0x00))
61 #define MCI_CLOCK(i) (*(volatile unsigned long *) (pl180_base[i]+0x04))
62 #define MCI_ARGUMENT(i) (*(volatile unsigned long *) (pl180_base[i]+0x08))
63 #define MCI_COMMAND(i) (*(volatile unsigned long *) (pl180_base[i]+0x0C))
64 #define MCI_RESPCMD(i) (*(volatile unsigned long *) (pl180_base[i]+0x10))
65 #define MCI_RESP0(i) (*(volatile unsigned long *) (pl180_base[i]+0x14))
66 #define MCI_RESP1(i) (*(volatile unsigned long *) (pl180_base[i]+0x18))
67 #define MCI_RESP2(i) (*(volatile unsigned long *) (pl180_base[i]+0x1C))
68 #define MCI_RESP3(i) (*(volatile unsigned long *) (pl180_base[i]+0x20))
69 #define MCI_DATA_TIMER(i) (*(volatile unsigned long *) (pl180_base[i]+0x24))
70 #define MCI_DATA_LENGTH(i) (*(volatile unsigned short*) (pl180_base[i]+0x28))
71 #define MCI_DATA_CTRL(i) (*(volatile unsigned char *) (pl180_base[i]+0x2C))
72 #define MCI_DATA_CNT(i) (*(volatile unsigned short*) (pl180_base[i]+0x30))
73 #define MCI_STATUS(i) (*(volatile unsigned long *) (pl180_base[i]+0x34))
74 #define MCI_CLEAR(i) (*(volatile unsigned long *) (pl180_base[i]+0x38))
75 #define MCI_MASK0(i) (*(volatile unsigned long *) (pl180_base[i]+0x3C))
76 #define MCI_MASK1(i) (*(volatile unsigned long *) (pl180_base[i]+0x40))
77 #define MCI_SELECT(i) (*(volatile unsigned long *) (pl180_base[i]+0x44))
78 #define MCI_FIFO_CNT(i) (*(volatile unsigned long *) (pl180_base[i]+0x48))
80 #define MCI_DATA_ERROR \
87 #define MCI_RESPONSE_ERROR \
91 #define MCI_FIFO(i) ((unsigned long *) (pl180_base[i]+0x80))
93 #define INTERNAL_AS3525 0 /* embedded SD card */
94 #define SD_SLOT_AS3525 1 /* SD slot if present */
96 static const int pl180_base
[NUM_DRIVES
] = {
98 #ifdef HAVE_MULTIDRIVE
103 static int sd_wait_for_tran_state(const int drive
);
104 static int sd_select_bank(signed char bank
);
105 static int sd_init_card(const int drive
);
106 static void init_pl180_controller(const int drive
);
108 #define BLOCKS_PER_BANK 0x7a7800u
110 static tCardInfo card_info
[NUM_DRIVES
];
112 /* maximum timeouts recommanded in the SD Specification v2.00 */
113 #define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
114 #define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
116 /* for compatibility */
117 static long last_disk_activity
= -1;
119 #define MIN_YIELD_PERIOD 5 /* ticks */
120 static long next_yield
= 0;
122 static long sd_stack
[(DEFAULT_STACK_SIZE
*2 + 0x200)/sizeof(long)];
123 static const char sd_thread_name
[] = "ata/sd";
124 static struct mutex sd_mtx
;
125 static struct event_queue sd_queue
;
126 bool sd_enabled
= false;
128 #if defined(HAVE_MULTIDRIVE)
129 static bool hs_card
= false;
130 #define EXT_SD_BITS (1<<2)
133 static struct wakeup transfer_completion_signal
;
134 static volatile unsigned int transfer_error
[NUM_VOLUMES
];
135 #define PL180_MAX_TRANSFER_ERRORS 10
137 #define UNALIGNED_NUM_SECTORS 10
138 static unsigned char aligned_buffer
[UNALIGNED_NUM_SECTORS
* SD_BLOCK_SIZE
] __attribute__((aligned(32))); /* align on cache line size */
139 static unsigned char *uncached_buffer
= AS3525_UNCACHED_ADDR(&aligned_buffer
[0]);
142 static inline void mci_delay(void) { udelay(1000) ; }
145 static inline bool card_detect_target(void)
147 #if defined(HAVE_MULTIDRIVE)
148 return !(GPIOA_PIN(2));
156 static int sd1_oneshot_callback(struct timeout
*tmo
)
160 /* This is called only if the state was stable for 300ms - check state
161 * and post appropriate event. */
162 if (card_detect_target())
164 queue_broadcast(SYS_HOTSWAP_INSERTED
, 0);
167 queue_broadcast(SYS_HOTSWAP_EXTRACTED
, 0);
172 void sd_gpioa_isr(void)
174 static struct timeout sd1_oneshot
;
175 if (GPIOA_MIS
& EXT_SD_BITS
)
176 timeout_register(&sd1_oneshot
, sd1_oneshot_callback
, (3*HZ
/10), 0);
177 /* acknowledge interrupt */
178 GPIOA_IC
= EXT_SD_BITS
;
180 #endif /* HAVE_HOTSWAP */
184 const int status
= MCI_STATUS(INTERNAL_AS3525
);
186 transfer_error
[INTERNAL_AS3525
] = status
& MCI_DATA_ERROR
;
188 wakeup_signal(&transfer_completion_signal
);
189 MCI_CLEAR(INTERNAL_AS3525
) = status
;
192 #ifdef HAVE_MULTIDRIVE
195 const int status
= MCI_STATUS(SD_SLOT_AS3525
);
197 transfer_error
[SD_SLOT_AS3525
] = status
& MCI_DATA_ERROR
;
199 wakeup_signal(&transfer_completion_signal
);
200 MCI_CLEAR(SD_SLOT_AS3525
) = status
;
204 static bool send_cmd(const int drive
, const int cmd
, const int arg
,
205 const int flags
, long *response
)
209 unsigned cmd_retries
= 6;
212 /* Clear old status flags */
213 MCI_CLEAR(drive
) = 0x7ff;
215 /* Load command argument or clear if none */
216 MCI_ARGUMENT(drive
) = (flags
& MCI_ARG
) ? arg
: 0;
218 /* Construct MCI_COMMAND & enable CPSM */
221 /* b6 */| ((flags
& (MCI_RESP
|MCI_LONG_RESP
)) ? MCI_COMMAND_RESPONSE
: 0)
222 /* b7 */| ((flags
& MCI_LONG_RESP
) ? MCI_COMMAND_LONG_RESPONSE
: 0)
223 /* b8 | MCI_COMMAND_INTERRUPT */
224 /* b9 | MCI_COMMAND_PENDING */ /*Only used with stream data transfer*/
225 /* b10*/| MCI_COMMAND_ENABLE
; /* Enables CPSM */
227 /* Wait while cmd completes then disable CPSM */
228 while(MCI_STATUS(drive
) & MCI_CMD_ACTIVE
);
229 MCI_COMMAND(drive
) = 0;
231 status
= MCI_STATUS(drive
);
233 /* Handle command responses */
234 if(flags
& MCI_RESP
) /* CMD expects response */
236 response
[0] = MCI_RESP0(drive
); /* Always prepare short response */
238 if(status
& MCI_RESPONSE_ERROR
) /* timeout or crc failure */
241 if(status
& MCI_CMD_RESP_END
) /* Response passed CRC check */
243 if(flags
& MCI_LONG_RESP
)
244 { /* response[0] has already been read */
245 response
[1] = MCI_RESP1(drive
);
246 response
[2] = MCI_RESP2(drive
);
247 response
[3] = MCI_RESP3(drive
);
252 else if(status
& MCI_CMD_SENT
) /* CMD sent, no response required */
259 #define MCI_FULLSPEED (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS) /* MCLK */
260 #define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */
261 #define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */
262 #define MCI_IDENTSPEED (MCI_CLOCK_ENABLE | AS3525_SD_IDENT_DIV) /* IDENT */
264 static int sd_init_card(const int drive
)
266 unsigned long response
;
270 /* MCLCK on and set to 400kHz ident frequency */
271 MCI_CLOCK(drive
) = MCI_IDENTSPEED
;
273 /* 100 - 400kHz clock required for Identification Mode */
274 /* Start of Card Identification Mode ************************************/
277 if(!send_cmd(drive
, SD_GO_IDLE_STATE
, 0, MCI_NO_FLAGS
, NULL
))
281 /* CMD8 Check for v2 sd card. Must be sent before using ACMD41
282 Non v2 cards will not respond to this command*/
283 if(send_cmd(drive
, SD_SEND_IF_COND
, 0x1AA, MCI_RESP
|MCI_ARG
, &response
))
284 if((response
& 0xFFF) == 0x1AA)
287 /* timeout for initialization is 1sec, from SD Specification 2.00 */
288 init_timeout
= current_tick
+ HZ
;
291 /* this timeout is the only valid error for this loop*/
292 if(TIME_AFTER(current_tick
, init_timeout
))
296 send_cmd(drive
, SD_APP_CMD
, 0, MCI_RESP
|MCI_ARG
, &response
);
298 /* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
299 send_cmd(drive
, SD_APP_OP_COND
, (0x00FF8000 | (sd_v2
? 1<<30 : 0)),
300 MCI_RESP
|MCI_ARG
, &card_info
[drive
].ocr
);
302 } while(!(card_info
[drive
].ocr
& (1<<31)));
305 if(!send_cmd(drive
, SD_ALL_SEND_CID
, 0, MCI_RESP
|MCI_LONG_RESP
|MCI_ARG
,
306 card_info
[drive
].cid
))
310 if(!send_cmd(drive
, SD_SEND_RELATIVE_ADDR
, 0, MCI_RESP
|MCI_ARG
,
311 &card_info
[drive
].rca
))
314 /* End of Card Identification Mode ************************************/
316 #ifdef HAVE_MULTIDRIVE /* The internal SDs are v1 */
318 /* Try to switch V2 cards to HS timings, non HS seem to ignore this */
321 /* CMD7 w/rca: Select card to put it in TRAN state */
322 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_RESP
|MCI_ARG
, &response
))
325 if(sd_wait_for_tran_state(drive
))
328 if(!send_cmd(drive
, SD_SWITCH_FUNC
, 0x80fffff1, MCI_ARG
, NULL
))
332 /* go back to STBY state so we can read csd */
333 /* CMD7 w/rca=0: Deselect card to put it in STBY state */
334 if(!send_cmd(drive
, SD_DESELECT_CARD
, 0, MCI_ARG
, NULL
))
338 #endif /* HAVE_MULTIDRIVE */
341 if(!send_cmd(drive
, SD_SEND_CSD
, card_info
[drive
].rca
,
342 MCI_RESP
|MCI_LONG_RESP
|MCI_ARG
, card_info
[drive
].csd
))
345 sd_parse_csd(&card_info
[drive
]);
347 #if defined(HAVE_MULTIDRIVE)
348 hs_card
= (card_info
[drive
].speed
== 50000000);
351 /* Boost MCICLK to operating speed */
352 if(drive
== INTERNAL_AS3525
)
353 MCI_CLOCK(drive
) = MCI_HALFSPEED
; /* MCICLK = IDE_CLK/2 = 25 MHz */
354 #if defined(HAVE_MULTIDRIVE)
356 /* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
357 MCI_CLOCK(drive
) = (hs_card
? MCI_HALFSPEED
: MCI_QUARTERSPEED
);
360 /* CMD7 w/rca: Select card to put it in TRAN state */
361 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_RESP
|MCI_ARG
, &response
))
365 /* Switch to to 4 bit widebus mode */
366 if(sd_wait_for_tran_state(drive
) < 0)
368 /* CMD55 */ /* Response is requested due to timing issue */
369 if(!send_cmd(drive
, SD_APP_CMD
, card_info
[drive
].rca
, MCI_ARG
|MCI_RESP
, &response
))
372 if(!send_cmd(drive
, SD_SET_CLR_CARD_DETECT
, 0, MCI_ARG
|MCI_RESP
, &response
))
374 /* CMD55 */ /* Response is requested due to timing issue */
375 if(!send_cmd(drive
, SD_APP_CMD
, card_info
[drive
].rca
, MCI_ARG
|MCI_RESP
, &response
))
378 if(!send_cmd(drive
, SD_SET_BUS_WIDTH
, 2, MCI_ARG
|MCI_RESP
, &response
))
380 /* Now that card is widebus make controller aware */
381 MCI_CLOCK(drive
) |= MCI_CLOCK_WIDEBUS
;
385 * enable bank switching
386 * without issuing this command, we only have access to 1/4 of the blocks
387 * of the first bank (0x1E9E00 blocks, which is the size reported in the
390 if(drive
== INTERNAL_AS3525
)
392 const int ret
= sd_select_bank(-1);
396 /* CMD7 w/rca = 0: Unselect card to put it in STBY state */
397 if(!send_cmd(drive
, SD_SELECT_CARD
, 0, MCI_ARG
, NULL
))
401 /* CMD9 send CSD again, so we got the correct number of blocks */
402 if(!send_cmd(drive
, SD_SEND_CSD
, card_info
[drive
].rca
,
403 MCI_RESP
|MCI_LONG_RESP
|MCI_ARG
, card_info
[drive
].csd
))
406 sd_parse_csd(&card_info
[drive
]);
407 /* The OF is stored in the first blocks */
408 card_info
[INTERNAL_AS3525
].numblocks
-= AMS_OF_SIZE
;
410 /* CMD7 w/rca: Select card to put it in TRAN state */
411 if(!send_cmd(drive
, SD_SELECT_CARD
, card_info
[drive
].rca
, MCI_RESP
|MCI_ARG
, &response
))
415 card_info
[drive
].initialized
= 1;
420 static void sd_thread(void) __attribute__((noreturn
));
421 static void sd_thread(void)
423 struct queue_event ev
;
424 bool idle_notified
= false;
428 queue_wait_w_tmo(&sd_queue
, &ev
, HZ
);
433 case SYS_HOTSWAP_INSERTED
:
434 case SYS_HOTSWAP_EXTRACTED
:
436 int microsd_init
= 1;
437 fat_lock(); /* lock-out FAT activity first -
438 prevent deadlocking via disk_mount that
439 would cause a reverse-order attempt with
441 mutex_lock(&sd_mtx
); /* lock-out card activity - direct calls
442 into driver that bypass the fat cache */
444 /* We now have exclusive control of fat cache and ata */
446 disk_unmount(SD_SLOT_AS3525
); /* release "by force", ensure file
447 descriptors aren't leaked and any busy
448 ones are invalid if mounting */
450 /* Force card init for new card, re-init for re-inserted one or
451 * clear if the last attempt to init failed with an error. */
452 card_info
[SD_SLOT_AS3525
].initialized
= 0;
454 if (ev
.id
== SYS_HOTSWAP_INSERTED
)
457 init_pl180_controller(SD_SLOT_AS3525
);
458 microsd_init
= sd_init_card(SD_SLOT_AS3525
);
459 if (microsd_init
< 0) /* initialisation failed */
460 panicf("microSD init failed : %d", microsd_init
);
462 microsd_init
= disk_mount(SD_SLOT_AS3525
); /* 0 if fail */
466 * Mount succeeded, or this was an EXTRACTED event,
467 * in both cases notify the system about the changed filesystems
470 queue_broadcast(SYS_FS_CHANGED
, 0);
472 /* Access is now safe */
473 mutex_unlock(&sd_mtx
);
480 if (TIME_BEFORE(current_tick
, last_disk_activity
+(3*HZ
)))
482 idle_notified
= false;
486 /* never let a timer wrap confuse us */
487 next_yield
= current_tick
;
491 call_storage_idle_notifys(false);
492 idle_notified
= true;
497 case SYS_USB_CONNECTED
:
498 usb_acknowledge(SYS_USB_CONNECTED_ACK
);
499 /* Wait until the USB cable is extracted again */
500 usb_wait_for_disconnect(&sd_queue
);
503 case SYS_USB_DISCONNECTED
:
504 usb_acknowledge(SYS_USB_DISCONNECTED_ACK
);
510 static void init_pl180_controller(const int drive
)
512 MCI_COMMAND(drive
) = MCI_DATA_CTRL(drive
) = 0;
513 MCI_CLEAR(drive
) = 0x7ff;
515 MCI_MASK0(drive
) = MCI_DATA_ERROR
| MCI_DATA_END
;
516 MCI_MASK1(drive
) = 0;
517 #ifdef HAVE_MULTIDRIVE
519 (drive
== INTERNAL_AS3525
) ? INTERRUPT_NAND
: INTERRUPT_MCI0
;
520 /* clear previous irq */
521 GPIOA_IC
= EXT_SD_BITS
;
522 /* enable edge detecting */
523 GPIOA_IS
&= ~EXT_SD_BITS
;
524 /* detect both raising and falling edges */
525 GPIOA_IBE
|= EXT_SD_BITS
;
526 /* enable the card detect interrupt */
527 GPIOA_IE
|= EXT_SD_BITS
;
530 VIC_INT_ENABLE
= INTERRUPT_NAND
;
533 MCI_POWER(drive
) = MCI_POWER_UP
| (MCI_VDD_3_0
); /* OF Setting */
536 MCI_POWER(drive
) |= MCI_POWER_ON
;
539 MCI_SELECT(drive
) = 0;
541 /* Pl180 clocks get turned on at start of card init */
547 CGU_IDE
= (1<<6) /* enable non AHB interface*/
548 | (AS3525_IDE_DIV
<< 2)
549 | AS3525_CLK_PLLA
; /* clock source = PLLA */
551 CGU_PERI
|= CGU_NAF_CLOCK_ENABLE
;
552 #ifdef HAVE_MULTIDRIVE
553 CGU_PERI
|= CGU_MCI_CLOCK_ENABLE
;
554 CCU_IO
&= ~(1<<3); /* bits 3:2 = 01, xpd is SD interface */
558 wakeup_init(&transfer_completion_signal
);
560 init_pl180_controller(INTERNAL_AS3525
);
561 ret
= sd_init_card(INTERNAL_AS3525
);
564 #ifdef HAVE_MULTIDRIVE
565 init_pl180_controller(SD_SLOT_AS3525
);
571 queue_init(&sd_queue
, true);
572 create_thread(sd_thread
, sd_stack
, sizeof(sd_stack
), 0,
573 sd_thread_name
IF_PRIO(, PRIORITY_USER_INTERFACE
) IF_COP(, CPU
));
582 bool sd_removable(IF_MD_NONVOID(int drive
))
587 bool sd_present(IF_MD_NONVOID(int drive
))
589 return (drive
== 0) ? true : card_detect_target();
591 #endif /* HAVE_HOTSWAP */
593 static int sd_wait_for_tran_state(const int drive
)
595 unsigned long response
= 0;
596 unsigned int timeout
= current_tick
+ 5 * HZ
;
600 if(!send_cmd(drive
, SD_SEND_STATUS
, card_info
[drive
].rca
,
601 MCI_RESP
|MCI_ARG
, &response
))
604 if (((response
>> 9) & 0xf) == SD_TRAN
)
607 if(TIME_AFTER(current_tick
, timeout
))
610 if (TIME_AFTER(current_tick
, next_yield
))
613 next_yield
= current_tick
+ MIN_YIELD_PERIOD
;
618 static int sd_select_bank(signed char bank
)
623 memset(uncached_buffer
, 0, 512);
625 { /* enable bank switching */
626 uncached_buffer
[0] = 16;
627 uncached_buffer
[1] = 1;
628 uncached_buffer
[2] = 10;
631 uncached_buffer
[0] = bank
;
634 if(loops
++ > PL180_MAX_TRANSFER_ERRORS
)
635 panicf("SD bank %d error : 0x%x", bank
,
636 transfer_error
[INTERNAL_AS3525
]);
638 ret
= sd_wait_for_tran_state(INTERNAL_AS3525
);
642 if(!send_cmd(INTERNAL_AS3525
, SD_SWITCH_FUNC
, 0x80ffffef, MCI_ARG
, NULL
))
647 if(!send_cmd(INTERNAL_AS3525
, 35, 0, MCI_NO_FLAGS
, NULL
))
653 /* we don't use the uncached buffer here, because we need the
654 * physical memory address for DMA transfers */
655 dma_enable_channel(0, aligned_buffer
, MCI_FIFO(INTERNAL_AS3525
),
656 DMA_PERI_SD
, DMAC_FLOWCTRL_PERI_MEM_TO_PERI
, true, false, 0, DMA_S8
,
659 MCI_DATA_TIMER(INTERNAL_AS3525
) = SD_MAX_WRITE_TIMEOUT
;
660 MCI_DATA_LENGTH(INTERNAL_AS3525
) = 512;
661 MCI_DATA_CTRL(INTERNAL_AS3525
) = (1<<0) /* enable */ |
662 (0<<1) /* transfer direction */ |
664 (9<<4) /* 2^9 = 512 */ ;
666 /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
667 wakeup_wait(&transfer_completion_signal
, TIMEOUT_BLOCK
);
669 /* Wait for FIFO to empty, card may still be in PRG state */
670 while(MCI_STATUS(INTERNAL_AS3525
) & MCI_TX_ACTIVE
);
674 } while(transfer_error
[INTERNAL_AS3525
]);
676 card_info
[INTERNAL_AS3525
].current_bank
= (bank
== -1) ? 0 : bank
;
681 static int sd_transfer_sectors(IF_MD2(int drive
,) unsigned long start
,
682 int count
, void* buf
, const bool write
)
684 #ifndef HAVE_MULTIDRIVE
689 bool aligned
= !((uintptr_t)buf
& (CACHEALIGN_SIZE
- 1));
695 if (card_info
[drive
].initialized
<= 0)
697 ret
= sd_init_card(drive
);
698 if (!(card_info
[drive
].initialized
))
699 goto sd_transfer_error_nodma
;
702 if(count
< 0) /* XXX: why is it signed ? */
705 goto sd_transfer_error_nodma
;
707 if((start
+count
) > card_info
[drive
].numblocks
)
710 goto sd_transfer_error_nodma
;
713 /* skip SanDisk OF */
714 if (drive
== INTERNAL_AS3525
)
715 start
+= AMS_OF_SIZE
;
717 last_disk_activity
= current_tick
;
724 clean_dcache_range(buf
, count
* SECTOR_SIZE
);
726 dump_dcache_range(buf
, count
* SECTOR_SIZE
);
731 /* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
732 * register, so we have to transfer maximum 127 sectors at a time. */
733 unsigned int transfer
= (count
>= 128) ? 127 : count
; /* sectors */
736 write
? SD_WRITE_MULTIPLE_BLOCK
: SD_READ_MULTIPLE_BLOCK
;
737 unsigned long bank_start
= start
;
738 unsigned long status
;
740 /* Only switch banks for internal storage */
741 if(drive
== INTERNAL_AS3525
)
743 unsigned int bank
= 0;
744 while(bank_start
>= BLOCKS_PER_BANK
)
746 bank_start
-= BLOCKS_PER_BANK
;
750 /* Switch bank if needed */
751 if(card_info
[INTERNAL_AS3525
].current_bank
!= bank
)
753 ret
= sd_select_bank(bank
);
757 goto sd_transfer_error
;
761 /* Do not cross a bank boundary in a single transfer loop */
762 if((transfer
+ bank_start
) > BLOCKS_PER_BANK
)
763 transfer
= BLOCKS_PER_BANK
- bank_start
;
766 /* Set bank_start to the correct unit (blocks or bytes) */
767 if(!(card_info
[drive
].ocr
& (1<<30))) /* not SDHC */
768 bank_start
*= SD_BLOCK_SIZE
;
772 dma_buf
= AS3525_PHYSICAL_ADDR(buf
);
776 dma_buf
= aligned_buffer
;
777 if(transfer
> UNALIGNED_NUM_SECTORS
)
778 transfer
= UNALIGNED_NUM_SECTORS
;
781 memcpy(uncached_buffer
, buf
, transfer
* SD_BLOCK_SIZE
);
784 ret
= sd_wait_for_tran_state(drive
);
788 goto sd_transfer_error
;
791 if(!send_cmd(drive
, cmd
, bank_start
, MCI_ARG
, NULL
))
794 goto sd_transfer_error
;
799 dma_enable_channel(0, dma_buf
, MCI_FIFO(drive
),
800 (drive
== INTERNAL_AS3525
) ? DMA_PERI_SD
: DMA_PERI_SD_SLOT
,
801 DMAC_FLOWCTRL_PERI_MEM_TO_PERI
, true, false, 0, DMA_S8
, NULL
);
803 /*Small delay for writes prevents data crc failures at lower freqs*/
804 #ifdef HAVE_MULTIDRIVE
805 if((drive
== SD_SLOT_AS3525
) && !hs_card
)
807 int write_delay
= 125;
808 while(write_delay
--);
813 dma_enable_channel(0, MCI_FIFO(drive
), dma_buf
,
814 (drive
== INTERNAL_AS3525
) ? DMA_PERI_SD
: DMA_PERI_SD_SLOT
,
815 DMAC_FLOWCTRL_PERI_PERI_TO_MEM
, false, true, 0, DMA_S8
, NULL
);
817 MCI_DATA_TIMER(drive
) = write
?
818 SD_MAX_WRITE_TIMEOUT
: SD_MAX_READ_TIMEOUT
;
819 MCI_DATA_LENGTH(drive
) = transfer
* SD_BLOCK_SIZE
;
820 MCI_DATA_CTRL(drive
) = (1<<0) /* enable */ |
821 (!write
<<1) /* transfer direction */ |
823 (9<<4) /* 2^9 = 512 */ ;
825 /* Wakeup signal from NAND/MCIO isr on MCI_DATA_ERROR | MCI_DATA_END */
826 wakeup_wait(&transfer_completion_signal
, TIMEOUT_BLOCK
);
828 /* Wait for FIFO to empty, card may still be in PRG state for writes */
829 while(MCI_STATUS(drive
) & MCI_TX_ACTIVE
);
831 last_disk_activity
= current_tick
;
833 if(!send_cmd(drive
, SD_STOP_TRANSMISSION
, 0, MCI_RESP
, &status
))
836 goto sd_transfer_error
;
839 if(!transfer_error
[drive
])
841 if(!write
&& !aligned
)
842 memcpy(buf
, uncached_buffer
, transfer
* SD_BLOCK_SIZE
);
843 buf
+= transfer
* SD_BLOCK_SIZE
;
846 loops
= 0; /* reset errors counter */
848 else if(loops
++ > PL180_MAX_TRANSFER_ERRORS
)
849 panicf("SD Xfer %s err:0x%x Disk%d", (write
? "write": "read"),
850 transfer_error
[drive
], drive
);
857 sd_transfer_error_nodma
:
863 card_info
[drive
].initialized
= 0;
865 mutex_unlock(&sd_mtx
);
869 int sd_read_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
872 return sd_transfer_sectors(IF_MD2(drive
,) start
, count
, buf
, false);
875 int sd_write_sectors(IF_MD2(int drive
,) unsigned long start
, int count
,
878 return sd_transfer_sectors(IF_MD2(drive
,) start
, count
, (void*)buf
, true);
881 long sd_last_disk_activity(void)
883 return last_disk_activity
;
886 void sd_enable(bool on
)
888 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
889 extern int buttonlight_is_on
;
892 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
893 static bool cpu_boosted
= false;
896 if (sd_enabled
== on
)
897 return; /* nothing to do */
903 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
904 /* buttonlight AMSes need a bit of special handling for the buttonlight
905 * here due to the dual mapping of GPIOD and XPD */
906 CCU_IO
|= (1<<2); /* XPD is SD-MCI interface (b3:2 = 01) */
907 if (buttonlight_is_on
)
908 GPIOD_DIR
&= ~(1<<7);
913 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
914 if(card_detect_target()) /* If SD card present Boost cpu for voltage */
919 #endif /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
923 #if defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE)
929 #endif /* defined(HAVE_HOTSWAP) && defined (HAVE_ADJUSTABLE_CPU_VOLTAGE) */
931 #if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
932 CCU_IO
&= ~(1<<2); /* XPD is general purpose IO (b3:2 = 00) */
933 if (buttonlight_is_on
)
939 tCardInfo
*card_get_info_target(int card_no
)
941 return &card_info
[card_no
];
944 #ifdef CONFIG_STORAGE_MULTI
945 int sd_num_drives(int first_drive
)
947 /* We don't care which logical drive number(s) we have been assigned */
952 #endif /* CONFIG_STORAGE_MULTI */