2 * Copyright (C) 2010 Nathan Whitehorn
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
18 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
19 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
20 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
21 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
22 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
23 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #ifndef _POWERPC_PS3_IF_GLCREG_H
29 #define _POWERPC_PS3_IF_GLCREG_H
31 #define GLC_MAX_TX_PACKETS 128
32 #define GLC_MAX_RX_PACKETS 128
37 * software state for transmit job mbufs (may be elements of mbuf chains)
41 struct mbuf
*txs_mbuf
; /* head of our mbuf chain */
42 bus_dmamap_t txs_dmamap
; /* our DMA map */
43 int txs_firstdesc
; /* first descriptor in packet */
44 int txs_lastdesc
; /* last descriptor in packet */
46 int txs_ndescs
; /* number of descriptors */
47 STAILQ_ENTRY(glc_txsoft
) txs_q
;
50 STAILQ_HEAD(glc_txsq
, glc_txsoft
);
53 * software state for receive jobs
56 struct mbuf
*rxs_mbuf
; /* head of our mbuf chain */
57 bus_dmamap_t rxs_dmamap
; /* our DMA map */
59 int rxs_desc_slot
; /* DMA descriptor for this packet */
62 bus_dma_segment_t segment
;
69 u_char sc_enaddr
[ETHER_ADDR_LEN
];
70 int sc_tx_vlan
, sc_rx_vlan
;
73 uint64_t sc_dma_base
[5];
74 bus_dma_tag_t sc_dmadesc_tag
;
77 struct resource
*sc_irq
;
79 uint64_t *sc_hwirq_status
;
80 volatile uint64_t sc_interrupt_status
;
82 struct ifmedia sc_media
;
86 bus_dma_tag_t sc_txdma_tag
;
87 struct glc_txsoft sc_txsoft
[GLC_MAX_TX_PACKETS
];
88 struct glc_dmadesc
*sc_txdmadesc
;
89 int next_txdma_slot
, first_used_txdma_slot
, bsy_txdma_slots
;
90 bus_dmamap_t sc_txdmadesc_map
;
91 bus_addr_t sc_txdmadesc_phys
;
93 struct glc_txsq sc_txfreeq
;
94 struct glc_txsq sc_txdirtyq
;
98 bus_dma_tag_t sc_rxdma_tag
;
99 struct glc_rxsoft sc_rxsoft
[GLC_MAX_RX_PACKETS
];
100 struct glc_dmadesc
*sc_rxdmadesc
;
101 int sc_next_rxdma_slot
;
102 bus_dmamap_t sc_rxdmadesc_map
;
103 bus_addr_t sc_rxdmadesc_phys
;
107 struct callout sc_tick_ch
;
110 #define GELIC_GET_MAC_ADDRESS 0x0001
111 #define GELIC_GET_LINK_STATUS 0x0002
112 #define GELIC_SET_LINK_MODE 0x0003
113 #define GELIC_LINK_UP 0x0001
114 #define GELIC_FULL_DUPLEX 0x0002
115 #define GELIC_AUTO_NEG 0x0004
116 #define GELIC_SPEED_10 0x0010
117 #define GELIC_SPEED_100 0x0020
118 #define GELIC_SPEED_1000 0x0040
119 #define GELIC_GET_VLAN_ID 0x0004
120 #define GELIC_VLAN_TX_ETHERNET 0x0002
121 #define GELIC_VLAN_RX_ETHERNET 0x0012
122 #define GELIC_VLAN_TX_WIRELESS 0x0003
123 #define GELIC_VLAN_RX_WIRELESS 0x0013
125 /* Command status code */
126 #define GELIC_DESCR_OWNED 0xa0000000
127 #define GELIC_CMDSTAT_DMA_DONE 0x00000000
128 #define GELIC_CMDSTAT_CHAIN_END 0x00000002
129 #define GELIC_CMDSTAT_CSUM_TCP 0x00020000
130 #define GELIC_CMDSTAT_CSUM_UDP 0x00030000
131 #define GELIC_CMDSTAT_NOIPSEC 0x00080000
132 #define GELIC_CMDSTAT_LAST 0x00040000
133 #define GELIC_RXERRORS 0x7def8000
135 /* RX Data Status codes */
136 #define GELIC_RX_IPCSUM 0x20000000
137 #define GELIC_RX_TCPUDPCSUM 0x10000000
139 /* Interrupt options */
140 #define GELIC_INT_RXDONE 0x0000000000004000UL
141 #define GELIC_INT_RXFRAME 0x1000000000000000UL
142 #define GELIC_INT_TXDONE 0x0080000000000000UL
143 #define GELIC_INT_TX_CHAIN_END 0x0100000000000000UL
144 #define GELIC_INT_PHY 0x0000000020000000UL
146 /* Hardware DMA descriptor. Must be 32-byte aligned */
149 uint32_t paddr
; /* Must be 128 byte aligned for receive */
153 uint32_t result_size
;
159 #endif /* _POWERPC_PS3_IF_GLCREG_H */