arch/alpha/kernel/sys_sio.c

   1 /*
   2  *      linux/arch/alpha/kernel/sys_sio.c
   3  *
   4  *      Copyright (C) 1995 David A Rusling
   5  *      Copyright (C) 1996 Jay A Estabrook
   6  *      Copyright (C) 1998 Richard Henderson
   7  *
   8  * Code for all boards that route the PCI interrupts through the SIO
   9  * PCI/ISA bridge.  This includes Noname (AXPpci33), Multia (UDB),
  10  * Kenetics's Platform 2000, Avanti (AlphaStation), XL, and AlphaBook1.
  11  */
  12
  13 #include <linux/config.h>
  14 #include <linux/kernel.h>
  15 #include <linux/types.h>
  16 #include <linux/mm.h>
  17 #include <linux/sched.h>
  18 #include <linux/pci.h>
  19 #include <linux/init.h>
  20
  21 #include <asm/compiler.h>
  22 #include <asm/ptrace.h>
  23 #include <asm/system.h>
  24 #include <asm/dma.h>
  25 #include <asm/irq.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/io.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/core_apecs.h>
  30 #include <asm/core_lca.h>
  31
  32 #include "proto.h"
  33 #include "irq.h"
  34 #include "bios32.h"
  35 #include "machvec.h"
  36
  37 static void
  38 sio_update_irq_hw(unsigned long irq, unsigned long mask, int unmask_p)
  39 {
  40         if (irq >= 8)
  41                 outb(mask >> 8, 0xA1);
  42         else
  43                 outb(mask, 0x21);
  44 }
  45
  46 static void __init
  47 sio_init_irq(void)
  48 {
  49         STANDARD_INIT_IRQ_PROLOG;
  50
  51         if (alpha_using_srm)
  52                 alpha_mv.device_interrupt = srm_device_interrupt;
  53
  54         enable_irq(2);                  /* enable cascade */
  55 }
  56
  57 static inline void __init
  58 xl_init_arch(unsigned long *mem_start, unsigned long *mem_end)
  59 {
  60         /*
  61          * Set up the PCI->physical memory translation windows.  For
  62          * the XL we *must* use both windows, in order to maximize the
  63          * amount of physical memory that can be used to DMA from the
  64          * ISA bus, and still allow PCI bus devices access to all of
  65          * host memory.
  66          *
  67          * See <asm/apecs.h> for window bases and sizes.
  68          *
  69          * This restriction due to the true XL motherboards' 82379AB SIO
  70          * PCI<->ISA bridge chip which passes only 27 bits of address...
  71          */
  72
  73         *(vuip)APECS_IOC_PB1R = 1<<19 | (APECS_XL_DMA_WIN1_BASE & 0xfff00000U);
  74         *(vuip)APECS_IOC_PM1R = (APECS_XL_DMA_WIN1_SIZE - 1) & 0xfff00000U;
  75         *(vuip)APECS_IOC_TB1R = 0;
  76
  77         *(vuip)APECS_IOC_PB2R = 1<<19 | (APECS_XL_DMA_WIN2_BASE & 0xfff00000U);
  78         *(vuip)APECS_IOC_PM2R = (APECS_XL_DMA_WIN2_SIZE - 1) & 0xfff00000U;
  79         *(vuip)APECS_IOC_TB2R = 0;
  80
  81         /*
  82          * Finally, clear the HAXR2 register, which gets used for PCI
  83          * Config Space accesses. That is the way we want to use it,
  84          * and we do not want to depend on what ARC or SRM might have
  85          * left behind...
  86          */
  87
  88         *(vuip)APECS_IOC_HAXR2 = 0; mb();
  89 }
  90
  91 static inline void __init
  92 alphabook1_init_arch(unsigned long *mem_start, unsigned long *mem_end)
  93 {
  94         /* The AlphaBook1 has LCD video fixed at 800x600,
  95            37 rows and 100 cols. */
  96         screen_info.orig_y = 37;
  97         screen_info.orig_video_cols = 100;
  98         screen_info.orig_video_lines = 37;
  99
 100         lca_init_arch(mem_start, mem_end);
 101 }
 102
 103
 104 /*
 105  * sio_route_tab selects irq routing in PCI/ISA bridge so that:
 106  *              PIRQ0 -> irq 15
 107  *              PIRQ1 -> irq  9
 108  *              PIRQ2 -> irq 10
 109  *              PIRQ3 -> irq 11
 110  *
 111  * This probably ought to be configurable via MILO.  For
 112  * example, sound boards seem to like using IRQ 9.
 113  *
 114  * This is NOT how we should do it. PIRQ0-X should have
 115  * their own IRQ's, the way intel uses the IO-APIC irq's.
 116  */
 117 static unsigned long sio_route_tab __initdata = 0;
 118
 119 static void __init
 120 sio_pci_fixup(int (*map_irq)(struct pci_dev *dev, int sel, int pin),
 121               unsigned long new_route_tab)
 122 {
 123         unsigned int route_tab;
 124
 125         /* Examine or update the PCI routing table.  */
 126         pcibios_read_config_dword(0, PCI_DEVFN(7, 0), 0x60, &route_tab);
 127
 128         sio_route_tab = route_tab;
 129         if (PCI_MODIFY) {
 130                 sio_route_tab = new_route_tab;
 131                 pcibios_write_config_dword(0, PCI_DEVFN(7, 0), 0x60,
 132                                            new_route_tab);
 133         }
 134
 135         /* Update all the IRQs.  */
 136         common_pci_fixup(map_irq, common_swizzle);
 137 }
 138
 139 static unsigned int __init
 140 sio_collect_irq_levels(void)
 141 {
 142         unsigned int level_bits = 0;
 143         struct pci_dev *dev;
 144
 145         /* Iterate through the devices, collecting IRQ levels.  */
 146         for (dev = pci_devices; dev; dev = dev->next) {
 147                 if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
 148                     (dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
 149                         continue;
 150
 151                 if (dev->irq)
 152                         level_bits |= (1 << dev->irq);
 153         }
 154         return level_bits;
 155 }
 156
 157 static void __init
 158 sio_fixup_irq_levels(unsigned int level_bits)
 159 {
 160         unsigned int old_level_bits;
 161
 162         /*
 163          * Now, make all PCI interrupts level sensitive.  Notice:
 164          * these registers must be accessed byte-wise.  inw()/outw()
 165          * don't work.
 166          *
 167          * Make sure to turn off any level bits set for IRQs 9,10,11,15,
 168          *  so that the only bits getting set are for devices actually found.
 169          * Note that we do preserve the remainder of the bits, which we hope
 170          *  will be set correctly by ARC/SRM.
 171          *
 172          * Note: we at least preserve any level-set bits on AlphaBook1
 173          */
 174         old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);
 175
 176         level_bits |= (old_level_bits & 0x71ff);
 177
 178         outb((level_bits >> 0) & 0xff, 0x4d0);
 179         outb((level_bits >> 8) & 0xff, 0x4d1);
 180 }
 181
 182 static inline int __init
 183 noname_map_irq(struct pci_dev *dev, int slot, int pin)
 184 {
 185         /*
 186          * The Noname board has 5 PCI slots with each of the 4
 187          * interrupt pins routed to different pins on the PCI/ISA
 188          * bridge (PIRQ0-PIRQ3).  The table below is based on
 189          * information available at:
 190          *
 191          *   http://ftp.digital.com/pub/DEC/axppci/ref_interrupts.txt
 192          *
 193          * I have no information on the Avanti interrupt routing, but
 194          * the routing seems to be identical to the Noname except
 195          * that the Avanti has an additional slot whose routing I'm
 196          * unsure of.
 197          *
 198          * pirq_tab[0] is a fake entry to deal with old PCI boards
 199          * that have the interrupt pin number hardwired to 0 (meaning
 200          * that they use the default INTA line, if they are interrupt
 201          * driven at all).
 202          */
 203         static char irq_tab[][5] __initlocaldata = {
 204                 /*INT A   B   C   D */
 205                 { 3,  3,  3,  3,  3}, /* idsel  6 (53c810) */
 206                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 207                 { 2,  2, -1, -1, -1}, /* idsel  8 (Hack: slot closest ISA) */
 208                 {-1, -1, -1, -1, -1}, /* idsel  9 (unused) */
 209                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 210                 { 0,  0,  2,  1,  0}, /* idsel 11 KN25_PCI_SLOT0 */
 211                 { 1,  1,  0,  2,  1}, /* idsel 12 KN25_PCI_SLOT1 */
 212                 { 2,  2,  1,  0,  2}, /* idsel 13 KN25_PCI_SLOT2 */
 213                 { 0,  0,  0,  0,  0}, /* idsel 14 AS255 TULIP */
 214         };
 215         const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
 216         int irq = COMMON_TABLE_LOOKUP, tmp;
 217         tmp = __kernel_extbl(sio_route_tab, irq);
 218         return irq >= 0 ? tmp : -1;
 219 }
 220
 221 static inline void __init
 222 noname_pci_fixup(void)
 223 {
 224         /*
 225          * For UDB, the only available PCI slot must not map to IRQ 9,
 226          * since that's the builtin MSS sound chip. That PCI slot
 227          * will map to PIRQ1 (for INTA at least), so we give it IRQ 15
 228          * instead.
 229          *
 230          * Unfortunately we have to do this for NONAME as well, since
 231          * they are co-indicated when the platform type "Noname" is
 232          * selected... :-(
 233          */
 234         layout_all_busses(DEFAULT_IO_BASE, APECS_AND_LCA_DEFAULT_MEM_BASE);
 235         sio_pci_fixup(noname_map_irq, 0x0b0a0f0d);
 236         sio_fixup_irq_levels(sio_collect_irq_levels());
 237         enable_ide(0x26e);
 238 }
 239
 240 static inline void __init
 241 avanti_pci_fixup(void)
 242 {
 243         layout_all_busses(DEFAULT_IO_BASE, APECS_AND_LCA_DEFAULT_MEM_BASE);
 244         sio_pci_fixup(noname_map_irq, 0x0b0a0e0f);
 245         sio_fixup_irq_levels(sio_collect_irq_levels());
 246         enable_ide(0x26e);
 247 }
 248
 249 static inline void __init
 250 xl_pci_fixup(void)
 251 {
 252         layout_all_busses(DEFAULT_IO_BASE, XL_DEFAULT_MEM_BASE);
 253         sio_pci_fixup(noname_map_irq, 0x0b0a090f);
 254         sio_fixup_irq_levels(sio_collect_irq_levels());
 255         enable_ide(0x26e);
 256 }
 257
 258 static inline int __init
 259 p2k_map_irq(struct pci_dev *dev, int slot, int pin)
 260 {
 261         static char irq_tab[][5] __initlocaldata = {
 262                 /*INT A   B   C   D */
 263                 { 0,  0, -1, -1, -1}, /* idsel  6 (53c810) */
 264                 {-1, -1, -1, -1, -1}, /* idsel  7 (SIO: PCI/ISA bridge) */
 265                 { 1,  1,  2,  3,  0}, /* idsel  8 (slot A) */
 266                 { 2,  2,  3,  0,  1}, /* idsel  9 (slot B) */
 267                 {-1, -1, -1, -1, -1}, /* idsel 10 (unused) */
 268                 {-1, -1, -1, -1, -1}, /* idsel 11 (unused) */
 269                 { 3,  3, -1, -1, -1}, /* idsel 12 (CMD0646) */
 270         };
 271         const long min_idsel = 6, max_idsel = 12, irqs_per_slot = 5;
 272         int irq = COMMON_TABLE_LOOKUP, tmp;
 273         tmp = __kernel_extbl(sio_route_tab, irq);
 274         return irq >= 0 ? tmp : -1;
 275 }
 276
 277 static inline void __init
 278 p2k_pci_fixup(void)
 279 {
 280         layout_all_busses(DEFAULT_IO_BASE, APECS_AND_LCA_DEFAULT_MEM_BASE);
 281         sio_pci_fixup(p2k_map_irq, 0x0b0a090f);
 282         sio_fixup_irq_levels(sio_collect_irq_levels());
 283         enable_ide(0x26e);
 284 }
 285
 286 static inline void __init
 287 alphabook1_pci_fixup(void)
 288 {
 289         struct pci_dev *dev;
 290         unsigned char orig, config;
 291
 292         layout_all_busses(DEFAULT_IO_BASE, APECS_AND_LCA_DEFAULT_MEM_BASE);
 293
 294         /* For the AlphaBook1, NCR810 SCSI is 14, PCMCIA controller is 15. */
 295         sio_pci_fixup(noname_map_irq, 0x0e0f0a0a);
 296
 297         /*
 298          * On the AlphaBook1, the PCMCIA chip (Cirrus 6729)
 299          * is sensitive to PCI bus bursts, so we must DISABLE
 300          * burst mode for the NCR 8xx SCSI... :-(
 301          *
 302          * Note that the NCR810 SCSI driver must preserve the
 303          * setting of the bit in order for this to work.  At the
 304          * moment (2.0.29), ncr53c8xx.c does NOT do this, but
 305          * 53c7,8xx.c DOES.
 306          */
 307         for (dev = pci_devices; dev; dev = dev->next) {
 308                 if (dev->vendor == PCI_VENDOR_ID_NCR &&
 309                     (dev->device == PCI_DEVICE_ID_NCR_53C810 ||
 310                      dev->device == PCI_DEVICE_ID_NCR_53C815 ||
 311                      dev->device == PCI_DEVICE_ID_NCR_53C820 ||
 312                      dev->device == PCI_DEVICE_ID_NCR_53C825)) {
 313                         unsigned int io_port;
 314                         unsigned char ctest4;
 315
 316                         pcibios_read_config_dword(dev->bus->number,
 317                                                   dev->devfn,
 318                                                   PCI_BASE_ADDRESS_0,
 319                                                   &io_port);
 320                         io_port &= PCI_BASE_ADDRESS_IO_MASK;
 321                         ctest4 = inb(io_port+0x21);
 322                         if (!(ctest4 & 0x80)) {
 323                                 printk("AlphaBook1 NCR init: setting"
 324                                        " burst disable\n");
 325                                 outb(ctest4 | 0x80, io_port+0x21);
 326                         }
 327                 }
 328         }
 329
 330         /* Do not set *ANY* level triggers for AlphaBook1. */
 331         sio_fixup_irq_levels(0);
 332
 333         /* Make sure that register PR1 indicates 1Mb mem */
 334         outb(0x0f, 0x3ce); orig = inb(0x3cf);   /* read PR5  */
 335         outb(0x0f, 0x3ce); outb(0x05, 0x3cf);   /* unlock PR0-4 */
 336         outb(0x0b, 0x3ce); config = inb(0x3cf); /* read PR1 */
 337         if ((config & 0xc0) != 0xc0) {
 338                 printk("AlphaBook1 VGA init: setting 1Mb memory\n");
 339                 config |= 0xc0;
 340                 outb(0x0b, 0x3ce); outb(config, 0x3cf); /* write PR1 */
 341         }
 342         outb(0x0f, 0x3ce); outb(orig, 0x3cf); /* (re)lock PR0-4 */
 343 }
 344
 345
 346 /*
 347  * The System Vectors
 348  */
 349
 350 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_BOOK1)
 351 struct alpha_machine_vector alphabook1_mv __initmv = {
 352         vector_name:            "AlphaBook1",
 353         DO_EV4_MMU,
 354         DO_DEFAULT_RTC,
 355         DO_LCA_IO,
 356         DO_LCA_BUS,
 357         machine_check:          lca_machine_check,
 358         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 359
 360         nr_irqs:                16,
 361         irq_probe_mask:         _PROBE_MASK(16),
 362         update_irq_hw:          sio_update_irq_hw,
 363         ack_irq:                generic_ack_irq,
 364         device_interrupt:       isa_device_interrupt,
 365
 366         init_arch:              alphabook1_init_arch,
 367         init_irq:               sio_init_irq,
 368         init_pit:               generic_init_pit,
 369         pci_fixup:              alphabook1_pci_fixup,
 370         kill_arch:              generic_kill_arch,
 371 };
 372 ALIAS_MV(alphabook1)
 373 #endif
 374
 375 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_AVANTI)
 376 struct alpha_machine_vector avanti_mv __initmv = {
 377         vector_name:            "Avanti",
 378         DO_EV4_MMU,
 379         DO_DEFAULT_RTC,
 380         DO_APECS_IO,
 381         DO_APECS_BUS,
 382         machine_check:          apecs_machine_check,
 383         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 384
 385         nr_irqs:                16,
 386         irq_probe_mask:         _PROBE_MASK(16),
 387         update_irq_hw:          sio_update_irq_hw,
 388         ack_irq:                generic_ack_irq,
 389         device_interrupt:       isa_device_interrupt,
 390
 391         init_arch:              apecs_init_arch,
 392         init_irq:               sio_init_irq,
 393         init_pit:               generic_init_pit,
 394         pci_fixup:              avanti_pci_fixup,
 395         kill_arch:              generic_kill_arch,
 396 };
 397 ALIAS_MV(avanti)
 398 #endif
 399
 400 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_NONAME)
 401 struct alpha_machine_vector noname_mv __initmv = {
 402         vector_name:            "Noname",
 403         DO_EV4_MMU,
 404         DO_DEFAULT_RTC,
 405         DO_LCA_IO,
 406         DO_LCA_BUS,
 407         machine_check:          lca_machine_check,
 408         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 409
 410         nr_irqs:                16,
 411         irq_probe_mask:         _PROBE_MASK(16),
 412         update_irq_hw:          sio_update_irq_hw,
 413         ack_irq:                generic_ack_irq,
 414         device_interrupt:       srm_device_interrupt,
 415
 416         init_arch:              lca_init_arch,
 417         init_irq:               sio_init_irq,
 418         init_pit:               generic_init_pit,
 419         pci_fixup:              noname_pci_fixup,
 420         kill_arch:              generic_kill_arch,
 421 };
 422 ALIAS_MV(noname)
 423 #endif
 424
 425 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_P2K)
 426 struct alpha_machine_vector p2k_mv __initmv = {
 427         vector_name:            "Platform2000",
 428         DO_EV4_MMU,
 429         DO_DEFAULT_RTC,
 430         DO_LCA_IO,
 431         DO_LCA_BUS,
 432         machine_check:          lca_machine_check,
 433         max_dma_address:        ALPHA_MAX_DMA_ADDRESS,
 434
 435         nr_irqs:                16,
 436         irq_probe_mask:         P2K_PROBE_MASK,
 437         update_irq_hw:          sio_update_irq_hw,
 438         ack_irq:                generic_ack_irq,
 439         device_interrupt:       srm_device_interrupt,
 440
 441         init_arch:              lca_init_arch,
 442         init_irq:               sio_init_irq,
 443         init_pit:               generic_init_pit,
 444         pci_fixup:              p2k_pci_fixup,
 445         kill_arch:              generic_kill_arch,
 446 };
 447 ALIAS_MV(p2k)
 448 #endif
 449
 450 #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_XL)
 451 struct alpha_machine_vector xl_mv __initmv = {
 452         vector_name:            "XL",
 453         DO_EV4_MMU,
 454         DO_DEFAULT_RTC,
 455         DO_APECS_IO,
 456         BUS(apecs_xl),
 457         machine_check:          apecs_machine_check,
 458         max_dma_address:        ALPHA_XL_MAX_DMA_ADDRESS,
 459
 460         nr_irqs:                16,
 461         irq_probe_mask:         _PROBE_MASK(16),
 462         update_irq_hw:          sio_update_irq_hw,
 463         ack_irq:                generic_ack_irq,
 464         device_interrupt:       isa_device_interrupt,
 465
 466         init_arch:              xl_init_arch,
 467         init_irq:               sio_init_irq,
 468         init_pit:               generic_init_pit,
 469         pci_fixup:              xl_pci_fixup,
 470         kill_arch:              generic_kill_arch,
 471 };
 472 ALIAS_MV(xl)
 473 #endif