include/asm-sparc64/pbm.h

   1 /* $Id: pbm.h,v 1.17 1999/08/30 10:14:54 davem Exp $
   2  * pbm.h: UltraSparc PCI controller software state.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@redhat.com)
   5  */
   6
   7 #ifndef __SPARC64_PBM_H
   8 #define __SPARC64_PBM_H
   9
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/ioport.h>
  13 #include <linux/spinlock.h>
  14
  15 #include <asm/io.h>
  16 #include <asm/page.h>
  17 #include <asm/oplib.h>
  18
  19 /* The abstraction used here is that there are PCI controllers,
  20  * each with one (Sabre) or two (PSYCHO/SCHIZO) PCI bus modules
  21  * underneath.  Each PCI controller has a single IOMMU shared
  22  * by the PCI bus modules underneath, and if a streaming buffer
  23  * is present, each PCI bus module has it's own. (ie. the IOMMU
  24  * is shared between PBMs, the STC is not)  Furthermore, each
  25  * PCI bus module controls it's own autonomous PCI bus.
  26  */
  27
  28 struct pci_controller_info;
  29
  30 /* This contains the software state necessary to drive a PCI
  31  * controller's IOMMU.
  32  */
  33 struct pci_iommu {
  34         /* This protects the controller's IOMMU and all
  35          * streaming buffers underneath.
  36          */
  37         spinlock_t      lock;
  38
  39         /* Context allocator. */
  40         unsigned int    iommu_cur_ctx;
  41
  42         /* IOMMU page table, a linear array of ioptes. */
  43         iopte_t         *page_table;    /* The page table itself. */
  44         int             page_table_sz;  /* How many pages does it map? */
  45
  46         /* Base PCI memory space address where IOMMU mappings
  47          * begin.
  48          */
  49         u32             page_table_map_base;
  50
  51         /* IOMMU Controller Registers */
  52         int             iommu_has_ctx_flush;    /* Feature test. */
  53         unsigned long   iommu_control;          /* IOMMU control register */
  54         unsigned long   iommu_tsbbase;          /* IOMMU page table base register */
  55         unsigned long   iommu_flush;            /* IOMMU page flush register */
  56         unsigned long   iommu_ctxflush;         /* IOMMU context flush register */
  57
  58         /* This is a register in the PCI controller, which if
  59          * read will have no side-effects but will guarentee
  60          * completion of all previous writes into IOMMU/STC.
  61          */
  62         unsigned long   write_complete_reg;
  63 };
  64
  65 /* This describes a PCI bus module's streaming buffer. */
  66 struct pci_strbuf {
  67         int             strbuf_enabled;         /* Present and using it? */
  68         int             strbuf_has_ctx_flush;   /* Supports context flushing? */
  69
  70         /* Streaming Buffer Control Registers */
  71         unsigned long   strbuf_control;         /* STC control register */
  72         unsigned long   strbuf_pflush;          /* STC page flush register */
  73         unsigned long   strbuf_fsync;           /* STC flush synchronization reg */
  74         unsigned long   strbuf_ctxflush;        /* STC context flush register */
  75         unsigned long   strbuf_ctxmatch_base;   /* STC context flush match reg */
  76         unsigned long   strbuf_flushflag_pa;    /* Physical address of flush flag */
  77         volatile unsigned long *strbuf_flushflag; /* The flush flag itself */
  78
  79         /* And this is the actual flush flag area.
  80          * We allocate extra because the chips require
  81          * a 64-byte aligned area.
  82          */
  83         volatile unsigned long  __flushflag_buf[(64 + (64 - 1)) / sizeof(long)];
  84 };
  85
  86 #define PCI_STC_FLUSHFLAG_INIT(STC) \
  87         (*((STC)->strbuf_flushflag) = 0UL)
  88 #define PCI_STC_FLUSHFLAG_SET(STC) \
  89         (*((STC)->strbuf_flushflag) != 0UL)
  90
  91 /* There can be quite a few ranges and interrupt maps on a PCI
  92  * segment.  Thus...
  93  */
  94 #define PROM_PCIRNG_MAX         64
  95 #define PROM_PCIIMAP_MAX        64
  96
  97 struct pci_pbm_info {
  98         /* PCI controller we sit under. */
  99         struct pci_controller_info      *parent;
 100
 101         /* Name used for top-level resources. */
 102         char                            name[64];
 103
 104         /* OBP specific information. */
 105         int                             prom_node;
 106         char                            prom_name[64];
 107         struct linux_prom_pci_ranges    pbm_ranges[PROM_PCIRNG_MAX];
 108         int                             num_pbm_ranges;
 109         struct linux_prom_pci_intmap    pbm_intmap[PROM_PCIIMAP_MAX];
 110         int                             num_pbm_intmap;
 111         struct linux_prom_pci_intmask   pbm_intmask;
 112
 113         /* PBM I/O and Memory space resources. */
 114         struct resource                 io_space;
 115         struct resource                 mem_space;
 116
 117         /* This PBM's streaming buffer. */
 118         struct pci_strbuf               stc;
 119
 120         /* Now things for the actual PCI bus probes. */
 121         unsigned int                    pci_first_busno;
 122         unsigned int                    pci_last_busno;
 123         struct pci_bus                  *pci_bus;
 124 };
 125
 126 struct pci_controller_info {
 127         /* List of all PCI controllers. */
 128         struct pci_controller_info      *next;
 129
 130         /* Physical address base of controller registers
 131          * and PCI config space.
 132          */
 133         unsigned long                   controller_regs;
 134         unsigned long                   config_space;
 135
 136         /* Opaque 32-bit system bus Port ID. */
 137         u32                             portid;
 138
 139         /* Each controller gets a unique index, used mostly for
 140          * error logging purposes.
 141          */
 142         int                             index;
 143
 144         /* The PCI bus modules controlled by us. */
 145         struct pci_pbm_info             pbm_A;
 146         struct pci_pbm_info             pbm_B;
 147
 148         /* Operations which are controller specific. */
 149         void (*scan_bus)(struct pci_controller_info *);
 150         unsigned int (*irq_build)(struct pci_controller_info *, struct pci_dev *, unsigned int);
 151         void (*base_address_update)(struct pci_dev *, int);
 152         void (*resource_adjust)(struct pci_dev *, struct resource *, struct resource *);
 153
 154         /* Now things for the actual PCI bus probes. */
 155         struct pci_ops                  *pci_ops;
 156         unsigned int                    pci_first_busno;
 157         unsigned int                    pci_last_busno;
 158
 159         /* IOMMU state shared by both PBM segments. */
 160         struct pci_iommu                iommu;
 161
 162         void                            *starfire_cookie;
 163 };
 164
 165 /* PCI devices which are not bridges have this placed in their pci_dev
 166  * sysdata member.  This makes OBP aware PCI device drivers easier to
 167  * code.
 168  */
 169 struct pcidev_cookie {
 170         struct pci_pbm_info             *pbm;
 171         char                            prom_name[64];
 172         int                             prom_node;
 173         struct linux_prom_pci_registers prom_regs[PROMREG_MAX];
 174         int num_prom_regs;
 175         struct linux_prom_pci_registers prom_assignments[PROMREG_MAX];
 176         int num_prom_assignments;
 177 };
 178
 179 /* Currently these are the same across all PCI controllers
 180  * we support.  Someday they may not be...
 181  */
 182 #define PCI_IRQ_IGN     0x000007c0      /* Interrupt Group Number */
 183 #define PCI_IRQ_INO     0x0000003f      /* Interrupt Number */
 184
 185 #endif /* !(__SPARC64_PBM_H) */