include/asm-sparc64/iommu.h

   1 /* iommu.h: Definitions for the sun5 IOMMU.
   2  *
   3  * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
   4  */
   5 #ifndef _SPARC64_IOMMU_H
   6 #define _SPARC64_IOMMU_H
   7
   8 #include <linux/spinlock.h>
   9 #include <asm/page.h>
  10 #include <asm/sysio.h>
  11
  12 /* The iommu handles all virtual to physical address translations
  13  * that occur between the SYSIO and physical memory.  Access by
  14  * the cpu to IO registers and similar go over the UPA so are
  15  * translated by the on chip TLB's.  The iommu and the TLB do
  16  * not need to have the same translations at all, in fact most
  17  * of the time the translations they handle are a disjoint set.
  18  * Basically the iommu handles all SYSIO dvma translations.
  19  */
  20
  21 /* The IOMMU register set. */
  22 #define IOMMU_CTRL_IMPL     0xf000000000000000 /* Implementation                */
  23 #define IOMMU_CTRL_VERS     0x0f00000000000000 /* Version                       */
  24 #define IOMMU_CTRL_TSBSZ    0x0000000000070000 /* TSB Size                      */
  25 #define IOMMU_TSBSZ_1K      0x0000000000000000 /* TSB Table 1024 8-byte entries */
  26 #define IOMMU_TSBSZ_2K      0x0000000000010000 /* TSB Table 2048 8-byte entries */
  27 #define IOMMU_TSBSZ_4K      0x0000000000020000 /* TSB Table 4096 8-byte entries */
  28 #define IOMMU_TSBSZ_8K      0x0000000000030000 /* TSB Table 8192 8-byte entries */
  29 #define IOMMU_TSBSZ_16K     0x0000000000040000 /* TSB Table 16k 8-byte entries  */
  30 #define IOMMU_TSBSZ_32K     0x0000000000050000 /* TSB Table 32k 8-byte entries  */
  31 #define IOMMU_TSBSZ_64K     0x0000000000060000 /* TSB Table 64k 8-byte entries  */
  32 #define IOMMU_TSBSZ_128K    0x0000000000070000 /* TSB Table 128k 8-byte entries */
  33 #define IOMMU_CTRL_TBWSZ    0x0000000000000004 /* Assumed page size, 0=8k 1=64k */
  34 #define IOMMU_CTRL_DENAB    0x0000000000000002 /* Diagnostic mode enable        */
  35 #define IOMMU_CTRL_ENAB     0x0000000000000001 /* IOMMU Enable                  */
  36
  37 /* The format of an iopte in the page tables, we only use 64k pages. */
  38 #define IOPTE_VALID         0x8000000000000000 /* IOPTE is valid                   */
  39 #define IOPTE_64K           0x2000000000000000 /* IOPTE is for 64k page            */
  40 #define IOPTE_STBUF         0x1000000000000000 /* DVMA can use streaming buffer    */
  41 #define IOPTE_INTRA         0x0800000000000000 /* SBUS slot-->slot direct transfer */
  42 #define IOPTE_CONTEXT       0x07ff800000000000 /* Context number                   */
  43 #define IOPTE_PAGE          0x00007fffffffe000 /* Physical page number (PA[40:13]) */
  44 #define IOPTE_CACHE         0x0000000000000010 /* Cached (in UPA E-cache)          */
  45 #define IOPTE_WRITE         0x0000000000000002 /* Writeable                        */
  46
  47 struct iommu_struct {
  48         struct sysio_regs       *sysio_regs;
  49         iopte_t                 *page_table;
  50         volatile unsigned int   flushflag;
  51         unsigned int            strbuf_enabled;
  52         spinlock_t              iommu_lock;
  53 };
  54
  55 #endif /* !(_SPARC_IOMMU_H) */