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Import 2.3.18pre1
[davej-history.git] / drivers / scsi / qlogicisp.c
blob1b5d772a2eaf5d6de9ed84f404b1b7c7052e3dfe
1 /*
2 * QLogic ISP1020 Intelligent SCSI Processor Driver (PCI)
3 * Written by Erik H. Moe, ehm@cris.com
4 * Copyright 1995, Erik H. Moe
5 * Copyright 1996, 1997 Michael A. Griffith <grif@acm.org>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2, or (at your option) any
10 * later version.
11 *
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 */
17
18 #include <linux/blk.h>
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/ioport.h>
22 #include <linux/sched.h>
23 #include <linux/types.h>
24 #include <linux/pci.h>
25 #include <linux/delay.h>
26 #include <linux/unistd.h>
27 #include <linux/spinlock.h>
28 #include <asm/io.h>
29 #include <asm/irq.h>
30 #include <asm/byteorder.h>
31
32 #include "sd.h"
33 #include "hosts.h"
34 #include "qlogicisp.h"
35
36 /* Configuration section *****************************************************/
37
38 /* Set the following macro to 1 to reload the ISP1020's firmware. This is
39 the latest firmware provided by QLogic. This may be an earlier/later
40 revision than supplied by your board. */
41
42 #define RELOAD_FIRMWARE 1
43
44 /* Set the following macro to 1 to reload the ISP1020's defaults from nvram.
45 If you are not sure of your settings, leave this alone, the driver will
46 use a set of 'safe' defaults */
47
48 #define USE_NVRAM_DEFAULTS 0
49
50 /* Macros used for debugging */
51
52 #define DEBUG_ISP1020 0
53 #define DEBUG_ISP1020_INTR 0
54 #define DEBUG_ISP1020_SETUP 0
55 #define TRACE_ISP 0
56
57 #define DEFAULT_LOOP_COUNT 1000000
58
59 #define LinuxVersionCode(v, p, s) (((v)<<16)+((p)<<8)+(s))
60
61 /* End Configuration section *************************************************/
62
63 #include <linux/module.h>
64
65 #if TRACE_ISP
66
67 # define TRACE_BUF_LEN (32*1024)
68
69 struct {
70 u_long next;
71 struct {
72 u_long time;
73 u_int index;
74 u_int addr;
75 u_char * name;
76 } buf[TRACE_BUF_LEN];
77 } trace;
78
79 #define TRACE(w, i, a) \
80 { \
81 unsigned long flags; \
82 \
83 save_flags(flags); \
84 cli(); \
85 trace.buf[trace.next].name = (w); \
86 trace.buf[trace.next].time = jiffies; \
87 trace.buf[trace.next].index = (i); \
88 trace.buf[trace.next].addr = (long) (a); \
89 trace.next = (trace.next + 1) & (TRACE_BUF_LEN - 1); \
90 restore_flags(flags); \
91 }
92
93 #else
94 # define TRACE(w, i, a)
95 #endif
96
97 #if DEBUG_ISP1020
98 #define ENTER(x) printk("isp1020 : entering %s()\n", x);
99 #define LEAVE(x) printk("isp1020 : leaving %s()\n", x);
100 #define DEBUG(x) x
101 #else
102 #define ENTER(x)
103 #define LEAVE(x)
104 #define DEBUG(x)
105 #endif /* DEBUG_ISP1020 */
106
107 #if DEBUG_ISP1020_INTR
108 #define ENTER_INTR(x) printk("isp1020 : entering %s()\n", x);
109 #define LEAVE_INTR(x) printk("isp1020 : leaving %s()\n", x);
110 #define DEBUG_INTR(x) x
111 #else
112 #define ENTER_INTR(x)
113 #define LEAVE_INTR(x)
114 #define DEBUG_INTR(x)
115 #endif /* DEBUG ISP1020_INTR */
116
117 #define ISP1020_REV_ID 1
118
119 #define MAX_TARGETS 16
120 #define MAX_LUNS 8
121
122 /* host configuration and control registers */
123 #define HOST_HCCR 0xc0 /* host command and control */
124
125 /* pci bus interface registers */
126 #define PCI_ID_LOW 0x00 /* vendor id */
127 #define PCI_ID_HIGH 0x02 /* device id */
128 #define ISP_CFG0 0x04 /* configuration register #0 */
129 #define ISP_CFG1 0x06 /* configuration register #1 */
130 #define PCI_INTF_CTL 0x08 /* pci interface control */
131 #define PCI_INTF_STS 0x0a /* pci interface status */
132 #define PCI_SEMAPHORE 0x0c /* pci semaphore */
133 #define PCI_NVRAM 0x0e /* pci nvram interface */
134
135 /* mailbox registers */
136 #define MBOX0 0x70 /* mailbox 0 */
137 #define MBOX1 0x72 /* mailbox 1 */
138 #define MBOX2 0x74 /* mailbox 2 */
139 #define MBOX3 0x76 /* mailbox 3 */
140 #define MBOX4 0x78 /* mailbox 4 */
141 #define MBOX5 0x7a /* mailbox 5 */
142
143 /* mailbox command complete status codes */
144 #define MBOX_COMMAND_COMPLETE 0x4000
145 #define INVALID_COMMAND 0x4001
146 #define HOST_INTERFACE_ERROR 0x4002
147 #define TEST_FAILED 0x4003
148 #define COMMAND_ERROR 0x4005
149 #define COMMAND_PARAM_ERROR 0x4006
150
151 /* async event status codes */
152 #define ASYNC_SCSI_BUS_RESET 0x8001
153 #define SYSTEM_ERROR 0x8002
154 #define REQUEST_TRANSFER_ERROR 0x8003
155 #define RESPONSE_TRANSFER_ERROR 0x8004
156 #define REQUEST_QUEUE_WAKEUP 0x8005
157 #define EXECUTION_TIMEOUT_RESET 0x8006
158
159 struct Entry_header {
160 u_char entry_type;
161 u_char entry_cnt;
162 u_char sys_def_1;
163 u_char flags;
164 };
165
166 /* entry header type commands */
167 #define ENTRY_COMMAND 1
168 #define ENTRY_CONTINUATION 2
169 #define ENTRY_STATUS 3
170 #define ENTRY_MARKER 4
171 #define ENTRY_EXTENDED_COMMAND 5
172
173 /* entry header flag definitions */
174 #define EFLAG_CONTINUATION 1
175 #define EFLAG_BUSY 2
176 #define EFLAG_BAD_HEADER 4
177 #define EFLAG_BAD_PAYLOAD 8
178
179 struct dataseg {
180 u_int d_base;
181 u_int d_count;
182 };
183
184 struct Command_Entry {
185 struct Entry_header hdr;
186 u_int handle;
187 u_char target_lun;
188 u_char target_id;
189 u_short cdb_length;
190 u_short control_flags;
191 u_short rsvd;
192 u_short time_out;
193 u_short segment_cnt;
194 u_char cdb[12];
195 struct dataseg dataseg[4];
196 };
197
198 /* command entry control flag definitions */
199 #define CFLAG_NODISC 0x01
200 #define CFLAG_HEAD_TAG 0x02
201 #define CFLAG_ORDERED_TAG 0x04
202 #define CFLAG_SIMPLE_TAG 0x08
203 #define CFLAG_TAR_RTN 0x10
204 #define CFLAG_READ 0x20
205 #define CFLAG_WRITE 0x40
206
207 struct Ext_Command_Entry {
208 struct Entry_header hdr;
209 u_int handle;
210 u_char target_lun;
211 u_char target_id;
212 u_short cdb_length;
213 u_short control_flags;
214 u_short rsvd;
215 u_short time_out;
216 u_short segment_cnt;
217 u_char cdb[44];
218 };
219
220 struct Continuation_Entry {
221 struct Entry_header hdr;
222 u_int reserved;
223 struct dataseg dataseg[7];
224 };
225
226 struct Marker_Entry {
227 struct Entry_header hdr;
228 u_int reserved;
229 u_char target_lun;
230 u_char target_id;
231 u_char modifier;
232 u_char rsvd;
233 u_char rsvds[52];
234 };
235
236 /* marker entry modifier definitions */
237 #define SYNC_DEVICE 0
238 #define SYNC_TARGET 1
239 #define SYNC_ALL 2
240
241 struct Status_Entry {
242 struct Entry_header hdr;
243 u_int handle;
244 u_short scsi_status;
245 u_short completion_status;
246 u_short state_flags;
247 u_short status_flags;
248 u_short time;
249 u_short req_sense_len;
250 u_int residual;
251 u_char rsvd[8];
252 u_char req_sense_data[32];
253 };
254
255 /* status entry completion status definitions */
256 #define CS_COMPLETE 0x0000
257 #define CS_INCOMPLETE 0x0001
258 #define CS_DMA_ERROR 0x0002
259 #define CS_TRANSPORT_ERROR 0x0003
260 #define CS_RESET_OCCURRED 0x0004
261 #define CS_ABORTED 0x0005
262 #define CS_TIMEOUT 0x0006
263 #define CS_DATA_OVERRUN 0x0007
264 #define CS_COMMAND_OVERRUN 0x0008
265 #define CS_STATUS_OVERRUN 0x0009
266 #define CS_BAD_MESSAGE 0x000a
267 #define CS_NO_MESSAGE_OUT 0x000b
268 #define CS_EXT_ID_FAILED 0x000c
269 #define CS_IDE_MSG_FAILED 0x000d
270 #define CS_ABORT_MSG_FAILED 0x000e
271 #define CS_REJECT_MSG_FAILED 0x000f
272 #define CS_NOP_MSG_FAILED 0x0010
273 #define CS_PARITY_ERROR_MSG_FAILED 0x0011
274 #define CS_DEVICE_RESET_MSG_FAILED 0x0012
275 #define CS_ID_MSG_FAILED 0x0013
276 #define CS_UNEXP_BUS_FREE 0x0014
277 #define CS_DATA_UNDERRUN 0x0015
278
279 /* status entry state flag definitions */
280 #define SF_GOT_BUS 0x0100
281 #define SF_GOT_TARGET 0x0200
282 #define SF_SENT_CDB 0x0400
283 #define SF_TRANSFERRED_DATA 0x0800
284 #define SF_GOT_STATUS 0x1000
285 #define SF_GOT_SENSE 0x2000
286
287 /* status entry status flag definitions */
288 #define STF_DISCONNECT 0x0001
289 #define STF_SYNCHRONOUS 0x0002
290 #define STF_PARITY_ERROR 0x0004
291 #define STF_BUS_RESET 0x0008
292 #define STF_DEVICE_RESET 0x0010
293 #define STF_ABORTED 0x0020
294 #define STF_TIMEOUT 0x0040
295 #define STF_NEGOTIATION 0x0080
296
297 /* interface control commands */
298 #define ISP_RESET 0x0001
299 #define ISP_EN_INT 0x0002
300 #define ISP_EN_RISC 0x0004
301
302 /* host control commands */
303 #define HCCR_NOP 0x0000
304 #define HCCR_RESET 0x1000
305 #define HCCR_PAUSE 0x2000
306 #define HCCR_RELEASE 0x3000
307 #define HCCR_SINGLE_STEP 0x4000
308 #define HCCR_SET_HOST_INTR 0x5000
309 #define HCCR_CLEAR_HOST_INTR 0x6000
310 #define HCCR_CLEAR_RISC_INTR 0x7000
311 #define HCCR_BP_ENABLE 0x8000
312 #define HCCR_BIOS_DISABLE 0x9000
313 #define HCCR_TEST_MODE 0xf000
314
315 #define RISC_BUSY 0x0004
316
317 /* mailbox commands */
318 #define MBOX_NO_OP 0x0000
319 #define MBOX_LOAD_RAM 0x0001
320 #define MBOX_EXEC_FIRMWARE 0x0002
321 #define MBOX_DUMP_RAM 0x0003
322 #define MBOX_WRITE_RAM_WORD 0x0004
323 #define MBOX_READ_RAM_WORD 0x0005
324 #define MBOX_MAILBOX_REG_TEST 0x0006
325 #define MBOX_VERIFY_CHECKSUM 0x0007
326 #define MBOX_ABOUT_FIRMWARE 0x0008
327 #define MBOX_CHECK_FIRMWARE 0x000e
328 #define MBOX_INIT_REQ_QUEUE 0x0010
329 #define MBOX_INIT_RES_QUEUE 0x0011
330 #define MBOX_EXECUTE_IOCB 0x0012
331 #define MBOX_WAKE_UP 0x0013
332 #define MBOX_STOP_FIRMWARE 0x0014
333 #define MBOX_ABORT 0x0015
334 #define MBOX_ABORT_DEVICE 0x0016
335 #define MBOX_ABORT_TARGET 0x0017
336 #define MBOX_BUS_RESET 0x0018
337 #define MBOX_STOP_QUEUE 0x0019
338 #define MBOX_START_QUEUE 0x001a
339 #define MBOX_SINGLE_STEP_QUEUE 0x001b
340 #define MBOX_ABORT_QUEUE 0x001c
341 #define MBOX_GET_DEV_QUEUE_STATUS 0x001d
342 #define MBOX_GET_FIRMWARE_STATUS 0x001f
343 #define MBOX_GET_INIT_SCSI_ID 0x0020
344 #define MBOX_GET_SELECT_TIMEOUT 0x0021
345 #define MBOX_GET_RETRY_COUNT 0x0022
346 #define MBOX_GET_TAG_AGE_LIMIT 0x0023
347 #define MBOX_GET_CLOCK_RATE 0x0024
348 #define MBOX_GET_ACT_NEG_STATE 0x0025
349 #define MBOX_GET_ASYNC_DATA_SETUP_TIME 0x0026
350 #define MBOX_GET_PCI_PARAMS 0x0027
351 #define MBOX_GET_TARGET_PARAMS 0x0028
352 #define MBOX_GET_DEV_QUEUE_PARAMS 0x0029
353 #define MBOX_SET_INIT_SCSI_ID 0x0030
354 #define MBOX_SET_SELECT_TIMEOUT 0x0031
355 #define MBOX_SET_RETRY_COUNT 0x0032
356 #define MBOX_SET_TAG_AGE_LIMIT 0x0033
357 #define MBOX_SET_CLOCK_RATE 0x0034
358 #define MBOX_SET_ACTIVE_NEG_STATE 0x0035
359 #define MBOX_SET_ASYNC_DATA_SETUP_TIME 0x0036
360 #define MBOX_SET_PCI_CONTROL_PARAMS 0x0037
361 #define MBOX_SET_TARGET_PARAMS 0x0038
362 #define MBOX_SET_DEV_QUEUE_PARAMS 0x0039
363 #define MBOX_RETURN_BIOS_BLOCK_ADDR 0x0040
364 #define MBOX_WRITE_FOUR_RAM_WORDS 0x0041
365 #define MBOX_EXEC_BIOS_IOCB 0x0042
366
367 #include "qlogicisp_asm.c"
368
369 #define PACKB(a, b) (((a)<<4)|(b))
370
371 static const u_char mbox_param[] = {
372 PACKB(1, 1), /* MBOX_NO_OP */
373 PACKB(5, 5), /* MBOX_LOAD_RAM */
374 PACKB(2, 0), /* MBOX_EXEC_FIRMWARE */
375 PACKB(5, 5), /* MBOX_DUMP_RAM */
376 PACKB(3, 3), /* MBOX_WRITE_RAM_WORD */
377 PACKB(2, 3), /* MBOX_READ_RAM_WORD */
378 PACKB(6, 6), /* MBOX_MAILBOX_REG_TEST */
379 PACKB(2, 3), /* MBOX_VERIFY_CHECKSUM */
380 PACKB(1, 3), /* MBOX_ABOUT_FIRMWARE */
381 PACKB(0, 0), /* 0x0009 */
382 PACKB(0, 0), /* 0x000a */
383 PACKB(0, 0), /* 0x000b */
384 PACKB(0, 0), /* 0x000c */
385 PACKB(0, 0), /* 0x000d */
386 PACKB(1, 2), /* MBOX_CHECK_FIRMWARE */
387 PACKB(0, 0), /* 0x000f */
388 PACKB(5, 5), /* MBOX_INIT_REQ_QUEUE */
389 PACKB(6, 6), /* MBOX_INIT_RES_QUEUE */
390 PACKB(4, 4), /* MBOX_EXECUTE_IOCB */
391 PACKB(2, 2), /* MBOX_WAKE_UP */
392 PACKB(1, 6), /* MBOX_STOP_FIRMWARE */
393 PACKB(4, 4), /* MBOX_ABORT */
394 PACKB(2, 2), /* MBOX_ABORT_DEVICE */
395 PACKB(3, 3), /* MBOX_ABORT_TARGET */
396 PACKB(2, 2), /* MBOX_BUS_RESET */
397 PACKB(2, 3), /* MBOX_STOP_QUEUE */
398 PACKB(2, 3), /* MBOX_START_QUEUE */
399 PACKB(2, 3), /* MBOX_SINGLE_STEP_QUEUE */
400 PACKB(2, 3), /* MBOX_ABORT_QUEUE */
401 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_STATUS */
402 PACKB(0, 0), /* 0x001e */
403 PACKB(1, 3), /* MBOX_GET_FIRMWARE_STATUS */
404 PACKB(1, 2), /* MBOX_GET_INIT_SCSI_ID */
405 PACKB(1, 2), /* MBOX_GET_SELECT_TIMEOUT */
406 PACKB(1, 3), /* MBOX_GET_RETRY_COUNT */
407 PACKB(1, 2), /* MBOX_GET_TAG_AGE_LIMIT */
408 PACKB(1, 2), /* MBOX_GET_CLOCK_RATE */
409 PACKB(1, 2), /* MBOX_GET_ACT_NEG_STATE */
410 PACKB(1, 2), /* MBOX_GET_ASYNC_DATA_SETUP_TIME */
411 PACKB(1, 3), /* MBOX_GET_PCI_PARAMS */
412 PACKB(2, 4), /* MBOX_GET_TARGET_PARAMS */
413 PACKB(2, 4), /* MBOX_GET_DEV_QUEUE_PARAMS */
414 PACKB(0, 0), /* 0x002a */
415 PACKB(0, 0), /* 0x002b */
416 PACKB(0, 0), /* 0x002c */
417 PACKB(0, 0), /* 0x002d */
418 PACKB(0, 0), /* 0x002e */
419 PACKB(0, 0), /* 0x002f */
420 PACKB(2, 2), /* MBOX_SET_INIT_SCSI_ID */
421 PACKB(2, 2), /* MBOX_SET_SELECT_TIMEOUT */
422 PACKB(3, 3), /* MBOX_SET_RETRY_COUNT */
423 PACKB(2, 2), /* MBOX_SET_TAG_AGE_LIMIT */
424 PACKB(2, 2), /* MBOX_SET_CLOCK_RATE */
425 PACKB(2, 2), /* MBOX_SET_ACTIVE_NEG_STATE */
426 PACKB(2, 2), /* MBOX_SET_ASYNC_DATA_SETUP_TIME */
427 PACKB(3, 3), /* MBOX_SET_PCI_CONTROL_PARAMS */
428 PACKB(4, 4), /* MBOX_SET_TARGET_PARAMS */
429 PACKB(4, 4), /* MBOX_SET_DEV_QUEUE_PARAMS */
430 PACKB(0, 0), /* 0x003a */
431 PACKB(0, 0), /* 0x003b */
432 PACKB(0, 0), /* 0x003c */
433 PACKB(0, 0), /* 0x003d */
434 PACKB(0, 0), /* 0x003e */
435 PACKB(0, 0), /* 0x003f */
436 PACKB(1, 2), /* MBOX_RETURN_BIOS_BLOCK_ADDR */
437 PACKB(6, 1), /* MBOX_WRITE_FOUR_RAM_WORDS */
438 PACKB(2, 3) /* MBOX_EXEC_BIOS_IOCB */
439 };
440
441 #define MAX_MBOX_COMMAND (sizeof(mbox_param)/sizeof(u_short))
442
443 struct host_param {
444 u_short fifo_threshold;
445 u_short host_adapter_enable;
446 u_short initiator_scsi_id;
447 u_short bus_reset_delay;
448 u_short retry_count;
449 u_short retry_delay;
450 u_short async_data_setup_time;
451 u_short req_ack_active_negation;
452 u_short data_line_active_negation;
453 u_short data_dma_burst_enable;
454 u_short command_dma_burst_enable;
455 u_short tag_aging;
456 u_short selection_timeout;
457 u_short max_queue_depth;
458 };
459
460 /*
461 * Device Flags:
462 *
463 * Bit Name
464 * ---------
465 * 7 Disconnect Privilege
466 * 6 Parity Checking
467 * 5 Wide Data Transfers
468 * 4 Synchronous Data Transfers
469 * 3 Tagged Queuing
470 * 2 Automatic Request Sense
471 * 1 Stop Queue on Check Condition
472 * 0 Renegotiate on Error
473 */
474
475 struct dev_param {
476 u_short device_flags;
477 u_short execution_throttle;
478 u_short synchronous_period;
479 u_short synchronous_offset;
480 u_short device_enable;
481 u_short reserved; /* pad */
482 };
483
484 /*
485 * The result queue can be quite a bit smaller since continuation entries
486 * do not show up there:
487 */
488 #define RES_QUEUE_LEN ((QLOGICISP_REQ_QUEUE_LEN + 1) / 8 - 1)
489 #define QUEUE_ENTRY_LEN 64
490
491 struct isp1020_hostdata {
492 u_char revision;
493 struct host_param host_param;
494 struct dev_param dev_param[MAX_TARGETS];
495 struct pci_dev *pci_dev;
496
497 /* result and request queues (shared with isp1020): */
498 u_int req_in_ptr; /* index of next request slot */
499 u_int res_out_ptr; /* index of next result slot */
500
501 /* this is here so the queues are nicely aligned */
502 long send_marker; /* do we need to send a marker? */
503
504 char res[RES_QUEUE_LEN+1][QUEUE_ENTRY_LEN];
505 char req[QLOGICISP_REQ_QUEUE_LEN+1][QUEUE_ENTRY_LEN];
506 };
507
508 /* queue length's _must_ be power of two: */
509 #define QUEUE_DEPTH(in, out, ql) ((in - out) & (ql))
510 #define REQ_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, \
511 QLOGICISP_REQ_QUEUE_LEN)
512 #define RES_QUEUE_DEPTH(in, out) QUEUE_DEPTH(in, out, RES_QUEUE_LEN)
513
514 static void isp1020_enable_irqs(struct Scsi_Host *);
515 static void isp1020_disable_irqs(struct Scsi_Host *);
516 static int isp1020_init(struct Scsi_Host *);
517 static int isp1020_reset_hardware(struct Scsi_Host *);
518 static int isp1020_set_defaults(struct Scsi_Host *);
519 static int isp1020_load_parameters(struct Scsi_Host *);
520 static int isp1020_mbox_command(struct Scsi_Host *, u_short []);
521 static int isp1020_return_status(struct Status_Entry *);
522 static void isp1020_intr_handler(int, void *, struct pt_regs *);
523 static void do_isp1020_intr_handler(int, void *, struct pt_regs *);
524
525 #if USE_NVRAM_DEFAULTS
526 static int isp1020_get_defaults(struct Scsi_Host *);
527 static int isp1020_verify_nvram(struct Scsi_Host *);
528 static u_short isp1020_read_nvram_word(struct Scsi_Host *, u_short);
529 #endif
530
531 #if DEBUG_ISP1020
532 static void isp1020_print_scsi_cmd(Scsi_Cmnd *);
533 #endif
534 #if DEBUG_ISP1020_INTR
535 static void isp1020_print_status_entry(struct Status_Entry *);
536 #endif
537
538 static struct proc_dir_entry proc_scsi_isp1020 = {
539 PROC_SCSI_QLOGICISP, 7, "isp1020",
540 S_IFDIR | S_IRUGO | S_IXUGO, 2
541 };
542
543
544 static inline void isp1020_enable_irqs(struct Scsi_Host *host)
545 {
546 outw(ISP_EN_INT|ISP_EN_RISC, host->io_port + PCI_INTF_CTL);
547 }
548
549
550 static inline void isp1020_disable_irqs(struct Scsi_Host *host)
551 {
552 outw(0x0, host->io_port + PCI_INTF_CTL);
553 }
554
555
556 int isp1020_detect(Scsi_Host_Template *tmpt)
557 {
558 int hosts = 0;
559 struct Scsi_Host *host;
560 struct isp1020_hostdata *hostdata;
561 struct pci_dev *pdev = NULL;
562
563 ENTER("isp1020_detect");
564
565 tmpt->proc_dir = &proc_scsi_isp1020;
566
567 if (pci_present() == 0) {
568 printk("qlogicisp : PCI not present\n");
569 return 0;
570 }
571
572 while ((pdev = pci_find_device(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020, pdev)))
573 {
574 host = scsi_register(tmpt, sizeof(struct isp1020_hostdata));
575 hostdata = (struct isp1020_hostdata *) host->hostdata;
576
577 memset(hostdata, 0, sizeof(struct isp1020_hostdata));
578 hostdata->pci_dev = pdev;
579
580 if (isp1020_init(host) || isp1020_reset_hardware(host)
581 #if USE_NVRAM_DEFAULTS
582 || isp1020_get_defaults(host)
583 #else
584 || isp1020_set_defaults(host)
585 #endif /* USE_NVRAM_DEFAULTS */
586 || isp1020_load_parameters(host)) {
587 scsi_unregister(host);
588 continue;
589 }
590
591 host->this_id = hostdata->host_param.initiator_scsi_id;
592
593 if (request_irq(host->irq, do_isp1020_intr_handler, SA_INTERRUPT | SA_SHIRQ,
594 "qlogicisp", host))
595 {
596 printk("qlogicisp : interrupt %d already in use\n",
597 host->irq);
598 scsi_unregister(host);
599 continue;
600 }
601
602 if (check_region(host->io_port, 0xff)) {
603 printk("qlogicisp : i/o region 0x%lx-0x%lx already "
604 "in use\n",
605 host->io_port, host->io_port + 0xff);
606 free_irq(host->irq, host);
607 scsi_unregister(host);
608 continue;
609 }
610
611 request_region(host->io_port, 0xff, "qlogicisp");
612
613 outw(0x0, host->io_port + PCI_SEMAPHORE);
614 outw(HCCR_CLEAR_RISC_INTR, host->io_port + HOST_HCCR);
615 isp1020_enable_irqs(host);
616
617 hosts++;
618 }
619
620 LEAVE("isp1020_detect");
621
622 return hosts;
623 }
624
625
626 int isp1020_release(struct Scsi_Host *host)
627 {
628 struct isp1020_hostdata *hostdata;
629
630 ENTER("isp1020_release");
631
632 hostdata = (struct isp1020_hostdata *) host->hostdata;
633
634 outw(0x0, host->io_port + PCI_INTF_CTL);
635 free_irq(host->irq, host);
636
637 release_region(host->io_port, 0xff);
638
639 LEAVE("isp1020_release");
640
641 return 0;
642 }
643
644
645 const char *isp1020_info(struct Scsi_Host *host)
646 {
647 static char buf[80];
648 struct isp1020_hostdata *hostdata;
649
650 ENTER("isp1020_info");
651
652 hostdata = (struct isp1020_hostdata *) host->hostdata;
653 sprintf(buf,
654 "QLogic ISP1020 SCSI on PCI bus %02x device %02x irq %d base 0x%lx",
655 hostdata->pci_dev->bus->number, hostdata->pci_dev->devfn, host->irq,
656 host->io_port);
657
658 LEAVE("isp1020_info");
659
660 return buf;
661 }
662
663
664 /*
665 * The middle SCSI layer ensures that queuecommand never gets invoked
666 * concurrently with itself or the interrupt handler (though the
667 * interrupt handler may call this routine as part of
668 * request-completion handling).
669 */
670 int isp1020_queuecommand(Scsi_Cmnd *Cmnd, void (*done)(Scsi_Cmnd *))
671 {
672 int i, sg_count, n, num_free;
673 u_int in_ptr, out_ptr;
674 struct dataseg * ds;
675 struct scatterlist *sg;
676 struct Command_Entry *cmd;
677 struct Continuation_Entry *cont;
678 struct Scsi_Host *host;
679 struct isp1020_hostdata *hostdata;
680
681 ENTER("isp1020_queuecommand");
682
683 host = Cmnd->host;
684 hostdata = (struct isp1020_hostdata *) host->hostdata;
685 Cmnd->scsi_done = done;
686
687 DEBUG(isp1020_print_scsi_cmd(Cmnd));
688
689 out_ptr = inw(host->io_port + MBOX4);
690 in_ptr = hostdata->req_in_ptr;
691
692 DEBUG(printk("qlogicisp : request queue depth %d\n",
693 REQ_QUEUE_DEPTH(in_ptr, out_ptr)));
694
695 cmd = (struct Command_Entry *) &hostdata->req[in_ptr][0];
696 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
697 if (in_ptr == out_ptr) {
698 printk("qlogicisp : request queue overflow\n");
699 return 1;
700 }
701
702 if (hostdata->send_marker) {
703 struct Marker_Entry *marker;
704
705 TRACE("queue marker", in_ptr, 0);
706
707 DEBUG(printk("qlogicisp : adding marker entry\n"));
708 marker = (struct Marker_Entry *) cmd;
709 memset(marker, 0, sizeof(struct Marker_Entry));
710
711 marker->hdr.entry_type = ENTRY_MARKER;
712 marker->hdr.entry_cnt = 1;
713 marker->modifier = SYNC_ALL;
714
715 hostdata->send_marker = 0;
716
717 if (((in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN) == out_ptr) {
718 outw(in_ptr, host->io_port + MBOX4);
719 hostdata->req_in_ptr = in_ptr;
720 printk("qlogicisp : request queue overflow\n");
721 return 1;
722 }
723 cmd = (struct Command_Entry *) &hostdata->req[in_ptr][0];
724 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
725 }
726
727 TRACE("queue command", in_ptr, Cmnd);
728
729 memset(cmd, 0, sizeof(struct Command_Entry));
730
731 cmd->hdr.entry_type = ENTRY_COMMAND;
732 cmd->hdr.entry_cnt = 1;
733
734 cmd->handle = cpu_to_le32((u_int) virt_to_bus(Cmnd));
735 cmd->target_lun = Cmnd->lun;
736 cmd->target_id = Cmnd->target;
737 cmd->cdb_length = cpu_to_le16(Cmnd->cmd_len);
738 cmd->control_flags = cpu_to_le16(CFLAG_READ | CFLAG_WRITE);
739 cmd->time_out = cpu_to_le16(30);
740
741 memcpy(cmd->cdb, Cmnd->cmnd, Cmnd->cmd_len);
742
743 if (Cmnd->use_sg) {
744 cmd->segment_cnt = cpu_to_le16(sg_count = Cmnd->use_sg);
745 sg = (struct scatterlist *) Cmnd->request_buffer;
746 ds = cmd->dataseg;
747
748 /* fill in first four sg entries: */
749 n = sg_count;
750 if (n > 4)
751 n = 4;
752 for (i = 0; i < n; i++) {
753 ds[i].d_base = cpu_to_le32((u_int) virt_to_bus(sg->address));
754 ds[i].d_count = cpu_to_le32(sg->length);
755 ++sg;
756 }
757 sg_count -= 4;
758
759 while (sg_count > 0) {
760 ++cmd->hdr.entry_cnt;
761 cont = (struct Continuation_Entry *)
762 &hostdata->req[in_ptr][0];
763 in_ptr = (in_ptr + 1) & QLOGICISP_REQ_QUEUE_LEN;
764 if (in_ptr == out_ptr) {
765 printk("isp1020: unexpected request queue "
766 "overflow\n");
767 return 1;
768 }
769 TRACE("queue continuation", in_ptr, 0);
770 cont->hdr.entry_type = ENTRY_CONTINUATION;
771 cont->hdr.entry_cnt = 0;
772 cont->hdr.sys_def_1 = 0;
773 cont->hdr.flags = 0;
774 cont->reserved = 0;
775 ds = cont->dataseg;
776 n = sg_count;
777 if (n > 7)
778 n = 7;
779 for (i = 0; i < n; ++i) {
780 ds[i].d_base = cpu_to_le32((u_int)virt_to_bus(sg->address));
781 ds[i].d_count = cpu_to_le32(sg->length);
782 ++sg;
783 }
784 sg_count -= n;
785 }
786 } else {
787 cmd->dataseg[0].d_base =
788 cpu_to_le32((u_int) virt_to_bus(Cmnd->request_buffer));
789 cmd->dataseg[0].d_count =
790 cpu_to_le32((u_int) Cmnd->request_bufflen);
791 cmd->segment_cnt = cpu_to_le16(1);
792 }
793
794 outw(in_ptr, host->io_port + MBOX4);
795 hostdata->req_in_ptr = in_ptr;
796
797 num_free = QLOGICISP_REQ_QUEUE_LEN - REQ_QUEUE_DEPTH(in_ptr, out_ptr);
798 host->can_queue = host->host_busy + num_free;
799 host->sg_tablesize = QLOGICISP_MAX_SG(num_free);
800
801 LEAVE("isp1020_queuecommand");
802
803 return 0;
804 }
805
806
807 #define ASYNC_EVENT_INTERRUPT 0x01
808
809 void do_isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
810 {
811 unsigned long flags;
812
813 spin_lock_irqsave(&io_request_lock, flags);
814 isp1020_intr_handler(irq, dev_id, regs);
815 spin_unlock_irqrestore(&io_request_lock, flags);
816 }
817
818 void isp1020_intr_handler(int irq, void *dev_id, struct pt_regs *regs)
819 {
820 Scsi_Cmnd *Cmnd;
821 struct Status_Entry *sts;
822 struct Scsi_Host *host = dev_id;
823 struct isp1020_hostdata *hostdata;
824 u_int in_ptr, out_ptr;
825 u_short status;
826
827 ENTER_INTR("isp1020_intr_handler");
828
829 hostdata = (struct isp1020_hostdata *) host->hostdata;
830
831 DEBUG_INTR(printk("qlogicisp : interrupt on line %d\n", irq));
832
833 if (!(inw(host->io_port + PCI_INTF_STS) & 0x04)) {
834 /* spurious interrupts can happen legally */
835 DEBUG_INTR(printk("qlogicisp: got spurious interrupt\n"));
836 return;
837 }
838 in_ptr = inw(host->io_port + MBOX5);
839 outw(HCCR_CLEAR_RISC_INTR, host->io_port + HOST_HCCR);
840
841 if ((inw(host->io_port + PCI_SEMAPHORE) & ASYNC_EVENT_INTERRUPT)) {
842 status = inw(host->io_port + MBOX0);
843
844 DEBUG_INTR(printk("qlogicisp : mbox completion status: %x\n",
845 status));
846
847 switch (status) {
848 case ASYNC_SCSI_BUS_RESET:
849 case EXECUTION_TIMEOUT_RESET:
850 hostdata->send_marker = 1;
851 break;
852 case INVALID_COMMAND:
853 case HOST_INTERFACE_ERROR:
854 case COMMAND_ERROR:
855 case COMMAND_PARAM_ERROR:
856 printk("qlogicisp : bad mailbox return status\n");
857 break;
858 }
859 outw(0x0, host->io_port + PCI_SEMAPHORE);
860 }
861 out_ptr = hostdata->res_out_ptr;
862
863 DEBUG_INTR(printk("qlogicisp : response queue update\n"));
864 DEBUG_INTR(printk("qlogicisp : response queue depth %d\n",
865 QUEUE_DEPTH(in_ptr, out_ptr, RES_QUEUE_LEN)));
866
867 while (out_ptr != in_ptr) {
868 sts = (struct Status_Entry *) &hostdata->res[out_ptr][0];
869 out_ptr = (out_ptr + 1) & RES_QUEUE_LEN;
870
871 Cmnd = (Scsi_Cmnd *) bus_to_virt(le32_to_cpu(sts->handle));
872
873 TRACE("done", out_ptr, Cmnd);
874
875 if (le16_to_cpu(sts->completion_status) == CS_RESET_OCCURRED
876 || le16_to_cpu(sts->completion_status) == CS_ABORTED
877 || (le16_to_cpu(sts->status_flags) & STF_BUS_RESET))
878 hostdata->send_marker = 1;
879
880 if (le16_to_cpu(sts->state_flags) & SF_GOT_SENSE)
881 memcpy(Cmnd->sense_buffer, sts->req_sense_data,
882 sizeof(Cmnd->sense_buffer));
883
884 DEBUG_INTR(isp1020_print_status_entry(sts));
885
886 if (sts->hdr.entry_type == ENTRY_STATUS)
887 Cmnd->result = isp1020_return_status(sts);
888 else
889 Cmnd->result = DID_ERROR << 16;
890
891 outw(out_ptr, host->io_port + MBOX5);
892 (*Cmnd->scsi_done)(Cmnd);
893 }
894 hostdata->res_out_ptr = out_ptr;
895
896 LEAVE_INTR("isp1020_intr_handler");
897 }
898
899
900 static int isp1020_return_status(struct Status_Entry *sts)
901 {
902 int host_status = DID_ERROR;
903 #if DEBUG_ISP1020_INTR
904 static char *reason[] = {
905 "DID_OK",
906 "DID_NO_CONNECT",
907 "DID_BUS_BUSY",
908 "DID_TIME_OUT",
909 "DID_BAD_TARGET",
910 "DID_ABORT",
911 "DID_PARITY",
912 "DID_ERROR",
913 "DID_RESET",
914 "DID_BAD_INTR"
915 };
916 #endif /* DEBUG_ISP1020_INTR */
917
918 ENTER("isp1020_return_status");
919
920 DEBUG(printk("qlogicisp : completion status = 0x%04x\n",
921 le16_to_cpu(sts->completion_status)));
922
923 switch(le16_to_cpu(sts->completion_status)) {
924 case CS_COMPLETE:
925 host_status = DID_OK;
926 break;
927 case CS_INCOMPLETE:
928 if (!(le16_to_cpu(sts->state_flags) & SF_GOT_BUS))
929 host_status = DID_NO_CONNECT;
930 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_TARGET))
931 host_status = DID_BAD_TARGET;
932 else if (!(le16_to_cpu(sts->state_flags) & SF_SENT_CDB))
933 host_status = DID_ERROR;
934 else if (!(le16_to_cpu(sts->state_flags) & SF_TRANSFERRED_DATA))
935 host_status = DID_ERROR;
936 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_STATUS))
937 host_status = DID_ERROR;
938 else if (!(le16_to_cpu(sts->state_flags) & SF_GOT_SENSE))
939 host_status = DID_ERROR;
940 break;
941 case CS_DMA_ERROR:
942 case CS_TRANSPORT_ERROR:
943 host_status = DID_ERROR;
944 break;
945 case CS_RESET_OCCURRED:
946 host_status = DID_RESET;
947 break;
948 case CS_ABORTED:
949 host_status = DID_ABORT;
950 break;
951 case CS_TIMEOUT:
952 host_status = DID_TIME_OUT;
953 break;
954 case CS_DATA_OVERRUN:
955 case CS_COMMAND_OVERRUN:
956 case CS_STATUS_OVERRUN:
957 case CS_BAD_MESSAGE:
958 case CS_NO_MESSAGE_OUT:
959 case CS_EXT_ID_FAILED:
960 case CS_IDE_MSG_FAILED:
961 case CS_ABORT_MSG_FAILED:
962 case CS_NOP_MSG_FAILED:
963 case CS_PARITY_ERROR_MSG_FAILED:
964 case CS_DEVICE_RESET_MSG_FAILED:
965 case CS_ID_MSG_FAILED:
966 case CS_UNEXP_BUS_FREE:
967 host_status = DID_ERROR;
968 break;
969 case CS_DATA_UNDERRUN:
970 host_status = DID_OK;
971 break;
972 default:
973 printk("qlogicisp : unknown completion status 0x%04x\n",
974 le16_to_cpu(sts->completion_status));
975 host_status = DID_ERROR;
976 break;
977 }
978
979 DEBUG_INTR(printk("qlogicisp : host status (%s) scsi status %x\n",
980 reason[host_status], le16_to_cpu(sts->scsi_status)));
981
982 LEAVE("isp1020_return_status");
983
984 return (le16_to_cpu(sts->scsi_status) & STATUS_MASK) | (host_status << 16);
985 }
986
987
988 int isp1020_abort(Scsi_Cmnd *Cmnd)
989 {
990 u_short param[6];
991 struct Scsi_Host *host;
992 struct isp1020_hostdata *hostdata;
993 int return_status = SCSI_ABORT_SUCCESS;
994 u_int cmdaddr = virt_to_bus(Cmnd);
995
996 ENTER("isp1020_abort");
997
998 host = Cmnd->host;
999 hostdata = (struct isp1020_hostdata *) host->hostdata;
1000
1001 isp1020_disable_irqs(host);
1002
1003 param[0] = MBOX_ABORT;
1004 param[1] = (((u_short) Cmnd->target) << 8) | Cmnd->lun;
1005 param[2] = cmdaddr >> 16;
1006 param[3] = cmdaddr & 0xffff;
1007
1008 isp1020_mbox_command(host, param);
1009
1010 if (param[0] != MBOX_COMMAND_COMPLETE) {
1011 printk("qlogicisp : scsi abort failure: %x\n", param[0]);
1012 return_status = SCSI_ABORT_ERROR;
1013 }
1014
1015 isp1020_enable_irqs(host);
1016
1017 LEAVE("isp1020_abort");
1018
1019 return return_status;
1020 }
1021
1022
1023 int isp1020_reset(Scsi_Cmnd *Cmnd, unsigned int reset_flags)
1024 {
1025 u_short param[6];
1026 struct Scsi_Host *host;
1027 struct isp1020_hostdata *hostdata;
1028 int return_status = SCSI_RESET_SUCCESS;
1029
1030 ENTER("isp1020_reset");
1031
1032 host = Cmnd->host;
1033 hostdata = (struct isp1020_hostdata *) host->hostdata;
1034
1035 param[0] = MBOX_BUS_RESET;
1036 param[1] = hostdata->host_param.bus_reset_delay;
1037
1038 isp1020_disable_irqs(host);
1039
1040 isp1020_mbox_command(host, param);
1041
1042 if (param[0] != MBOX_COMMAND_COMPLETE) {
1043 printk("qlogicisp : scsi bus reset failure: %x\n", param[0]);
1044 return_status = SCSI_RESET_ERROR;
1045 }
1046
1047 isp1020_enable_irqs(host);
1048
1049 LEAVE("isp1020_reset");
1050
1051 return return_status;;
1052 }
1053
1054
1055 int isp1020_biosparam(Disk *disk, kdev_t n, int ip[])
1056 {
1057 int size = disk->capacity;
1058
1059 ENTER("isp1020_biosparam");
1060
1061 ip[0] = 64;
1062 ip[1] = 32;
1063 ip[2] = size >> 11;
1064 if (ip[2] > 1024) {
1065 ip[0] = 255;
1066 ip[1] = 63;
1067 ip[2] = size / (ip[0] * ip[1]);
1068 #if 0
1069 if (ip[2] > 1023)
1070 ip[2] = 1023;
1071 #endif
1072 }
1073
1074 LEAVE("isp1020_biosparam");
1075
1076 return 0;
1077 }
1078
1079
1080 static int isp1020_reset_hardware(struct Scsi_Host *host)
1081 {
1082 u_short param[6];
1083 int loop_count;
1084
1085 ENTER("isp1020_reset_hardware");
1086
1087 outw(ISP_RESET, host->io_port + PCI_INTF_CTL);
1088 udelay(100);
1089 outw(HCCR_RESET, host->io_port + HOST_HCCR);
1090 udelay(100);
1091 outw(HCCR_RELEASE, host->io_port + HOST_HCCR);
1092 outw(HCCR_BIOS_DISABLE, host->io_port + HOST_HCCR);
1093
1094 loop_count = DEFAULT_LOOP_COUNT;
1095 while (--loop_count && inw(host->io_port + HOST_HCCR) == RISC_BUSY)
1096 barrier();
1097 if (!loop_count)
1098 printk("qlogicisp: reset_hardware loop timeout\n");
1099
1100 outw(0, host->io_port + ISP_CFG1);
1101
1102 #if DEBUG_ISP1020
1103 printk("qlogicisp : mbox 0 0x%04x \n", inw(host->io_port + MBOX0));
1104 printk("qlogicisp : mbox 1 0x%04x \n", inw(host->io_port + MBOX1));
1105 printk("qlogicisp : mbox 2 0x%04x \n", inw(host->io_port + MBOX2));
1106 printk("qlogicisp : mbox 3 0x%04x \n", inw(host->io_port + MBOX3));
1107 printk("qlogicisp : mbox 4 0x%04x \n", inw(host->io_port + MBOX4));
1108 printk("qlogicisp : mbox 5 0x%04x \n", inw(host->io_port + MBOX5));
1109 #endif /* DEBUG_ISP1020 */
1110
1111 param[0] = MBOX_NO_OP;
1112 isp1020_mbox_command(host, param);
1113 if (param[0] != MBOX_COMMAND_COMPLETE) {
1114 printk("qlogicisp : NOP test failed\n");
1115 return 1;
1116 }
1117
1118 DEBUG(printk("qlogicisp : loading risc ram\n"));
1119
1120 #if RELOAD_FIRMWARE
1121 for (loop_count = 0; loop_count < risc_code_length01; loop_count++) {
1122 param[0] = MBOX_WRITE_RAM_WORD;
1123 param[1] = risc_code_addr01 + loop_count;
1124 param[2] = risc_code01[loop_count];
1125 isp1020_mbox_command(host, param);
1126 if (param[0] != MBOX_COMMAND_COMPLETE) {
1127 printk("qlogicisp : firmware load failure at %d\n",
1128 loop_count);
1129 return 1;
1130 }
1131 }
1132 #endif /* RELOAD_FIRMWARE */
1133
1134 DEBUG(printk("qlogicisp : verifying checksum\n"));
1135
1136 param[0] = MBOX_VERIFY_CHECKSUM;
1137 param[1] = risc_code_addr01;
1138
1139 isp1020_mbox_command(host, param);
1140
1141 if (param[0] != MBOX_COMMAND_COMPLETE) {
1142 printk("qlogicisp : ram checksum failure\n");
1143 return 1;
1144 }
1145
1146 DEBUG(printk("qlogicisp : executing firmware\n"));
1147
1148 param[0] = MBOX_EXEC_FIRMWARE;
1149 param[1] = risc_code_addr01;
1150
1151 isp1020_mbox_command(host, param);
1152
1153 param[0] = MBOX_ABOUT_FIRMWARE;
1154
1155 isp1020_mbox_command(host, param);
1156
1157 if (param[0] != MBOX_COMMAND_COMPLETE) {
1158 printk("qlogicisp : about firmware failure\n");
1159 return 1;
1160 }
1161
1162 DEBUG(printk("qlogicisp : firmware major revision %d\n", param[1]));
1163 DEBUG(printk("qlogicisp : firmware minor revision %d\n", param[2]));
1164
1165 LEAVE("isp1020_reset_hardware");
1166
1167 return 0;
1168 }
1169
1170
1171 static int isp1020_init(struct Scsi_Host *sh)
1172 {
1173 u_long io_base, io_flags;
1174 struct isp1020_hostdata *hostdata;
1175 u_char revision;
1176 u_int irq;
1177 u_short command;
1178 struct pci_dev *pdev;
1179
1180 ENTER("isp1020_init");
1181
1182 hostdata = (struct isp1020_hostdata *) sh->hostdata;
1183 pdev = hostdata->pci_dev;
1184
1185 if (pci_read_config_word(pdev, PCI_COMMAND, &command)
1186 || pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision))
1187 {
1188 printk("qlogicisp : error reading PCI configuration\n");
1189 return 1;
1190 }
1191
1192 io_base = pdev->resource[0].start;
1193 io_flags = pdev->resource[0].flags;
1194 irq = pdev->irq;
1195
1196 if (pdev->vendor != PCI_VENDOR_ID_QLOGIC) {
1197 printk("qlogicisp : 0x%04x is not QLogic vendor ID\n",
1198 pdev->vendor);
1199 return 1;
1200 }
1201
1202 if (pdev->device != PCI_DEVICE_ID_QLOGIC_ISP1020) {
1203 printk("qlogicisp : 0x%04x does not match ISP1020 device id\n",
1204 pdev->device);
1205 return 1;
1206 }
1207
1208 #ifdef __sparc__
1209 command |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY|
1210 PCI_COMMAND_INVALIDATE|PCI_COMMAND_SERR);
1211 pci_write_config_word(pdev, PCI_COMMAND, command);
1212 pci_read_config_word(pdev, PCI_COMMAND, &command);
1213 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 16);
1214 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 64);
1215 #endif
1216
1217 if (! ((command & PCI_COMMAND_IO)
1218 && ((io_flags & PCI_BASE_ADDRESS_SPACE)
1219 == PCI_BASE_ADDRESS_SPACE_IO))) {
1220 printk("qlogicisp : i/o mapping is disabled\n");
1221 return 1;
1222 }
1223
1224 if (!(command & PCI_COMMAND_MASTER)) {
1225 printk("qlogicisp : bus mastering is disabled\n");
1226 return 1;
1227 }
1228
1229 if (revision != ISP1020_REV_ID)
1230 printk("qlogicisp : new isp1020 revision ID (%d)\n", revision);
1231
1232 if (inw(io_base + PCI_ID_LOW) != PCI_VENDOR_ID_QLOGIC
1233 || inw(io_base + PCI_ID_HIGH) != PCI_DEVICE_ID_QLOGIC_ISP1020)
1234 {
1235 printk("qlogicisp : can't decode i/o address space 0x%lx\n",
1236 io_base);
1237 return 1;
1238 }
1239
1240 hostdata->revision = revision;
1241
1242 sh->irq = irq;
1243 sh->io_port = io_base;
1244 sh->max_id = MAX_TARGETS;
1245 sh->max_lun = MAX_LUNS;
1246
1247 LEAVE("isp1020_init");
1248
1249 return 0;
1250 }
1251
1252
1253 #if USE_NVRAM_DEFAULTS
1254
1255 static int isp1020_get_defaults(struct Scsi_Host *host)
1256 {
1257 int i;
1258 u_short value;
1259 struct isp1020_hostdata *hostdata =
1260 (struct isp1020_hostdata *) host->hostdata;
1261
1262 ENTER("isp1020_get_defaults");
1263
1264 if (!isp1020_verify_nvram(host)) {
1265 printk("qlogicisp : nvram checksum failure\n");
1266 printk("qlogicisp : attempting to use default parameters\n");
1267 return isp1020_set_defaults(host);
1268 }
1269
1270 value = isp1020_read_nvram_word(host, 2);
1271 hostdata->host_param.fifo_threshold = (value >> 8) & 0x03;
1272 hostdata->host_param.host_adapter_enable = (value >> 11) & 0x01;
1273 hostdata->host_param.initiator_scsi_id = (value >> 12) & 0x0f;
1274
1275 value = isp1020_read_nvram_word(host, 3);
1276 hostdata->host_param.bus_reset_delay = value & 0xff;
1277 hostdata->host_param.retry_count = value >> 8;
1278
1279 value = isp1020_read_nvram_word(host, 4);
1280 hostdata->host_param.retry_delay = value & 0xff;
1281 hostdata->host_param.async_data_setup_time = (value >> 8) & 0x0f;
1282 hostdata->host_param.req_ack_active_negation = (value >> 12) & 0x01;
1283 hostdata->host_param.data_line_active_negation = (value >> 13) & 0x01;
1284 hostdata->host_param.data_dma_burst_enable = (value >> 14) & 0x01;
1285 hostdata->host_param.command_dma_burst_enable = (value >> 15);
1286
1287 value = isp1020_read_nvram_word(host, 5);
1288 hostdata->host_param.tag_aging = value & 0xff;
1289
1290 value = isp1020_read_nvram_word(host, 6);
1291 hostdata->host_param.selection_timeout = value & 0xffff;
1292
1293 value = isp1020_read_nvram_word(host, 7);
1294 hostdata->host_param.max_queue_depth = value & 0xffff;
1295
1296 #if DEBUG_ISP1020_SETUP
1297 printk("qlogicisp : fifo threshold=%d\n",
1298 hostdata->host_param.fifo_threshold);
1299 printk("qlogicisp : initiator scsi id=%d\n",
1300 hostdata->host_param.initiator_scsi_id);
1301 printk("qlogicisp : bus reset delay=%d\n",
1302 hostdata->host_param.bus_reset_delay);
1303 printk("qlogicisp : retry count=%d\n",
1304 hostdata->host_param.retry_count);
1305 printk("qlogicisp : retry delay=%d\n",
1306 hostdata->host_param.retry_delay);
1307 printk("qlogicisp : async data setup time=%d\n",
1308 hostdata->host_param.async_data_setup_time);
1309 printk("qlogicisp : req/ack active negation=%d\n",
1310 hostdata->host_param.req_ack_active_negation);
1311 printk("qlogicisp : data line active negation=%d\n",
1312 hostdata->host_param.data_line_active_negation);
1313 printk("qlogicisp : data DMA burst enable=%d\n",
1314 hostdata->host_param.data_dma_burst_enable);
1315 printk("qlogicisp : command DMA burst enable=%d\n",
1316 hostdata->host_param.command_dma_burst_enable);
1317 printk("qlogicisp : tag age limit=%d\n",
1318 hostdata->host_param.tag_aging);
1319 printk("qlogicisp : selection timeout limit=%d\n",
1320 hostdata->host_param.selection_timeout);
1321 printk("qlogicisp : max queue depth=%d\n",
1322 hostdata->host_param.max_queue_depth);
1323 #endif /* DEBUG_ISP1020_SETUP */
1324
1325 for (i = 0; i < MAX_TARGETS; i++) {
1326
1327 value = isp1020_read_nvram_word(host, 14 + i * 3);
1328 hostdata->dev_param[i].device_flags = value & 0xff;
1329 hostdata->dev_param[i].execution_throttle = value >> 8;
1330
1331 value = isp1020_read_nvram_word(host, 15 + i * 3);
1332 hostdata->dev_param[i].synchronous_period = value & 0xff;
1333 hostdata->dev_param[i].synchronous_offset = (value >> 8) & 0x0f;
1334 hostdata->dev_param[i].device_enable = (value >> 12) & 0x01;
1335
1336 #if DEBUG_ISP1020_SETUP
1337 printk("qlogicisp : target 0x%02x\n", i);
1338 printk("qlogicisp : device flags=0x%02x\n",
1339 hostdata->dev_param[i].device_flags);
1340 printk("qlogicisp : execution throttle=%d\n",
1341 hostdata->dev_param[i].execution_throttle);
1342 printk("qlogicisp : synchronous period=%d\n",
1343 hostdata->dev_param[i].synchronous_period);
1344 printk("qlogicisp : synchronous offset=%d\n",
1345 hostdata->dev_param[i].synchronous_offset);
1346 printk("qlogicisp : device enable=%d\n",
1347 hostdata->dev_param[i].device_enable);
1348 #endif /* DEBUG_ISP1020_SETUP */
1349 }
1350
1351 LEAVE("isp1020_get_defaults");
1352
1353 return 0;
1354 }
1355
1356
1357 #define ISP1020_NVRAM_LEN 0x40
1358 #define ISP1020_NVRAM_SIG1 0x5349
1359 #define ISP1020_NVRAM_SIG2 0x2050
1360
1361 static int isp1020_verify_nvram(struct Scsi_Host *host)
1362 {
1363 int i;
1364 u_short value;
1365 u_char checksum = 0;
1366
1367 for (i = 0; i < ISP1020_NVRAM_LEN; i++) {
1368 value = isp1020_read_nvram_word(host, i);
1369
1370 switch (i) {
1371 case 0:
1372 if (value != ISP1020_NVRAM_SIG1) return 0;
1373 break;
1374 case 1:
1375 if (value != ISP1020_NVRAM_SIG2) return 0;
1376 break;
1377 case 2:
1378 if ((value & 0xff) != 0x02) return 0;
1379 break;
1380 }
1381 checksum += value & 0xff;
1382 checksum += value >> 8;
1383 }
1384
1385 return (checksum == 0);
1386 }
1387
1388 #define NVRAM_DELAY() udelay(2) /* 2 microsecond delay */
1389
1390
1391 u_short isp1020_read_nvram_word(struct Scsi_Host *host, u_short byte)
1392 {
1393 int i;
1394 u_short value, output, input;
1395
1396 byte &= 0x3f; byte |= 0x0180;
1397
1398 for (i = 8; i >= 0; i--) {
1399 output = ((byte >> i) & 0x1) ? 0x4 : 0x0;
1400 outw(output | 0x2, host->io_port + PCI_NVRAM); NVRAM_DELAY();
1401 outw(output | 0x3, host->io_port + PCI_NVRAM); NVRAM_DELAY();
1402 outw(output | 0x2, host->io_port + PCI_NVRAM); NVRAM_DELAY();
1403 }
1404
1405 for (i = 0xf, value = 0; i >= 0; i--) {
1406 value <<= 1;
1407 outw(0x3, host->io_port + PCI_NVRAM); NVRAM_DELAY();
1408 input = inw(host->io_port + PCI_NVRAM); NVRAM_DELAY();
1409 outw(0x2, host->io_port + PCI_NVRAM); NVRAM_DELAY();
1410 if (input & 0x8) value |= 1;
1411 }
1412
1413 outw(0x0, host->io_port + PCI_NVRAM); NVRAM_DELAY();
1414
1415 return value;
1416 }
1417
1418 #endif /* USE_NVRAM_DEFAULTS */
1419
1420
1421 static int isp1020_set_defaults(struct Scsi_Host *host)
1422 {
1423 struct isp1020_hostdata *hostdata =
1424 (struct isp1020_hostdata *) host->hostdata;
1425 int i;
1426
1427 ENTER("isp1020_set_defaults");
1428
1429 hostdata->host_param.fifo_threshold = 2;
1430 hostdata->host_param.host_adapter_enable = 1;
1431 hostdata->host_param.initiator_scsi_id = 7;
1432 hostdata->host_param.bus_reset_delay = 3;
1433 hostdata->host_param.retry_count = 0;
1434 hostdata->host_param.retry_delay = 1;
1435 hostdata->host_param.async_data_setup_time = 6;
1436 hostdata->host_param.req_ack_active_negation = 1;
1437 hostdata->host_param.data_line_active_negation = 1;
1438 hostdata->host_param.data_dma_burst_enable = 1;
1439 hostdata->host_param.command_dma_burst_enable = 1;
1440 hostdata->host_param.tag_aging = 8;
1441 hostdata->host_param.selection_timeout = 250;
1442 hostdata->host_param.max_queue_depth = 256;
1443
1444 for (i = 0; i < MAX_TARGETS; i++) {
1445 hostdata->dev_param[i].device_flags = 0xfd;
1446 hostdata->dev_param[i].execution_throttle = 16;
1447 hostdata->dev_param[i].synchronous_period = 25;
1448 hostdata->dev_param[i].synchronous_offset = 12;
1449 hostdata->dev_param[i].device_enable = 1;
1450 }
1451
1452 LEAVE("isp1020_set_defaults");
1453
1454 return 0;
1455 }
1456
1457
1458 static int isp1020_load_parameters(struct Scsi_Host *host)
1459 {
1460 int i, k;
1461 u_int queue_addr;
1462 u_short param[6];
1463 u_short isp_cfg1;
1464 unsigned long flags;
1465 struct isp1020_hostdata *hostdata =
1466 (struct isp1020_hostdata *) host->hostdata;
1467
1468 ENTER("isp1020_load_parameters");
1469
1470 save_flags(flags);
1471 cli();
1472
1473 outw(hostdata->host_param.fifo_threshold, host->io_port + ISP_CFG1);
1474
1475 param[0] = MBOX_SET_INIT_SCSI_ID;
1476 param[1] = hostdata->host_param.initiator_scsi_id;
1477
1478 isp1020_mbox_command(host, param);
1479
1480 if (param[0] != MBOX_COMMAND_COMPLETE) {
1481 restore_flags(flags);
1482 printk("qlogicisp : set initiator id failure\n");
1483 return 1;
1484 }
1485
1486 param[0] = MBOX_SET_RETRY_COUNT;
1487 param[1] = hostdata->host_param.retry_count;
1488 param[2] = hostdata->host_param.retry_delay;
1489
1490 isp1020_mbox_command(host, param);
1491
1492 if (param[0] != MBOX_COMMAND_COMPLETE) {
1493 restore_flags(flags);
1494 printk("qlogicisp : set retry count failure\n");
1495 return 1;
1496 }
1497
1498 param[0] = MBOX_SET_ASYNC_DATA_SETUP_TIME;
1499 param[1] = hostdata->host_param.async_data_setup_time;
1500
1501 isp1020_mbox_command(host, param);
1502
1503 if (param[0] != MBOX_COMMAND_COMPLETE) {
1504 restore_flags(flags);
1505 printk("qlogicisp : async data setup time failure\n");
1506 return 1;
1507 }
1508
1509 param[0] = MBOX_SET_ACTIVE_NEG_STATE;
1510 param[1] = (hostdata->host_param.req_ack_active_negation << 4)
1511 | (hostdata->host_param.data_line_active_negation << 5);
1512
1513 isp1020_mbox_command(host, param);
1514
1515 if (param[0] != MBOX_COMMAND_COMPLETE) {
1516 restore_flags(flags);
1517 printk("qlogicisp : set active negation state failure\n");
1518 return 1;
1519 }
1520
1521 param[0] = MBOX_SET_PCI_CONTROL_PARAMS;
1522 param[1] = hostdata->host_param.data_dma_burst_enable << 1;
1523 param[2] = hostdata->host_param.command_dma_burst_enable << 1;
1524
1525 isp1020_mbox_command(host, param);
1526
1527 if (param[0] != MBOX_COMMAND_COMPLETE) {
1528 restore_flags(flags);
1529 printk("qlogicisp : set pci control parameter failure\n");
1530 return 1;
1531 }
1532
1533 isp_cfg1 = inw(host->io_port + ISP_CFG1);
1534
1535 if (hostdata->host_param.data_dma_burst_enable
1536 || hostdata->host_param.command_dma_burst_enable)
1537 isp_cfg1 |= 0x0004;
1538 else
1539 isp_cfg1 &= 0xfffb;
1540
1541 outw(isp_cfg1, host->io_port + ISP_CFG1);
1542
1543 param[0] = MBOX_SET_TAG_AGE_LIMIT;
1544 param[1] = hostdata->host_param.tag_aging;
1545
1546 isp1020_mbox_command(host, param);
1547
1548 if (param[0] != MBOX_COMMAND_COMPLETE) {
1549 restore_flags(flags);
1550 printk("qlogicisp : set tag age limit failure\n");
1551 return 1;
1552 }
1553
1554 param[0] = MBOX_SET_SELECT_TIMEOUT;
1555 param[1] = hostdata->host_param.selection_timeout;
1556
1557 isp1020_mbox_command(host, param);
1558
1559 if (param[0] != MBOX_COMMAND_COMPLETE) {
1560 restore_flags(flags);
1561 printk("qlogicisp : set selection timeout failure\n");
1562 return 1;
1563 }
1564
1565 for (i = 0; i < MAX_TARGETS; i++) {
1566
1567 if (!hostdata->dev_param[i].device_enable)
1568 continue;
1569
1570 param[0] = MBOX_SET_TARGET_PARAMS;
1571 param[1] = i << 8;
1572 param[2] = hostdata->dev_param[i].device_flags << 8;
1573 param[3] = (hostdata->dev_param[i].synchronous_offset << 8)
1574 | hostdata->dev_param[i].synchronous_period;
1575
1576 isp1020_mbox_command(host, param);
1577
1578 if (param[0] != MBOX_COMMAND_COMPLETE) {
1579 restore_flags(flags);
1580 printk("qlogicisp : set target parameter failure\n");
1581 return 1;
1582 }
1583
1584 for (k = 0; k < MAX_LUNS; k++) {
1585
1586 param[0] = MBOX_SET_DEV_QUEUE_PARAMS;
1587 param[1] = (i << 8) | k;
1588 param[2] = hostdata->host_param.max_queue_depth;
1589 param[3] = hostdata->dev_param[i].execution_throttle;
1590
1591 isp1020_mbox_command(host, param);
1592
1593 if (param[0] != MBOX_COMMAND_COMPLETE) {
1594 restore_flags(flags);
1595 printk("qlogicisp : set device queue "
1596 "parameter failure\n");
1597 return 1;
1598 }
1599 }
1600 }
1601
1602 queue_addr = (u_int) virt_to_bus(&hostdata->res[0][0]);
1603
1604 param[0] = MBOX_INIT_RES_QUEUE;
1605 param[1] = RES_QUEUE_LEN + 1;
1606 param[2] = (u_short) (queue_addr >> 16);
1607 param[3] = (u_short) (queue_addr & 0xffff);
1608 param[4] = 0;
1609 param[5] = 0;
1610
1611 isp1020_mbox_command(host, param);
1612
1613 if (param[0] != MBOX_COMMAND_COMPLETE) {
1614 restore_flags(flags);
1615 printk("qlogicisp : set response queue failure\n");
1616 return 1;
1617 }
1618
1619 queue_addr = (u_int) virt_to_bus(&hostdata->req[0][0]);
1620
1621 param[0] = MBOX_INIT_REQ_QUEUE;
1622 param[1] = QLOGICISP_REQ_QUEUE_LEN + 1;
1623 param[2] = (u_short) (queue_addr >> 16);
1624 param[3] = (u_short) (queue_addr & 0xffff);
1625 param[4] = 0;
1626
1627 isp1020_mbox_command(host, param);
1628
1629 if (param[0] != MBOX_COMMAND_COMPLETE) {
1630 restore_flags(flags);
1631 printk("qlogicisp : set request queue failure\n");
1632 return 1;
1633 }
1634
1635 restore_flags(flags);
1636
1637 LEAVE("isp1020_load_parameters");
1638
1639 return 0;
1640 }
1641
1642
1643 /*
1644 * currently, this is only called during initialization or abort/reset,
1645 * at which times interrupts are disabled, so polling is OK, I guess...
1646 */
1647 static int isp1020_mbox_command(struct Scsi_Host *host, u_short param[])
1648 {
1649 int loop_count;
1650
1651 if (mbox_param[param[0]] == 0)
1652 return 1;
1653
1654 loop_count = DEFAULT_LOOP_COUNT;
1655 while (--loop_count && inw(host->io_port + HOST_HCCR) & 0x0080)
1656 barrier();
1657 if (!loop_count)
1658 printk("qlogicisp: mbox_command loop timeout #1\n");
1659
1660 switch(mbox_param[param[0]] >> 4) {
1661 case 6: outw(param[5], host->io_port + MBOX5);
1662 case 5: outw(param[4], host->io_port + MBOX4);
1663 case 4: outw(param[3], host->io_port + MBOX3);
1664 case 3: outw(param[2], host->io_port + MBOX2);
1665 case 2: outw(param[1], host->io_port + MBOX1);
1666 case 1: outw(param[0], host->io_port + MBOX0);
1667 }
1668
1669 outw(0x0, host->io_port + PCI_SEMAPHORE);
1670 outw(HCCR_CLEAR_RISC_INTR, host->io_port + HOST_HCCR);
1671 outw(HCCR_SET_HOST_INTR, host->io_port + HOST_HCCR);
1672
1673 loop_count = DEFAULT_LOOP_COUNT;
1674 while (--loop_count && !(inw(host->io_port + PCI_INTF_STS) & 0x04))
1675 barrier();
1676 if (!loop_count)
1677 printk("qlogicisp: mbox_command loop timeout #2\n");
1678
1679 loop_count = DEFAULT_LOOP_COUNT;
1680 while (--loop_count && inw(host->io_port + MBOX0) == 0x04)
1681 barrier();
1682 if (!loop_count)
1683 printk("qlogicisp: mbox_command loop timeout #3\n");
1684
1685 switch(mbox_param[param[0]] & 0xf) {
1686 case 6: param[5] = inw(host->io_port + MBOX5);
1687 case 5: param[4] = inw(host->io_port + MBOX4);
1688 case 4: param[3] = inw(host->io_port + MBOX3);
1689 case 3: param[2] = inw(host->io_port + MBOX2);
1690 case 2: param[1] = inw(host->io_port + MBOX1);
1691 case 1: param[0] = inw(host->io_port + MBOX0);
1692 }
1693
1694 outw(0x0, host->io_port + PCI_SEMAPHORE);
1695 outw(HCCR_CLEAR_RISC_INTR, host->io_port + HOST_HCCR);
1696
1697 return 0;
1698 }
1699
1700
1701 #if DEBUG_ISP1020_INTR
1702
1703 void isp1020_print_status_entry(struct Status_Entry *status)
1704 {
1705 int i;
1706
1707 printk("qlogicisp : entry count = 0x%02x, type = 0x%02x, flags = 0x%02x\n",
1708 status->hdr.entry_cnt, status->hdr.entry_type, status->hdr.flags);
1709 printk("qlogicisp : scsi status = 0x%04x, completion status = 0x%04x\n",
1710 le16_to_cpu(status->scsi_status), le16_to_cpu(status->completion_status));
1711 printk("qlogicisp : state flags = 0x%04x, status flags = 0x%04x\n",
1712 le16_to_cpu(status->state_flags), le16_to_cpu(status->status_flags));
1713 printk("qlogicisp : time = 0x%04x, request sense length = 0x%04x\n",
1714 le16_to_cpu(status->time), le16_to_cpu(status->req_sense_len));
1715 printk("qlogicisp : residual transfer length = 0x%08x\n",
1716 le32_to_cpu(status->residual));
1717
1718 for (i = 0; i < le16_to_cpu(status->req_sense_len); i++)
1719 printk("qlogicisp : sense data = 0x%02x\n", status->req_sense_data[i]);
1720 }
1721
1722 #endif /* DEBUG_ISP1020_INTR */
1723
1724
1725 #if DEBUG_ISP1020
1726
1727 void isp1020_print_scsi_cmd(Scsi_Cmnd *cmd)
1728 {
1729 int i;
1730
1731 printk("qlogicisp : target = 0x%02x, lun = 0x%02x, cmd_len = 0x%02x\n",
1732 cmd->target, cmd->lun, cmd->cmd_len);
1733 printk("qlogicisp : command = ");
1734 for (i = 0; i < cmd->cmd_len; i++)
1735 printk("0x%02x ", cmd->cmnd[i]);
1736 printk("\n");
1737 }
1738
1739 #endif /* DEBUG_ISP1020 */
1740
1741
1742 #ifdef MODULE
1743 Scsi_Host_Template driver_template = QLOGICISP;
1744
1745 #include "scsi_module.c"
1746 #endif /* MODULE */
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