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Import 2.3.18pre1
[davej-history.git] / drivers / scsi / mesh.c
blob8cadff737909fb4169932aec10cfcf470fdeffd4
1 /*
2 * SCSI low-level driver for the MESH (Macintosh Enhanced SCSI Hardware)
3 * bus adaptor found on Power Macintosh computers.
4 * We assume the MESH is connected to a DBDMA (descriptor-based DMA)
5 * controller.
6 *
7 * Paul Mackerras, August 1996.
8 * Copyright (C) 1996 Paul Mackerras.
9 */
10 #include <linux/config.h>
11 #include <linux/kernel.h>
12 #include <linux/delay.h>
13 #include <linux/types.h>
14 #include <linux/string.h>
15 #include <linux/malloc.h>
16 #include <linux/blk.h>
17 #include <linux/proc_fs.h>
18 #include <linux/stat.h>
19 #include <linux/tqueue.h>
20 #include <linux/interrupt.h>
21 #include <linux/reboot.h>
22 #include <linux/spinlock.h>
23 #include <asm/dbdma.h>
24 #include <asm/io.h>
25 #include <asm/pgtable.h>
26 #include <asm/prom.h>
27 #include <asm/system.h>
28 #include <asm/irq.h>
29 #include <asm/hydra.h>
30 #include <asm/processor.h>
31 #include <asm/feature.h>
32
33 #include "scsi.h"
34 #include "hosts.h"
35 #include "mesh.h"
36
37 /*
38 * To do:
39 * - handle aborts correctly
40 * - retry arbitration if lost (unless higher levels do this for us)
41 */
42
43 #define MESH_NEW_STYLE_EH
44
45 #if 1
46 #undef KERN_DEBUG
47 #define KERN_DEBUG KERN_WARNING
48 #endif
49
50 #if CONFIG_SCSI_MESH_SYNC_RATE == 0
51 int mesh_sync_period = 100;
52 int mesh_sync_offset = 0;
53 #else
54 int mesh_sync_period = 1000 / CONFIG_SCSI_MESH_SYNC_RATE; /* ns */
55 int mesh_sync_offset = 15;
56 #endif
57
58 int mesh_sync_targets = 0xff; /* targets to set synchronous (bitmap) */
59 int mesh_resel_targets = 0xff; /* targets that we let disconnect (bitmap) */
60 int mesh_debug_targets = 0; /* print debug for these targets */
61 unsigned char use_active_neg = 0; /* bit mask for SEQ_ACTIVE_NEG if used */
62
63 #define ALLOW_SYNC(tgt) ((mesh_sync_targets >> (tgt)) & 1)
64 #define ALLOW_RESEL(tgt) ((mesh_resel_targets >> (tgt)) & 1)
65 #define ALLOW_DEBUG(tgt) ((mesh_debug_targets >> (tgt)) & 1)
66 #define DEBUG_TARGET(cmd) ((cmd) && ALLOW_DEBUG((cmd)->target))
67
68 struct proc_dir_entry proc_scsi_mesh = {
69 PROC_SCSI_MESH, 4, "mesh",
70 S_IFDIR | S_IRUGO | S_IXUGO, 2
71 };
72
73 #undef MESH_DBG
74 #define N_DBG_LOG 50
75 #define N_DBG_SLOG 20
76 #define NUM_DBG_EVENTS 13
77 #undef DBG_USE_TB /* bombs on 601 */
78
79 struct dbglog {
80 char *fmt;
81 u32 tb;
82 u8 phase;
83 u8 bs0;
84 u8 bs1;
85 u8 tgt;
86 int d;
87 };
88
89 enum mesh_phase {
90 idle,
91 arbitrating,
92 selecting,
93 commanding,
94 dataing,
95 statusing,
96 busfreeing,
97 disconnecting,
98 reselecting
99 };
100
101 enum msg_phase {
102 msg_none,
103 msg_out,
104 msg_out_xxx,
105 msg_out_last,
106 msg_in,
107 msg_in_bad,
108 };
109
110 enum sdtr_phase {
111 do_sdtr,
112 sdtr_sent,
113 sdtr_done
114 };
115
116 struct mesh_target {
117 enum sdtr_phase sdtr_state;
118 int sync_params;
119 int data_goes_out; /* guess as to data direction */
120 Scsi_Cmnd *current_req;
121 u32 saved_ptr;
122 int want_abort;
123 #ifdef MESH_DBG
124 int log_ix;
125 int n_log;
126 struct dbglog log[N_DBG_LOG];
127 #endif
128 };
129
130 struct mesh_state {
131 volatile struct mesh_regs *mesh;
132 int meshintr;
133 volatile struct dbdma_regs *dma;
134 int dmaintr;
135 struct Scsi_Host *host;
136 struct mesh_state *next;
137 Scsi_Cmnd *request_q;
138 Scsi_Cmnd *request_qtail;
139 enum mesh_phase phase; /* what we're currently trying to do */
140 enum msg_phase msgphase;
141 int conn_tgt; /* target we're connected to */
142 Scsi_Cmnd *current_req; /* req we're currently working on */
143 int data_ptr;
144 int dma_started;
145 int dma_count;
146 int stat;
147 int aborting;
148 int expect_reply;
149 int n_msgin;
150 u8 msgin[16];
151 int n_msgout;
152 int last_n_msgout;
153 u8 msgout[16];
154 struct dbdma_cmd *dma_cmds; /* space for dbdma commands, aligned */
155 int clk_freq;
156 struct mesh_target tgts[8];
157 #ifndef MESH_NEW_STYLE_EH
158 Scsi_Cmnd *completed_q;
159 Scsi_Cmnd *completed_qtail;
160 struct tq_struct tqueue;
161 #endif
162 #ifdef MESH_DBG
163 int log_ix;
164 int n_log;
165 struct dbglog log[N_DBG_SLOG];
166 #endif
167 };
168
169 #ifdef MESH_DBG
170
171 static void dlog(struct mesh_state *ms, char *fmt, int a);
172 static void dumplog(struct mesh_state *ms, int tgt);
173 static void dumpslog(struct mesh_state *ms);
174
175 #else
176 static inline void dlog(struct mesh_state *ms, char *fmt, int a)
177 {}
178 static inline void dumplog(struct mesh_state *ms, int tgt)
179 {}
180 static inline void dumpslog(struct mesh_state *ms)
181 {}
182
183 #endif /* MESH_DBG */
184 #define MKWORD(a, b, c, d) (((a) << 24) + ((b) << 16) + ((c) << 8) + (d))
185
186 static struct mesh_state *all_meshes;
187
188 static void mesh_init(struct mesh_state *);
189 static int mesh_notify_reboot(struct notifier_block *, unsigned long, void *);
190 static void mesh_dump_regs(struct mesh_state *);
191 static void mesh_start(struct mesh_state *);
192 static void mesh_start_cmd(struct mesh_state *, Scsi_Cmnd *);
193 #ifndef MESH_NEW_STYLE_EH
194 static void finish_cmds(void *);
195 #endif
196 static void add_sdtr_msg(struct mesh_state *);
197 static void set_sdtr(struct mesh_state *, int, int);
198 static void start_phase(struct mesh_state *);
199 static void get_msgin(struct mesh_state *);
200 static int msgin_length(struct mesh_state *);
201 static void cmd_complete(struct mesh_state *);
202 static void phase_mismatch(struct mesh_state *);
203 static void reselected(struct mesh_state *);
204 static void handle_reset(struct mesh_state *);
205 static void handle_error(struct mesh_state *);
206 static void handle_exception(struct mesh_state *);
207 static void mesh_interrupt(int, void *, struct pt_regs *);
208 static void do_mesh_interrupt(int, void *, struct pt_regs *);
209 static void handle_msgin(struct mesh_state *);
210 static void mesh_done(struct mesh_state *, int);
211 static void mesh_completed(struct mesh_state *, Scsi_Cmnd *);
212 static void set_dma_cmds(struct mesh_state *, Scsi_Cmnd *);
213 static void halt_dma(struct mesh_state *);
214 static int data_goes_out(Scsi_Cmnd *);
215 static void do_abort(struct mesh_state *ms);
216
217 static struct notifier_block mesh_notifier = {
218 mesh_notify_reboot,
219 NULL,
220 0
221 };
222
223 int
224 mesh_detect(Scsi_Host_Template *tp)
225 {
226 struct device_node *mesh;
227 int nmeshes, tgt, *cfp, minper;
228 struct mesh_state *ms, **prev_statep;
229 struct Scsi_Host *mesh_host;
230 void *dma_cmd_space;
231
232 if (_machine == _MACH_Pmac) {
233 use_active_neg = (find_devices("mac-io") ? 0 : SEQ_ACTIVE_NEG);
234 } else {
235 /* CHRP mac-io */
236 use_active_neg = SEQ_ACTIVE_NEG;
237 }
238
239 nmeshes = 0;
240 prev_statep = &all_meshes;
241 /*
242 * On powermacs, the MESH node has device_type "mesh".
243 * On chrp machines, its device_type is "scsi" with
244 * "chrp,mesh0" as its `compatible' property.
245 */
246 mesh = find_devices("mesh");
247 if (mesh == 0)
248 mesh = find_compatible_devices("scsi", "chrp,mesh0");
249 for (; mesh != 0; mesh = mesh->next) {
250 if (mesh->n_addrs != 2 || mesh->n_intrs != 2) {
251 printk(KERN_ERR "mesh: expected 2 addrs and 2 intrs"
252 " (got %d,%d)", mesh->n_addrs, mesh->n_intrs);
253 continue;
254 }
255 mesh_host = scsi_register(tp, sizeof(struct mesh_state));
256 if (mesh_host == 0) {
257 printk(KERN_ERR "mesh: couldn't register host");
258 continue;
259 }
260 mesh_host->unique_id = nmeshes;
261 #ifndef MODULE
262 note_scsi_host(mesh, mesh_host);
263 #endif
264
265 ms = (struct mesh_state *) mesh_host->hostdata;
266 if (ms == 0)
267 panic("no mesh state");
268 memset(ms, 0, sizeof(*ms));
269 ms->host = mesh_host;
270 ms->mesh = (volatile struct mesh_regs *)
271 ioremap(mesh->addrs[0].address, 0x1000);
272 ms->dma = (volatile struct dbdma_regs *)
273 ioremap(mesh->addrs[1].address, 0x1000);
274 ms->meshintr = mesh->intrs[0].line;
275 ms->dmaintr = mesh->intrs[1].line;
276
277 /* Space for dma command list: +1 for stop command,
278 +1 to allow for aligning. */
279 dma_cmd_space = kmalloc((mesh_host->sg_tablesize + 2) *
280 sizeof(struct dbdma_cmd), GFP_KERNEL);
281 if (dma_cmd_space == 0)
282 panic("mesh: couldn't allocate dma command space");
283 ms->dma_cmds = (struct dbdma_cmd *) DBDMA_ALIGN(dma_cmd_space);
284 memset(ms->dma_cmds, 0, (mesh_host->sg_tablesize + 1)
285 * sizeof(struct dbdma_cmd));
286
287 ms->current_req = 0;
288 for (tgt = 0; tgt < 8; ++tgt) {
289 ms->tgts[tgt].sdtr_state = do_sdtr;
290 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
291 ms->tgts[tgt].current_req = 0;
292 }
293 #ifndef MESH_NEW_STYLE_EH
294 ms->tqueue.routine = finish_cmds;
295 ms->tqueue.data = ms;
296 #endif
297 *prev_statep = ms;
298 prev_statep = &ms->next;
299
300 if ((cfp = (int *) get_property(mesh, "clock-frequency",
301 NULL))) {
302 ms->clk_freq = *cfp;
303 } else {
304 printk(KERN_INFO "mesh: assuming 50MHz clock frequency\n");
305 ms->clk_freq = 50000000;
306 }
307 /* The maximum sync rate is clock / 5; increase
308 mesh_sync_period if necessary. */
309 minper = 1000000000 / (ms->clk_freq / 5); /* ns */
310 if (mesh_sync_period < minper)
311 mesh_sync_period = minper;
312
313 feature_set(mesh, FEATURE_MESH_enable);
314 mdelay(200);
315
316 mesh_init(ms);
317
318 if (request_irq(ms->meshintr, do_mesh_interrupt, 0, "MESH", ms)) {
319 printk(KERN_ERR "MESH: can't get irq %d\n", ms->meshintr);
320 }
321
322 ++nmeshes;
323 }
324
325 if ((_machine == _MACH_Pmac) && (nmeshes > 0))
326 register_reboot_notifier(&mesh_notifier);
327
328 return nmeshes;
329 }
330
331 int
332 mesh_queue(Scsi_Cmnd *cmd, void (*done)(Scsi_Cmnd *))
333 {
334 unsigned long flags;
335 struct mesh_state *ms;
336
337 cmd->scsi_done = done;
338 cmd->host_scribble = NULL;
339
340 ms = (struct mesh_state *) cmd->host->hostdata;
341
342 save_flags(flags);
343 cli();
344 if (ms->request_q == NULL)
345 ms->request_q = cmd;
346 else
347 ms->request_qtail->host_scribble = (void *) cmd;
348 ms->request_qtail = cmd;
349
350 if (ms->phase == idle)
351 mesh_start(ms);
352
353 restore_flags(flags);
354 return 0;
355 }
356
357 int
358 mesh_abort(Scsi_Cmnd *cmd)
359 {
360 struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
361
362 printk(KERN_DEBUG "mesh_abort(%p)\n", cmd);
363 mesh_dump_regs(ms);
364 dumplog(ms, cmd->target);
365 dumpslog(ms);
366 return SCSI_ABORT_SNOOZE;
367 }
368
369 static void
370 mesh_dump_regs(struct mesh_state *ms)
371 {
372 volatile struct mesh_regs *mr = ms->mesh;
373 volatile struct dbdma_regs *md = ms->dma;
374 int t;
375 struct mesh_target *tp;
376
377 printk(KERN_DEBUG "mesh: state at %p, regs at %p, dma at %p\n",
378 ms, mr, md);
379 printk(KERN_DEBUG " ct=%4x seq=%2x bs=%4x fc=%2x "
380 "exc=%2x err=%2x im=%2x int=%2x sp=%2x\n",
381 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
382 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
383 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
384 mr->sync_params);
385 while(in_8(&mr->fifo_count))
386 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
387 printk(KERN_DEBUG " dma stat=%x cmdptr=%x\n",
388 in_le32(&md->status), in_le32(&md->cmdptr));
389 printk(KERN_DEBUG " phase=%d msgphase=%d conn_tgt=%d data_ptr=%d\n",
390 ms->phase, ms->msgphase, ms->conn_tgt, ms->data_ptr);
391 printk(KERN_DEBUG " dma_st=%d dma_ct=%d n_msgout=%d\n",
392 ms->dma_started, ms->dma_count, ms->n_msgout);
393 for (t = 0; t < 8; ++t) {
394 tp = &ms->tgts[t];
395 if (tp->current_req == NULL)
396 continue;
397 printk(KERN_DEBUG " target %d: req=%p goes_out=%d saved_ptr=%d\n",
398 t, tp->current_req, tp->data_goes_out, tp->saved_ptr);
399 }
400 }
401
402 int
403 mesh_reset(Scsi_Cmnd *cmd, unsigned how)
404 {
405 struct mesh_state *ms = (struct mesh_state *) cmd->host->hostdata;
406 volatile struct mesh_regs *mr = ms->mesh;
407 volatile struct dbdma_regs *md = ms->dma;
408 unsigned long flags;
409 int ret;
410
411 printk(KERN_DEBUG "mesh_reset %x\n", how);
412 ret = SCSI_RESET_BUS_RESET;
413 save_flags(flags);
414 cli();
415 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
416 out_8(&mr->exception, 0xff); /* clear all exception bits */
417 out_8(&mr->error, 0xff); /* clear all error bits */
418 if (how & SCSI_RESET_SUGGEST_HOST_RESET) {
419 out_8(&mr->sequence, SEQ_RESETMESH);
420 ret |= SCSI_RESET_HOST_RESET;
421 udelay(1);
422 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
423 out_8(&mr->source_id, ms->host->this_id);
424 out_8(&mr->sel_timeout, 25); /* 250ms */
425 out_8(&mr->sync_params, ASYNC_PARAMS);
426 }
427 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
428 udelay(30); /* leave it on for >= 25us */
429 out_8(&mr->bus_status1, 0); /* negate RST */
430 #ifdef DO_ASYNC_RESET
431 if (how & SCSI_RESET_ASYNCHRONOUS) {
432 restore_flags(flags);
433 ret |= SCSI_RESET_PENDING;
434 } else
435 #endif
436 {
437 handle_reset(ms);
438 restore_flags(flags);
439 #ifndef MESH_NEW_STYLE_EH
440 finish_cmds(ms);
441 #endif
442 ret |= SCSI_RESET_SUCCESS;
443 }
444 return ret;
445 }
446
447 /*
448 * If we leave drives set for synchronous transfers (especially
449 * CDROMs), and reboot to MacOS, it gets confused, poor thing.
450 * So, on reboot we reset the SCSI bus.
451 */
452 static int
453 mesh_notify_reboot(struct notifier_block *this, unsigned long code, void *x)
454 {
455 struct mesh_state *ms;
456 volatile struct mesh_regs *mr;
457
458 if (code == SYS_DOWN) {
459 printk(KERN_INFO "resetting MESH scsi bus(es)\n");
460 for (ms = all_meshes; ms != 0; ms = ms->next) {
461 mr = ms->mesh;
462 out_8(&mr->intr_mask, 0);
463 out_8(&mr->interrupt,
464 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
465 out_8(&mr->bus_status1, BS1_RST);
466 udelay(30);
467 out_8(&mr->bus_status1, 0);
468 }
469 }
470 return NOTIFY_DONE;
471 }
472
473 int
474 mesh_command(Scsi_Cmnd *cmd)
475 {
476 printk(KERN_WARNING "whoops... mesh_command called\n");
477 return -1;
478 }
479
480 static void
481 mesh_init(struct mesh_state *ms)
482 {
483 volatile struct mesh_regs *mr = ms->mesh;
484 volatile struct dbdma_regs *md = ms->dma;
485
486 udelay(100);
487
488 out_le32(&md->control, (RUN|PAUSE|FLUSH|WAKE) << 16); /* stop dma */
489 out_8(&mr->exception, 0xff); /* clear all exception bits */
490 out_8(&mr->error, 0xff); /* clear all error bits */
491 out_8(&mr->sequence, SEQ_RESETMESH);
492 udelay(10);
493 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
494 out_8(&mr->source_id, ms->host->this_id);
495 out_8(&mr->sel_timeout, 25); /* 250ms */
496 out_8(&mr->sync_params, ASYNC_PARAMS);
497
498 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
499 udelay(30); /* leave it on for >= 25us */
500 out_8(&mr->bus_status1, 0); /* negate RST */
501
502 out_8(&mr->sequence, SEQ_FLUSHFIFO);
503 udelay(1);
504 out_8(&mr->sync_params, ASYNC_PARAMS);
505 out_8(&mr->sequence, SEQ_ENBRESEL);
506 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
507 }
508
509 /*
510 * Start the next command for a MESH.
511 * Should be called with interrupts disabled.
512 */
513 static void
514 mesh_start(struct mesh_state *ms)
515 {
516 Scsi_Cmnd *cmd, *prev, *next;
517
518 if (ms->phase != idle || ms->current_req != NULL) {
519 printk(KERN_ERR "inappropriate mesh_start (phase=%d, ms=%p)",
520 ms->phase, ms);
521 return;
522 }
523
524 while (ms->phase == idle) {
525 prev = NULL;
526 for (cmd = ms->request_q; ; cmd = (Scsi_Cmnd *) cmd->host_scribble) {
527 if (cmd == NULL)
528 return;
529 if (ms->tgts[cmd->target].current_req == NULL)
530 break;
531 prev = cmd;
532 }
533 next = (Scsi_Cmnd *) cmd->host_scribble;
534 if (prev == NULL)
535 ms->request_q = next;
536 else
537 prev->host_scribble = (void *) next;
538 if (next == NULL)
539 ms->request_qtail = prev;
540
541 mesh_start_cmd(ms, cmd);
542 }
543 }
544
545 static void
546 mesh_start_cmd(struct mesh_state *ms, Scsi_Cmnd *cmd)
547 {
548 volatile struct mesh_regs *mr = ms->mesh;
549 int t;
550
551 ms->current_req = cmd;
552 ms->tgts[cmd->target].data_goes_out = data_goes_out(cmd);
553 ms->tgts[cmd->target].current_req = cmd;
554
555 #if 1
556 if (DEBUG_TARGET(cmd)) {
557 int i;
558 printk(KERN_DEBUG "mesh_start: %p ser=%lu tgt=%d cmd=",
559 cmd, cmd->serial_number, cmd->target);
560 for (i = 0; i < cmd->cmd_len; ++i)
561 printk(" %x", cmd->cmnd[i]);
562 printk(" use_sg=%d buffer=%p bufflen=%u\n",
563 cmd->use_sg, cmd->request_buffer, cmd->request_bufflen);
564 }
565 #endif
566
567 ms->phase = arbitrating;
568 ms->msgphase = msg_none;
569 ms->data_ptr = 0;
570 ms->dma_started = 0;
571 ms->n_msgout = 0;
572 ms->last_n_msgout = 0;
573 ms->expect_reply = 0;
574 ms->conn_tgt = cmd->target;
575 ms->tgts[cmd->target].saved_ptr = 0;
576 ms->stat = DID_OK;
577 ms->aborting = 0;
578 #ifdef MESH_DBG
579 ms->tgts[cmd->target].n_log = 0;
580 dlog(ms, "start cmd=%x", (int) cmd);
581 #endif
582
583 /* Off we go */
584 dlog(ms, "about to arb, intr/exc/err/fc=%.8x",
585 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
586 out_8(&mr->interrupt, INT_CMDDONE);
587 out_8(&mr->sequence, SEQ_ENBRESEL);
588 udelay(1);
589
590 if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
591 /*
592 * Some other device has the bus or is arbitrating for it -
593 * probably a target which is about to reselect us.
594 */
595 dlog(ms, "busy b4 arb, intr/exc/err/fc=%.8x",
596 MKWORD(mr->interrupt, mr->exception,
597 mr->error, mr->fifo_count));
598 for (t = 100; t > 0; --t) {
599 if ((mr->bus_status1 & (BS1_BSY | BS1_SEL)) == 0)
600 break;
601 if (in_8(&mr->interrupt) != 0) {
602 dlog(ms, "intr b4 arb, intr/exc/err/fc=%.8x",
603 MKWORD(mr->interrupt, mr->exception,
604 mr->error, mr->fifo_count));
605 mesh_interrupt(0, (void *)ms, 0);
606 if (ms->phase != arbitrating)
607 return;
608 }
609 udelay(1);
610 }
611 if (mr->bus_status1 & (BS1_BSY | BS1_SEL)) {
612 /* XXX should try again in a little while */
613 ms->stat = DID_BUS_BUSY;
614 ms->phase = idle;
615 mesh_done(ms, 0);
616 return;
617 }
618 }
619
620 /*
621 * Apparently the mesh has a bug where it will assert both its
622 * own bit and the target's bit on the bus during arbitration.
623 */
624 out_8(&mr->dest_id, mr->source_id);
625
626 /*
627 * There appears to be a race with reselection sometimes,
628 * where a target reselects us just as we issue the
629 * arbitrate command. It seems that then the arbitrate
630 * command just hangs waiting for the bus to be free
631 * without giving us a reselection exception.
632 * The only way I have found to get it to respond correctly
633 * is this: disable reselection before issuing the arbitrate
634 * command, then after issuing it, if it looks like a target
635 * is trying to reselect us, reset the mesh and then enable
636 * reselection.
637 */
638 out_8(&mr->sequence, SEQ_DISRESEL);
639 if (in_8(&mr->interrupt) != 0) {
640 dlog(ms, "intr after disresel, intr/exc/err/fc=%.8x",
641 MKWORD(mr->interrupt, mr->exception,
642 mr->error, mr->fifo_count));
643 mesh_interrupt(0, (void *)ms, 0);
644 if (ms->phase != arbitrating)
645 return;
646 dlog(ms, "after intr after disresel, intr/exc/err/fc=%.8x",
647 MKWORD(mr->interrupt, mr->exception,
648 mr->error, mr->fifo_count));
649 }
650
651 out_8(&mr->sequence, SEQ_ARBITRATE);
652
653 for (t = 230; t > 0; --t) {
654 if (in_8(&mr->interrupt) != 0)
655 break;
656 udelay(1);
657 }
658 dlog(ms, "after arb, intr/exc/err/fc=%.8x",
659 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
660 if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
661 && (mr->bus_status0 & BS0_IO)) {
662 /* looks like a reselection - try resetting the mesh */
663 dlog(ms, "resel? after arb, intr/exc/err/fc=%.8x",
664 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
665 out_8(&mr->sequence, SEQ_RESETMESH);
666 udelay(10);
667 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
668 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
669 out_8(&mr->sequence, SEQ_ENBRESEL);
670 for (t = 10; t > 0 && mr->interrupt == 0; --t)
671 udelay(1);
672 dlog(ms, "tried reset after arb, intr/exc/err/fc=%.8x",
673 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
674 #ifndef MESH_MULTIPLE_HOSTS
675 if (mr->interrupt == 0 && (mr->bus_status1 & BS1_SEL)
676 && (mr->bus_status0 & BS0_IO)) {
677 printk(KERN_ERR "mesh: controller not responding"
678 " to reselection!\n");
679 /*
680 * If this is a target reselecting us, and the
681 * mesh isn't responding, the higher levels of
682 * the scsi code will eventually time out and
683 * reset the bus.
684 */
685 }
686 #endif
687 }
688 }
689
690 #ifndef MESH_NEW_STYLE_EH
691 static void
692 finish_cmds(void *data)
693 {
694 struct mesh_state *ms = data;
695 Scsi_Cmnd *cmd;
696 unsigned long flags;
697
698 for (;;) {
699 spin_lock_irqsave(&io_request_lock, flags);
700 cmd = ms->completed_q;
701 if (cmd == NULL) {
702 spin_unlock_irqrestore(&io_request_lock, flags);
703 break;
704 }
705 ms->completed_q = (Scsi_Cmnd *) cmd->host_scribble;
706 (*cmd->scsi_done)(cmd);
707 spin_unlock_irqrestore(&io_request_lock, flags);
708 }
709 }
710 #endif /* MESH_NEW_STYLE_EH */
711
712 static inline void
713 add_sdtr_msg(struct mesh_state *ms)
714 {
715 int i = ms->n_msgout;
716
717 ms->msgout[i] = EXTENDED_MESSAGE;
718 ms->msgout[i+1] = 3;
719 ms->msgout[i+2] = EXTENDED_SDTR;
720 ms->msgout[i+3] = mesh_sync_period/4;
721 ms->msgout[i+4] = (ALLOW_SYNC(ms->conn_tgt)? mesh_sync_offset: 0);
722 ms->n_msgout = i + 5;
723 }
724
725 static void
726 set_sdtr(struct mesh_state *ms, int period, int offset)
727 {
728 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
729 volatile struct mesh_regs *mr = ms->mesh;
730 int v, tr;
731
732 tp->sdtr_state = sdtr_done;
733 if (offset == 0) {
734 /* asynchronous */
735 if (SYNC_OFF(tp->sync_params))
736 printk(KERN_INFO "mesh: target %d now asynchronous\n",
737 ms->conn_tgt);
738 tp->sync_params = ASYNC_PARAMS;
739 out_8(&mr->sync_params, ASYNC_PARAMS);
740 return;
741 }
742 /*
743 * We need to compute ceil(clk_freq * period / 500e6) - 2
744 * without incurring overflow.
745 */
746 v = (ms->clk_freq / 5000) * period;
747 if (v <= 250000) {
748 /* special case: sync_period == 5 * clk_period */
749 v = 0;
750 /* units of tr are 100kB/s */
751 tr = (ms->clk_freq + 250000) / 500000;
752 } else {
753 /* sync_period == (v + 2) * 2 * clk_period */
754 v = (v + 99999) / 100000 - 2;
755 if (v > 15)
756 v = 15; /* oops */
757 tr = ((ms->clk_freq / (v + 2)) + 199999) / 200000;
758 }
759 if (offset > 15)
760 offset = 15; /* can't happen */
761 tp->sync_params = SYNC_PARAMS(offset, v);
762 out_8(&mr->sync_params, tp->sync_params);
763 printk(KERN_INFO "mesh: target %d synchronous at %d.%d MB/s\n",
764 ms->conn_tgt, tr/10, tr%10);
765 }
766
767 static void
768 start_phase(struct mesh_state *ms)
769 {
770 int i, seq, nb;
771 volatile struct mesh_regs *mr = ms->mesh;
772 volatile struct dbdma_regs *md = ms->dma;
773 Scsi_Cmnd *cmd = ms->current_req;
774 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
775
776 dlog(ms, "start_phase nmo/exc/fc/seq = %.8x",
777 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
778 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
779 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
780 switch (ms->msgphase) {
781 case msg_none:
782 break;
783
784 case msg_in:
785 out_8(&mr->count_hi, 0);
786 out_8(&mr->count_lo, 1);
787 out_8(&mr->sequence, SEQ_MSGIN + seq);
788 ms->n_msgin = 0;
789 return;
790
791 case msg_out:
792 /*
793 * To make sure ATN drops before we assert ACK for
794 * the last byte of the message, we have to do the
795 * last byte specially.
796 */
797 if (ms->n_msgout <= 0) {
798 printk(KERN_ERR "mesh: msg_out but n_msgout=%d\n",
799 ms->n_msgout);
800 mesh_dump_regs(ms);
801 ms->msgphase = msg_none;
802 break;
803 }
804 if (ALLOW_DEBUG(ms->conn_tgt)) {
805 printk(KERN_DEBUG "mesh: sending %d msg bytes:",
806 ms->n_msgout);
807 for (i = 0; i < ms->n_msgout; ++i)
808 printk(" %x", ms->msgout[i]);
809 printk("\n");
810 }
811 dlog(ms, "msgout msg=%.8x", MKWORD(ms->n_msgout, ms->msgout[0],
812 ms->msgout[1], ms->msgout[2]));
813 out_8(&mr->count_hi, 0);
814 out_8(&mr->sequence, SEQ_FLUSHFIFO);
815 udelay(1);
816 /*
817 * If ATN is not already asserted, we assert it, then
818 * issue a SEQ_MSGOUT to get the mesh to drop ACK.
819 */
820 if ((mr->bus_status0 & BS0_ATN) == 0) {
821 dlog(ms, "bus0 was %.2x explictly asserting ATN", mr->bus_status0);
822 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
823 udelay(1);
824 out_8(&mr->count_lo, 1);
825 out_8(&mr->sequence, SEQ_MSGOUT + seq);
826 out_8(&mr->bus_status0, 0); /* release explicit ATN */
827 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
828 }
829 if (ms->n_msgout == 1) {
830 /*
831 * We can't issue the SEQ_MSGOUT without ATN
832 * until the target has asserted REQ. The logic
833 * in cmd_complete handles both situations:
834 * REQ already asserted or not.
835 */
836 cmd_complete(ms);
837 } else {
838 out_8(&mr->count_lo, ms->n_msgout - 1);
839 out_8(&mr->sequence, SEQ_MSGOUT + seq);
840 for (i = 0; i < ms->n_msgout - 1; ++i)
841 out_8(&mr->fifo, ms->msgout[i]);
842 }
843 return;
844
845 default:
846 printk(KERN_ERR "mesh bug: start_phase msgphase=%d\n",
847 ms->msgphase);
848 }
849
850 switch (ms->phase) {
851 case selecting:
852 out_8(&mr->dest_id, ms->conn_tgt);
853 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
854 break;
855 case commanding:
856 out_8(&mr->sync_params, tp->sync_params);
857 out_8(&mr->count_hi, 0);
858 if (cmd) {
859 out_8(&mr->count_lo, cmd->cmd_len);
860 out_8(&mr->sequence, SEQ_COMMAND + seq);
861 for (i = 0; i < cmd->cmd_len; ++i)
862 out_8(&mr->fifo, cmd->cmnd[i]);
863 } else {
864 out_8(&mr->count_lo, 6);
865 out_8(&mr->sequence, SEQ_COMMAND + seq);
866 for (i = 0; i < 6; ++i)
867 out_8(&mr->fifo, 0);
868 }
869 break;
870 case dataing:
871 /* transfer data, if any */
872 if (!ms->dma_started) {
873 set_dma_cmds(ms, cmd);
874 out_le32(&md->cmdptr, virt_to_phys(ms->dma_cmds));
875 out_le32(&md->control, (RUN << 16) | RUN);
876 ms->dma_started = 1;
877 }
878 nb = ms->dma_count;
879 if (nb > 0xfff0)
880 nb = 0xfff0;
881 ms->dma_count -= nb;
882 ms->data_ptr += nb;
883 out_8(&mr->count_lo, nb);
884 out_8(&mr->count_hi, nb >> 8);
885 out_8(&mr->sequence, (tp->data_goes_out?
886 SEQ_DATAOUT: SEQ_DATAIN) + SEQ_DMA_MODE + seq);
887 break;
888 case statusing:
889 out_8(&mr->count_hi, 0);
890 out_8(&mr->count_lo, 1);
891 out_8(&mr->sequence, SEQ_STATUS + seq);
892 break;
893 case busfreeing:
894 case disconnecting:
895 out_8(&mr->sequence, SEQ_ENBRESEL);
896 udelay(1);
897 dlog(ms, "enbresel intr/exc/err/fc=%.8x",
898 MKWORD(mr->interrupt, mr->exception, mr->error,
899 mr->fifo_count));
900 out_8(&mr->sequence, SEQ_BUSFREE);
901 break;
902 default:
903 printk(KERN_ERR "mesh: start_phase called with phase=%d\n",
904 ms->phase);
905 dumpslog(ms);
906 }
907
908 }
909
910 static inline void
911 get_msgin(struct mesh_state *ms)
912 {
913 volatile struct mesh_regs *mr = ms->mesh;
914 int i, n;
915
916 n = mr->fifo_count;
917 if (n != 0) {
918 i = ms->n_msgin;
919 ms->n_msgin = i + n;
920 for (; n > 0; --n)
921 ms->msgin[i++] = in_8(&mr->fifo);
922 }
923 }
924
925 static inline int
926 msgin_length(struct mesh_state *ms)
927 {
928 int b, n;
929
930 n = 1;
931 if (ms->n_msgin > 0) {
932 b = ms->msgin[0];
933 if (b == 1) {
934 /* extended message */
935 n = ms->n_msgin < 2? 2: ms->msgin[1] + 2;
936 } else if (0x20 <= b && b <= 0x2f) {
937 /* 2-byte message */
938 n = 2;
939 }
940 }
941 return n;
942 }
943
944 static void
945 cmd_complete(struct mesh_state *ms)
946 {
947 volatile struct mesh_regs *mr = ms->mesh;
948 Scsi_Cmnd *cmd = ms->current_req;
949 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
950 int seq, n, t;
951
952 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
953 seq = use_active_neg + (ms->n_msgout? SEQ_ATN: 0);
954 switch (ms->msgphase) {
955 case msg_out_xxx:
956 /* huh? we expected a phase mismatch */
957 ms->n_msgin = 0;
958 ms->msgphase = msg_in;
959 /* fall through */
960
961 case msg_in:
962 /* should have some message bytes in fifo */
963 get_msgin(ms);
964 n = msgin_length(ms);
965 if (ms->n_msgin < n) {
966 out_8(&mr->count_lo, n - ms->n_msgin);
967 out_8(&mr->sequence, SEQ_MSGIN + seq);
968 } else {
969 ms->msgphase = msg_none;
970 handle_msgin(ms);
971 start_phase(ms);
972 }
973 break;
974
975 case msg_in_bad:
976 out_8(&mr->sequence, SEQ_FLUSHFIFO);
977 udelay(1);
978 out_8(&mr->count_lo, 1);
979 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
980 break;
981
982 case msg_out:
983 /*
984 * To get the right timing on ATN wrt ACK, we have
985 * to get the MESH to drop ACK, wait until REQ gets
986 * asserted, then drop ATN. To do this we first
987 * issue a SEQ_MSGOUT with ATN and wait for REQ,
988 * then change the command to a SEQ_MSGOUT w/o ATN.
989 * If we don't see REQ in a reasonable time, we
990 * change the command to SEQ_MSGIN with ATN,
991 * wait for the phase mismatch interrupt, then
992 * issue the SEQ_MSGOUT without ATN.
993 */
994 out_8(&mr->count_lo, 1);
995 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
996 t = 30; /* wait up to 30us */
997 while ((mr->bus_status0 & BS0_REQ) == 0 && --t >= 0)
998 udelay(1);
999 dlog(ms, "last_mbyte err/exc/fc/cl=%.8x",
1000 MKWORD(mr->error, mr->exception,
1001 mr->fifo_count, mr->count_lo));
1002 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1003 /* whoops, target didn't do what we expected */
1004 ms->last_n_msgout = ms->n_msgout;
1005 ms->n_msgout = 0;
1006 if (in_8(&mr->interrupt) & INT_ERROR) {
1007 printk(KERN_ERR "mesh: error %x in msg_out\n",
1008 in_8(&mr->error));
1009 handle_error(ms);
1010 return;
1011 }
1012 if (in_8(&mr->exception) != EXC_PHASEMM)
1013 printk(KERN_ERR "mesh: exc %x in msg_out\n",
1014 in_8(&mr->exception));
1015 else
1016 printk(KERN_DEBUG "mesh: bs0=%x in msg_out\n",
1017 in_8(&mr->bus_status0));
1018 handle_exception(ms);
1019 return;
1020 }
1021 if (mr->bus_status0 & BS0_REQ) {
1022 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1023 udelay(1);
1024 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1025 ms->msgphase = msg_out_last;
1026 } else {
1027 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1028 ms->msgphase = msg_out_xxx;
1029 }
1030 break;
1031
1032 case msg_out_last:
1033 ms->last_n_msgout = ms->n_msgout;
1034 ms->n_msgout = 0;
1035 ms->msgphase = ms->expect_reply? msg_in: msg_none;
1036 start_phase(ms);
1037 break;
1038
1039 case msg_none:
1040 switch (ms->phase) {
1041 case idle:
1042 printk(KERN_ERR "mesh: interrupt in idle phase?\n");
1043 dumpslog(ms);
1044 return;
1045 case selecting:
1046 dlog(ms, "Selecting phase at command completion",0);
1047 ms->msgout[0] = IDENTIFY(ALLOW_RESEL(ms->conn_tgt),
1048 (cmd? cmd->lun: 0));
1049 ms->n_msgout = 1;
1050 ms->expect_reply = 0;
1051 if (ms->aborting) {
1052 ms->msgout[0] = ABORT;
1053 ms->n_msgout++;
1054 } else if (tp->sdtr_state == do_sdtr) {
1055 /* add SDTR message */
1056 add_sdtr_msg(ms);
1057 ms->expect_reply = 1;
1058 tp->sdtr_state = sdtr_sent;
1059 }
1060 ms->msgphase = msg_out;
1061 /*
1062 * We need to wait for REQ before dropping ATN.
1063 * We wait for at most 30us, then fall back to
1064 * a scheme where we issue a SEQ_COMMAND with ATN,
1065 * which will give us a phase mismatch interrupt
1066 * when REQ does come, and then we send the message.
1067 */
1068 t = 230; /* wait up to 230us */
1069 while ((mr->bus_status0 & BS0_REQ) == 0) {
1070 if (--t < 0) {
1071 dlog(ms, "impatient for req", ms->n_msgout);
1072 ms->msgphase = msg_none;
1073 break;
1074 }
1075 udelay(1);
1076 }
1077 break;
1078 case dataing:
1079 if (ms->dma_count != 0) {
1080 start_phase(ms);
1081 return;
1082 }
1083 /*
1084 * We can get a phase mismatch here if the target
1085 * changes to the status phase, even though we have
1086 * had a command complete interrupt. Then, if we
1087 * issue the SEQ_STATUS command, we'll get a sequence
1088 * error interrupt. Which isn't so bad except that
1089 * occasionally the mesh actually executes the
1090 * SEQ_STATUS *as well as* giving us the sequence
1091 * error and phase mismatch exception.
1092 */
1093 out_8(&mr->sequence, 0);
1094 out_8(&mr->interrupt,
1095 INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1096 halt_dma(ms);
1097 break;
1098 case statusing:
1099 if (cmd) {
1100 cmd->SCp.Status = mr->fifo;
1101 if (DEBUG_TARGET(cmd))
1102 printk(KERN_DEBUG "mesh: status is %x\n",
1103 cmd->SCp.Status);
1104 }
1105 ms->msgphase = msg_in;
1106 break;
1107 case busfreeing:
1108 mesh_done(ms, 1);
1109 return;
1110 case disconnecting:
1111 ms->current_req = 0;
1112 ms->phase = idle;
1113 mesh_start(ms);
1114 return;
1115 default:
1116 break;
1117 }
1118 ++ms->phase;
1119 start_phase(ms);
1120 break;
1121 }
1122 }
1123
1124 static void phase_mismatch(struct mesh_state *ms)
1125 {
1126 volatile struct mesh_regs *mr = ms->mesh;
1127 int phase;
1128
1129 dlog(ms, "phasemm ch/cl/seq/fc=%.8x",
1130 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1131 phase = mr->bus_status0 & BS0_PHASE;
1132 if (ms->msgphase == msg_out_xxx && phase == BP_MSGOUT) {
1133 /* output the last byte of the message, without ATN */
1134 out_8(&mr->count_lo, 1);
1135 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1136 udelay(1);
1137 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1138 ms->msgphase = msg_out_last;
1139 return;
1140 }
1141
1142 if (ms->msgphase == msg_in) {
1143 get_msgin(ms);
1144 if (ms->n_msgin)
1145 handle_msgin(ms);
1146 }
1147
1148 if (ms->dma_started)
1149 halt_dma(ms);
1150 if (mr->fifo_count) {
1151 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1152 udelay(1);
1153 }
1154
1155 ms->msgphase = msg_none;
1156 switch (phase) {
1157 case BP_DATAIN:
1158 ms->tgts[ms->conn_tgt].data_goes_out = 0;
1159 ms->phase = dataing;
1160 break;
1161 case BP_DATAOUT:
1162 ms->tgts[ms->conn_tgt].data_goes_out = 1;
1163 ms->phase = dataing;
1164 break;
1165 case BP_COMMAND:
1166 ms->phase = commanding;
1167 break;
1168 case BP_STATUS:
1169 ms->phase = statusing;
1170 break;
1171 case BP_MSGIN:
1172 ms->msgphase = msg_in;
1173 ms->n_msgin = 0;
1174 break;
1175 case BP_MSGOUT:
1176 ms->msgphase = msg_out;
1177 if (ms->n_msgout == 0) {
1178 if (ms->aborting) {
1179 do_abort(ms);
1180 } else {
1181 if (ms->last_n_msgout == 0) {
1182 printk(KERN_DEBUG
1183 "mesh: no msg to repeat\n");
1184 ms->msgout[0] = NOP;
1185 ms->last_n_msgout = 1;
1186 }
1187 ms->n_msgout = ms->last_n_msgout;
1188 }
1189 }
1190 break;
1191 default:
1192 printk(KERN_DEBUG "mesh: unknown scsi phase %x\n", phase);
1193 ms->stat = DID_ERROR;
1194 mesh_done(ms, 1);
1195 return;
1196 }
1197
1198 start_phase(ms);
1199 }
1200
1201 static void
1202 reselected(struct mesh_state *ms)
1203 {
1204 volatile struct mesh_regs *mr = ms->mesh;
1205 Scsi_Cmnd *cmd;
1206 struct mesh_target *tp;
1207 int b, t, prev;
1208
1209 switch (ms->phase) {
1210 case idle:
1211 break;
1212 case arbitrating:
1213 if ((cmd = ms->current_req) != NULL) {
1214 /* put the command back on the queue */
1215 cmd->host_scribble = (void *) ms->request_q;
1216 if (ms->request_q == NULL)
1217 ms->request_qtail = cmd;
1218 ms->request_q = cmd;
1219 tp = &ms->tgts[cmd->target];
1220 tp->current_req = NULL;
1221 }
1222 break;
1223 case busfreeing:
1224 ms->phase = reselecting;
1225 mesh_done(ms, 0);
1226 break;
1227 case disconnecting:
1228 break;
1229 default:
1230 printk(KERN_ERR "mesh: reselected in phase %d/%d tgt %d\n",
1231 ms->msgphase, ms->phase, ms->conn_tgt);
1232 dumplog(ms, ms->conn_tgt);
1233 dumpslog(ms);
1234 }
1235
1236 ms->current_req = NULL;
1237 ms->phase = dataing;
1238 ms->msgphase = msg_in;
1239 ms->dma_started = 0;
1240 ms->n_msgout = 0;
1241 ms->last_n_msgout = 0;
1242 prev = ms->conn_tgt;
1243
1244 /*
1245 * We seem to get abortive reselections sometimes.
1246 */
1247 while ((mr->bus_status1 & BS1_BSY) == 0) {
1248 static int mesh_aborted_resels;
1249 mesh_aborted_resels++;
1250 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1251 udelay(1);
1252 out_8(&mr->sequence, SEQ_ENBRESEL);
1253 udelay(5);
1254 dlog(ms, "extra resel err/exc/fc = %.6x",
1255 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
1256 }
1257 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1258 udelay(1);
1259 out_8(&mr->sequence, SEQ_ENBRESEL);
1260 udelay(1);
1261 out_8(&mr->sync_params, ASYNC_PARAMS);
1262
1263 /*
1264 * Find out who reselected us.
1265 */
1266 if (mr->fifo_count == 0) {
1267 printk(KERN_ERR "mesh: reselection but nothing in fifo?\n");
1268 ms->conn_tgt = ms->host->this_id;
1269 goto bogus;
1270 }
1271 /* get the last byte in the fifo */
1272 do {
1273 b = in_8(&mr->fifo);
1274 dlog(ms, "reseldata %x", b);
1275 } while (in_8(&mr->fifo_count));
1276 for (t = 0; t < 8; ++t)
1277 if ((b & (1 << t)) != 0 && t != ms->host->this_id)
1278 break;
1279 if (b != (1 << t) + (1 << ms->host->this_id)) {
1280 printk(KERN_ERR "mesh: bad reselection data %x\n", b);
1281 ms->conn_tgt = ms->host->this_id;
1282 goto bogus;
1283 }
1284
1285
1286 /*
1287 * Set up to continue with that target's transfer.
1288 */
1289 ms->conn_tgt = t;
1290 tp = &ms->tgts[t];
1291 out_8(&mr->sync_params, tp->sync_params);
1292 if (ALLOW_DEBUG(t)) {
1293 printk(KERN_DEBUG "mesh: reselected by target %d\n", t);
1294 printk(KERN_DEBUG "mesh: saved_ptr=%x goes_out=%d cmd=%p\n",
1295 tp->saved_ptr, tp->data_goes_out, tp->current_req);
1296 }
1297 ms->current_req = tp->current_req;
1298 if (tp->current_req == NULL) {
1299 printk(KERN_ERR "mesh: reselected by tgt %d but no cmd!\n", t);
1300 goto bogus;
1301 }
1302 ms->data_ptr = tp->saved_ptr;
1303 dlog(ms, "resel prev tgt=%d", prev);
1304 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
1305 start_phase(ms);
1306 return;
1307
1308 bogus:
1309 dumplog(ms, ms->conn_tgt);
1310 dumpslog(ms);
1311 ms->data_ptr = 0;
1312 ms->aborting = 1;
1313 start_phase(ms);
1314 }
1315
1316 static void do_abort(struct mesh_state *ms)
1317 {
1318 ms->msgout[0] = ABORT;
1319 ms->n_msgout = 1;
1320 ms->aborting = 1;
1321 ms->stat = DID_ABORT;
1322 dlog(ms, "abort", 0);
1323 }
1324
1325 static void
1326 handle_reset(struct mesh_state *ms)
1327 {
1328 int tgt;
1329 struct mesh_target *tp;
1330 Scsi_Cmnd *cmd;
1331 volatile struct mesh_regs *mr = ms->mesh;
1332
1333 for (tgt = 0; tgt < 8; ++tgt) {
1334 tp = &ms->tgts[tgt];
1335 if ((cmd = tp->current_req) != NULL) {
1336 cmd->result = DID_RESET << 16;
1337 tp->current_req = NULL;
1338 mesh_completed(ms, cmd);
1339 }
1340 ms->tgts[tgt].sdtr_state = do_sdtr;
1341 ms->tgts[tgt].sync_params = ASYNC_PARAMS;
1342 }
1343 ms->current_req = NULL;
1344 while ((cmd = ms->request_q) != NULL) {
1345 ms->request_q = (Scsi_Cmnd *) cmd->host_scribble;
1346 cmd->result = DID_RESET << 16;
1347 mesh_completed(ms, cmd);
1348 }
1349 ms->phase = idle;
1350 ms->msgphase = msg_none;
1351 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1352 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1353 udelay(1);
1354 out_8(&mr->sync_params, ASYNC_PARAMS);
1355 out_8(&mr->sequence, SEQ_ENBRESEL);
1356 }
1357
1358 static void
1359 do_mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1360 {
1361 unsigned long flags;
1362
1363 spin_lock_irqsave(&io_request_lock, flags);
1364 mesh_interrupt(irq, dev_id, ptregs);
1365 spin_unlock_irqrestore(&io_request_lock, flags);
1366 }
1367
1368 static void handle_error(struct mesh_state *ms)
1369 {
1370 int err, exc, count;
1371 volatile struct mesh_regs *mr = ms->mesh;
1372
1373 err = in_8(&mr->error);
1374 exc = in_8(&mr->exception);
1375 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1376 dlog(ms, "error err/exc/fc/cl=%.8x",
1377 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1378 if (err & ERR_SCSIRESET) {
1379 /* SCSI bus was reset */
1380 printk(KERN_INFO "mesh: SCSI bus reset detected: "
1381 "waiting for end...");
1382 while ((mr->bus_status1 & BS1_RST) != 0)
1383 udelay(1);
1384 printk("done\n");
1385 handle_reset(ms);
1386 /* request_q is empty, no point in mesh_start() */
1387 return;
1388 }
1389 if (err & ERR_UNEXPDISC) {
1390 /* Unexpected disconnect */
1391 if (exc & EXC_RESELECTED) {
1392 reselected(ms);
1393 return;
1394 }
1395 if (!ms->aborting) {
1396 printk(KERN_WARNING "mesh: target %d aborted\n",
1397 ms->conn_tgt);
1398 dumplog(ms, ms->conn_tgt);
1399 dumpslog(ms);
1400 }
1401 out_8(&mr->interrupt, INT_CMDDONE);
1402 ms->stat = DID_ABORT;
1403 mesh_done(ms, 1);
1404 return;
1405 }
1406 if (err & ERR_PARITY) {
1407 if (ms->msgphase == msg_in) {
1408 printk(KERN_ERR "mesh: msg parity error, target %d\n",
1409 ms->conn_tgt);
1410 ms->msgout[0] = MSG_PARITY_ERROR;
1411 ms->n_msgout = 1;
1412 ms->msgphase = msg_in_bad;
1413 cmd_complete(ms);
1414 return;
1415 }
1416 if (ms->stat == DID_OK) {
1417 printk(KERN_ERR "mesh: parity error, target %d\n",
1418 ms->conn_tgt);
1419 ms->stat = DID_PARITY;
1420 }
1421 count = (mr->count_hi << 8) + mr->count_lo;
1422 if (count == 0) {
1423 cmd_complete(ms);
1424 } else {
1425 /* reissue the data transfer command */
1426 out_8(&mr->sequence, mr->sequence);
1427 }
1428 return;
1429 }
1430 if (err & ERR_SEQERR) {
1431 if (exc & EXC_RESELECTED) {
1432 /* This can happen if we issue a command to
1433 get the bus just after the target reselects us. */
1434 static int mesh_resel_seqerr;
1435 mesh_resel_seqerr++;
1436 reselected(ms);
1437 return;
1438 }
1439 if (exc == EXC_PHASEMM) {
1440 static int mesh_phasemm_seqerr;
1441 mesh_phasemm_seqerr++;
1442 phase_mismatch(ms);
1443 return;
1444 }
1445 printk(KERN_ERR "mesh: sequence error (err=%x exc=%x)\n",
1446 err, exc);
1447 } else {
1448 printk(KERN_ERR "mesh: unknown error %x (exc=%x)\n", err, exc);
1449 }
1450 mesh_dump_regs(ms);
1451 dumplog(ms, ms->conn_tgt);
1452 if (ms->phase > selecting && (mr->bus_status1 & BS1_BSY)) {
1453 /* try to do what the target wants */
1454 do_abort(ms);
1455 phase_mismatch(ms);
1456 return;
1457 }
1458 ms->stat = DID_ERROR;
1459 mesh_done(ms, 1);
1460 }
1461
1462 static void handle_exception(struct mesh_state *ms)
1463 {
1464 int exc;
1465 volatile struct mesh_regs *mr = ms->mesh;
1466
1467 exc = in_8(&mr->exception);
1468 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1469 if (exc & EXC_RESELECTED) {
1470 static int mesh_resel_exc;
1471 mesh_resel_exc++;
1472 reselected(ms);
1473 } else if (exc == EXC_ARBLOST) {
1474 printk(KERN_DEBUG "mesh: lost arbitration\n");
1475 ms->stat = DID_BUS_BUSY;
1476 mesh_done(ms, 1);
1477 } else if (exc == EXC_SELTO) {
1478 /* selection timed out */
1479 ms->stat = DID_BAD_TARGET;
1480 mesh_done(ms, 1);
1481 } else if (exc == EXC_PHASEMM) {
1482 /* target wants to do something different:
1483 find out what it wants and do it. */
1484 phase_mismatch(ms);
1485 } else {
1486 printk(KERN_ERR "mesh: can't cope with exception %x\n", exc);
1487 mesh_dump_regs(ms);
1488 dumplog(ms, ms->conn_tgt);
1489 do_abort(ms);
1490 phase_mismatch(ms);
1491 }
1492 }
1493
1494 static void
1495 mesh_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
1496 {
1497 struct mesh_state *ms = (struct mesh_state *) dev_id;
1498 volatile struct mesh_regs *mr = ms->mesh;
1499 int intr;
1500
1501 #if 0
1502 if (ALLOW_DEBUG(ms->conn_tgt))
1503 printk(KERN_DEBUG "mesh_intr, bs0=%x int=%x exc=%x err=%x "
1504 "phase=%d msgphase=%d\n", mr->bus_status0,
1505 mr->interrupt, mr->exception, mr->error,
1506 ms->phase, ms->msgphase);
1507 #endif
1508 while ((intr = in_8(&mr->interrupt)) != 0) {
1509 dlog(ms, "interrupt intr/err/exc/seq=%.8x",
1510 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1511 if (intr & INT_ERROR) {
1512 handle_error(ms);
1513 } else if (intr & INT_EXCEPTION) {
1514 handle_exception(ms);
1515 } else if (intr & INT_CMDDONE) {
1516 out_8(&mr->interrupt, INT_CMDDONE);
1517 cmd_complete(ms);
1518 }
1519 }
1520 }
1521
1522 static void
1523 handle_msgin(struct mesh_state *ms)
1524 {
1525 int i, code;
1526 Scsi_Cmnd *cmd = ms->current_req;
1527 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1528
1529 if (ms->n_msgin == 0)
1530 return;
1531 code = ms->msgin[0];
1532 if (ALLOW_DEBUG(ms->conn_tgt)) {
1533 printk(KERN_DEBUG "got %d message bytes:", ms->n_msgin);
1534 for (i = 0; i < ms->n_msgin; ++i)
1535 printk(" %x", ms->msgin[i]);
1536 printk("\n");
1537 }
1538 dlog(ms, "msgin msg=%.8x",
1539 MKWORD(ms->n_msgin, code, ms->msgin[1], ms->msgin[2]));
1540
1541 ms->expect_reply = 0;
1542 ms->n_msgout = 0;
1543 if (ms->n_msgin < msgin_length(ms))
1544 goto reject;
1545 if (cmd)
1546 cmd->SCp.Message = code;
1547 switch (code) {
1548 case COMMAND_COMPLETE:
1549 break;
1550 case EXTENDED_MESSAGE:
1551 switch (ms->msgin[2]) {
1552 case EXTENDED_MODIFY_DATA_POINTER:
1553 ms->data_ptr += (ms->msgin[3] << 24) + ms->msgin[6]
1554 + (ms->msgin[4] << 16) + (ms->msgin[5] << 8);
1555 break;
1556 case EXTENDED_SDTR:
1557 if (tp->sdtr_state != sdtr_sent) {
1558 /* reply with an SDTR */
1559 add_sdtr_msg(ms);
1560 /* limit period to at least his value,
1561 offset to no more than his */
1562 if (ms->msgout[3] < ms->msgin[3])
1563 ms->msgout[3] = ms->msgin[3];
1564 if (ms->msgout[4] > ms->msgin[4])
1565 ms->msgout[4] = ms->msgin[4];
1566 set_sdtr(ms, ms->msgout[3], ms->msgout[4]);
1567 ms->msgphase = msg_out;
1568 } else {
1569 set_sdtr(ms, ms->msgin[3], ms->msgin[4]);
1570 }
1571 break;
1572 default:
1573 goto reject;
1574 }
1575 break;
1576 case SAVE_POINTERS:
1577 tp->saved_ptr = ms->data_ptr;
1578 break;
1579 case RESTORE_POINTERS:
1580 ms->data_ptr = tp->saved_ptr;
1581 break;
1582 case DISCONNECT:
1583 ms->phase = disconnecting;
1584 break;
1585 case ABORT:
1586 break;
1587 case MESSAGE_REJECT:
1588 if (tp->sdtr_state == sdtr_sent)
1589 set_sdtr(ms, 0, 0);
1590 break;
1591 case NOP:
1592 break;
1593 default:
1594 if (IDENTIFY_BASE <= code && code <= IDENTIFY_BASE + 7) {
1595 if (cmd == NULL) {
1596 do_abort(ms);
1597 ms->msgphase = msg_out;
1598 } else if (code != cmd->lun + IDENTIFY_BASE) {
1599 printk(KERN_WARNING "mesh: lun mismatch "
1600 "(%d != %d) on reselection from "
1601 "target %d\n", i, cmd->lun,
1602 ms->conn_tgt);
1603 }
1604 break;
1605 }
1606 goto reject;
1607 }
1608 return;
1609
1610 reject:
1611 printk(KERN_WARNING "mesh: rejecting message from target %d:",
1612 ms->conn_tgt);
1613 for (i = 0; i < ms->n_msgin; ++i)
1614 printk(" %x", ms->msgin[i]);
1615 printk("\n");
1616 ms->msgout[0] = MESSAGE_REJECT;
1617 ms->n_msgout = 1;
1618 ms->msgphase = msg_out;
1619 }
1620
1621 static void
1622 mesh_done(struct mesh_state *ms, int start_next)
1623 {
1624 Scsi_Cmnd *cmd;
1625 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1626
1627 cmd = ms->current_req;
1628 ms->current_req = 0;
1629 tp->current_req = 0;
1630 if (cmd) {
1631 cmd->result = (ms->stat << 16) + cmd->SCp.Status;
1632 if (ms->stat == DID_OK)
1633 cmd->result += (cmd->SCp.Message << 8);
1634 if (DEBUG_TARGET(cmd)) {
1635 printk(KERN_DEBUG "mesh_done: result = %x, data_ptr=%d, buflen=%d\n",
1636 cmd->result, ms->data_ptr, cmd->request_bufflen);
1637 if ((cmd->cmnd[0] == 0 || cmd->cmnd[0] == 0x12 || cmd->cmnd[0] == 3)
1638 && cmd->request_buffer != 0) {
1639 unsigned char *b = cmd->request_buffer;
1640 printk(KERN_DEBUG "buffer = %x %x %x %x %x %x %x %x\n",
1641 b[0], b[1], b[2], b[3], b[4], b[5], b[6], b[7]);
1642 }
1643 }
1644 cmd->SCp.this_residual -= ms->data_ptr;
1645 mesh_completed(ms, cmd);
1646 }
1647 if (start_next) {
1648 out_8(&ms->mesh->sequence, SEQ_ENBRESEL);
1649 udelay(1);
1650 ms->phase = idle;
1651 mesh_start(ms);
1652 }
1653 }
1654
1655 static void
1656 mesh_completed(struct mesh_state *ms, Scsi_Cmnd *cmd)
1657 {
1658 #ifdef MESH_NEW_STYLE_EH
1659 (*cmd->scsi_done)(cmd);
1660 #else
1661 if (ms->completed_q == NULL)
1662 ms->completed_q = cmd;
1663 else
1664 ms->completed_qtail->host_scribble = (void *) cmd;
1665 ms->completed_qtail = cmd;
1666 cmd->host_scribble = NULL;
1667 queue_task(&ms->tqueue, &tq_immediate);
1668 mark_bh(IMMEDIATE_BH);
1669 #endif /* MESH_NEW_STYLE_EH */
1670 }
1671
1672 /*
1673 * Set up DMA commands for transferring data.
1674 */
1675 static void
1676 set_dma_cmds(struct mesh_state *ms, Scsi_Cmnd *cmd)
1677 {
1678 int i, dma_cmd, total, off, dtot;
1679 struct scatterlist *scl;
1680 struct dbdma_cmd *dcmds;
1681
1682 dma_cmd = ms->tgts[ms->conn_tgt].data_goes_out?
1683 OUTPUT_MORE: INPUT_MORE;
1684 dcmds = ms->dma_cmds;
1685 dtot = 0;
1686 if (cmd) {
1687 cmd->SCp.this_residual = cmd->request_bufflen;
1688 if (cmd->use_sg > 0) {
1689 total = 0;
1690 scl = (struct scatterlist *) cmd->buffer;
1691 off = ms->data_ptr;
1692 for (i = 0; i < cmd->use_sg; ++i, ++scl) {
1693 total += scl->length;
1694 if (off >= scl->length) {
1695 off -= scl->length;
1696 continue;
1697 }
1698 if (scl->length > 0xffff)
1699 panic("mesh: scatterlist element >= 64k");
1700 st_le16(&dcmds->req_count, scl->length - off);
1701 st_le16(&dcmds->command, dma_cmd);
1702 st_le32(&dcmds->phy_addr,
1703 virt_to_phys(scl->address) + off);
1704 dcmds->xfer_status = 0;
1705 ++dcmds;
1706 dtot += scl->length - off;
1707 off = 0;
1708 }
1709 } else if (ms->data_ptr < cmd->request_bufflen) {
1710 dtot = cmd->request_bufflen - ms->data_ptr;
1711 if (dtot > 0xffff)
1712 panic("mesh: transfer size >= 64k");
1713 st_le16(&dcmds->req_count, dtot);
1714 st_le32(&dcmds->phy_addr,
1715 virt_to_phys(cmd->request_buffer) + ms->data_ptr);
1716 dcmds->xfer_status = 0;
1717 ++dcmds;
1718 }
1719 }
1720 if (dtot == 0) {
1721 /* Either the target has overrun our buffer,
1722 or the caller didn't provide a buffer. */
1723 static char mesh_extra_buf[64];
1724
1725 dtot = sizeof(mesh_extra_buf);
1726 st_le16(&dcmds->req_count, dtot);
1727 st_le32(&dcmds->phy_addr, virt_to_phys(mesh_extra_buf));
1728 dcmds->xfer_status = 0;
1729 ++dcmds;
1730 }
1731 dma_cmd += OUTPUT_LAST - OUTPUT_MORE;
1732 st_le16(&dcmds[-1].command, dma_cmd);
1733 memset(dcmds, 0, sizeof(*dcmds));
1734 st_le16(&dcmds->command, DBDMA_STOP);
1735 ms->dma_count = dtot;
1736 }
1737
1738 static void
1739 halt_dma(struct mesh_state *ms)
1740 {
1741 volatile struct dbdma_regs *md = ms->dma;
1742 volatile struct mesh_regs *mr = ms->mesh;
1743 Scsi_Cmnd *cmd = ms->current_req;
1744 int t, nb;
1745
1746 if (!ms->tgts[ms->conn_tgt].data_goes_out) {
1747 /* wait a little while until the fifo drains */
1748 t = 50;
1749 while (t > 0 && mr->fifo_count != 0
1750 && (in_le32(&md->status) & ACTIVE) != 0) {
1751 --t;
1752 udelay(1);
1753 }
1754 }
1755 out_le32(&md->control, RUN << 16); /* turn off RUN bit */
1756 nb = (mr->count_hi << 8) + mr->count_lo;
1757 dlog(ms, "halt_dma fc/count=%.6x",
1758 MKWORD(0, mr->fifo_count, 0, nb));
1759 if (ms->tgts[ms->conn_tgt].data_goes_out)
1760 nb += mr->fifo_count;
1761 /* nb is the number of bytes not yet transferred
1762 to/from the target. */
1763 ms->data_ptr -= nb;
1764 dlog(ms, "data_ptr %x", ms->data_ptr);
1765 if (ms->data_ptr < 0) {
1766 printk(KERN_ERR "mesh: halt_dma: data_ptr=%d (nb=%d, ms=%p)\n",
1767 ms->data_ptr, nb, ms);
1768 ms->data_ptr = 0;
1769 #ifdef MESH_DBG
1770 dumplog(ms, ms->conn_tgt);
1771 dumpslog(ms);
1772 #endif /* MESH_DBG */
1773 } else if (cmd && cmd->request_bufflen != 0 &&
1774 ms->data_ptr > cmd->request_bufflen) {
1775 printk(KERN_DEBUG "mesh: target %d overrun, "
1776 "data_ptr=%x total=%x goes_out=%d\n",
1777 ms->conn_tgt, ms->data_ptr, cmd->request_bufflen,
1778 ms->tgts[ms->conn_tgt].data_goes_out);
1779 }
1780 ms->dma_started = 0;
1781 }
1782
1783 /*
1784 * Work out whether we expect data to go out from the host adaptor or into it.
1785 * (If this information is available from somewhere else in the scsi
1786 * code, somebody please let me know :-)
1787 */
1788 static int
1789 data_goes_out(Scsi_Cmnd *cmd)
1790 {
1791 switch (cmd->cmnd[0]) {
1792 case CHANGE_DEFINITION:
1793 case COMPARE:
1794 case COPY:
1795 case COPY_VERIFY:
1796 case FORMAT_UNIT:
1797 case LOG_SELECT:
1798 case MEDIUM_SCAN:
1799 case MODE_SELECT:
1800 case MODE_SELECT_10:
1801 case REASSIGN_BLOCKS:
1802 case RESERVE:
1803 case SEARCH_EQUAL:
1804 case SEARCH_EQUAL_12:
1805 case SEARCH_HIGH:
1806 case SEARCH_HIGH_12:
1807 case SEARCH_LOW:
1808 case SEARCH_LOW_12:
1809 case SEND_DIAGNOSTIC:
1810 case SEND_VOLUME_TAG:
1811 case SET_WINDOW:
1812 case UPDATE_BLOCK:
1813 case WRITE_BUFFER:
1814 case WRITE_6:
1815 case WRITE_10:
1816 case WRITE_12:
1817 case WRITE_LONG:
1818 case WRITE_LONG_2: /* alternate code for WRITE_LONG */
1819 case WRITE_SAME:
1820 case WRITE_VERIFY:
1821 case WRITE_VERIFY_12:
1822 return 1;
1823 default:
1824 return 0;
1825 }
1826 }
1827
1828 #ifdef MESH_DBG
1829 static inline u32 readtb(void)
1830 {
1831 u32 tb;
1832
1833 #ifdef DBG_USE_TB
1834 /* Beware: if you enable this, it will crash on 601s. */
1835 asm ("mftb %0" : "=r" (tb) : );
1836 #else
1837 tb = 0;
1838 #endif
1839 return tb;
1840 }
1841
1842 static void dlog(struct mesh_state *ms, char *fmt, int a)
1843 {
1844 struct mesh_target *tp = &ms->tgts[ms->conn_tgt];
1845 struct dbglog *tlp, *slp;
1846
1847 tlp = &tp->log[tp->log_ix];
1848 slp = &ms->log[ms->log_ix];
1849 tlp->fmt = fmt;
1850 tlp->tb = readtb();
1851 tlp->phase = (ms->msgphase << 4) + ms->phase;
1852 tlp->bs0 = ms->mesh->bus_status0;
1853 tlp->bs1 = ms->mesh->bus_status1;
1854 tlp->tgt = ms->conn_tgt;
1855 tlp->d = a;
1856 *slp = *tlp;
1857 if (++tp->log_ix >= N_DBG_LOG)
1858 tp->log_ix = 0;
1859 if (tp->n_log < N_DBG_LOG)
1860 ++tp->n_log;
1861 if (++ms->log_ix >= N_DBG_SLOG)
1862 ms->log_ix = 0;
1863 if (ms->n_log < N_DBG_SLOG)
1864 ++ms->n_log;
1865 }
1866
1867 static void dumplog(struct mesh_state *ms, int t)
1868 {
1869 struct mesh_target *tp = &ms->tgts[t];
1870 struct dbglog *lp;
1871 int i;
1872
1873 if (tp->n_log == 0)
1874 return;
1875 i = tp->log_ix - tp->n_log;
1876 if (i < 0)
1877 i += N_DBG_LOG;
1878 tp->n_log = 0;
1879 do {
1880 lp = &tp->log[i];
1881 printk(KERN_DEBUG "mesh log %d: bs=%.2x%.2x ph=%.2x ",
1882 t, lp->bs1, lp->bs0, lp->phase);
1883 #ifdef DBG_USE_TB
1884 printk("tb=%10u ", lp->tb);
1885 #endif
1886 printk(lp->fmt, lp->d);
1887 printk("\n");
1888 if (++i >= N_DBG_LOG)
1889 i = 0;
1890 } while (i != tp->log_ix);
1891 }
1892
1893 static void dumpslog(struct mesh_state *ms)
1894 {
1895 struct dbglog *lp;
1896 int i;
1897
1898 if (ms->n_log == 0)
1899 return;
1900 i = ms->log_ix - ms->n_log;
1901 if (i < 0)
1902 i += N_DBG_SLOG;
1903 ms->n_log = 0;
1904 do {
1905 lp = &ms->log[i];
1906 printk(KERN_DEBUG "mesh log: bs=%.2x%.2x ph=%.2x t%d ",
1907 lp->bs1, lp->bs0, lp->phase, lp->tgt);
1908 #ifdef DBG_USE_TB
1909 printk("tb=%10u ", lp->tb);
1910 #endif
1911 printk(lp->fmt, lp->d);
1912 printk("\n");
1913 if (++i >= N_DBG_SLOG)
1914 i = 0;
1915 } while (i != ms->log_ix);
1916 }
1917 #endif /* MESH_DBG */
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