2 * $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
4 * PCI Bus Services, see include/linux/pci.h for further explanation.
6 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
9 * Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
12 #include <linux/types.h>
13 #include <linux/kernel.h>
14 #include <linux/pci.h>
15 #include <linux/string.h>
16 #include <linux/init.h>
17 #include <linux/malloc.h>
18 #include <linux/ioport.h>
26 #define DBG(x...) printk(x)
31 struct pci_bus
*pci_root
;
32 struct pci_dev
*pci_devices
= NULL
;
33 static struct pci_dev
**pci_last_dev_p
= &pci_devices
;
34 static int pci_reverse __initdata
= 0;
37 pci_find_slot(unsigned int bus
, unsigned int devfn
)
41 for(dev
=pci_devices
; dev
; dev
=dev
->next
)
42 if (dev
->bus
->number
== bus
&& dev
->devfn
== devfn
)
49 pci_find_subsys(unsigned int vendor
, unsigned int device
,
50 unsigned int ss_vendor
, unsigned int ss_device
,
61 if ((vendor
== PCI_ANY_ID
|| dev
->vendor
== vendor
) &&
62 (device
== PCI_ANY_ID
|| dev
->device
== device
) &&
63 (ss_vendor
== PCI_ANY_ID
|| dev
->subsystem_vendor
== ss_vendor
) &&
64 (ss_device
== PCI_ANY_ID
|| dev
->subsystem_device
== ss_device
))
73 pci_find_device(unsigned int vendor
, unsigned int device
, struct pci_dev
*from
)
75 return pci_find_subsys(vendor
, device
, PCI_ANY_ID
, PCI_ANY_ID
, from
);
80 pci_find_class(unsigned int class, struct pci_dev
*from
)
86 while (from
&& from
->class != class)
93 pci_find_capability(struct pci_dev
*dev
, int cap
)
99 pci_read_config_word(dev
, PCI_STATUS
, &status
);
100 if (!(status
& PCI_STATUS_CAP_LIST
))
102 pci_read_config_byte(dev
, PCI_CAPABILITY_LIST
, &pos
);
103 while (ttl
-- && pos
>= 0x40) {
105 pci_read_config_byte(dev
, pos
+ PCI_CAP_LIST_ID
, &id
);
110 pci_read_config_byte(dev
, pos
+ PCI_CAP_LIST_NEXT
, &pos
);
117 * For given resource region of given device, return the resource
118 * region of parent bus the given region is contained in or where
119 * it should be allocated from.
122 pci_find_parent_resource(struct pci_dev
*dev
, struct resource
*res
)
124 struct pci_bus
*bus
= dev
->bus
;
126 struct resource
*best
= NULL
;
130 struct resource
*r
= bus
->resource
[i
];
133 if (res
->start
&& !(res
->start
>= r
->start
&& res
->end
<= r
->end
))
134 continue; /* Not contained */
135 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
136 continue; /* Wrong type */
137 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
))
138 return r
; /* Exact match */
139 if ((res
->flags
& IORESOURCE_PREFETCH
) && !(r
->flags
& IORESOURCE_PREFETCH
))
140 best
= r
; /* Approximating prefetchable by non-prefetchable */
146 printk(KERN_ERR
"PCI: Bug: Parent resource not found!\n");
152 * This interrupt-safe spinlock protects all accesses to PCI
153 * configuration space.
156 static spinlock_t pci_lock
= SPIN_LOCK_UNLOCKED
;
159 * Wrappers for all PCI configuration access functions. They just check
160 * alignment, do locking and call the low-level functions pointed to
164 #define PCI_byte_BAD 0
165 #define PCI_word_BAD (pos & 1)
166 #define PCI_dword_BAD (pos & 3)
168 #define PCI_OP(rw,size,type) \
169 int pci_##rw##_config_##size (struct pci_dev *dev, int pos, type value) \
172 unsigned long flags; \
173 if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
174 spin_lock_irqsave(&pci_lock, flags); \
175 res = dev->bus->ops->rw##_##size(dev, pos, value); \
176 spin_unlock_irqrestore(&pci_lock, flags); \
180 PCI_OP(read
, byte
, u8
*)
181 PCI_OP(read
, word
, u16
*)
182 PCI_OP(read
, dword
, u32
*)
183 PCI_OP(write
, byte
, u8
)
184 PCI_OP(write
, word
, u16
)
185 PCI_OP(write
, dword
, u32
)
189 pci_set_master(struct pci_dev
*dev
)
194 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
195 if (! (cmd
& PCI_COMMAND_MASTER
)) {
196 printk("PCI: Enabling bus mastering for device %s\n", dev
->name
);
197 cmd
|= PCI_COMMAND_MASTER
;
198 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
200 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &lat
);
202 printk("PCI: Increasing latency timer of device %s to 64\n", dev
->name
);
203 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 64);
208 * Assign new address to PCI resource. We hope our resource information
209 * is complete. On the PC, we don't re-assign resources unless we are
210 * forced to do so or the driver asks us to.
212 * Expects start=0, end=size-1, flags=resource type.
214 int __init
pci_assign_resource(struct pci_dev
*dev
, int i
)
216 struct resource
*r
= &dev
->resource
[i
];
217 struct resource
*pr
= pci_find_parent_resource(dev
, r
);
218 unsigned long size
= r
->end
+ 1;
222 if (r
->flags
& IORESOURCE_IO
) {
225 if (allocate_resource(pr
, r
, size
, 0x1000, ~0, 1024))
228 if (allocate_resource(pr
, r
, size
, 0x10000000, ~0, size
))
232 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ 4*i
, r
->start
);
237 * Translate the low bits of the PCI base
238 * to the resource type
240 static inline unsigned int pci_resource_flags(unsigned int flags
)
242 if (flags
& PCI_BASE_ADDRESS_SPACE_IO
)
243 return IORESOURCE_IO
;
245 if (flags
& PCI_BASE_ADDRESS_MEM_PREFETCH
)
246 return IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
248 return IORESOURCE_MEM
;
251 void __init
pci_read_bases(struct pci_dev
*dev
, unsigned int howmany
, int rom
)
253 unsigned int pos
, reg
, next
;
256 struct resource
*res
;
258 /* Disable IO and memory while we fiddle */
259 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
260 tmp
= cmd
& ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
);
261 pci_write_config_word(dev
, PCI_COMMAND
, tmp
);
263 for(pos
=0; pos
<howmany
; pos
= next
) {
265 res
= &dev
->resource
[pos
];
266 res
->name
= dev
->name
;
267 reg
= PCI_BASE_ADDRESS_0
+ (pos
<< 2);
268 pci_read_config_dword(dev
, reg
, &l
);
269 pci_write_config_dword(dev
, reg
, ~0);
270 pci_read_config_dword(dev
, reg
, &sz
);
271 pci_write_config_dword(dev
, reg
, l
);
272 if (!sz
|| sz
== 0xffffffff)
276 if ((l
& PCI_BASE_ADDRESS_SPACE
) == PCI_BASE_ADDRESS_SPACE_MEMORY
) {
277 res
->start
= l
& PCI_BASE_ADDRESS_MEM_MASK
;
278 sz
= ~(sz
& PCI_BASE_ADDRESS_MEM_MASK
);
280 res
->start
= l
& PCI_BASE_ADDRESS_IO_MASK
;
281 sz
= ~(sz
& PCI_BASE_ADDRESS_IO_MASK
) & 0xffff;
283 res
->end
= res
->start
+ (unsigned long) sz
;
284 res
->flags
|= (l
& 0xf) | pci_resource_flags(l
);
285 if ((l
& (PCI_BASE_ADDRESS_SPACE
| PCI_BASE_ADDRESS_MEM_TYPE_MASK
))
286 == (PCI_BASE_ADDRESS_SPACE_MEMORY
| PCI_BASE_ADDRESS_MEM_TYPE_64
)) {
287 pci_read_config_dword(dev
, reg
+4, &l
);
289 #if BITS_PER_LONG == 64
290 res
->start
|= ((unsigned long) l
) << 32;
291 res
->end
= res
->start
+ sz
;
292 pci_write_config_dword(dev
, reg
+4, ~0);
293 pci_read_config_dword(dev
, reg
+4, &tmp
);
294 pci_write_config_dword(dev
, reg
+4, l
);
296 res
->end
= res
->start
+ (((unsigned long) ~l
) << 32);
299 printk(KERN_ERR
"PCI: Unable to handle 64-bit address for device %s\n", dev
->name
);
308 res
= &dev
->resource
[PCI_ROM_RESOURCE
];
309 pci_read_config_dword(dev
, rom
, &l
);
310 pci_write_config_dword(dev
, rom
, ~PCI_ROM_ADDRESS_ENABLE
);
311 pci_read_config_dword(dev
, rom
, &sz
);
312 pci_write_config_dword(dev
, rom
, l
);
315 if (sz
&& sz
!= 0xffffffff) {
316 res
->flags
= (l
& PCI_ROM_ADDRESS_ENABLE
) |
317 IORESOURCE_MEM
| IORESOURCE_PREFETCH
| IORESOURCE_READONLY
| IORESOURCE_CACHEABLE
;
318 res
->start
= l
& PCI_ROM_ADDRESS_MASK
;
319 sz
= ~(sz
& PCI_ROM_ADDRESS_MASK
);
320 res
->end
= res
->start
+ (unsigned long) sz
;
322 res
->name
= dev
->name
;
324 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
327 void __init
pci_read_bridge_bases(struct pci_dev
*dev
, struct pci_bus
*child
)
329 u8 io_base_lo
, io_limit_lo
;
330 u16 mem_base_lo
, mem_limit_lo
, io_base_hi
, io_limit_hi
;
331 u32 mem_base_hi
, mem_limit_hi
;
332 unsigned long base
, limit
;
333 struct resource
*res
;
337 child
->resource
[i
] = &dev
->resource
[PCI_BRIDGE_RESOURCES
+i
];
339 res
= child
->resource
[0];
340 pci_read_config_byte(dev
, PCI_IO_BASE
, &io_base_lo
);
341 pci_read_config_byte(dev
, PCI_IO_LIMIT
, &io_limit_lo
);
342 pci_read_config_word(dev
, PCI_IO_BASE_UPPER16
, &io_base_hi
);
343 pci_read_config_word(dev
, PCI_IO_LIMIT_UPPER16
, &io_limit_hi
);
344 base
= ((io_base_lo
& PCI_IO_RANGE_MASK
) << 8) | (io_base_hi
<< 16);
345 limit
= ((io_limit_lo
& PCI_IO_RANGE_MASK
) << 8) | (io_limit_hi
<< 16);
346 if (base
&& base
<= limit
) {
347 res
->flags
|= (io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) | IORESOURCE_IO
;
349 res
->end
= limit
+ 0xfff;
350 res
->name
= child
->name
;
353 res
= child
->resource
[1];
354 pci_read_config_word(dev
, PCI_MEMORY_BASE
, &mem_base_lo
);
355 pci_read_config_word(dev
, PCI_MEMORY_LIMIT
, &mem_limit_lo
);
356 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
357 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
358 if (base
&& base
<= limit
) {
359 res
->flags
|= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
;
361 res
->end
= limit
+ 0xfffff;
362 res
->name
= child
->name
;
365 res
= child
->resource
[2];
366 pci_read_config_word(dev
, PCI_PREF_MEMORY_BASE
, &mem_base_lo
);
367 pci_read_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, &mem_limit_lo
);
368 pci_read_config_dword(dev
, PCI_PREF_BASE_UPPER32
, &mem_base_hi
);
369 pci_read_config_dword(dev
, PCI_PREF_LIMIT_UPPER32
, &mem_limit_hi
);
370 base
= (mem_base_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
371 limit
= (mem_limit_lo
& PCI_MEMORY_RANGE_MASK
) << 16;
372 #if BITS_PER_LONG == 64
373 base
|= ((long) mem_base_hi
) << 32;
374 limit
|= ((long) mem_limit_hi
) << 32;
376 if (mem_base_hi
|| mem_limit_hi
) {
377 printk(KERN_ERR
"PCI: Unable to handle 64-bit address space for %s\n", child
->name
);
381 if (base
&& base
<= limit
) {
382 res
->flags
|= (mem_base_lo
& PCI_MEMORY_RANGE_TYPE_MASK
) | IORESOURCE_MEM
| IORESOURCE_PREFETCH
;
384 res
->end
= limit
+ 0xfffff;
385 res
->name
= child
->name
;
389 static unsigned int __init
pci_do_scan_bus(struct pci_bus
*bus
)
391 unsigned int devfn
, l
, max
, class;
392 unsigned char irq
, hdr_type
, is_multi
= 0;
393 struct pci_dev
*dev
, **bus_last
;
394 struct pci_bus
*child
;
395 struct pci_dev
*dev_cache
= NULL
;
397 DBG("pci_do_scan_bus for bus %d\n", bus
->number
);
398 bus_last
= &bus
->devices
;
399 max
= bus
->secondary
;
400 for (devfn
= 0; devfn
< 0xff; ++devfn
) {
401 if (PCI_FUNC(devfn
) && !is_multi
) {
402 /* not a multi-function device */
406 dev_cache
= kmalloc(sizeof(*dev
), GFP_KERNEL
);
411 memset(dev
, 0, sizeof(*dev
));
415 if (pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
))
417 if (!PCI_FUNC(devfn
))
418 is_multi
= hdr_type
& 0x80;
420 if (pci_read_config_dword(dev
, PCI_VENDOR_ID
, &l
) ||
421 /* some broken boards return 0 if a slot is empty: */
422 l
== 0xffffffff || l
== 0x00000000 || l
== 0x0000ffff || l
== 0xffff0000)
426 dev
->vendor
= l
& 0xffff;
427 dev
->device
= (l
>> 16) & 0xffff;
428 sprintf(dev
->name
, "%02x:%02x.%d", bus
->number
, PCI_SLOT(devfn
), PCI_FUNC(devfn
));
429 pci_name_device(dev
);
431 pci_read_config_dword(dev
, PCI_CLASS_REVISION
, &class);
432 class >>= 8; /* upper 3 bytes */
435 dev
->hdr_type
= hdr_type
;
437 switch (hdr_type
& 0x7f) { /* header type */
438 case PCI_HEADER_TYPE_NORMAL
: /* standard header */
439 if (class == PCI_CLASS_BRIDGE_PCI
)
442 * If the card generates interrupts, read IRQ number
443 * (some architectures change it during pcibios_fixup())
445 pci_read_config_byte(dev
, PCI_INTERRUPT_PIN
, &irq
);
447 pci_read_config_byte(dev
, PCI_INTERRUPT_LINE
, &irq
);
450 * read base address registers, again pcibios_fixup() can
453 pci_read_bases(dev
, 6, PCI_ROM_ADDRESS
);
454 pci_read_config_word(dev
, PCI_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
455 pci_read_config_word(dev
, PCI_SUBSYSTEM_ID
, &dev
->subsystem_device
);
457 case PCI_HEADER_TYPE_BRIDGE
: /* bridge header */
458 if (class != PCI_CLASS_BRIDGE_PCI
)
460 pci_read_bases(dev
, 2, PCI_ROM_ADDRESS1
);
462 case PCI_HEADER_TYPE_CARDBUS
: /* CardBus bridge header */
463 if (class != PCI_CLASS_BRIDGE_CARDBUS
)
465 pci_read_bases(dev
, 1, 0);
466 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_VENDOR_ID
, &dev
->subsystem_vendor
);
467 pci_read_config_word(dev
, PCI_CB_SUBSYSTEM_ID
, &dev
->subsystem_device
);
469 default: /* unknown header */
471 printk(KERN_ERR
"PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n",
472 bus
->number
, dev
->devfn
, dev
->vendor
, dev
->device
, class, hdr_type
);
476 DBG("PCI: %02x:%02x [%04x/%04x]\n", bus
->number
, dev
->devfn
, dev
->vendor
, dev
->device
);
479 * Put it into the global PCI device chain. It's used to
480 * find devices once everything is set up.
483 *pci_last_dev_p
= dev
;
484 pci_last_dev_p
= &dev
->next
;
486 dev
->next
= pci_devices
;
491 * Now insert it into the list of devices held
495 bus_last
= &dev
->sibling
;
497 /* Fix up broken headers */
498 pci_fixup_device(PCI_FIXUP_HEADER
, dev
);
502 * Setting of latency timer in case it was less than 32 was
503 * a great idea, but it confused several broken devices. Grrr.
505 pci_read_config_byte(dev
, PCI_LATENCY_TIMER
, &tmp
);
507 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 32);
514 * After performing arch-dependent fixup of the bus, look behind
515 * all PCI-to-PCI bridges on this bus.
517 pcibios_fixup_bus(bus
);
518 for(dev
=bus
->devices
; dev
; dev
=dev
->sibling
)
520 * If it's a bridge, scan the bus behind it.
522 if ((dev
->class >> 8) == PCI_CLASS_BRIDGE_PCI
) {
527 * Insert it into the tree of buses.
529 child
= kmalloc(sizeof(*child
), GFP_KERNEL
);
530 memset(child
, 0, sizeof(*child
));
531 child
->next
= bus
->children
;
532 bus
->children
= child
;
535 child
->ops
= bus
->ops
;
538 * Set up the primary, secondary and subordinate
539 * bus numbers. Read resource ranges behind the bridge.
541 child
->number
= child
->secondary
= ++max
;
542 child
->primary
= bus
->secondary
;
543 child
->subordinate
= 0xff;
544 sprintf(child
->name
, "PCI Bus #%02x", child
->number
);
546 * Clear all status bits and turn off memory,
547 * I/O and master enables.
549 pci_read_config_word(dev
, PCI_COMMAND
, &cr
);
550 pci_write_config_word(dev
, PCI_COMMAND
, 0x0000);
551 pci_write_config_word(dev
, PCI_STATUS
, 0xffff);
553 * Read the existing primary/secondary/subordinate bus
554 * number configuration to determine if the PCI bridge
555 * has already been configured by the system. If so,
556 * do not modify the configuration, merely note it.
558 pci_read_config_dword(dev
, PCI_PRIMARY_BUS
, &buses
);
559 if ((buses
& 0xFFFFFF) != 0
560 && ! pcibios_assign_all_busses())
564 child
->primary
= buses
& 0xFF;
565 child
->secondary
= (buses
>> 8) & 0xFF;
566 child
->subordinate
= (buses
>> 16) & 0xFF;
567 child
->number
= child
->secondary
;
568 cmax
= pci_do_scan_bus(child
);
569 if (cmax
> max
) max
= cmax
;
574 * Configure the bus numbers for this bridge:
578 (((unsigned int)(child
->primary
) << 0) |
579 ((unsigned int)(child
->secondary
) << 8) |
580 ((unsigned int)(child
->subordinate
) << 16));
581 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
583 * Now we can scan all subordinate buses:
585 max
= pci_do_scan_bus(child
);
587 * Set the subordinate bus number to its real
590 child
->subordinate
= max
;
591 buses
= (buses
& 0xff00ffff)
592 | ((unsigned int)(child
->subordinate
) << 16);
593 pci_write_config_dword(dev
, PCI_PRIMARY_BUS
, buses
);
595 pci_write_config_word(dev
, PCI_COMMAND
, cr
);
599 * We've scanned the bus and so we know all about what's on
600 * the other side of any bridges that may be on this bus plus
603 * Return how far we've got finding sub-buses.
605 DBG("PCI: pci_do_scan_bus returning with max=%02x\n", max
);
609 static int __init
pci_bus_exists(struct pci_bus
*b
, int nr
)
614 if (b
->children
&& pci_bus_exists(b
->children
, nr
))
621 struct pci_bus
* __init
pci_scan_bus(int bus
, struct pci_ops
*ops
, void *sysdata
)
623 struct pci_bus
*b
, **r
;
625 if (pci_bus_exists(pci_root
, bus
)) {
626 /* If we already got to this bus through a different bridge, ignore it */
627 DBG("PCI: Bus %02x already known\n", bus
);
631 b
= kmalloc(sizeof(*b
), GFP_KERNEL
);
632 memset(b
, 0, sizeof(*b
));
634 /* Put the new bus at the end of the chain of busses. */
640 b
->number
= b
->secondary
= bus
;
641 b
->sysdata
= sysdata
;
643 b
->resource
[0] = &ioport_resource
;
644 b
->resource
[1] = &iomem_resource
;
645 b
->subordinate
= pci_do_scan_bus(b
);
649 void __init
pci_init(void)
655 for(dev
=pci_devices
; dev
; dev
=dev
->next
)
656 pci_fixup_device(PCI_FIXUP_FINAL
, dev
);
659 static int __init
pci_setup(char *str
)
662 char *k
= strchr(str
, ',');
665 if (*str
&& (str
= pcibios_setup(str
)) && *str
) {
666 if (!strcmp(str
, "reverse"))
668 else printk(KERN_ERR
"PCI: Unknown option `%s'\n", str
);
675 __setup("pci=", pci_setup
);