drivers/pci/pci.c

   1 /*
   2  *      $Id: pci.c,v 1.91 1999/01/21 13:34:01 davem Exp $
   3  *
   4  *      PCI Bus Services, see include/linux/pci.h for further explanation.
   5  *
   6  *      Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
   7  *      David Mosberger-Tang
   8  *
   9  *      Copyright 1997 -- 1999 Martin Mares <mj@atrey.karlin.mff.cuni.cz>
  10  */
  11
  12 #include <linux/types.h>
  13 #include <linux/kernel.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/init.h>
  17 #include <linux/malloc.h>
  18 #include <linux/ioport.h>
  19
  20 #include <asm/pci.h>
  21 #include <asm/page.h>
  22
  23 #undef DEBUG
  24
  25 #ifdef DEBUG
  26 #define DBG(x...) printk(x)
  27 #else
  28 #define DBG(x...)
  29 #endif
  30
  31 struct pci_bus *pci_root;
  32 struct pci_dev *pci_devices = NULL;
  33 static struct pci_dev **pci_last_dev_p = &pci_devices;
  34 static int pci_reverse __initdata = 0;
  35
  36 struct pci_dev *
  37 pci_find_slot(unsigned int bus, unsigned int devfn)
  38 {
  39         struct pci_dev *dev;
  40
  41         for(dev=pci_devices; dev; dev=dev->next)
  42                 if (dev->bus->number == bus && dev->devfn == devfn)
  43                         break;
  44         return dev;
  45 }
  46
  47
  48 struct pci_dev *
  49 pci_find_subsys(unsigned int vendor, unsigned int device,
  50                 unsigned int ss_vendor, unsigned int ss_device,
  51                 struct pci_dev *from)
  52 {
  53         struct pci_dev *dev;
  54
  55         if (from)
  56                 dev = from->next;
  57         else
  58                 dev = pci_devices;
  59
  60         while (dev) {
  61                 if ((vendor == PCI_ANY_ID || dev->vendor == vendor) &&
  62                     (device == PCI_ANY_ID || dev->device == device) &&
  63                     (ss_vendor == PCI_ANY_ID || dev->subsystem_vendor == ss_vendor) &&
  64                     (ss_device == PCI_ANY_ID || dev->subsystem_device == ss_device))
  65                         return dev;
  66                 dev = dev->next;
  67         }
  68         return NULL;
  69 }
  70
  71
  72 struct pci_dev *
  73 pci_find_device(unsigned int vendor, unsigned int device, struct pci_dev *from)
  74 {
  75         return pci_find_subsys(vendor, device, PCI_ANY_ID, PCI_ANY_ID, from);
  76 }
  77
  78
  79 struct pci_dev *
  80 pci_find_class(unsigned int class, struct pci_dev *from)
  81 {
  82         if (!from)
  83                 from = pci_devices;
  84         else
  85                 from = from->next;
  86         while (from && from->class != class)
  87                 from = from->next;
  88         return from;
  89 }
  90
  91
  92 int
  93 pci_find_capability(struct pci_dev *dev, int cap)
  94 {
  95         u16 status;
  96         u8 pos, id;
  97         int ttl = 48;
  98
  99         pci_read_config_word(dev, PCI_STATUS, &status);
 100         if (!(status & PCI_STATUS_CAP_LIST))
 101                 return 0;
 102         pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos);
 103         while (ttl-- && pos >= 0x40) {
 104                 pos &= ~3;
 105                 pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id);
 106                 if (id == 0xff)
 107                         break;
 108                 if (id == cap)
 109                         return pos;
 110                 pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos);
 111         }
 112         return 0;
 113 }
 114
 115
 116 /*
 117  *  For given resource region of given device, return the resource
 118  *  region of parent bus the given region is contained in or where
 119  *  it should be allocated from.
 120  */
 121 struct resource *
 122 pci_find_parent_resource(struct pci_dev *dev, struct resource *res)
 123 {
 124         struct pci_bus *bus = dev->bus;
 125         int i;
 126         struct resource *best = NULL;
 127
 128         while (bus) {
 129                 for(i=0; i<4; i++) {
 130                         struct resource *r = bus->resource[i];
 131                         if (!r)
 132                                 continue;
 133                         if (res->start && !(res->start >= r->start && res->end <= r->end))
 134                                 continue;       /* Not contained */
 135                         if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM))
 136                                 continue;       /* Wrong type */
 137                         if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH))
 138                                 return r;       /* Exact match */
 139                         if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH))
 140                                 best = r;       /* Approximating prefetchable by non-prefetchable */
 141                 }
 142                 if (best)
 143                         return best;
 144                 bus = bus->parent;
 145         }
 146         printk(KERN_ERR "PCI: Bug: Parent resource not found!\n");
 147         return NULL;
 148 }
 149
 150
 151 /*
 152  * This interrupt-safe spinlock protects all accesses to PCI
 153  * configuration space.
 154  */
 155
 156 static spinlock_t pci_lock = SPIN_LOCK_UNLOCKED;
 157
 158 /*
 159  *  Wrappers for all PCI configuration access functions.  They just check
 160  *  alignment, do locking and call the low-level functions pointed to
 161  *  by pci_dev->ops.
 162  */
 163
 164 #define PCI_byte_BAD 0
 165 #define PCI_word_BAD (pos & 1)
 166 #define PCI_dword_BAD (pos & 3)
 167
 168 #define PCI_OP(rw,size,type) \
 169 int pci_##rw##_config_##size (struct pci_dev *dev, int pos, type value) \
 170 {                                                                       \
 171         int res;                                                        \
 172         unsigned long flags;                                            \
 173         if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER;       \
 174         spin_lock_irqsave(&pci_lock, flags);                            \
 175         res = dev->bus->ops->rw##_##size(dev, pos, value);              \
 176         spin_unlock_irqrestore(&pci_lock, flags);                       \
 177         return res;                                                     \
 178 }
 179
 180 PCI_OP(read, byte, u8 *)
 181 PCI_OP(read, word, u16 *)
 182 PCI_OP(read, dword, u32 *)
 183 PCI_OP(write, byte, u8)
 184 PCI_OP(write, word, u16)
 185 PCI_OP(write, dword, u32)
 186
 187
 188 void
 189 pci_set_master(struct pci_dev *dev)
 190 {
 191         u16 cmd;
 192         u8 lat;
 193
 194         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 195         if (! (cmd & PCI_COMMAND_MASTER)) {
 196                 printk("PCI: Enabling bus mastering for device %s\n", dev->name);
 197                 cmd |= PCI_COMMAND_MASTER;
 198                 pci_write_config_word(dev, PCI_COMMAND, cmd);
 199         }
 200         pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
 201         if (lat < 16) {
 202                 printk("PCI: Increasing latency timer of device %s to 64\n", dev->name);
 203                 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
 204         }
 205 }
 206
 207 /*
 208  * Assign new address to PCI resource.  We hope our resource information
 209  * is complete.  On the PC, we don't re-assign resources unless we are
 210  * forced to do so or the driver asks us to.
 211  *
 212  * Expects start=0, end=size-1, flags=resource type.
 213  */
 214 int __init pci_assign_resource(struct pci_dev *dev, int i)
 215 {
 216         struct resource *r = &dev->resource[i];
 217         struct resource *pr = pci_find_parent_resource(dev, r);
 218         unsigned long size = r->end + 1;
 219
 220         if (!pr)
 221                 return -EINVAL;
 222         if (r->flags & IORESOURCE_IO) {
 223                 if (size > 0x100)
 224                         return -EFBIG;
 225                 if (allocate_resource(pr, r, size, 0x1000, ~0, 1024))
 226                         return -EBUSY;
 227         } else {
 228                 if (allocate_resource(pr, r, size, 0x10000000, ~0, size))
 229                         return -EBUSY;
 230         }
 231         if (i < 6)
 232                 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4*i, r->start);
 233         return 0;
 234 }
 235
 236 /*
 237  * Translate the low bits of the PCI base
 238  * to the resource type
 239  */
 240 static inline unsigned int pci_resource_flags(unsigned int flags)
 241 {
 242         if (flags & PCI_BASE_ADDRESS_SPACE_IO)
 243                 return IORESOURCE_IO;
 244
 245         if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
 246                 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
 247
 248         return IORESOURCE_MEM;
 249 }
 250
 251 void __init pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
 252 {
 253         unsigned int pos, reg, next;
 254         u32 l, sz, tmp;
 255         u16 cmd;
 256         struct resource *res;
 257
 258         /* Disable IO and memory while we fiddle */
 259         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 260         tmp = cmd & ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
 261         pci_write_config_word(dev, PCI_COMMAND, tmp);
 262
 263         for(pos=0; pos<howmany; pos = next) {
 264                 next = pos+1;
 265                 res = &dev->resource[pos];
 266                 res->name = dev->name;
 267                 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
 268                 pci_read_config_dword(dev, reg, &l);
 269                 pci_write_config_dword(dev, reg, ~0);
 270                 pci_read_config_dword(dev, reg, &sz);
 271                 pci_write_config_dword(dev, reg, l);
 272                 if (!sz || sz == 0xffffffff)
 273                         continue;
 274                 if (l == 0xffffffff)
 275                         l = 0;
 276                 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
 277                         res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
 278                         sz = ~(sz & PCI_BASE_ADDRESS_MEM_MASK);
 279                 } else {
 280                         res->start = l & PCI_BASE_ADDRESS_IO_MASK;
 281                         sz = ~(sz & PCI_BASE_ADDRESS_IO_MASK) & 0xffff;
 282                 }
 283                 res->end = res->start + (unsigned long) sz;
 284                 res->flags |= (l & 0xf) | pci_resource_flags(l);
 285                 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
 286                     == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
 287                         pci_read_config_dword(dev, reg+4, &l);
 288                         next++;
 289 #if BITS_PER_LONG == 64
 290                         res->start |= ((unsigned long) l) << 32;
 291                         res->end = res->start + sz;
 292                         pci_write_config_dword(dev, reg+4, ~0);
 293                         pci_read_config_dword(dev, reg+4, &tmp);
 294                         pci_write_config_dword(dev, reg+4, l);
 295                         if (l)
 296                                 res->end = res->start + (((unsigned long) ~l) << 32);
 297 #else
 298                         if (l) {
 299                                 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", dev->name);
 300                                 res->start = 0;
 301                                 res->flags = 0;
 302                                 continue;
 303                         }
 304 #endif
 305                 }
 306         }
 307         if (rom) {
 308                 res = &dev->resource[PCI_ROM_RESOURCE];
 309                 pci_read_config_dword(dev, rom, &l);
 310                 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
 311                 pci_read_config_dword(dev, rom, &sz);
 312                 pci_write_config_dword(dev, rom, l);
 313                 if (l == 0xffffffff)
 314                         l = 0;
 315                 if (sz && sz != 0xffffffff) {
 316                         res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
 317                           IORESOURCE_MEM | IORESOURCE_PREFETCH | IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
 318                         res->start = l & PCI_ROM_ADDRESS_MASK;
 319                         sz = ~(sz & PCI_ROM_ADDRESS_MASK);
 320                         res->end = res->start + (unsigned long) sz;
 321                 }
 322                 res->name = dev->name;
 323         }
 324         pci_write_config_word(dev, PCI_COMMAND, cmd);
 325 }
 326
 327 void __init pci_read_bridge_bases(struct pci_dev *dev, struct pci_bus *child)
 328 {
 329         u8 io_base_lo, io_limit_lo;
 330         u16 mem_base_lo, mem_limit_lo, io_base_hi, io_limit_hi;
 331         u32 mem_base_hi, mem_limit_hi;
 332         unsigned long base, limit;
 333         struct resource *res;
 334         int i;
 335
 336         for(i=0; i<3; i++)
 337                 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
 338
 339         res = child->resource[0];
 340         pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
 341         pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
 342         pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
 343         pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
 344         base = ((io_base_lo & PCI_IO_RANGE_MASK) << 8) | (io_base_hi << 16);
 345         limit = ((io_limit_lo & PCI_IO_RANGE_MASK) << 8) | (io_limit_hi << 16);
 346         if (base && base <= limit) {
 347                 res->flags |= (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
 348                 res->start = base;
 349                 res->end = limit + 0xfff;
 350                 res->name = child->name;
 351         }
 352
 353         res = child->resource[1];
 354         pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
 355         pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
 356         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 357         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 358         if (base && base <= limit) {
 359                 res->flags |= (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
 360                 res->start = base;
 361                 res->end = limit + 0xfffff;
 362                 res->name = child->name;
 363         }
 364
 365         res = child->resource[2];
 366         pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
 367         pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
 368         pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
 369         pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
 370         base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
 371         limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
 372 #if BITS_PER_LONG == 64
 373         base |= ((long) mem_base_hi) << 32;
 374         limit |= ((long) mem_limit_hi) << 32;
 375 #else
 376         if (mem_base_hi || mem_limit_hi) {
 377                 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name);
 378                 return;
 379         }
 380 #endif
 381         if (base && base <= limit) {
 382                 res->flags |= (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
 383                 res->start = base;
 384                 res->end = limit + 0xfffff;
 385                 res->name = child->name;
 386         }
 387 }
 388
 389 static unsigned int __init pci_do_scan_bus(struct pci_bus *bus)
 390 {
 391         unsigned int devfn, l, max, class;
 392         unsigned char irq, hdr_type, is_multi = 0;
 393         struct pci_dev *dev, **bus_last;
 394         struct pci_bus *child;
 395         struct pci_dev *dev_cache = NULL;
 396
 397         DBG("pci_do_scan_bus for bus %d\n", bus->number);
 398         bus_last = &bus->devices;
 399         max = bus->secondary;
 400         for (devfn = 0; devfn < 0xff; ++devfn) {
 401                 if (PCI_FUNC(devfn) && !is_multi) {
 402                         /* not a multi-function device */
 403                         continue;
 404                 }
 405                 if (!dev_cache) {
 406                         dev_cache = kmalloc(sizeof(*dev), GFP_KERNEL);
 407                         if (!dev_cache)
 408                                 continue;
 409                 }
 410                 dev = dev_cache;
 411                 memset(dev, 0, sizeof(*dev));
 412                 dev->bus = bus;
 413                 dev->devfn  = devfn;
 414
 415                 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
 416                         continue;
 417                 if (!PCI_FUNC(devfn))
 418                         is_multi = hdr_type & 0x80;
 419
 420                 if (pci_read_config_dword(dev, PCI_VENDOR_ID, &l) ||
 421                     /* some broken boards return 0 if a slot is empty: */
 422                     l == 0xffffffff || l == 0x00000000 || l == 0x0000ffff || l == 0xffff0000)
 423                         continue;
 424
 425                 dev_cache = NULL;
 426                 dev->vendor = l & 0xffff;
 427                 dev->device = (l >> 16) & 0xffff;
 428                 sprintf(dev->name, "%02x:%02x.%d", bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
 429                 pci_name_device(dev);
 430
 431                 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
 432                 class >>= 8;                                /* upper 3 bytes */
 433                 dev->class = class;
 434                 class >>= 8;
 435                 dev->hdr_type = hdr_type;
 436
 437                 switch (hdr_type & 0x7f) {                  /* header type */
 438                 case PCI_HEADER_TYPE_NORMAL:                /* standard header */
 439                         if (class == PCI_CLASS_BRIDGE_PCI)
 440                                 goto bad;
 441                         /*
 442                          * If the card generates interrupts, read IRQ number
 443                          * (some architectures change it during pcibios_fixup())
 444                          */
 445                         pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
 446                         if (irq)
 447                                 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
 448                         dev->irq = irq;
 449                         /*
 450                          * read base address registers, again pcibios_fixup() can
 451                          * tweak these
 452                          */
 453                         pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
 454                         pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 455                         pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
 456                         break;
 457                 case PCI_HEADER_TYPE_BRIDGE:                /* bridge header */
 458                         if (class != PCI_CLASS_BRIDGE_PCI)
 459                                 goto bad;
 460                         pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
 461                         break;
 462                 case PCI_HEADER_TYPE_CARDBUS:               /* CardBus bridge header */
 463                         if (class != PCI_CLASS_BRIDGE_CARDBUS)
 464                                 goto bad;
 465                         pci_read_bases(dev, 1, 0);
 466                         pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
 467                         pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
 468                         break;
 469                 default:                                    /* unknown header */
 470                 bad:
 471                         printk(KERN_ERR "PCI: %02x:%02x [%04x/%04x/%06x] has unknown header type %02x, ignoring.\n",
 472                                bus->number, dev->devfn, dev->vendor, dev->device, class, hdr_type);
 473                         continue;
 474                 }
 475
 476                 DBG("PCI: %02x:%02x [%04x/%04x]\n", bus->number, dev->devfn, dev->vendor, dev->device);
 477
 478                 /*
 479                  * Put it into the global PCI device chain. It's used to
 480                  * find devices once everything is set up.
 481                  */
 482                 if (!pci_reverse) {
 483                         *pci_last_dev_p = dev;
 484                         pci_last_dev_p = &dev->next;
 485                 } else {
 486                         dev->next = pci_devices;
 487                         pci_devices = dev;
 488                 }
 489
 490                 /*
 491                  * Now insert it into the list of devices held
 492                  * by the parent bus.
 493                  */
 494                 *bus_last = dev;
 495                 bus_last = &dev->sibling;
 496
 497                 /* Fix up broken headers */
 498                 pci_fixup_device(PCI_FIXUP_HEADER, dev);
 499
 500 #if 0
 501                 /*
 502                  * Setting of latency timer in case it was less than 32 was
 503                  * a great idea, but it confused several broken devices. Grrr.
 504                  */
 505                 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &tmp);
 506                 if (tmp < 32)
 507                         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
 508 #endif
 509         }
 510         if (dev_cache)
 511                 kfree(dev_cache);
 512
 513         /*
 514          * After performing arch-dependent fixup of the bus, look behind
 515          * all PCI-to-PCI bridges on this bus.
 516          */
 517         pcibios_fixup_bus(bus);
 518         for(dev=bus->devices; dev; dev=dev->sibling)
 519                 /*
 520                  * If it's a bridge, scan the bus behind it.
 521                  */
 522                 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 523                         unsigned int buses;
 524                         unsigned short cr;
 525
 526                         /*
 527                          * Insert it into the tree of buses.
 528                          */
 529                         child = kmalloc(sizeof(*child), GFP_KERNEL);
 530                         memset(child, 0, sizeof(*child));
 531                         child->next = bus->children;
 532                         bus->children = child;
 533                         child->self = dev;
 534                         child->parent = bus;
 535                         child->ops = bus->ops;
 536
 537                         /*
 538                          * Set up the primary, secondary and subordinate
 539                          * bus numbers.  Read resource ranges behind the bridge.
 540                          */
 541                         child->number = child->secondary = ++max;
 542                         child->primary = bus->secondary;
 543                         child->subordinate = 0xff;
 544                         sprintf(child->name, "PCI Bus #%02x", child->number);
 545                         /*
 546                          * Clear all status bits and turn off memory,
 547                          * I/O and master enables.
 548                          */
 549                         pci_read_config_word(dev, PCI_COMMAND, &cr);
 550                         pci_write_config_word(dev, PCI_COMMAND, 0x0000);
 551                         pci_write_config_word(dev, PCI_STATUS, 0xffff);
 552                         /*
 553                          * Read the existing primary/secondary/subordinate bus
 554                          * number configuration to determine if the PCI bridge
 555                          * has already been configured by the system.  If so,
 556                          * do not modify the configuration, merely note it.
 557                          */
 558                         pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
 559                         if ((buses & 0xFFFFFF) != 0
 560                             && ! pcibios_assign_all_busses())
 561                           {
 562                             unsigned int cmax;
 563
 564                             child->primary = buses & 0xFF;
 565                             child->secondary = (buses >> 8) & 0xFF;
 566                             child->subordinate = (buses >> 16) & 0xFF;
 567                             child->number = child->secondary;
 568                             cmax = pci_do_scan_bus(child);
 569                             if (cmax > max) max = cmax;
 570                           }
 571                         else
 572                           {
 573                             /*
 574                              * Configure the bus numbers for this bridge:
 575                              */
 576                             buses &= 0xff000000;
 577                             buses |=
 578                               (((unsigned int)(child->primary)     <<  0) |
 579                                ((unsigned int)(child->secondary)   <<  8) |
 580                                ((unsigned int)(child->subordinate) << 16));
 581                             pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 582                             /*
 583                              * Now we can scan all subordinate buses:
 584                              */
 585                             max = pci_do_scan_bus(child);
 586                             /*
 587                              * Set the subordinate bus number to its real
 588                              * value:
 589                              */
 590                             child->subordinate = max;
 591                             buses = (buses & 0xff00ffff)
 592                               | ((unsigned int)(child->subordinate) << 16);
 593                             pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
 594                           }
 595                         pci_write_config_word(dev, PCI_COMMAND, cr);
 596                 }
 597
 598         /*
 599          * We've scanned the bus and so we know all about what's on
 600          * the other side of any bridges that may be on this bus plus
 601          * any devices.
 602          *
 603          * Return how far we've got finding sub-buses.
 604          */
 605         DBG("PCI: pci_do_scan_bus returning with max=%02x\n", max);
 606         return max;
 607 }
 608
 609 static int __init pci_bus_exists(struct pci_bus *b, int nr)
 610 {
 611         while (b) {
 612                 if (b->number == nr)
 613                         return 1;
 614                 if (b->children && pci_bus_exists(b->children, nr))
 615                         return 1;
 616                 b = b->next;
 617         }
 618         return 0;
 619 }
 620
 621 struct pci_bus * __init pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata)
 622 {
 623         struct pci_bus *b, **r;
 624
 625         if (pci_bus_exists(pci_root, bus)) {
 626                 /* If we already got to this bus through a different bridge, ignore it */
 627                 DBG("PCI: Bus %02x already known\n", bus);
 628                 return NULL;
 629         }
 630
 631         b = kmalloc(sizeof(*b), GFP_KERNEL);
 632         memset(b, 0, sizeof(*b));
 633
 634         /* Put the new bus at the end of the chain of busses.  */
 635         r = &pci_root;
 636         while (*r)
 637                 r = &(*r)->next;
 638         *r = b;
 639
 640         b->number = b->secondary = bus;
 641         b->sysdata = sysdata;
 642         b->ops = ops;
 643         b->resource[0] = &ioport_resource;
 644         b->resource[1] = &iomem_resource;
 645         b->subordinate = pci_do_scan_bus(b);
 646         return b;
 647 }
 648
 649 void __init pci_init(void)
 650 {
 651         struct pci_dev *dev;
 652
 653         pcibios_init();
 654
 655         for(dev=pci_devices; dev; dev=dev->next)
 656                 pci_fixup_device(PCI_FIXUP_FINAL, dev);
 657 }
 658
 659 static int __init pci_setup(char *str)
 660 {
 661         while (str) {
 662                 char *k = strchr(str, ',');
 663                 if (k)
 664                         *k++ = 0;
 665                 if (*str && (str = pcibios_setup(str)) && *str) {
 666                         if (!strcmp(str, "reverse"))
 667                                 pci_reverse = 1;
 668                         else printk(KERN_ERR "PCI: Unknown option `%s'\n", str);
 669                 }
 670                 str = k;
 671         }
 672         return 1;
 673 }
 674
 675 __setup("pci=", pci_setup);