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Import 2.3.18pre1
[davej-history.git] / arch / sparc64 / mm / init.c
blobc1d8d24aeb4fd94514ed042477e6d88a875d1091
1 /* $Id: init.c,v 1.135 1999/09/06 22:55:10 ecd Exp $
2 * arch/sparc64/mm/init.c
3 *
4 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 */
7
8 #include <linux/config.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/mm.h>
12 #include <linux/malloc.h>
13 #include <linux/blk.h>
14 #include <linux/swap.h>
15 #include <linux/swapctl.h>
16
17 #include <asm/head.h>
18 #include <asm/system.h>
19 #include <asm/page.h>
20 #include <asm/pgtable.h>
21 #include <asm/oplib.h>
22 #include <asm/iommu.h>
23 #include <asm/io.h>
24 #include <asm/uaccess.h>
25 #include <asm/mmu_context.h>
26 #include <asm/vaddrs.h>
27 #include <asm/dma.h>
28
29 /* Turn this off if you suspect some place in some physical memory hole
30 might get into page tables (something would be broken very much). */
31
32 #define FREE_UNUSED_MEM_MAP
33
34 extern void show_net_buffers(void);
35 extern unsigned long device_scan(unsigned long);
36
37 struct sparc_phys_banks sp_banks[SPARC_PHYS_BANKS];
38
39 unsigned long *sparc64_valid_addr_bitmap;
40
41 /* Ugly, but necessary... -DaveM */
42 unsigned long phys_base;
43
44 /* get_new_mmu_context() uses "cache + 1". */
45 spinlock_t ctx_alloc_lock = SPIN_LOCK_UNLOCKED;
46 unsigned long tlb_context_cache = CTX_FIRST_VERSION - 1;
47 #define CTX_BMAP_SLOTS (1UL << (CTX_VERSION_SHIFT - 6))
48 unsigned long mmu_context_bmap[CTX_BMAP_SLOTS];
49
50 /* References to section boundaries */
51 extern char __init_begin, __init_end, etext, __bss_start;
52
53 int do_check_pgt_cache(int low, int high)
54 {
55 int freed = 0;
56
57 if(pgtable_cache_size > high) {
58 do {
59 #ifdef __SMP__
60 if(pgd_quicklist)
61 free_pgd_slow(get_pgd_fast()), freed++;
62 #endif
63 if(pte_quicklist)
64 free_pte_slow(get_pte_fast()), freed++;
65 } while(pgtable_cache_size > low);
66 }
67 #ifndef __SMP__
68 if (pgd_cache_size > high / 4) {
69 struct page *page, *page2;
70 for (page2 = NULL, page = (struct page *)pgd_quicklist; page;) {
71 if ((unsigned long)page->pprev_hash == 3) {
72 if (page2)
73 page2->next_hash = page->next_hash;
74 else
75 (struct page *)pgd_quicklist = page->next_hash;
76 page->next_hash = NULL;
77 page->pprev_hash = NULL;
78 pgd_cache_size -= 2;
79 __free_page(page);
80 freed++;
81 if (page2)
82 page = page2->next_hash;
83 else
84 page = (struct page *)pgd_quicklist;
85 if (pgd_cache_size <= low / 4)
86 break;
87 continue;
88 }
89 page2 = page;
90 page = page->next_hash;
91 }
92 }
93 #endif
94 return freed;
95 }
96
97 /*
98 * BAD_PAGE is the page that is used for page faults when linux
99 * is out-of-memory. Older versions of linux just did a
100 * do_exit(), but using this instead means there is less risk
101 * for a process dying in kernel mode, possibly leaving an inode
102 * unused etc..
103 *
104 * BAD_PAGETABLE is the accompanying page-table: it is initialized
105 * to point to BAD_PAGE entries.
106 *
107 * ZERO_PAGE is a special page that is used for zero-initialized
108 * data and COW.
109 */
110 pte_t __bad_page(void)
111 {
112 memset((void *) &empty_bad_page, 0, PAGE_SIZE);
113 return pte_mkdirty(mk_pte((((unsigned long) &empty_bad_page)
114 - ((unsigned long)&empty_zero_page) + phys_base + PAGE_OFFSET),
115 PAGE_SHARED));
116 }
117
118 void show_mem(void)
119 {
120 int free = 0,total = 0,reserved = 0;
121 int shared = 0, cached = 0;
122 struct page *page, *end;
123
124 printk("\nMem-info:\n");
125 show_free_areas();
126 printk("Free swap: %6dkB\n",nr_swap_pages<<(PAGE_SHIFT-10));
127 for (page = mem_map, end = mem_map + max_mapnr;
128 page < end; page++) {
129 if (PageSkip(page)) {
130 if (page->next_hash < page)
131 break;
132 page = page->next_hash;
133 }
134 total++;
135 if (PageReserved(page))
136 reserved++;
137 else if (PageSwapCache(page))
138 cached++;
139 else if (!atomic_read(&page->count))
140 free++;
141 else
142 shared += atomic_read(&page->count) - 1;
143 }
144 printk("%d pages of RAM\n",total);
145 printk("%d free pages\n",free);
146 printk("%d reserved pages\n",reserved);
147 printk("%d pages shared\n",shared);
148 printk("%d pages swap cached\n",cached);
149 printk("%d pages in page table cache\n",pgtable_cache_size);
150 #ifndef __SMP__
151 printk("%d entries in page dir cache\n",pgd_cache_size);
152 #endif
153 #ifdef CONFIG_NET
154 show_net_buffers();
155 #endif
156 }
157
158 /* IOMMU support, the ideas are right, the code should be cleaned a bit still... */
159
160 /* This keeps track of pages used in sparc_alloc_dvma() invocations. */
161 /* NOTE: All of these are inited to 0 in bss, don't need to make data segment bigger */
162 #define DVMAIO_SIZE 0x2000000
163 static unsigned long dvma_map_pages[DVMAIO_SIZE >> 16];
164 static unsigned long dvma_pages_current_offset;
165 static int dvma_pages_current_index;
166 static unsigned long dvmaiobase = 0;
167 static unsigned long dvmaiosz __initdata = 0;
168
169 void __init dvmaio_init(void)
170 {
171 long i;
172
173 if (!dvmaiobase) {
174 for (i = 0; sp_banks[i].num_bytes != 0; i++)
175 if (sp_banks[i].base_addr + sp_banks[i].num_bytes > dvmaiobase)
176 dvmaiobase = sp_banks[i].base_addr + sp_banks[i].num_bytes;
177
178 /* We map directly phys_base to phys_base+(4GB-DVMAIO_SIZE). */
179 dvmaiobase -= phys_base;
180
181 dvmaiobase = (dvmaiobase + DVMAIO_SIZE + 0x400000 - 1) & ~(0x400000 - 1);
182 for (i = 0; i < 6; i++)
183 if (dvmaiobase <= ((1024L * 64 * 1024) << i))
184 break;
185 dvmaiobase = ((1024L * 64 * 1024) << i) - DVMAIO_SIZE;
186 dvmaiosz = i;
187 }
188 }
189
190 void __init iommu_init(int iommu_node, struct linux_sbus *sbus)
191 {
192 extern int this_is_starfire;
193 extern void *starfire_hookup(int);
194 struct iommu_struct *iommu;
195 struct sysio_regs *sregs;
196 struct linux_prom64_registers rprop;
197 unsigned long impl, vers;
198 unsigned long control, tsbbase;
199 unsigned long tsbbases[32];
200 unsigned long *iopte;
201 int err, i, j;
202
203 dvmaio_init();
204 err = prom_getproperty(iommu_node, "reg", (char *)&rprop,
205 sizeof(rprop));
206 if(err == -1) {
207 prom_printf("iommu_init: Cannot map SYSIO control registers.\n");
208 prom_halt();
209 }
210 sregs = (struct sysio_regs *) __va(rprop.phys_addr);
211
212 if(!sregs) {
213 prom_printf("iommu_init: Fatal error, sysio regs not mapped\n");
214 prom_halt();
215 }
216
217 iommu = kmalloc(sizeof(struct iommu_struct), GFP_ATOMIC);
218 if (!iommu) {
219 prom_printf("iommu_init: Fatal error, kmalloc(iommu) failed\n");
220 prom_halt();
221 }
222
223 spin_lock_init(&iommu->iommu_lock);
224 iommu->sysio_regs = sregs;
225 sbus->iommu = iommu;
226
227 control = sregs->iommu_control;
228 impl = (control & IOMMU_CTRL_IMPL) >> 60;
229 vers = (control & IOMMU_CTRL_VERS) >> 56;
230 printk("IOMMU(SBUS): IMPL[%x] VERS[%x] SYSIO mapped at %016lx\n",
231 (unsigned int) impl, (unsigned int)vers, (unsigned long) sregs);
232
233 /* Streaming buffer is unreliable on VERS 0 of SYSIO,
234 * although such parts were never shipped in production
235 * Sun hardware, I check just to be robust. --DaveM
236 */
237 vers = ((sregs->control & SYSIO_CONTROL_VER) >> 56);
238 if (vers == 0)
239 iommu->strbuf_enabled = 0;
240 else
241 iommu->strbuf_enabled = 1;
242
243 control &= ~(IOMMU_CTRL_TSBSZ);
244 control |= ((IOMMU_TSBSZ_2K * dvmaiosz) | IOMMU_CTRL_TBWSZ | IOMMU_CTRL_ENAB);
245
246 /* Use only 64k pages, things are layed out in the 32-bit SBUS
247 * address space like this:
248 *
249 * 0x00000000 ----------------------------------------
250 * | Direct physical mappings for most |
251 * | DVMA to paddr's within this range |
252 * dvmaiobase ----------------------------------------
253 * | For mappings requested via |
254 * | sparc_alloc_dvma() |
255 * dvmaiobase+32M ----------------------------------------
256 *
257 * NOTE: we need to order 2 contiguous order 5, that's the largest
258 * chunk page_alloc will give us. -JJ */
259 tsbbase = 0;
260 if (dvmaiosz == 6) {
261 memset (tsbbases, 0, sizeof(tsbbases));
262 for (i = 0; i < 32; i++) {
263 tsbbases[i] = __get_free_pages(GFP_DMA, 5);
264 for (j = 0; j < i; j++)
265 if (tsbbases[j] == tsbbases[i] + 32768*sizeof(iopte_t)) {
266 tsbbase = tsbbases[i];
267 break;
268 } else if (tsbbases[i] == tsbbases[j] + 32768*sizeof(iopte_t)) {
269 tsbbase = tsbbases[j];
270 break;
271 }
272 if (tsbbase) {
273 tsbbases[i] = 0;
274 tsbbases[j] = 0;
275 break;
276 }
277 }
278 for (i = 0; i < 32; i++)
279 if (tsbbases[i])
280 free_pages(tsbbases[i], 5);
281 } else
282 tsbbase = __get_free_pages(GFP_DMA, dvmaiosz);
283 if (!tsbbase) {
284 prom_printf("Strange. Could not allocate 512K of contiguous RAM.\n");
285 prom_halt();
286 }
287 iommu->page_table = (iopte_t *) tsbbase;
288 iopte = (unsigned long *) tsbbase;
289
290 /* Setup aliased mappings... */
291 for(i = 0; i < (dvmaiobase >> 16); i++) {
292 unsigned long val = ((((unsigned long)i) << 16UL) + phys_base);
293
294 val |= IOPTE_VALID | IOPTE_64K | IOPTE_WRITE;
295 if (iommu->strbuf_enabled)
296 val |= IOPTE_STBUF;
297 else
298 val |= IOPTE_CACHE;
299 *iopte = val;
300 iopte++;
301 }
302
303 /* Clear all sparc_alloc_dvma() maps. */
304 for( ; i < ((dvmaiobase + DVMAIO_SIZE) >> 16); i++)
305 *iopte++ = 0;
306
307 sregs->iommu_tsbbase = __pa(tsbbase);
308 sregs->iommu_control = control;
309
310 /* Get the streaming buffer going. */
311 control = sregs->sbuf_control;
312 impl = (control & SYSIO_SBUFCTRL_IMPL) >> 60;
313 vers = (control & SYSIO_SBUFCTRL_REV) >> 56;
314 printk("IOMMU: Streaming Buffer IMPL[%x] REV[%x] ... ",
315 (unsigned int)impl, (unsigned int)vers);
316 iommu->flushflag = 0;
317
318 if (iommu->strbuf_enabled != 0) {
319 sregs->sbuf_control = (control | SYSIO_SBUFCTRL_SB_EN);
320 printk("ENABLED\n");
321 } else {
322 sregs->sbuf_control = (control & ~(SYSIO_SBUFCTRL_SB_EN));
323 printk("DISABLED\n");
324 }
325
326 /* Finally enable DVMA arbitration for all devices, just in case. */
327 sregs->sbus_control |= SYSIO_SBCNTRL_AEN;
328
329 /* If necessary, hook us up for starfire IRQ translations. */
330 sbus->upaid = prom_getintdefault(sbus->prom_node, "upa-portid", -1);
331 if(this_is_starfire)
332 sbus->starfire_cookie = starfire_hookup(sbus->upaid);
333 else
334 sbus->starfire_cookie = NULL;
335 }
336
337 void mmu_map_dma_area(unsigned long addr, int len, __u32 *dvma_addr,
338 struct linux_sbus *sbus)
339 {
340 pgd_t *pgdp;
341 pmd_t *pmdp;
342 pte_t *ptep;
343
344 /* Find out if we need to grab some pages. */
345 if(!dvma_map_pages[dvma_pages_current_index] ||
346 ((dvma_pages_current_offset + len) > (1 << 16))) {
347 struct linux_sbus *sbus;
348 unsigned long *iopte;
349 unsigned long newpages = __get_free_pages(GFP_KERNEL, 3);
350 int i;
351
352 if(!newpages)
353 panic("AIEEE cannot get DVMA pages.");
354
355 memset((char *)newpages, 0, (1 << 16));
356
357 if(!dvma_map_pages[dvma_pages_current_index]) {
358 dvma_map_pages[dvma_pages_current_index] = newpages;
359 i = dvma_pages_current_index;
360 } else {
361 dvma_map_pages[dvma_pages_current_index + 1] = newpages;
362 i = dvma_pages_current_index + 1;
363 }
364
365 /* Stick it in the IOMMU. */
366 i = (dvmaiobase >> 16) + i;
367 for_each_sbus(sbus) {
368 struct iommu_struct *iommu = sbus->iommu;
369 unsigned long flags;
370
371 spin_lock_irqsave(&iommu->iommu_lock, flags);
372 iopte = (unsigned long *)(iommu->page_table + i);
373 *iopte = (IOPTE_VALID | IOPTE_64K | IOPTE_CACHE | IOPTE_WRITE);
374 *iopte |= __pa(newpages);
375 spin_unlock_irqrestore(&iommu->iommu_lock, flags);
376 }
377 }
378
379 /* Get this out of the way. */
380 *dvma_addr = (__u32) ((dvmaiobase) +
381 (dvma_pages_current_index << 16) +
382 (dvma_pages_current_offset));
383
384 while(len > 0) {
385 while((len > 0) && (dvma_pages_current_offset < (1 << 16))) {
386 pte_t pte;
387 unsigned long the_page =
388 dvma_map_pages[dvma_pages_current_index] +
389 dvma_pages_current_offset;
390
391 /* Map the CPU's view. */
392 pgdp = pgd_offset(&init_mm, addr);
393 pmdp = pmd_alloc_kernel(pgdp, addr);
394 ptep = pte_alloc_kernel(pmdp, addr);
395 pte = mk_pte(the_page, PAGE_KERNEL);
396 set_pte(ptep, pte);
397
398 dvma_pages_current_offset += PAGE_SIZE;
399 addr += PAGE_SIZE;
400 len -= PAGE_SIZE;
401 }
402 dvma_pages_current_index++;
403 dvma_pages_current_offset = 0;
404 }
405 }
406
407 __u32 mmu_get_scsi_one(char *vaddr, unsigned long len, struct linux_sbus *sbus)
408 {
409 struct iommu_struct *iommu = sbus->iommu;
410 struct sysio_regs *sregs = iommu->sysio_regs;
411 unsigned long start = (unsigned long) vaddr;
412 unsigned long end = PAGE_ALIGN(start + len);
413 unsigned long flags, tmp;
414 volatile u64 *sbctrl = (volatile u64 *) &sregs->sbus_control;
415
416 start &= PAGE_MASK;
417 if (end > MAX_DMA_ADDRESS) {
418 printk("mmu_get_scsi_one: Bogus DMA buffer address [%016lx:%d]\n",
419 (unsigned long) vaddr, (int)len);
420 panic("DMA address too large, tell DaveM");
421 }
422
423 if (iommu->strbuf_enabled) {
424 volatile u64 *sbuf_pflush = (volatile u64 *) &sregs->sbuf_pflush;
425
426 spin_lock_irqsave(&iommu->iommu_lock, flags);
427 iommu->flushflag = 0;
428 while(start < end) {
429 *sbuf_pflush = start;
430 start += PAGE_SIZE;
431 }
432 sregs->sbuf_fsync = __pa(&(iommu->flushflag));
433 tmp = *sbctrl;
434 while(iommu->flushflag == 0)
435 membar("#LoadLoad");
436 spin_unlock_irqrestore(&iommu->iommu_lock, flags);
437 }
438
439 return sbus_dvma_addr(vaddr);
440 }
441
442 void mmu_release_scsi_one(u32 vaddr, unsigned long len, struct linux_sbus *sbus)
443 {
444 struct iommu_struct *iommu = sbus->iommu;
445 struct sysio_regs *sregs = iommu->sysio_regs;
446 unsigned long start = (unsigned long) vaddr;
447 unsigned long end = PAGE_ALIGN(start + len);
448 unsigned long flags, tmp;
449 volatile u64 *sbctrl = (volatile u64 *) &sregs->sbus_control;
450
451 start &= PAGE_MASK;
452
453 if (iommu->strbuf_enabled) {
454 volatile u64 *sbuf_pflush = (volatile u64 *) &sregs->sbuf_pflush;
455
456 spin_lock_irqsave(&iommu->iommu_lock, flags);
457
458 /* 1) Clear the flush flag word */
459 iommu->flushflag = 0;
460
461 /* 2) Tell the streaming buffer which entries
462 * we want flushed.
463 */
464 while(start < end) {
465 *sbuf_pflush = start;
466 start += PAGE_SIZE;
467 }
468
469 /* 3) Initiate flush sequence. */
470 sregs->sbuf_fsync = __pa(&(iommu->flushflag));
471
472 /* 4) Guarentee completion of all previous writes
473 * by reading SYSIO's SBUS control register.
474 */
475 tmp = *sbctrl;
476
477 /* 5) Wait for flush flag to get set. */
478 while(iommu->flushflag == 0)
479 membar("#LoadLoad");
480
481 spin_unlock_irqrestore(&iommu->iommu_lock, flags);
482 }
483 }
484
485 void mmu_get_scsi_sgl(struct mmu_sglist *sg, int sz, struct linux_sbus *sbus)
486 {
487 struct iommu_struct *iommu = sbus->iommu;
488 struct sysio_regs *sregs = iommu->sysio_regs;
489 unsigned long flags, tmp;
490 volatile u64 *sbctrl = (volatile u64 *) &sregs->sbus_control;
491
492 if (iommu->strbuf_enabled) {
493 volatile u64 *sbuf_pflush = (volatile u64 *) &sregs->sbuf_pflush;
494
495 spin_lock_irqsave(&iommu->iommu_lock, flags);
496 iommu->flushflag = 0;
497
498 while(sz >= 0) {
499 unsigned long start = (unsigned long)sg[sz].addr;
500 unsigned long end = PAGE_ALIGN(start + sg[sz].len);
501
502 if (end > MAX_DMA_ADDRESS) {
503 printk("mmu_get_scsi_sgl: Bogus DMA buffer address "
504 "[%016lx:%d]\n", start, (int) sg[sz].len);
505 panic("DMA address too large, tell DaveM");
506 }
507
508 sg[sz--].dvma_addr = sbus_dvma_addr(start);
509 start &= PAGE_MASK;
510 while(start < end) {
511 *sbuf_pflush = start;
512 start += PAGE_SIZE;
513 }
514 }
515
516 sregs->sbuf_fsync = __pa(&(iommu->flushflag));
517 tmp = *sbctrl;
518 while(iommu->flushflag == 0)
519 membar("#LoadLoad");
520 spin_unlock_irqrestore(&iommu->iommu_lock, flags);
521 } else {
522 /* Just verify the addresses and fill in the
523 * dvma_addr fields in this case.
524 */
525 while(sz >= 0) {
526 unsigned long start = (unsigned long)sg[sz].addr;
527 unsigned long end = PAGE_ALIGN(start + sg[sz].len);
528 if (end > MAX_DMA_ADDRESS) {
529 printk("mmu_get_scsi_sgl: Bogus DMA buffer address "
530 "[%016lx:%d]\n", start, (int) sg[sz].len);
531 panic("DMA address too large, tell DaveM");
532 }
533 sg[sz--].dvma_addr = sbus_dvma_addr(start);
534 }
535 }
536 }
537
538 void mmu_release_scsi_sgl(struct mmu_sglist *sg, int sz, struct linux_sbus *sbus)
539 {
540 struct iommu_struct *iommu = sbus->iommu;
541 struct sysio_regs *sregs = iommu->sysio_regs;
542 volatile u64 *sbctrl = (volatile u64 *) &sregs->sbus_control;
543 unsigned long flags, tmp;
544
545 if (iommu->strbuf_enabled) {
546 volatile u64 *sbuf_pflush = (volatile u64 *) &sregs->sbuf_pflush;
547
548 spin_lock_irqsave(&iommu->iommu_lock, flags);
549
550 /* 1) Clear the flush flag word */
551 iommu->flushflag = 0;
552
553 /* 2) Tell the streaming buffer which entries
554 * we want flushed.
555 */
556 while(sz >= 0) {
557 unsigned long start = sg[sz].dvma_addr;
558 unsigned long end = PAGE_ALIGN(start + sg[sz].len);
559
560 start &= PAGE_MASK;
561 while(start < end) {
562 *sbuf_pflush = start;
563 start += PAGE_SIZE;
564 }
565 sz--;
566 }
567
568 /* 3) Initiate flush sequence. */
569 sregs->sbuf_fsync = __pa(&(iommu->flushflag));
570
571 /* 4) Guarentee completion of previous writes
572 * by reading SYSIO's SBUS control register.
573 */
574 tmp = *sbctrl;
575
576 /* 5) Wait for flush flag to get set. */
577 while(iommu->flushflag == 0)
578 membar("#LoadLoad");
579
580 spin_unlock_irqrestore(&iommu->iommu_lock, flags);
581 }
582 }
583
584 void mmu_set_sbus64(struct linux_sbus_device *sdev, int bursts)
585 {
586 struct linux_sbus *sbus = sdev->my_bus;
587 struct sysio_regs *sregs = sbus->iommu->sysio_regs;
588 int slot = sdev->slot;
589 volatile u64 *cfg;
590 u64 tmp;
591
592 switch(slot) {
593 case 0:
594 cfg = &sregs->sbus_s0cfg;
595 break;
596 case 1:
597 cfg = &sregs->sbus_s1cfg;
598 break;
599 case 2:
600 cfg = &sregs->sbus_s2cfg;
601 break;
602 case 3:
603 cfg = &sregs->sbus_s3cfg;
604 break;
605
606 case 13:
607 cfg = &sregs->sbus_s4cfg;
608 break;
609 case 14:
610 cfg = &sregs->sbus_s5cfg;
611 break;
612 case 15:
613 cfg = &sregs->sbus_s6cfg;
614 break;
615
616 default:
617 return;
618 };
619
620 /* ETM already enabled? If so, we're done. */
621 tmp = *cfg;
622 if ((tmp & SYSIO_SBSCFG_ETM) != 0)
623 return;
624
625 /* Set burst bits. */
626 if (bursts & DMA_BURST8)
627 tmp |= SYSIO_SBSCFG_BA8;
628 if (bursts & DMA_BURST16)
629 tmp |= SYSIO_SBSCFG_BA16;
630 if (bursts & DMA_BURST32)
631 tmp |= SYSIO_SBSCFG_BA32;
632 if (bursts & DMA_BURST64)
633 tmp |= SYSIO_SBSCFG_BA64;
634
635 /* Finally turn on ETM and set register. */
636 *cfg = (tmp | SYSIO_SBSCFG_ETM);
637 }
638
639 int mmu_info(char *buf)
640 {
641 /* We'll do the rest later to make it nice... -DaveM */
642 return sprintf(buf, "MMU Type\t: Spitfire\n");
643 }
644
645 static unsigned long mempool;
646
647 struct linux_prom_translation {
648 unsigned long virt;
649 unsigned long size;
650 unsigned long data;
651 };
652
653 static inline void inherit_prom_mappings(void)
654 {
655 struct linux_prom_translation *trans;
656 pgd_t *pgdp;
657 pmd_t *pmdp;
658 pte_t *ptep;
659 int node, n, i;
660
661 node = prom_finddevice("/virtual-memory");
662 n = prom_getproplen(node, "translations");
663 if (n == 0 || n == -1) {
664 prom_printf("Couldn't get translation property\n");
665 prom_halt();
666 }
667
668 for (i = 1; i < n; i <<= 1) /* empty */;
669 trans = sparc_init_alloc(&mempool, i);
670
671 if (prom_getproperty(node, "translations", (char *)trans, i) == -1) {
672 prom_printf("Couldn't get translation property\n");
673 prom_halt();
674 }
675 n = n / sizeof(*trans);
676
677 for (i = 0; i < n; i++) {
678 unsigned long vaddr;
679
680 if (trans[i].virt >= 0xf0000000 && trans[i].virt < 0x100000000) {
681 for (vaddr = trans[i].virt;
682 vaddr < trans[i].virt + trans[i].size;
683 vaddr += PAGE_SIZE) {
684 pgdp = pgd_offset(&init_mm, vaddr);
685 if (pgd_none(*pgdp)) {
686 pmdp = sparc_init_alloc(&mempool,
687 PMD_TABLE_SIZE);
688 memset(pmdp, 0, PAGE_SIZE);
689 pgd_set(pgdp, pmdp);
690 }
691 pmdp = pmd_offset(pgdp, vaddr);
692 if (pmd_none(*pmdp)) {
693 ptep = sparc_init_alloc(&mempool,
694 PTE_TABLE_SIZE);
695 pmd_set(pmdp, ptep);
696 }
697 ptep = pte_offset(pmdp, vaddr);
698 set_pte (ptep, __pte(trans[i].data | _PAGE_MODIFIED));
699 trans[i].data += PAGE_SIZE;
700 }
701 }
702 }
703 }
704
705 /* The OBP specifications for sun4u mark 0xfffffffc00000000 and
706 * upwards as reserved for use by the firmware (I wonder if this
707 * will be the same on Cheetah...). We use this virtual address
708 * range for the VPTE table mappings of the nucleus so we need
709 * to zap them when we enter the PROM. -DaveM
710 */
711 static void __flush_nucleus_vptes(void)
712 {
713 unsigned long prom_reserved_base = 0xfffffffc00000000UL;
714 int i;
715
716 /* Only DTLB must be checked for VPTE entries. */
717 for(i = 0; i < 63; i++) {
718 unsigned long tag = spitfire_get_dtlb_tag(i);
719
720 if(((tag & ~(PAGE_MASK)) == 0) &&
721 ((tag & (PAGE_MASK)) >= prom_reserved_base)) {
722 __asm__ __volatile__("stxa %%g0, [%0] %1"
723 : /* no outputs */
724 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
725 membar("#Sync");
726 spitfire_put_dtlb_data(i, 0x0UL);
727 membar("#Sync");
728 }
729 }
730 }
731
732 static int prom_ditlb_set = 0;
733 struct prom_tlb_entry {
734 int tlb_ent;
735 unsigned long tlb_tag;
736 unsigned long tlb_data;
737 };
738 struct prom_tlb_entry prom_itlb[8], prom_dtlb[8];
739
740 void prom_world(int enter)
741 {
742 unsigned long pstate;
743 int i;
744
745 if (!enter)
746 set_fs(current->thread.current_ds);
747
748 if (!prom_ditlb_set)
749 return;
750
751 /* Make sure the following runs atomically. */
752 __asm__ __volatile__("flushw\n\t"
753 "rdpr %%pstate, %0\n\t"
754 "wrpr %0, %1, %%pstate"
755 : "=r" (pstate)
756 : "i" (PSTATE_IE));
757
758 if (enter) {
759 /* Kick out nucleus VPTEs. */
760 __flush_nucleus_vptes();
761
762 /* Install PROM world. */
763 for (i = 0; i < 8; i++) {
764 if (prom_dtlb[i].tlb_ent != -1) {
765 __asm__ __volatile__("stxa %0, [%1] %2"
766 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
767 "i" (ASI_DMMU));
768 membar("#Sync");
769 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
770 prom_dtlb[i].tlb_data);
771 membar("#Sync");
772 }
773
774 if (prom_itlb[i].tlb_ent != -1) {
775 __asm__ __volatile__("stxa %0, [%1] %2"
776 : : "r" (prom_itlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
777 "i" (ASI_IMMU));
778 membar("#Sync");
779 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
780 prom_itlb[i].tlb_data);
781 membar("#Sync");
782 }
783 }
784 } else {
785 for (i = 0; i < 8; i++) {
786 if (prom_dtlb[i].tlb_ent != -1) {
787 __asm__ __volatile__("stxa %%g0, [%0] %1"
788 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
789 membar("#Sync");
790 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent, 0x0UL);
791 membar("#Sync");
792 }
793 if (prom_itlb[i].tlb_ent != -1) {
794 __asm__ __volatile__("stxa %%g0, [%0] %1"
795 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
796 membar("#Sync");
797 spitfire_put_itlb_data(prom_itlb[i].tlb_ent, 0x0UL);
798 membar("#Sync");
799 }
800 }
801 }
802 __asm__ __volatile__("wrpr %0, 0, %%pstate"
803 : : "r" (pstate));
804 }
805
806 void inherit_locked_prom_mappings(int save_p)
807 {
808 int i;
809 int dtlb_seen = 0;
810 int itlb_seen = 0;
811
812 /* Fucking losing PROM has more mappings in the TLB, but
813 * it (conveniently) fails to mention any of these in the
814 * translations property. The only ones that matter are
815 * the locked PROM tlb entries, so we impose the following
816 * irrecovable rule on the PROM, it is allowed 8 locked
817 * entries in the ITLB and 8 in the DTLB.
818 *
819 * Supposedly the upper 16GB of the address space is
820 * reserved for OBP, BUT I WISH THIS WAS DOCUMENTED
821 * SOMEWHERE!!!!!!!!!!!!!!!!! Furthermore the entire interface
822 * used between the client program and the firmware on sun5
823 * systems to coordinate mmu mappings is also COMPLETELY
824 * UNDOCUMENTED!!!!!! Thanks S(t)un!
825 */
826 if (save_p) {
827 for(i = 0; i < 8; i++) {
828 prom_dtlb[i].tlb_ent = -1;
829 prom_itlb[i].tlb_ent = -1;
830 }
831 }
832 for(i = 0; i < 63; i++) {
833 unsigned long data;
834
835 data = spitfire_get_dtlb_data(i);
836 if((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
837 unsigned long tag = spitfire_get_dtlb_tag(i);
838
839 if(save_p) {
840 prom_dtlb[dtlb_seen].tlb_ent = i;
841 prom_dtlb[dtlb_seen].tlb_tag = tag;
842 prom_dtlb[dtlb_seen].tlb_data = data;
843 }
844 __asm__ __volatile__("stxa %%g0, [%0] %1"
845 : : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
846 membar("#Sync");
847 spitfire_put_dtlb_data(i, 0x0UL);
848 membar("#Sync");
849
850 dtlb_seen++;
851 if(dtlb_seen > 7)
852 break;
853 }
854 }
855 for(i = 0; i < 63; i++) {
856 unsigned long data;
857
858 data = spitfire_get_itlb_data(i);
859 if((data & (_PAGE_L|_PAGE_VALID)) == (_PAGE_L|_PAGE_VALID)) {
860 unsigned long tag = spitfire_get_itlb_tag(i);
861
862 if(save_p) {
863 prom_itlb[itlb_seen].tlb_ent = i;
864 prom_itlb[itlb_seen].tlb_tag = tag;
865 prom_itlb[itlb_seen].tlb_data = data;
866 }
867 __asm__ __volatile__("stxa %%g0, [%0] %1"
868 : : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
869 membar("#Sync");
870 spitfire_put_itlb_data(i, 0x0UL);
871 membar("#Sync");
872
873 itlb_seen++;
874 if(itlb_seen > 7)
875 break;
876 }
877 }
878 if (save_p)
879 prom_ditlb_set = 1;
880 }
881
882 /* Give PROM back his world, done during reboots... */
883 void prom_reload_locked(void)
884 {
885 int i;
886
887 for (i = 0; i < 8; i++) {
888 if (prom_dtlb[i].tlb_ent != -1) {
889 __asm__ __volatile__("stxa %0, [%1] %2"
890 : : "r" (prom_dtlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
891 "i" (ASI_DMMU));
892 membar("#Sync");
893 spitfire_put_dtlb_data(prom_dtlb[i].tlb_ent,
894 prom_dtlb[i].tlb_data);
895 membar("#Sync");
896 }
897
898 if (prom_itlb[i].tlb_ent != -1) {
899 __asm__ __volatile__("stxa %0, [%1] %2"
900 : : "r" (prom_itlb[i].tlb_tag), "r" (TLB_TAG_ACCESS),
901 "i" (ASI_IMMU));
902 membar("#Sync");
903 spitfire_put_itlb_data(prom_itlb[i].tlb_ent,
904 prom_itlb[i].tlb_data);
905 membar("#Sync");
906 }
907 }
908 }
909
910 void __flush_dcache_range(unsigned long start, unsigned long end)
911 {
912 unsigned long va;
913 int n = 0;
914
915 for (va = start; va < end; va += 32) {
916 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
917 if (++n >= 512)
918 break;
919 }
920 }
921
922 void __flush_cache_all(void)
923 {
924 unsigned long va;
925
926 flushw_all();
927 for(va = 0; va < (PAGE_SIZE << 1); va += 32)
928 spitfire_put_icache_tag(va, 0x0);
929 }
930
931 /* If not locked, zap it. */
932 void __flush_tlb_all(void)
933 {
934 unsigned long pstate;
935 int i;
936
937 __asm__ __volatile__("flushw\n\t"
938 "rdpr %%pstate, %0\n\t"
939 "wrpr %0, %1, %%pstate"
940 : "=r" (pstate)
941 : "i" (PSTATE_IE));
942 for(i = 0; i < 64; i++) {
943 if(!(spitfire_get_dtlb_data(i) & _PAGE_L)) {
944 __asm__ __volatile__("stxa %%g0, [%0] %1"
945 : /* no outputs */
946 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
947 membar("#Sync");
948 spitfire_put_dtlb_data(i, 0x0UL);
949 membar("#Sync");
950 }
951 if(!(spitfire_get_itlb_data(i) & _PAGE_L)) {
952 __asm__ __volatile__("stxa %%g0, [%0] %1"
953 : /* no outputs */
954 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
955 membar("#Sync");
956 spitfire_put_itlb_data(i, 0x0UL);
957 membar("#Sync");
958 }
959 }
960 __asm__ __volatile__("wrpr %0, 0, %%pstate"
961 : : "r" (pstate));
962 }
963
964 /* Caller does TLB context flushing on local CPU if necessary.
965 *
966 * We must be careful about boundary cases so that we never
967 * let the user have CTX 0 (nucleus) or we ever use a CTX
968 * version of zero (and thus NO_CONTEXT would not be caught
969 * by version mis-match tests in mmu_context.h).
970 */
971 void get_new_mmu_context(struct mm_struct *mm)
972 {
973 unsigned long ctx, new_ctx;
974
975 spin_lock(&ctx_alloc_lock);
976 ctx = CTX_HWBITS(tlb_context_cache + 1);
977 if (ctx == 0)
978 ctx = 1;
979 if (CTX_VALID(mm->context)) {
980 unsigned long nr = CTX_HWBITS(mm->context);
981 mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
982 }
983 new_ctx = find_next_zero_bit(mmu_context_bmap, 1UL << CTX_VERSION_SHIFT, ctx);
984 if (new_ctx >= (1UL << CTX_VERSION_SHIFT)) {
985 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
986 if (new_ctx >= ctx) {
987 int i;
988 new_ctx = (tlb_context_cache & CTX_VERSION_MASK) +
989 CTX_FIRST_VERSION;
990 if (new_ctx == 1)
991 new_ctx = CTX_FIRST_VERSION;
992
993 /* Don't call memset, for 16 entries that's just
994 * plain silly...
995 */
996 mmu_context_bmap[0] = 3;
997 mmu_context_bmap[1] = 0;
998 mmu_context_bmap[2] = 0;
999 mmu_context_bmap[3] = 0;
1000 for(i = 4; i < CTX_BMAP_SLOTS; i += 4) {
1001 mmu_context_bmap[i + 0] = 0;
1002 mmu_context_bmap[i + 1] = 0;
1003 mmu_context_bmap[i + 2] = 0;
1004 mmu_context_bmap[i + 3] = 0;
1005 }
1006 goto out;
1007 }
1008 }
1009 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
1010 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
1011 out:
1012 tlb_context_cache = new_ctx;
1013 spin_unlock(&ctx_alloc_lock);
1014
1015 mm->context = new_ctx;
1016 }
1017
1018 #ifndef __SMP__
1019 struct pgtable_cache_struct pgt_quicklists;
1020 #endif
1021
1022 pmd_t *get_pmd_slow(pgd_t *pgd, unsigned long offset)
1023 {
1024 pmd_t *pmd;
1025
1026 pmd = (pmd_t *) __get_free_page(GFP_KERNEL);
1027 if(pmd) {
1028 memset(pmd, 0, PAGE_SIZE);
1029 pgd_set(pgd, pmd);
1030 return pmd + offset;
1031 }
1032 return NULL;
1033 }
1034
1035 pte_t *get_pte_slow(pmd_t *pmd, unsigned long offset)
1036 {
1037 pte_t *pte;
1038
1039 pte = (pte_t *) __get_free_page(GFP_KERNEL);
1040 if(pte) {
1041 memset(pte, 0, PAGE_SIZE);
1042 pmd_set(pmd, pte);
1043 return pte + offset;
1044 }
1045 return NULL;
1046 }
1047
1048 static void __init
1049 allocate_ptable_skeleton(unsigned long start, unsigned long end)
1050 {
1051 pgd_t *pgdp;
1052 pmd_t *pmdp;
1053 pte_t *ptep;
1054
1055 while (start < end) {
1056 pgdp = pgd_offset(&init_mm, start);
1057 if (pgd_none(*pgdp)) {
1058 pmdp = sparc_init_alloc(&mempool, PAGE_SIZE);
1059 memset(pmdp, 0, PAGE_SIZE);
1060 pgd_set(pgdp, pmdp);
1061 }
1062 pmdp = pmd_offset(pgdp, start);
1063 if (pmd_none(*pmdp)) {
1064 ptep = sparc_init_alloc(&mempool, PAGE_SIZE);
1065 memset(ptep, 0, PAGE_SIZE);
1066 pmd_set(pmdp, ptep);
1067 }
1068 start = (start + PMD_SIZE) & PMD_MASK;
1069 }
1070 }
1071
1072 /*
1073 * Create a mapping for an I/O register. Have to make sure the side-effect
1074 * bit is set.
1075 */
1076
1077 void sparc_ultra_mapioaddr(unsigned long physaddr, unsigned long virt_addr,
1078 int bus, int rdonly)
1079 {
1080 pgd_t *pgdp = pgd_offset(&init_mm, virt_addr);
1081 pmd_t *pmdp = pmd_offset(pgdp, virt_addr);
1082 pte_t *ptep = pte_offset(pmdp, virt_addr);
1083 pte_t pte;
1084
1085 physaddr &= PAGE_MASK;
1086
1087 if(rdonly)
1088 pte = mk_pte_phys(physaddr, __pgprot(pg_iobits | __PRIV_BITS));
1089 else
1090 pte = mk_pte_phys(physaddr, __pgprot(pg_iobits | __DIRTY_BITS | __PRIV_BITS));
1091
1092 set_pte(ptep, pte);
1093 }
1094
1095 /* XXX no longer used, remove me... -DaveM */
1096 void sparc_ultra_unmapioaddr(unsigned long virt_addr)
1097 {
1098 pgd_t *pgdp;
1099 pmd_t *pmdp;
1100 pte_t *ptep;
1101
1102 pgdp = pgd_offset(&init_mm, virt_addr);
1103 pmdp = pmd_offset(pgdp, virt_addr);
1104 ptep = pte_offset(pmdp, virt_addr);
1105
1106 /* No need to flush uncacheable page. */
1107 pte_clear(ptep);
1108 }
1109
1110 void sparc_ultra_dump_itlb(void)
1111 {
1112 int slot;
1113
1114 printk ("Contents of itlb: ");
1115 for (slot = 0; slot < 14; slot++) printk (" ");
1116 printk ("%2x:%016lx,%016lx\n", 0, spitfire_get_itlb_tag(0), spitfire_get_itlb_data(0));
1117 for (slot = 1; slot < 64; slot+=3) {
1118 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1119 slot, spitfire_get_itlb_tag(slot), spitfire_get_itlb_data(slot),
1120 slot+1, spitfire_get_itlb_tag(slot+1), spitfire_get_itlb_data(slot+1),
1121 slot+2, spitfire_get_itlb_tag(slot+2), spitfire_get_itlb_data(slot+2));
1122 }
1123 }
1124
1125 void sparc_ultra_dump_dtlb(void)
1126 {
1127 int slot;
1128
1129 printk ("Contents of dtlb: ");
1130 for (slot = 0; slot < 14; slot++) printk (" ");
1131 printk ("%2x:%016lx,%016lx\n", 0, spitfire_get_dtlb_tag(0),
1132 spitfire_get_dtlb_data(0));
1133 for (slot = 1; slot < 64; slot+=3) {
1134 printk ("%2x:%016lx,%016lx %2x:%016lx,%016lx %2x:%016lx,%016lx\n",
1135 slot, spitfire_get_dtlb_tag(slot), spitfire_get_dtlb_data(slot),
1136 slot+1, spitfire_get_dtlb_tag(slot+1), spitfire_get_dtlb_data(slot+1),
1137 slot+2, spitfire_get_dtlb_tag(slot+2), spitfire_get_dtlb_data(slot+2));
1138 }
1139 }
1140
1141 /* paging_init() sets up the page tables */
1142
1143 extern unsigned long free_area_init(unsigned long, unsigned long);
1144 extern unsigned long sun_serial_setup(unsigned long);
1145
1146 unsigned long __init
1147 paging_init(unsigned long start_mem, unsigned long end_mem)
1148 {
1149 extern pmd_t swapper_pmd_dir[1024];
1150 extern unsigned int sparc64_vpte_patchme1[1];
1151 extern unsigned int sparc64_vpte_patchme2[1];
1152 unsigned long alias_base = phys_base + PAGE_OFFSET;
1153 unsigned long second_alias_page = 0;
1154 unsigned long pt;
1155 unsigned long flags;
1156 unsigned long shift = alias_base - ((unsigned long)&empty_zero_page);
1157
1158 set_bit(0, mmu_context_bmap);
1159 /* We assume physical memory starts at some 4mb multiple,
1160 * if this were not true we wouldn't boot up to this point
1161 * anyways.
1162 */
1163 pt = phys_base | _PAGE_VALID | _PAGE_SZ4MB;
1164 pt |= _PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W;
1165 __save_and_cli(flags);
1166 __asm__ __volatile__("
1167 stxa %1, [%0] %3
1168 stxa %2, [%5] %4
1169 membar #Sync
1170 flush %%g6
1171 nop
1172 nop
1173 nop"
1174 : /* No outputs */
1175 : "r" (TLB_TAG_ACCESS), "r" (alias_base), "r" (pt),
1176 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (61 << 3)
1177 : "memory");
1178 if (start_mem >= KERNBASE + 0x340000) {
1179 second_alias_page = alias_base + 0x400000;
1180 __asm__ __volatile__("
1181 stxa %1, [%0] %3
1182 stxa %2, [%5] %4
1183 membar #Sync
1184 flush %%g6
1185 nop
1186 nop
1187 nop"
1188 : /* No outputs */
1189 : "r" (TLB_TAG_ACCESS), "r" (second_alias_page), "r" (pt + 0x400000),
1190 "i" (ASI_DMMU), "i" (ASI_DTLB_DATA_ACCESS), "r" (60 << 3)
1191 : "memory");
1192 }
1193 __restore_flags(flags);
1194
1195 /* Now set kernel pgd to upper alias so physical page computations
1196 * work.
1197 */
1198 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
1199
1200 memset(swapper_pmd_dir, 0, sizeof(swapper_pmd_dir));
1201
1202 /* Now can init the kernel/bad page tables. */
1203 pgd_set(&swapper_pg_dir[0], swapper_pmd_dir + (shift / sizeof(pgd_t)));
1204
1205 sparc64_vpte_patchme1[0] |= (init_mm.pgd[0] >> 10);
1206 sparc64_vpte_patchme2[0] |= (init_mm.pgd[0] & 0x3ff);
1207 flushi((long)&sparc64_vpte_patchme1[0]);
1208
1209 /* We use mempool to create page tables, therefore adjust it up
1210 * such that __pa() macros etc. work.
1211 */
1212 mempool = PAGE_ALIGN(start_mem) + shift;
1213
1214 #ifdef CONFIG_SUN_SERIAL
1215 /* This does not logically belong here, but is the first place
1216 we can initialize it at, so that we work in the PAGE_OFFSET+
1217 address space. */
1218 mempool = sun_serial_setup(mempool);
1219 #endif
1220
1221 /* Allocate 64M for dynamic DVMA mapping area. */
1222 allocate_ptable_skeleton(DVMA_VADDR, DVMA_VADDR + 0x4000000);
1223 inherit_prom_mappings();
1224
1225 /* Ok, we can use our TLB miss and window trap handlers safely.
1226 * We need to do a quick peek here to see if we are on StarFire
1227 * or not, so setup_tba can setup the IRQ globals correctly (it
1228 * needs to get the hard smp processor id correctly).
1229 */
1230 {
1231 extern void setup_tba(int);
1232 int is_starfire = prom_finddevice("/ssp-serial");
1233 if(is_starfire != 0 && is_starfire != -1)
1234 is_starfire = 1;
1235 else
1236 is_starfire = 0;
1237 setup_tba(is_starfire);
1238 }
1239
1240 /* Really paranoid. */
1241 flushi((long)&empty_zero_page);
1242 membar("#Sync");
1243
1244 /* Cleanup the extra locked TLB entry we created since we have the
1245 * nice TLB miss handlers of ours installed now.
1246 */
1247 /* We only created DTLB mapping of this stuff. */
1248 spitfire_flush_dtlb_nucleus_page(alias_base);
1249 if (second_alias_page)
1250 spitfire_flush_dtlb_nucleus_page(second_alias_page);
1251 membar("#Sync");
1252
1253 /* Paranoid */
1254 flushi((long)&empty_zero_page);
1255 membar("#Sync");
1256
1257 inherit_locked_prom_mappings(1);
1258
1259 flush_tlb_all();
1260
1261 start_mem = free_area_init(PAGE_ALIGN(mempool), end_mem);
1262
1263 return device_scan (PAGE_ALIGN (start_mem));
1264 }
1265
1266 static void __init taint_real_pages(unsigned long start_mem, unsigned long end_mem)
1267 {
1268 unsigned long tmp = 0, paddr, endaddr;
1269 unsigned long end = __pa(end_mem);
1270
1271 dvmaio_init();
1272 for (paddr = __pa(start_mem); paddr < end; ) {
1273 for (; sp_banks[tmp].num_bytes != 0; tmp++)
1274 if (sp_banks[tmp].base_addr + sp_banks[tmp].num_bytes > paddr)
1275 break;
1276 if (!sp_banks[tmp].num_bytes) {
1277 mem_map[paddr>>PAGE_SHIFT].flags |= (1<<PG_skip);
1278 mem_map[paddr>>PAGE_SHIFT].next_hash = mem_map + (phys_base >> PAGE_SHIFT);
1279 mem_map[(paddr>>PAGE_SHIFT)+1UL].flags |= (1<<PG_skip);
1280 mem_map[(paddr>>PAGE_SHIFT)+1UL].next_hash = mem_map + (phys_base >> PAGE_SHIFT);
1281 return;
1282 }
1283
1284 if (sp_banks[tmp].base_addr > paddr) {
1285 /* Making a one or two pages PG_skip holes
1286 * is not necessary. We add one more because
1287 * we must set the PG_skip flag on the first
1288 * two mem_map[] entries for the hole. Go and
1289 * see the mm/filemap.c:shrink_mmap() loop for
1290 * details. -DaveM
1291 */
1292 if (sp_banks[tmp].base_addr - paddr > 3 * PAGE_SIZE) {
1293 mem_map[paddr>>PAGE_SHIFT].flags |= (1<<PG_skip);
1294 mem_map[paddr>>PAGE_SHIFT].next_hash = mem_map + (sp_banks[tmp].base_addr >> PAGE_SHIFT);
1295 mem_map[(paddr>>PAGE_SHIFT)+1UL].flags |= (1<<PG_skip);
1296 mem_map[(paddr>>PAGE_SHIFT)+1UL].next_hash = mem_map + (sp_banks[tmp].base_addr >> PAGE_SHIFT);
1297 }
1298 paddr = sp_banks[tmp].base_addr;
1299 }
1300
1301 endaddr = sp_banks[tmp].base_addr + sp_banks[tmp].num_bytes;
1302 while (paddr < endaddr) {
1303 mem_map[paddr>>PAGE_SHIFT].flags &= ~(1<<PG_reserved);
1304 set_bit(paddr >> 22, sparc64_valid_addr_bitmap);
1305 if (paddr >= (MAX_DMA_ADDRESS - PAGE_OFFSET))
1306 mem_map[paddr>>PAGE_SHIFT].flags &= ~(1<<PG_DMA);
1307 paddr += PAGE_SIZE;
1308 }
1309 }
1310 }
1311
1312 void __init mem_init(unsigned long start_mem, unsigned long end_mem)
1313 {
1314 int codepages = 0;
1315 int datapages = 0;
1316 int initpages = 0;
1317 unsigned long addr;
1318 unsigned long alias_base = phys_base + PAGE_OFFSET - (long)(&empty_zero_page);
1319 struct page *page, *end;
1320 int i;
1321
1322 end_mem &= PAGE_MASK;
1323 max_mapnr = MAP_NR(end_mem);
1324 high_memory = (void *) end_mem;
1325
1326 start_mem = ((start_mem + 7UL) & ~7UL);
1327 sparc64_valid_addr_bitmap = (unsigned long *)start_mem;
1328 i = max_mapnr >> ((22 - PAGE_SHIFT) + 6);
1329 i += 1;
1330 memset(sparc64_valid_addr_bitmap, 0, i << 3);
1331 start_mem += i << 3;
1332
1333 start_mem = PAGE_ALIGN(start_mem);
1334 num_physpages = 0;
1335
1336 if (phys_base) {
1337 mem_map[0].flags |= (1<<PG_skip) | (1<<PG_reserved);
1338 mem_map[0].next_hash = mem_map + (phys_base >> PAGE_SHIFT);
1339 mem_map[1].flags |= (1<<PG_skip) | (1<<PG_reserved);
1340 mem_map[1].next_hash = mem_map + (phys_base >> PAGE_SHIFT);
1341 }
1342
1343 addr = PAGE_OFFSET + phys_base;
1344 while(addr < start_mem) {
1345 #ifdef CONFIG_BLK_DEV_INITRD
1346 if (initrd_below_start_ok && addr >= initrd_start && addr < initrd_end)
1347 mem_map[MAP_NR(addr)].flags &= ~(1<<PG_reserved);
1348 else
1349 #endif
1350 mem_map[MAP_NR(addr)].flags |= (1<<PG_reserved);
1351 set_bit(__pa(addr) >> 22, sparc64_valid_addr_bitmap);
1352 addr += PAGE_SIZE;
1353 }
1354
1355 taint_real_pages(start_mem, end_mem);
1356
1357 #ifdef FREE_UNUSED_MEM_MAP
1358 end = mem_map + max_mapnr;
1359 for (page = mem_map; page < end; page++) {
1360 if (PageSkip(page)) {
1361 unsigned long low, high;
1362
1363 /* See taint_real_pages() for why this is done. -DaveM */
1364 page++;
1365
1366 low = PAGE_ALIGN((unsigned long)(page+1));
1367 if (page->next_hash < page)
1368 high = ((unsigned long)end) & PAGE_MASK;
1369 else
1370 high = ((unsigned long)page->next_hash) & PAGE_MASK;
1371 while (low < high) {
1372 mem_map[MAP_NR(low)].flags &= ~(1<<PG_reserved);
1373 low += PAGE_SIZE;
1374 }
1375 }
1376 }
1377 #endif
1378
1379 for (addr = PAGE_OFFSET; addr < end_mem; addr += PAGE_SIZE) {
1380 if (PageSkip(mem_map + MAP_NR(addr))) {
1381 unsigned long next = mem_map[MAP_NR(addr)].next_hash - mem_map;
1382
1383 next = (next << PAGE_SHIFT) + PAGE_OFFSET;
1384 if (next < addr || next >= end_mem)
1385 break;
1386 addr = next;
1387 }
1388 num_physpages++;
1389 if (PageReserved(mem_map + MAP_NR(addr))) {
1390 if ((addr < ((unsigned long) &etext) + alias_base) && (addr >= alias_base))
1391 codepages++;
1392 else if((addr >= ((unsigned long)&__init_begin) + alias_base)
1393 && (addr < ((unsigned long)&__init_end) + alias_base))
1394 initpages++;
1395 else if((addr < start_mem) && (addr >= alias_base))
1396 datapages++;
1397 continue;
1398 }
1399 atomic_set(&mem_map[MAP_NR(addr)].count, 1);
1400 #ifdef CONFIG_BLK_DEV_INITRD
1401 if (!initrd_start ||
1402 (addr < initrd_start || addr >= initrd_end))
1403 #endif
1404 free_page(addr);
1405 }
1406
1407 #ifndef __SMP__
1408 {
1409 /* Put empty_pg_dir on pgd_quicklist */
1410 extern pgd_t empty_pg_dir[1024];
1411 unsigned long addr = (unsigned long)empty_pg_dir;
1412
1413 memset(empty_pg_dir, 0, sizeof(empty_pg_dir));
1414 addr += alias_base;
1415 mem_map[MAP_NR(addr)].pprev_hash = 0;
1416 free_pgd_fast((pgd_t *)addr);
1417 }
1418 #endif
1419
1420 printk("Memory: %uk available (%dk kernel code, %dk data, %dk init) [%016lx,%016lx]\n",
1421 nr_free_pages << (PAGE_SHIFT-10),
1422 codepages << (PAGE_SHIFT-10),
1423 datapages << (PAGE_SHIFT-10),
1424 initpages << (PAGE_SHIFT-10),
1425 PAGE_OFFSET, end_mem);
1426
1427 /* NOTE NOTE NOTE NOTE
1428 * Please keep track of things and make sure this
1429 * always matches the code in mm/page_alloc.c -DaveM
1430 */
1431 i = nr_free_pages >> 7;
1432 if (i < 48)
1433 i = 48;
1434 if (i > 256)
1435 i = 256;
1436 freepages.min = i;
1437 freepages.low = i << 1;
1438 freepages.high = freepages.low + i;
1439 }
1440
1441 void free_initmem (void)
1442 {
1443 unsigned long addr;
1444
1445 addr = (unsigned long)(&__init_begin);
1446 for (; addr < (unsigned long)(&__init_end); addr += PAGE_SIZE) {
1447 unsigned long page = addr + (long)__va(phys_base)
1448 - (long)(&empty_zero_page);
1449
1450 mem_map[MAP_NR(page)].flags &= ~(1 << PG_reserved);
1451 atomic_set(&mem_map[MAP_NR(page)].count, 1);
1452 free_page(page);
1453 }
1454 }
1455
1456 void si_meminfo(struct sysinfo *val)
1457 {
1458 struct page *page, *end;
1459
1460 val->totalram = 0;
1461 val->sharedram = 0;
1462 val->freeram = ((unsigned long)nr_free_pages) << PAGE_SHIFT;
1463 val->bufferram = atomic_read(&buffermem);
1464 for (page = mem_map, end = mem_map + max_mapnr;
1465 page < end; page++) {
1466 if (PageSkip(page)) {
1467 if (page->next_hash < page)
1468 break;
1469 page = page->next_hash;
1470 }
1471 if (PageReserved(page))
1472 continue;
1473 val->totalram++;
1474 if (!atomic_read(&page->count))
1475 continue;
1476 val->sharedram += atomic_read(&page->count) - 1;
1477 }
1478 val->totalram <<= PAGE_SHIFT;
1479 val->sharedram <<= PAGE_SHIFT;
1480 val->totalbig = 0;
1481 val->freebig = 0;
1482 }
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