1 /* $Id: pci_sabre.c,v 1.2 1999/09/05 04:58:06 davem Exp $
2 * pci_sabre.c: Sabre specific PCI controller support.
4 * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
5 * Copyright (C) 1998, 1999 Eddie C. Dost (ecd@skynet.be)
6 * Copyright (C) 1999 Jakub Jelinek (jj@ultra.linux.cz)
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/pci.h>
12 #include <linux/init.h>
13 #include <linux/malloc.h>
17 #include <asm/iommu.h>
22 /* All SABRE registers are 64-bits. The following accessor
23 * routines are how they are accessed. The REG parameter
24 * is a physical address.
26 #define sabre_read(__reg) \
28 __asm__ __volatile__("ldxa [%1] %2, %0" \
30 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 #define sabre_write(__reg, __val) \
35 __asm__ __volatile__("stxa %0, [%1] %2" \
37 : "r" (__val), "r" (__reg), \
38 "i" (ASI_PHYS_BYPASS_EC_E))
40 /* SABRE PCI controller register offsets and definitions. */
41 #define SABRE_UE_AFSR 0x0030UL
42 #define SABRE_UEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
43 #define SABRE_UEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
44 #define SABRE_UEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
45 #define SABRE_UEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
46 #define SABRE_UEAFSR_SDTE 0x0200000000000000UL /* Secondary DMA Translation Error */
47 #define SABRE_UEAFSR_PDTE 0x0100000000000000UL /* Primary DMA Translation Error */
48 #define SABRE_UEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
49 #define SABRE_UEAFSR_OFF 0x00000000e0000000UL /* Offset (AFAR bits [5:3] */
50 #define SABRE_UEAFSR_BLK 0x0000000000800000UL /* Was block operation */
51 #define SABRE_UECE_AFAR 0x0038UL
52 #define SABRE_CE_AFSR 0x0040UL
53 #define SABRE_CEAFSR_PDRD 0x4000000000000000UL /* Primary PCI DMA Read */
54 #define SABRE_CEAFSR_PDWR 0x2000000000000000UL /* Primary PCI DMA Write */
55 #define SABRE_CEAFSR_SDRD 0x0800000000000000UL /* Secondary PCI DMA Read */
56 #define SABRE_CEAFSR_SDWR 0x0400000000000000UL /* Secondary PCI DMA Write */
57 #define SABRE_CEAFSR_ESYND 0x00ff000000000000UL /* ECC Syndrome */
58 #define SABRE_CEAFSR_BMSK 0x0000ffff00000000UL /* Bytemask */
59 #define SABRE_CEAFSR_OFF 0x00000000e0000000UL /* Offset */
60 #define SABRE_CEAFSR_BLK 0x0000000000800000UL /* Was block operation */
61 #define SABRE_UECE_AFAR_ALIAS 0x0048UL /* Aliases to 0x0038 */
62 #define SABRE_IOMMU_CONTROL 0x0200UL
63 #define SABRE_IOMMUCTRL_ERRSTS 0x0000000006000000UL /* Error status bits */
64 #define SABRE_IOMMUCTRL_ERR 0x0000000001000000UL /* Error present in IOTLB */
65 #define SABRE_IOMMUCTRL_LCKEN 0x0000000000800000UL /* IOTLB lock enable */
66 #define SABRE_IOMMUCTRL_LCKPTR 0x0000000000780000UL /* IOTLB lock pointer */
67 #define SABRE_IOMMUCTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
68 #define SABRE_IOMMUCTRL_TBWSZ 0x0000000000000004UL /* TSB assumed page size */
69 #define SABRE_IOMMUCTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
70 #define SABRE_IOMMUCTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
71 #define SABRE_IOMMU_TSBBASE 0x0208UL
72 #define SABRE_IOMMU_FLUSH 0x0210UL
73 #define SABRE_IMAP_A_SLOT0 0x0c00UL
74 #define SABRE_IMAP_B_SLOT0 0x0c20UL
75 #define SABRE_IMAP_SCSI 0x1000UL
76 #define SABRE_IMAP_ETH 0x1008UL
77 #define SABRE_IMAP_BPP 0x1010UL
78 #define SABRE_IMAP_AU_REC 0x1018UL
79 #define SABRE_IMAP_AU_PLAY 0x1020UL
80 #define SABRE_IMAP_PFAIL 0x1028UL
81 #define SABRE_IMAP_KMS 0x1030UL
82 #define SABRE_IMAP_FLPY 0x1038UL
83 #define SABRE_IMAP_SHW 0x1040UL
84 #define SABRE_IMAP_KBD 0x1048UL
85 #define SABRE_IMAP_MS 0x1050UL
86 #define SABRE_IMAP_SER 0x1058UL
87 #define SABRE_IMAP_UE 0x1070UL
88 #define SABRE_IMAP_CE 0x1078UL
89 #define SABRE_IMAP_PCIERR 0x1080UL
90 #define SABRE_IMAP_GFX 0x1098UL
91 #define SABRE_IMAP_EUPA 0x10a0UL
92 #define SABRE_ICLR_A_SLOT0 0x1400UL
93 #define SABRE_ICLR_B_SLOT0 0x1480UL
94 #define SABRE_ICLR_SCSI 0x1800UL
95 #define SABRE_ICLR_ETH 0x1808UL
96 #define SABRE_ICLR_BPP 0x1810UL
97 #define SABRE_ICLR_AU_REC 0x1818UL
98 #define SABRE_ICLR_AU_PLAY 0x1820UL
99 #define SABRE_ICLR_PFAIL 0x1828UL
100 #define SABRE_ICLR_KMS 0x1830UL
101 #define SABRE_ICLR_FLPY 0x1838UL
102 #define SABRE_ICLR_SHW 0x1840UL
103 #define SABRE_ICLR_KBD 0x1848UL
104 #define SABRE_ICLR_MS 0x1850UL
105 #define SABRE_ICLR_SER 0x1858UL
106 #define SABRE_ICLR_UE 0x1870UL
107 #define SABRE_ICLR_CE 0x1878UL
108 #define SABRE_ICLR_PCIERR 0x1880UL
109 #define SABRE_WRSYNC 0x1c20UL
110 #define SABRE_PCICTRL 0x2000UL
111 #define SABRE_PCICTRL_MRLEN 0x0000001000000000UL /* Use MemoryReadLine for block loads/stores */
112 #define SABRE_PCICTRL_SERR 0x0000000400000000UL /* Set when SERR asserted on PCI bus */
113 #define SABRE_PCICTRL_ARBPARK 0x0000000000200000UL /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
114 #define SABRE_PCICTRL_CPUPRIO 0x0000000000100000UL /* Ultra-IIi granted every other bus cycle */
115 #define SABRE_PCICTRL_ARBPRIO 0x00000000000f0000UL /* Slot which is granted every other bus cycle */
116 #define SABRE_PCICTRL_ERREN 0x0000000000000100UL /* PCI Error Interrupt Enable */
117 #define SABRE_PCICTRL_RTRYWE 0x0000000000000080UL /* DMA Flow Control 0=wait-if-possible 1=retry */
118 #define SABRE_PCICTRL_AEN 0x000000000000000fUL /* Slot PCI arbitration enables */
119 #define SABRE_PIOAFSR 0x2010UL
120 #define SABRE_PIOAFSR_PMA 0x8000000000000000UL /* Primary Master Abort */
121 #define SABRE_PIOAFSR_PTA 0x4000000000000000UL /* Primary Target Abort */
122 #define SABRE_PIOAFSR_PRTRY 0x2000000000000000UL /* Primary Excessive Retries */
123 #define SABRE_PIOAFSR_PPERR 0x1000000000000000UL /* Primary Parity Error */
124 #define SABRE_PIOAFSR_SMA 0x0800000000000000UL /* Secondary Master Abort */
125 #define SABRE_PIOAFSR_STA 0x0400000000000000UL /* Secondary Target Abort */
126 #define SABRE_PIOAFSR_SRTRY 0x0200000000000000UL /* Secondary Excessive Retries */
127 #define SABRE_PIOAFSR_SPERR 0x0100000000000000UL /* Secondary Parity Error */
128 #define SABRE_PIOAFSR_BMSK 0x0000ffff00000000UL /* Byte Mask */
129 #define SABRE_PIOAFSR_BLK 0x0000000080000000UL /* Was Block Operation */
130 #define SABRE_PIOAFAR 0x2018UL
131 #define SABRE_PCIDIAG 0x2020UL
132 #define SABRE_PCIDIAG_DRTRY 0x0000000000000040UL /* Disable PIO Retry Limit */
133 #define SABRE_PCIDIAG_IPAPAR 0x0000000000000008UL /* Invert PIO Address Parity */
134 #define SABRE_PCIDIAG_IPDPAR 0x0000000000000004UL /* Invert PIO Data Parity */
135 #define SABRE_PCIDIAG_IDDPAR 0x0000000000000002UL /* Invert DMA Data Parity */
136 #define SABRE_PCIDIAG_ELPBK 0x0000000000000001UL /* Loopback Enable - not supported */
137 #define SABRE_PCITASR 0x2028UL
138 #define SABRE_PCITASR_EF 0x0000000000000080UL /* Respond to 0xe0000000-0xffffffff */
139 #define SABRE_PCITASR_CD 0x0000000000000040UL /* Respond to 0xc0000000-0xdfffffff */
140 #define SABRE_PCITASR_AB 0x0000000000000020UL /* Respond to 0xa0000000-0xbfffffff */
141 #define SABRE_PCITASR_89 0x0000000000000010UL /* Respond to 0x80000000-0x9fffffff */
142 #define SABRE_PCITASR_67 0x0000000000000008UL /* Respond to 0x60000000-0x7fffffff */
143 #define SABRE_PCITASR_45 0x0000000000000004UL /* Respond to 0x40000000-0x5fffffff */
144 #define SABRE_PCITASR_23 0x0000000000000002UL /* Respond to 0x20000000-0x3fffffff */
145 #define SABRE_PCITASR_01 0x0000000000000001UL /* Respond to 0x00000000-0x1fffffff */
146 #define SABRE_PIOBUF_DIAG 0x5000UL
147 #define SABRE_DMABUF_DIAGLO 0x5100UL
148 #define SABRE_DMABUF_DIAGHI 0x51c0UL
149 #define SABRE_IMAP_GFX_ALIAS 0x6000UL /* Aliases to 0x1098 */
150 #define SABRE_IMAP_EUPA_ALIAS 0x8000UL /* Aliases to 0x10a0 */
151 #define SABRE_IOMMU_VADIAG 0xa400UL
152 #define SABRE_IOMMU_TCDIAG 0xa408UL
153 #define SABRE_IOMMU_TAG 0xa580UL
154 #define SABRE_IOMMUTAG_ERRSTS 0x0000000001800000UL /* Error status bits */
155 #define SABRE_IOMMUTAG_ERR 0x0000000000400000UL /* Error present */
156 #define SABRE_IOMMUTAG_WRITE 0x0000000000200000UL /* Page is writable */
157 #define SABRE_IOMMUTAG_STREAM 0x0000000000100000UL /* Streamable bit - unused */
158 #define SABRE_IOMMUTAG_SIZE 0x0000000000080000UL /* 0=8k 1=16k */
159 #define SABRE_IOMMUTAG_VPN 0x000000000007ffffUL /* Virtual Page Number [31:13] */
160 #define SABRE_IOMMU_DATA 0xa600UL
161 #define SABRE_IOMMUDATA_VALID 0x0000000040000000UL /* Valid */
162 #define SABRE_IOMMUDATA_USED 0x0000000020000000UL /* Used (for LRU algorithm) */
163 #define SABRE_IOMMUDATA_CACHE 0x0000000010000000UL /* Cacheable */
164 #define SABRE_IOMMUDATA_PPN 0x00000000001fffffUL /* Physical Page Number [33:13] */
165 #define SABRE_PCI_IRQSTATE 0xa800UL
166 #define SABRE_OBIO_IRQSTATE 0xa808UL
167 #define SABRE_FFBCFG 0xf000UL
168 #define SABRE_FFBCFG_SPRQS 0x000000000f000000 /* Slave P_RQST queue size */
169 #define SABRE_FFBCFG_ONEREAD 0x0000000000004000 /* Slave supports one outstanding read */
170 #define SABRE_MCCTRL0 0xf010UL
171 #define SABRE_MCCTRL0_RENAB 0x0000000080000000 /* Refresh Enable */
172 #define SABRE_MCCTRL0_EENAB 0x0000000010000000 /* Enable all ECC functions */
173 #define SABRE_MCCTRL0_11BIT 0x0000000000001000 /* Enable 11-bit column addressing */
174 #define SABRE_MCCTRL0_DPP 0x0000000000000f00 /* DIMM Pair Present Bits */
175 #define SABRE_MCCTRL0_RINTVL 0x00000000000000ff /* Refresh Interval */
176 #define SABRE_MCCTRL1 0xf018UL
177 #define SABRE_MCCTRL1_AMDC 0x0000000038000000 /* Advance Memdata Clock */
178 #define SABRE_MCCTRL1_ARDC 0x0000000007000000 /* Advance DRAM Read Data Clock */
179 #define SABRE_MCCTRL1_CSR 0x0000000000e00000 /* CAS to RAS delay for CBR refresh */
180 #define SABRE_MCCTRL1_CASRW 0x00000000001c0000 /* CAS length for read/write */
181 #define SABRE_MCCTRL1_RCD 0x0000000000038000 /* RAS to CAS delay */
182 #define SABRE_MCCTRL1_CP 0x0000000000007000 /* CAS Precharge */
183 #define SABRE_MCCTRL1_RP 0x0000000000000e00 /* RAS Precharge */
184 #define SABRE_MCCTRL1_RAS 0x00000000000001c0 /* Length of RAS for refresh */
185 #define SABRE_MCCTRL1_CASRW2 0x0000000000000038 /* Must be same as CASRW */
186 #define SABRE_MCCTRL1_RSC 0x0000000000000007 /* RAS after CAS hold time */
187 #define SABRE_RESETCTRL 0xf020UL
189 #define SABRE_CONFIGSPACE 0x001000000UL
190 #define SABRE_IOSPACE 0x002000000UL
191 #define SABRE_IOSPACE_SIZE 0x00000ffffUL
192 #define SABRE_MEMSPACE 0x100000000UL
193 #define SABRE_MEMSPACE_SIZE 0x07fffffffUL
195 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
196 * configuration space address format:
198 * 32 24 23 16 15 11 10 8 7 2 1 0
199 * ---------------------------------------------------------
200 * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
201 * ---------------------------------------------------------
203 #define SABRE_CONFIG_BASE(PBM) \
204 ((PBM)->parent->config_space | (1UL << 24))
205 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \
206 (((unsigned long)(BUS) << 16) | \
207 ((unsigned long)(DEVFN) << 8) | \
208 ((unsigned long)(REG)))
210 static void *sabre_pci_config_mkaddr(struct pci_pbm_info
*pbm
,
218 (SABRE_CONFIG_BASE(pbm
) |
219 SABRE_CONFIG_ENCODE(bus
, devfn
, where
));
222 static int sabre_out_of_range(unsigned char devfn
)
224 return (((PCI_SLOT(devfn
) == 0) && (PCI_FUNC(devfn
) > 0)) ||
225 ((PCI_SLOT(devfn
) == 1) && (PCI_FUNC(devfn
) > 1)) ||
226 (PCI_SLOT(devfn
) > 1));
229 static int __sabre_out_of_range(struct pci_pbm_info
*pbm
,
233 return ((pbm
->parent
== 0) ||
234 ((pbm
== &pbm
->parent
->pbm_B
) &&
235 (bus
== pbm
->pci_first_busno
) &&
236 PCI_SLOT(devfn
) > 8) ||
237 ((pbm
== &pbm
->parent
->pbm_A
) &&
238 (bus
== pbm
->pci_first_busno
) &&
239 PCI_SLOT(devfn
) > 8));
242 static int __sabre_read_byte(struct pci_dev
*dev
, int where
, u8
*value
)
244 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
245 unsigned char bus
= dev
->bus
->number
;
246 unsigned int devfn
= dev
->devfn
;
250 addr
= sabre_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
252 return PCIBIOS_SUCCESSFUL
;
254 if (__sabre_out_of_range(pbm
, bus
, devfn
))
255 return PCIBIOS_SUCCESSFUL
;
256 pci_config_read8(addr
, value
);
257 return PCIBIOS_SUCCESSFUL
;
260 static int __sabre_read_word(struct pci_dev
*dev
, int where
, u16
*value
)
262 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
263 unsigned char bus
= dev
->bus
->number
;
264 unsigned int devfn
= dev
->devfn
;
268 addr
= sabre_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
270 return PCIBIOS_SUCCESSFUL
;
272 if (__sabre_out_of_range(pbm
, bus
, devfn
))
273 return PCIBIOS_SUCCESSFUL
;
276 printk("pcibios_read_config_word: misaligned reg [%x]\n",
278 return PCIBIOS_SUCCESSFUL
;
280 pci_config_read16(addr
, value
);
281 return PCIBIOS_SUCCESSFUL
;
284 static int __sabre_read_dword(struct pci_dev
*dev
, int where
, u32
*value
)
286 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
287 unsigned char bus
= dev
->bus
->number
;
288 unsigned int devfn
= dev
->devfn
;
292 addr
= sabre_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
294 return PCIBIOS_SUCCESSFUL
;
296 if (__sabre_out_of_range(pbm
, bus
, devfn
))
297 return PCIBIOS_SUCCESSFUL
;
300 printk("pcibios_read_config_dword: misaligned reg [%x]\n",
302 return PCIBIOS_SUCCESSFUL
;
304 pci_config_read32(addr
, value
);
305 return PCIBIOS_SUCCESSFUL
;
308 static int sabre_read_byte(struct pci_dev
*dev
, int where
, u8
*value
)
310 if (dev
->bus
->number
)
311 return __sabre_read_byte(dev
, where
, value
);
313 if (sabre_out_of_range(dev
->devfn
)) {
315 return PCIBIOS_SUCCESSFUL
;
321 __sabre_read_word(dev
, where
& ~1, &tmp
);
326 return PCIBIOS_SUCCESSFUL
;
328 return __sabre_read_byte(dev
, where
, value
);
331 static int sabre_read_word(struct pci_dev
*dev
, int where
, u16
*value
)
333 if (dev
->bus
->number
)
334 return __sabre_read_word(dev
, where
, value
);
336 if (sabre_out_of_range(dev
->devfn
)) {
338 return PCIBIOS_SUCCESSFUL
;
342 return __sabre_read_word(dev
, where
, value
);
346 __sabre_read_byte(dev
, where
, &tmp
);
348 __sabre_read_byte(dev
, where
+ 1, &tmp
);
350 return PCIBIOS_SUCCESSFUL
;
354 static int sabre_read_dword(struct pci_dev
*dev
, int where
, u32
*value
)
358 if (dev
->bus
->number
)
359 return __sabre_read_dword(dev
, where
, value
);
361 if (sabre_out_of_range(dev
->devfn
)) {
363 return PCIBIOS_SUCCESSFUL
;
366 sabre_read_word(dev
, where
, &tmp
);
368 sabre_read_word(dev
, where
+ 2, &tmp
);
370 return PCIBIOS_SUCCESSFUL
;
373 static int __sabre_write_byte(struct pci_dev
*dev
, int where
, u8 value
)
375 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
376 unsigned char bus
= dev
->bus
->number
;
377 unsigned int devfn
= dev
->devfn
;
380 addr
= sabre_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
382 return PCIBIOS_SUCCESSFUL
;
384 if (__sabre_out_of_range(pbm
, bus
, devfn
))
385 return PCIBIOS_SUCCESSFUL
;
386 pci_config_write8(addr
, value
);
387 return PCIBIOS_SUCCESSFUL
;
390 static int __sabre_write_word(struct pci_dev
*dev
, int where
, u16 value
)
392 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
393 unsigned char bus
= dev
->bus
->number
;
394 unsigned int devfn
= dev
->devfn
;
397 addr
= sabre_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
399 return PCIBIOS_SUCCESSFUL
;
401 if (__sabre_out_of_range(pbm
, bus
, devfn
))
402 return PCIBIOS_SUCCESSFUL
;
405 printk("pcibios_write_config_word: misaligned reg [%x]\n",
407 return PCIBIOS_SUCCESSFUL
;
409 pci_config_write16(addr
, value
);
410 return PCIBIOS_SUCCESSFUL
;
413 static int __sabre_write_dword(struct pci_dev
*dev
, int where
, u32 value
)
415 struct pci_pbm_info
*pbm
= pci_bus2pbm
[dev
->bus
->number
];
416 unsigned char bus
= dev
->bus
->number
;
417 unsigned int devfn
= dev
->devfn
;
420 addr
= sabre_pci_config_mkaddr(pbm
, bus
, devfn
, where
);
422 return PCIBIOS_SUCCESSFUL
;
424 if (__sabre_out_of_range(pbm
, bus
, devfn
))
425 return PCIBIOS_SUCCESSFUL
;
428 printk("pcibios_write_config_dword: misaligned reg [%x]\n",
430 return PCIBIOS_SUCCESSFUL
;
432 pci_config_write32(addr
, value
);
433 return PCIBIOS_SUCCESSFUL
;
436 static int sabre_write_byte(struct pci_dev
*dev
, int where
, u8 value
)
438 if (dev
->bus
->number
)
439 return __sabre_write_byte(dev
, where
, value
);
441 if (sabre_out_of_range(dev
->devfn
))
442 return PCIBIOS_SUCCESSFUL
;
447 __sabre_read_word(dev
, where
& ~1, &tmp
);
455 return __sabre_write_word(dev
, where
& ~1, tmp
);
457 return __sabre_write_byte(dev
, where
, value
);
460 static int sabre_write_word(struct pci_dev
*dev
, int where
, u16 value
)
462 if (dev
->bus
->number
)
463 return __sabre_write_word(dev
, where
, value
);
465 if (sabre_out_of_range(dev
->devfn
))
466 return PCIBIOS_SUCCESSFUL
;
469 return __sabre_write_word(dev
, where
, value
);
471 __sabre_write_byte(dev
, where
, value
& 0xff);
472 __sabre_write_byte(dev
, where
+ 1, value
>> 8);
473 return PCIBIOS_SUCCESSFUL
;
477 static int sabre_write_dword(struct pci_dev
*dev
, int where
, u32 value
)
479 if (dev
->bus
->number
)
480 return __sabre_write_dword(dev
, where
, value
);
482 if (sabre_out_of_range(dev
->devfn
))
483 return PCIBIOS_SUCCESSFUL
;
485 sabre_write_word(dev
, where
, value
& 0xffff);
486 sabre_write_word(dev
, where
+ 2, value
>> 16);
487 return PCIBIOS_SUCCESSFUL
;
490 static struct pci_ops sabre_ops
= {
499 static unsigned long sabre_pcislot_imap_offset(unsigned long ino
)
501 unsigned int bus
= (ino
& 0x10) >> 4;
502 unsigned int slot
= (ino
& 0x0c) >> 2;
505 return SABRE_IMAP_A_SLOT0
+ (slot
* 8);
507 return SABRE_IMAP_B_SLOT0
+ (slot
* 8);
510 static unsigned long __onboard_imap_off
[] = {
511 /*0x20*/ SABRE_IMAP_SCSI
,
512 /*0x21*/ SABRE_IMAP_ETH
,
513 /*0x22*/ SABRE_IMAP_BPP
,
514 /*0x23*/ SABRE_IMAP_AU_REC
,
515 /*0x24*/ SABRE_IMAP_AU_PLAY
,
516 /*0x25*/ SABRE_IMAP_PFAIL
,
517 /*0x26*/ SABRE_IMAP_KMS
,
518 /*0x27*/ SABRE_IMAP_FLPY
,
519 /*0x28*/ SABRE_IMAP_SHW
,
520 /*0x29*/ SABRE_IMAP_KBD
,
521 /*0x2a*/ SABRE_IMAP_MS
,
522 /*0x2b*/ SABRE_IMAP_SER
,
523 /*0x2c*/ 0 /* reserved */,
524 /*0x2d*/ 0 /* reserved */,
525 /*0x2e*/ SABRE_IMAP_UE
,
526 /*0x2f*/ SABRE_IMAP_CE
,
527 /*0x30*/ SABRE_IMAP_PCIERR
,
529 #define SABRE_ONBOARD_IRQ_BASE 0x20
530 #define SABRE_ONBOARD_IRQ_LAST 0x30
531 #define sabre_onboard_imap_offset(__ino) \
532 __onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
534 #define sabre_iclr_offset(ino) \
535 ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) : \
536 (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
538 /* PCI SABRE INO number to Sparc PIL level. */
539 static unsigned char sabre_pil_table
[] = {
540 /*0x00*/0, 0, 0, 0, /* PCI A slot 0 Int A, B, C, D */
541 /*0x04*/0, 0, 0, 0, /* PCI A slot 1 Int A, B, C, D */
542 /*0x08*/0, 0, 0, 0, /* PCI A slot 2 Int A, B, C, D */
543 /*0x0c*/0, 0, 0, 0, /* PCI A slot 3 Int A, B, C, D */
544 /*0x10*/0, 0, 0, 0, /* PCI B slot 0 Int A, B, C, D */
545 /*0x14*/0, 0, 0, 0, /* PCI B slot 1 Int A, B, C, D */
546 /*0x18*/0, 0, 0, 0, /* PCI B slot 2 Int A, B, C, D */
547 /*0x1c*/0, 0, 0, 0, /* PCI B slot 3 Int A, B, C, D */
548 /*0x20*/3, /* SCSI */
549 /*0x21*/5, /* Ethernet */
550 /*0x22*/8, /* Parallel Port */
551 /*0x23*/13, /* Audio Record */
552 /*0x24*/14, /* Audio Playback */
553 /*0x25*/15, /* PowerFail */
554 /*0x26*/3, /* second SCSI */
555 /*0x27*/11, /* Floppy */
556 /*0x28*/2, /* Spare Hardware */
557 /*0x29*/9, /* Keyboard */
558 /*0x2a*/4, /* Mouse */
559 /*0x2b*/12, /* Serial */
560 /*0x2c*/10, /* Timer 0 */
561 /*0x2d*/11, /* Timer 1 */
562 /*0x2e*/15, /* Uncorrectable ECC */
563 /*0x2f*/15, /* Correctable ECC */
564 /*0x30*/15, /* PCI Bus A Error */
565 /*0x31*/15, /* PCI Bus B Error */
566 /*0x32*/1, /* Power Management */
569 static int __init
sabre_ino_to_pil(struct pci_dev
*pdev
, unsigned int ino
)
573 ret
= sabre_pil_table
[ino
];
574 if (ret
== 0 && pdev
== NULL
) {
576 } else if (ret
== 0) {
577 switch ((pdev
->class >> 16) & 0x0f) {
578 case PCI_BASE_CLASS_STORAGE
:
581 case PCI_BASE_CLASS_NETWORK
:
584 case PCI_BASE_CLASS_DISPLAY
:
587 case PCI_BASE_CLASS_MULTIMEDIA
:
588 case PCI_BASE_CLASS_MEMORY
:
589 case PCI_BASE_CLASS_BRIDGE
:
599 static unsigned int __init
sabre_irq_build(struct pci_controller_info
*p
,
600 struct pci_dev
*pdev
,
603 struct ino_bucket
*bucket
;
604 volatile unsigned int *imap
, *iclr
;
605 unsigned long imap_off
, iclr_off
;
606 int pil
, inofixup
= 0;
609 if (ino
< SABRE_ONBOARD_IRQ_BASE
) {
611 imap_off
= sabre_pcislot_imap_offset(ino
);
614 if (ino
> SABRE_ONBOARD_IRQ_LAST
) {
615 prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino
);
618 imap_off
= sabre_onboard_imap_offset(ino
);
621 /* Now build the IRQ bucket. */
622 pil
= sabre_ino_to_pil(pdev
, ino
);
623 imap
= (volatile unsigned int *)__va(p
->controller_regs
+ imap_off
);
626 iclr_off
= sabre_iclr_offset(ino
);
627 iclr
= (volatile unsigned int *)__va(p
->controller_regs
+ iclr_off
);
630 if ((ino
& 0x20) == 0)
631 inofixup
= ino
& 0x03;
633 bucket
= __bucket(build_irq(pil
, inofixup
, iclr
, imap
));
634 bucket
->flags
|= IBF_PCI
;
636 /* XXX We still need to code up support for this in irq.c
637 * XXX It's easy to code up since only one SIMBA can exist
638 * XXX in a machine and this is where the sync register is. -DaveM
641 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
642 if (pdev
->bus
->number
!= pcp
->pbm
->pci_first_busno
)
643 bucket
->flags
|= IBF_DMA_SYNC
;
645 return __irq(bucket
);
648 /* SABRE error handling support. */
649 static void sabre_check_iommu_error(struct pci_controller_info
*p
,
653 unsigned long iommu_tag
[16];
654 unsigned long iommu_data
[16];
659 spin_lock_irqsave(&p
->iommu
.lock
, flags
);
660 control
= sabre_read(p
->iommu
.iommu_control
);
661 if (control
& SABRE_IOMMUCTRL_ERR
) {
664 /* Clear the error encountered bit.
665 * NOTE: On Sabre this is write 1 to clear,
666 * which is different from Psycho.
668 sabre_write(p
->iommu
.iommu_control
, control
);
669 switch((control
& SABRE_IOMMUCTRL_ERRSTS
) >> 25UL) {
671 type_string
= "Invalid Error";
674 type_string
= "ECC Error";
677 type_string
= "Unknown";
680 printk("SABRE%d: IOMMU Error, type[%s]\n",
681 p
->index
, type_string
);
683 /* Enter diagnostic mode and probe for error'd
684 * entries in the IOTLB.
686 control
&= ~(SABRE_IOMMUCTRL_ERRSTS
| SABRE_IOMMUCTRL_ERR
);
687 sabre_write(p
->iommu
.iommu_control
,
688 (control
| SABRE_IOMMUCTRL_DENAB
));
689 for (i
= 0; i
< 16; i
++) {
690 unsigned long base
= p
->controller_regs
;
693 sabre_read(base
+ SABRE_IOMMU_TAG
+ (i
* 8UL));
695 sabre_read(base
+ SABRE_IOMMU_DATA
+ (i
* 8UL));
696 sabre_write(base
+ SABRE_IOMMU_TAG
+ (i
* 8UL), 0);
697 sabre_write(base
+ SABRE_IOMMU_DATA
+ (i
* 8UL), 0);
699 sabre_write(p
->iommu
.iommu_control
, control
);
701 for (i
= 0; i
< 16; i
++) {
702 unsigned long tag
, data
;
705 if (!(tag
& SABRE_IOMMUTAG_ERR
))
708 data
= iommu_data
[i
];
709 switch((tag
& SABRE_IOMMUTAG_ERRSTS
) >> 23UL) {
711 type_string
= "Invalid Error";
714 type_string
= "ECC Error";
717 type_string
= "Unknown";
720 printk("SABRE%d: IOMMU TAG(%d)[error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
721 p
->index
, i
, type_string
,
722 ((tag
& SABRE_IOMMUTAG_WRITE
) ? 1 : 0),
723 ((tag
& SABRE_IOMMUTAG_SIZE
) ? 64 : 8),
724 ((tag
& SABRE_IOMMUTAG_VPN
) << PAGE_SHIFT
));
725 printk("SABRE%d: IOMMU DATA(%d)[valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
727 ((data
& SABRE_IOMMUDATA_VALID
) ? 1 : 0),
728 ((data
& SABRE_IOMMUDATA_USED
) ? 1 : 0),
729 ((data
& SABRE_IOMMUDATA_CACHE
) ? 1 : 0),
730 ((data
& SABRE_IOMMUDATA_PPN
) << PAGE_SHIFT
));
733 spin_unlock_irqrestore(&p
->iommu
.lock
, flags
);
736 static void sabre_ue_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
738 struct pci_controller_info
*p
= dev_id
;
739 unsigned long afsr_reg
= p
->controller_regs
+ SABRE_UE_AFSR
;
740 unsigned long afar_reg
= p
->controller_regs
+ SABRE_UECE_AFAR
;
741 unsigned long afsr
, afar
, error_bits
;
744 /* Latch uncorrectable error status. */
745 afar
= sabre_read(afar_reg
);
746 afsr
= sabre_read(afsr_reg
);
748 /* Clear the primary/secondary error status bits. */
750 (SABRE_UEAFSR_PDRD
| SABRE_UEAFSR_PDWR
|
751 SABRE_UEAFSR_SDRD
| SABRE_UEAFSR_SDWR
|
752 SABRE_UEAFSR_SDTE
| SABRE_UEAFSR_PDTE
);
753 sabre_write(afsr_reg
, error_bits
);
756 printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
758 ((error_bits
& SABRE_UEAFSR_PDRD
) ?
760 ((error_bits
& SABRE_UEAFSR_PDWR
) ?
761 "DMA Write" : "???")),
762 ((error_bits
& SABRE_UEAFSR_PDTE
) ?
763 ":Translation Error" : ""));
764 printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
766 (afsr
& SABRE_UEAFSR_BMSK
) >> 32UL,
767 (afsr
& SABRE_UEAFSR_OFF
) >> 29UL,
768 ((afsr
& SABRE_UEAFSR_BLK
) ? 1 : 0));
769 printk("SABRE%d: UE AFAR [%016lx]\n", p
->index
, afar
);
770 printk("SABRE%d: UE Secondary errors [", p
->index
);
772 if (afsr
& SABRE_UEAFSR_SDRD
) {
774 printk("(DMA Read)");
776 if (afsr
& SABRE_UEAFSR_SDWR
) {
778 printk("(DMA Write)");
780 if (afsr
& SABRE_UEAFSR_SDTE
) {
782 printk("(Translation Error)");
788 /* Interrogate IOMMU for error status. */
789 sabre_check_iommu_error(p
, afsr
, afar
);
792 static void sabre_ce_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
794 struct pci_controller_info
*p
= dev_id
;
795 unsigned long afsr_reg
= p
->controller_regs
+ SABRE_CE_AFSR
;
796 unsigned long afar_reg
= p
->controller_regs
+ SABRE_UECE_AFAR
;
797 unsigned long afsr
, afar
, error_bits
;
800 /* Latch error status. */
801 afar
= sabre_read(afar_reg
);
802 afsr
= sabre_read(afsr_reg
);
804 /* Clear primary/secondary error status bits. */
806 (SABRE_CEAFSR_PDRD
| SABRE_CEAFSR_PDWR
|
807 SABRE_CEAFSR_SDRD
| SABRE_CEAFSR_SDWR
);
808 sabre_write(afsr_reg
, error_bits
);
811 printk("SABRE%d: Correctable Error, primary error type[%s]\n",
813 ((error_bits
& SABRE_CEAFSR_PDRD
) ?
815 ((error_bits
& SABRE_CEAFSR_PDWR
) ?
816 "DMA Write" : "???")));
817 printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
820 (afsr
& SABRE_CEAFSR_ESYND
) >> 48UL,
821 (afsr
& SABRE_CEAFSR_BMSK
) >> 32UL,
822 (afsr
& SABRE_CEAFSR_OFF
) >> 29UL,
823 ((afsr
& SABRE_CEAFSR_BLK
) ? 1 : 0));
824 printk("SABRE%d: CE AFAR [%016lx]\n", p
->index
, afar
);
825 printk("SABRE%d: CE Secondary errors [", p
->index
);
827 if (afsr
& SABRE_CEAFSR_SDRD
) {
829 printk("(DMA Read)");
831 if (afsr
& SABRE_CEAFSR_SDWR
) {
833 printk("(DMA Write)");
840 static void sabre_pcierr_intr(int irq
, void *dev_id
, struct pt_regs
*regs
)
842 struct pci_controller_info
*p
= dev_id
;
843 unsigned long afsr_reg
, afar_reg
;
844 unsigned long afsr
, afar
, error_bits
;
847 afsr_reg
= p
->controller_regs
+ SABRE_PIOAFSR
;
848 afar_reg
= p
->controller_regs
+ SABRE_PIOAFAR
;
850 /* Latch error status. */
851 afar
= sabre_read(afar_reg
);
852 afsr
= sabre_read(afsr_reg
);
854 /* Clear primary/secondary error status bits. */
856 (SABRE_PIOAFSR_PMA
| SABRE_PIOAFSR_PTA
|
857 SABRE_PIOAFSR_PRTRY
| SABRE_PIOAFSR_PPERR
|
858 SABRE_PIOAFSR_SMA
| SABRE_PIOAFSR_STA
|
859 SABRE_PIOAFSR_SRTRY
| SABRE_PIOAFSR_SPERR
);
860 sabre_write(afsr_reg
, error_bits
);
863 printk("SABRE%d: PCI Error, primary error type[%s]\n",
865 (((error_bits
& SABRE_PIOAFSR_PMA
) ?
867 ((error_bits
& SABRE_PIOAFSR_PTA
) ?
869 ((error_bits
& SABRE_PIOAFSR_PRTRY
) ?
870 "Excessive Retries" :
871 ((error_bits
& SABRE_PIOAFSR_PPERR
) ?
872 "Parity Error" : "???"))))));
873 printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
875 (afsr
& SABRE_PIOAFSR_BMSK
) >> 32UL,
876 (afsr
& SABRE_PIOAFSR_BLK
) ? 1 : 0);
877 printk("SABRE%d: PCI AFAR [%016lx]\n", p
->index
, afar
);
878 printk("SABRE%d: PCI Secondary errors [", p
->index
);
880 if (afsr
& SABRE_PIOAFSR_SMA
) {
882 printk("(Master Abort)");
884 if (afsr
& SABRE_PIOAFSR_STA
) {
886 printk("(Target Abort)");
888 if (afsr
& SABRE_PIOAFSR_SRTRY
) {
890 printk("(Excessive Retries)");
892 if (afsr
& SABRE_PIOAFSR_SPERR
) {
894 printk("(Parity Error)");
900 /* For the error types shown, scan both PCI buses for devices
901 * which have logged that error type.
904 /* If we see a Target Abort, this could be the result of an
905 * IOMMU translation error of some sort. It is extremely
906 * useful to log this information as usually it indicates
907 * a bug in the IOMMU support code or a PCI device driver.
909 if (error_bits
& (SABRE_PIOAFSR_PTA
| SABRE_PIOAFSR_STA
)) {
910 sabre_check_iommu_error(p
, afsr
, afar
);
911 pci_scan_for_target_abort(p
, &p
->pbm_A
, p
->pbm_A
.pci_bus
);
912 pci_scan_for_target_abort(p
, &p
->pbm_B
, p
->pbm_B
.pci_bus
);
914 if (error_bits
& (SABRE_PIOAFSR_PMA
| SABRE_PIOAFSR_SMA
)) {
915 pci_scan_for_master_abort(p
, &p
->pbm_A
, p
->pbm_A
.pci_bus
);
916 pci_scan_for_master_abort(p
, &p
->pbm_B
, p
->pbm_B
.pci_bus
);
918 /* For excessive retries, SABRE/PBM will abort the device
919 * and there is no way to specifically check for excessive
920 * retries in the config space status registers. So what
921 * we hope is that we'll catch it via the master/target
925 if (error_bits
& (SABRE_PIOAFSR_PPERR
| SABRE_PIOAFSR_SPERR
)) {
926 pci_scan_for_parity_error(p
, &p
->pbm_A
, p
->pbm_A
.pci_bus
);
927 pci_scan_for_parity_error(p
, &p
->pbm_B
, p
->pbm_B
.pci_bus
);
931 /* XXX What about PowerFail/PowerManagement??? -DaveM */
932 #define SABRE_UE_INO 0x2e
933 #define SABRE_CE_INO 0x2f
934 #define SABRE_PCIERR_INO 0x30
935 static void __init
sabre_register_error_handlers(struct pci_controller_info
*p
)
937 unsigned long base
= p
->controller_regs
;
938 unsigned long irq
, portid
= p
->portid
;
941 /* We clear the error bits in the appropriate AFSR before
942 * registering the handler so that we don't get spurious
945 sabre_write(base
+ SABRE_UE_AFSR
,
946 (SABRE_UEAFSR_PDRD
| SABRE_UEAFSR_PDWR
|
947 SABRE_UEAFSR_SDRD
| SABRE_UEAFSR_SDWR
|
948 SABRE_UEAFSR_SDTE
| SABRE_UEAFSR_PDTE
));
949 irq
= sabre_irq_build(p
, NULL
, (portid
<< 6) | SABRE_UE_INO
);
950 if (request_irq(irq
, sabre_ue_intr
,
951 SA_SHIRQ
, "SABRE UE", p
) < 0) {
952 prom_printf("SABRE%d: Cannot register UE interrupt.\n",
957 sabre_write(base
+ SABRE_CE_AFSR
,
958 (SABRE_CEAFSR_PDRD
| SABRE_CEAFSR_PDWR
|
959 SABRE_CEAFSR_SDRD
| SABRE_CEAFSR_SDWR
));
960 irq
= sabre_irq_build(p
, NULL
, (portid
<< 6) | SABRE_CE_INO
);
961 if (request_irq(irq
, sabre_ce_intr
,
962 SA_SHIRQ
, "SABRE CE", p
) < 0) {
963 prom_printf("SABRE%d: Cannot register CE interrupt.\n",
968 irq
= sabre_irq_build(p
, NULL
, (portid
<< 6) | SABRE_PCIERR_INO
);
969 if (request_irq(irq
, sabre_pcierr_intr
,
970 SA_SHIRQ
, "SABRE PCIERR", p
) < 0) {
971 prom_printf("SABRE%d: Cannot register PciERR interrupt.\n",
976 tmp
= sabre_read(base
+ SABRE_PCICTRL
);
977 tmp
|= SABRE_PCICTRL_ERREN
;
978 sabre_write(base
+ SABRE_PCICTRL
, tmp
);
981 static void __init
sabre_resource_adjust(struct pci_dev
*pdev
,
982 struct resource
*res
,
983 struct resource
*root
)
985 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
986 struct pci_controller_info
*p
= pcp
->pbm
->parent
;
989 if (res
->flags
& IORESOURCE_IO
)
990 base
= p
->controller_regs
+ SABRE_IOSPACE
;
992 base
= p
->controller_regs
+ SABRE_MEMSPACE
;
998 static void __init
sabre_base_address_update(struct pci_dev
*pdev
, int resource
)
1000 struct pcidev_cookie
*pcp
= pdev
->sysdata
;
1001 struct pci_pbm_info
*pbm
= pcp
->pbm
;
1002 struct pci_controller_info
*p
= pbm
->parent
;
1003 struct resource
*res
= &pdev
->resource
[resource
];
1008 if (res
->flags
& IORESOURCE_IO
)
1009 base
= p
->controller_regs
+ SABRE_IOSPACE
;
1011 base
= p
->controller_regs
+ SABRE_MEMSPACE
;
1013 where
= PCI_BASE_ADDRESS_0
+ (resource
* 4);
1014 size
= res
->end
- res
->start
;
1015 pci_read_config_dword(pdev
, where
, ®
);
1016 reg
= ((reg
& size
) |
1017 (((u32
)(res
->start
- base
)) & ~size
));
1018 pci_write_config_dword(pdev
, where
, reg
);
1021 static void __init
apb_init(struct pci_controller_info
*p
, struct pci_bus
*sabre_bus
)
1023 struct pci_dev
*pdev
;
1027 for(pdev
= pci_devices
; pdev
; pdev
= pdev
->next
) {
1028 if(pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1029 pdev
->device
== PCI_DEVICE_ID_SUN_SABRE
) {
1030 sabre_write_byte(pdev
, PCI_LATENCY_TIMER
, 64);
1035 for (pdev
= sabre_bus
->devices
; pdev
; pdev
= pdev
->sibling
) {
1036 if (pdev
->vendor
== PCI_VENDOR_ID_SUN
&&
1037 pdev
->device
== PCI_DEVICE_ID_SUN_SIMBA
) {
1038 sabre_read_word(pdev
, PCI_COMMAND
, &word
);
1039 word
|= PCI_COMMAND_SERR
| PCI_COMMAND_PARITY
|
1040 PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
|
1042 sabre_write_word(pdev
, PCI_COMMAND
, word
);
1044 /* Status register bits are "write 1 to clear". */
1045 sabre_write_word(pdev
, PCI_STATUS
, 0xffff);
1046 sabre_write_word(pdev
, PCI_SEC_STATUS
, 0xffff);
1048 sabre_read_word(pdev
, PCI_BRIDGE_CONTROL
, &word
);
1049 word
= PCI_BRIDGE_CTL_MASTER_ABORT
|
1050 PCI_BRIDGE_CTL_SERR
|
1051 PCI_BRIDGE_CTL_PARITY
;
1052 sabre_write_word(pdev
, PCI_BRIDGE_CONTROL
, word
);
1054 sabre_read_dword(pdev
, APB_PCI_CONTROL_HIGH
, &dword
);
1055 dword
= APB_PCI_CTL_HIGH_SERR
|
1056 APB_PCI_CTL_HIGH_ARBITER_EN
;
1057 sabre_write_dword(pdev
, APB_PCI_CONTROL_HIGH
, dword
);
1059 /* Systems with SIMBA are usually workstations, so
1060 * we configure to park to SIMBA not to the previous
1063 sabre_read_dword(pdev
, APB_PCI_CONTROL_LOW
, &dword
);
1064 dword
= APB_PCI_CTL_LOW_ERRINT_EN
| 0x0f;
1065 sabre_write_dword(pdev
, APB_PCI_CONTROL_LOW
, dword
);
1067 /* Don't mess with the retry limit and PIO/DMA latency
1068 * timer settings. But do set primary and secondary
1071 sabre_write_byte(pdev
, PCI_LATENCY_TIMER
, 64);
1072 sabre_write_byte(pdev
, PCI_SEC_LATENCY_TIMER
, 64);
1077 static void __init
sabre_scan_bus(struct pci_controller_info
*p
)
1079 static int once
= 0;
1080 struct pci_bus
*sabre_bus
, *pbus
;
1082 /* Unlike for PSYCHO, we can only have one SABRE
1083 * in a system. Having multiple SABREs is thus
1084 * and error, and as a consequence we do not need
1085 * to do any bus renumbering but we do have to have
1086 * the pci_bus2pbm array setup properly.
1088 * Also note that the SABRE host bridge is hardwired
1092 prom_printf("SABRE: Multiple controllers unsupported.\n");
1097 /* The pci_bus2pbm table has already been setup in sabre_init. */
1098 sabre_bus
= pci_scan_bus(p
->pci_first_busno
,
1101 apb_init(p
, sabre_bus
);
1103 for (pbus
= sabre_bus
->children
; pbus
; pbus
= pbus
->next
) {
1104 struct pci_pbm_info
*pbm
;
1106 if (pbus
->number
== p
->pbm_A
.pci_first_busno
) {
1108 } else if (pbus
->number
== p
->pbm_B
.pci_first_busno
) {
1113 pbus
->sysdata
= pbm
;
1114 pbm
->pci_bus
= pbus
;
1115 pci_fill_in_pbm_cookies(pbus
, pbm
, pbm
->prom_node
);
1116 pci_record_assignments(pbm
, pbus
);
1117 pci_assign_unassigned(pbm
, pbus
);
1118 pci_fixup_irq(pbm
, pbus
);
1121 sabre_register_error_handlers(p
);
1124 static void __init
sabre_iommu_init(struct pci_controller_info
*p
,
1125 int tsbsize
, unsigned long dvma_offset
)
1127 struct linux_mlist_p1275
*mlist
;
1128 unsigned long tsbbase
, i
, n
, order
;
1132 /* Invalidate TLB Entries. */
1133 control
= sabre_read(p
->controller_regs
+ SABRE_IOMMU_CONTROL
);
1134 control
|= IOMMU_CTRL_DENAB
;
1135 sabre_write(p
->controller_regs
+ SABRE_IOMMU_CONTROL
, control
);
1137 for(i
= 0; i
< 16; i
++)
1138 sabre_write(p
->controller_regs
+ SABRE_IOMMU_DATA
+ (i
* 8UL), 0);
1140 control
&= ~(IOMMU_CTRL_DENAB
);
1141 sabre_write(p
->controller_regs
+ SABRE_IOMMU_CONTROL
, control
);
1143 for(order
= 0;; order
++)
1144 if((PAGE_SIZE
<< order
) >= ((tsbsize
* 1024) * 8))
1146 tsbbase
= __get_free_pages(GFP_DMA
, order
);
1148 prom_printf("SABRE_IOMMU: Error, gfp(tsb) failed.\n");
1151 iopte
= (iopte_t
*)tsbbase
;
1153 /* Initialize to "none" settings. */
1154 for(i
= 0; i
< PCI_DVMA_HASHSZ
; i
++) {
1155 pci_dvma_v2p_hash
[i
] = PCI_DVMA_HASH_NONE
;
1156 pci_dvma_p2v_hash
[i
] = PCI_DVMA_HASH_NONE
;
1160 mlist
= *prom_meminfo()->p1275_totphys
;
1162 unsigned long paddr
= mlist
->start_adr
;
1163 unsigned long num_bytes
= mlist
->num_bytes
;
1165 if(paddr
>= (((unsigned long) high_memory
) - PAGE_OFFSET
))
1168 if((paddr
+ num_bytes
) >= (((unsigned long) high_memory
) - PAGE_OFFSET
))
1170 (((unsigned long) high_memory
) -
1171 PAGE_OFFSET
) - paddr
;
1173 /* Align base and length so we map whole hash table sized chunks
1174 * at a time (and therefore full 64K IOMMU pages).
1176 paddr
&= ~((1UL << 24UL) - 1);
1177 num_bytes
= (num_bytes
+ ((1UL << 24UL) - 1)) & ~((1UL << 24) - 1);
1179 /* Move up the base for mappings already created. */
1180 while(pci_dvma_v2p_hash
[pci_dvma_ahashfn(paddr
)] !=
1181 PCI_DVMA_HASH_NONE
) {
1182 paddr
+= (1UL << 24UL);
1183 num_bytes
-= (1UL << 24UL);
1184 if(num_bytes
== 0UL)
1188 /* Move down the size for tail mappings already created. */
1189 while(pci_dvma_v2p_hash
[pci_dvma_ahashfn(paddr
+ num_bytes
- (1UL << 24UL))] !=
1190 PCI_DVMA_HASH_NONE
) {
1191 num_bytes
-= (1UL << 24UL);
1192 if(num_bytes
== 0UL)
1196 /* Now map the rest. */
1197 for (i
= 0; i
< ((num_bytes
+ ((1 << 16) - 1)) >> 16); i
++) {
1198 iopte_val(*iopte
) = ((IOPTE_VALID
| IOPTE_64K
|
1199 IOPTE_CACHE
| IOPTE_WRITE
) |
1200 (paddr
& IOPTE_PAGE
));
1203 set_dvma_hash(dvma_offset
, paddr
, (n
<< 16));
1204 if (++n
> (tsbsize
* 1024))
1211 mlist
= mlist
->theres_more
;
1215 prom_printf("WARNING: not all physical memory mapped in IOMMU\n");
1216 prom_printf("Try booting with mem=xxxM or similar\n");
1220 sabre_write(p
->controller_regs
+ SABRE_IOMMU_TSBBASE
, __pa(tsbbase
));
1222 control
= sabre_read(p
->controller_regs
+ SABRE_IOMMU_CONTROL
);
1223 control
&= ~(IOMMU_CTRL_TSBSZ
);
1224 control
|= (IOMMU_CTRL_TBWSZ
| IOMMU_CTRL_ENAB
);
1227 control
|= IOMMU_TSBSZ_8K
;
1230 control
|= IOMMU_TSBSZ_16K
;
1233 control
|= IOMMU_TSBSZ_32K
;
1236 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize
);
1240 sabre_write(p
->controller_regs
+ SABRE_IOMMU_CONTROL
, control
);
1243 static void __init
pbm_register_toplevel_resources(struct pci_controller_info
*p
,
1244 struct pci_pbm_info
*pbm
)
1246 char *name
= pbm
->name
;
1247 unsigned long ibase
= p
->controller_regs
+ SABRE_IOSPACE
;
1248 unsigned long mbase
= p
->controller_regs
+ SABRE_MEMSPACE
;
1250 unsigned long first
, last
, i
;
1253 sprintf(name
, "SABRE%d PBM%c",
1255 (pbm
== &p
->pbm_A
? 'A' : 'B'));
1256 pbm
->io_space
.name
= pbm
->mem_space
.name
= name
;
1258 devfn
= PCI_DEVFN(1, (pbm
== &p
->pbm_A
) ? 0 : 1);
1259 addr
= sabre_pci_config_mkaddr(pbm
, 0, devfn
, APB_IO_ADDRESS_MAP
);
1261 pci_config_read8(addr
, &map
);
1265 for (i
= 0; i
< 8; i
++) {
1266 if ((map
& (1 << i
)) != 0) {
1273 pbm
->io_space
.start
= ibase
+ (first
<< 21UL);
1274 pbm
->io_space
.end
= ibase
+ (last
<< 21UL) + ((1 << 21UL) - 1);
1275 pbm
->io_space
.flags
= IORESOURCE_IO
;
1277 addr
= sabre_pci_config_mkaddr(pbm
, 0, devfn
, APB_MEM_ADDRESS_MAP
);
1279 pci_config_read8(addr
, &map
);
1283 for (i
= 0; i
< 8; i
++) {
1284 if ((map
& (1 << i
)) != 0) {
1291 pbm
->mem_space
.start
= mbase
+ (first
<< 29UL);
1292 pbm
->mem_space
.end
= mbase
+ (last
<< 29UL) + ((1 << 29UL) - 1);
1293 pbm
->mem_space
.flags
= IORESOURCE_MEM
;
1295 if (request_resource(&ioport_resource
, &pbm
->io_space
) < 0) {
1296 prom_printf("Cannot register PBM-%c's IO space.\n",
1297 (pbm
== &p
->pbm_A
? 'A' : 'B'));
1300 if (request_resource(&iomem_resource
, &pbm
->mem_space
) < 0) {
1301 prom_printf("Cannot register PBM-%c's MEM space.\n",
1302 (pbm
== &p
->pbm_A
? 'A' : 'B'));
1307 static void __init
sabre_pbm_init(struct pci_controller_info
*p
, int sabre_node
)
1313 node
= prom_getchild(sabre_node
);
1314 while ((node
= prom_searchsiblings(node
, "pci")) != 0) {
1315 struct pci_pbm_info
*pbm
;
1318 err
= prom_getproperty(node
, "model", namebuf
, sizeof(namebuf
));
1319 if ((err
<= 0) || strncmp(namebuf
, "SUNW,simba", err
))
1322 err
= prom_getproperty(node
, "bus-range",
1323 (char *)&busrange
[0], sizeof(busrange
));
1324 if (err
== 0 || err
== -1) {
1325 prom_printf("APB: Error, cannot get PCI bus-range.\n");
1329 if (busrange
[0] == 1)
1334 pbm
->prom_node
= node
;
1335 pbm
->pci_first_busno
= busrange
[0];
1336 pbm
->pci_last_busno
= busrange
[1];
1337 for (err
= pbm
->pci_first_busno
;
1338 err
<= pbm
->pci_last_busno
;
1340 pci_bus2pbm
[err
] = pbm
;
1343 prom_getstring(node
, "name", pbm
->prom_name
, sizeof(pbm
->prom_name
));
1344 err
= prom_getproperty(node
, "ranges",
1345 (char *)pbm
->pbm_ranges
,
1346 sizeof(pbm
->pbm_ranges
));
1348 pbm
->num_pbm_ranges
=
1349 (err
/ sizeof(struct linux_prom_pci_ranges
));
1351 pbm
->num_pbm_ranges
= 0;
1353 err
= prom_getproperty(node
, "interrupt-map",
1354 (char *)pbm
->pbm_intmap
,
1355 sizeof(pbm
->pbm_intmap
));
1357 pbm
->num_pbm_intmap
= (err
/ sizeof(struct linux_prom_pci_intmap
));
1358 err
= prom_getproperty(node
, "interrupt-map-mask",
1359 (char *)&pbm
->pbm_intmask
,
1360 sizeof(pbm
->pbm_intmask
));
1362 prom_printf("APB: Fatal error, no interrupt-map-mask.\n");
1366 pbm
->num_pbm_intmap
= 0;
1367 memset(&pbm
->pbm_intmask
, 0, sizeof(pbm
->pbm_intmask
));
1370 pbm_register_toplevel_resources(p
, pbm
);
1373 node
= prom_getsibling(node
);
1379 void __init
sabre_init(int pnode
)
1381 struct linux_prom64_registers pr_regs
[2];
1382 struct pci_controller_info
*p
;
1383 unsigned long flags
;
1390 p
= kmalloc(sizeof(*p
), GFP_ATOMIC
);
1392 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1396 upa_portid
= prom_getintdefault(pnode
, "upa-portid", 0xff);
1398 memset(p
, 0, sizeof(*p
));
1400 spin_lock_irqsave(&pci_controller_lock
, flags
);
1401 p
->next
= pci_controller_root
;
1402 pci_controller_root
= p
;
1403 spin_unlock_irqrestore(&pci_controller_lock
, flags
);
1405 p
->portid
= upa_portid
;
1406 p
->index
= pci_num_controllers
++;
1407 p
->scan_bus
= sabre_scan_bus
;
1408 p
->irq_build
= sabre_irq_build
;
1409 p
->base_address_update
= sabre_base_address_update
;
1410 p
->resource_adjust
= sabre_resource_adjust
;
1411 p
->pci_ops
= &sabre_ops
;
1414 * Map in SABRE register set and report the presence of this SABRE.
1416 err
= prom_getproperty(pnode
, "reg",
1417 (char *)&pr_regs
[0], sizeof(pr_regs
));
1418 if(err
== 0 || err
== -1) {
1419 prom_printf("SABRE: Error, cannot get U2P registers "
1425 * First REG in property is base of entire SABRE register space.
1427 p
->controller_regs
= pr_regs
[0].phys_addr
;
1428 printk("PCI: Found SABRE, main regs at %016lx\n", p
->controller_regs
);
1430 /* Error interrupts are enabled later after the bus scan. */
1431 sabre_write(p
->controller_regs
+ SABRE_PCICTRL
,
1432 (SABRE_PCICTRL_MRLEN
| SABRE_PCICTRL_SERR
|
1433 SABRE_PCICTRL_ARBPARK
| SABRE_PCICTRL_AEN
));
1435 /* Now map in PCI config space for entire SABRE. */
1436 p
->config_space
= p
->controller_regs
+ SABRE_CONFIGSPACE
;
1437 printk("SABRE: PCI config space at %016lx\n", p
->config_space
);
1439 err
= prom_getproperty(pnode
, "virtual-dma",
1440 (char *)&vdma
[0], sizeof(vdma
));
1441 if(err
== 0 || err
== -1) {
1442 prom_printf("SABRE: Error, cannot get virtual-dma property "
1458 prom_printf("SABRE: strange virtual-dma size.\n");
1462 sabre_iommu_init(p
, tsbsize
, vdma
[0]);
1464 printk("SABRE: DVMA at %08x [%08x]\n", vdma
[0], vdma
[1]);
1466 err
= prom_getproperty(pnode
, "bus-range",
1467 (char *)&busrange
[0], sizeof(busrange
));
1468 if(err
== 0 || err
== -1) {
1469 prom_printf("SABRE: Error, cannot get PCI bus-range "
1474 p
->pci_first_busno
= busrange
[0];
1475 p
->pci_last_busno
= busrange
[1];
1478 * Handle config space reads through any Simba on APB.
1480 for (bus
= p
->pci_first_busno
; bus
<= p
->pci_last_busno
; bus
++)
1481 pci_bus2pbm
[bus
] = &p
->pbm_A
;
1484 * Look for APB underneath.
1486 sabre_pbm_init(p
, pnode
);