arch/ppc/kernel/gemini_setup.c

   1 /*
   2  *  linux/arch/ppc/kernel/setup.c
   3  *
   4  *  Copyright (C) 1995 Linus Torvalds
   5  *  Adapted from 'alpha' version by Gary Thomas
   6  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   7  *  Synergy Microsystems board support by Dan Cox (dan@synergymicro.com)
   8  *
   9  */
  10
  11 #include <linux/config.h>
  12 #include <linux/stddef.h>
  13 #include <linux/kernel.h>
  14 #include <linux/init.h>
  15 #include <linux/errno.h>
  16 #include <linux/reboot.h>
  17 #include <linux/pci.h>
  18 #include <linux/kdev_t.h>
  19 #include <linux/types.h>
  20 #include <linux/major.h>
  21 #include <linux/blk.h>
  22 #include <linux/console.h>
  23 #include <linux/openpic.h>
  24
  25 #include <asm/system.h>
  26 #include <asm/pgtable.h>
  27 #include <asm/page.h>
  28 #include <asm/dma.h>
  29 #include <asm/io.h>
  30 #include <asm/m48t35.h>
  31 #include <asm/gemini.h>
  32
  33 #include "time.h"
  34 #include "local_irq.h"
  35 #include "open_pic.h"
  36
  37 void gemini_setup_pci_ptrs(void);
  38
  39 static int l2_printed = 0;
  40 static unsigned char gemini_switch_map = 0;
  41 static char *gemini_board_families[] = {
  42         "VGM", "VSS", "KGM", "VGR", "KSS"
  43 };
  44
  45 static char *gemini_memtypes[] = {
  46         "EDO DRAM, 60nS", "SDRAM, 15nS, CL=2", "SDRAM, 15nS, CL=2 with ECC"
  47 };
  48
  49 static unsigned int cpu_7xx[16] = {
  50         0, 15, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 16, 12, 7, 0
  51 };
  52 static unsigned int cpu_6xx[16] = {
  53         0, 0, 14, 0, 0, 13, 5, 9, 6, 11, 8, 10, 0, 12, 7, 0
  54 };
  55
  56
  57 static inline unsigned long _get_HID1(void)
  58 {
  59         unsigned long val;
  60
  61         __asm__ __volatile__("mfspr %0,1009" : "=r" (val));
  62         return val;
  63 }
  64
  65 int
  66 gemini_get_cpuinfo(char *buffer)
  67 {
  68         int i, len;
  69         unsigned char reg, rev;
  70         char *family;
  71         unsigned int type;
  72
  73         reg = readb(GEMINI_FEAT);
  74         family = gemini_board_families[((reg>>4) & 0xf)];
  75         if (((reg>>4) & 0xf) > 2)
  76                 printk(KERN_ERR "cpuinfo(): unable to determine board family\n");
  77
  78         reg = readb(GEMINI_BREV);
  79         type = (reg>>4) & 0xf;
  80         rev = reg & 0xf;
  81
  82         reg = readb(GEMINI_BECO);
  83
  84         len = sprintf( buffer, "machine\t\t: Gemini %s%d, rev %c, eco %d\n",
  85                        family, type, (rev + 'A'), (reg & 0xf));
  86
  87         len += sprintf( buffer+len, "vendor\t\t: %s\n",
  88                         (_get_PVR() & (1<<15)) ? "IBM" : "Motorola");
  89
  90         reg = readb(GEMINI_MEMCFG);
  91         len += sprintf( buffer+len, "memory type\t: %s\n",
  92                         gemini_memtypes[(reg & 0xc0)>>6]);
  93         len += sprintf( buffer+len, "switches on\t: ");
  94         for( i=0; i < 8; i++ ) {
  95                 if ( gemini_switch_map & (1<<i))
  96                         len += sprintf(buffer+len, "%d ", i);
  97         }
  98         len += sprintf(buffer+len, "\n");
  99
 100         return len;
 101 }
 102
 103 static u_char gemini_openpic_initsenses[] = {
 104         1,
 105         1,
 106         1,
 107         1,
 108         0,
 109         0,
 110         1, /* remainder are level-triggered */
 111 };
 112
 113 #define GEMINI_MPIC_ADDR (0xfcfc0000)
 114 #define GEMINI_MPIC_PCI_CFG (0x80005800)
 115
 116 void __init gemini_openpic_init(void)
 117 {
 118         grackle_write(GEMINI_MPIC_PCI_CFG + PCI_BASE_ADDRESS_0,
 119                       GEMINI_MPIC_ADDR);
 120         grackle_write(GEMINI_MPIC_PCI_CFG + PCI_COMMAND, PCI_COMMAND_MEMORY);
 121
 122         OpenPIC = (volatile struct OpenPIC *) GEMINI_MPIC_ADDR;
 123         OpenPIC_InitSenses = gemini_openpic_initsenses;
 124         OpenPIC_NumInitSenses = sizeof( gemini_openpic_initsenses );
 125
 126         ioremap( GEMINI_MPIC_ADDR, sizeof( struct OpenPIC ));
 127 }
 128
 129
 130 extern unsigned long loops_per_sec;
 131 extern int root_mountflags;
 132 extern char cmd_line[];
 133
 134
 135 void __init gemini_setup_arch(unsigned long *memstart, unsigned long *memend)
 136 {
 137         unsigned int cpu;
 138         extern char cmd_line[];
 139
 140
 141         loops_per_sec = 50000000;
 142
 143 #ifdef CONFIG_BLK_DEV_INITRD
 144         /* bootable off CDROM */
 145         if (initrd_start)
 146                 ROOT_DEV = MKDEV(SCSI_CDROM_MAJOR, 0);
 147         else
 148 #endif
 149                 ROOT_DEV = to_kdev_t(0x0801);
 150
 151         /* nothing but serial consoles... */
 152         sprintf(cmd_line, "%s console=ttyS0", cmd_line);
 153
 154
 155         /* The user switches on the front panel can be used as follows:
 156
 157            Switch 0 - adds "debug" to the command line for verbose boot info,
 158            Switch 7 - boots in single-user mode
 159
 160         */
 161
 162         gemini_switch_map = readb( GEMINI_USWITCH );
 163
 164         if ( gemini_switch_map & (1<<GEMINI_SWITCH_VERBOSE))
 165                 sprintf(cmd_line, "%s debug", cmd_line);
 166
 167         if ( gemini_switch_map & (1<<GEMINI_SWITCH_SINGLE_USER))
 168                 sprintf(cmd_line, "%s single", cmd_line);
 169
 170         printk("Boot arguments: %s\n", cmd_line);
 171
 172         /* mutter some kind words about who made the CPU */
 173         cpu = _get_PVR();
 174         printk("CPU manufacturer: %s [rev=%04x]\n", (cpu & (1<<15)) ? "IBM" :
 175                "Motorola", (cpu & 0xffff));
 176
 177         /* take special pains to map the MPIC, since it isn't mapped yet */
 178         gemini_openpic_init();
 179
 180         /* start the L2 */
 181         gemini_init_l2();
 182
 183 }
 184
 185
 186 int
 187 gemini_get_clock_speed(void)
 188 {
 189         unsigned long hid1;
 190         int clock;
 191         unsigned char reg;
 192
 193         hid1 = _get_HID1();
 194         if ((_get_PVR()>>16) == 8)
 195                 hid1 = cpu_7xx[hid1];
 196         else
 197                 hid1 = cpu_6xx[hid1];
 198
 199         reg = readb(GEMINI_BSTAT) & 0xc0;
 200
 201         switch( reg >> 2 ) {
 202
 203         case 0:
 204         default:
 205                 clock = (hid1*100)/3;
 206                 break;
 207
 208         case 1:
 209                 clock = (hid1*125)/3;
 210                 break;
 211
 212         case 2:
 213                 clock = (hid1*50)/3;
 214                 break;
 215         }
 216
 217         return clock;
 218 }
 219
 220
 221 #define L2CR_PIPE_LATEWR   (0x01800000)   /* late-write SRAM */
 222 #define L2CR_L2CTL         (0x00100000)   /* RAM control */
 223 #define L2CR_INST_DISABLE  (0x00400000)   /* disable for insn's */
 224 #define L2CR_L2I           (0x00200000)   /* global invalidate */
 225 #define L2CR_L2E           (0x80000000)   /* enable */
 226 #define L2CR_L2WT          (0x00080000)   /* write-through */
 227
 228 void __init gemini_init_l2(void)
 229 {
 230         unsigned char reg;
 231         unsigned long cache;
 232         int speed;
 233
 234         reg = readb(GEMINI_L2CFG);
 235
 236         /* 750's L2 initializes differently from a 604's.  Also note that a Grackle
 237            bug will hang a dual-604 board, so make sure that doesn't happen by not
 238            turning on the L2 */
 239         if ( _get_PVR() >> 16 != 8 ) {
 240
 241                 /* check for dual cpus and cry sadly about the loss of an L2... */
 242                 if ((( readb(GEMINI_CPUSTAT) & 0x0c ) >> 2) != 1)
 243                         printk("Sorry. Your dual-604 does not allow the L2 to be enabled due "
 244                                "to a Grackle bug.\n");
 245                 else if ( reg & GEMINI_L2_SIZE_MASK ) {
 246                         printk("Enabling 604 L2 cache: %dKb\n",
 247                                (128<<((reg & GEMINI_L2_SIZE_MASK)>>6)));
 248                         writeb( 1, GEMINI_L2CFG );
 249                 }
 250         }
 251
 252         /* do a 750 */
 253         else {
 254                 /* Synergy's first round of 750 boards had the L2 size stuff into the
 255                    board register above.  If it's there, it's used; if not, the
 256                    standard default is 1Mb.  The L2 type, I'm told, is "most likely
 257                    probably always going to be late-write".  --Dan */
 258
 259                 if (reg & 0xc0) {
 260                         if (!l2_printed) {
 261                                 printk("Enabling 750 L2 cache: %dKb\n",
 262                                        (128 << ((reg & 0xc0)>>6)));
 263                                 l2_printed=1;
 264                         }
 265
 266                         /* take the size given */
 267                         cache = (((reg>>6) & 0x3)<<28);
 268                 }
 269                 else
 270                         /* default of 1Mb */
 271                         cache = 0x3<<28;
 272
 273                 reg &= 0x3;
 274
 275                 /* a cache ratio of 1:1 and CPU clock speeds in excess of 300Mhz are bad
 276                    things.  If found, tune it down to 1:1.5.  -- Dan */
 277                 if (!reg) {
 278
 279                         speed = gemini_get_clock_speed();
 280
 281                         if (speed >= 300) {
 282                                 printk("Warning:  L2 ratio is 1:1 on a %dMhz processor.  Dropping to 1:1.5.\n",
 283                                        speed );
 284                                 printk("Contact Synergy Microsystems for an ECO to fix this problem\n");
 285                                 reg = 0x1;
 286                         }
 287                 }
 288
 289                 /* standard stuff */
 290                 cache |= ((1<<reg)<<25);
 291 #ifdef __SMP__
 292                 /* A couple errata for the 750's (both IBM and Motorola silicon)
 293                    note that you can get missed cache lines on MP implementations.
 294                    The workaround - if you call it that - is to make the L2
 295                    write-through.  This is fixed in IBM's 3.1 rev (I'm told), but
 296                    for now, always make 2.x versions use L2 write-through. --Dan */
 297                 if (((_get_PVR()>>8) & 0xf) <= 2)
 298                         cache |= L2CR_L2WT;
 299 #endif
 300                 cache |= L2CR_PIPE_LATEWR|L2CR_L2CTL|L2CR_INST_DISABLE;
 301                 _set_L2CR(0);
 302                 _set_L2CR(cache|L2CR_L2I|L2CR_L2E);
 303         }
 304 }
 305
 306 void
 307 gemini_restart(char *cmd)
 308 {
 309         __cli();
 310         /* make a clean restart, not via the MPIC */
 311         _gemini_reboot();
 312         for(;;);
 313 }
 314
 315 void
 316 gemini_power_off(void)
 317 {
 318         for(;;);
 319 }
 320
 321 void
 322 gemini_halt(void)
 323 {
 324         gemini_restart(NULL);
 325 }
 326
 327 void __init gemini_init_IRQ(void)
 328 {
 329         int i;
 330
 331         /* gemini has no 8259 */
 332         open_pic.irq_offset = 0;
 333         for( i=0; i < 16; i++ )
 334                 irq_desc[i].ctl = &open_pic;
 335         openpic_init(1);
 336 }
 337
 338 #define gemini_rtc_read(x)       (readb(GEMINI_RTC+(x)))
 339 #define gemini_rtc_write(val,x)  (writeb((val),(GEMINI_RTC+(x))))
 340
 341 /* ensure that the RTC is up and running */
 342 void __init gemini_time_init(void)
 343 {
 344         unsigned char reg;
 345
 346         reg = gemini_rtc_read(M48T35_RTC_CONTROL);
 347
 348         if ( reg & M48T35_RTC_STOPPED ) {
 349                 printk(KERN_INFO "M48T35 real-time-clock was stopped. Now starting...\n");
 350                 gemini_rtc_write((reg & ~(M48T35_RTC_STOPPED)), M48T35_RTC_CONTROL);
 351                 gemini_rtc_write((reg | M48T35_RTC_SET), M48T35_RTC_CONTROL);
 352         }
 353 }
 354
 355 #undef DEBUG_RTC
 356
 357 unsigned long
 358 gemini_get_rtc_time(void)
 359 {
 360         unsigned int year, mon, day, hour, min, sec;
 361         unsigned char reg;
 362
 363         reg = gemini_rtc_read(M48T35_RTC_CONTROL);
 364         gemini_rtc_write((reg|M48T35_RTC_READ), M48T35_RTC_CONTROL);
 365 #ifdef DEBUG_RTC
 366         printk("get rtc: reg = %x\n", reg);
 367 #endif
 368
 369         do {
 370                 sec = gemini_rtc_read(M48T35_RTC_SECONDS);
 371                 min = gemini_rtc_read(M48T35_RTC_MINUTES);
 372                 hour = gemini_rtc_read(M48T35_RTC_HOURS);
 373                 day = gemini_rtc_read(M48T35_RTC_DOM);
 374                 mon = gemini_rtc_read(M48T35_RTC_MONTH);
 375                 year = gemini_rtc_read(M48T35_RTC_YEAR);
 376         } while( sec != gemini_rtc_read(M48T35_RTC_SECONDS));
 377 #ifdef DEBUG_RTC
 378         printk("get rtc: sec=%x, min=%x, hour=%x, day=%x, mon=%x, year=%x\n",
 379                sec, min, hour, day, mon, year);
 380 #endif
 381
 382         gemini_rtc_write(reg, M48T35_RTC_CONTROL);
 383
 384         BCD_TO_BIN(sec);
 385         BCD_TO_BIN(min);
 386         BCD_TO_BIN(hour);
 387         BCD_TO_BIN(day);
 388         BCD_TO_BIN(mon);
 389         BCD_TO_BIN(year);
 390
 391         if ((year += 1900) < 1970)
 392                 year += 100;
 393 #ifdef DEBUG_RTC
 394         printk("get rtc: sec=%x, min=%x, hour=%x, day=%x, mon=%x, year=%x\n",
 395                sec, min, hour, day, mon, year);
 396 #endif
 397
 398         return mktime( year, mon, day, hour, min, sec );
 399 }
 400
 401
 402 int
 403 gemini_set_rtc_time( unsigned long now )
 404 {
 405         unsigned char reg;
 406         struct rtc_time tm;
 407
 408         to_tm( now, &tm );
 409
 410         reg = gemini_rtc_read(M48T35_RTC_CONTROL);
 411 #if DEBUG_RTC
 412         printk("set rtc: reg = %x\n", reg);
 413 #endif
 414
 415         gemini_rtc_write((reg|M48T35_RTC_SET), M48T35_RTC_CONTROL);
 416 #if DEBUG_RTC
 417         printk("set rtc: tm vals - sec=%x, min=%x, hour=%x, mon=%x, mday=%x, year=%x\n",
 418                tm.tm_sec, tm.tm_min, tm.tm_hour, tm.tm_mon, tm.tm_mday, tm.tm_year);
 419 #endif
 420
 421         tm.tm_year -= 1900;
 422         BIN_TO_BCD(tm.tm_sec);
 423         BIN_TO_BCD(tm.tm_min);
 424         BIN_TO_BCD(tm.tm_hour);
 425         BIN_TO_BCD(tm.tm_mon);
 426         BIN_TO_BCD(tm.tm_mday);
 427         BIN_TO_BCD(tm.tm_year);
 428 #ifdef DEBUG_RTC
 429         printk("set rtc: tm vals - sec=%x, min=%x, hour=%x, mon=%x, mday=%x, year=%x\n",
 430                tm.tm_sec, tm.tm_min, tm.tm_hour, tm.tm_mon, tm.tm_mday, tm.tm_year);
 431 #endif
 432
 433         gemini_rtc_write(tm.tm_sec, M48T35_RTC_SECONDS);
 434         gemini_rtc_write(tm.tm_min, M48T35_RTC_MINUTES);
 435         gemini_rtc_write(tm.tm_hour, M48T35_RTC_HOURS);
 436         gemini_rtc_write(tm.tm_mday, M48T35_RTC_DOM);
 437         gemini_rtc_write(tm.tm_mon, M48T35_RTC_MONTH);
 438         gemini_rtc_write(tm.tm_year, M48T35_RTC_YEAR);
 439
 440         /* done writing */
 441         gemini_rtc_write(reg, M48T35_RTC_CONTROL);
 442
 443         if ((time_state == TIME_ERROR) || (time_state == TIME_BAD))
 444                 time_state = TIME_OK;
 445
 446         return 0;
 447 }
 448
 449 /*  use the RTC to determine the decrementer count */
 450 void __init gemini_calibrate_decr(void)
 451 {
 452         int freq, divisor;
 453         unsigned char reg;
 454
 455         /* determine processor bus speed */
 456         reg = readb(GEMINI_BSTAT);
 457
 458         switch(((reg & 0x0c)>>2)&0x3) {
 459         case 0:
 460         default:
 461                 freq = 66;
 462                 break;
 463         case 1:
 464                 freq = 83;
 465                 break;
 466         case 2:
 467                 freq = 100;
 468                 break;
 469         }
 470
 471         freq *= 1000000;
 472         divisor = 4;
 473         decrementer_count = freq / HZ / divisor;
 474         count_period_num = divisor;
 475         count_period_den = freq / 1000000;
 476 }
 477
 478
 479 void __init gemini_init(unsigned long r3, unsigned long r4, unsigned long r5,
 480                         unsigned long r6, unsigned long r7)
 481 {
 482         void chrp_do_IRQ(struct pt_regs *, int, int);
 483         void layout_bus( struct pci_bus * );
 484
 485         gemini_setup_pci_ptrs();
 486
 487         ISA_DMA_THRESHOLD = 0;
 488         DMA_MODE_READ = 0;
 489         DMA_MODE_WRITE = 0;
 490
 491 #ifdef CONFIG_BLK_DEV_INITRD
 492         if ( r4 )
 493         {
 494                 initrd_start = r4 + KERNELBASE;
 495                 initrd_end = r5 + KERNELBASE;
 496         }
 497 #endif
 498
 499         ppc_md.setup_arch = gemini_setup_arch;
 500         ppc_md.setup_residual = NULL;
 501         ppc_md.get_cpuinfo = gemini_get_cpuinfo;
 502         ppc_md.irq_cannonicalize = NULL;
 503         ppc_md.init_IRQ = gemini_init_IRQ;
 504         ppc_md.do_IRQ = chrp_do_IRQ;
 505         ppc_md.init = NULL;
 506
 507         ppc_md.restart = gemini_restart;
 508         ppc_md.power_off = gemini_power_off;
 509         ppc_md.halt = gemini_halt;
 510
 511         ppc_md.time_init = gemini_time_init;
 512         ppc_md.set_rtc_time = gemini_set_rtc_time;
 513         ppc_md.get_rtc_time = gemini_get_rtc_time;
 514         ppc_md.calibrate_decr = gemini_calibrate_decr;
 515
 516         /* no keyboard/mouse/video stuff yet.. */
 517         ppc_md.kbd_setkeycode = NULL;
 518         ppc_md.kbd_getkeycode = NULL;
 519         ppc_md.kbd_translate = NULL;
 520         ppc_md.kbd_unexpected_up = NULL;
 521         ppc_md.kbd_leds = NULL;
 522         ppc_md.kbd_init_hw = NULL;
 523 #ifdef CONFIG_MAGIC_SYSRQ
 524         ppc_md.ppc_kbd_sysrq_xlate = NULL;
 525 #endif
 526         ppc_md.pcibios_fixup_bus = layout_bus;
 527 }