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60 <H2><A NAME=
"SECTION00070000000000000000">
62 </H2><DL COMPACT
><DD><P></P><DT><A NAME=
"Bahar93">1</A>
64 R.
I. Bahar, E.
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M. Gaona, G.
D. Hachtel, E.
Macii, A.
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66 <BR>Algebraic decision diagrams and their applications.
67 <BR>In
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68 Design
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70 <P></P><DT><A NAME=
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72 B.
Bollig, M.
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73 <BR>Simulated annealing to improve variable orderings for OBDDs.
74 <BR>Presented at the International Workshop on Logic Synthesis,
75 Granlibakken, CA, May
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77 <P></P><DT><A NAME=
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79 K.
S. Brace, R.
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E. Bryant.
80 <BR>Efficient implementation of a BDD package.
81 <BR>In
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84 <P></P><DT><A NAME=
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86 R.
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87 <BR>VIS: A system for verification and synthesis.
88 <BR>Technical Report UCB/ERL M95/
104, Electronics Research Lab, Univ. of
89 California, December
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91 <P></P><DT><A NAME=
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94 <BR>Graph-based algorithms for Boolean function manipulation.
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97 <P></P><DT><A NAME=
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99 R.
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100 <BR>A genetic algorithm for variable ordering of OBDDs.
101 <BR>Presented at the International Workshop on Logic Synthesis,
102 Granlibakken, CA, May
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104 <P></P><DT><A NAME=
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106 S.
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107 <BR>Finding the optimal variable ordering for binary decision diagrams.
108 <BR><EM>IEEE Transactions on Computers
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110 <P></P><DT><A NAME=
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112 M.
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113 <BR>On variable ordering of binary decision diagrams for the application
114 of multi-level logic synthesis.
115 <BR>In
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116 pages
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118 <P></P><DT><A NAME=
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120 M.
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121 <BR>A dynamic programming approach to sequencing problems.
122 <BR><EM>J. SIAM
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124 <P></P><DT><A NAME=
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126 N.
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127 <BR>Minimization of binary decision diagrams based on exchanges of
129 <BR>In
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130 Design
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475, Santa Clara, CA, November
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132 <P></P><DT><A NAME=
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134 S.-W. Jeong, T.-S. Kim, and F.
Somenzi.
135 <BR>An efficient method for optimal BDD ordering computation.
136 <BR>In
<EM>International Conference on VLSI and CAD (ICVC'
93)
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137 Korea, November
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139 <P></P><DT><A NAME=
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142 <BR>Zero-suppressed BDDs for set manipulation in combinatorial
144 <BR>In
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</EM>, pages
145 272-
277, Dallas, TX, June
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147 <P></P><DT><A NAME=
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149 S.
Panda and F.
Somenzi.
150 <BR>Who are the variables in your neighborhood.
151 <BR>In
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152 Design
</EM>, pages
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77, San Jose, CA, November
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154 <P></P><DT><A NAME=
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156 S.
Panda, F.
Somenzi, and B.
F. Plessier.
157 <BR>Symmetry detection and dynamic variable ordering of decision
159 <BR>In
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160 Design
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162 <P></P><DT><A NAME=
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165 <BR><EM>A General Framework for Verification of Sequential Circuits
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166 <BR>PhD thesis, University of Colorado at Boulder, Dept. of Electrical
167 and Computer Engineering,
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169 <P></P><DT><A NAME=
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172 <BR>Dynamic variable ordering for ordered binary decision diagrams.
173 <BR>In
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174 Design
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47, Santa Clara, CA, November
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176 <P></P><DT><A NAME=
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178 E.
M. Sentovich, K.
J. Singh, C.
Moon, H.
Savoj, R.
K. Brayton, and
179 A.
Sangiovanni-Vincentelli.
180 <BR>Sequential circuit design using synthesis and optimization.
181 <BR>In
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182 Design
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333, Cambridge, MA, October
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