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  59
  60 <H2><A NAME="SECTION00070000000000000000">
  61 Bibliography</A>
  62 </H2><DL COMPACT><DD><P></P><DT><A NAME="Bahar93">1</A>
  63 <DD>
  64 R.&nbsp;I. Bahar, E.&nbsp;A. Frohm, C.&nbsp;M. Gaona, G.&nbsp;D. Hachtel, E.&nbsp;Macii, A.&nbsp;Pardo, and
  65   F.&nbsp;Somenzi.
  66 <BR>Algebraic decision diagrams and their applications.
  67 <BR>In <EM>Proceedings of the International Conference on Computer-Aided
  68   Design</EM>, pages 188-191, Santa Clara, CA, November 1993.
  69
  70 <P></P><DT><A NAME="Bollig95">2</A>
  71 <DD>
  72 B.&nbsp;Bollig, M.&nbsp;L&#246;bbing, and I.&nbsp;Wegener.
  73 <BR>Simulated annealing to improve variable orderings for OBDDs.
  74 <BR>Presented at the International Workshop on Logic Synthesis,
  75   Granlibakken, CA, May 1995.
  76
  77 <P></P><DT><A NAME="BBR">3</A>
  78 <DD>
  79 K.&nbsp;S. Brace, R.&nbsp;L. Rudell, and R.&nbsp;E. Bryant.
  80 <BR>Efficient implementation of a BDD package.
  81 <BR>In <EM>Proceedings of the 27th Design Automation Conference</EM>, pages
  82   40-45, Orlando, FL, June 1990.
  83
  84 <P></P><DT><A NAME="VIS">4</A>
  85 <DD>
  86 R.&nbsp;K. Brayton et&nbsp;al.
  87 <BR>VIS: A system for verification and synthesis.
  88 <BR>Technical Report UCB/ERL M95/104, Electronics Research Lab, Univ. of
  89   California, December 1995.
  90
  91 <P></P><DT><A NAME="BDD">5</A>
  92 <DD>
  93 R.&nbsp;E. Bryant.
  94 <BR>Graph-based algorithms for Boolean function manipulation.
  95 <BR><EM>IEEE Transactions on Computers</EM>, C-35(8):677-691, August 1986.
  96
  97 <P></P><DT><A NAME="Drechs95">6</A>
  98 <DD>
  99 R.&nbsp;Drechsler, B.&nbsp;Becker, and N.&nbsp;G&#246;ckel.
 100 <BR>A genetic algorithm for variable ordering of OBDDs.
 101 <BR>Presented at the International Workshop on Logic Synthesis,
 102   Granlibakken, CA, May 1995.
 103
 104 <P></P><DT><A NAME="Friedman90">7</A>
 105 <DD>
 106 S.&nbsp;J. Friedman and K.&nbsp;J. Supowit.
 107 <BR>Finding the optimal variable ordering for binary decision diagrams.
 108 <BR><EM>IEEE Transactions on Computers</EM>, 39(5):710-713, May 1990.
 109
 110 <P></P><DT><A NAME="Fujita91b">8</A>
 111 <DD>
 112 M.&nbsp;Fujita, Y.&nbsp;Matsunaga, and T.&nbsp;Kakuda.
 113 <BR>On variable ordering of binary decision diagrams for the application
 114   of multi-level logic synthesis.
 115 <BR>In <EM>Proceedings of the European Conference on Design Automation</EM>,
 116   pages 50-54, Amsterdam, February 1991.
 117
 118 <P></P><DT><A NAME="Held62">9</A>
 119 <DD>
 120 M.&nbsp;Held and R.&nbsp;M. Karp.
 121 <BR>A dynamic programming approach to sequencing problems.
 122 <BR><EM>J. SIAM</EM>, 10(1):196-210, 1962.
 123
 124 <P></P><DT><A NAME="Ishiur91">10</A>
 125 <DD>
 126 N.&nbsp;Ishiura, H.&nbsp;Sawada, and S.&nbsp;Yajima.
 127 <BR>Minimization of binary decision diagrams based on exchanges of
 128   variables.
 129 <BR>In <EM>Proceedings of the International Conference on Computer-Aided
 130   Design</EM>, pages 472-475, Santa Clara, CA, November 1991.
 131
 132 <P></P><DT><A NAME="Jeong93">11</A>
 133 <DD>
 134 S.-W. Jeong, T.-S. Kim, and F.&nbsp;Somenzi.
 135 <BR>An efficient method for optimal BDD ordering computation.
 136 <BR>In <EM>International Conference on VLSI and CAD (ICVC'93)</EM>, Taejon,
 137   Korea, November 1993.
 138
 139 <P></P><DT><A NAME="Minato93">12</A>
 140 <DD>
 141 S.-I. Minato.
 142 <BR>Zero-suppressed BDDs for set manipulation in combinatorial
 143   problems.
 144 <BR>In <EM>Proceedings of the Design Automation Conference</EM>, pages
 145   272-277, Dallas, TX, June 1993.
 146
 147 <P></P><DT><A NAME="Panda95b">13</A>
 148 <DD>
 149 S.&nbsp;Panda and F.&nbsp;Somenzi.
 150 <BR>Who are the variables in your neighborhood.
 151 <BR>In <EM>Proceedings of the International Conference on Computer-Aided
 152   Design</EM>, pages 74-77, San Jose, CA, November 1995.
 153
 154 <P></P><DT><A NAME="Panda94">14</A>
 155 <DD>
 156 S.&nbsp;Panda, F.&nbsp;Somenzi, and B.&nbsp;F. Plessier.
 157 <BR>Symmetry detection and dynamic variable ordering of decision
 158   diagrams.
 159 <BR>In <EM>Proceedings of the International Conference on Computer-Aided
 160   Design</EM>, pages 628-631, San Jose, CA, November 1994.
 161
 162 <P></P><DT><A NAME="Plessi93">15</A>
 163 <DD>
 164 B.&nbsp;F. Plessier.
 165 <BR><EM>A General Framework for Verification of Sequential Circuits</EM>.
 166 <BR>PhD thesis, University of Colorado at Boulder, Dept. of Electrical
 167   and Computer Engineering, 1993.
 168
 169 <P></P><DT><A NAME="Rudell93">16</A>
 170 <DD>
 171 R.&nbsp;Rudell.
 172 <BR>Dynamic variable ordering for ordered binary decision diagrams.
 173 <BR>In <EM>Proceedings of the International Conference on Computer-Aided
 174   Design</EM>, pages 42-47, Santa Clara, CA, November 1993.
 175
 176 <P></P><DT><A NAME="Sentov92">17</A>
 177 <DD>
 178 E.&nbsp;M. Sentovich, K.&nbsp;J. Singh, C.&nbsp;Moon, H.&nbsp;Savoj, R.&nbsp;K. Brayton, and
 179   A.&nbsp;Sangiovanni-Vincentelli.
 180 <BR>Sequential circuit design using synthesis and optimization.
 181 <BR>In <EM>Proceedings of the International Conference on Computer
 182   Design</EM>, pages 328-333, Cambridge, MA, October 1992.
 183 </DL>
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 187 <A NAME="1097"></A>
 188 <A NAME="1098"></A>
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 190
 191 <P>
 192 <BR><HR>
 193 <ADDRESS>
 194 Fabio Somenzi
 195 2009-02-20
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