1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const insn_template
*start
;
101 const insn_template
*end
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const insn_template
*match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "l1om", PROCESSOR_L1OM
,
582 { "k6", PROCESSOR_K6
,
584 { "k6_2", PROCESSOR_K6
,
586 { "athlon", PROCESSOR_ATHLON
,
588 { "sledgehammer", PROCESSOR_K8
,
590 { "opteron", PROCESSOR_K8
,
592 { "k8", PROCESSOR_K8
,
594 { "amdfam10", PROCESSOR_AMDFAM10
,
595 CPU_AMDFAM10_FLAGS
},
596 { ".8087", PROCESSOR_UNKNOWN
,
598 { ".287", PROCESSOR_UNKNOWN
,
600 { ".387", PROCESSOR_UNKNOWN
,
602 { ".no87", PROCESSOR_UNKNOWN
,
604 { ".mmx", PROCESSOR_UNKNOWN
,
606 { ".nommx", PROCESSOR_UNKNOWN
,
608 { ".sse", PROCESSOR_UNKNOWN
,
610 { ".sse2", PROCESSOR_UNKNOWN
,
612 { ".sse3", PROCESSOR_UNKNOWN
,
614 { ".ssse3", PROCESSOR_UNKNOWN
,
616 { ".sse4.1", PROCESSOR_UNKNOWN
,
618 { ".sse4.2", PROCESSOR_UNKNOWN
,
620 { ".sse4", PROCESSOR_UNKNOWN
,
622 { ".nosse", PROCESSOR_UNKNOWN
,
624 { ".avx", PROCESSOR_UNKNOWN
,
626 { ".noavx", PROCESSOR_UNKNOWN
,
628 { ".vmx", PROCESSOR_UNKNOWN
,
630 { ".smx", PROCESSOR_UNKNOWN
,
632 { ".xsave", PROCESSOR_UNKNOWN
,
634 { ".aes", PROCESSOR_UNKNOWN
,
636 { ".pclmul", PROCESSOR_UNKNOWN
,
638 { ".clmul", PROCESSOR_UNKNOWN
,
640 { ".fma", PROCESSOR_UNKNOWN
,
642 { ".fma4", PROCESSOR_UNKNOWN
,
644 { ".movbe", PROCESSOR_UNKNOWN
,
646 { ".ept", PROCESSOR_UNKNOWN
,
648 { ".clflush", PROCESSOR_UNKNOWN
,
650 { ".syscall", PROCESSOR_UNKNOWN
,
652 { ".rdtscp", PROCESSOR_UNKNOWN
,
654 { ".3dnow", PROCESSOR_UNKNOWN
,
656 { ".3dnowa", PROCESSOR_UNKNOWN
,
658 { ".padlock", PROCESSOR_UNKNOWN
,
660 { ".pacifica", PROCESSOR_UNKNOWN
,
662 { ".svme", PROCESSOR_UNKNOWN
,
664 { ".sse4a", PROCESSOR_UNKNOWN
,
666 { ".abm", PROCESSOR_UNKNOWN
,
671 /* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
675 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
682 && *input_line_pointer
== ',')
684 align
= parse_align (needs_align
- 1);
686 if (align
== (addressT
) -1)
701 bss_alloc (symbolP
, size
, align
);
706 pe_lcomm (int needs_align
)
708 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
712 const pseudo_typeS md_pseudo_table
[] =
714 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes
, 0},
717 {"align", s_align_ptwo
, 0},
719 {"arch", set_cpu_arch
, 0},
723 {"lcomm", pe_lcomm
, 1},
725 {"ffloat", float_cons
, 'f'},
726 {"dfloat", float_cons
, 'd'},
727 {"tfloat", float_cons
, 'x'},
729 {"slong", signed_cons
, 4},
730 {"noopt", s_ignore
, 0},
731 {"optim", s_ignore
, 0},
732 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
733 {"code16", set_code_flag
, CODE_16BIT
},
734 {"code32", set_code_flag
, CODE_32BIT
},
735 {"code64", set_code_flag
, CODE_64BIT
},
736 {"intel_syntax", set_intel_syntax
, 1},
737 {"att_syntax", set_intel_syntax
, 0},
738 {"intel_mnemonic", set_intel_mnemonic
, 1},
739 {"att_mnemonic", set_intel_mnemonic
, 0},
740 {"allow_index_reg", set_allow_index_reg
, 1},
741 {"disallow_index_reg", set_allow_index_reg
, 0},
742 {"sse_check", set_sse_check
, 0},
743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common
, 0},
746 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
747 {"loc", dwarf2_directive_loc
, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
751 {"secrel32", pe_directive_secrel
, 0},
756 /* For interface with expression (). */
757 extern char *input_line_pointer
;
759 /* Hash table for instruction mnemonic lookup. */
760 static struct hash_control
*op_hash
;
762 /* Hash table for register lookup. */
763 static struct hash_control
*reg_hash
;
766 i386_align_code (fragS
*fragP
, int count
)
768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
771 static const char f32_1
[] =
773 static const char f32_2
[] =
774 {0x66,0x90}; /* xchg %ax,%ax */
775 static const char f32_3
[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4
[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5
[] =
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7
[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8
[] =
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9
[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10
[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11
[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12
[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14
[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f16_3
[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
809 static const char f16_4
[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5
[] =
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6
[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7
[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8
[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char jump_31
[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
828 static const char *const f32_patt
[] = {
829 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
830 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
832 static const char *const f16_patt
[] = {
833 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
836 static const char alt_3
[] =
838 /* nopl 0(%[re]ax) */
839 static const char alt_4
[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5
[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6
[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7
[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8
[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9
[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10
[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14
[] =
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15
[] =
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11
[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12
[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
916 static const char alt_short_13
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 static const char alt_short_14
[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15
[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt
[] = {
930 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
931 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
932 alt_short_14
, alt_short_15
934 static const char *const alt_long_patt
[] = {
935 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
936 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
937 alt_long_14
, alt_long_15
940 /* Only align for at least a positive non-zero boundary. */
941 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
962 if (flag_code
== CODE_16BIT
)
966 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
968 /* Adjust jump offset. */
969 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
972 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
973 f16_patt
[count
- 1], count
);
977 const char *const *patt
= NULL
;
979 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune
)
984 case PROCESSOR_UNKNOWN
:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
987 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
988 patt
= alt_long_patt
;
992 case PROCESSOR_PENTIUMPRO
:
993 case PROCESSOR_PENTIUM4
:
994 case PROCESSOR_NOCONA
:
996 case PROCESSOR_CORE2
:
997 case PROCESSOR_COREI7
:
999 case PROCESSOR_GENERIC64
:
1000 patt
= alt_long_patt
;
1003 case PROCESSOR_ATHLON
:
1005 case PROCESSOR_AMDFAM10
:
1006 patt
= alt_short_patt
;
1008 case PROCESSOR_I386
:
1009 case PROCESSOR_I486
:
1010 case PROCESSOR_PENTIUM
:
1011 case PROCESSOR_GENERIC32
:
1018 switch (fragP
->tc_frag_data
.tune
)
1020 case PROCESSOR_UNKNOWN
:
1021 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1022 PROCESSOR_UNKNOWN. */
1026 case PROCESSOR_I386
:
1027 case PROCESSOR_I486
:
1028 case PROCESSOR_PENTIUM
:
1030 case PROCESSOR_ATHLON
:
1032 case PROCESSOR_AMDFAM10
:
1033 case PROCESSOR_GENERIC32
:
1034 /* We use cpu_arch_isa_flags to check if we CAN optimize
1036 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1037 patt
= alt_short_patt
;
1041 case PROCESSOR_PENTIUMPRO
:
1042 case PROCESSOR_PENTIUM4
:
1043 case PROCESSOR_NOCONA
:
1044 case PROCESSOR_CORE
:
1045 case PROCESSOR_CORE2
:
1046 case PROCESSOR_COREI7
:
1047 case PROCESSOR_L1OM
:
1048 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1049 patt
= alt_long_patt
;
1053 case PROCESSOR_GENERIC64
:
1054 patt
= alt_long_patt
;
1059 if (patt
== f32_patt
)
1061 /* If the padding is less than 15 bytes, we use the normal
1062 ones. Otherwise, we use a jump instruction and adjust
1066 /* For 64bit, the limit is 3 bytes. */
1067 if (flag_code
== CODE_64BIT
1068 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1073 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1074 patt
[count
- 1], count
);
1077 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1079 /* Adjust jump offset. */
1080 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1085 /* Maximum length of an instruction is 15 byte. If the
1086 padding is greater than 15 bytes and we don't use jump,
1087 we have to break it into smaller pieces. */
1088 int padding
= count
;
1089 while (padding
> 15)
1092 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1097 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1098 patt
[padding
- 1], padding
);
1101 fragP
->fr_var
= count
;
1105 operand_type_all_zero (const union i386_operand_type
*x
)
1107 switch (ARRAY_SIZE(x
->array
))
1116 return !x
->array
[0];
1123 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1125 switch (ARRAY_SIZE(x
->array
))
1140 operand_type_equal (const union i386_operand_type
*x
,
1141 const union i386_operand_type
*y
)
1143 switch (ARRAY_SIZE(x
->array
))
1146 if (x
->array
[2] != y
->array
[2])
1149 if (x
->array
[1] != y
->array
[1])
1152 return x
->array
[0] == y
->array
[0];
1160 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1162 switch (ARRAY_SIZE(x
->array
))
1171 return !x
->array
[0];
1178 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1180 switch (ARRAY_SIZE(x
->array
))
1195 cpu_flags_equal (const union i386_cpu_flags
*x
,
1196 const union i386_cpu_flags
*y
)
1198 switch (ARRAY_SIZE(x
->array
))
1201 if (x
->array
[2] != y
->array
[2])
1204 if (x
->array
[1] != y
->array
[1])
1207 return x
->array
[0] == y
->array
[0];
1215 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1217 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1218 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1221 static INLINE i386_cpu_flags
1222 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1224 switch (ARRAY_SIZE (x
.array
))
1227 x
.array
[2] &= y
.array
[2];
1229 x
.array
[1] &= y
.array
[1];
1231 x
.array
[0] &= y
.array
[0];
1239 static INLINE i386_cpu_flags
1240 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1242 switch (ARRAY_SIZE (x
.array
))
1245 x
.array
[2] |= y
.array
[2];
1247 x
.array
[1] |= y
.array
[1];
1249 x
.array
[0] |= y
.array
[0];
1257 static INLINE i386_cpu_flags
1258 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1260 switch (ARRAY_SIZE (x
.array
))
1263 x
.array
[2] &= ~y
.array
[2];
1265 x
.array
[1] &= ~y
.array
[1];
1267 x
.array
[0] &= ~y
.array
[0];
1275 #define CPU_FLAGS_ARCH_MATCH 0x1
1276 #define CPU_FLAGS_64BIT_MATCH 0x2
1277 #define CPU_FLAGS_AES_MATCH 0x4
1278 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1279 #define CPU_FLAGS_AVX_MATCH 0x10
1281 #define CPU_FLAGS_32BIT_MATCH \
1282 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1283 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1284 #define CPU_FLAGS_PERFECT_MATCH \
1285 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1287 /* Return CPU flags match bits. */
1290 cpu_flags_match (const insn_template
*t
)
1292 i386_cpu_flags x
= t
->cpu_flags
;
1293 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1295 x
.bitfield
.cpu64
= 0;
1296 x
.bitfield
.cpuno64
= 0;
1298 if (cpu_flags_all_zero (&x
))
1300 /* This instruction is available on all archs. */
1301 match
|= CPU_FLAGS_32BIT_MATCH
;
1305 /* This instruction is available only on some archs. */
1306 i386_cpu_flags cpu
= cpu_arch_flags
;
1308 cpu
.bitfield
.cpu64
= 0;
1309 cpu
.bitfield
.cpuno64
= 0;
1310 cpu
= cpu_flags_and (x
, cpu
);
1311 if (!cpu_flags_all_zero (&cpu
))
1313 if (x
.bitfield
.cpuavx
)
1315 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1316 if (cpu
.bitfield
.cpuavx
)
1318 /* Check SSE2AVX. */
1319 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1321 match
|= (CPU_FLAGS_ARCH_MATCH
1322 | CPU_FLAGS_AVX_MATCH
);
1324 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1325 match
|= CPU_FLAGS_AES_MATCH
;
1327 if (!x
.bitfield
.cpupclmul
1328 || cpu
.bitfield
.cpupclmul
)
1329 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1333 match
|= CPU_FLAGS_ARCH_MATCH
;
1336 match
|= CPU_FLAGS_32BIT_MATCH
;
1342 static INLINE i386_operand_type
1343 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1345 switch (ARRAY_SIZE (x
.array
))
1348 x
.array
[2] &= y
.array
[2];
1350 x
.array
[1] &= y
.array
[1];
1352 x
.array
[0] &= y
.array
[0];
1360 static INLINE i386_operand_type
1361 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1363 switch (ARRAY_SIZE (x
.array
))
1366 x
.array
[2] |= y
.array
[2];
1368 x
.array
[1] |= y
.array
[1];
1370 x
.array
[0] |= y
.array
[0];
1378 static INLINE i386_operand_type
1379 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1381 switch (ARRAY_SIZE (x
.array
))
1384 x
.array
[2] ^= y
.array
[2];
1386 x
.array
[1] ^= y
.array
[1];
1388 x
.array
[0] ^= y
.array
[0];
1396 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1397 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1398 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1399 static const i386_operand_type inoutportreg
1400 = OPERAND_TYPE_INOUTPORTREG
;
1401 static const i386_operand_type reg16_inoutportreg
1402 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1403 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1404 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1405 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1406 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1407 static const i386_operand_type anydisp
1408 = OPERAND_TYPE_ANYDISP
;
1409 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1410 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1411 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1412 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1413 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1414 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1415 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1416 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1417 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1418 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1419 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1430 operand_type_check (i386_operand_type t
, enum operand_type c
)
1435 return (t
.bitfield
.reg8
1438 || t
.bitfield
.reg64
);
1441 return (t
.bitfield
.imm8
1445 || t
.bitfield
.imm32s
1446 || t
.bitfield
.imm64
);
1449 return (t
.bitfield
.disp8
1450 || t
.bitfield
.disp16
1451 || t
.bitfield
.disp32
1452 || t
.bitfield
.disp32s
1453 || t
.bitfield
.disp64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
1461 || t
.bitfield
.baseindex
);
1470 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1471 operand J for instruction template T. */
1474 match_reg_size (const insn_template
*t
, unsigned int j
)
1476 return !((i
.types
[j
].bitfield
.byte
1477 && !t
->operand_types
[j
].bitfield
.byte
)
1478 || (i
.types
[j
].bitfield
.word
1479 && !t
->operand_types
[j
].bitfield
.word
)
1480 || (i
.types
[j
].bitfield
.dword
1481 && !t
->operand_types
[j
].bitfield
.dword
)
1482 || (i
.types
[j
].bitfield
.qword
1483 && !t
->operand_types
[j
].bitfield
.qword
));
1486 /* Return 1 if there is no conflict in any size on operand J for
1487 instruction template T. */
1490 match_mem_size (const insn_template
*t
, unsigned int j
)
1492 return (match_reg_size (t
, j
)
1493 && !((i
.types
[j
].bitfield
.unspecified
1494 && !t
->operand_types
[j
].bitfield
.unspecified
)
1495 || (i
.types
[j
].bitfield
.fword
1496 && !t
->operand_types
[j
].bitfield
.fword
)
1497 || (i
.types
[j
].bitfield
.tbyte
1498 && !t
->operand_types
[j
].bitfield
.tbyte
)
1499 || (i
.types
[j
].bitfield
.xmmword
1500 && !t
->operand_types
[j
].bitfield
.xmmword
)
1501 || (i
.types
[j
].bitfield
.ymmword
1502 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1505 /* Return 1 if there is no size conflict on any operands for
1506 instruction template T. */
1509 operand_size_match (const insn_template
*t
)
1514 /* Don't check jump instructions. */
1515 if (t
->opcode_modifier
.jump
1516 || t
->opcode_modifier
.jumpbyte
1517 || t
->opcode_modifier
.jumpdword
1518 || t
->opcode_modifier
.jumpintersegment
)
1521 /* Check memory and accumulator operand size. */
1522 for (j
= 0; j
< i
.operands
; j
++)
1524 if (t
->operand_types
[j
].bitfield
.anysize
)
1527 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1533 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1541 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1544 /* Check reverse. */
1545 gas_assert (i
.operands
== 2);
1548 for (j
= 0; j
< 2; j
++)
1550 if (t
->operand_types
[j
].bitfield
.acc
1551 && !match_reg_size (t
, j
? 0 : 1))
1557 if (i
.types
[j
].bitfield
.mem
1558 && !match_mem_size (t
, j
? 0 : 1))
1569 operand_type_match (i386_operand_type overlap
,
1570 i386_operand_type given
)
1572 i386_operand_type temp
= overlap
;
1574 temp
.bitfield
.jumpabsolute
= 0;
1575 temp
.bitfield
.unspecified
= 0;
1576 temp
.bitfield
.byte
= 0;
1577 temp
.bitfield
.word
= 0;
1578 temp
.bitfield
.dword
= 0;
1579 temp
.bitfield
.fword
= 0;
1580 temp
.bitfield
.qword
= 0;
1581 temp
.bitfield
.tbyte
= 0;
1582 temp
.bitfield
.xmmword
= 0;
1583 temp
.bitfield
.ymmword
= 0;
1584 if (operand_type_all_zero (&temp
))
1587 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1588 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1591 /* If given types g0 and g1 are registers they must be of the same type
1592 unless the expected operand type register overlap is null.
1593 Note that Acc in a template matches every size of reg. */
1596 operand_type_register_match (i386_operand_type m0
,
1597 i386_operand_type g0
,
1598 i386_operand_type t0
,
1599 i386_operand_type m1
,
1600 i386_operand_type g1
,
1601 i386_operand_type t1
)
1603 if (!operand_type_check (g0
, reg
))
1606 if (!operand_type_check (g1
, reg
))
1609 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1610 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1611 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1612 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1615 if (m0
.bitfield
.acc
)
1617 t0
.bitfield
.reg8
= 1;
1618 t0
.bitfield
.reg16
= 1;
1619 t0
.bitfield
.reg32
= 1;
1620 t0
.bitfield
.reg64
= 1;
1623 if (m1
.bitfield
.acc
)
1625 t1
.bitfield
.reg8
= 1;
1626 t1
.bitfield
.reg16
= 1;
1627 t1
.bitfield
.reg32
= 1;
1628 t1
.bitfield
.reg64
= 1;
1631 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1632 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1633 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1634 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1637 static INLINE
unsigned int
1638 mode_from_disp_size (i386_operand_type t
)
1640 if (t
.bitfield
.disp8
)
1642 else if (t
.bitfield
.disp16
1643 || t
.bitfield
.disp32
1644 || t
.bitfield
.disp32s
)
1651 fits_in_signed_byte (offsetT num
)
1653 return (num
>= -128) && (num
<= 127);
1657 fits_in_unsigned_byte (offsetT num
)
1659 return (num
& 0xff) == num
;
1663 fits_in_unsigned_word (offsetT num
)
1665 return (num
& 0xffff) == num
;
1669 fits_in_signed_word (offsetT num
)
1671 return (-32768 <= num
) && (num
<= 32767);
1675 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1680 return (!(((offsetT
) -1 << 31) & num
)
1681 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1683 } /* fits_in_signed_long() */
1686 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1691 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1693 } /* fits_in_unsigned_long() */
1695 static i386_operand_type
1696 smallest_imm_type (offsetT num
)
1698 i386_operand_type t
;
1700 operand_type_set (&t
, 0);
1701 t
.bitfield
.imm64
= 1;
1703 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1705 /* This code is disabled on the 486 because all the Imm1 forms
1706 in the opcode table are slower on the i486. They're the
1707 versions with the implicitly specified single-position
1708 displacement, which has another syntax if you really want to
1710 t
.bitfield
.imm1
= 1;
1711 t
.bitfield
.imm8
= 1;
1712 t
.bitfield
.imm8s
= 1;
1713 t
.bitfield
.imm16
= 1;
1714 t
.bitfield
.imm32
= 1;
1715 t
.bitfield
.imm32s
= 1;
1717 else if (fits_in_signed_byte (num
))
1719 t
.bitfield
.imm8
= 1;
1720 t
.bitfield
.imm8s
= 1;
1721 t
.bitfield
.imm16
= 1;
1722 t
.bitfield
.imm32
= 1;
1723 t
.bitfield
.imm32s
= 1;
1725 else if (fits_in_unsigned_byte (num
))
1727 t
.bitfield
.imm8
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1734 t
.bitfield
.imm16
= 1;
1735 t
.bitfield
.imm32
= 1;
1736 t
.bitfield
.imm32s
= 1;
1738 else if (fits_in_signed_long (num
))
1740 t
.bitfield
.imm32
= 1;
1741 t
.bitfield
.imm32s
= 1;
1743 else if (fits_in_unsigned_long (num
))
1744 t
.bitfield
.imm32
= 1;
1750 offset_in_range (offsetT val
, int size
)
1756 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1757 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1758 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1760 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1766 /* If BFD64, sign extend val for 32bit address mode. */
1767 if (flag_code
!= CODE_64BIT
1768 || i
.prefix
[ADDR_PREFIX
])
1769 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1770 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1773 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1775 char buf1
[40], buf2
[40];
1777 sprint_value (buf1
, val
);
1778 sprint_value (buf2
, val
& mask
);
1779 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1784 /* Returns 0 if attempting to add a prefix where one from the same
1785 class already exists, 1 if non rep/repne added, 2 if rep/repne
1788 add_prefix (unsigned int prefix
)
1793 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1794 && flag_code
== CODE_64BIT
)
1796 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1797 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1798 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1809 case CS_PREFIX_OPCODE
:
1810 case DS_PREFIX_OPCODE
:
1811 case ES_PREFIX_OPCODE
:
1812 case FS_PREFIX_OPCODE
:
1813 case GS_PREFIX_OPCODE
:
1814 case SS_PREFIX_OPCODE
:
1818 case REPNE_PREFIX_OPCODE
:
1819 case REPE_PREFIX_OPCODE
:
1822 case LOCK_PREFIX_OPCODE
:
1830 case ADDR_PREFIX_OPCODE
:
1834 case DATA_PREFIX_OPCODE
:
1838 if (i
.prefix
[q
] != 0)
1846 i
.prefix
[q
] |= prefix
;
1849 as_bad (_("same type of prefix used twice"));
1855 set_code_flag (int value
)
1857 flag_code
= (enum flag_code
) value
;
1858 if (flag_code
== CODE_64BIT
)
1860 cpu_arch_flags
.bitfield
.cpu64
= 1;
1861 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1865 cpu_arch_flags
.bitfield
.cpu64
= 0;
1866 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1868 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1870 as_bad (_("64bit mode not supported on this CPU."));
1872 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1874 as_bad (_("32bit mode not supported on this CPU."));
1876 stackop_size
= '\0';
1880 set_16bit_gcc_code_flag (int new_code_flag
)
1882 flag_code
= (enum flag_code
) new_code_flag
;
1883 if (flag_code
!= CODE_16BIT
)
1885 cpu_arch_flags
.bitfield
.cpu64
= 0;
1886 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1887 stackop_size
= LONG_MNEM_SUFFIX
;
1891 set_intel_syntax (int syntax_flag
)
1893 /* Find out if register prefixing is specified. */
1894 int ask_naked_reg
= 0;
1897 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1899 char *string
= input_line_pointer
;
1900 int e
= get_symbol_end ();
1902 if (strcmp (string
, "prefix") == 0)
1904 else if (strcmp (string
, "noprefix") == 0)
1907 as_bad (_("bad argument to syntax directive."));
1908 *input_line_pointer
= e
;
1910 demand_empty_rest_of_line ();
1912 intel_syntax
= syntax_flag
;
1914 if (ask_naked_reg
== 0)
1915 allow_naked_reg
= (intel_syntax
1916 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1918 allow_naked_reg
= (ask_naked_reg
< 0);
1920 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1922 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1923 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1924 register_prefix
= allow_naked_reg
? "" : "%";
1928 set_intel_mnemonic (int mnemonic_flag
)
1930 intel_mnemonic
= mnemonic_flag
;
1934 set_allow_index_reg (int flag
)
1936 allow_index_reg
= flag
;
1940 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1944 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1946 char *string
= input_line_pointer
;
1947 int e
= get_symbol_end ();
1949 if (strcmp (string
, "none") == 0)
1950 sse_check
= sse_check_none
;
1951 else if (strcmp (string
, "warning") == 0)
1952 sse_check
= sse_check_warning
;
1953 else if (strcmp (string
, "error") == 0)
1954 sse_check
= sse_check_error
;
1956 as_bad (_("bad argument to sse_check directive."));
1957 *input_line_pointer
= e
;
1960 as_bad (_("missing argument for sse_check directive"));
1962 demand_empty_rest_of_line ();
1966 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1967 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1969 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1970 static const char *arch
;
1972 /* Intel LIOM is only supported on ELF. */
1978 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1979 use default_arch. */
1980 arch
= cpu_arch_name
;
1982 arch
= default_arch
;
1985 /* If we are targeting Intel L1OM, we must enable it. */
1986 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
1987 || new_flag
.bitfield
.cpul1om
)
1990 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
1995 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1999 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2001 char *string
= input_line_pointer
;
2002 int e
= get_symbol_end ();
2004 i386_cpu_flags flags
;
2006 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2008 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2010 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2014 cpu_arch_name
= cpu_arch
[i
].name
;
2015 cpu_sub_arch_name
= NULL
;
2016 cpu_arch_flags
= cpu_arch
[i
].flags
;
2017 if (flag_code
== CODE_64BIT
)
2019 cpu_arch_flags
.bitfield
.cpu64
= 1;
2020 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2024 cpu_arch_flags
.bitfield
.cpu64
= 0;
2025 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2027 cpu_arch_isa
= cpu_arch
[i
].type
;
2028 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2029 if (!cpu_arch_tune_set
)
2031 cpu_arch_tune
= cpu_arch_isa
;
2032 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2037 if (strncmp (string
+ 1, "no", 2))
2038 flags
= cpu_flags_or (cpu_arch_flags
,
2041 flags
= cpu_flags_and_not (cpu_arch_flags
,
2043 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2045 if (cpu_sub_arch_name
)
2047 char *name
= cpu_sub_arch_name
;
2048 cpu_sub_arch_name
= concat (name
,
2050 (const char *) NULL
);
2054 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2055 cpu_arch_flags
= flags
;
2057 *input_line_pointer
= e
;
2058 demand_empty_rest_of_line ();
2062 if (i
>= ARRAY_SIZE (cpu_arch
))
2063 as_bad (_("no such architecture: `%s'"), string
);
2065 *input_line_pointer
= e
;
2068 as_bad (_("missing cpu architecture"));
2070 no_cond_jump_promotion
= 0;
2071 if (*input_line_pointer
== ','
2072 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2074 char *string
= ++input_line_pointer
;
2075 int e
= get_symbol_end ();
2077 if (strcmp (string
, "nojumps") == 0)
2078 no_cond_jump_promotion
= 1;
2079 else if (strcmp (string
, "jumps") == 0)
2082 as_bad (_("no such architecture modifier: `%s'"), string
);
2084 *input_line_pointer
= e
;
2087 demand_empty_rest_of_line ();
2090 enum bfd_architecture
2093 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2095 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2096 || flag_code
!= CODE_64BIT
)
2097 as_fatal (_("Intel L1OM is 64bit ELF only"));
2098 return bfd_arch_l1om
;
2101 return bfd_arch_i386
;
2107 if (!strcmp (default_arch
, "x86_64"))
2109 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2111 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2112 as_fatal (_("Intel L1OM is 64bit ELF only"));
2113 return bfd_mach_l1om
;
2116 return bfd_mach_x86_64
;
2118 else if (!strcmp (default_arch
, "i386"))
2119 return bfd_mach_i386_i386
;
2121 as_fatal (_("Unknown architecture"));
2127 const char *hash_err
;
2129 /* Initialize op_hash hash table. */
2130 op_hash
= hash_new ();
2133 const insn_template
*optab
;
2134 templates
*core_optab
;
2136 /* Setup for loop. */
2138 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2139 core_optab
->start
= optab
;
2144 if (optab
->name
== NULL
2145 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2147 /* different name --> ship out current template list;
2148 add to hash table; & begin anew. */
2149 core_optab
->end
= optab
;
2150 hash_err
= hash_insert (op_hash
,
2152 (void *) core_optab
);
2155 as_fatal (_("Internal Error: Can't hash %s: %s"),
2159 if (optab
->name
== NULL
)
2161 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2162 core_optab
->start
= optab
;
2167 /* Initialize reg_hash hash table. */
2168 reg_hash
= hash_new ();
2170 const reg_entry
*regtab
;
2171 unsigned int regtab_size
= i386_regtab_size
;
2173 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2175 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2177 as_fatal (_("Internal Error: Can't hash %s: %s"),
2183 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2188 for (c
= 0; c
< 256; c
++)
2193 mnemonic_chars
[c
] = c
;
2194 register_chars
[c
] = c
;
2195 operand_chars
[c
] = c
;
2197 else if (ISLOWER (c
))
2199 mnemonic_chars
[c
] = c
;
2200 register_chars
[c
] = c
;
2201 operand_chars
[c
] = c
;
2203 else if (ISUPPER (c
))
2205 mnemonic_chars
[c
] = TOLOWER (c
);
2206 register_chars
[c
] = mnemonic_chars
[c
];
2207 operand_chars
[c
] = c
;
2210 if (ISALPHA (c
) || ISDIGIT (c
))
2211 identifier_chars
[c
] = c
;
2214 identifier_chars
[c
] = c
;
2215 operand_chars
[c
] = c
;
2220 identifier_chars
['@'] = '@';
2223 identifier_chars
['?'] = '?';
2224 operand_chars
['?'] = '?';
2226 digit_chars
['-'] = '-';
2227 mnemonic_chars
['_'] = '_';
2228 mnemonic_chars
['-'] = '-';
2229 mnemonic_chars
['.'] = '.';
2230 identifier_chars
['_'] = '_';
2231 identifier_chars
['.'] = '.';
2233 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2234 operand_chars
[(unsigned char) *p
] = *p
;
2237 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2240 record_alignment (text_section
, 2);
2241 record_alignment (data_section
, 2);
2242 record_alignment (bss_section
, 2);
2246 if (flag_code
== CODE_64BIT
)
2248 x86_dwarf2_return_column
= 16;
2249 x86_cie_data_alignment
= -8;
2253 x86_dwarf2_return_column
= 8;
2254 x86_cie_data_alignment
= -4;
2259 i386_print_statistics (FILE *file
)
2261 hash_print_statistics (file
, "i386 opcode", op_hash
);
2262 hash_print_statistics (file
, "i386 register", reg_hash
);
2267 /* Debugging routines for md_assemble. */
2268 static void pte (insn_template
*);
2269 static void pt (i386_operand_type
);
2270 static void pe (expressionS
*);
2271 static void ps (symbolS
*);
2274 pi (char *line
, i386_insn
*x
)
2278 fprintf (stdout
, "%s: template ", line
);
2280 fprintf (stdout
, " address: base %s index %s scale %x\n",
2281 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2282 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2283 x
->log2_scale_factor
);
2284 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2285 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2286 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2287 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2288 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2289 (x
->rex
& REX_W
) != 0,
2290 (x
->rex
& REX_R
) != 0,
2291 (x
->rex
& REX_X
) != 0,
2292 (x
->rex
& REX_B
) != 0);
2293 for (i
= 0; i
< x
->operands
; i
++)
2295 fprintf (stdout
, " #%d: ", i
+ 1);
2297 fprintf (stdout
, "\n");
2298 if (x
->types
[i
].bitfield
.reg8
2299 || x
->types
[i
].bitfield
.reg16
2300 || x
->types
[i
].bitfield
.reg32
2301 || x
->types
[i
].bitfield
.reg64
2302 || x
->types
[i
].bitfield
.regmmx
2303 || x
->types
[i
].bitfield
.regxmm
2304 || x
->types
[i
].bitfield
.regymm
2305 || x
->types
[i
].bitfield
.sreg2
2306 || x
->types
[i
].bitfield
.sreg3
2307 || x
->types
[i
].bitfield
.control
2308 || x
->types
[i
].bitfield
.debug
2309 || x
->types
[i
].bitfield
.test
)
2310 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2311 if (operand_type_check (x
->types
[i
], imm
))
2313 if (operand_type_check (x
->types
[i
], disp
))
2314 pe (x
->op
[i
].disps
);
2319 pte (insn_template
*t
)
2322 fprintf (stdout
, " %d operands ", t
->operands
);
2323 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2324 if (t
->extension_opcode
!= None
)
2325 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2326 if (t
->opcode_modifier
.d
)
2327 fprintf (stdout
, "D");
2328 if (t
->opcode_modifier
.w
)
2329 fprintf (stdout
, "W");
2330 fprintf (stdout
, "\n");
2331 for (i
= 0; i
< t
->operands
; i
++)
2333 fprintf (stdout
, " #%d type ", i
+ 1);
2334 pt (t
->operand_types
[i
]);
2335 fprintf (stdout
, "\n");
2342 fprintf (stdout
, " operation %d\n", e
->X_op
);
2343 fprintf (stdout
, " add_number %ld (%lx)\n",
2344 (long) e
->X_add_number
, (long) e
->X_add_number
);
2345 if (e
->X_add_symbol
)
2347 fprintf (stdout
, " add_symbol ");
2348 ps (e
->X_add_symbol
);
2349 fprintf (stdout
, "\n");
2353 fprintf (stdout
, " op_symbol ");
2354 ps (e
->X_op_symbol
);
2355 fprintf (stdout
, "\n");
2362 fprintf (stdout
, "%s type %s%s",
2364 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2365 segment_name (S_GET_SEGMENT (s
)));
2368 static struct type_name
2370 i386_operand_type mask
;
2373 const type_names
[] =
2375 { OPERAND_TYPE_REG8
, "r8" },
2376 { OPERAND_TYPE_REG16
, "r16" },
2377 { OPERAND_TYPE_REG32
, "r32" },
2378 { OPERAND_TYPE_REG64
, "r64" },
2379 { OPERAND_TYPE_IMM8
, "i8" },
2380 { OPERAND_TYPE_IMM8
, "i8s" },
2381 { OPERAND_TYPE_IMM16
, "i16" },
2382 { OPERAND_TYPE_IMM32
, "i32" },
2383 { OPERAND_TYPE_IMM32S
, "i32s" },
2384 { OPERAND_TYPE_IMM64
, "i64" },
2385 { OPERAND_TYPE_IMM1
, "i1" },
2386 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2387 { OPERAND_TYPE_DISP8
, "d8" },
2388 { OPERAND_TYPE_DISP16
, "d16" },
2389 { OPERAND_TYPE_DISP32
, "d32" },
2390 { OPERAND_TYPE_DISP32S
, "d32s" },
2391 { OPERAND_TYPE_DISP64
, "d64" },
2392 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2393 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2394 { OPERAND_TYPE_CONTROL
, "control reg" },
2395 { OPERAND_TYPE_TEST
, "test reg" },
2396 { OPERAND_TYPE_DEBUG
, "debug reg" },
2397 { OPERAND_TYPE_FLOATREG
, "FReg" },
2398 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2399 { OPERAND_TYPE_SREG2
, "SReg2" },
2400 { OPERAND_TYPE_SREG3
, "SReg3" },
2401 { OPERAND_TYPE_ACC
, "Acc" },
2402 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2403 { OPERAND_TYPE_REGMMX
, "rMMX" },
2404 { OPERAND_TYPE_REGXMM
, "rXMM" },
2405 { OPERAND_TYPE_REGYMM
, "rYMM" },
2406 { OPERAND_TYPE_ESSEG
, "es" },
2410 pt (i386_operand_type t
)
2413 i386_operand_type a
;
2415 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2417 a
= operand_type_and (t
, type_names
[j
].mask
);
2418 if (!operand_type_all_zero (&a
))
2419 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2424 #endif /* DEBUG386 */
2426 static bfd_reloc_code_real_type
2427 reloc (unsigned int size
,
2430 bfd_reloc_code_real_type other
)
2432 if (other
!= NO_RELOC
)
2434 reloc_howto_type
*reloc
;
2439 case BFD_RELOC_X86_64_GOT32
:
2440 return BFD_RELOC_X86_64_GOT64
;
2442 case BFD_RELOC_X86_64_PLTOFF64
:
2443 return BFD_RELOC_X86_64_PLTOFF64
;
2445 case BFD_RELOC_X86_64_GOTPC32
:
2446 other
= BFD_RELOC_X86_64_GOTPC64
;
2448 case BFD_RELOC_X86_64_GOTPCREL
:
2449 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2451 case BFD_RELOC_X86_64_TPOFF32
:
2452 other
= BFD_RELOC_X86_64_TPOFF64
;
2454 case BFD_RELOC_X86_64_DTPOFF32
:
2455 other
= BFD_RELOC_X86_64_DTPOFF64
;
2461 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2462 if (size
== 4 && flag_code
!= CODE_64BIT
)
2465 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2467 as_bad (_("unknown relocation (%u)"), other
);
2468 else if (size
!= bfd_get_reloc_size (reloc
))
2469 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2470 bfd_get_reloc_size (reloc
),
2472 else if (pcrel
&& !reloc
->pc_relative
)
2473 as_bad (_("non-pc-relative relocation for pc-relative field"));
2474 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2476 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2478 as_bad (_("relocated field and relocation type differ in signedness"));
2487 as_bad (_("there are no unsigned pc-relative relocations"));
2490 case 1: return BFD_RELOC_8_PCREL
;
2491 case 2: return BFD_RELOC_16_PCREL
;
2492 case 4: return BFD_RELOC_32_PCREL
;
2493 case 8: return BFD_RELOC_64_PCREL
;
2495 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2502 case 4: return BFD_RELOC_X86_64_32S
;
2507 case 1: return BFD_RELOC_8
;
2508 case 2: return BFD_RELOC_16
;
2509 case 4: return BFD_RELOC_32
;
2510 case 8: return BFD_RELOC_64
;
2512 as_bad (_("cannot do %s %u byte relocation"),
2513 sign
> 0 ? "signed" : "unsigned", size
);
2519 /* Here we decide which fixups can be adjusted to make them relative to
2520 the beginning of the section instead of the symbol. Basically we need
2521 to make sure that the dynamic relocations are done correctly, so in
2522 some cases we force the original symbol to be used. */
2525 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2531 /* Don't adjust pc-relative references to merge sections in 64-bit
2533 if (use_rela_relocations
2534 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2538 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2539 and changed later by validate_fix. */
2540 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2541 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2544 /* adjust_reloc_syms doesn't know about the GOT. */
2545 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2546 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2547 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2553 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2554 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2555 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2556 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2557 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2566 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2567 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2568 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2569 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2570 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2571 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2572 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2579 intel_float_operand (const char *mnemonic
)
2581 /* Note that the value returned is meaningful only for opcodes with (memory)
2582 operands, hence the code here is free to improperly handle opcodes that
2583 have no operands (for better performance and smaller code). */
2585 if (mnemonic
[0] != 'f')
2586 return 0; /* non-math */
2588 switch (mnemonic
[1])
2590 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2591 the fs segment override prefix not currently handled because no
2592 call path can make opcodes without operands get here */
2594 return 2 /* integer op */;
2596 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2597 return 3; /* fldcw/fldenv */
2600 if (mnemonic
[2] != 'o' /* fnop */)
2601 return 3; /* non-waiting control op */
2604 if (mnemonic
[2] == 's')
2605 return 3; /* frstor/frstpm */
2608 if (mnemonic
[2] == 'a')
2609 return 3; /* fsave */
2610 if (mnemonic
[2] == 't')
2612 switch (mnemonic
[3])
2614 case 'c': /* fstcw */
2615 case 'd': /* fstdw */
2616 case 'e': /* fstenv */
2617 case 's': /* fsts[gw] */
2623 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2624 return 0; /* fxsave/fxrstor are not really math ops */
2631 /* Build the VEX prefix. */
2634 build_vex_prefix (const insn_template
*t
)
2636 unsigned int register_specifier
;
2637 unsigned int implied_prefix
;
2638 unsigned int vector_length
;
2640 /* Check register specifier. */
2641 if (i
.vex
.register_specifier
)
2643 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2644 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2645 register_specifier
+= 8;
2646 register_specifier
= ~register_specifier
& 0xf;
2649 register_specifier
= 0xf;
2651 /* Use 2-byte VEX prefix by swappping destination and source
2654 && i
.operands
== i
.reg_operands
2655 && i
.tm
.opcode_modifier
.vex0f
2656 && i
.tm
.opcode_modifier
.s
2659 unsigned int xchg
= i
.operands
- 1;
2660 union i386_op temp_op
;
2661 i386_operand_type temp_type
;
2663 temp_type
= i
.types
[xchg
];
2664 i
.types
[xchg
] = i
.types
[0];
2665 i
.types
[0] = temp_type
;
2666 temp_op
= i
.op
[xchg
];
2667 i
.op
[xchg
] = i
.op
[0];
2670 gas_assert (i
.rm
.mode
== 3);
2674 i
.rm
.regmem
= i
.rm
.reg
;
2677 /* Use the next insn. */
2681 vector_length
= i
.tm
.opcode_modifier
.vex
== 2 ? 1 : 0;
2683 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2688 case DATA_PREFIX_OPCODE
:
2691 case REPE_PREFIX_OPCODE
:
2694 case REPNE_PREFIX_OPCODE
:
2701 /* Use 2-byte VEX prefix if possible. */
2702 if (i
.tm
.opcode_modifier
.vex0f
2703 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2705 /* 2-byte VEX prefix. */
2709 i
.vex
.bytes
[0] = 0xc5;
2711 /* Check the REX.R bit. */
2712 r
= (i
.rex
& REX_R
) ? 0 : 1;
2713 i
.vex
.bytes
[1] = (r
<< 7
2714 | register_specifier
<< 3
2715 | vector_length
<< 2
2720 /* 3-byte VEX prefix. */
2723 if (i
.tm
.opcode_modifier
.vex0f
)
2725 else if (i
.tm
.opcode_modifier
.vex0f38
)
2727 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2733 i
.vex
.bytes
[0] = 0xc4;
2735 /* The high 3 bits of the second VEX byte are 1's compliment
2736 of RXB bits from REX. */
2737 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2739 /* Check the REX.W bit. */
2740 w
= (i
.rex
& REX_W
) ? 1 : 0;
2741 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2746 if (i
.tm
.opcode_modifier
.vexw1
)
2750 i
.vex
.bytes
[2] = (w
<< 7
2751 | register_specifier
<< 3
2752 | vector_length
<< 2
2758 process_immext (void)
2762 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2764 /* SSE3 Instructions have the fixed operands with an opcode
2765 suffix which is coded in the same place as an 8-bit immediate
2766 field would be. Here we check those operands and remove them
2770 for (x
= 0; x
< i
.operands
; x
++)
2771 if (i
.op
[x
].regs
->reg_num
!= x
)
2772 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2773 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2779 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2780 which is coded in the same place as an 8-bit immediate field
2781 would be. Here we fake an 8-bit immediate operand from the
2782 opcode suffix stored in tm.extension_opcode.
2784 AVX instructions also use this encoding, for some of
2785 3 argument instructions. */
2787 gas_assert (i
.imm_operands
== 0
2789 || (i
.tm
.opcode_modifier
.vex
2790 && i
.operands
<= 4)));
2792 exp
= &im_expressions
[i
.imm_operands
++];
2793 i
.op
[i
.operands
].imms
= exp
;
2794 i
.types
[i
.operands
] = imm8
;
2796 exp
->X_op
= O_constant
;
2797 exp
->X_add_number
= i
.tm
.extension_opcode
;
2798 i
.tm
.extension_opcode
= None
;
2801 /* This is the guts of the machine-dependent assembler. LINE points to a
2802 machine dependent instruction. This function is supposed to emit
2803 the frags/bytes it assembles to. */
2806 md_assemble (char *line
)
2809 char mnemonic
[MAX_MNEM_SIZE
];
2810 const insn_template
*t
;
2812 /* Initialize globals. */
2813 memset (&i
, '\0', sizeof (i
));
2814 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2815 i
.reloc
[j
] = NO_RELOC
;
2816 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2817 memset (im_expressions
, '\0', sizeof (im_expressions
));
2818 save_stack_p
= save_stack
;
2820 /* First parse an instruction mnemonic & call i386_operand for the operands.
2821 We assume that the scrubber has arranged it so that line[0] is the valid
2822 start of a (possibly prefixed) mnemonic. */
2824 line
= parse_insn (line
, mnemonic
);
2828 line
= parse_operands (line
, mnemonic
);
2833 /* Now we've parsed the mnemonic into a set of templates, and have the
2834 operands at hand. */
2836 /* All intel opcodes have reversed operands except for "bound" and
2837 "enter". We also don't reverse intersegment "jmp" and "call"
2838 instructions with 2 immediate operands so that the immediate segment
2839 precedes the offset, as it does when in AT&T mode. */
2842 && (strcmp (mnemonic
, "bound") != 0)
2843 && (strcmp (mnemonic
, "invlpga") != 0)
2844 && !(operand_type_check (i
.types
[0], imm
)
2845 && operand_type_check (i
.types
[1], imm
)))
2848 /* The order of the immediates should be reversed
2849 for 2 immediates extrq and insertq instructions */
2850 if (i
.imm_operands
== 2
2851 && (strcmp (mnemonic
, "extrq") == 0
2852 || strcmp (mnemonic
, "insertq") == 0))
2853 swap_2_operands (0, 1);
2858 /* Don't optimize displacement for movabs since it only takes 64bit
2861 && (flag_code
!= CODE_64BIT
2862 || strcmp (mnemonic
, "movabs") != 0))
2865 /* Next, we find a template that matches the given insn,
2866 making sure the overlap of the given operands types is consistent
2867 with the template operand types. */
2869 if (!(t
= match_template ()))
2872 if (sse_check
!= sse_check_none
2873 && !i
.tm
.opcode_modifier
.noavx
2874 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2875 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2876 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2877 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2878 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2879 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2881 (sse_check
== sse_check_warning
2883 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2886 /* Zap movzx and movsx suffix. The suffix has been set from
2887 "word ptr" or "byte ptr" on the source operand in Intel syntax
2888 or extracted from mnemonic in AT&T syntax. But we'll use
2889 the destination register to choose the suffix for encoding. */
2890 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2892 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2893 there is no suffix, the default will be byte extension. */
2894 if (i
.reg_operands
!= 2
2897 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2902 if (i
.tm
.opcode_modifier
.fwait
)
2903 if (!add_prefix (FWAIT_OPCODE
))
2906 /* Check string instruction segment overrides. */
2907 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2909 if (!check_string ())
2911 i
.disp_operands
= 0;
2914 if (!process_suffix ())
2917 /* Update operand types. */
2918 for (j
= 0; j
< i
.operands
; j
++)
2919 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2921 /* Make still unresolved immediate matches conform to size of immediate
2922 given in i.suffix. */
2923 if (!finalize_imm ())
2926 if (i
.types
[0].bitfield
.imm1
)
2927 i
.imm_operands
= 0; /* kludge for shift insns. */
2929 /* We only need to check those implicit registers for instructions
2930 with 3 operands or less. */
2931 if (i
.operands
<= 3)
2932 for (j
= 0; j
< i
.operands
; j
++)
2933 if (i
.types
[j
].bitfield
.inoutportreg
2934 || i
.types
[j
].bitfield
.shiftcount
2935 || i
.types
[j
].bitfield
.acc
2936 || i
.types
[j
].bitfield
.floatacc
)
2939 /* ImmExt should be processed after SSE2AVX. */
2940 if (!i
.tm
.opcode_modifier
.sse2avx
2941 && i
.tm
.opcode_modifier
.immext
)
2944 /* For insns with operands there are more diddles to do to the opcode. */
2947 if (!process_operands ())
2950 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2952 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2953 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2956 if (i
.tm
.opcode_modifier
.vex
)
2957 build_vex_prefix (t
);
2959 /* Handle conversion of 'int $3' --> special int3 insn. */
2960 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2962 i
.tm
.base_opcode
= INT3_OPCODE
;
2966 if ((i
.tm
.opcode_modifier
.jump
2967 || i
.tm
.opcode_modifier
.jumpbyte
2968 || i
.tm
.opcode_modifier
.jumpdword
)
2969 && i
.op
[0].disps
->X_op
== O_constant
)
2971 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2972 the absolute address given by the constant. Since ix86 jumps and
2973 calls are pc relative, we need to generate a reloc. */
2974 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2975 i
.op
[0].disps
->X_op
= O_symbol
;
2978 if (i
.tm
.opcode_modifier
.rex64
)
2981 /* For 8 bit registers we need an empty rex prefix. Also if the
2982 instruction already has a prefix, we need to convert old
2983 registers to new ones. */
2985 if ((i
.types
[0].bitfield
.reg8
2986 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2987 || (i
.types
[1].bitfield
.reg8
2988 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2989 || ((i
.types
[0].bitfield
.reg8
2990 || i
.types
[1].bitfield
.reg8
)
2995 i
.rex
|= REX_OPCODE
;
2996 for (x
= 0; x
< 2; x
++)
2998 /* Look for 8 bit operand that uses old registers. */
2999 if (i
.types
[x
].bitfield
.reg8
3000 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3002 /* In case it is "hi" register, give up. */
3003 if (i
.op
[x
].regs
->reg_num
> 3)
3004 as_bad (_("can't encode register '%s%s' in an "
3005 "instruction requiring REX prefix."),
3006 register_prefix
, i
.op
[x
].regs
->reg_name
);
3008 /* Otherwise it is equivalent to the extended register.
3009 Since the encoding doesn't change this is merely
3010 cosmetic cleanup for debug output. */
3012 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3018 add_prefix (REX_OPCODE
| i
.rex
);
3020 /* We are ready to output the insn. */
3025 parse_insn (char *line
, char *mnemonic
)
3028 char *token_start
= l
;
3031 const insn_template
*t
;
3034 /* Non-zero if we found a prefix only acceptable with string insns. */
3035 const char *expecting_string_instruction
= NULL
;
3040 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3045 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3047 as_bad (_("no such instruction: `%s'"), token_start
);
3052 if (!is_space_char (*l
)
3053 && *l
!= END_OF_INSN
3055 || (*l
!= PREFIX_SEPARATOR
3058 as_bad (_("invalid character %s in mnemonic"),
3059 output_invalid (*l
));
3062 if (token_start
== l
)
3064 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3065 as_bad (_("expecting prefix; got nothing"));
3067 as_bad (_("expecting mnemonic; got nothing"));
3071 /* Look up instruction (or prefix) via hash table. */
3072 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3074 if (*l
!= END_OF_INSN
3075 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3076 && current_templates
3077 && current_templates
->start
->opcode_modifier
.isprefix
)
3079 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3081 as_bad ((flag_code
!= CODE_64BIT
3082 ? _("`%s' is only supported in 64-bit mode")
3083 : _("`%s' is not supported in 64-bit mode")),
3084 current_templates
->start
->name
);
3087 /* If we are in 16-bit mode, do not allow addr16 or data16.
3088 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3089 if ((current_templates
->start
->opcode_modifier
.size16
3090 || current_templates
->start
->opcode_modifier
.size32
)
3091 && flag_code
!= CODE_64BIT
3092 && (current_templates
->start
->opcode_modifier
.size32
3093 ^ (flag_code
== CODE_16BIT
)))
3095 as_bad (_("redundant %s prefix"),
3096 current_templates
->start
->name
);
3099 /* Add prefix, checking for repeated prefixes. */
3100 switch (add_prefix (current_templates
->start
->base_opcode
))
3105 expecting_string_instruction
= current_templates
->start
->name
;
3108 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3115 if (!current_templates
)
3117 /* Check if we should swap operand in encoding. */
3118 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3124 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3127 if (!current_templates
)
3130 /* See if we can get a match by trimming off a suffix. */
3133 case WORD_MNEM_SUFFIX
:
3134 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3135 i
.suffix
= SHORT_MNEM_SUFFIX
;
3137 case BYTE_MNEM_SUFFIX
:
3138 case QWORD_MNEM_SUFFIX
:
3139 i
.suffix
= mnem_p
[-1];
3141 current_templates
= (const templates
*) hash_find (op_hash
,
3144 case SHORT_MNEM_SUFFIX
:
3145 case LONG_MNEM_SUFFIX
:
3148 i
.suffix
= mnem_p
[-1];
3150 current_templates
= (const templates
*) hash_find (op_hash
,
3159 if (intel_float_operand (mnemonic
) == 1)
3160 i
.suffix
= SHORT_MNEM_SUFFIX
;
3162 i
.suffix
= LONG_MNEM_SUFFIX
;
3164 current_templates
= (const templates
*) hash_find (op_hash
,
3169 if (!current_templates
)
3171 as_bad (_("no such instruction: `%s'"), token_start
);
3176 if (current_templates
->start
->opcode_modifier
.jump
3177 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3179 /* Check for a branch hint. We allow ",pt" and ",pn" for
3180 predict taken and predict not taken respectively.
3181 I'm not sure that branch hints actually do anything on loop
3182 and jcxz insns (JumpByte) for current Pentium4 chips. They
3183 may work in the future and it doesn't hurt to accept them
3185 if (l
[0] == ',' && l
[1] == 'p')
3189 if (!add_prefix (DS_PREFIX_OPCODE
))
3193 else if (l
[2] == 'n')
3195 if (!add_prefix (CS_PREFIX_OPCODE
))
3201 /* Any other comma loses. */
3204 as_bad (_("invalid character %s in mnemonic"),
3205 output_invalid (*l
));
3209 /* Check if instruction is supported on specified architecture. */
3211 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3213 supported
|= cpu_flags_match (t
);
3214 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3218 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3220 as_bad (flag_code
== CODE_64BIT
3221 ? _("`%s' is not supported in 64-bit mode")
3222 : _("`%s' is only supported in 64-bit mode"),
3223 current_templates
->start
->name
);
3226 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3228 as_bad (_("`%s' is not supported on `%s%s'"),
3229 current_templates
->start
->name
,
3230 cpu_arch_name
? cpu_arch_name
: default_arch
,
3231 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3236 if (!cpu_arch_flags
.bitfield
.cpui386
3237 && (flag_code
!= CODE_16BIT
))
3239 as_warn (_("use .code16 to ensure correct addressing mode"));
3242 /* Check for rep/repne without a string instruction. */
3243 if (expecting_string_instruction
)
3245 static templates override
;
3247 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3248 if (t
->opcode_modifier
.isstring
)
3250 if (t
>= current_templates
->end
)
3252 as_bad (_("expecting string instruction after `%s'"),
3253 expecting_string_instruction
);
3256 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3257 if (!t
->opcode_modifier
.isstring
)
3260 current_templates
= &override
;
3267 parse_operands (char *l
, const char *mnemonic
)
3271 /* 1 if operand is pending after ','. */
3272 unsigned int expecting_operand
= 0;
3274 /* Non-zero if operand parens not balanced. */
3275 unsigned int paren_not_balanced
;
3277 while (*l
!= END_OF_INSN
)
3279 /* Skip optional white space before operand. */
3280 if (is_space_char (*l
))
3282 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3284 as_bad (_("invalid character %s before operand %d"),
3285 output_invalid (*l
),
3289 token_start
= l
; /* after white space */
3290 paren_not_balanced
= 0;
3291 while (paren_not_balanced
|| *l
!= ',')
3293 if (*l
== END_OF_INSN
)
3295 if (paren_not_balanced
)
3298 as_bad (_("unbalanced parenthesis in operand %d."),
3301 as_bad (_("unbalanced brackets in operand %d."),
3306 break; /* we are done */
3308 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3310 as_bad (_("invalid character %s in operand %d"),
3311 output_invalid (*l
),
3318 ++paren_not_balanced
;
3320 --paren_not_balanced
;
3325 ++paren_not_balanced
;
3327 --paren_not_balanced
;
3331 if (l
!= token_start
)
3332 { /* Yes, we've read in another operand. */
3333 unsigned int operand_ok
;
3334 this_operand
= i
.operands
++;
3335 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3336 if (i
.operands
> MAX_OPERANDS
)
3338 as_bad (_("spurious operands; (%d operands/instruction max)"),
3342 /* Now parse operand adding info to 'i' as we go along. */
3343 END_STRING_AND_SAVE (l
);
3347 i386_intel_operand (token_start
,
3348 intel_float_operand (mnemonic
));
3350 operand_ok
= i386_att_operand (token_start
);
3352 RESTORE_END_STRING (l
);
3358 if (expecting_operand
)
3360 expecting_operand_after_comma
:
3361 as_bad (_("expecting operand after ','; got nothing"));
3366 as_bad (_("expecting operand before ','; got nothing"));
3371 /* Now *l must be either ',' or END_OF_INSN. */
3374 if (*++l
== END_OF_INSN
)
3376 /* Just skip it, if it's \n complain. */
3377 goto expecting_operand_after_comma
;
3379 expecting_operand
= 1;
3386 swap_2_operands (int xchg1
, int xchg2
)
3388 union i386_op temp_op
;
3389 i386_operand_type temp_type
;
3390 enum bfd_reloc_code_real temp_reloc
;
3392 temp_type
= i
.types
[xchg2
];
3393 i
.types
[xchg2
] = i
.types
[xchg1
];
3394 i
.types
[xchg1
] = temp_type
;
3395 temp_op
= i
.op
[xchg2
];
3396 i
.op
[xchg2
] = i
.op
[xchg1
];
3397 i
.op
[xchg1
] = temp_op
;
3398 temp_reloc
= i
.reloc
[xchg2
];
3399 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3400 i
.reloc
[xchg1
] = temp_reloc
;
3404 swap_operands (void)
3410 swap_2_operands (1, i
.operands
- 2);
3413 swap_2_operands (0, i
.operands
- 1);
3419 if (i
.mem_operands
== 2)
3421 const seg_entry
*temp_seg
;
3422 temp_seg
= i
.seg
[0];
3423 i
.seg
[0] = i
.seg
[1];
3424 i
.seg
[1] = temp_seg
;
3428 /* Try to ensure constant immediates are represented in the smallest
3433 char guess_suffix
= 0;
3437 guess_suffix
= i
.suffix
;
3438 else if (i
.reg_operands
)
3440 /* Figure out a suffix from the last register operand specified.
3441 We can't do this properly yet, ie. excluding InOutPortReg,
3442 but the following works for instructions with immediates.
3443 In any case, we can't set i.suffix yet. */
3444 for (op
= i
.operands
; --op
>= 0;)
3445 if (i
.types
[op
].bitfield
.reg8
)
3447 guess_suffix
= BYTE_MNEM_SUFFIX
;
3450 else if (i
.types
[op
].bitfield
.reg16
)
3452 guess_suffix
= WORD_MNEM_SUFFIX
;
3455 else if (i
.types
[op
].bitfield
.reg32
)
3457 guess_suffix
= LONG_MNEM_SUFFIX
;
3460 else if (i
.types
[op
].bitfield
.reg64
)
3462 guess_suffix
= QWORD_MNEM_SUFFIX
;
3466 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3467 guess_suffix
= WORD_MNEM_SUFFIX
;
3469 for (op
= i
.operands
; --op
>= 0;)
3470 if (operand_type_check (i
.types
[op
], imm
))
3472 switch (i
.op
[op
].imms
->X_op
)
3475 /* If a suffix is given, this operand may be shortened. */
3476 switch (guess_suffix
)
3478 case LONG_MNEM_SUFFIX
:
3479 i
.types
[op
].bitfield
.imm32
= 1;
3480 i
.types
[op
].bitfield
.imm64
= 1;
3482 case WORD_MNEM_SUFFIX
:
3483 i
.types
[op
].bitfield
.imm16
= 1;
3484 i
.types
[op
].bitfield
.imm32
= 1;
3485 i
.types
[op
].bitfield
.imm32s
= 1;
3486 i
.types
[op
].bitfield
.imm64
= 1;
3488 case BYTE_MNEM_SUFFIX
:
3489 i
.types
[op
].bitfield
.imm8
= 1;
3490 i
.types
[op
].bitfield
.imm8s
= 1;
3491 i
.types
[op
].bitfield
.imm16
= 1;
3492 i
.types
[op
].bitfield
.imm32
= 1;
3493 i
.types
[op
].bitfield
.imm32s
= 1;
3494 i
.types
[op
].bitfield
.imm64
= 1;
3498 /* If this operand is at most 16 bits, convert it
3499 to a signed 16 bit number before trying to see
3500 whether it will fit in an even smaller size.
3501 This allows a 16-bit operand such as $0xffe0 to
3502 be recognised as within Imm8S range. */
3503 if ((i
.types
[op
].bitfield
.imm16
)
3504 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3506 i
.op
[op
].imms
->X_add_number
=
3507 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3509 if ((i
.types
[op
].bitfield
.imm32
)
3510 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3513 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3514 ^ ((offsetT
) 1 << 31))
3515 - ((offsetT
) 1 << 31));
3518 = operand_type_or (i
.types
[op
],
3519 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3521 /* We must avoid matching of Imm32 templates when 64bit
3522 only immediate is available. */
3523 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3524 i
.types
[op
].bitfield
.imm32
= 0;
3531 /* Symbols and expressions. */
3533 /* Convert symbolic operand to proper sizes for matching, but don't
3534 prevent matching a set of insns that only supports sizes other
3535 than those matching the insn suffix. */
3537 i386_operand_type mask
, allowed
;
3538 const insn_template
*t
;
3540 operand_type_set (&mask
, 0);
3541 operand_type_set (&allowed
, 0);
3543 for (t
= current_templates
->start
;
3544 t
< current_templates
->end
;
3546 allowed
= operand_type_or (allowed
,
3547 t
->operand_types
[op
]);
3548 switch (guess_suffix
)
3550 case QWORD_MNEM_SUFFIX
:
3551 mask
.bitfield
.imm64
= 1;
3552 mask
.bitfield
.imm32s
= 1;
3554 case LONG_MNEM_SUFFIX
:
3555 mask
.bitfield
.imm32
= 1;
3557 case WORD_MNEM_SUFFIX
:
3558 mask
.bitfield
.imm16
= 1;
3560 case BYTE_MNEM_SUFFIX
:
3561 mask
.bitfield
.imm8
= 1;
3566 allowed
= operand_type_and (mask
, allowed
);
3567 if (!operand_type_all_zero (&allowed
))
3568 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3575 /* Try to use the smallest displacement type too. */
3577 optimize_disp (void)
3581 for (op
= i
.operands
; --op
>= 0;)
3582 if (operand_type_check (i
.types
[op
], disp
))
3584 if (i
.op
[op
].disps
->X_op
== O_constant
)
3586 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3588 if (i
.types
[op
].bitfield
.disp16
3589 && (disp
& ~(offsetT
) 0xffff) == 0)
3591 /* If this operand is at most 16 bits, convert
3592 to a signed 16 bit number and don't use 64bit
3594 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3595 i
.types
[op
].bitfield
.disp64
= 0;
3597 if (i
.types
[op
].bitfield
.disp32
3598 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3600 /* If this operand is at most 32 bits, convert
3601 to a signed 32 bit number and don't use 64bit
3603 disp
&= (((offsetT
) 2 << 31) - 1);
3604 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3605 i
.types
[op
].bitfield
.disp64
= 0;
3607 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3609 i
.types
[op
].bitfield
.disp8
= 0;
3610 i
.types
[op
].bitfield
.disp16
= 0;
3611 i
.types
[op
].bitfield
.disp32
= 0;
3612 i
.types
[op
].bitfield
.disp32s
= 0;
3613 i
.types
[op
].bitfield
.disp64
= 0;
3617 else if (flag_code
== CODE_64BIT
)
3619 if (fits_in_signed_long (disp
))
3621 i
.types
[op
].bitfield
.disp64
= 0;
3622 i
.types
[op
].bitfield
.disp32s
= 1;
3624 if (i
.prefix
[ADDR_PREFIX
]
3625 && fits_in_unsigned_long (disp
))
3626 i
.types
[op
].bitfield
.disp32
= 1;
3628 if ((i
.types
[op
].bitfield
.disp32
3629 || i
.types
[op
].bitfield
.disp32s
3630 || i
.types
[op
].bitfield
.disp16
)
3631 && fits_in_signed_byte (disp
))
3632 i
.types
[op
].bitfield
.disp8
= 1;
3634 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3635 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3637 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3638 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3639 i
.types
[op
].bitfield
.disp8
= 0;
3640 i
.types
[op
].bitfield
.disp16
= 0;
3641 i
.types
[op
].bitfield
.disp32
= 0;
3642 i
.types
[op
].bitfield
.disp32s
= 0;
3643 i
.types
[op
].bitfield
.disp64
= 0;
3646 /* We only support 64bit displacement on constants. */
3647 i
.types
[op
].bitfield
.disp64
= 0;
3651 static const insn_template
*
3652 match_template (void)
3654 /* Points to template once we've found it. */
3655 const insn_template
*t
;
3656 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3657 i386_operand_type overlap4
;
3658 unsigned int found_reverse_match
;
3659 i386_opcode_modifier suffix_check
;
3660 i386_operand_type operand_types
[MAX_OPERANDS
];
3661 int addr_prefix_disp
;
3663 unsigned int found_cpu_match
;
3664 unsigned int check_register
;
3666 #if MAX_OPERANDS != 5
3667 # error "MAX_OPERANDS must be 5."
3670 found_reverse_match
= 0;
3671 addr_prefix_disp
= -1;
3673 memset (&suffix_check
, 0, sizeof (suffix_check
));
3674 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3675 suffix_check
.no_bsuf
= 1;
3676 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3677 suffix_check
.no_wsuf
= 1;
3678 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3679 suffix_check
.no_ssuf
= 1;
3680 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3681 suffix_check
.no_lsuf
= 1;
3682 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3683 suffix_check
.no_qsuf
= 1;
3684 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3685 suffix_check
.no_ldsuf
= 1;
3687 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3689 addr_prefix_disp
= -1;
3691 /* Must have right number of operands. */
3692 if (i
.operands
!= t
->operands
)
3695 /* Check processor support. */
3696 found_cpu_match
= (cpu_flags_match (t
)
3697 == CPU_FLAGS_PERFECT_MATCH
);
3698 if (!found_cpu_match
)
3701 /* Check old gcc support. */
3702 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3705 /* Check AT&T mnemonic. */
3706 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3709 /* Check AT&T syntax Intel syntax. */
3710 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3711 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3714 /* Check the suffix, except for some instructions in intel mode. */
3715 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3716 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3717 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3718 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3719 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3720 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3721 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3724 if (!operand_size_match (t
))
3727 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3728 operand_types
[j
] = t
->operand_types
[j
];
3730 /* In general, don't allow 64-bit operands in 32-bit mode. */
3731 if (i
.suffix
== QWORD_MNEM_SUFFIX
3732 && flag_code
!= CODE_64BIT
3734 ? (!t
->opcode_modifier
.ignoresize
3735 && !intel_float_operand (t
->name
))
3736 : intel_float_operand (t
->name
) != 2)
3737 && ((!operand_types
[0].bitfield
.regmmx
3738 && !operand_types
[0].bitfield
.regxmm
3739 && !operand_types
[0].bitfield
.regymm
)
3740 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3741 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3742 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3743 && (t
->base_opcode
!= 0x0fc7
3744 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3747 /* In general, don't allow 32-bit operands on pre-386. */
3748 else if (i
.suffix
== LONG_MNEM_SUFFIX
3749 && !cpu_arch_flags
.bitfield
.cpui386
3751 ? (!t
->opcode_modifier
.ignoresize
3752 && !intel_float_operand (t
->name
))
3753 : intel_float_operand (t
->name
) != 2)
3754 && ((!operand_types
[0].bitfield
.regmmx
3755 && !operand_types
[0].bitfield
.regxmm
)
3756 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3757 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3760 /* Do not verify operands when there are none. */
3764 /* We've found a match; break out of loop. */
3768 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3769 into Disp32/Disp16/Disp32 operand. */
3770 if (i
.prefix
[ADDR_PREFIX
] != 0)
3772 /* There should be only one Disp operand. */
3776 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3778 if (operand_types
[j
].bitfield
.disp16
)
3780 addr_prefix_disp
= j
;
3781 operand_types
[j
].bitfield
.disp32
= 1;
3782 operand_types
[j
].bitfield
.disp16
= 0;
3788 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3790 if (operand_types
[j
].bitfield
.disp32
)
3792 addr_prefix_disp
= j
;
3793 operand_types
[j
].bitfield
.disp32
= 0;
3794 operand_types
[j
].bitfield
.disp16
= 1;
3800 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3802 if (operand_types
[j
].bitfield
.disp64
)
3804 addr_prefix_disp
= j
;
3805 operand_types
[j
].bitfield
.disp64
= 0;
3806 operand_types
[j
].bitfield
.disp32
= 1;
3814 /* We check register size only if size of operands can be
3815 encoded the canonical way. */
3816 check_register
= t
->opcode_modifier
.w
;
3817 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3818 switch (t
->operands
)
3821 if (!operand_type_match (overlap0
, i
.types
[0]))
3825 /* xchg %eax, %eax is a special case. It is an aliase for nop
3826 only in 32bit mode and we can use opcode 0x90. In 64bit
3827 mode, we can't use 0x90 for xchg %eax, %eax since it should
3828 zero-extend %eax to %rax. */
3829 if (flag_code
== CODE_64BIT
3830 && t
->base_opcode
== 0x90
3831 && operand_type_equal (&i
.types
[0], &acc32
)
3832 && operand_type_equal (&i
.types
[1], &acc32
))
3836 /* If we swap operand in encoding, we either match
3837 the next one or reverse direction of operands. */
3838 if (t
->opcode_modifier
.s
)
3840 else if (t
->opcode_modifier
.d
)
3845 /* If we swap operand in encoding, we match the next one. */
3846 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3850 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3851 if (!operand_type_match (overlap0
, i
.types
[0])
3852 || !operand_type_match (overlap1
, i
.types
[1])
3854 && !operand_type_register_match (overlap0
, i
.types
[0],
3856 overlap1
, i
.types
[1],
3859 /* Check if other direction is valid ... */
3860 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3864 /* Try reversing direction of operands. */
3865 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3866 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3867 if (!operand_type_match (overlap0
, i
.types
[0])
3868 || !operand_type_match (overlap1
, i
.types
[1])
3870 && !operand_type_register_match (overlap0
,
3877 /* Does not match either direction. */
3880 /* found_reverse_match holds which of D or FloatDR
3882 if (t
->opcode_modifier
.d
)
3883 found_reverse_match
= Opcode_D
;
3884 else if (t
->opcode_modifier
.floatd
)
3885 found_reverse_match
= Opcode_FloatD
;
3887 found_reverse_match
= 0;
3888 if (t
->opcode_modifier
.floatr
)
3889 found_reverse_match
|= Opcode_FloatR
;
3893 /* Found a forward 2 operand match here. */
3894 switch (t
->operands
)
3897 overlap4
= operand_type_and (i
.types
[4],
3900 overlap3
= operand_type_and (i
.types
[3],
3903 overlap2
= operand_type_and (i
.types
[2],
3908 switch (t
->operands
)
3911 if (!operand_type_match (overlap4
, i
.types
[4])
3912 || !operand_type_register_match (overlap3
,
3920 if (!operand_type_match (overlap3
, i
.types
[3])
3922 && !operand_type_register_match (overlap2
,
3930 /* Here we make use of the fact that there are no
3931 reverse match 3 operand instructions, and all 3
3932 operand instructions only need to be checked for
3933 register consistency between operands 2 and 3. */
3934 if (!operand_type_match (overlap2
, i
.types
[2])
3936 && !operand_type_register_match (overlap1
,
3946 /* Found either forward/reverse 2, 3 or 4 operand match here:
3947 slip through to break. */
3949 if (!found_cpu_match
)
3951 found_reverse_match
= 0;
3955 /* We've found a match; break out of loop. */
3959 if (t
== current_templates
->end
)
3961 /* We found no match. */
3963 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3964 current_templates
->start
->name
);
3966 as_bad (_("suffix or operands invalid for `%s'"),
3967 current_templates
->start
->name
);
3971 if (!quiet_warnings
)
3974 && (i
.types
[0].bitfield
.jumpabsolute
3975 != operand_types
[0].bitfield
.jumpabsolute
))
3977 as_warn (_("indirect %s without `*'"), t
->name
);
3980 if (t
->opcode_modifier
.isprefix
3981 && t
->opcode_modifier
.ignoresize
)
3983 /* Warn them that a data or address size prefix doesn't
3984 affect assembly of the next line of code. */
3985 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3989 /* Copy the template we found. */
3992 if (addr_prefix_disp
!= -1)
3993 i
.tm
.operand_types
[addr_prefix_disp
]
3994 = operand_types
[addr_prefix_disp
];
3996 if (found_reverse_match
)
3998 /* If we found a reverse match we must alter the opcode
3999 direction bit. found_reverse_match holds bits to change
4000 (different for int & float insns). */
4002 i
.tm
.base_opcode
^= found_reverse_match
;
4004 i
.tm
.operand_types
[0] = operand_types
[1];
4005 i
.tm
.operand_types
[1] = operand_types
[0];
4014 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4015 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4017 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4019 as_bad (_("`%s' operand %d must use `%ses' segment"),
4025 /* There's only ever one segment override allowed per instruction.
4026 This instruction possibly has a legal segment override on the
4027 second operand, so copy the segment to where non-string
4028 instructions store it, allowing common code. */
4029 i
.seg
[0] = i
.seg
[1];
4031 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4033 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4035 as_bad (_("`%s' operand %d must use `%ses' segment"),
4046 process_suffix (void)
4048 /* If matched instruction specifies an explicit instruction mnemonic
4050 if (i
.tm
.opcode_modifier
.size16
)
4051 i
.suffix
= WORD_MNEM_SUFFIX
;
4052 else if (i
.tm
.opcode_modifier
.size32
)
4053 i
.suffix
= LONG_MNEM_SUFFIX
;
4054 else if (i
.tm
.opcode_modifier
.size64
)
4055 i
.suffix
= QWORD_MNEM_SUFFIX
;
4056 else if (i
.reg_operands
)
4058 /* If there's no instruction mnemonic suffix we try to invent one
4059 based on register operands. */
4062 /* We take i.suffix from the last register operand specified,
4063 Destination register type is more significant than source
4064 register type. crc32 in SSE4.2 prefers source register
4066 if (i
.tm
.base_opcode
== 0xf20f38f1)
4068 if (i
.types
[0].bitfield
.reg16
)
4069 i
.suffix
= WORD_MNEM_SUFFIX
;
4070 else if (i
.types
[0].bitfield
.reg32
)
4071 i
.suffix
= LONG_MNEM_SUFFIX
;
4072 else if (i
.types
[0].bitfield
.reg64
)
4073 i
.suffix
= QWORD_MNEM_SUFFIX
;
4075 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4077 if (i
.types
[0].bitfield
.reg8
)
4078 i
.suffix
= BYTE_MNEM_SUFFIX
;
4085 if (i
.tm
.base_opcode
== 0xf20f38f1
4086 || i
.tm
.base_opcode
== 0xf20f38f0)
4088 /* We have to know the operand size for crc32. */
4089 as_bad (_("ambiguous memory operand size for `%s`"),
4094 for (op
= i
.operands
; --op
>= 0;)
4095 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4097 if (i
.types
[op
].bitfield
.reg8
)
4099 i
.suffix
= BYTE_MNEM_SUFFIX
;
4102 else if (i
.types
[op
].bitfield
.reg16
)
4104 i
.suffix
= WORD_MNEM_SUFFIX
;
4107 else if (i
.types
[op
].bitfield
.reg32
)
4109 i
.suffix
= LONG_MNEM_SUFFIX
;
4112 else if (i
.types
[op
].bitfield
.reg64
)
4114 i
.suffix
= QWORD_MNEM_SUFFIX
;
4120 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4122 if (!check_byte_reg ())
4125 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4127 if (!check_long_reg ())
4130 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4133 && i
.tm
.opcode_modifier
.ignoresize
4134 && i
.tm
.opcode_modifier
.no_qsuf
)
4136 else if (!check_qword_reg ())
4139 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4141 if (!check_word_reg ())
4144 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4145 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4147 /* Skip if the instruction has x/y suffix. match_template
4148 should check if it is a valid suffix. */
4150 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4151 /* Do nothing if the instruction is going to ignore the prefix. */
4156 else if (i
.tm
.opcode_modifier
.defaultsize
4158 /* exclude fldenv/frstor/fsave/fstenv */
4159 && i
.tm
.opcode_modifier
.no_ssuf
)
4161 i
.suffix
= stackop_size
;
4163 else if (intel_syntax
4165 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4166 || i
.tm
.opcode_modifier
.jumpbyte
4167 || i
.tm
.opcode_modifier
.jumpintersegment
4168 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4169 && i
.tm
.extension_opcode
<= 3)))
4174 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4176 i
.suffix
= QWORD_MNEM_SUFFIX
;
4180 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4181 i
.suffix
= LONG_MNEM_SUFFIX
;
4184 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4185 i
.suffix
= WORD_MNEM_SUFFIX
;
4194 if (i
.tm
.opcode_modifier
.w
)
4196 as_bad (_("no instruction mnemonic suffix given and "
4197 "no register operands; can't size instruction"));
4203 unsigned int suffixes
;
4205 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4206 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4208 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4210 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4212 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4214 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4217 /* There are more than suffix matches. */
4218 if (i
.tm
.opcode_modifier
.w
4219 || ((suffixes
& (suffixes
- 1))
4220 && !i
.tm
.opcode_modifier
.defaultsize
4221 && !i
.tm
.opcode_modifier
.ignoresize
))
4223 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4229 /* Change the opcode based on the operand size given by i.suffix;
4230 We don't need to change things for byte insns. */
4233 && i
.suffix
!= BYTE_MNEM_SUFFIX
4234 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4235 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4237 /* It's not a byte, select word/dword operation. */
4238 if (i
.tm
.opcode_modifier
.w
)
4240 if (i
.tm
.opcode_modifier
.shortform
)
4241 i
.tm
.base_opcode
|= 8;
4243 i
.tm
.base_opcode
|= 1;
4246 /* Now select between word & dword operations via the operand
4247 size prefix, except for instructions that will ignore this
4249 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4251 /* The address size override prefix changes the size of the
4253 if ((flag_code
== CODE_32BIT
4254 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4255 || (flag_code
!= CODE_32BIT
4256 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4257 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4260 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4261 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4262 && !i
.tm
.opcode_modifier
.ignoresize
4263 && !i
.tm
.opcode_modifier
.floatmf
4264 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4265 || (flag_code
== CODE_64BIT
4266 && i
.tm
.opcode_modifier
.jumpbyte
)))
4268 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4270 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4271 prefix
= ADDR_PREFIX_OPCODE
;
4273 if (!add_prefix (prefix
))
4277 /* Set mode64 for an operand. */
4278 if (i
.suffix
== QWORD_MNEM_SUFFIX
4279 && flag_code
== CODE_64BIT
4280 && !i
.tm
.opcode_modifier
.norex64
)
4282 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4283 need rex64. cmpxchg8b is also a special case. */
4284 if (! (i
.operands
== 2
4285 && i
.tm
.base_opcode
== 0x90
4286 && i
.tm
.extension_opcode
== None
4287 && operand_type_equal (&i
.types
[0], &acc64
)
4288 && operand_type_equal (&i
.types
[1], &acc64
))
4289 && ! (i
.operands
== 1
4290 && i
.tm
.base_opcode
== 0xfc7
4291 && i
.tm
.extension_opcode
== 1
4292 && !operand_type_check (i
.types
[0], reg
)
4293 && operand_type_check (i
.types
[0], anymem
)))
4297 /* Size floating point instruction. */
4298 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4299 if (i
.tm
.opcode_modifier
.floatmf
)
4300 i
.tm
.base_opcode
^= 4;
4307 check_byte_reg (void)
4311 for (op
= i
.operands
; --op
>= 0;)
4313 /* If this is an eight bit register, it's OK. If it's the 16 or
4314 32 bit version of an eight bit register, we will just use the
4315 low portion, and that's OK too. */
4316 if (i
.types
[op
].bitfield
.reg8
)
4319 /* Don't generate this warning if not needed. */
4320 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4323 /* crc32 doesn't generate this warning. */
4324 if (i
.tm
.base_opcode
== 0xf20f38f0)
4327 if ((i
.types
[op
].bitfield
.reg16
4328 || i
.types
[op
].bitfield
.reg32
4329 || i
.types
[op
].bitfield
.reg64
)
4330 && i
.op
[op
].regs
->reg_num
< 4)
4332 /* Prohibit these changes in the 64bit mode, since the
4333 lowering is more complicated. */
4334 if (flag_code
== CODE_64BIT
4335 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4337 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4338 register_prefix
, i
.op
[op
].regs
->reg_name
,
4342 #if REGISTER_WARNINGS
4344 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4345 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4347 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4348 ? REGNAM_AL
- REGNAM_AX
4349 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4351 i
.op
[op
].regs
->reg_name
,
4356 /* Any other register is bad. */
4357 if (i
.types
[op
].bitfield
.reg16
4358 || i
.types
[op
].bitfield
.reg32
4359 || i
.types
[op
].bitfield
.reg64
4360 || i
.types
[op
].bitfield
.regmmx
4361 || i
.types
[op
].bitfield
.regxmm
4362 || i
.types
[op
].bitfield
.regymm
4363 || i
.types
[op
].bitfield
.sreg2
4364 || i
.types
[op
].bitfield
.sreg3
4365 || i
.types
[op
].bitfield
.control
4366 || i
.types
[op
].bitfield
.debug
4367 || i
.types
[op
].bitfield
.test
4368 || i
.types
[op
].bitfield
.floatreg
4369 || i
.types
[op
].bitfield
.floatacc
)
4371 as_bad (_("`%s%s' not allowed with `%s%c'"),
4373 i
.op
[op
].regs
->reg_name
,
4383 check_long_reg (void)
4387 for (op
= i
.operands
; --op
>= 0;)
4388 /* Reject eight bit registers, except where the template requires
4389 them. (eg. movzb) */
4390 if (i
.types
[op
].bitfield
.reg8
4391 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4392 || i
.tm
.operand_types
[op
].bitfield
.reg32
4393 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4395 as_bad (_("`%s%s' not allowed with `%s%c'"),
4397 i
.op
[op
].regs
->reg_name
,
4402 /* Warn if the e prefix on a general reg is missing. */
4403 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4404 && i
.types
[op
].bitfield
.reg16
4405 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4406 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4408 /* Prohibit these changes in the 64bit mode, since the
4409 lowering is more complicated. */
4410 if (flag_code
== CODE_64BIT
)
4412 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4413 register_prefix
, i
.op
[op
].regs
->reg_name
,
4417 #if REGISTER_WARNINGS
4419 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4421 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4423 i
.op
[op
].regs
->reg_name
,
4427 /* Warn if the r prefix on a general reg is missing. */
4428 else if (i
.types
[op
].bitfield
.reg64
4429 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4430 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4433 && i
.tm
.opcode_modifier
.toqword
4434 && !i
.types
[0].bitfield
.regxmm
)
4436 /* Convert to QWORD. We want REX byte. */
4437 i
.suffix
= QWORD_MNEM_SUFFIX
;
4441 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4442 register_prefix
, i
.op
[op
].regs
->reg_name
,
4451 check_qword_reg (void)
4455 for (op
= i
.operands
; --op
>= 0; )
4456 /* Reject eight bit registers, except where the template requires
4457 them. (eg. movzb) */
4458 if (i
.types
[op
].bitfield
.reg8
4459 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4460 || i
.tm
.operand_types
[op
].bitfield
.reg32
4461 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4463 as_bad (_("`%s%s' not allowed with `%s%c'"),
4465 i
.op
[op
].regs
->reg_name
,
4470 /* Warn if the e prefix on a general reg is missing. */
4471 else if ((i
.types
[op
].bitfield
.reg16
4472 || i
.types
[op
].bitfield
.reg32
)
4473 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4474 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4476 /* Prohibit these changes in the 64bit mode, since the
4477 lowering is more complicated. */
4479 && i
.tm
.opcode_modifier
.todword
4480 && !i
.types
[0].bitfield
.regxmm
)
4482 /* Convert to DWORD. We don't want REX byte. */
4483 i
.suffix
= LONG_MNEM_SUFFIX
;
4487 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4488 register_prefix
, i
.op
[op
].regs
->reg_name
,
4497 check_word_reg (void)
4500 for (op
= i
.operands
; --op
>= 0;)
4501 /* Reject eight bit registers, except where the template requires
4502 them. (eg. movzb) */
4503 if (i
.types
[op
].bitfield
.reg8
4504 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4505 || i
.tm
.operand_types
[op
].bitfield
.reg32
4506 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4508 as_bad (_("`%s%s' not allowed with `%s%c'"),
4510 i
.op
[op
].regs
->reg_name
,
4515 /* Warn if the e prefix on a general reg is present. */
4516 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4517 && i
.types
[op
].bitfield
.reg32
4518 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4519 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4521 /* Prohibit these changes in the 64bit mode, since the
4522 lowering is more complicated. */
4523 if (flag_code
== CODE_64BIT
)
4525 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4526 register_prefix
, i
.op
[op
].regs
->reg_name
,
4531 #if REGISTER_WARNINGS
4532 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4534 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4536 i
.op
[op
].regs
->reg_name
,
4544 update_imm (unsigned int j
)
4546 i386_operand_type overlap
= i
.types
[j
];
4547 if ((overlap
.bitfield
.imm8
4548 || overlap
.bitfield
.imm8s
4549 || overlap
.bitfield
.imm16
4550 || overlap
.bitfield
.imm32
4551 || overlap
.bitfield
.imm32s
4552 || overlap
.bitfield
.imm64
)
4553 && !operand_type_equal (&overlap
, &imm8
)
4554 && !operand_type_equal (&overlap
, &imm8s
)
4555 && !operand_type_equal (&overlap
, &imm16
)
4556 && !operand_type_equal (&overlap
, &imm32
)
4557 && !operand_type_equal (&overlap
, &imm32s
)
4558 && !operand_type_equal (&overlap
, &imm64
))
4562 i386_operand_type temp
;
4564 operand_type_set (&temp
, 0);
4565 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4567 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4568 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4570 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4571 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4572 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4574 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4575 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4578 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4581 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4582 || operand_type_equal (&overlap
, &imm16_32
)
4583 || operand_type_equal (&overlap
, &imm16_32s
))
4585 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4590 if (!operand_type_equal (&overlap
, &imm8
)
4591 && !operand_type_equal (&overlap
, &imm8s
)
4592 && !operand_type_equal (&overlap
, &imm16
)
4593 && !operand_type_equal (&overlap
, &imm32
)
4594 && !operand_type_equal (&overlap
, &imm32s
)
4595 && !operand_type_equal (&overlap
, &imm64
))
4597 as_bad (_("no instruction mnemonic suffix given; "
4598 "can't determine immediate size"));
4602 i
.types
[j
] = overlap
;
4612 /* Update the first 2 immediate operands. */
4613 n
= i
.operands
> 2 ? 2 : i
.operands
;
4616 for (j
= 0; j
< n
; j
++)
4617 if (update_imm (j
) == 0)
4620 /* The 3rd operand can't be immediate operand. */
4621 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4628 bad_implicit_operand (int xmm
)
4630 const char *reg
= xmm
? "xmm0" : "ymm0";
4632 as_bad (_("the last operand of `%s' must be `%s%s'"),
4633 i
.tm
.name
, register_prefix
, reg
);
4635 as_bad (_("the first operand of `%s' must be `%s%s'"),
4636 i
.tm
.name
, register_prefix
, reg
);
4641 process_operands (void)
4643 /* Default segment register this instruction will use for memory
4644 accesses. 0 means unknown. This is only for optimizing out
4645 unnecessary segment overrides. */
4646 const seg_entry
*default_seg
= 0;
4648 if (i
.tm
.opcode_modifier
.sse2avx
4649 && (i
.tm
.opcode_modifier
.vexnds
4650 || i
.tm
.opcode_modifier
.vexndd
))
4652 unsigned int dup
= i
.operands
;
4653 unsigned int dest
= dup
- 1;
4656 /* The destination must be an xmm register. */
4657 gas_assert (i
.reg_operands
4658 && MAX_OPERANDS
> dup
4659 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4661 if (i
.tm
.opcode_modifier
.firstxmm0
)
4663 /* The first operand is implicit and must be xmm0. */
4664 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4665 if (i
.op
[0].regs
->reg_num
!= 0)
4666 return bad_implicit_operand (1);
4668 if (i
.tm
.opcode_modifier
.vex3sources
)
4670 /* Keep xmm0 for instructions with VEX prefix and 3
4676 /* We remove the first xmm0 and keep the number of
4677 operands unchanged, which in fact duplicates the
4679 for (j
= 1; j
< i
.operands
; j
++)
4681 i
.op
[j
- 1] = i
.op
[j
];
4682 i
.types
[j
- 1] = i
.types
[j
];
4683 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4687 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4689 gas_assert ((MAX_OPERANDS
- 1) > dup
4690 && i
.tm
.opcode_modifier
.vex3sources
);
4692 /* Add the implicit xmm0 for instructions with VEX prefix
4694 for (j
= i
.operands
; j
> 0; j
--)
4696 i
.op
[j
] = i
.op
[j
- 1];
4697 i
.types
[j
] = i
.types
[j
- 1];
4698 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4701 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4702 i
.types
[0] = regxmm
;
4703 i
.tm
.operand_types
[0] = regxmm
;
4706 i
.reg_operands
+= 2;
4711 i
.op
[dup
] = i
.op
[dest
];
4712 i
.types
[dup
] = i
.types
[dest
];
4713 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4722 i
.op
[dup
] = i
.op
[dest
];
4723 i
.types
[dup
] = i
.types
[dest
];
4724 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4727 if (i
.tm
.opcode_modifier
.immext
)
4730 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4734 /* The first operand is implicit and must be xmm0/ymm0. */
4735 gas_assert (i
.reg_operands
4736 && (operand_type_equal (&i
.types
[0], ®xmm
)
4737 || operand_type_equal (&i
.types
[0], ®ymm
)));
4738 if (i
.op
[0].regs
->reg_num
!= 0)
4739 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4741 for (j
= 1; j
< i
.operands
; j
++)
4743 i
.op
[j
- 1] = i
.op
[j
];
4744 i
.types
[j
- 1] = i
.types
[j
];
4746 /* We need to adjust fields in i.tm since they are used by
4747 build_modrm_byte. */
4748 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4755 else if (i
.tm
.opcode_modifier
.regkludge
)
4757 /* The imul $imm, %reg instruction is converted into
4758 imul $imm, %reg, %reg, and the clr %reg instruction
4759 is converted into xor %reg, %reg. */
4761 unsigned int first_reg_op
;
4763 if (operand_type_check (i
.types
[0], reg
))
4767 /* Pretend we saw the extra register operand. */
4768 gas_assert (i
.reg_operands
== 1
4769 && i
.op
[first_reg_op
+ 1].regs
== 0);
4770 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4771 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4776 if (i
.tm
.opcode_modifier
.shortform
)
4778 if (i
.types
[0].bitfield
.sreg2
4779 || i
.types
[0].bitfield
.sreg3
)
4781 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4782 && i
.op
[0].regs
->reg_num
== 1)
4784 as_bad (_("you can't `pop %scs'"), register_prefix
);
4787 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4788 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4793 /* The register or float register operand is in operand
4797 if (i
.types
[0].bitfield
.floatreg
4798 || operand_type_check (i
.types
[0], reg
))
4802 /* Register goes in low 3 bits of opcode. */
4803 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4804 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4806 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4808 /* Warn about some common errors, but press on regardless.
4809 The first case can be generated by gcc (<= 2.8.1). */
4810 if (i
.operands
== 2)
4812 /* Reversed arguments on faddp, fsubp, etc. */
4813 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4814 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4815 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4819 /* Extraneous `l' suffix on fp insn. */
4820 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4821 register_prefix
, i
.op
[0].regs
->reg_name
);
4826 else if (i
.tm
.opcode_modifier
.modrm
)
4828 /* The opcode is completed (modulo i.tm.extension_opcode which
4829 must be put into the modrm byte). Now, we make the modrm and
4830 index base bytes based on all the info we've collected. */
4832 default_seg
= build_modrm_byte ();
4834 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4838 else if (i
.tm
.opcode_modifier
.isstring
)
4840 /* For the string instructions that allow a segment override
4841 on one of their operands, the default segment is ds. */
4845 if (i
.tm
.base_opcode
== 0x8d /* lea */
4848 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4850 /* If a segment was explicitly specified, and the specified segment
4851 is not the default, use an opcode prefix to select it. If we
4852 never figured out what the default segment is, then default_seg
4853 will be zero at this point, and the specified segment prefix will
4855 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4857 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4863 static const seg_entry
*
4864 build_modrm_byte (void)
4866 const seg_entry
*default_seg
= 0;
4867 unsigned int source
, dest
;
4870 /* The first operand of instructions with VEX prefix and 3 sources
4871 must be VEX_Imm4. */
4872 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4875 unsigned int nds
, reg
;
4878 if (i
.tm
.opcode_modifier
.veximmext
4879 && i
.tm
.opcode_modifier
.immext
)
4881 dest
= i
.operands
- 2;
4882 gas_assert (dest
== 3);
4885 dest
= i
.operands
- 1;
4888 /* This instruction must have 4 register operands
4889 or 3 register operands plus 1 memory operand.
4890 It must have VexNDS and VexImmExt. */
4891 gas_assert ((i
.reg_operands
== 4
4892 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4893 && i
.tm
.opcode_modifier
.vexnds
4894 && i
.tm
.opcode_modifier
.veximmext
4895 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4896 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4898 /* Generate an 8bit immediate operand to encode the register
4900 exp
= &im_expressions
[i
.imm_operands
++];
4901 i
.op
[i
.operands
].imms
= exp
;
4902 i
.types
[i
.operands
] = imm8
;
4904 /* If VexW1 is set, the first operand is the source and
4905 the second operand is encoded in the immediate operand. */
4906 if (i
.tm
.opcode_modifier
.vexw1
)
4916 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4917 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4919 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4920 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4922 exp
->X_op
= O_constant
;
4924 = ((i
.op
[reg
].regs
->reg_num
4925 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4926 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4931 /* i.reg_operands MUST be the number of real register operands;
4932 implicit registers do not count. If there are 3 register
4933 operands, it must be a instruction with VexNDS. For a
4934 instruction with VexNDD, the destination register is encoded
4935 in VEX prefix. If there are 4 register operands, it must be
4936 a instruction with VEX prefix and 3 sources. */
4937 if (i
.mem_operands
== 0
4938 && ((i
.reg_operands
== 2
4939 && !i
.tm
.opcode_modifier
.vexndd
)
4940 || (i
.reg_operands
== 3
4941 && i
.tm
.opcode_modifier
.vexnds
)
4942 || (i
.reg_operands
== 4 && vex_3_sources
)))
4950 /* When there are 3 operands, one of them may be immediate,
4951 which may be the first or the last operand. Otherwise,
4952 the first operand must be shift count register (cl) or it
4953 is an instruction with VexNDS. */
4954 gas_assert (i
.imm_operands
== 1
4955 || (i
.imm_operands
== 0
4956 && (i
.tm
.opcode_modifier
.vexnds
4957 || i
.types
[0].bitfield
.shiftcount
)));
4958 if (operand_type_check (i
.types
[0], imm
)
4959 || i
.types
[0].bitfield
.shiftcount
)
4965 /* When there are 4 operands, the first two must be 8bit
4966 immediate operands. The source operand will be the 3rd
4969 For instructions with VexNDS, if the first operand
4970 an imm8, the source operand is the 2nd one. If the last
4971 operand is imm8, the source operand is the first one. */
4972 gas_assert ((i
.imm_operands
== 2
4973 && i
.types
[0].bitfield
.imm8
4974 && i
.types
[1].bitfield
.imm8
)
4975 || (i
.tm
.opcode_modifier
.vexnds
4976 && i
.imm_operands
== 1
4977 && (i
.types
[0].bitfield
.imm8
4978 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4979 if (i
.tm
.opcode_modifier
.vexnds
)
4981 if (i
.types
[0].bitfield
.imm8
)
4999 if (i
.tm
.opcode_modifier
.vexnds
)
5001 /* For instructions with VexNDS, the register-only
5002 source operand must be XMM or YMM register. It is
5003 encoded in VEX prefix. We need to clear RegMem bit
5004 before calling operand_type_equal. */
5005 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5006 op
.bitfield
.regmem
= 0;
5007 if ((dest
+ 1) >= i
.operands
5008 || (!operand_type_equal (&op
, ®xmm
)
5009 && !operand_type_equal (&op
, ®ymm
)))
5011 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5017 /* One of the register operands will be encoded in the i.tm.reg
5018 field, the other in the combined i.tm.mode and i.tm.regmem
5019 fields. If no form of this instruction supports a memory
5020 destination operand, then we assume the source operand may
5021 sometimes be a memory operand and so we need to store the
5022 destination in the i.rm.reg field. */
5023 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5024 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5026 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5027 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5028 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5030 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5035 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5036 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5037 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5039 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5042 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5044 if (!i
.types
[0].bitfield
.control
5045 && !i
.types
[1].bitfield
.control
)
5047 i
.rex
&= ~(REX_R
| REX_B
);
5048 add_prefix (LOCK_PREFIX_OPCODE
);
5052 { /* If it's not 2 reg operands... */
5057 unsigned int fake_zero_displacement
= 0;
5060 for (op
= 0; op
< i
.operands
; op
++)
5061 if (operand_type_check (i
.types
[op
], anymem
))
5063 gas_assert (op
< i
.operands
);
5067 if (i
.base_reg
== 0)
5070 if (!i
.disp_operands
)
5071 fake_zero_displacement
= 1;
5072 if (i
.index_reg
== 0)
5074 /* Operand is just <disp> */
5075 if (flag_code
== CODE_64BIT
)
5077 /* 64bit mode overwrites the 32bit absolute
5078 addressing by RIP relative addressing and
5079 absolute addressing is encoded by one of the
5080 redundant SIB forms. */
5081 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5082 i
.sib
.base
= NO_BASE_REGISTER
;
5083 i
.sib
.index
= NO_INDEX_REGISTER
;
5084 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5085 ? disp32s
: disp32
);
5087 else if ((flag_code
== CODE_16BIT
)
5088 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5090 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5091 i
.types
[op
] = disp16
;
5095 i
.rm
.regmem
= NO_BASE_REGISTER
;
5096 i
.types
[op
] = disp32
;
5099 else /* !i.base_reg && i.index_reg */
5101 if (i
.index_reg
->reg_num
== RegEiz
5102 || i
.index_reg
->reg_num
== RegRiz
)
5103 i
.sib
.index
= NO_INDEX_REGISTER
;
5105 i
.sib
.index
= i
.index_reg
->reg_num
;
5106 i
.sib
.base
= NO_BASE_REGISTER
;
5107 i
.sib
.scale
= i
.log2_scale_factor
;
5108 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5109 i
.types
[op
].bitfield
.disp8
= 0;
5110 i
.types
[op
].bitfield
.disp16
= 0;
5111 i
.types
[op
].bitfield
.disp64
= 0;
5112 if (flag_code
!= CODE_64BIT
)
5114 /* Must be 32 bit */
5115 i
.types
[op
].bitfield
.disp32
= 1;
5116 i
.types
[op
].bitfield
.disp32s
= 0;
5120 i
.types
[op
].bitfield
.disp32
= 0;
5121 i
.types
[op
].bitfield
.disp32s
= 1;
5123 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5127 /* RIP addressing for 64bit mode. */
5128 else if (i
.base_reg
->reg_num
== RegRip
||
5129 i
.base_reg
->reg_num
== RegEip
)
5131 i
.rm
.regmem
= NO_BASE_REGISTER
;
5132 i
.types
[op
].bitfield
.disp8
= 0;
5133 i
.types
[op
].bitfield
.disp16
= 0;
5134 i
.types
[op
].bitfield
.disp32
= 0;
5135 i
.types
[op
].bitfield
.disp32s
= 1;
5136 i
.types
[op
].bitfield
.disp64
= 0;
5137 i
.flags
[op
] |= Operand_PCrel
;
5138 if (! i
.disp_operands
)
5139 fake_zero_displacement
= 1;
5141 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5143 switch (i
.base_reg
->reg_num
)
5146 if (i
.index_reg
== 0)
5148 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5149 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5153 if (i
.index_reg
== 0)
5156 if (operand_type_check (i
.types
[op
], disp
) == 0)
5158 /* fake (%bp) into 0(%bp) */
5159 i
.types
[op
].bitfield
.disp8
= 1;
5160 fake_zero_displacement
= 1;
5163 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5164 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5166 default: /* (%si) -> 4 or (%di) -> 5 */
5167 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5169 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5171 else /* i.base_reg and 32/64 bit mode */
5173 if (flag_code
== CODE_64BIT
5174 && operand_type_check (i
.types
[op
], disp
))
5176 i386_operand_type temp
;
5177 operand_type_set (&temp
, 0);
5178 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5180 if (i
.prefix
[ADDR_PREFIX
] == 0)
5181 i
.types
[op
].bitfield
.disp32s
= 1;
5183 i
.types
[op
].bitfield
.disp32
= 1;
5186 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5187 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5189 i
.sib
.base
= i
.base_reg
->reg_num
;
5190 /* x86-64 ignores REX prefix bit here to avoid decoder
5192 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5195 if (i
.disp_operands
== 0)
5197 fake_zero_displacement
= 1;
5198 i
.types
[op
].bitfield
.disp8
= 1;
5201 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5205 i
.sib
.scale
= i
.log2_scale_factor
;
5206 if (i
.index_reg
== 0)
5208 /* <disp>(%esp) becomes two byte modrm with no index
5209 register. We've already stored the code for esp
5210 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5211 Any base register besides %esp will not use the
5212 extra modrm byte. */
5213 i
.sib
.index
= NO_INDEX_REGISTER
;
5217 if (i
.index_reg
->reg_num
== RegEiz
5218 || i
.index_reg
->reg_num
== RegRiz
)
5219 i
.sib
.index
= NO_INDEX_REGISTER
;
5221 i
.sib
.index
= i
.index_reg
->reg_num
;
5222 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5223 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5228 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5229 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5232 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5235 if (fake_zero_displacement
)
5237 /* Fakes a zero displacement assuming that i.types[op]
5238 holds the correct displacement size. */
5241 gas_assert (i
.op
[op
].disps
== 0);
5242 exp
= &disp_expressions
[i
.disp_operands
++];
5243 i
.op
[op
].disps
= exp
;
5244 exp
->X_op
= O_constant
;
5245 exp
->X_add_number
= 0;
5246 exp
->X_add_symbol
= (symbolS
*) 0;
5247 exp
->X_op_symbol
= (symbolS
*) 0;
5255 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5256 (if any) based on i.tm.extension_opcode. Again, we must be
5257 careful to make sure that segment/control/debug/test/MMX
5258 registers are coded into the i.rm.reg field. */
5262 unsigned int vex_reg
= ~0;
5264 for (op
= 0; op
< i
.operands
; op
++)
5265 if (i
.types
[op
].bitfield
.reg8
5266 || i
.types
[op
].bitfield
.reg16
5267 || i
.types
[op
].bitfield
.reg32
5268 || i
.types
[op
].bitfield
.reg64
5269 || i
.types
[op
].bitfield
.regmmx
5270 || i
.types
[op
].bitfield
.regxmm
5271 || i
.types
[op
].bitfield
.regymm
5272 || i
.types
[op
].bitfield
.sreg2
5273 || i
.types
[op
].bitfield
.sreg3
5274 || i
.types
[op
].bitfield
.control
5275 || i
.types
[op
].bitfield
.debug
5276 || i
.types
[op
].bitfield
.test
)
5281 else if (i
.tm
.opcode_modifier
.vexnds
)
5283 /* For instructions with VexNDS, the register-only
5284 source operand is encoded in VEX prefix. */
5285 gas_assert (mem
!= (unsigned int) ~0);
5290 gas_assert (op
< i
.operands
);
5295 gas_assert (vex_reg
< i
.operands
);
5298 else if (i
.tm
.opcode_modifier
.vexndd
)
5300 /* For instructions with VexNDD, there should be
5301 no memory operand and the register destination
5302 is encoded in VEX prefix. */
5303 gas_assert (i
.mem_operands
== 0
5304 && (op
+ 2) == i
.operands
);
5308 gas_assert (op
< i
.operands
);
5310 if (vex_reg
!= (unsigned int) ~0)
5312 gas_assert (i
.reg_operands
== 2);
5314 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5316 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5319 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5322 /* If there is an extension opcode to put here, the
5323 register number must be put into the regmem field. */
5324 if (i
.tm
.extension_opcode
!= None
)
5326 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5327 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5332 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5333 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5337 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5338 must set it to 3 to indicate this is a register operand
5339 in the regmem field. */
5340 if (!i
.mem_operands
)
5344 /* Fill in i.rm.reg field with extension opcode (if any). */
5345 if (i
.tm
.extension_opcode
!= None
)
5346 i
.rm
.reg
= i
.tm
.extension_opcode
;
5352 output_branch (void)
5357 relax_substateT subtype
;
5362 if (flag_code
== CODE_16BIT
)
5366 if (i
.prefix
[DATA_PREFIX
] != 0)
5372 /* Pentium4 branch hints. */
5373 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5374 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5379 if (i
.prefix
[REX_PREFIX
] != 0)
5385 if (i
.prefixes
!= 0 && !intel_syntax
)
5386 as_warn (_("skipping prefixes on this instruction"));
5388 /* It's always a symbol; End frag & setup for relax.
5389 Make sure there is enough room in this frag for the largest
5390 instruction we may generate in md_convert_frag. This is 2
5391 bytes for the opcode and room for the prefix and largest
5393 frag_grow (prefix
+ 2 + 4);
5394 /* Prefix and 1 opcode byte go in fr_fix. */
5395 p
= frag_more (prefix
+ 1);
5396 if (i
.prefix
[DATA_PREFIX
] != 0)
5397 *p
++ = DATA_PREFIX_OPCODE
;
5398 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5399 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5400 *p
++ = i
.prefix
[SEG_PREFIX
];
5401 if (i
.prefix
[REX_PREFIX
] != 0)
5402 *p
++ = i
.prefix
[REX_PREFIX
];
5403 *p
= i
.tm
.base_opcode
;
5405 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5406 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5407 else if (cpu_arch_flags
.bitfield
.cpui386
)
5408 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5410 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5413 sym
= i
.op
[0].disps
->X_add_symbol
;
5414 off
= i
.op
[0].disps
->X_add_number
;
5416 if (i
.op
[0].disps
->X_op
!= O_constant
5417 && i
.op
[0].disps
->X_op
!= O_symbol
)
5419 /* Handle complex expressions. */
5420 sym
= make_expr_symbol (i
.op
[0].disps
);
5424 /* 1 possible extra opcode + 4 byte displacement go in var part.
5425 Pass reloc in fr_var. */
5426 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5436 if (i
.tm
.opcode_modifier
.jumpbyte
)
5438 /* This is a loop or jecxz type instruction. */
5440 if (i
.prefix
[ADDR_PREFIX
] != 0)
5442 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5445 /* Pentium4 branch hints. */
5446 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5447 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5449 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5458 if (flag_code
== CODE_16BIT
)
5461 if (i
.prefix
[DATA_PREFIX
] != 0)
5463 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5473 if (i
.prefix
[REX_PREFIX
] != 0)
5475 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5479 if (i
.prefixes
!= 0 && !intel_syntax
)
5480 as_warn (_("skipping prefixes on this instruction"));
5482 p
= frag_more (1 + size
);
5483 *p
++ = i
.tm
.base_opcode
;
5485 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5486 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5488 /* All jumps handled here are signed, but don't use a signed limit
5489 check for 32 and 16 bit jumps as we want to allow wrap around at
5490 4G and 64k respectively. */
5492 fixP
->fx_signed
= 1;
5496 output_interseg_jump (void)
5504 if (flag_code
== CODE_16BIT
)
5508 if (i
.prefix
[DATA_PREFIX
] != 0)
5514 if (i
.prefix
[REX_PREFIX
] != 0)
5524 if (i
.prefixes
!= 0 && !intel_syntax
)
5525 as_warn (_("skipping prefixes on this instruction"));
5527 /* 1 opcode; 2 segment; offset */
5528 p
= frag_more (prefix
+ 1 + 2 + size
);
5530 if (i
.prefix
[DATA_PREFIX
] != 0)
5531 *p
++ = DATA_PREFIX_OPCODE
;
5533 if (i
.prefix
[REX_PREFIX
] != 0)
5534 *p
++ = i
.prefix
[REX_PREFIX
];
5536 *p
++ = i
.tm
.base_opcode
;
5537 if (i
.op
[1].imms
->X_op
== O_constant
)
5539 offsetT n
= i
.op
[1].imms
->X_add_number
;
5542 && !fits_in_unsigned_word (n
)
5543 && !fits_in_signed_word (n
))
5545 as_bad (_("16-bit jump out of range"));
5548 md_number_to_chars (p
, n
, size
);
5551 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5552 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5553 if (i
.op
[0].imms
->X_op
!= O_constant
)
5554 as_bad (_("can't handle non absolute segment in `%s'"),
5556 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5562 fragS
*insn_start_frag
;
5563 offsetT insn_start_off
;
5565 /* Tie dwarf2 debug info to the address at the start of the insn.
5566 We can't do this after the insn has been output as the current
5567 frag may have been closed off. eg. by frag_var. */
5568 dwarf2_emit_insn (0);
5570 insn_start_frag
= frag_now
;
5571 insn_start_off
= frag_now_fix ();
5574 if (i
.tm
.opcode_modifier
.jump
)
5576 else if (i
.tm
.opcode_modifier
.jumpbyte
5577 || i
.tm
.opcode_modifier
.jumpdword
)
5579 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5580 output_interseg_jump ();
5583 /* Output normal instructions here. */
5587 unsigned int prefix
;
5589 /* Since the VEX prefix contains the implicit prefix, we don't
5590 need the explicit prefix. */
5591 if (!i
.tm
.opcode_modifier
.vex
)
5593 switch (i
.tm
.opcode_length
)
5596 if (i
.tm
.base_opcode
& 0xff000000)
5598 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5603 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5605 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5606 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5609 if (prefix
!= REPE_PREFIX_OPCODE
5610 || (i
.prefix
[LOCKREP_PREFIX
]
5611 != REPE_PREFIX_OPCODE
))
5612 add_prefix (prefix
);
5615 add_prefix (prefix
);
5624 /* The prefix bytes. */
5625 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5627 FRAG_APPEND_1_CHAR (*q
);
5630 if (i
.tm
.opcode_modifier
.vex
)
5632 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5637 /* REX byte is encoded in VEX prefix. */
5641 FRAG_APPEND_1_CHAR (*q
);
5644 /* There should be no other prefixes for instructions
5649 /* Now the VEX prefix. */
5650 p
= frag_more (i
.vex
.length
);
5651 for (j
= 0; j
< i
.vex
.length
; j
++)
5652 p
[j
] = i
.vex
.bytes
[j
];
5655 /* Now the opcode; be careful about word order here! */
5656 if (i
.tm
.opcode_length
== 1)
5658 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5662 switch (i
.tm
.opcode_length
)
5666 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5676 /* Put out high byte first: can't use md_number_to_chars! */
5677 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5678 *p
= i
.tm
.base_opcode
& 0xff;
5681 /* Now the modrm byte and sib byte (if present). */
5682 if (i
.tm
.opcode_modifier
.modrm
)
5684 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5687 /* If i.rm.regmem == ESP (4)
5688 && i.rm.mode != (Register mode)
5690 ==> need second modrm byte. */
5691 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5693 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5694 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5696 | i
.sib
.scale
<< 6));
5699 if (i
.disp_operands
)
5700 output_disp (insn_start_frag
, insn_start_off
);
5703 output_imm (insn_start_frag
, insn_start_off
);
5709 pi ("" /*line*/, &i
);
5711 #endif /* DEBUG386 */
5714 /* Return the size of the displacement operand N. */
5717 disp_size (unsigned int n
)
5720 if (i
.types
[n
].bitfield
.disp64
)
5722 else if (i
.types
[n
].bitfield
.disp8
)
5724 else if (i
.types
[n
].bitfield
.disp16
)
5729 /* Return the size of the immediate operand N. */
5732 imm_size (unsigned int n
)
5735 if (i
.types
[n
].bitfield
.imm64
)
5737 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5739 else if (i
.types
[n
].bitfield
.imm16
)
5745 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5750 for (n
= 0; n
< i
.operands
; n
++)
5752 if (operand_type_check (i
.types
[n
], disp
))
5754 if (i
.op
[n
].disps
->X_op
== O_constant
)
5756 int size
= disp_size (n
);
5759 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5761 p
= frag_more (size
);
5762 md_number_to_chars (p
, val
, size
);
5766 enum bfd_reloc_code_real reloc_type
;
5767 int size
= disp_size (n
);
5768 int sign
= i
.types
[n
].bitfield
.disp32s
;
5769 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5771 /* We can't have 8 bit displacement here. */
5772 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5774 /* The PC relative address is computed relative
5775 to the instruction boundary, so in case immediate
5776 fields follows, we need to adjust the value. */
5777 if (pcrel
&& i
.imm_operands
)
5782 for (n1
= 0; n1
< i
.operands
; n1
++)
5783 if (operand_type_check (i
.types
[n1
], imm
))
5785 /* Only one immediate is allowed for PC
5786 relative address. */
5787 gas_assert (sz
== 0);
5789 i
.op
[n
].disps
->X_add_number
-= sz
;
5791 /* We should find the immediate. */
5792 gas_assert (sz
!= 0);
5795 p
= frag_more (size
);
5796 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5798 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5799 && (((reloc_type
== BFD_RELOC_32
5800 || reloc_type
== BFD_RELOC_X86_64_32S
5801 || (reloc_type
== BFD_RELOC_64
5803 && (i
.op
[n
].disps
->X_op
== O_symbol
5804 || (i
.op
[n
].disps
->X_op
== O_add
5805 && ((symbol_get_value_expression
5806 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5808 || reloc_type
== BFD_RELOC_32_PCREL
))
5812 if (insn_start_frag
== frag_now
)
5813 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5818 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5819 for (fr
= insn_start_frag
->fr_next
;
5820 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5822 add
+= p
- frag_now
->fr_literal
;
5827 reloc_type
= BFD_RELOC_386_GOTPC
;
5828 i
.op
[n
].imms
->X_add_number
+= add
;
5830 else if (reloc_type
== BFD_RELOC_64
)
5831 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5833 /* Don't do the adjustment for x86-64, as there
5834 the pcrel addressing is relative to the _next_
5835 insn, and that is taken care of in other code. */
5836 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5838 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5839 i
.op
[n
].disps
, pcrel
, reloc_type
);
5846 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5851 for (n
= 0; n
< i
.operands
; n
++)
5853 if (operand_type_check (i
.types
[n
], imm
))
5855 if (i
.op
[n
].imms
->X_op
== O_constant
)
5857 int size
= imm_size (n
);
5860 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5862 p
= frag_more (size
);
5863 md_number_to_chars (p
, val
, size
);
5867 /* Not absolute_section.
5868 Need a 32-bit fixup (don't support 8bit
5869 non-absolute imms). Try to support other
5871 enum bfd_reloc_code_real reloc_type
;
5872 int size
= imm_size (n
);
5875 if (i
.types
[n
].bitfield
.imm32s
5876 && (i
.suffix
== QWORD_MNEM_SUFFIX
5877 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5882 p
= frag_more (size
);
5883 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5885 /* This is tough to explain. We end up with this one if we
5886 * have operands that look like
5887 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5888 * obtain the absolute address of the GOT, and it is strongly
5889 * preferable from a performance point of view to avoid using
5890 * a runtime relocation for this. The actual sequence of
5891 * instructions often look something like:
5896 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5898 * The call and pop essentially return the absolute address
5899 * of the label .L66 and store it in %ebx. The linker itself
5900 * will ultimately change the first operand of the addl so
5901 * that %ebx points to the GOT, but to keep things simple, the
5902 * .o file must have this operand set so that it generates not
5903 * the absolute address of .L66, but the absolute address of
5904 * itself. This allows the linker itself simply treat a GOTPC
5905 * relocation as asking for a pcrel offset to the GOT to be
5906 * added in, and the addend of the relocation is stored in the
5907 * operand field for the instruction itself.
5909 * Our job here is to fix the operand so that it would add
5910 * the correct offset so that %ebx would point to itself. The
5911 * thing that is tricky is that .-.L66 will point to the
5912 * beginning of the instruction, so we need to further modify
5913 * the operand so that it will point to itself. There are
5914 * other cases where you have something like:
5916 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5918 * and here no correction would be required. Internally in
5919 * the assembler we treat operands of this form as not being
5920 * pcrel since the '.' is explicitly mentioned, and I wonder
5921 * whether it would simplify matters to do it this way. Who
5922 * knows. In earlier versions of the PIC patches, the
5923 * pcrel_adjust field was used to store the correction, but
5924 * since the expression is not pcrel, I felt it would be
5925 * confusing to do it this way. */
5927 if ((reloc_type
== BFD_RELOC_32
5928 || reloc_type
== BFD_RELOC_X86_64_32S
5929 || reloc_type
== BFD_RELOC_64
)
5931 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5932 && (i
.op
[n
].imms
->X_op
== O_symbol
5933 || (i
.op
[n
].imms
->X_op
== O_add
5934 && ((symbol_get_value_expression
5935 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5940 if (insn_start_frag
== frag_now
)
5941 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5946 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5947 for (fr
= insn_start_frag
->fr_next
;
5948 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5950 add
+= p
- frag_now
->fr_literal
;
5954 reloc_type
= BFD_RELOC_386_GOTPC
;
5956 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5958 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5959 i
.op
[n
].imms
->X_add_number
+= add
;
5961 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5962 i
.op
[n
].imms
, 0, reloc_type
);
5968 /* x86_cons_fix_new is called via the expression parsing code when a
5969 reloc is needed. We use this hook to get the correct .got reloc. */
5970 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5971 static int cons_sign
= -1;
5974 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5977 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5979 got_reloc
= NO_RELOC
;
5982 if (exp
->X_op
== O_secrel
)
5984 exp
->X_op
= O_symbol
;
5985 r
= BFD_RELOC_32_SECREL
;
5989 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5992 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5993 # define lex_got(reloc, adjust, types) NULL
5995 /* Parse operands of the form
5996 <symbol>@GOTOFF+<nnn>
5997 and similar .plt or .got references.
5999 If we find one, set up the correct relocation in RELOC and copy the
6000 input string, minus the `@GOTOFF' into a malloc'd buffer for
6001 parsing by the calling routine. Return this buffer, and if ADJUST
6002 is non-null set it to the length of the string we removed from the
6003 input line. Otherwise return NULL. */
6005 lex_got (enum bfd_reloc_code_real
*reloc
,
6007 i386_operand_type
*types
)
6009 /* Some of the relocations depend on the size of what field is to
6010 be relocated. But in our callers i386_immediate and i386_displacement
6011 we don't yet know the operand size (this will be set by insn
6012 matching). Hence we record the word32 relocation here,
6013 and adjust the reloc according to the real size in reloc(). */
6014 static const struct {
6016 const enum bfd_reloc_code_real rel
[2];
6017 const i386_operand_type types64
;
6019 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6020 BFD_RELOC_X86_64_PLTOFF64
},
6021 OPERAND_TYPE_IMM64
},
6022 { "PLT", { BFD_RELOC_386_PLT32
,
6023 BFD_RELOC_X86_64_PLT32
},
6024 OPERAND_TYPE_IMM32_32S_DISP32
},
6025 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6026 BFD_RELOC_X86_64_GOTPLT64
},
6027 OPERAND_TYPE_IMM64_DISP64
},
6028 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6029 BFD_RELOC_X86_64_GOTOFF64
},
6030 OPERAND_TYPE_IMM64_DISP64
},
6031 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6032 BFD_RELOC_X86_64_GOTPCREL
},
6033 OPERAND_TYPE_IMM32_32S_DISP32
},
6034 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6035 BFD_RELOC_X86_64_TLSGD
},
6036 OPERAND_TYPE_IMM32_32S_DISP32
},
6037 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6038 _dummy_first_bfd_reloc_code_real
},
6039 OPERAND_TYPE_NONE
},
6040 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6041 BFD_RELOC_X86_64_TLSLD
},
6042 OPERAND_TYPE_IMM32_32S_DISP32
},
6043 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6044 BFD_RELOC_X86_64_GOTTPOFF
},
6045 OPERAND_TYPE_IMM32_32S_DISP32
},
6046 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6047 BFD_RELOC_X86_64_TPOFF32
},
6048 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6049 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6050 _dummy_first_bfd_reloc_code_real
},
6051 OPERAND_TYPE_NONE
},
6052 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6053 BFD_RELOC_X86_64_DTPOFF32
},
6055 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6056 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6057 _dummy_first_bfd_reloc_code_real
},
6058 OPERAND_TYPE_NONE
},
6059 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6060 _dummy_first_bfd_reloc_code_real
},
6061 OPERAND_TYPE_NONE
},
6062 { "GOT", { BFD_RELOC_386_GOT32
,
6063 BFD_RELOC_X86_64_GOT32
},
6064 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6065 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6066 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6067 OPERAND_TYPE_IMM32_32S_DISP32
},
6068 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6069 BFD_RELOC_X86_64_TLSDESC_CALL
},
6070 OPERAND_TYPE_IMM32_32S_DISP32
},
6078 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6079 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6082 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6086 len
= strlen (gotrel
[j
].str
);
6087 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6089 if (gotrel
[j
].rel
[object_64bit
] != 0)
6092 char *tmpbuf
, *past_reloc
;
6094 *reloc
= gotrel
[j
].rel
[object_64bit
];
6100 if (flag_code
!= CODE_64BIT
)
6102 types
->bitfield
.imm32
= 1;
6103 types
->bitfield
.disp32
= 1;
6106 *types
= gotrel
[j
].types64
;
6109 if (GOT_symbol
== NULL
)
6110 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6112 /* The length of the first part of our input line. */
6113 first
= cp
- input_line_pointer
;
6115 /* The second part goes from after the reloc token until
6116 (and including) an end_of_line char or comma. */
6117 past_reloc
= cp
+ 1 + len
;
6119 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6121 second
= cp
+ 1 - past_reloc
;
6123 /* Allocate and copy string. The trailing NUL shouldn't
6124 be necessary, but be safe. */
6125 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6126 memcpy (tmpbuf
, input_line_pointer
, first
);
6127 if (second
!= 0 && *past_reloc
!= ' ')
6128 /* Replace the relocation token with ' ', so that
6129 errors like foo@GOTOFF1 will be detected. */
6130 tmpbuf
[first
++] = ' ';
6131 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6132 tmpbuf
[first
+ second
] = '\0';
6136 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6137 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6142 /* Might be a symbol version string. Don't as_bad here. */
6147 x86_cons (expressionS
*exp
, int size
)
6149 intel_syntax
= -intel_syntax
;
6151 if (size
== 4 || (object_64bit
&& size
== 8))
6153 /* Handle @GOTOFF and the like in an expression. */
6155 char *gotfree_input_line
;
6158 save
= input_line_pointer
;
6159 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6160 if (gotfree_input_line
)
6161 input_line_pointer
= gotfree_input_line
;
6165 if (gotfree_input_line
)
6167 /* expression () has merrily parsed up to the end of line,
6168 or a comma - in the wrong buffer. Transfer how far
6169 input_line_pointer has moved to the right buffer. */
6170 input_line_pointer
= (save
6171 + (input_line_pointer
- gotfree_input_line
)
6173 free (gotfree_input_line
);
6174 if (exp
->X_op
== O_constant
6175 || exp
->X_op
== O_absent
6176 || exp
->X_op
== O_illegal
6177 || exp
->X_op
== O_register
6178 || exp
->X_op
== O_big
)
6180 char c
= *input_line_pointer
;
6181 *input_line_pointer
= 0;
6182 as_bad (_("missing or invalid expression `%s'"), save
);
6183 *input_line_pointer
= c
;
6190 intel_syntax
= -intel_syntax
;
6193 i386_intel_simplify (exp
);
6198 signed_cons (int size
)
6200 if (flag_code
== CODE_64BIT
)
6208 pe_directive_secrel (dummy
)
6209 int dummy ATTRIBUTE_UNUSED
;
6216 if (exp
.X_op
== O_symbol
)
6217 exp
.X_op
= O_secrel
;
6219 emit_expr (&exp
, 4);
6221 while (*input_line_pointer
++ == ',');
6223 input_line_pointer
--;
6224 demand_empty_rest_of_line ();
6229 i386_immediate (char *imm_start
)
6231 char *save_input_line_pointer
;
6232 char *gotfree_input_line
;
6235 i386_operand_type types
;
6237 operand_type_set (&types
, ~0);
6239 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6241 as_bad (_("at most %d immediate operands are allowed"),
6242 MAX_IMMEDIATE_OPERANDS
);
6246 exp
= &im_expressions
[i
.imm_operands
++];
6247 i
.op
[this_operand
].imms
= exp
;
6249 if (is_space_char (*imm_start
))
6252 save_input_line_pointer
= input_line_pointer
;
6253 input_line_pointer
= imm_start
;
6255 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6256 if (gotfree_input_line
)
6257 input_line_pointer
= gotfree_input_line
;
6259 exp_seg
= expression (exp
);
6262 if (*input_line_pointer
)
6263 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6265 input_line_pointer
= save_input_line_pointer
;
6266 if (gotfree_input_line
)
6268 free (gotfree_input_line
);
6270 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6271 exp
->X_op
= O_illegal
;
6274 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6278 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6279 i386_operand_type types
, const char *imm_start
)
6281 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6284 as_bad (_("missing or invalid immediate expression `%s'"),
6288 else if (exp
->X_op
== O_constant
)
6290 /* Size it properly later. */
6291 i
.types
[this_operand
].bitfield
.imm64
= 1;
6292 /* If BFD64, sign extend val. */
6293 if (!use_rela_relocations
6294 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6296 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6298 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6299 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6300 && exp_seg
!= absolute_section
6301 && exp_seg
!= text_section
6302 && exp_seg
!= data_section
6303 && exp_seg
!= bss_section
6304 && exp_seg
!= undefined_section
6305 && !bfd_is_com_section (exp_seg
))
6307 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6311 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6314 as_bad (_("illegal immediate register operand %s"), imm_start
);
6319 /* This is an address. The size of the address will be
6320 determined later, depending on destination register,
6321 suffix, or the default for the section. */
6322 i
.types
[this_operand
].bitfield
.imm8
= 1;
6323 i
.types
[this_operand
].bitfield
.imm16
= 1;
6324 i
.types
[this_operand
].bitfield
.imm32
= 1;
6325 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6326 i
.types
[this_operand
].bitfield
.imm64
= 1;
6327 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6335 i386_scale (char *scale
)
6338 char *save
= input_line_pointer
;
6340 input_line_pointer
= scale
;
6341 val
= get_absolute_expression ();
6346 i
.log2_scale_factor
= 0;
6349 i
.log2_scale_factor
= 1;
6352 i
.log2_scale_factor
= 2;
6355 i
.log2_scale_factor
= 3;
6359 char sep
= *input_line_pointer
;
6361 *input_line_pointer
= '\0';
6362 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6364 *input_line_pointer
= sep
;
6365 input_line_pointer
= save
;
6369 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6371 as_warn (_("scale factor of %d without an index register"),
6372 1 << i
.log2_scale_factor
);
6373 i
.log2_scale_factor
= 0;
6375 scale
= input_line_pointer
;
6376 input_line_pointer
= save
;
6381 i386_displacement (char *disp_start
, char *disp_end
)
6385 char *save_input_line_pointer
;
6386 char *gotfree_input_line
;
6388 i386_operand_type bigdisp
, types
= anydisp
;
6391 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6393 as_bad (_("at most %d displacement operands are allowed"),
6394 MAX_MEMORY_OPERANDS
);
6398 operand_type_set (&bigdisp
, 0);
6399 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6400 || (!current_templates
->start
->opcode_modifier
.jump
6401 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6403 bigdisp
.bitfield
.disp32
= 1;
6404 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6405 if (flag_code
== CODE_64BIT
)
6409 bigdisp
.bitfield
.disp32s
= 1;
6410 bigdisp
.bitfield
.disp64
= 1;
6413 else if ((flag_code
== CODE_16BIT
) ^ override
)
6415 bigdisp
.bitfield
.disp32
= 0;
6416 bigdisp
.bitfield
.disp16
= 1;
6421 /* For PC-relative branches, the width of the displacement
6422 is dependent upon data size, not address size. */
6423 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6424 if (flag_code
== CODE_64BIT
)
6426 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6427 bigdisp
.bitfield
.disp16
= 1;
6430 bigdisp
.bitfield
.disp32
= 1;
6431 bigdisp
.bitfield
.disp32s
= 1;
6437 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6439 : LONG_MNEM_SUFFIX
));
6440 bigdisp
.bitfield
.disp32
= 1;
6441 if ((flag_code
== CODE_16BIT
) ^ override
)
6443 bigdisp
.bitfield
.disp32
= 0;
6444 bigdisp
.bitfield
.disp16
= 1;
6448 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6451 exp
= &disp_expressions
[i
.disp_operands
];
6452 i
.op
[this_operand
].disps
= exp
;
6454 save_input_line_pointer
= input_line_pointer
;
6455 input_line_pointer
= disp_start
;
6456 END_STRING_AND_SAVE (disp_end
);
6458 #ifndef GCC_ASM_O_HACK
6459 #define GCC_ASM_O_HACK 0
6462 END_STRING_AND_SAVE (disp_end
+ 1);
6463 if (i
.types
[this_operand
].bitfield
.baseIndex
6464 && displacement_string_end
[-1] == '+')
6466 /* This hack is to avoid a warning when using the "o"
6467 constraint within gcc asm statements.
6470 #define _set_tssldt_desc(n,addr,limit,type) \
6471 __asm__ __volatile__ ( \
6473 "movw %w1,2+%0\n\t" \
6475 "movb %b1,4+%0\n\t" \
6476 "movb %4,5+%0\n\t" \
6477 "movb $0,6+%0\n\t" \
6478 "movb %h1,7+%0\n\t" \
6480 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6482 This works great except that the output assembler ends
6483 up looking a bit weird if it turns out that there is
6484 no offset. You end up producing code that looks like:
6497 So here we provide the missing zero. */
6499 *displacement_string_end
= '0';
6502 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6503 if (gotfree_input_line
)
6504 input_line_pointer
= gotfree_input_line
;
6506 exp_seg
= expression (exp
);
6509 if (*input_line_pointer
)
6510 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6512 RESTORE_END_STRING (disp_end
+ 1);
6514 input_line_pointer
= save_input_line_pointer
;
6515 if (gotfree_input_line
)
6517 free (gotfree_input_line
);
6519 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6520 exp
->X_op
= O_illegal
;
6523 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6525 RESTORE_END_STRING (disp_end
);
6531 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6532 i386_operand_type types
, const char *disp_start
)
6534 i386_operand_type bigdisp
;
6537 /* We do this to make sure that the section symbol is in
6538 the symbol table. We will ultimately change the relocation
6539 to be relative to the beginning of the section. */
6540 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6541 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6542 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6544 if (exp
->X_op
!= O_symbol
)
6547 if (S_IS_LOCAL (exp
->X_add_symbol
)
6548 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6549 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6550 exp
->X_op
= O_subtract
;
6551 exp
->X_op_symbol
= GOT_symbol
;
6552 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6553 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6554 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6555 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6557 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6560 else if (exp
->X_op
== O_absent
6561 || exp
->X_op
== O_illegal
6562 || exp
->X_op
== O_big
)
6565 as_bad (_("missing or invalid displacement expression `%s'"),
6570 else if (flag_code
== CODE_64BIT
6571 && !i
.prefix
[ADDR_PREFIX
]
6572 && exp
->X_op
== O_constant
)
6574 /* Since displacement is signed extended to 64bit, don't allow
6575 disp32 and turn off disp32s if they are out of range. */
6576 i
.types
[this_operand
].bitfield
.disp32
= 0;
6577 if (!fits_in_signed_long (exp
->X_add_number
))
6579 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6580 if (i
.types
[this_operand
].bitfield
.baseindex
)
6582 as_bad (_("0x%lx out range of signed 32bit displacement"),
6583 (long) exp
->X_add_number
);
6589 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6590 else if (exp
->X_op
!= O_constant
6591 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6592 && exp_seg
!= absolute_section
6593 && exp_seg
!= text_section
6594 && exp_seg
!= data_section
6595 && exp_seg
!= bss_section
6596 && exp_seg
!= undefined_section
6597 && !bfd_is_com_section (exp_seg
))
6599 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6604 /* Check if this is a displacement only operand. */
6605 bigdisp
= i
.types
[this_operand
];
6606 bigdisp
.bitfield
.disp8
= 0;
6607 bigdisp
.bitfield
.disp16
= 0;
6608 bigdisp
.bitfield
.disp32
= 0;
6609 bigdisp
.bitfield
.disp32s
= 0;
6610 bigdisp
.bitfield
.disp64
= 0;
6611 if (operand_type_all_zero (&bigdisp
))
6612 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6618 /* Make sure the memory operand we've been dealt is valid.
6619 Return 1 on success, 0 on a failure. */
6622 i386_index_check (const char *operand_string
)
6625 const char *kind
= "base/index";
6626 #if INFER_ADDR_PREFIX
6632 if (current_templates
->start
->opcode_modifier
.isstring
6633 && !current_templates
->start
->opcode_modifier
.immext
6634 && (current_templates
->end
[-1].opcode_modifier
.isstring
6637 /* Memory operands of string insns are special in that they only allow
6638 a single register (rDI, rSI, or rBX) as their memory address. */
6639 unsigned int expected
;
6641 kind
= "string address";
6643 if (current_templates
->start
->opcode_modifier
.w
)
6645 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6647 if (!type
.bitfield
.baseindex
6648 || ((!i
.mem_operands
!= !intel_syntax
)
6649 && current_templates
->end
[-1].operand_types
[1]
6650 .bitfield
.baseindex
))
6651 type
= current_templates
->end
[-1].operand_types
[1];
6652 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6655 expected
= 3 /* rBX */;
6657 if (!i
.base_reg
|| i
.index_reg
6658 || operand_type_check (i
.types
[this_operand
], disp
))
6660 else if (!(flag_code
== CODE_64BIT
6661 ? i
.prefix
[ADDR_PREFIX
]
6662 ? i
.base_reg
->reg_type
.bitfield
.reg32
6663 : i
.base_reg
->reg_type
.bitfield
.reg64
6664 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6665 ? i
.base_reg
->reg_type
.bitfield
.reg32
6666 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6668 else if (i
.base_reg
->reg_num
!= expected
)
6675 for (j
= 0; j
< i386_regtab_size
; ++j
)
6676 if ((flag_code
== CODE_64BIT
6677 ? i
.prefix
[ADDR_PREFIX
]
6678 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6679 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6680 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6681 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6682 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6683 && i386_regtab
[j
].reg_num
== expected
)
6685 gas_assert (j
< i386_regtab_size
);
6686 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6688 intel_syntax
? '[' : '(',
6690 i386_regtab
[j
].reg_name
,
6691 intel_syntax
? ']' : ')');
6695 else if (flag_code
== CODE_64BIT
)
6698 && ((i
.prefix
[ADDR_PREFIX
] == 0
6699 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6700 || (i
.prefix
[ADDR_PREFIX
]
6701 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6703 || i
.base_reg
->reg_num
!=
6704 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6706 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6707 || (i
.prefix
[ADDR_PREFIX
] == 0
6708 && i
.index_reg
->reg_num
!= RegRiz
6709 && !i
.index_reg
->reg_type
.bitfield
.reg64
6711 || (i
.prefix
[ADDR_PREFIX
]
6712 && i
.index_reg
->reg_num
!= RegEiz
6713 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6718 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6722 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6723 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6725 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6726 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6728 && i
.base_reg
->reg_num
< 6
6729 && i
.index_reg
->reg_num
>= 6
6730 && i
.log2_scale_factor
== 0))))
6737 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6739 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6740 && i
.index_reg
->reg_num
!= RegEiz
)
6741 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6747 #if INFER_ADDR_PREFIX
6748 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6750 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6752 /* Change the size of any displacement too. At most one of
6753 Disp16 or Disp32 is set.
6754 FIXME. There doesn't seem to be any real need for separate
6755 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6756 Removing them would probably clean up the code quite a lot. */
6757 if (flag_code
!= CODE_64BIT
6758 && (i
.types
[this_operand
].bitfield
.disp16
6759 || i
.types
[this_operand
].bitfield
.disp32
))
6760 i
.types
[this_operand
]
6761 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6766 as_bad (_("`%s' is not a valid %s expression"),
6771 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6773 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6774 ? flag_code
== CODE_32BIT
6783 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6787 i386_att_operand (char *operand_string
)
6791 char *op_string
= operand_string
;
6793 if (is_space_char (*op_string
))
6796 /* We check for an absolute prefix (differentiating,
6797 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6798 if (*op_string
== ABSOLUTE_PREFIX
)
6801 if (is_space_char (*op_string
))
6803 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6806 /* Check if operand is a register. */
6807 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6809 i386_operand_type temp
;
6811 /* Check for a segment override by searching for ':' after a
6812 segment register. */
6814 if (is_space_char (*op_string
))
6816 if (*op_string
== ':'
6817 && (r
->reg_type
.bitfield
.sreg2
6818 || r
->reg_type
.bitfield
.sreg3
))
6823 i
.seg
[i
.mem_operands
] = &es
;
6826 i
.seg
[i
.mem_operands
] = &cs
;
6829 i
.seg
[i
.mem_operands
] = &ss
;
6832 i
.seg
[i
.mem_operands
] = &ds
;
6835 i
.seg
[i
.mem_operands
] = &fs
;
6838 i
.seg
[i
.mem_operands
] = &gs
;
6842 /* Skip the ':' and whitespace. */
6844 if (is_space_char (*op_string
))
6847 if (!is_digit_char (*op_string
)
6848 && !is_identifier_char (*op_string
)
6849 && *op_string
!= '('
6850 && *op_string
!= ABSOLUTE_PREFIX
)
6852 as_bad (_("bad memory operand `%s'"), op_string
);
6855 /* Handle case of %es:*foo. */
6856 if (*op_string
== ABSOLUTE_PREFIX
)
6859 if (is_space_char (*op_string
))
6861 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6863 goto do_memory_reference
;
6867 as_bad (_("junk `%s' after register"), op_string
);
6871 temp
.bitfield
.baseindex
= 0;
6872 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6874 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6875 i
.op
[this_operand
].regs
= r
;
6878 else if (*op_string
== REGISTER_PREFIX
)
6880 as_bad (_("bad register name `%s'"), op_string
);
6883 else if (*op_string
== IMMEDIATE_PREFIX
)
6886 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6888 as_bad (_("immediate operand illegal with absolute jump"));
6891 if (!i386_immediate (op_string
))
6894 else if (is_digit_char (*op_string
)
6895 || is_identifier_char (*op_string
)
6896 || *op_string
== '(')
6898 /* This is a memory reference of some sort. */
6901 /* Start and end of displacement string expression (if found). */
6902 char *displacement_string_start
;
6903 char *displacement_string_end
;
6905 do_memory_reference
:
6906 if ((i
.mem_operands
== 1
6907 && !current_templates
->start
->opcode_modifier
.isstring
)
6908 || i
.mem_operands
== 2)
6910 as_bad (_("too many memory references for `%s'"),
6911 current_templates
->start
->name
);
6915 /* Check for base index form. We detect the base index form by
6916 looking for an ')' at the end of the operand, searching
6917 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6919 base_string
= op_string
+ strlen (op_string
);
6922 if (is_space_char (*base_string
))
6925 /* If we only have a displacement, set-up for it to be parsed later. */
6926 displacement_string_start
= op_string
;
6927 displacement_string_end
= base_string
+ 1;
6929 if (*base_string
== ')')
6932 unsigned int parens_balanced
= 1;
6933 /* We've already checked that the number of left & right ()'s are
6934 equal, so this loop will not be infinite. */
6938 if (*base_string
== ')')
6940 if (*base_string
== '(')
6943 while (parens_balanced
);
6945 temp_string
= base_string
;
6947 /* Skip past '(' and whitespace. */
6949 if (is_space_char (*base_string
))
6952 if (*base_string
== ','
6953 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6956 displacement_string_end
= temp_string
;
6958 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6962 base_string
= end_op
;
6963 if (is_space_char (*base_string
))
6967 /* There may be an index reg or scale factor here. */
6968 if (*base_string
== ',')
6971 if (is_space_char (*base_string
))
6974 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6977 base_string
= end_op
;
6978 if (is_space_char (*base_string
))
6980 if (*base_string
== ',')
6983 if (is_space_char (*base_string
))
6986 else if (*base_string
!= ')')
6988 as_bad (_("expecting `,' or `)' "
6989 "after index register in `%s'"),
6994 else if (*base_string
== REGISTER_PREFIX
)
6996 as_bad (_("bad register name `%s'"), base_string
);
7000 /* Check for scale factor. */
7001 if (*base_string
!= ')')
7003 char *end_scale
= i386_scale (base_string
);
7008 base_string
= end_scale
;
7009 if (is_space_char (*base_string
))
7011 if (*base_string
!= ')')
7013 as_bad (_("expecting `)' "
7014 "after scale factor in `%s'"),
7019 else if (!i
.index_reg
)
7021 as_bad (_("expecting index register or scale factor "
7022 "after `,'; got '%c'"),
7027 else if (*base_string
!= ')')
7029 as_bad (_("expecting `,' or `)' "
7030 "after base register in `%s'"),
7035 else if (*base_string
== REGISTER_PREFIX
)
7037 as_bad (_("bad register name `%s'"), base_string
);
7042 /* If there's an expression beginning the operand, parse it,
7043 assuming displacement_string_start and
7044 displacement_string_end are meaningful. */
7045 if (displacement_string_start
!= displacement_string_end
)
7047 if (!i386_displacement (displacement_string_start
,
7048 displacement_string_end
))
7052 /* Special case for (%dx) while doing input/output op. */
7054 && operand_type_equal (&i
.base_reg
->reg_type
,
7055 ®16_inoutportreg
)
7057 && i
.log2_scale_factor
== 0
7058 && i
.seg
[i
.mem_operands
] == 0
7059 && !operand_type_check (i
.types
[this_operand
], disp
))
7061 i
.types
[this_operand
] = inoutportreg
;
7065 if (i386_index_check (operand_string
) == 0)
7067 i
.types
[this_operand
].bitfield
.mem
= 1;
7072 /* It's not a memory operand; argh! */
7073 as_bad (_("invalid char %s beginning operand %d `%s'"),
7074 output_invalid (*op_string
),
7079 return 1; /* Normal return. */
7082 /* md_estimate_size_before_relax()
7084 Called just before relax() for rs_machine_dependent frags. The x86
7085 assembler uses these frags to handle variable size jump
7088 Any symbol that is now undefined will not become defined.
7089 Return the correct fr_subtype in the frag.
7090 Return the initial "guess for variable size of frag" to caller.
7091 The guess is actually the growth beyond the fixed part. Whatever
7092 we do to grow the fixed or variable part contributes to our
7096 md_estimate_size_before_relax (fragP
, segment
)
7100 /* We've already got fragP->fr_subtype right; all we have to do is
7101 check for un-relaxable symbols. On an ELF system, we can't relax
7102 an externally visible symbol, because it may be overridden by a
7104 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7105 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7107 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7108 || S_IS_WEAK (fragP
->fr_symbol
)
7109 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7110 & BSF_GNU_INDIRECT_FUNCTION
))))
7112 #if defined (OBJ_COFF) && defined (TE_PE)
7113 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7114 && S_IS_WEAK (fragP
->fr_symbol
))
7118 /* Symbol is undefined in this segment, or we need to keep a
7119 reloc so that weak symbols can be overridden. */
7120 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7121 enum bfd_reloc_code_real reloc_type
;
7122 unsigned char *opcode
;
7125 if (fragP
->fr_var
!= NO_RELOC
)
7126 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7128 reloc_type
= BFD_RELOC_16_PCREL
;
7130 reloc_type
= BFD_RELOC_32_PCREL
;
7132 old_fr_fix
= fragP
->fr_fix
;
7133 opcode
= (unsigned char *) fragP
->fr_opcode
;
7135 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7138 /* Make jmp (0xeb) a (d)word displacement jump. */
7140 fragP
->fr_fix
+= size
;
7141 fix_new (fragP
, old_fr_fix
, size
,
7143 fragP
->fr_offset
, 1,
7149 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7151 /* Negate the condition, and branch past an
7152 unconditional jump. */
7155 /* Insert an unconditional jump. */
7157 /* We added two extra opcode bytes, and have a two byte
7159 fragP
->fr_fix
+= 2 + 2;
7160 fix_new (fragP
, old_fr_fix
+ 2, 2,
7162 fragP
->fr_offset
, 1,
7169 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7174 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7176 fragP
->fr_offset
, 1,
7178 fixP
->fx_signed
= 1;
7182 /* This changes the byte-displacement jump 0x7N
7183 to the (d)word-displacement jump 0x0f,0x8N. */
7184 opcode
[1] = opcode
[0] + 0x10;
7185 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7186 /* We've added an opcode byte. */
7187 fragP
->fr_fix
+= 1 + size
;
7188 fix_new (fragP
, old_fr_fix
+ 1, size
,
7190 fragP
->fr_offset
, 1,
7195 BAD_CASE (fragP
->fr_subtype
);
7199 return fragP
->fr_fix
- old_fr_fix
;
7202 /* Guess size depending on current relax state. Initially the relax
7203 state will correspond to a short jump and we return 1, because
7204 the variable part of the frag (the branch offset) is one byte
7205 long. However, we can relax a section more than once and in that
7206 case we must either set fr_subtype back to the unrelaxed state,
7207 or return the value for the appropriate branch. */
7208 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7211 /* Called after relax() is finished.
7213 In: Address of frag.
7214 fr_type == rs_machine_dependent.
7215 fr_subtype is what the address relaxed to.
7217 Out: Any fixSs and constants are set up.
7218 Caller will turn frag into a ".space 0". */
7221 md_convert_frag (abfd
, sec
, fragP
)
7222 bfd
*abfd ATTRIBUTE_UNUSED
;
7223 segT sec ATTRIBUTE_UNUSED
;
7226 unsigned char *opcode
;
7227 unsigned char *where_to_put_displacement
= NULL
;
7228 offsetT target_address
;
7229 offsetT opcode_address
;
7230 unsigned int extension
= 0;
7231 offsetT displacement_from_opcode_start
;
7233 opcode
= (unsigned char *) fragP
->fr_opcode
;
7235 /* Address we want to reach in file space. */
7236 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7238 /* Address opcode resides at in file space. */
7239 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7241 /* Displacement from opcode start to fill into instruction. */
7242 displacement_from_opcode_start
= target_address
- opcode_address
;
7244 if ((fragP
->fr_subtype
& BIG
) == 0)
7246 /* Don't have to change opcode. */
7247 extension
= 1; /* 1 opcode + 1 displacement */
7248 where_to_put_displacement
= &opcode
[1];
7252 if (no_cond_jump_promotion
7253 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7254 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7255 _("long jump required"));
7257 switch (fragP
->fr_subtype
)
7259 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7260 extension
= 4; /* 1 opcode + 4 displacement */
7262 where_to_put_displacement
= &opcode
[1];
7265 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7266 extension
= 2; /* 1 opcode + 2 displacement */
7268 where_to_put_displacement
= &opcode
[1];
7271 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7272 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7273 extension
= 5; /* 2 opcode + 4 displacement */
7274 opcode
[1] = opcode
[0] + 0x10;
7275 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7276 where_to_put_displacement
= &opcode
[2];
7279 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7280 extension
= 3; /* 2 opcode + 2 displacement */
7281 opcode
[1] = opcode
[0] + 0x10;
7282 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7283 where_to_put_displacement
= &opcode
[2];
7286 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7291 where_to_put_displacement
= &opcode
[3];
7295 BAD_CASE (fragP
->fr_subtype
);
7300 /* If size if less then four we are sure that the operand fits,
7301 but if it's 4, then it could be that the displacement is larger
7303 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7305 && ((addressT
) (displacement_from_opcode_start
- extension
7306 + ((addressT
) 1 << 31))
7307 > (((addressT
) 2 << 31) - 1)))
7309 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7310 _("jump target out of range"));
7311 /* Make us emit 0. */
7312 displacement_from_opcode_start
= extension
;
7314 /* Now put displacement after opcode. */
7315 md_number_to_chars ((char *) where_to_put_displacement
,
7316 (valueT
) (displacement_from_opcode_start
- extension
),
7317 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7318 fragP
->fr_fix
+= extension
;
7321 /* Apply a fixup (fixS) to segment data, once it has been determined
7322 by our caller that we have all the info we need to fix it up.
7324 On the 386, immediates, displacements, and data pointers are all in
7325 the same (little-endian) format, so we don't need to care about which
7329 md_apply_fix (fixP
, valP
, seg
)
7330 /* The fix we're to put in. */
7332 /* Pointer to the value of the bits. */
7334 /* Segment fix is from. */
7335 segT seg ATTRIBUTE_UNUSED
;
7337 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7338 valueT value
= *valP
;
7340 #if !defined (TE_Mach)
7343 switch (fixP
->fx_r_type
)
7349 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7352 case BFD_RELOC_X86_64_32S
:
7353 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7356 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7359 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7364 if (fixP
->fx_addsy
!= NULL
7365 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7366 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7367 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7368 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7369 && !use_rela_relocations
)
7371 /* This is a hack. There should be a better way to handle this.
7372 This covers for the fact that bfd_install_relocation will
7373 subtract the current location (for partial_inplace, PC relative
7374 relocations); see more below. */
7378 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7381 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7383 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7386 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7389 || (symbol_section_p (fixP
->fx_addsy
)
7390 && sym_seg
!= absolute_section
))
7391 && !generic_force_reloc (fixP
))
7393 /* Yes, we add the values in twice. This is because
7394 bfd_install_relocation subtracts them out again. I think
7395 bfd_install_relocation is broken, but I don't dare change
7397 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7401 #if defined (OBJ_COFF) && defined (TE_PE)
7402 /* For some reason, the PE format does not store a
7403 section address offset for a PC relative symbol. */
7404 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7405 || S_IS_WEAK (fixP
->fx_addsy
))
7406 value
+= md_pcrel_from (fixP
);
7409 #if defined (OBJ_COFF) && defined (TE_PE)
7410 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7412 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7416 /* Fix a few things - the dynamic linker expects certain values here,
7417 and we must not disappoint it. */
7418 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7419 if (IS_ELF
&& fixP
->fx_addsy
)
7420 switch (fixP
->fx_r_type
)
7422 case BFD_RELOC_386_PLT32
:
7423 case BFD_RELOC_X86_64_PLT32
:
7424 /* Make the jump instruction point to the address of the operand. At
7425 runtime we merely add the offset to the actual PLT entry. */
7429 case BFD_RELOC_386_TLS_GD
:
7430 case BFD_RELOC_386_TLS_LDM
:
7431 case BFD_RELOC_386_TLS_IE_32
:
7432 case BFD_RELOC_386_TLS_IE
:
7433 case BFD_RELOC_386_TLS_GOTIE
:
7434 case BFD_RELOC_386_TLS_GOTDESC
:
7435 case BFD_RELOC_X86_64_TLSGD
:
7436 case BFD_RELOC_X86_64_TLSLD
:
7437 case BFD_RELOC_X86_64_GOTTPOFF
:
7438 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7439 value
= 0; /* Fully resolved at runtime. No addend. */
7441 case BFD_RELOC_386_TLS_LE
:
7442 case BFD_RELOC_386_TLS_LDO_32
:
7443 case BFD_RELOC_386_TLS_LE_32
:
7444 case BFD_RELOC_X86_64_DTPOFF32
:
7445 case BFD_RELOC_X86_64_DTPOFF64
:
7446 case BFD_RELOC_X86_64_TPOFF32
:
7447 case BFD_RELOC_X86_64_TPOFF64
:
7448 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7451 case BFD_RELOC_386_TLS_DESC_CALL
:
7452 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7453 value
= 0; /* Fully resolved at runtime. No addend. */
7454 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7458 case BFD_RELOC_386_GOT32
:
7459 case BFD_RELOC_X86_64_GOT32
:
7460 value
= 0; /* Fully resolved at runtime. No addend. */
7463 case BFD_RELOC_VTABLE_INHERIT
:
7464 case BFD_RELOC_VTABLE_ENTRY
:
7471 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7473 #endif /* !defined (TE_Mach) */
7475 /* Are we finished with this relocation now? */
7476 if (fixP
->fx_addsy
== NULL
)
7478 #if defined (OBJ_COFF) && defined (TE_PE)
7479 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7482 /* Remember value for tc_gen_reloc. */
7483 fixP
->fx_addnumber
= value
;
7484 /* Clear out the frag for now. */
7488 else if (use_rela_relocations
)
7490 fixP
->fx_no_overflow
= 1;
7491 /* Remember value for tc_gen_reloc. */
7492 fixP
->fx_addnumber
= value
;
7496 md_number_to_chars (p
, value
, fixP
->fx_size
);
7500 md_atof (int type
, char *litP
, int *sizeP
)
7502 /* This outputs the LITTLENUMs in REVERSE order;
7503 in accord with the bigendian 386. */
7504 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7507 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7510 output_invalid (int c
)
7513 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7516 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7517 "(0x%x)", (unsigned char) c
);
7518 return output_invalid_buf
;
7521 /* REG_STRING starts *before* REGISTER_PREFIX. */
7523 static const reg_entry
*
7524 parse_real_register (char *reg_string
, char **end_op
)
7526 char *s
= reg_string
;
7528 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7531 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7532 if (*s
== REGISTER_PREFIX
)
7535 if (is_space_char (*s
))
7539 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7541 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7542 return (const reg_entry
*) NULL
;
7546 /* For naked regs, make sure that we are not dealing with an identifier.
7547 This prevents confusing an identifier like `eax_var' with register
7549 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7550 return (const reg_entry
*) NULL
;
7554 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7556 /* Handle floating point regs, allowing spaces in the (i) part. */
7557 if (r
== i386_regtab
/* %st is first entry of table */)
7559 if (is_space_char (*s
))
7564 if (is_space_char (*s
))
7566 if (*s
>= '0' && *s
<= '7')
7570 if (is_space_char (*s
))
7575 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7580 /* We have "%st(" then garbage. */
7581 return (const reg_entry
*) NULL
;
7585 if (r
== NULL
|| allow_pseudo_reg
)
7588 if (operand_type_all_zero (&r
->reg_type
))
7589 return (const reg_entry
*) NULL
;
7591 if ((r
->reg_type
.bitfield
.reg32
7592 || r
->reg_type
.bitfield
.sreg3
7593 || r
->reg_type
.bitfield
.control
7594 || r
->reg_type
.bitfield
.debug
7595 || r
->reg_type
.bitfield
.test
)
7596 && !cpu_arch_flags
.bitfield
.cpui386
)
7597 return (const reg_entry
*) NULL
;
7599 if (r
->reg_type
.bitfield
.floatreg
7600 && !cpu_arch_flags
.bitfield
.cpu8087
7601 && !cpu_arch_flags
.bitfield
.cpu287
7602 && !cpu_arch_flags
.bitfield
.cpu387
)
7603 return (const reg_entry
*) NULL
;
7605 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7606 return (const reg_entry
*) NULL
;
7608 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7609 return (const reg_entry
*) NULL
;
7611 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7612 return (const reg_entry
*) NULL
;
7614 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7615 if (!allow_index_reg
7616 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7617 return (const reg_entry
*) NULL
;
7619 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7620 || r
->reg_type
.bitfield
.reg64
)
7621 && (!cpu_arch_flags
.bitfield
.cpulm
7622 || !operand_type_equal (&r
->reg_type
, &control
))
7623 && flag_code
!= CODE_64BIT
)
7624 return (const reg_entry
*) NULL
;
7626 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7627 return (const reg_entry
*) NULL
;
7632 /* REG_STRING starts *before* REGISTER_PREFIX. */
7634 static const reg_entry
*
7635 parse_register (char *reg_string
, char **end_op
)
7639 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7640 r
= parse_real_register (reg_string
, end_op
);
7645 char *save
= input_line_pointer
;
7649 input_line_pointer
= reg_string
;
7650 c
= get_symbol_end ();
7651 symbolP
= symbol_find (reg_string
);
7652 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7654 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7656 know (e
->X_op
== O_register
);
7657 know (e
->X_add_number
>= 0
7658 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7659 r
= i386_regtab
+ e
->X_add_number
;
7660 *end_op
= input_line_pointer
;
7662 *input_line_pointer
= c
;
7663 input_line_pointer
= save
;
7669 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7672 char *end
= input_line_pointer
;
7675 r
= parse_register (name
, &input_line_pointer
);
7676 if (r
&& end
<= input_line_pointer
)
7678 *nextcharP
= *input_line_pointer
;
7679 *input_line_pointer
= 0;
7680 e
->X_op
= O_register
;
7681 e
->X_add_number
= r
- i386_regtab
;
7684 input_line_pointer
= end
;
7686 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7690 md_operand (expressionS
*e
)
7695 switch (*input_line_pointer
)
7697 case REGISTER_PREFIX
:
7698 r
= parse_real_register (input_line_pointer
, &end
);
7701 e
->X_op
= O_register
;
7702 e
->X_add_number
= r
- i386_regtab
;
7703 input_line_pointer
= end
;
7708 gas_assert (intel_syntax
);
7709 end
= input_line_pointer
++;
7711 if (*input_line_pointer
== ']')
7713 ++input_line_pointer
;
7714 e
->X_op_symbol
= make_expr_symbol (e
);
7715 e
->X_add_symbol
= NULL
;
7716 e
->X_add_number
= 0;
7722 input_line_pointer
= end
;
7729 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7730 const char *md_shortopts
= "kVQ:sqn";
7732 const char *md_shortopts
= "qn";
7735 #define OPTION_32 (OPTION_MD_BASE + 0)
7736 #define OPTION_64 (OPTION_MD_BASE + 1)
7737 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7738 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7739 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7740 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7741 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7742 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7743 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7744 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7745 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7746 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7748 struct option md_longopts
[] =
7750 {"32", no_argument
, NULL
, OPTION_32
},
7751 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7752 || defined (TE_PE) || defined (TE_PEP))
7753 {"64", no_argument
, NULL
, OPTION_64
},
7755 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7756 {"march", required_argument
, NULL
, OPTION_MARCH
},
7757 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7758 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7759 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7760 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7761 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7762 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7763 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7764 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7765 {NULL
, no_argument
, NULL
, 0}
7767 size_t md_longopts_size
= sizeof (md_longopts
);
7770 md_parse_option (int c
, char *arg
)
7778 optimize_align_code
= 0;
7785 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7786 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7787 should be emitted or not. FIXME: Not implemented. */
7791 /* -V: SVR4 argument to print version ID. */
7793 print_version_id ();
7796 /* -k: Ignore for FreeBSD compatibility. */
7801 /* -s: On i386 Solaris, this tells the native assembler to use
7802 .stab instead of .stab.excl. We always use .stab anyhow. */
7805 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7806 || defined (TE_PE) || defined (TE_PEP))
7809 const char **list
, **l
;
7811 list
= bfd_target_list ();
7812 for (l
= list
; *l
!= NULL
; l
++)
7813 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7814 || strcmp (*l
, "coff-x86-64") == 0
7815 || strcmp (*l
, "pe-x86-64") == 0
7816 || strcmp (*l
, "pei-x86-64") == 0)
7818 default_arch
= "x86_64";
7822 as_fatal (_("No compiled in support for x86_64"));
7829 default_arch
= "i386";
7833 #ifdef SVR4_COMMENT_CHARS
7838 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7840 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7844 i386_comment_chars
= n
;
7850 arch
= xstrdup (arg
);
7854 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7855 next
= strchr (arch
, '+');
7858 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7860 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7863 cpu_arch_name
= cpu_arch
[i
].name
;
7864 cpu_sub_arch_name
= NULL
;
7865 cpu_arch_flags
= cpu_arch
[i
].flags
;
7866 cpu_arch_isa
= cpu_arch
[i
].type
;
7867 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7868 if (!cpu_arch_tune_set
)
7870 cpu_arch_tune
= cpu_arch_isa
;
7871 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7875 else if (*cpu_arch
[i
].name
== '.'
7876 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7878 /* ISA entension. */
7879 i386_cpu_flags flags
;
7881 if (strncmp (arch
, "no", 2))
7882 flags
= cpu_flags_or (cpu_arch_flags
,
7885 flags
= cpu_flags_and_not (cpu_arch_flags
,
7887 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7889 if (cpu_sub_arch_name
)
7891 char *name
= cpu_sub_arch_name
;
7892 cpu_sub_arch_name
= concat (name
,
7894 (const char *) NULL
);
7898 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7899 cpu_arch_flags
= flags
;
7905 if (i
>= ARRAY_SIZE (cpu_arch
))
7906 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7910 while (next
!= NULL
);
7915 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7916 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7918 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7920 cpu_arch_tune_set
= 1;
7921 cpu_arch_tune
= cpu_arch
[i
].type
;
7922 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7926 if (i
>= ARRAY_SIZE (cpu_arch
))
7927 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7930 case OPTION_MMNEMONIC
:
7931 if (strcasecmp (arg
, "att") == 0)
7933 else if (strcasecmp (arg
, "intel") == 0)
7936 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7939 case OPTION_MSYNTAX
:
7940 if (strcasecmp (arg
, "att") == 0)
7942 else if (strcasecmp (arg
, "intel") == 0)
7945 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7948 case OPTION_MINDEX_REG
:
7949 allow_index_reg
= 1;
7952 case OPTION_MNAKED_REG
:
7953 allow_naked_reg
= 1;
7956 case OPTION_MOLD_GCC
:
7960 case OPTION_MSSE2AVX
:
7964 case OPTION_MSSE_CHECK
:
7965 if (strcasecmp (arg
, "error") == 0)
7966 sse_check
= sse_check_error
;
7967 else if (strcasecmp (arg
, "warning") == 0)
7968 sse_check
= sse_check_warning
;
7969 else if (strcasecmp (arg
, "none") == 0)
7970 sse_check
= sse_check_none
;
7972 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7982 md_show_usage (stream
)
7985 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7986 fprintf (stream
, _("\
7988 -V print assembler version number\n\
7991 fprintf (stream
, _("\
7992 -n Do not optimize code alignment\n\
7993 -q quieten some warnings\n"));
7994 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7995 fprintf (stream
, _("\
7998 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7999 || defined (TE_PE) || defined (TE_PEP))
8000 fprintf (stream
, _("\
8001 --32/--64 generate 32bit/64bit code\n"));
8003 #ifdef SVR4_COMMENT_CHARS
8004 fprintf (stream
, _("\
8005 --divide do not treat `/' as a comment character\n"));
8007 fprintf (stream
, _("\
8008 --divide ignored\n"));
8010 fprintf (stream
, _("\
8011 -march=CPU[,+EXTENSION...]\n\
8012 generate code for CPU and EXTENSION, CPU is one of:\n\
8013 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8014 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8015 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8016 amdfam10, generic32, generic64\n\
8017 EXTENSION is combination of:\n\
8018 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8019 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8020 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8021 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8022 svme, abm, padlock, fma4\n"));
8023 fprintf (stream
, _("\
8024 -mtune=CPU optimize for CPU, CPU is one of:\n\
8025 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8026 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8027 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8028 amdfam10, generic32, generic64\n"));
8029 fprintf (stream
, _("\
8030 -msse2avx encode SSE instructions with VEX prefix\n"));
8031 fprintf (stream
, _("\
8032 -msse-check=[none|error|warning]\n\
8033 check SSE instructions\n"));
8034 fprintf (stream
, _("\
8035 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8036 fprintf (stream
, _("\
8037 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8038 fprintf (stream
, _("\
8039 -mindex-reg support pseudo index registers\n"));
8040 fprintf (stream
, _("\
8041 -mnaked-reg don't require `%%' prefix for registers\n"));
8042 fprintf (stream
, _("\
8043 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8046 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8047 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8048 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8050 /* Pick the target format to use. */
8053 i386_target_format (void)
8055 if (!strcmp (default_arch
, "x86_64"))
8057 set_code_flag (CODE_64BIT
);
8058 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8060 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8061 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8062 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8063 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8064 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8065 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8066 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8067 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8068 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8069 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8070 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8072 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8074 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8075 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8076 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8077 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8078 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8079 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8080 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8081 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8082 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8083 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8086 else if (!strcmp (default_arch
, "i386"))
8088 set_code_flag (CODE_32BIT
);
8089 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8091 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8092 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8093 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8095 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8097 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8098 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8099 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8103 as_fatal (_("Unknown architecture"));
8104 switch (OUTPUT_FLAVOR
)
8106 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8107 case bfd_target_aout_flavour
:
8108 return AOUT_TARGET_FORMAT
;
8110 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8111 # if defined (TE_PE) || defined (TE_PEP)
8112 case bfd_target_coff_flavour
:
8113 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8114 # elif defined (TE_GO32)
8115 case bfd_target_coff_flavour
:
8118 case bfd_target_coff_flavour
:
8122 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8123 case bfd_target_elf_flavour
:
8125 if (flag_code
== CODE_64BIT
)
8128 use_rela_relocations
= 1;
8130 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8132 if (flag_code
!= CODE_64BIT
)
8133 as_fatal (_("Intel L1OM is 64bit only"));
8134 return ELF_TARGET_L1OM_FORMAT
;
8137 return (flag_code
== CODE_64BIT
8138 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8141 #if defined (OBJ_MACH_O)
8142 case bfd_target_mach_o_flavour
:
8143 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8151 #endif /* OBJ_MAYBE_ more than one */
8153 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8155 i386_elf_emit_arch_note (void)
8157 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8160 asection
*seg
= now_seg
;
8161 subsegT subseg
= now_subseg
;
8162 Elf_Internal_Note i_note
;
8163 Elf_External_Note e_note
;
8164 asection
*note_secp
;
8167 /* Create the .note section. */
8168 note_secp
= subseg_new (".note", 0);
8169 bfd_set_section_flags (stdoutput
,
8171 SEC_HAS_CONTENTS
| SEC_READONLY
);
8173 /* Process the arch string. */
8174 len
= strlen (cpu_arch_name
);
8176 i_note
.namesz
= len
+ 1;
8178 i_note
.type
= NT_ARCH
;
8179 p
= frag_more (sizeof (e_note
.namesz
));
8180 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8181 p
= frag_more (sizeof (e_note
.descsz
));
8182 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8183 p
= frag_more (sizeof (e_note
.type
));
8184 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8185 p
= frag_more (len
+ 1);
8186 strcpy (p
, cpu_arch_name
);
8188 frag_align (2, 0, 0);
8190 subseg_set (seg
, subseg
);
8196 md_undefined_symbol (name
)
8199 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8200 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8201 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8202 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8206 if (symbol_find (name
))
8207 as_bad (_("GOT already in symbol table"));
8208 GOT_symbol
= symbol_new (name
, undefined_section
,
8209 (valueT
) 0, &zero_address_frag
);
8216 /* Round up a section size to the appropriate boundary. */
8219 md_section_align (segment
, size
)
8220 segT segment ATTRIBUTE_UNUSED
;
8223 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8224 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8226 /* For a.out, force the section size to be aligned. If we don't do
8227 this, BFD will align it for us, but it will not write out the
8228 final bytes of the section. This may be a bug in BFD, but it is
8229 easier to fix it here since that is how the other a.out targets
8233 align
= bfd_get_section_alignment (stdoutput
, segment
);
8234 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8241 /* On the i386, PC-relative offsets are relative to the start of the
8242 next instruction. That is, the address of the offset, plus its
8243 size, since the offset is always the last part of the insn. */
8246 md_pcrel_from (fixS
*fixP
)
8248 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8254 s_bss (int ignore ATTRIBUTE_UNUSED
)
8258 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8260 obj_elf_section_change_hook ();
8262 temp
= get_absolute_expression ();
8263 subseg_set (bss_section
, (subsegT
) temp
);
8264 demand_empty_rest_of_line ();
8270 i386_validate_fix (fixS
*fixp
)
8272 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8274 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8278 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8283 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8285 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8292 tc_gen_reloc (section
, fixp
)
8293 asection
*section ATTRIBUTE_UNUSED
;
8297 bfd_reloc_code_real_type code
;
8299 switch (fixp
->fx_r_type
)
8301 case BFD_RELOC_X86_64_PLT32
:
8302 case BFD_RELOC_X86_64_GOT32
:
8303 case BFD_RELOC_X86_64_GOTPCREL
:
8304 case BFD_RELOC_386_PLT32
:
8305 case BFD_RELOC_386_GOT32
:
8306 case BFD_RELOC_386_GOTOFF
:
8307 case BFD_RELOC_386_GOTPC
:
8308 case BFD_RELOC_386_TLS_GD
:
8309 case BFD_RELOC_386_TLS_LDM
:
8310 case BFD_RELOC_386_TLS_LDO_32
:
8311 case BFD_RELOC_386_TLS_IE_32
:
8312 case BFD_RELOC_386_TLS_IE
:
8313 case BFD_RELOC_386_TLS_GOTIE
:
8314 case BFD_RELOC_386_TLS_LE_32
:
8315 case BFD_RELOC_386_TLS_LE
:
8316 case BFD_RELOC_386_TLS_GOTDESC
:
8317 case BFD_RELOC_386_TLS_DESC_CALL
:
8318 case BFD_RELOC_X86_64_TLSGD
:
8319 case BFD_RELOC_X86_64_TLSLD
:
8320 case BFD_RELOC_X86_64_DTPOFF32
:
8321 case BFD_RELOC_X86_64_DTPOFF64
:
8322 case BFD_RELOC_X86_64_GOTTPOFF
:
8323 case BFD_RELOC_X86_64_TPOFF32
:
8324 case BFD_RELOC_X86_64_TPOFF64
:
8325 case BFD_RELOC_X86_64_GOTOFF64
:
8326 case BFD_RELOC_X86_64_GOTPC32
:
8327 case BFD_RELOC_X86_64_GOT64
:
8328 case BFD_RELOC_X86_64_GOTPCREL64
:
8329 case BFD_RELOC_X86_64_GOTPC64
:
8330 case BFD_RELOC_X86_64_GOTPLT64
:
8331 case BFD_RELOC_X86_64_PLTOFF64
:
8332 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8333 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8335 case BFD_RELOC_VTABLE_ENTRY
:
8336 case BFD_RELOC_VTABLE_INHERIT
:
8338 case BFD_RELOC_32_SECREL
:
8340 code
= fixp
->fx_r_type
;
8342 case BFD_RELOC_X86_64_32S
:
8343 if (!fixp
->fx_pcrel
)
8345 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8346 code
= fixp
->fx_r_type
;
8352 switch (fixp
->fx_size
)
8355 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8356 _("can not do %d byte pc-relative relocation"),
8358 code
= BFD_RELOC_32_PCREL
;
8360 case 1: code
= BFD_RELOC_8_PCREL
; break;
8361 case 2: code
= BFD_RELOC_16_PCREL
; break;
8362 case 4: code
= BFD_RELOC_32_PCREL
; break;
8364 case 8: code
= BFD_RELOC_64_PCREL
; break;
8370 switch (fixp
->fx_size
)
8373 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8374 _("can not do %d byte relocation"),
8376 code
= BFD_RELOC_32
;
8378 case 1: code
= BFD_RELOC_8
; break;
8379 case 2: code
= BFD_RELOC_16
; break;
8380 case 4: code
= BFD_RELOC_32
; break;
8382 case 8: code
= BFD_RELOC_64
; break;
8389 if ((code
== BFD_RELOC_32
8390 || code
== BFD_RELOC_32_PCREL
8391 || code
== BFD_RELOC_X86_64_32S
)
8393 && fixp
->fx_addsy
== GOT_symbol
)
8396 code
= BFD_RELOC_386_GOTPC
;
8398 code
= BFD_RELOC_X86_64_GOTPC32
;
8400 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8402 && fixp
->fx_addsy
== GOT_symbol
)
8404 code
= BFD_RELOC_X86_64_GOTPC64
;
8407 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8408 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8409 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8411 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8413 if (!use_rela_relocations
)
8415 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8416 vtable entry to be used in the relocation's section offset. */
8417 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8418 rel
->address
= fixp
->fx_offset
;
8419 #if defined (OBJ_COFF) && defined (TE_PE)
8420 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8421 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8426 /* Use the rela in 64bit mode. */
8429 if (!fixp
->fx_pcrel
)
8430 rel
->addend
= fixp
->fx_offset
;
8434 case BFD_RELOC_X86_64_PLT32
:
8435 case BFD_RELOC_X86_64_GOT32
:
8436 case BFD_RELOC_X86_64_GOTPCREL
:
8437 case BFD_RELOC_X86_64_TLSGD
:
8438 case BFD_RELOC_X86_64_TLSLD
:
8439 case BFD_RELOC_X86_64_GOTTPOFF
:
8440 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8441 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8442 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8445 rel
->addend
= (section
->vma
8447 + fixp
->fx_addnumber
8448 + md_pcrel_from (fixp
));
8453 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8454 if (rel
->howto
== NULL
)
8456 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8457 _("cannot represent relocation type %s"),
8458 bfd_get_reloc_code_name (code
));
8459 /* Set howto to a garbage value so that we can keep going. */
8460 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8461 gas_assert (rel
->howto
!= NULL
);
8467 #include "tc-i386-intel.c"
8470 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8472 int saved_naked_reg
;
8473 char saved_register_dot
;
8475 saved_naked_reg
= allow_naked_reg
;
8476 allow_naked_reg
= 1;
8477 saved_register_dot
= register_chars
['.'];
8478 register_chars
['.'] = '.';
8479 allow_pseudo_reg
= 1;
8480 expression_and_evaluate (exp
);
8481 allow_pseudo_reg
= 0;
8482 register_chars
['.'] = saved_register_dot
;
8483 allow_naked_reg
= saved_naked_reg
;
8485 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8487 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8489 exp
->X_op
= O_constant
;
8490 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8491 .dw2_regnum
[flag_code
>> 1];
8494 exp
->X_op
= O_illegal
;
8499 tc_x86_frame_initial_instructions (void)
8501 static unsigned int sp_regno
[2];
8503 if (!sp_regno
[flag_code
>> 1])
8505 char *saved_input
= input_line_pointer
;
8506 char sp
[][4] = {"esp", "rsp"};
8509 input_line_pointer
= sp
[flag_code
>> 1];
8510 tc_x86_parse_to_dw2regnum (&exp
);
8511 gas_assert (exp
.X_op
== O_constant
);
8512 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8513 input_line_pointer
= saved_input
;
8516 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8517 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8521 i386_elf_section_type (const char *str
, size_t len
)
8523 if (flag_code
== CODE_64BIT
8524 && len
== sizeof ("unwind") - 1
8525 && strncmp (str
, "unwind", 6) == 0)
8526 return SHT_X86_64_UNWIND
;
8533 i386_solaris_fix_up_eh_frame (segT sec
)
8535 if (flag_code
== CODE_64BIT
)
8536 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8542 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8546 expr
.X_op
= O_secrel
;
8547 expr
.X_add_symbol
= symbol
;
8548 expr
.X_add_number
= 0;
8549 emit_expr (&expr
, size
);
8553 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8554 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8557 x86_64_section_letter (int letter
, char **ptr_msg
)
8559 if (flag_code
== CODE_64BIT
)
8562 return SHF_X86_64_LARGE
;
8564 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8567 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8572 x86_64_section_word (char *str
, size_t len
)
8574 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8575 return SHF_X86_64_LARGE
;
8581 handle_large_common (int small ATTRIBUTE_UNUSED
)
8583 if (flag_code
!= CODE_64BIT
)
8585 s_comm_internal (0, elf_common_parse
);
8586 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8590 static segT lbss_section
;
8591 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8592 asection
*saved_bss_section
= bss_section
;
8594 if (lbss_section
== NULL
)
8596 flagword applicable
;
8598 subsegT subseg
= now_subseg
;
8600 /* The .lbss section is for local .largecomm symbols. */
8601 lbss_section
= subseg_new (".lbss", 0);
8602 applicable
= bfd_applicable_section_flags (stdoutput
);
8603 bfd_set_section_flags (stdoutput
, lbss_section
,
8604 applicable
& SEC_ALLOC
);
8605 seg_info (lbss_section
)->bss
= 1;
8607 subseg_set (seg
, subseg
);
8610 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8611 bss_section
= lbss_section
;
8613 s_comm_internal (0, elf_common_parse
);
8615 elf_com_section_ptr
= saved_com_section_ptr
;
8616 bss_section
= saved_bss_section
;
8619 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */