1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
135 unsigned int negated
; /* turn off indicated flags. */
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_sse_check (int);
146 static void set_cpu_arch (int);
148 static void pe_directive_secrel (int);
150 static void signed_cons (int);
151 static char *output_invalid (int c
);
152 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
154 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS
*);
159 static int i386_intel_parse_name (const char *, expressionS
*);
160 static const reg_entry
*parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (int, int);
165 static void optimize_imm (void);
166 static void optimize_disp (void);
167 static const insn_template
*match_template (void);
168 static int check_string (void);
169 static int process_suffix (void);
170 static int check_byte_reg (void);
171 static int check_long_reg (void);
172 static int check_qword_reg (void);
173 static int check_word_reg (void);
174 static int finalize_imm (void);
175 static int process_operands (void);
176 static const seg_entry
*build_modrm_byte (void);
177 static void output_insn (void);
178 static void output_imm (fragS
*, offsetT
);
179 static void output_disp (fragS
*, offsetT
);
181 static void s_bss (int);
183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
187 static const char *default_arch
= DEFAULT_ARCH
;
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes
[3];
195 /* Destination or source register specifier. */
196 const reg_entry
*register_specifier
;
199 /* 'md_assemble ()' gathers together information and puts it into a
206 const reg_entry
*regs
;
211 operand_size_mismatch
,
212 operand_type_mismatch
,
213 register_type_mismatch
,
214 number_of_operands_mismatch
,
215 invalid_instruction_suffix
,
218 unsupported_with_intel_mnemonic
,
225 /* TM holds the template for the insn were currently assembling. */
228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
232 /* OPERANDS gives the number of given operands. */
233 unsigned int operands
;
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
238 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
240 /* TYPES [i] is the type (see above #defines) which tells us how to
241 use OP[i] for the corresponding operand. */
242 i386_operand_type types
[MAX_OPERANDS
];
244 /* Displacement expression, immediate expression, or register for each
246 union i386_op op
[MAX_OPERANDS
];
248 /* Flags for operands. */
249 unsigned int flags
[MAX_OPERANDS
];
250 #define Operand_PCrel 1
252 /* Relocation type for operand */
253 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry
*base_reg
;
258 const reg_entry
*index_reg
;
259 unsigned int log2_scale_factor
;
261 /* SEG gives the seg_entries of this insn. They are zero unless
262 explicit segment overrides are given. */
263 const seg_entry
*seg
[2];
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes
;
268 unsigned char prefix
[MAX_PREFIXES
];
270 /* RM and SIB are the modrm byte and the sib byte where the
271 addressing modes of this insn are encoded. */
277 /* Swap operand in encoding. */
278 unsigned int swap_operand
;
281 enum i386_error error
;
284 typedef struct _i386_insn i386_insn
;
286 /* List of chars besides those in app.c:symbol_chars that can start an
287 operand. Used to prevent the scrubber eating vital white-space. */
288 const char extra_symbol_chars
[] = "*%-(["
297 #if (defined (TE_I386AIX) \
298 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
299 && !defined (TE_GNU) \
300 && !defined (TE_LINUX) \
301 && !defined (TE_NETWARE) \
302 && !defined (TE_FreeBSD) \
303 && !defined (TE_NetBSD)))
304 /* This array holds the chars that always start a comment. If the
305 pre-processor is disabled, these aren't very useful. The option
306 --divide will remove '/' from this list. */
307 const char *i386_comment_chars
= "#/";
308 #define SVR4_COMMENT_CHARS 1
309 #define PREFIX_SEPARATOR '\\'
312 const char *i386_comment_chars
= "#";
313 #define PREFIX_SEPARATOR '/'
316 /* This array holds the chars that only start a comment at the beginning of
317 a line. If the line seems to have the form '# 123 filename'
318 .line and .file directives will appear in the pre-processed output.
319 Note that input_file.c hand checks for '#' at the beginning of the
320 first line of the input file. This is because the compiler outputs
321 #NO_APP at the beginning of its output.
322 Also note that comments started like this one will always work if
323 '/' isn't otherwise defined. */
324 const char line_comment_chars
[] = "#/";
326 const char line_separator_chars
[] = ";";
328 /* Chars that can be used to separate mant from exp in floating point
330 const char EXP_CHARS
[] = "eE";
332 /* Chars that mean this number is a floating point constant
335 const char FLT_CHARS
[] = "fFdDxX";
337 /* Tables for lexical analysis. */
338 static char mnemonic_chars
[256];
339 static char register_chars
[256];
340 static char operand_chars
[256];
341 static char identifier_chars
[256];
342 static char digit_chars
[256];
344 /* Lexical macros. */
345 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
346 #define is_operand_char(x) (operand_chars[(unsigned char) x])
347 #define is_register_char(x) (register_chars[(unsigned char) x])
348 #define is_space_char(x) ((x) == ' ')
349 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
350 #define is_digit_char(x) (digit_chars[(unsigned char) x])
352 /* All non-digit non-letter characters that may occur in an operand. */
353 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
355 /* md_assemble() always leaves the strings it's passed unaltered. To
356 effect this we maintain a stack of saved characters that we've smashed
357 with '\0's (indicating end of strings for various sub-fields of the
358 assembler instruction). */
359 static char save_stack
[32];
360 static char *save_stack_p
;
361 #define END_STRING_AND_SAVE(s) \
362 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
363 #define RESTORE_END_STRING(s) \
364 do { *(s) = *--save_stack_p; } while (0)
366 /* The instruction we're assembling. */
369 /* Possible templates for current insn. */
370 static const templates
*current_templates
;
372 /* Per instruction expressionS buffers: max displacements & immediates. */
373 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
374 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
376 /* Current operand we are working on. */
377 static int this_operand
= -1;
379 /* We support four different modes. FLAG_CODE variable is used to distinguish
387 static enum flag_code flag_code
;
388 static unsigned int object_64bit
;
389 static int use_rela_relocations
= 0;
391 /* The names used to print error messages. */
392 static const char *flag_code_names
[] =
399 /* 1 for intel syntax,
401 static int intel_syntax
= 0;
403 /* 1 for intel mnemonic,
404 0 if att mnemonic. */
405 static int intel_mnemonic
= !SYSV386_COMPAT
;
407 /* 1 if support old (<= 2.8.1) versions of gcc. */
408 static int old_gcc
= OLDGCC_COMPAT
;
410 /* 1 if pseudo registers are permitted. */
411 static int allow_pseudo_reg
= 0;
413 /* 1 if register prefix % not required. */
414 static int allow_naked_reg
= 0;
416 /* 1 if pseudo index register, eiz/riz, is allowed . */
417 static int allow_index_reg
= 0;
427 /* Register prefix used for error message. */
428 static const char *register_prefix
= "%";
430 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
431 leave, push, and pop instructions so that gcc has the same stack
432 frame as in 32 bit mode. */
433 static char stackop_size
= '\0';
435 /* Non-zero to optimize code alignment. */
436 int optimize_align_code
= 1;
438 /* Non-zero to quieten some warnings. */
439 static int quiet_warnings
= 0;
442 static const char *cpu_arch_name
= NULL
;
443 static char *cpu_sub_arch_name
= NULL
;
445 /* CPU feature flags. */
446 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
448 /* If we have selected a cpu we are generating instructions for. */
449 static int cpu_arch_tune_set
= 0;
451 /* Cpu we are generating instructions for. */
452 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
454 /* CPU feature flags of cpu we are generating instructions for. */
455 static i386_cpu_flags cpu_arch_tune_flags
;
457 /* CPU instruction set architecture used. */
458 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
460 /* CPU feature flags of instruction set architecture used. */
461 i386_cpu_flags cpu_arch_isa_flags
;
463 /* If set, conditional jumps are not automatically promoted to handle
464 larger than a byte offset. */
465 static unsigned int no_cond_jump_promotion
= 0;
467 /* Encode SSE instructions with VEX prefix. */
468 static unsigned int sse2avx
;
470 /* Encode scalar AVX instructions with specific vector length. */
477 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
478 static symbolS
*GOT_symbol
;
480 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
481 unsigned int x86_dwarf2_return_column
;
483 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
484 int x86_cie_data_alignment
;
486 /* Interface to relax_segment.
487 There are 3 major relax states for 386 jump insns because the
488 different types of jumps add different sizes to frags when we're
489 figuring out what sort of jump to choose to reach a given label. */
492 #define UNCOND_JUMP 0
494 #define COND_JUMP86 2
499 #define SMALL16 (SMALL | CODE16)
501 #define BIG16 (BIG | CODE16)
505 #define INLINE __inline__
511 #define ENCODE_RELAX_STATE(type, size) \
512 ((relax_substateT) (((type) << 2) | (size)))
513 #define TYPE_FROM_RELAX_STATE(s) \
515 #define DISP_SIZE_FROM_RELAX_STATE(s) \
516 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
518 /* This table is used by relax_frag to promote short jumps to long
519 ones where necessary. SMALL (short) jumps may be promoted to BIG
520 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
521 don't allow a short jump in a 32 bit code segment to be promoted to
522 a 16 bit offset jump because it's slower (requires data size
523 prefix), and doesn't work, unless the destination is in the bottom
524 64k of the code segment (The top 16 bits of eip are zeroed). */
526 const relax_typeS md_relax_table
[] =
529 1) most positive reach of this state,
530 2) most negative reach of this state,
531 3) how many bytes this mode will have in the variable part of the frag
532 4) which index into the table to try if we can't fit into this one. */
534 /* UNCOND_JUMP states. */
535 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
536 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
537 /* dword jmp adds 4 bytes to frag:
538 0 extra opcode bytes, 4 displacement bytes. */
540 /* word jmp adds 2 byte2 to frag:
541 0 extra opcode bytes, 2 displacement bytes. */
544 /* COND_JUMP states. */
545 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
546 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
547 /* dword conditionals adds 5 bytes to frag:
548 1 extra opcode byte, 4 displacement bytes. */
550 /* word conditionals add 3 bytes to frag:
551 1 extra opcode byte, 2 displacement bytes. */
554 /* COND_JUMP86 states. */
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
557 /* dword conditionals adds 5 bytes to frag:
558 1 extra opcode byte, 4 displacement bytes. */
560 /* word conditionals add 4 bytes to frag:
561 1 displacement byte and a 3 byte long branch insn. */
565 static const arch_entry cpu_arch
[] =
567 /* Do not replace the first two entries - i386_target_format()
568 relies on them being there in this order. */
569 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
570 CPU_GENERIC32_FLAGS
, 0, 0 },
571 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
572 CPU_GENERIC64_FLAGS
, 0, 0 },
573 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
574 CPU_NONE_FLAGS
, 0, 0 },
575 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
576 CPU_I186_FLAGS
, 0, 0 },
577 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
578 CPU_I286_FLAGS
, 0, 0 },
579 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
580 CPU_I386_FLAGS
, 0, 0 },
581 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
582 CPU_I486_FLAGS
, 0, 0 },
583 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
584 CPU_I586_FLAGS
, 0, 0 },
585 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
586 CPU_I686_FLAGS
, 0, 0 },
587 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
588 CPU_I586_FLAGS
, 0, 0 },
589 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
590 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
591 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
592 CPU_P2_FLAGS
, 0, 0 },
593 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
594 CPU_P3_FLAGS
, 0, 0 },
595 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
596 CPU_P4_FLAGS
, 0, 0 },
597 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
598 CPU_CORE_FLAGS
, 0, 0 },
599 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
600 CPU_NOCONA_FLAGS
, 0, 0 },
601 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
602 CPU_CORE_FLAGS
, 1, 0 },
603 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
604 CPU_CORE_FLAGS
, 0, 0 },
605 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
606 CPU_CORE2_FLAGS
, 1, 0 },
607 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
608 CPU_CORE2_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
610 CPU_COREI7_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
612 CPU_L1OM_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
614 CPU_K6_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
616 CPU_K6_2_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
618 CPU_ATHLON_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
620 CPU_K8_FLAGS
, 1, 0 },
621 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
622 CPU_K8_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
624 CPU_K8_FLAGS
, 0, 0 },
625 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
626 CPU_AMDFAM10_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
628 CPU_BDVER1_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
630 CPU_8087_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
632 CPU_287_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
634 CPU_387_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
636 CPU_ANY87_FLAGS
, 0, 1 },
637 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
638 CPU_MMX_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
640 CPU_3DNOWA_FLAGS
, 0, 1 },
641 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
642 CPU_SSE_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
644 CPU_SSE2_FLAGS
, 0, 0 },
645 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
646 CPU_SSE3_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
648 CPU_SSSE3_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
650 CPU_SSE4_1_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
652 CPU_SSE4_2_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
654 CPU_SSE4_2_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
656 CPU_ANY_SSE_FLAGS
, 0, 1 },
657 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
658 CPU_AVX_FLAGS
, 0, 0 },
659 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
660 CPU_ANY_AVX_FLAGS
, 0, 1 },
661 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
662 CPU_VMX_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
664 CPU_SMX_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
666 CPU_XSAVE_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
668 CPU_XSAVEOPT_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
670 CPU_AES_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
672 CPU_PCLMUL_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
674 CPU_PCLMUL_FLAGS
, 1, 0 },
675 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
676 CPU_FSGSBASE_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
678 CPU_RDRND_FLAGS
, 0, 0 },
679 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
680 CPU_F16C_FLAGS
, 0, 0 },
681 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
682 CPU_FMA_FLAGS
, 0, 0 },
683 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
684 CPU_FMA4_FLAGS
, 0, 0 },
685 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
686 CPU_XOP_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
688 CPU_LWP_FLAGS
, 0, 0 },
689 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
690 CPU_MOVBE_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
692 CPU_EPT_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
694 CPU_CLFLUSH_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
696 CPU_NOP_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
698 CPU_SYSCALL_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
700 CPU_RDTSCP_FLAGS
, 0, 0 },
701 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
702 CPU_3DNOW_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
704 CPU_3DNOWA_FLAGS
, 0, 0 },
705 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
706 CPU_PADLOCK_FLAGS
, 0, 0 },
707 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
708 CPU_SVME_FLAGS
, 1, 0 },
709 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
710 CPU_SVME_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
712 CPU_SSE4A_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
714 CPU_ABM_FLAGS
, 0, 0 },
718 /* Like s_lcomm_internal in gas/read.c but the alignment string
719 is allowed to be optional. */
722 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
729 && *input_line_pointer
== ',')
731 align
= parse_align (needs_align
- 1);
733 if (align
== (addressT
) -1)
748 bss_alloc (symbolP
, size
, align
);
753 pe_lcomm (int needs_align
)
755 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
759 const pseudo_typeS md_pseudo_table
[] =
761 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
762 {"align", s_align_bytes
, 0},
764 {"align", s_align_ptwo
, 0},
766 {"arch", set_cpu_arch
, 0},
770 {"lcomm", pe_lcomm
, 1},
772 {"ffloat", float_cons
, 'f'},
773 {"dfloat", float_cons
, 'd'},
774 {"tfloat", float_cons
, 'x'},
776 {"slong", signed_cons
, 4},
777 {"noopt", s_ignore
, 0},
778 {"optim", s_ignore
, 0},
779 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
780 {"code16", set_code_flag
, CODE_16BIT
},
781 {"code32", set_code_flag
, CODE_32BIT
},
782 {"code64", set_code_flag
, CODE_64BIT
},
783 {"intel_syntax", set_intel_syntax
, 1},
784 {"att_syntax", set_intel_syntax
, 0},
785 {"intel_mnemonic", set_intel_mnemonic
, 1},
786 {"att_mnemonic", set_intel_mnemonic
, 0},
787 {"allow_index_reg", set_allow_index_reg
, 1},
788 {"disallow_index_reg", set_allow_index_reg
, 0},
789 {"sse_check", set_sse_check
, 0},
790 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
791 {"largecomm", handle_large_common
, 0},
793 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
794 {"loc", dwarf2_directive_loc
, 0},
795 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
798 {"secrel32", pe_directive_secrel
, 0},
803 /* For interface with expression (). */
804 extern char *input_line_pointer
;
806 /* Hash table for instruction mnemonic lookup. */
807 static struct hash_control
*op_hash
;
809 /* Hash table for register lookup. */
810 static struct hash_control
*reg_hash
;
813 i386_align_code (fragS
*fragP
, int count
)
815 /* Various efficient no-op patterns for aligning code labels.
816 Note: Don't try to assemble the instructions in the comments.
817 0L and 0w are not legal. */
818 static const char f32_1
[] =
820 static const char f32_2
[] =
821 {0x66,0x90}; /* xchg %ax,%ax */
822 static const char f32_3
[] =
823 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
824 static const char f32_4
[] =
825 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
826 static const char f32_5
[] =
828 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
829 static const char f32_6
[] =
830 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
831 static const char f32_7
[] =
832 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
833 static const char f32_8
[] =
835 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
836 static const char f32_9
[] =
837 {0x89,0xf6, /* movl %esi,%esi */
838 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
839 static const char f32_10
[] =
840 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
841 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
842 static const char f32_11
[] =
843 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
844 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
845 static const char f32_12
[] =
846 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
847 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
848 static const char f32_13
[] =
849 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
850 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
851 static const char f32_14
[] =
852 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
853 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
854 static const char f16_3
[] =
855 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
856 static const char f16_4
[] =
857 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
858 static const char f16_5
[] =
860 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
861 static const char f16_6
[] =
862 {0x89,0xf6, /* mov %si,%si */
863 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
864 static const char f16_7
[] =
865 {0x8d,0x74,0x00, /* lea 0(%si),%si */
866 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
867 static const char f16_8
[] =
868 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
869 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
870 static const char jump_31
[] =
871 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
872 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
873 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
874 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
875 static const char *const f32_patt
[] = {
876 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
877 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
879 static const char *const f16_patt
[] = {
880 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
883 static const char alt_3
[] =
885 /* nopl 0(%[re]ax) */
886 static const char alt_4
[] =
887 {0x0f,0x1f,0x40,0x00};
888 /* nopl 0(%[re]ax,%[re]ax,1) */
889 static const char alt_5
[] =
890 {0x0f,0x1f,0x44,0x00,0x00};
891 /* nopw 0(%[re]ax,%[re]ax,1) */
892 static const char alt_6
[] =
893 {0x66,0x0f,0x1f,0x44,0x00,0x00};
894 /* nopl 0L(%[re]ax) */
895 static const char alt_7
[] =
896 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
897 /* nopl 0L(%[re]ax,%[re]ax,1) */
898 static const char alt_8
[] =
899 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* nopw 0L(%[re]ax,%[re]ax,1) */
901 static const char alt_9
[] =
902 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_10
[] =
905 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
907 nopw %cs:0L(%[re]ax,%[re]ax,1) */
908 static const char alt_long_11
[] =
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 nopw %cs:0L(%[re]ax,%[re]ax,1) */
914 static const char alt_long_12
[] =
917 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
921 nopw %cs:0L(%[re]ax,%[re]ax,1) */
922 static const char alt_long_13
[] =
926 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_long_14
[] =
937 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
943 nopw %cs:0L(%[re]ax,%[re]ax,1) */
944 static const char alt_long_15
[] =
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 /* nopl 0(%[re]ax,%[re]ax,1)
952 nopw 0(%[re]ax,%[re]ax,1) */
953 static const char alt_short_11
[] =
954 {0x0f,0x1f,0x44,0x00,0x00,
955 0x66,0x0f,0x1f,0x44,0x00,0x00};
956 /* nopw 0(%[re]ax,%[re]ax,1)
957 nopw 0(%[re]ax,%[re]ax,1) */
958 static const char alt_short_12
[] =
959 {0x66,0x0f,0x1f,0x44,0x00,0x00,
960 0x66,0x0f,0x1f,0x44,0x00,0x00};
961 /* nopw 0(%[re]ax,%[re]ax,1)
963 static const char alt_short_13
[] =
964 {0x66,0x0f,0x1f,0x44,0x00,0x00,
965 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
968 static const char alt_short_14
[] =
969 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
970 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
972 nopl 0L(%[re]ax,%[re]ax,1) */
973 static const char alt_short_15
[] =
974 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
975 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
976 static const char *const alt_short_patt
[] = {
977 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
978 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
979 alt_short_14
, alt_short_15
981 static const char *const alt_long_patt
[] = {
982 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
983 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
984 alt_long_14
, alt_long_15
987 /* Only align for at least a positive non-zero boundary. */
988 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
991 /* We need to decide which NOP sequence to use for 32bit and
992 64bit. When -mtune= is used:
994 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
995 PROCESSOR_GENERIC32, f32_patt will be used.
996 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
997 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
998 PROCESSOR_GENERIC64, alt_long_patt will be used.
999 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1000 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
1003 When -mtune= isn't used, alt_long_patt will be used if
1004 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1007 When -march= or .arch is used, we can't use anything beyond
1008 cpu_arch_isa_flags. */
1010 if (flag_code
== CODE_16BIT
)
1014 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1016 /* Adjust jump offset. */
1017 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1020 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1021 f16_patt
[count
- 1], count
);
1025 const char *const *patt
= NULL
;
1027 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1029 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1030 switch (cpu_arch_tune
)
1032 case PROCESSOR_UNKNOWN
:
1033 /* We use cpu_arch_isa_flags to check if we SHOULD
1034 optimize with nops. */
1035 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1036 patt
= alt_long_patt
;
1040 case PROCESSOR_PENTIUMPRO
:
1041 case PROCESSOR_PENTIUM4
:
1042 case PROCESSOR_NOCONA
:
1043 case PROCESSOR_CORE
:
1044 case PROCESSOR_CORE2
:
1045 case PROCESSOR_COREI7
:
1046 case PROCESSOR_L1OM
:
1047 case PROCESSOR_GENERIC64
:
1048 patt
= alt_long_patt
;
1051 case PROCESSOR_ATHLON
:
1053 case PROCESSOR_AMDFAM10
:
1054 case PROCESSOR_BDVER1
:
1055 patt
= alt_short_patt
;
1057 case PROCESSOR_I386
:
1058 case PROCESSOR_I486
:
1059 case PROCESSOR_PENTIUM
:
1060 case PROCESSOR_GENERIC32
:
1067 switch (fragP
->tc_frag_data
.tune
)
1069 case PROCESSOR_UNKNOWN
:
1070 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1071 PROCESSOR_UNKNOWN. */
1075 case PROCESSOR_I386
:
1076 case PROCESSOR_I486
:
1077 case PROCESSOR_PENTIUM
:
1079 case PROCESSOR_ATHLON
:
1081 case PROCESSOR_AMDFAM10
:
1082 case PROCESSOR_BDVER1
:
1083 case PROCESSOR_GENERIC32
:
1084 /* We use cpu_arch_isa_flags to check if we CAN optimize
1086 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1087 patt
= alt_short_patt
;
1091 case PROCESSOR_PENTIUMPRO
:
1092 case PROCESSOR_PENTIUM4
:
1093 case PROCESSOR_NOCONA
:
1094 case PROCESSOR_CORE
:
1095 case PROCESSOR_CORE2
:
1096 case PROCESSOR_COREI7
:
1097 case PROCESSOR_L1OM
:
1098 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1099 patt
= alt_long_patt
;
1103 case PROCESSOR_GENERIC64
:
1104 patt
= alt_long_patt
;
1109 if (patt
== f32_patt
)
1111 /* If the padding is less than 15 bytes, we use the normal
1112 ones. Otherwise, we use a jump instruction and adjust
1116 /* For 64bit, the limit is 3 bytes. */
1117 if (flag_code
== CODE_64BIT
1118 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1123 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1124 patt
[count
- 1], count
);
1127 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1129 /* Adjust jump offset. */
1130 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1135 /* Maximum length of an instruction is 15 byte. If the
1136 padding is greater than 15 bytes and we don't use jump,
1137 we have to break it into smaller pieces. */
1138 int padding
= count
;
1139 while (padding
> 15)
1142 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1147 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1148 patt
[padding
- 1], padding
);
1151 fragP
->fr_var
= count
;
1155 operand_type_all_zero (const union i386_operand_type
*x
)
1157 switch (ARRAY_SIZE(x
->array
))
1166 return !x
->array
[0];
1173 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1175 switch (ARRAY_SIZE(x
->array
))
1190 operand_type_equal (const union i386_operand_type
*x
,
1191 const union i386_operand_type
*y
)
1193 switch (ARRAY_SIZE(x
->array
))
1196 if (x
->array
[2] != y
->array
[2])
1199 if (x
->array
[1] != y
->array
[1])
1202 return x
->array
[0] == y
->array
[0];
1210 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1212 switch (ARRAY_SIZE(x
->array
))
1221 return !x
->array
[0];
1228 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1230 switch (ARRAY_SIZE(x
->array
))
1245 cpu_flags_equal (const union i386_cpu_flags
*x
,
1246 const union i386_cpu_flags
*y
)
1248 switch (ARRAY_SIZE(x
->array
))
1251 if (x
->array
[2] != y
->array
[2])
1254 if (x
->array
[1] != y
->array
[1])
1257 return x
->array
[0] == y
->array
[0];
1265 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1267 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1268 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1271 static INLINE i386_cpu_flags
1272 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1274 switch (ARRAY_SIZE (x
.array
))
1277 x
.array
[2] &= y
.array
[2];
1279 x
.array
[1] &= y
.array
[1];
1281 x
.array
[0] &= y
.array
[0];
1289 static INLINE i386_cpu_flags
1290 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1292 switch (ARRAY_SIZE (x
.array
))
1295 x
.array
[2] |= y
.array
[2];
1297 x
.array
[1] |= y
.array
[1];
1299 x
.array
[0] |= y
.array
[0];
1307 static INLINE i386_cpu_flags
1308 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1310 switch (ARRAY_SIZE (x
.array
))
1313 x
.array
[2] &= ~y
.array
[2];
1315 x
.array
[1] &= ~y
.array
[1];
1317 x
.array
[0] &= ~y
.array
[0];
1325 #define CPU_FLAGS_ARCH_MATCH 0x1
1326 #define CPU_FLAGS_64BIT_MATCH 0x2
1327 #define CPU_FLAGS_AES_MATCH 0x4
1328 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1329 #define CPU_FLAGS_AVX_MATCH 0x10
1331 #define CPU_FLAGS_32BIT_MATCH \
1332 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1333 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1334 #define CPU_FLAGS_PERFECT_MATCH \
1335 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1337 /* Return CPU flags match bits. */
1340 cpu_flags_match (const insn_template
*t
)
1342 i386_cpu_flags x
= t
->cpu_flags
;
1343 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1345 x
.bitfield
.cpu64
= 0;
1346 x
.bitfield
.cpuno64
= 0;
1348 if (cpu_flags_all_zero (&x
))
1350 /* This instruction is available on all archs. */
1351 match
|= CPU_FLAGS_32BIT_MATCH
;
1355 /* This instruction is available only on some archs. */
1356 i386_cpu_flags cpu
= cpu_arch_flags
;
1358 cpu
.bitfield
.cpu64
= 0;
1359 cpu
.bitfield
.cpuno64
= 0;
1360 cpu
= cpu_flags_and (x
, cpu
);
1361 if (!cpu_flags_all_zero (&cpu
))
1363 if (x
.bitfield
.cpuavx
)
1365 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1366 if (cpu
.bitfield
.cpuavx
)
1368 /* Check SSE2AVX. */
1369 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1371 match
|= (CPU_FLAGS_ARCH_MATCH
1372 | CPU_FLAGS_AVX_MATCH
);
1374 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1375 match
|= CPU_FLAGS_AES_MATCH
;
1377 if (!x
.bitfield
.cpupclmul
1378 || cpu
.bitfield
.cpupclmul
)
1379 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1383 match
|= CPU_FLAGS_ARCH_MATCH
;
1386 match
|= CPU_FLAGS_32BIT_MATCH
;
1392 static INLINE i386_operand_type
1393 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1395 switch (ARRAY_SIZE (x
.array
))
1398 x
.array
[2] &= y
.array
[2];
1400 x
.array
[1] &= y
.array
[1];
1402 x
.array
[0] &= y
.array
[0];
1410 static INLINE i386_operand_type
1411 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1413 switch (ARRAY_SIZE (x
.array
))
1416 x
.array
[2] |= y
.array
[2];
1418 x
.array
[1] |= y
.array
[1];
1420 x
.array
[0] |= y
.array
[0];
1428 static INLINE i386_operand_type
1429 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1431 switch (ARRAY_SIZE (x
.array
))
1434 x
.array
[2] ^= y
.array
[2];
1436 x
.array
[1] ^= y
.array
[1];
1438 x
.array
[0] ^= y
.array
[0];
1446 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1447 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1448 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1449 static const i386_operand_type inoutportreg
1450 = OPERAND_TYPE_INOUTPORTREG
;
1451 static const i386_operand_type reg16_inoutportreg
1452 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1453 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1454 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1455 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1456 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1457 static const i386_operand_type anydisp
1458 = OPERAND_TYPE_ANYDISP
;
1459 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1460 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1461 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1462 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1463 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1464 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1465 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1466 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1467 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1468 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1469 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1470 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1481 operand_type_check (i386_operand_type t
, enum operand_type c
)
1486 return (t
.bitfield
.reg8
1489 || t
.bitfield
.reg64
);
1492 return (t
.bitfield
.imm8
1496 || t
.bitfield
.imm32s
1497 || t
.bitfield
.imm64
);
1500 return (t
.bitfield
.disp8
1501 || t
.bitfield
.disp16
1502 || t
.bitfield
.disp32
1503 || t
.bitfield
.disp32s
1504 || t
.bitfield
.disp64
);
1507 return (t
.bitfield
.disp8
1508 || t
.bitfield
.disp16
1509 || t
.bitfield
.disp32
1510 || t
.bitfield
.disp32s
1511 || t
.bitfield
.disp64
1512 || t
.bitfield
.baseindex
);
1521 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1522 operand J for instruction template T. */
1525 match_reg_size (const insn_template
*t
, unsigned int j
)
1527 return !((i
.types
[j
].bitfield
.byte
1528 && !t
->operand_types
[j
].bitfield
.byte
)
1529 || (i
.types
[j
].bitfield
.word
1530 && !t
->operand_types
[j
].bitfield
.word
)
1531 || (i
.types
[j
].bitfield
.dword
1532 && !t
->operand_types
[j
].bitfield
.dword
)
1533 || (i
.types
[j
].bitfield
.qword
1534 && !t
->operand_types
[j
].bitfield
.qword
));
1537 /* Return 1 if there is no conflict in any size on operand J for
1538 instruction template T. */
1541 match_mem_size (const insn_template
*t
, unsigned int j
)
1543 return (match_reg_size (t
, j
)
1544 && !((i
.types
[j
].bitfield
.unspecified
1545 && !t
->operand_types
[j
].bitfield
.unspecified
)
1546 || (i
.types
[j
].bitfield
.fword
1547 && !t
->operand_types
[j
].bitfield
.fword
)
1548 || (i
.types
[j
].bitfield
.tbyte
1549 && !t
->operand_types
[j
].bitfield
.tbyte
)
1550 || (i
.types
[j
].bitfield
.xmmword
1551 && !t
->operand_types
[j
].bitfield
.xmmword
)
1552 || (i
.types
[j
].bitfield
.ymmword
1553 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1556 /* Return 1 if there is no size conflict on any operands for
1557 instruction template T. */
1560 operand_size_match (const insn_template
*t
)
1565 /* Don't check jump instructions. */
1566 if (t
->opcode_modifier
.jump
1567 || t
->opcode_modifier
.jumpbyte
1568 || t
->opcode_modifier
.jumpdword
1569 || t
->opcode_modifier
.jumpintersegment
)
1572 /* Check memory and accumulator operand size. */
1573 for (j
= 0; j
< i
.operands
; j
++)
1575 if (t
->operand_types
[j
].bitfield
.anysize
)
1578 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1584 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1593 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1596 i
.error
= operand_size_mismatch
;
1600 /* Check reverse. */
1601 gas_assert (i
.operands
== 2);
1604 for (j
= 0; j
< 2; j
++)
1606 if (t
->operand_types
[j
].bitfield
.acc
1607 && !match_reg_size (t
, j
? 0 : 1))
1610 if (i
.types
[j
].bitfield
.mem
1611 && !match_mem_size (t
, j
? 0 : 1))
1619 operand_type_match (i386_operand_type overlap
,
1620 i386_operand_type given
)
1622 i386_operand_type temp
= overlap
;
1624 temp
.bitfield
.jumpabsolute
= 0;
1625 temp
.bitfield
.unspecified
= 0;
1626 temp
.bitfield
.byte
= 0;
1627 temp
.bitfield
.word
= 0;
1628 temp
.bitfield
.dword
= 0;
1629 temp
.bitfield
.fword
= 0;
1630 temp
.bitfield
.qword
= 0;
1631 temp
.bitfield
.tbyte
= 0;
1632 temp
.bitfield
.xmmword
= 0;
1633 temp
.bitfield
.ymmword
= 0;
1634 if (operand_type_all_zero (&temp
))
1637 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1638 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1642 i
.error
= operand_type_mismatch
;
1646 /* If given types g0 and g1 are registers they must be of the same type
1647 unless the expected operand type register overlap is null.
1648 Note that Acc in a template matches every size of reg. */
1651 operand_type_register_match (i386_operand_type m0
,
1652 i386_operand_type g0
,
1653 i386_operand_type t0
,
1654 i386_operand_type m1
,
1655 i386_operand_type g1
,
1656 i386_operand_type t1
)
1658 if (!operand_type_check (g0
, reg
))
1661 if (!operand_type_check (g1
, reg
))
1664 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1665 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1666 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1667 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1670 if (m0
.bitfield
.acc
)
1672 t0
.bitfield
.reg8
= 1;
1673 t0
.bitfield
.reg16
= 1;
1674 t0
.bitfield
.reg32
= 1;
1675 t0
.bitfield
.reg64
= 1;
1678 if (m1
.bitfield
.acc
)
1680 t1
.bitfield
.reg8
= 1;
1681 t1
.bitfield
.reg16
= 1;
1682 t1
.bitfield
.reg32
= 1;
1683 t1
.bitfield
.reg64
= 1;
1686 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1687 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1688 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1689 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1692 i
.error
= register_type_mismatch
;
1697 static INLINE
unsigned int
1698 mode_from_disp_size (i386_operand_type t
)
1700 if (t
.bitfield
.disp8
)
1702 else if (t
.bitfield
.disp16
1703 || t
.bitfield
.disp32
1704 || t
.bitfield
.disp32s
)
1711 fits_in_signed_byte (offsetT num
)
1713 return (num
>= -128) && (num
<= 127);
1717 fits_in_unsigned_byte (offsetT num
)
1719 return (num
& 0xff) == num
;
1723 fits_in_unsigned_word (offsetT num
)
1725 return (num
& 0xffff) == num
;
1729 fits_in_signed_word (offsetT num
)
1731 return (-32768 <= num
) && (num
<= 32767);
1735 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1740 return (!(((offsetT
) -1 << 31) & num
)
1741 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1743 } /* fits_in_signed_long() */
1746 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1751 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1753 } /* fits_in_unsigned_long() */
1756 fits_in_imm4 (offsetT num
)
1758 return (num
& 0xf) == num
;
1761 static i386_operand_type
1762 smallest_imm_type (offsetT num
)
1764 i386_operand_type t
;
1766 operand_type_set (&t
, 0);
1767 t
.bitfield
.imm64
= 1;
1769 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1771 /* This code is disabled on the 486 because all the Imm1 forms
1772 in the opcode table are slower on the i486. They're the
1773 versions with the implicitly specified single-position
1774 displacement, which has another syntax if you really want to
1776 t
.bitfield
.imm1
= 1;
1777 t
.bitfield
.imm8
= 1;
1778 t
.bitfield
.imm8s
= 1;
1779 t
.bitfield
.imm16
= 1;
1780 t
.bitfield
.imm32
= 1;
1781 t
.bitfield
.imm32s
= 1;
1783 else if (fits_in_signed_byte (num
))
1785 t
.bitfield
.imm8
= 1;
1786 t
.bitfield
.imm8s
= 1;
1787 t
.bitfield
.imm16
= 1;
1788 t
.bitfield
.imm32
= 1;
1789 t
.bitfield
.imm32s
= 1;
1791 else if (fits_in_unsigned_byte (num
))
1793 t
.bitfield
.imm8
= 1;
1794 t
.bitfield
.imm16
= 1;
1795 t
.bitfield
.imm32
= 1;
1796 t
.bitfield
.imm32s
= 1;
1798 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1800 t
.bitfield
.imm16
= 1;
1801 t
.bitfield
.imm32
= 1;
1802 t
.bitfield
.imm32s
= 1;
1804 else if (fits_in_signed_long (num
))
1806 t
.bitfield
.imm32
= 1;
1807 t
.bitfield
.imm32s
= 1;
1809 else if (fits_in_unsigned_long (num
))
1810 t
.bitfield
.imm32
= 1;
1816 offset_in_range (offsetT val
, int size
)
1822 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1823 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1824 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1826 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1832 /* If BFD64, sign extend val for 32bit address mode. */
1833 if (flag_code
!= CODE_64BIT
1834 || i
.prefix
[ADDR_PREFIX
])
1835 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1836 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1839 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1841 char buf1
[40], buf2
[40];
1843 sprint_value (buf1
, val
);
1844 sprint_value (buf2
, val
& mask
);
1845 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1859 a. PREFIX_EXIST if attempting to add a prefix where one from the
1860 same class already exists.
1861 b. PREFIX_LOCK if lock prefix is added.
1862 c. PREFIX_REP if rep/repne prefix is added.
1863 d. PREFIX_OTHER if other prefix is added.
1866 static enum PREFIX_GROUP
1867 add_prefix (unsigned int prefix
)
1869 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1872 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1873 && flag_code
== CODE_64BIT
)
1875 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1876 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1877 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1888 case CS_PREFIX_OPCODE
:
1889 case DS_PREFIX_OPCODE
:
1890 case ES_PREFIX_OPCODE
:
1891 case FS_PREFIX_OPCODE
:
1892 case GS_PREFIX_OPCODE
:
1893 case SS_PREFIX_OPCODE
:
1897 case REPNE_PREFIX_OPCODE
:
1898 case REPE_PREFIX_OPCODE
:
1903 case LOCK_PREFIX_OPCODE
:
1912 case ADDR_PREFIX_OPCODE
:
1916 case DATA_PREFIX_OPCODE
:
1920 if (i
.prefix
[q
] != 0)
1928 i
.prefix
[q
] |= prefix
;
1931 as_bad (_("same type of prefix used twice"));
1937 update_code_flag (int value
, int check
)
1939 PRINTF_LIKE ((*as_error
));
1941 flag_code
= (enum flag_code
) value
;
1942 if (flag_code
== CODE_64BIT
)
1944 cpu_arch_flags
.bitfield
.cpu64
= 1;
1945 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1949 cpu_arch_flags
.bitfield
.cpu64
= 0;
1950 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1952 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1955 as_error
= as_fatal
;
1958 (*as_error
) (_("64bit mode not supported on `%s'."),
1959 cpu_arch_name
? cpu_arch_name
: default_arch
);
1961 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1964 as_error
= as_fatal
;
1967 (*as_error
) (_("32bit mode not supported on `%s'."),
1968 cpu_arch_name
? cpu_arch_name
: default_arch
);
1970 stackop_size
= '\0';
1974 set_code_flag (int value
)
1976 update_code_flag (value
, 0);
1980 set_16bit_gcc_code_flag (int new_code_flag
)
1982 flag_code
= (enum flag_code
) new_code_flag
;
1983 if (flag_code
!= CODE_16BIT
)
1985 cpu_arch_flags
.bitfield
.cpu64
= 0;
1986 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1987 stackop_size
= LONG_MNEM_SUFFIX
;
1991 set_intel_syntax (int syntax_flag
)
1993 /* Find out if register prefixing is specified. */
1994 int ask_naked_reg
= 0;
1997 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1999 char *string
= input_line_pointer
;
2000 int e
= get_symbol_end ();
2002 if (strcmp (string
, "prefix") == 0)
2004 else if (strcmp (string
, "noprefix") == 0)
2007 as_bad (_("bad argument to syntax directive."));
2008 *input_line_pointer
= e
;
2010 demand_empty_rest_of_line ();
2012 intel_syntax
= syntax_flag
;
2014 if (ask_naked_reg
== 0)
2015 allow_naked_reg
= (intel_syntax
2016 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2018 allow_naked_reg
= (ask_naked_reg
< 0);
2020 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2022 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2023 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2024 register_prefix
= allow_naked_reg
? "" : "%";
2028 set_intel_mnemonic (int mnemonic_flag
)
2030 intel_mnemonic
= mnemonic_flag
;
2034 set_allow_index_reg (int flag
)
2036 allow_index_reg
= flag
;
2040 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2044 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2046 char *string
= input_line_pointer
;
2047 int e
= get_symbol_end ();
2049 if (strcmp (string
, "none") == 0)
2050 sse_check
= sse_check_none
;
2051 else if (strcmp (string
, "warning") == 0)
2052 sse_check
= sse_check_warning
;
2053 else if (strcmp (string
, "error") == 0)
2054 sse_check
= sse_check_error
;
2056 as_bad (_("bad argument to sse_check directive."));
2057 *input_line_pointer
= e
;
2060 as_bad (_("missing argument for sse_check directive"));
2062 demand_empty_rest_of_line ();
2066 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2067 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2069 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2070 static const char *arch
;
2072 /* Intel LIOM is only supported on ELF. */
2078 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2079 use default_arch. */
2080 arch
= cpu_arch_name
;
2082 arch
= default_arch
;
2085 /* If we are targeting Intel L1OM, we must enable it. */
2086 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2087 || new_flag
.bitfield
.cpul1om
)
2090 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2095 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2099 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2101 char *string
= input_line_pointer
;
2102 int e
= get_symbol_end ();
2104 i386_cpu_flags flags
;
2106 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2108 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2110 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2114 cpu_arch_name
= cpu_arch
[j
].name
;
2115 cpu_sub_arch_name
= NULL
;
2116 cpu_arch_flags
= cpu_arch
[j
].flags
;
2117 if (flag_code
== CODE_64BIT
)
2119 cpu_arch_flags
.bitfield
.cpu64
= 1;
2120 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2124 cpu_arch_flags
.bitfield
.cpu64
= 0;
2125 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2127 cpu_arch_isa
= cpu_arch
[j
].type
;
2128 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2129 if (!cpu_arch_tune_set
)
2131 cpu_arch_tune
= cpu_arch_isa
;
2132 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2137 if (!cpu_arch
[j
].negated
)
2138 flags
= cpu_flags_or (cpu_arch_flags
,
2141 flags
= cpu_flags_and_not (cpu_arch_flags
,
2143 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2145 if (cpu_sub_arch_name
)
2147 char *name
= cpu_sub_arch_name
;
2148 cpu_sub_arch_name
= concat (name
,
2150 (const char *) NULL
);
2154 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2155 cpu_arch_flags
= flags
;
2157 *input_line_pointer
= e
;
2158 demand_empty_rest_of_line ();
2162 if (j
>= ARRAY_SIZE (cpu_arch
))
2163 as_bad (_("no such architecture: `%s'"), string
);
2165 *input_line_pointer
= e
;
2168 as_bad (_("missing cpu architecture"));
2170 no_cond_jump_promotion
= 0;
2171 if (*input_line_pointer
== ','
2172 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2174 char *string
= ++input_line_pointer
;
2175 int e
= get_symbol_end ();
2177 if (strcmp (string
, "nojumps") == 0)
2178 no_cond_jump_promotion
= 1;
2179 else if (strcmp (string
, "jumps") == 0)
2182 as_bad (_("no such architecture modifier: `%s'"), string
);
2184 *input_line_pointer
= e
;
2187 demand_empty_rest_of_line ();
2190 enum bfd_architecture
2193 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2195 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2196 || flag_code
!= CODE_64BIT
)
2197 as_fatal (_("Intel L1OM is 64bit ELF only"));
2198 return bfd_arch_l1om
;
2201 return bfd_arch_i386
;
2207 if (!strcmp (default_arch
, "x86_64"))
2209 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2211 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2212 as_fatal (_("Intel L1OM is 64bit ELF only"));
2213 return bfd_mach_l1om
;
2216 return bfd_mach_x86_64
;
2218 else if (!strcmp (default_arch
, "i386"))
2219 return bfd_mach_i386_i386
;
2221 as_fatal (_("Unknown architecture"));
2227 const char *hash_err
;
2229 /* Initialize op_hash hash table. */
2230 op_hash
= hash_new ();
2233 const insn_template
*optab
;
2234 templates
*core_optab
;
2236 /* Setup for loop. */
2238 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2239 core_optab
->start
= optab
;
2244 if (optab
->name
== NULL
2245 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2247 /* different name --> ship out current template list;
2248 add to hash table; & begin anew. */
2249 core_optab
->end
= optab
;
2250 hash_err
= hash_insert (op_hash
,
2252 (void *) core_optab
);
2255 as_fatal (_("Internal Error: Can't hash %s: %s"),
2259 if (optab
->name
== NULL
)
2261 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2262 core_optab
->start
= optab
;
2267 /* Initialize reg_hash hash table. */
2268 reg_hash
= hash_new ();
2270 const reg_entry
*regtab
;
2271 unsigned int regtab_size
= i386_regtab_size
;
2273 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2275 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2277 as_fatal (_("Internal Error: Can't hash %s: %s"),
2283 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2288 for (c
= 0; c
< 256; c
++)
2293 mnemonic_chars
[c
] = c
;
2294 register_chars
[c
] = c
;
2295 operand_chars
[c
] = c
;
2297 else if (ISLOWER (c
))
2299 mnemonic_chars
[c
] = c
;
2300 register_chars
[c
] = c
;
2301 operand_chars
[c
] = c
;
2303 else if (ISUPPER (c
))
2305 mnemonic_chars
[c
] = TOLOWER (c
);
2306 register_chars
[c
] = mnemonic_chars
[c
];
2307 operand_chars
[c
] = c
;
2310 if (ISALPHA (c
) || ISDIGIT (c
))
2311 identifier_chars
[c
] = c
;
2314 identifier_chars
[c
] = c
;
2315 operand_chars
[c
] = c
;
2320 identifier_chars
['@'] = '@';
2323 identifier_chars
['?'] = '?';
2324 operand_chars
['?'] = '?';
2326 digit_chars
['-'] = '-';
2327 mnemonic_chars
['_'] = '_';
2328 mnemonic_chars
['-'] = '-';
2329 mnemonic_chars
['.'] = '.';
2330 identifier_chars
['_'] = '_';
2331 identifier_chars
['.'] = '.';
2333 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2334 operand_chars
[(unsigned char) *p
] = *p
;
2337 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2340 record_alignment (text_section
, 2);
2341 record_alignment (data_section
, 2);
2342 record_alignment (bss_section
, 2);
2346 if (flag_code
== CODE_64BIT
)
2348 x86_dwarf2_return_column
= 16;
2349 x86_cie_data_alignment
= -8;
2353 x86_dwarf2_return_column
= 8;
2354 x86_cie_data_alignment
= -4;
2359 i386_print_statistics (FILE *file
)
2361 hash_print_statistics (file
, "i386 opcode", op_hash
);
2362 hash_print_statistics (file
, "i386 register", reg_hash
);
2367 /* Debugging routines for md_assemble. */
2368 static void pte (insn_template
*);
2369 static void pt (i386_operand_type
);
2370 static void pe (expressionS
*);
2371 static void ps (symbolS
*);
2374 pi (char *line
, i386_insn
*x
)
2378 fprintf (stdout
, "%s: template ", line
);
2380 fprintf (stdout
, " address: base %s index %s scale %x\n",
2381 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2382 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2383 x
->log2_scale_factor
);
2384 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2385 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2386 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2387 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2388 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2389 (x
->rex
& REX_W
) != 0,
2390 (x
->rex
& REX_R
) != 0,
2391 (x
->rex
& REX_X
) != 0,
2392 (x
->rex
& REX_B
) != 0);
2393 for (j
= 0; j
< x
->operands
; j
++)
2395 fprintf (stdout
, " #%d: ", j
+ 1);
2397 fprintf (stdout
, "\n");
2398 if (x
->types
[j
].bitfield
.reg8
2399 || x
->types
[j
].bitfield
.reg16
2400 || x
->types
[j
].bitfield
.reg32
2401 || x
->types
[j
].bitfield
.reg64
2402 || x
->types
[j
].bitfield
.regmmx
2403 || x
->types
[j
].bitfield
.regxmm
2404 || x
->types
[j
].bitfield
.regymm
2405 || x
->types
[j
].bitfield
.sreg2
2406 || x
->types
[j
].bitfield
.sreg3
2407 || x
->types
[j
].bitfield
.control
2408 || x
->types
[j
].bitfield
.debug
2409 || x
->types
[j
].bitfield
.test
)
2410 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2411 if (operand_type_check (x
->types
[j
], imm
))
2413 if (operand_type_check (x
->types
[j
], disp
))
2414 pe (x
->op
[j
].disps
);
2419 pte (insn_template
*t
)
2422 fprintf (stdout
, " %d operands ", t
->operands
);
2423 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2424 if (t
->extension_opcode
!= None
)
2425 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2426 if (t
->opcode_modifier
.d
)
2427 fprintf (stdout
, "D");
2428 if (t
->opcode_modifier
.w
)
2429 fprintf (stdout
, "W");
2430 fprintf (stdout
, "\n");
2431 for (j
= 0; j
< t
->operands
; j
++)
2433 fprintf (stdout
, " #%d type ", j
+ 1);
2434 pt (t
->operand_types
[j
]);
2435 fprintf (stdout
, "\n");
2442 fprintf (stdout
, " operation %d\n", e
->X_op
);
2443 fprintf (stdout
, " add_number %ld (%lx)\n",
2444 (long) e
->X_add_number
, (long) e
->X_add_number
);
2445 if (e
->X_add_symbol
)
2447 fprintf (stdout
, " add_symbol ");
2448 ps (e
->X_add_symbol
);
2449 fprintf (stdout
, "\n");
2453 fprintf (stdout
, " op_symbol ");
2454 ps (e
->X_op_symbol
);
2455 fprintf (stdout
, "\n");
2462 fprintf (stdout
, "%s type %s%s",
2464 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2465 segment_name (S_GET_SEGMENT (s
)));
2468 static struct type_name
2470 i386_operand_type mask
;
2473 const type_names
[] =
2475 { OPERAND_TYPE_REG8
, "r8" },
2476 { OPERAND_TYPE_REG16
, "r16" },
2477 { OPERAND_TYPE_REG32
, "r32" },
2478 { OPERAND_TYPE_REG64
, "r64" },
2479 { OPERAND_TYPE_IMM8
, "i8" },
2480 { OPERAND_TYPE_IMM8
, "i8s" },
2481 { OPERAND_TYPE_IMM16
, "i16" },
2482 { OPERAND_TYPE_IMM32
, "i32" },
2483 { OPERAND_TYPE_IMM32S
, "i32s" },
2484 { OPERAND_TYPE_IMM64
, "i64" },
2485 { OPERAND_TYPE_IMM1
, "i1" },
2486 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2487 { OPERAND_TYPE_DISP8
, "d8" },
2488 { OPERAND_TYPE_DISP16
, "d16" },
2489 { OPERAND_TYPE_DISP32
, "d32" },
2490 { OPERAND_TYPE_DISP32S
, "d32s" },
2491 { OPERAND_TYPE_DISP64
, "d64" },
2492 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2493 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2494 { OPERAND_TYPE_CONTROL
, "control reg" },
2495 { OPERAND_TYPE_TEST
, "test reg" },
2496 { OPERAND_TYPE_DEBUG
, "debug reg" },
2497 { OPERAND_TYPE_FLOATREG
, "FReg" },
2498 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2499 { OPERAND_TYPE_SREG2
, "SReg2" },
2500 { OPERAND_TYPE_SREG3
, "SReg3" },
2501 { OPERAND_TYPE_ACC
, "Acc" },
2502 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2503 { OPERAND_TYPE_REGMMX
, "rMMX" },
2504 { OPERAND_TYPE_REGXMM
, "rXMM" },
2505 { OPERAND_TYPE_REGYMM
, "rYMM" },
2506 { OPERAND_TYPE_ESSEG
, "es" },
2510 pt (i386_operand_type t
)
2513 i386_operand_type a
;
2515 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2517 a
= operand_type_and (t
, type_names
[j
].mask
);
2518 if (!operand_type_all_zero (&a
))
2519 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2524 #endif /* DEBUG386 */
2526 static bfd_reloc_code_real_type
2527 reloc (unsigned int size
,
2530 bfd_reloc_code_real_type other
)
2532 if (other
!= NO_RELOC
)
2534 reloc_howto_type
*rel
;
2539 case BFD_RELOC_X86_64_GOT32
:
2540 return BFD_RELOC_X86_64_GOT64
;
2542 case BFD_RELOC_X86_64_PLTOFF64
:
2543 return BFD_RELOC_X86_64_PLTOFF64
;
2545 case BFD_RELOC_X86_64_GOTPC32
:
2546 other
= BFD_RELOC_X86_64_GOTPC64
;
2548 case BFD_RELOC_X86_64_GOTPCREL
:
2549 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2551 case BFD_RELOC_X86_64_TPOFF32
:
2552 other
= BFD_RELOC_X86_64_TPOFF64
;
2554 case BFD_RELOC_X86_64_DTPOFF32
:
2555 other
= BFD_RELOC_X86_64_DTPOFF64
;
2561 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2562 if (size
== 4 && flag_code
!= CODE_64BIT
)
2565 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2567 as_bad (_("unknown relocation (%u)"), other
);
2568 else if (size
!= bfd_get_reloc_size (rel
))
2569 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2570 bfd_get_reloc_size (rel
),
2572 else if (pcrel
&& !rel
->pc_relative
)
2573 as_bad (_("non-pc-relative relocation for pc-relative field"));
2574 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2576 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2578 as_bad (_("relocated field and relocation type differ in signedness"));
2587 as_bad (_("there are no unsigned pc-relative relocations"));
2590 case 1: return BFD_RELOC_8_PCREL
;
2591 case 2: return BFD_RELOC_16_PCREL
;
2592 case 4: return BFD_RELOC_32_PCREL
;
2593 case 8: return BFD_RELOC_64_PCREL
;
2595 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2602 case 4: return BFD_RELOC_X86_64_32S
;
2607 case 1: return BFD_RELOC_8
;
2608 case 2: return BFD_RELOC_16
;
2609 case 4: return BFD_RELOC_32
;
2610 case 8: return BFD_RELOC_64
;
2612 as_bad (_("cannot do %s %u byte relocation"),
2613 sign
> 0 ? "signed" : "unsigned", size
);
2619 /* Here we decide which fixups can be adjusted to make them relative to
2620 the beginning of the section instead of the symbol. Basically we need
2621 to make sure that the dynamic relocations are done correctly, so in
2622 some cases we force the original symbol to be used. */
2625 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2627 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2631 /* Don't adjust pc-relative references to merge sections in 64-bit
2633 if (use_rela_relocations
2634 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2638 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2639 and changed later by validate_fix. */
2640 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2641 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2644 /* adjust_reloc_syms doesn't know about the GOT. */
2645 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2646 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2647 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2648 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2649 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2650 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2651 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2652 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2653 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2654 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2655 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2656 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2657 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2658 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2659 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2660 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2661 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2662 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2663 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2664 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2665 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2666 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2667 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2668 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2669 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2670 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2671 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2672 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2679 intel_float_operand (const char *mnemonic
)
2681 /* Note that the value returned is meaningful only for opcodes with (memory)
2682 operands, hence the code here is free to improperly handle opcodes that
2683 have no operands (for better performance and smaller code). */
2685 if (mnemonic
[0] != 'f')
2686 return 0; /* non-math */
2688 switch (mnemonic
[1])
2690 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2691 the fs segment override prefix not currently handled because no
2692 call path can make opcodes without operands get here */
2694 return 2 /* integer op */;
2696 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2697 return 3; /* fldcw/fldenv */
2700 if (mnemonic
[2] != 'o' /* fnop */)
2701 return 3; /* non-waiting control op */
2704 if (mnemonic
[2] == 's')
2705 return 3; /* frstor/frstpm */
2708 if (mnemonic
[2] == 'a')
2709 return 3; /* fsave */
2710 if (mnemonic
[2] == 't')
2712 switch (mnemonic
[3])
2714 case 'c': /* fstcw */
2715 case 'd': /* fstdw */
2716 case 'e': /* fstenv */
2717 case 's': /* fsts[gw] */
2723 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2724 return 0; /* fxsave/fxrstor are not really math ops */
2731 /* Build the VEX prefix. */
2734 build_vex_prefix (const insn_template
*t
)
2736 unsigned int register_specifier
;
2737 unsigned int implied_prefix
;
2738 unsigned int vector_length
;
2740 /* Check register specifier. */
2741 if (i
.vex
.register_specifier
)
2743 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2744 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2745 register_specifier
+= 8;
2746 register_specifier
= ~register_specifier
& 0xf;
2749 register_specifier
= 0xf;
2751 /* Use 2-byte VEX prefix by swappping destination and source
2754 && i
.operands
== i
.reg_operands
2755 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2756 && i
.tm
.opcode_modifier
.s
2759 unsigned int xchg
= i
.operands
- 1;
2760 union i386_op temp_op
;
2761 i386_operand_type temp_type
;
2763 temp_type
= i
.types
[xchg
];
2764 i
.types
[xchg
] = i
.types
[0];
2765 i
.types
[0] = temp_type
;
2766 temp_op
= i
.op
[xchg
];
2767 i
.op
[xchg
] = i
.op
[0];
2770 gas_assert (i
.rm
.mode
== 3);
2774 i
.rm
.regmem
= i
.rm
.reg
;
2777 /* Use the next insn. */
2781 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2782 vector_length
= avxscalar
;
2784 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2786 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2791 case DATA_PREFIX_OPCODE
:
2794 case REPE_PREFIX_OPCODE
:
2797 case REPNE_PREFIX_OPCODE
:
2804 /* Use 2-byte VEX prefix if possible. */
2805 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2806 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2808 /* 2-byte VEX prefix. */
2812 i
.vex
.bytes
[0] = 0xc5;
2814 /* Check the REX.R bit. */
2815 r
= (i
.rex
& REX_R
) ? 0 : 1;
2816 i
.vex
.bytes
[1] = (r
<< 7
2817 | register_specifier
<< 3
2818 | vector_length
<< 2
2823 /* 3-byte VEX prefix. */
2828 switch (i
.tm
.opcode_modifier
.vexopcode
)
2832 i
.vex
.bytes
[0] = 0xc4;
2836 i
.vex
.bytes
[0] = 0xc4;
2840 i
.vex
.bytes
[0] = 0xc4;
2844 i
.vex
.bytes
[0] = 0x8f;
2848 i
.vex
.bytes
[0] = 0x8f;
2852 i
.vex
.bytes
[0] = 0x8f;
2858 /* The high 3 bits of the second VEX byte are 1's compliment
2859 of RXB bits from REX. */
2860 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2862 /* Check the REX.W bit. */
2863 w
= (i
.rex
& REX_W
) ? 1 : 0;
2864 if (i
.tm
.opcode_modifier
.vexw
)
2869 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2873 i
.vex
.bytes
[2] = (w
<< 7
2874 | register_specifier
<< 3
2875 | vector_length
<< 2
2881 process_immext (void)
2885 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2887 /* SSE3 Instructions have the fixed operands with an opcode
2888 suffix which is coded in the same place as an 8-bit immediate
2889 field would be. Here we check those operands and remove them
2893 for (x
= 0; x
< i
.operands
; x
++)
2894 if (i
.op
[x
].regs
->reg_num
!= x
)
2895 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2896 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2902 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2903 which is coded in the same place as an 8-bit immediate field
2904 would be. Here we fake an 8-bit immediate operand from the
2905 opcode suffix stored in tm.extension_opcode.
2907 AVX instructions also use this encoding, for some of
2908 3 argument instructions. */
2910 gas_assert (i
.imm_operands
== 0
2912 || (i
.tm
.opcode_modifier
.vex
2913 && i
.operands
<= 4)));
2915 exp
= &im_expressions
[i
.imm_operands
++];
2916 i
.op
[i
.operands
].imms
= exp
;
2917 i
.types
[i
.operands
] = imm8
;
2919 exp
->X_op
= O_constant
;
2920 exp
->X_add_number
= i
.tm
.extension_opcode
;
2921 i
.tm
.extension_opcode
= None
;
2924 /* This is the guts of the machine-dependent assembler. LINE points to a
2925 machine dependent instruction. This function is supposed to emit
2926 the frags/bytes it assembles to. */
2929 md_assemble (char *line
)
2932 char mnemonic
[MAX_MNEM_SIZE
];
2933 const insn_template
*t
;
2935 /* Initialize globals. */
2936 memset (&i
, '\0', sizeof (i
));
2937 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2938 i
.reloc
[j
] = NO_RELOC
;
2939 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2940 memset (im_expressions
, '\0', sizeof (im_expressions
));
2941 save_stack_p
= save_stack
;
2943 /* First parse an instruction mnemonic & call i386_operand for the operands.
2944 We assume that the scrubber has arranged it so that line[0] is the valid
2945 start of a (possibly prefixed) mnemonic. */
2947 line
= parse_insn (line
, mnemonic
);
2951 line
= parse_operands (line
, mnemonic
);
2956 /* Now we've parsed the mnemonic into a set of templates, and have the
2957 operands at hand. */
2959 /* All intel opcodes have reversed operands except for "bound" and
2960 "enter". We also don't reverse intersegment "jmp" and "call"
2961 instructions with 2 immediate operands so that the immediate segment
2962 precedes the offset, as it does when in AT&T mode. */
2965 && (strcmp (mnemonic
, "bound") != 0)
2966 && (strcmp (mnemonic
, "invlpga") != 0)
2967 && !(operand_type_check (i
.types
[0], imm
)
2968 && operand_type_check (i
.types
[1], imm
)))
2971 /* The order of the immediates should be reversed
2972 for 2 immediates extrq and insertq instructions */
2973 if (i
.imm_operands
== 2
2974 && (strcmp (mnemonic
, "extrq") == 0
2975 || strcmp (mnemonic
, "insertq") == 0))
2976 swap_2_operands (0, 1);
2981 /* Don't optimize displacement for movabs since it only takes 64bit
2984 && (flag_code
!= CODE_64BIT
2985 || strcmp (mnemonic
, "movabs") != 0))
2988 /* Next, we find a template that matches the given insn,
2989 making sure the overlap of the given operands types is consistent
2990 with the template operand types. */
2992 if (!(t
= match_template ()))
2995 if (sse_check
!= sse_check_none
2996 && !i
.tm
.opcode_modifier
.noavx
2997 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2998 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2999 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3000 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3001 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3002 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3004 (sse_check
== sse_check_warning
3006 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3009 /* Zap movzx and movsx suffix. The suffix has been set from
3010 "word ptr" or "byte ptr" on the source operand in Intel syntax
3011 or extracted from mnemonic in AT&T syntax. But we'll use
3012 the destination register to choose the suffix for encoding. */
3013 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3015 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3016 there is no suffix, the default will be byte extension. */
3017 if (i
.reg_operands
!= 2
3020 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3025 if (i
.tm
.opcode_modifier
.fwait
)
3026 if (!add_prefix (FWAIT_OPCODE
))
3029 /* Check for lock without a lockable instruction. Destination operand
3030 must be memory unless it is xchg (0x86). */
3031 if (i
.prefix
[LOCK_PREFIX
]
3032 && (!i
.tm
.opcode_modifier
.islockable
3033 || i
.mem_operands
== 0
3034 || (i
.tm
.base_opcode
!= 0x86
3035 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3037 as_bad (_("expecting lockable instruction after `lock'"));
3041 /* Check string instruction segment overrides. */
3042 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3044 if (!check_string ())
3046 i
.disp_operands
= 0;
3049 if (!process_suffix ())
3052 /* Update operand types. */
3053 for (j
= 0; j
< i
.operands
; j
++)
3054 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3056 /* Make still unresolved immediate matches conform to size of immediate
3057 given in i.suffix. */
3058 if (!finalize_imm ())
3061 if (i
.types
[0].bitfield
.imm1
)
3062 i
.imm_operands
= 0; /* kludge for shift insns. */
3064 /* We only need to check those implicit registers for instructions
3065 with 3 operands or less. */
3066 if (i
.operands
<= 3)
3067 for (j
= 0; j
< i
.operands
; j
++)
3068 if (i
.types
[j
].bitfield
.inoutportreg
3069 || i
.types
[j
].bitfield
.shiftcount
3070 || i
.types
[j
].bitfield
.acc
3071 || i
.types
[j
].bitfield
.floatacc
)
3074 /* ImmExt should be processed after SSE2AVX. */
3075 if (!i
.tm
.opcode_modifier
.sse2avx
3076 && i
.tm
.opcode_modifier
.immext
)
3079 /* For insns with operands there are more diddles to do to the opcode. */
3082 if (!process_operands ())
3085 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3087 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3088 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3091 if (i
.tm
.opcode_modifier
.vex
)
3092 build_vex_prefix (t
);
3094 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3095 instructions may define INT_OPCODE as well, so avoid this corner
3096 case for those instructions that use MODRM. */
3097 if (i
.tm
.base_opcode
== INT_OPCODE
3098 && !i
.tm
.opcode_modifier
.modrm
3099 && i
.op
[0].imms
->X_add_number
== 3)
3101 i
.tm
.base_opcode
= INT3_OPCODE
;
3105 if ((i
.tm
.opcode_modifier
.jump
3106 || i
.tm
.opcode_modifier
.jumpbyte
3107 || i
.tm
.opcode_modifier
.jumpdword
)
3108 && i
.op
[0].disps
->X_op
== O_constant
)
3110 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3111 the absolute address given by the constant. Since ix86 jumps and
3112 calls are pc relative, we need to generate a reloc. */
3113 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3114 i
.op
[0].disps
->X_op
= O_symbol
;
3117 if (i
.tm
.opcode_modifier
.rex64
)
3120 /* For 8 bit registers we need an empty rex prefix. Also if the
3121 instruction already has a prefix, we need to convert old
3122 registers to new ones. */
3124 if ((i
.types
[0].bitfield
.reg8
3125 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3126 || (i
.types
[1].bitfield
.reg8
3127 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3128 || ((i
.types
[0].bitfield
.reg8
3129 || i
.types
[1].bitfield
.reg8
)
3134 i
.rex
|= REX_OPCODE
;
3135 for (x
= 0; x
< 2; x
++)
3137 /* Look for 8 bit operand that uses old registers. */
3138 if (i
.types
[x
].bitfield
.reg8
3139 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3141 /* In case it is "hi" register, give up. */
3142 if (i
.op
[x
].regs
->reg_num
> 3)
3143 as_bad (_("can't encode register '%s%s' in an "
3144 "instruction requiring REX prefix."),
3145 register_prefix
, i
.op
[x
].regs
->reg_name
);
3147 /* Otherwise it is equivalent to the extended register.
3148 Since the encoding doesn't change this is merely
3149 cosmetic cleanup for debug output. */
3151 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3157 add_prefix (REX_OPCODE
| i
.rex
);
3159 /* We are ready to output the insn. */
3164 parse_insn (char *line
, char *mnemonic
)
3167 char *token_start
= l
;
3170 const insn_template
*t
;
3173 /* Non-zero if we found a prefix only acceptable with string insns. */
3174 const char *expecting_string_instruction
= NULL
;
3179 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3184 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3186 as_bad (_("no such instruction: `%s'"), token_start
);
3191 if (!is_space_char (*l
)
3192 && *l
!= END_OF_INSN
3194 || (*l
!= PREFIX_SEPARATOR
3197 as_bad (_("invalid character %s in mnemonic"),
3198 output_invalid (*l
));
3201 if (token_start
== l
)
3203 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3204 as_bad (_("expecting prefix; got nothing"));
3206 as_bad (_("expecting mnemonic; got nothing"));
3210 /* Look up instruction (or prefix) via hash table. */
3211 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3213 if (*l
!= END_OF_INSN
3214 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3215 && current_templates
3216 && current_templates
->start
->opcode_modifier
.isprefix
)
3218 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3220 as_bad ((flag_code
!= CODE_64BIT
3221 ? _("`%s' is only supported in 64-bit mode")
3222 : _("`%s' is not supported in 64-bit mode")),
3223 current_templates
->start
->name
);
3226 /* If we are in 16-bit mode, do not allow addr16 or data16.
3227 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3228 if ((current_templates
->start
->opcode_modifier
.size16
3229 || current_templates
->start
->opcode_modifier
.size32
)
3230 && flag_code
!= CODE_64BIT
3231 && (current_templates
->start
->opcode_modifier
.size32
3232 ^ (flag_code
== CODE_16BIT
)))
3234 as_bad (_("redundant %s prefix"),
3235 current_templates
->start
->name
);
3238 /* Add prefix, checking for repeated prefixes. */
3239 switch (add_prefix (current_templates
->start
->base_opcode
))
3244 expecting_string_instruction
= current_templates
->start
->name
;
3249 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3256 if (!current_templates
)
3258 /* Check if we should swap operand in encoding. */
3259 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3265 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3268 if (!current_templates
)
3271 /* See if we can get a match by trimming off a suffix. */
3274 case WORD_MNEM_SUFFIX
:
3275 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3276 i
.suffix
= SHORT_MNEM_SUFFIX
;
3278 case BYTE_MNEM_SUFFIX
:
3279 case QWORD_MNEM_SUFFIX
:
3280 i
.suffix
= mnem_p
[-1];
3282 current_templates
= (const templates
*) hash_find (op_hash
,
3285 case SHORT_MNEM_SUFFIX
:
3286 case LONG_MNEM_SUFFIX
:
3289 i
.suffix
= mnem_p
[-1];
3291 current_templates
= (const templates
*) hash_find (op_hash
,
3300 if (intel_float_operand (mnemonic
) == 1)
3301 i
.suffix
= SHORT_MNEM_SUFFIX
;
3303 i
.suffix
= LONG_MNEM_SUFFIX
;
3305 current_templates
= (const templates
*) hash_find (op_hash
,
3310 if (!current_templates
)
3312 as_bad (_("no such instruction: `%s'"), token_start
);
3317 if (current_templates
->start
->opcode_modifier
.jump
3318 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3320 /* Check for a branch hint. We allow ",pt" and ",pn" for
3321 predict taken and predict not taken respectively.
3322 I'm not sure that branch hints actually do anything on loop
3323 and jcxz insns (JumpByte) for current Pentium4 chips. They
3324 may work in the future and it doesn't hurt to accept them
3326 if (l
[0] == ',' && l
[1] == 'p')
3330 if (!add_prefix (DS_PREFIX_OPCODE
))
3334 else if (l
[2] == 'n')
3336 if (!add_prefix (CS_PREFIX_OPCODE
))
3342 /* Any other comma loses. */
3345 as_bad (_("invalid character %s in mnemonic"),
3346 output_invalid (*l
));
3350 /* Check if instruction is supported on specified architecture. */
3352 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3354 supported
|= cpu_flags_match (t
);
3355 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3359 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3361 as_bad (flag_code
== CODE_64BIT
3362 ? _("`%s' is not supported in 64-bit mode")
3363 : _("`%s' is only supported in 64-bit mode"),
3364 current_templates
->start
->name
);
3367 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3369 as_bad (_("`%s' is not supported on `%s%s'"),
3370 current_templates
->start
->name
,
3371 cpu_arch_name
? cpu_arch_name
: default_arch
,
3372 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3377 if (!cpu_arch_flags
.bitfield
.cpui386
3378 && (flag_code
!= CODE_16BIT
))
3380 as_warn (_("use .code16 to ensure correct addressing mode"));
3383 /* Check for rep/repne without a string instruction. */
3384 if (expecting_string_instruction
)
3386 static templates override
;
3388 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3389 if (t
->opcode_modifier
.isstring
)
3391 if (t
>= current_templates
->end
)
3393 as_bad (_("expecting string instruction after `%s'"),
3394 expecting_string_instruction
);
3397 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3398 if (!t
->opcode_modifier
.isstring
)
3401 current_templates
= &override
;
3408 parse_operands (char *l
, const char *mnemonic
)
3412 /* 1 if operand is pending after ','. */
3413 unsigned int expecting_operand
= 0;
3415 /* Non-zero if operand parens not balanced. */
3416 unsigned int paren_not_balanced
;
3418 while (*l
!= END_OF_INSN
)
3420 /* Skip optional white space before operand. */
3421 if (is_space_char (*l
))
3423 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3425 as_bad (_("invalid character %s before operand %d"),
3426 output_invalid (*l
),
3430 token_start
= l
; /* after white space */
3431 paren_not_balanced
= 0;
3432 while (paren_not_balanced
|| *l
!= ',')
3434 if (*l
== END_OF_INSN
)
3436 if (paren_not_balanced
)
3439 as_bad (_("unbalanced parenthesis in operand %d."),
3442 as_bad (_("unbalanced brackets in operand %d."),
3447 break; /* we are done */
3449 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3451 as_bad (_("invalid character %s in operand %d"),
3452 output_invalid (*l
),
3459 ++paren_not_balanced
;
3461 --paren_not_balanced
;
3466 ++paren_not_balanced
;
3468 --paren_not_balanced
;
3472 if (l
!= token_start
)
3473 { /* Yes, we've read in another operand. */
3474 unsigned int operand_ok
;
3475 this_operand
= i
.operands
++;
3476 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3477 if (i
.operands
> MAX_OPERANDS
)
3479 as_bad (_("spurious operands; (%d operands/instruction max)"),
3483 /* Now parse operand adding info to 'i' as we go along. */
3484 END_STRING_AND_SAVE (l
);
3488 i386_intel_operand (token_start
,
3489 intel_float_operand (mnemonic
));
3491 operand_ok
= i386_att_operand (token_start
);
3493 RESTORE_END_STRING (l
);
3499 if (expecting_operand
)
3501 expecting_operand_after_comma
:
3502 as_bad (_("expecting operand after ','; got nothing"));
3507 as_bad (_("expecting operand before ','; got nothing"));
3512 /* Now *l must be either ',' or END_OF_INSN. */
3515 if (*++l
== END_OF_INSN
)
3517 /* Just skip it, if it's \n complain. */
3518 goto expecting_operand_after_comma
;
3520 expecting_operand
= 1;
3527 swap_2_operands (int xchg1
, int xchg2
)
3529 union i386_op temp_op
;
3530 i386_operand_type temp_type
;
3531 enum bfd_reloc_code_real temp_reloc
;
3533 temp_type
= i
.types
[xchg2
];
3534 i
.types
[xchg2
] = i
.types
[xchg1
];
3535 i
.types
[xchg1
] = temp_type
;
3536 temp_op
= i
.op
[xchg2
];
3537 i
.op
[xchg2
] = i
.op
[xchg1
];
3538 i
.op
[xchg1
] = temp_op
;
3539 temp_reloc
= i
.reloc
[xchg2
];
3540 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3541 i
.reloc
[xchg1
] = temp_reloc
;
3545 swap_operands (void)
3551 swap_2_operands (1, i
.operands
- 2);
3554 swap_2_operands (0, i
.operands
- 1);
3560 if (i
.mem_operands
== 2)
3562 const seg_entry
*temp_seg
;
3563 temp_seg
= i
.seg
[0];
3564 i
.seg
[0] = i
.seg
[1];
3565 i
.seg
[1] = temp_seg
;
3569 /* Try to ensure constant immediates are represented in the smallest
3574 char guess_suffix
= 0;
3578 guess_suffix
= i
.suffix
;
3579 else if (i
.reg_operands
)
3581 /* Figure out a suffix from the last register operand specified.
3582 We can't do this properly yet, ie. excluding InOutPortReg,
3583 but the following works for instructions with immediates.
3584 In any case, we can't set i.suffix yet. */
3585 for (op
= i
.operands
; --op
>= 0;)
3586 if (i
.types
[op
].bitfield
.reg8
)
3588 guess_suffix
= BYTE_MNEM_SUFFIX
;
3591 else if (i
.types
[op
].bitfield
.reg16
)
3593 guess_suffix
= WORD_MNEM_SUFFIX
;
3596 else if (i
.types
[op
].bitfield
.reg32
)
3598 guess_suffix
= LONG_MNEM_SUFFIX
;
3601 else if (i
.types
[op
].bitfield
.reg64
)
3603 guess_suffix
= QWORD_MNEM_SUFFIX
;
3607 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3608 guess_suffix
= WORD_MNEM_SUFFIX
;
3610 for (op
= i
.operands
; --op
>= 0;)
3611 if (operand_type_check (i
.types
[op
], imm
))
3613 switch (i
.op
[op
].imms
->X_op
)
3616 /* If a suffix is given, this operand may be shortened. */
3617 switch (guess_suffix
)
3619 case LONG_MNEM_SUFFIX
:
3620 i
.types
[op
].bitfield
.imm32
= 1;
3621 i
.types
[op
].bitfield
.imm64
= 1;
3623 case WORD_MNEM_SUFFIX
:
3624 i
.types
[op
].bitfield
.imm16
= 1;
3625 i
.types
[op
].bitfield
.imm32
= 1;
3626 i
.types
[op
].bitfield
.imm32s
= 1;
3627 i
.types
[op
].bitfield
.imm64
= 1;
3629 case BYTE_MNEM_SUFFIX
:
3630 i
.types
[op
].bitfield
.imm8
= 1;
3631 i
.types
[op
].bitfield
.imm8s
= 1;
3632 i
.types
[op
].bitfield
.imm16
= 1;
3633 i
.types
[op
].bitfield
.imm32
= 1;
3634 i
.types
[op
].bitfield
.imm32s
= 1;
3635 i
.types
[op
].bitfield
.imm64
= 1;
3639 /* If this operand is at most 16 bits, convert it
3640 to a signed 16 bit number before trying to see
3641 whether it will fit in an even smaller size.
3642 This allows a 16-bit operand such as $0xffe0 to
3643 be recognised as within Imm8S range. */
3644 if ((i
.types
[op
].bitfield
.imm16
)
3645 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3647 i
.op
[op
].imms
->X_add_number
=
3648 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3650 if ((i
.types
[op
].bitfield
.imm32
)
3651 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3654 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3655 ^ ((offsetT
) 1 << 31))
3656 - ((offsetT
) 1 << 31));
3659 = operand_type_or (i
.types
[op
],
3660 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3662 /* We must avoid matching of Imm32 templates when 64bit
3663 only immediate is available. */
3664 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3665 i
.types
[op
].bitfield
.imm32
= 0;
3672 /* Symbols and expressions. */
3674 /* Convert symbolic operand to proper sizes for matching, but don't
3675 prevent matching a set of insns that only supports sizes other
3676 than those matching the insn suffix. */
3678 i386_operand_type mask
, allowed
;
3679 const insn_template
*t
;
3681 operand_type_set (&mask
, 0);
3682 operand_type_set (&allowed
, 0);
3684 for (t
= current_templates
->start
;
3685 t
< current_templates
->end
;
3687 allowed
= operand_type_or (allowed
,
3688 t
->operand_types
[op
]);
3689 switch (guess_suffix
)
3691 case QWORD_MNEM_SUFFIX
:
3692 mask
.bitfield
.imm64
= 1;
3693 mask
.bitfield
.imm32s
= 1;
3695 case LONG_MNEM_SUFFIX
:
3696 mask
.bitfield
.imm32
= 1;
3698 case WORD_MNEM_SUFFIX
:
3699 mask
.bitfield
.imm16
= 1;
3701 case BYTE_MNEM_SUFFIX
:
3702 mask
.bitfield
.imm8
= 1;
3707 allowed
= operand_type_and (mask
, allowed
);
3708 if (!operand_type_all_zero (&allowed
))
3709 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3716 /* Try to use the smallest displacement type too. */
3718 optimize_disp (void)
3722 for (op
= i
.operands
; --op
>= 0;)
3723 if (operand_type_check (i
.types
[op
], disp
))
3725 if (i
.op
[op
].disps
->X_op
== O_constant
)
3727 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3729 if (i
.types
[op
].bitfield
.disp16
3730 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3732 /* If this operand is at most 16 bits, convert
3733 to a signed 16 bit number and don't use 64bit
3735 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3736 i
.types
[op
].bitfield
.disp64
= 0;
3738 if (i
.types
[op
].bitfield
.disp32
3739 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3741 /* If this operand is at most 32 bits, convert
3742 to a signed 32 bit number and don't use 64bit
3744 op_disp
&= (((offsetT
) 2 << 31) - 1);
3745 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3746 i
.types
[op
].bitfield
.disp64
= 0;
3748 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3750 i
.types
[op
].bitfield
.disp8
= 0;
3751 i
.types
[op
].bitfield
.disp16
= 0;
3752 i
.types
[op
].bitfield
.disp32
= 0;
3753 i
.types
[op
].bitfield
.disp32s
= 0;
3754 i
.types
[op
].bitfield
.disp64
= 0;
3758 else if (flag_code
== CODE_64BIT
)
3760 if (fits_in_signed_long (op_disp
))
3762 i
.types
[op
].bitfield
.disp64
= 0;
3763 i
.types
[op
].bitfield
.disp32s
= 1;
3765 if (i
.prefix
[ADDR_PREFIX
]
3766 && fits_in_unsigned_long (op_disp
))
3767 i
.types
[op
].bitfield
.disp32
= 1;
3769 if ((i
.types
[op
].bitfield
.disp32
3770 || i
.types
[op
].bitfield
.disp32s
3771 || i
.types
[op
].bitfield
.disp16
)
3772 && fits_in_signed_byte (op_disp
))
3773 i
.types
[op
].bitfield
.disp8
= 1;
3775 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3776 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3778 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3779 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3780 i
.types
[op
].bitfield
.disp8
= 0;
3781 i
.types
[op
].bitfield
.disp16
= 0;
3782 i
.types
[op
].bitfield
.disp32
= 0;
3783 i
.types
[op
].bitfield
.disp32s
= 0;
3784 i
.types
[op
].bitfield
.disp64
= 0;
3787 /* We only support 64bit displacement on constants. */
3788 i
.types
[op
].bitfield
.disp64
= 0;
3792 /* Check if operands are valid for the instruction. Update VEX
3796 VEX_check_operands (const insn_template
*t
)
3798 if (!t
->opcode_modifier
.vex
)
3801 /* Only check VEX_Imm4, which must be the first operand. */
3802 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3804 if (i
.op
[0].imms
->X_op
!= O_constant
3805 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3811 /* Turn off Imm8 so that update_imm won't complain. */
3812 i
.types
[0] = vec_imm4
;
3818 static const insn_template
*
3819 match_template (void)
3821 /* Points to template once we've found it. */
3822 const insn_template
*t
;
3823 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3824 i386_operand_type overlap4
;
3825 unsigned int found_reverse_match
;
3826 i386_opcode_modifier suffix_check
;
3827 i386_operand_type operand_types
[MAX_OPERANDS
];
3828 int addr_prefix_disp
;
3830 unsigned int found_cpu_match
;
3831 unsigned int check_register
;
3833 #if MAX_OPERANDS != 5
3834 # error "MAX_OPERANDS must be 5."
3837 found_reverse_match
= 0;
3838 addr_prefix_disp
= -1;
3840 memset (&suffix_check
, 0, sizeof (suffix_check
));
3841 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3842 suffix_check
.no_bsuf
= 1;
3843 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3844 suffix_check
.no_wsuf
= 1;
3845 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3846 suffix_check
.no_ssuf
= 1;
3847 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3848 suffix_check
.no_lsuf
= 1;
3849 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3850 suffix_check
.no_qsuf
= 1;
3851 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3852 suffix_check
.no_ldsuf
= 1;
3854 /* Must have right number of operands. */
3855 i
.error
= number_of_operands_mismatch
;
3857 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3859 addr_prefix_disp
= -1;
3861 if (i
.operands
!= t
->operands
)
3864 /* Check processor support. */
3865 i
.error
= unsupported
;
3866 found_cpu_match
= (cpu_flags_match (t
)
3867 == CPU_FLAGS_PERFECT_MATCH
);
3868 if (!found_cpu_match
)
3871 /* Check old gcc support. */
3872 i
.error
= old_gcc_only
;
3873 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3876 /* Check AT&T mnemonic. */
3877 i
.error
= unsupported_with_intel_mnemonic
;
3878 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3881 /* Check AT&T/Intel syntax. */
3882 i
.error
= unsupported_syntax
;
3883 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3884 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3887 /* Check the suffix, except for some instructions in intel mode. */
3888 i
.error
= invalid_instruction_suffix
;
3889 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3890 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3891 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3892 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3893 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3894 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3895 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3898 if (!operand_size_match (t
))
3901 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3902 operand_types
[j
] = t
->operand_types
[j
];
3904 /* In general, don't allow 64-bit operands in 32-bit mode. */
3905 if (i
.suffix
== QWORD_MNEM_SUFFIX
3906 && flag_code
!= CODE_64BIT
3908 ? (!t
->opcode_modifier
.ignoresize
3909 && !intel_float_operand (t
->name
))
3910 : intel_float_operand (t
->name
) != 2)
3911 && ((!operand_types
[0].bitfield
.regmmx
3912 && !operand_types
[0].bitfield
.regxmm
3913 && !operand_types
[0].bitfield
.regymm
)
3914 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3915 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3916 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3917 && (t
->base_opcode
!= 0x0fc7
3918 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3921 /* In general, don't allow 32-bit operands on pre-386. */
3922 else if (i
.suffix
== LONG_MNEM_SUFFIX
3923 && !cpu_arch_flags
.bitfield
.cpui386
3925 ? (!t
->opcode_modifier
.ignoresize
3926 && !intel_float_operand (t
->name
))
3927 : intel_float_operand (t
->name
) != 2)
3928 && ((!operand_types
[0].bitfield
.regmmx
3929 && !operand_types
[0].bitfield
.regxmm
)
3930 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3931 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3934 /* Do not verify operands when there are none. */
3938 /* We've found a match; break out of loop. */
3942 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3943 into Disp32/Disp16/Disp32 operand. */
3944 if (i
.prefix
[ADDR_PREFIX
] != 0)
3946 /* There should be only one Disp operand. */
3950 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3952 if (operand_types
[j
].bitfield
.disp16
)
3954 addr_prefix_disp
= j
;
3955 operand_types
[j
].bitfield
.disp32
= 1;
3956 operand_types
[j
].bitfield
.disp16
= 0;
3962 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3964 if (operand_types
[j
].bitfield
.disp32
)
3966 addr_prefix_disp
= j
;
3967 operand_types
[j
].bitfield
.disp32
= 0;
3968 operand_types
[j
].bitfield
.disp16
= 1;
3974 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3976 if (operand_types
[j
].bitfield
.disp64
)
3978 addr_prefix_disp
= j
;
3979 operand_types
[j
].bitfield
.disp64
= 0;
3980 operand_types
[j
].bitfield
.disp32
= 1;
3988 /* We check register size only if size of operands can be
3989 encoded the canonical way. */
3990 check_register
= t
->opcode_modifier
.w
;
3991 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3992 switch (t
->operands
)
3995 if (!operand_type_match (overlap0
, i
.types
[0]))
3999 /* xchg %eax, %eax is a special case. It is an aliase for nop
4000 only in 32bit mode and we can use opcode 0x90. In 64bit
4001 mode, we can't use 0x90 for xchg %eax, %eax since it should
4002 zero-extend %eax to %rax. */
4003 if (flag_code
== CODE_64BIT
4004 && t
->base_opcode
== 0x90
4005 && operand_type_equal (&i
.types
[0], &acc32
)
4006 && operand_type_equal (&i
.types
[1], &acc32
))
4010 /* If we swap operand in encoding, we either match
4011 the next one or reverse direction of operands. */
4012 if (t
->opcode_modifier
.s
)
4014 else if (t
->opcode_modifier
.d
)
4019 /* If we swap operand in encoding, we match the next one. */
4020 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4024 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4025 if (!operand_type_match (overlap0
, i
.types
[0])
4026 || !operand_type_match (overlap1
, i
.types
[1])
4028 && !operand_type_register_match (overlap0
, i
.types
[0],
4030 overlap1
, i
.types
[1],
4033 /* Check if other direction is valid ... */
4034 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4038 /* Try reversing direction of operands. */
4039 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4040 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4041 if (!operand_type_match (overlap0
, i
.types
[0])
4042 || !operand_type_match (overlap1
, i
.types
[1])
4044 && !operand_type_register_match (overlap0
,
4051 /* Does not match either direction. */
4054 /* found_reverse_match holds which of D or FloatDR
4056 if (t
->opcode_modifier
.d
)
4057 found_reverse_match
= Opcode_D
;
4058 else if (t
->opcode_modifier
.floatd
)
4059 found_reverse_match
= Opcode_FloatD
;
4061 found_reverse_match
= 0;
4062 if (t
->opcode_modifier
.floatr
)
4063 found_reverse_match
|= Opcode_FloatR
;
4067 /* Found a forward 2 operand match here. */
4068 switch (t
->operands
)
4071 overlap4
= operand_type_and (i
.types
[4],
4074 overlap3
= operand_type_and (i
.types
[3],
4077 overlap2
= operand_type_and (i
.types
[2],
4082 switch (t
->operands
)
4085 if (!operand_type_match (overlap4
, i
.types
[4])
4086 || !operand_type_register_match (overlap3
,
4094 if (!operand_type_match (overlap3
, i
.types
[3])
4096 && !operand_type_register_match (overlap2
,
4104 /* Here we make use of the fact that there are no
4105 reverse match 3 operand instructions, and all 3
4106 operand instructions only need to be checked for
4107 register consistency between operands 2 and 3. */
4108 if (!operand_type_match (overlap2
, i
.types
[2])
4110 && !operand_type_register_match (overlap1
,
4120 /* Found either forward/reverse 2, 3 or 4 operand match here:
4121 slip through to break. */
4123 if (!found_cpu_match
)
4125 found_reverse_match
= 0;
4129 /* Check if VEX operands are valid. */
4130 if (VEX_check_operands (t
))
4133 /* We've found a match; break out of loop. */
4137 if (t
== current_templates
->end
)
4139 /* We found no match. */
4140 const char *err_msg
;
4145 case operand_size_mismatch
:
4146 err_msg
= _("operand size mismatch");
4148 case operand_type_mismatch
:
4149 err_msg
= _("operand type mismatch");
4151 case register_type_mismatch
:
4152 err_msg
= _("register type mismatch");
4154 case number_of_operands_mismatch
:
4155 err_msg
= _("number of operands mismatch");
4157 case invalid_instruction_suffix
:
4158 err_msg
= _("invalid instruction suffix");
4161 err_msg
= _("Imm4 isn't the first operand");
4164 err_msg
= _("only supported with old gcc");
4166 case unsupported_with_intel_mnemonic
:
4167 err_msg
= _("unsupported with Intel mnemonic");
4169 case unsupported_syntax
:
4170 err_msg
= _("unsupported syntax");
4173 err_msg
= _("unsupported");
4176 as_bad (_("%s for `%s'"), err_msg
,
4177 current_templates
->start
->name
);
4181 if (!quiet_warnings
)
4184 && (i
.types
[0].bitfield
.jumpabsolute
4185 != operand_types
[0].bitfield
.jumpabsolute
))
4187 as_warn (_("indirect %s without `*'"), t
->name
);
4190 if (t
->opcode_modifier
.isprefix
4191 && t
->opcode_modifier
.ignoresize
)
4193 /* Warn them that a data or address size prefix doesn't
4194 affect assembly of the next line of code. */
4195 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4199 /* Copy the template we found. */
4202 if (addr_prefix_disp
!= -1)
4203 i
.tm
.operand_types
[addr_prefix_disp
]
4204 = operand_types
[addr_prefix_disp
];
4206 if (found_reverse_match
)
4208 /* If we found a reverse match we must alter the opcode
4209 direction bit. found_reverse_match holds bits to change
4210 (different for int & float insns). */
4212 i
.tm
.base_opcode
^= found_reverse_match
;
4214 i
.tm
.operand_types
[0] = operand_types
[1];
4215 i
.tm
.operand_types
[1] = operand_types
[0];
4224 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4225 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4227 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4229 as_bad (_("`%s' operand %d must use `%ses' segment"),
4235 /* There's only ever one segment override allowed per instruction.
4236 This instruction possibly has a legal segment override on the
4237 second operand, so copy the segment to where non-string
4238 instructions store it, allowing common code. */
4239 i
.seg
[0] = i
.seg
[1];
4241 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4243 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4245 as_bad (_("`%s' operand %d must use `%ses' segment"),
4256 process_suffix (void)
4258 /* If matched instruction specifies an explicit instruction mnemonic
4260 if (i
.tm
.opcode_modifier
.size16
)
4261 i
.suffix
= WORD_MNEM_SUFFIX
;
4262 else if (i
.tm
.opcode_modifier
.size32
)
4263 i
.suffix
= LONG_MNEM_SUFFIX
;
4264 else if (i
.tm
.opcode_modifier
.size64
)
4265 i
.suffix
= QWORD_MNEM_SUFFIX
;
4266 else if (i
.reg_operands
)
4268 /* If there's no instruction mnemonic suffix we try to invent one
4269 based on register operands. */
4272 /* We take i.suffix from the last register operand specified,
4273 Destination register type is more significant than source
4274 register type. crc32 in SSE4.2 prefers source register
4276 if (i
.tm
.base_opcode
== 0xf20f38f1)
4278 if (i
.types
[0].bitfield
.reg16
)
4279 i
.suffix
= WORD_MNEM_SUFFIX
;
4280 else if (i
.types
[0].bitfield
.reg32
)
4281 i
.suffix
= LONG_MNEM_SUFFIX
;
4282 else if (i
.types
[0].bitfield
.reg64
)
4283 i
.suffix
= QWORD_MNEM_SUFFIX
;
4285 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4287 if (i
.types
[0].bitfield
.reg8
)
4288 i
.suffix
= BYTE_MNEM_SUFFIX
;
4295 if (i
.tm
.base_opcode
== 0xf20f38f1
4296 || i
.tm
.base_opcode
== 0xf20f38f0)
4298 /* We have to know the operand size for crc32. */
4299 as_bad (_("ambiguous memory operand size for `%s`"),
4304 for (op
= i
.operands
; --op
>= 0;)
4305 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4307 if (i
.types
[op
].bitfield
.reg8
)
4309 i
.suffix
= BYTE_MNEM_SUFFIX
;
4312 else if (i
.types
[op
].bitfield
.reg16
)
4314 i
.suffix
= WORD_MNEM_SUFFIX
;
4317 else if (i
.types
[op
].bitfield
.reg32
)
4319 i
.suffix
= LONG_MNEM_SUFFIX
;
4322 else if (i
.types
[op
].bitfield
.reg64
)
4324 i
.suffix
= QWORD_MNEM_SUFFIX
;
4330 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4333 && i
.tm
.opcode_modifier
.ignoresize
4334 && i
.tm
.opcode_modifier
.no_bsuf
)
4336 else if (!check_byte_reg ())
4339 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4342 && i
.tm
.opcode_modifier
.ignoresize
4343 && i
.tm
.opcode_modifier
.no_lsuf
)
4345 else if (!check_long_reg ())
4348 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4351 && i
.tm
.opcode_modifier
.ignoresize
4352 && i
.tm
.opcode_modifier
.no_qsuf
)
4354 else if (!check_qword_reg ())
4357 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4360 && i
.tm
.opcode_modifier
.ignoresize
4361 && i
.tm
.opcode_modifier
.no_wsuf
)
4363 else if (!check_word_reg ())
4366 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4367 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4369 /* Skip if the instruction has x/y suffix. match_template
4370 should check if it is a valid suffix. */
4372 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4373 /* Do nothing if the instruction is going to ignore the prefix. */
4378 else if (i
.tm
.opcode_modifier
.defaultsize
4380 /* exclude fldenv/frstor/fsave/fstenv */
4381 && i
.tm
.opcode_modifier
.no_ssuf
)
4383 i
.suffix
= stackop_size
;
4385 else if (intel_syntax
4387 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4388 || i
.tm
.opcode_modifier
.jumpbyte
4389 || i
.tm
.opcode_modifier
.jumpintersegment
4390 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4391 && i
.tm
.extension_opcode
<= 3)))
4396 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4398 i
.suffix
= QWORD_MNEM_SUFFIX
;
4402 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4403 i
.suffix
= LONG_MNEM_SUFFIX
;
4406 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4407 i
.suffix
= WORD_MNEM_SUFFIX
;
4416 if (i
.tm
.opcode_modifier
.w
)
4418 as_bad (_("no instruction mnemonic suffix given and "
4419 "no register operands; can't size instruction"));
4425 unsigned int suffixes
;
4427 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4428 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4430 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4432 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4434 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4436 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4439 /* There are more than suffix matches. */
4440 if (i
.tm
.opcode_modifier
.w
4441 || ((suffixes
& (suffixes
- 1))
4442 && !i
.tm
.opcode_modifier
.defaultsize
4443 && !i
.tm
.opcode_modifier
.ignoresize
))
4445 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4451 /* Change the opcode based on the operand size given by i.suffix;
4452 We don't need to change things for byte insns. */
4455 && i
.suffix
!= BYTE_MNEM_SUFFIX
4456 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4457 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4459 /* It's not a byte, select word/dword operation. */
4460 if (i
.tm
.opcode_modifier
.w
)
4462 if (i
.tm
.opcode_modifier
.shortform
)
4463 i
.tm
.base_opcode
|= 8;
4465 i
.tm
.base_opcode
|= 1;
4468 /* Now select between word & dword operations via the operand
4469 size prefix, except for instructions that will ignore this
4471 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4473 /* The address size override prefix changes the size of the
4475 if ((flag_code
== CODE_32BIT
4476 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4477 || (flag_code
!= CODE_32BIT
4478 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4479 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4482 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4483 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4484 && !i
.tm
.opcode_modifier
.ignoresize
4485 && !i
.tm
.opcode_modifier
.floatmf
4486 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4487 || (flag_code
== CODE_64BIT
4488 && i
.tm
.opcode_modifier
.jumpbyte
)))
4490 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4492 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4493 prefix
= ADDR_PREFIX_OPCODE
;
4495 if (!add_prefix (prefix
))
4499 /* Set mode64 for an operand. */
4500 if (i
.suffix
== QWORD_MNEM_SUFFIX
4501 && flag_code
== CODE_64BIT
4502 && !i
.tm
.opcode_modifier
.norex64
)
4504 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4505 need rex64. cmpxchg8b is also a special case. */
4506 if (! (i
.operands
== 2
4507 && i
.tm
.base_opcode
== 0x90
4508 && i
.tm
.extension_opcode
== None
4509 && operand_type_equal (&i
.types
[0], &acc64
)
4510 && operand_type_equal (&i
.types
[1], &acc64
))
4511 && ! (i
.operands
== 1
4512 && i
.tm
.base_opcode
== 0xfc7
4513 && i
.tm
.extension_opcode
== 1
4514 && !operand_type_check (i
.types
[0], reg
)
4515 && operand_type_check (i
.types
[0], anymem
)))
4519 /* Size floating point instruction. */
4520 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4521 if (i
.tm
.opcode_modifier
.floatmf
)
4522 i
.tm
.base_opcode
^= 4;
4529 check_byte_reg (void)
4533 for (op
= i
.operands
; --op
>= 0;)
4535 /* If this is an eight bit register, it's OK. If it's the 16 or
4536 32 bit version of an eight bit register, we will just use the
4537 low portion, and that's OK too. */
4538 if (i
.types
[op
].bitfield
.reg8
)
4541 /* crc32 doesn't generate this warning. */
4542 if (i
.tm
.base_opcode
== 0xf20f38f0)
4545 if ((i
.types
[op
].bitfield
.reg16
4546 || i
.types
[op
].bitfield
.reg32
4547 || i
.types
[op
].bitfield
.reg64
)
4548 && i
.op
[op
].regs
->reg_num
< 4)
4550 /* Prohibit these changes in the 64bit mode, since the
4551 lowering is more complicated. */
4552 if (flag_code
== CODE_64BIT
4553 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4555 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4556 register_prefix
, i
.op
[op
].regs
->reg_name
,
4560 #if REGISTER_WARNINGS
4562 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4563 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4565 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4566 ? REGNAM_AL
- REGNAM_AX
4567 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4569 i
.op
[op
].regs
->reg_name
,
4574 /* Any other register is bad. */
4575 if (i
.types
[op
].bitfield
.reg16
4576 || i
.types
[op
].bitfield
.reg32
4577 || i
.types
[op
].bitfield
.reg64
4578 || i
.types
[op
].bitfield
.regmmx
4579 || i
.types
[op
].bitfield
.regxmm
4580 || i
.types
[op
].bitfield
.regymm
4581 || i
.types
[op
].bitfield
.sreg2
4582 || i
.types
[op
].bitfield
.sreg3
4583 || i
.types
[op
].bitfield
.control
4584 || i
.types
[op
].bitfield
.debug
4585 || i
.types
[op
].bitfield
.test
4586 || i
.types
[op
].bitfield
.floatreg
4587 || i
.types
[op
].bitfield
.floatacc
)
4589 as_bad (_("`%s%s' not allowed with `%s%c'"),
4591 i
.op
[op
].regs
->reg_name
,
4601 check_long_reg (void)
4605 for (op
= i
.operands
; --op
>= 0;)
4606 /* Reject eight bit registers, except where the template requires
4607 them. (eg. movzb) */
4608 if (i
.types
[op
].bitfield
.reg8
4609 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4610 || i
.tm
.operand_types
[op
].bitfield
.reg32
4611 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4613 as_bad (_("`%s%s' not allowed with `%s%c'"),
4615 i
.op
[op
].regs
->reg_name
,
4620 /* Warn if the e prefix on a general reg is missing. */
4621 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4622 && i
.types
[op
].bitfield
.reg16
4623 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4624 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4626 /* Prohibit these changes in the 64bit mode, since the
4627 lowering is more complicated. */
4628 if (flag_code
== CODE_64BIT
)
4630 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4631 register_prefix
, i
.op
[op
].regs
->reg_name
,
4635 #if REGISTER_WARNINGS
4637 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4639 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4641 i
.op
[op
].regs
->reg_name
,
4645 /* Warn if the r prefix on a general reg is missing. */
4646 else if (i
.types
[op
].bitfield
.reg64
4647 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4648 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4651 && i
.tm
.opcode_modifier
.toqword
4652 && !i
.types
[0].bitfield
.regxmm
)
4654 /* Convert to QWORD. We want REX byte. */
4655 i
.suffix
= QWORD_MNEM_SUFFIX
;
4659 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4660 register_prefix
, i
.op
[op
].regs
->reg_name
,
4669 check_qword_reg (void)
4673 for (op
= i
.operands
; --op
>= 0; )
4674 /* Reject eight bit registers, except where the template requires
4675 them. (eg. movzb) */
4676 if (i
.types
[op
].bitfield
.reg8
4677 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4678 || i
.tm
.operand_types
[op
].bitfield
.reg32
4679 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4681 as_bad (_("`%s%s' not allowed with `%s%c'"),
4683 i
.op
[op
].regs
->reg_name
,
4688 /* Warn if the e prefix on a general reg is missing. */
4689 else if ((i
.types
[op
].bitfield
.reg16
4690 || i
.types
[op
].bitfield
.reg32
)
4691 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4692 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4694 /* Prohibit these changes in the 64bit mode, since the
4695 lowering is more complicated. */
4697 && i
.tm
.opcode_modifier
.todword
4698 && !i
.types
[0].bitfield
.regxmm
)
4700 /* Convert to DWORD. We don't want REX byte. */
4701 i
.suffix
= LONG_MNEM_SUFFIX
;
4705 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4706 register_prefix
, i
.op
[op
].regs
->reg_name
,
4715 check_word_reg (void)
4718 for (op
= i
.operands
; --op
>= 0;)
4719 /* Reject eight bit registers, except where the template requires
4720 them. (eg. movzb) */
4721 if (i
.types
[op
].bitfield
.reg8
4722 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4723 || i
.tm
.operand_types
[op
].bitfield
.reg32
4724 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4726 as_bad (_("`%s%s' not allowed with `%s%c'"),
4728 i
.op
[op
].regs
->reg_name
,
4733 /* Warn if the e prefix on a general reg is present. */
4734 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4735 && i
.types
[op
].bitfield
.reg32
4736 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4737 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4739 /* Prohibit these changes in the 64bit mode, since the
4740 lowering is more complicated. */
4741 if (flag_code
== CODE_64BIT
)
4743 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4744 register_prefix
, i
.op
[op
].regs
->reg_name
,
4749 #if REGISTER_WARNINGS
4750 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4752 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4754 i
.op
[op
].regs
->reg_name
,
4762 update_imm (unsigned int j
)
4764 i386_operand_type overlap
= i
.types
[j
];
4765 if ((overlap
.bitfield
.imm8
4766 || overlap
.bitfield
.imm8s
4767 || overlap
.bitfield
.imm16
4768 || overlap
.bitfield
.imm32
4769 || overlap
.bitfield
.imm32s
4770 || overlap
.bitfield
.imm64
)
4771 && !operand_type_equal (&overlap
, &imm8
)
4772 && !operand_type_equal (&overlap
, &imm8s
)
4773 && !operand_type_equal (&overlap
, &imm16
)
4774 && !operand_type_equal (&overlap
, &imm32
)
4775 && !operand_type_equal (&overlap
, &imm32s
)
4776 && !operand_type_equal (&overlap
, &imm64
))
4780 i386_operand_type temp
;
4782 operand_type_set (&temp
, 0);
4783 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4785 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4786 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4788 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4789 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4790 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4792 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4793 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4796 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4799 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4800 || operand_type_equal (&overlap
, &imm16_32
)
4801 || operand_type_equal (&overlap
, &imm16_32s
))
4803 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4808 if (!operand_type_equal (&overlap
, &imm8
)
4809 && !operand_type_equal (&overlap
, &imm8s
)
4810 && !operand_type_equal (&overlap
, &imm16
)
4811 && !operand_type_equal (&overlap
, &imm32
)
4812 && !operand_type_equal (&overlap
, &imm32s
)
4813 && !operand_type_equal (&overlap
, &imm64
))
4815 as_bad (_("no instruction mnemonic suffix given; "
4816 "can't determine immediate size"));
4820 i
.types
[j
] = overlap
;
4830 /* Update the first 2 immediate operands. */
4831 n
= i
.operands
> 2 ? 2 : i
.operands
;
4834 for (j
= 0; j
< n
; j
++)
4835 if (update_imm (j
) == 0)
4838 /* The 3rd operand can't be immediate operand. */
4839 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4846 bad_implicit_operand (int xmm
)
4848 const char *ireg
= xmm
? "xmm0" : "ymm0";
4851 as_bad (_("the last operand of `%s' must be `%s%s'"),
4852 i
.tm
.name
, register_prefix
, ireg
);
4854 as_bad (_("the first operand of `%s' must be `%s%s'"),
4855 i
.tm
.name
, register_prefix
, ireg
);
4860 process_operands (void)
4862 /* Default segment register this instruction will use for memory
4863 accesses. 0 means unknown. This is only for optimizing out
4864 unnecessary segment overrides. */
4865 const seg_entry
*default_seg
= 0;
4867 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4869 unsigned int dupl
= i
.operands
;
4870 unsigned int dest
= dupl
- 1;
4873 /* The destination must be an xmm register. */
4874 gas_assert (i
.reg_operands
4875 && MAX_OPERANDS
> dupl
4876 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4878 if (i
.tm
.opcode_modifier
.firstxmm0
)
4880 /* The first operand is implicit and must be xmm0. */
4881 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4882 if (i
.op
[0].regs
->reg_num
!= 0)
4883 return bad_implicit_operand (1);
4885 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4887 /* Keep xmm0 for instructions with VEX prefix and 3
4893 /* We remove the first xmm0 and keep the number of
4894 operands unchanged, which in fact duplicates the
4896 for (j
= 1; j
< i
.operands
; j
++)
4898 i
.op
[j
- 1] = i
.op
[j
];
4899 i
.types
[j
- 1] = i
.types
[j
];
4900 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4904 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4906 gas_assert ((MAX_OPERANDS
- 1) > dupl
4907 && (i
.tm
.opcode_modifier
.vexsources
4910 /* Add the implicit xmm0 for instructions with VEX prefix
4912 for (j
= i
.operands
; j
> 0; j
--)
4914 i
.op
[j
] = i
.op
[j
- 1];
4915 i
.types
[j
] = i
.types
[j
- 1];
4916 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4919 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4920 i
.types
[0] = regxmm
;
4921 i
.tm
.operand_types
[0] = regxmm
;
4924 i
.reg_operands
+= 2;
4929 i
.op
[dupl
] = i
.op
[dest
];
4930 i
.types
[dupl
] = i
.types
[dest
];
4931 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4940 i
.op
[dupl
] = i
.op
[dest
];
4941 i
.types
[dupl
] = i
.types
[dest
];
4942 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4945 if (i
.tm
.opcode_modifier
.immext
)
4948 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4952 /* The first operand is implicit and must be xmm0/ymm0. */
4953 gas_assert (i
.reg_operands
4954 && (operand_type_equal (&i
.types
[0], ®xmm
)
4955 || operand_type_equal (&i
.types
[0], ®ymm
)));
4956 if (i
.op
[0].regs
->reg_num
!= 0)
4957 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4959 for (j
= 1; j
< i
.operands
; j
++)
4961 i
.op
[j
- 1] = i
.op
[j
];
4962 i
.types
[j
- 1] = i
.types
[j
];
4964 /* We need to adjust fields in i.tm since they are used by
4965 build_modrm_byte. */
4966 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4973 else if (i
.tm
.opcode_modifier
.regkludge
)
4975 /* The imul $imm, %reg instruction is converted into
4976 imul $imm, %reg, %reg, and the clr %reg instruction
4977 is converted into xor %reg, %reg. */
4979 unsigned int first_reg_op
;
4981 if (operand_type_check (i
.types
[0], reg
))
4985 /* Pretend we saw the extra register operand. */
4986 gas_assert (i
.reg_operands
== 1
4987 && i
.op
[first_reg_op
+ 1].regs
== 0);
4988 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4989 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4994 if (i
.tm
.opcode_modifier
.shortform
)
4996 if (i
.types
[0].bitfield
.sreg2
4997 || i
.types
[0].bitfield
.sreg3
)
4999 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5000 && i
.op
[0].regs
->reg_num
== 1)
5002 as_bad (_("you can't `pop %scs'"), register_prefix
);
5005 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5006 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5011 /* The register or float register operand is in operand
5015 if (i
.types
[0].bitfield
.floatreg
5016 || operand_type_check (i
.types
[0], reg
))
5020 /* Register goes in low 3 bits of opcode. */
5021 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5022 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5024 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5026 /* Warn about some common errors, but press on regardless.
5027 The first case can be generated by gcc (<= 2.8.1). */
5028 if (i
.operands
== 2)
5030 /* Reversed arguments on faddp, fsubp, etc. */
5031 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5032 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5033 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5037 /* Extraneous `l' suffix on fp insn. */
5038 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5039 register_prefix
, i
.op
[0].regs
->reg_name
);
5044 else if (i
.tm
.opcode_modifier
.modrm
)
5046 /* The opcode is completed (modulo i.tm.extension_opcode which
5047 must be put into the modrm byte). Now, we make the modrm and
5048 index base bytes based on all the info we've collected. */
5050 default_seg
= build_modrm_byte ();
5052 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5056 else if (i
.tm
.opcode_modifier
.isstring
)
5058 /* For the string instructions that allow a segment override
5059 on one of their operands, the default segment is ds. */
5063 if (i
.tm
.base_opcode
== 0x8d /* lea */
5066 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5068 /* If a segment was explicitly specified, and the specified segment
5069 is not the default, use an opcode prefix to select it. If we
5070 never figured out what the default segment is, then default_seg
5071 will be zero at this point, and the specified segment prefix will
5073 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5075 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5081 static const seg_entry
*
5082 build_modrm_byte (void)
5084 const seg_entry
*default_seg
= 0;
5085 unsigned int source
, dest
;
5088 /* The first operand of instructions with VEX prefix and 3 sources
5089 must be VEX_Imm4. */
5090 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5093 unsigned int nds
, reg_slot
;
5096 if (i
.tm
.opcode_modifier
.veximmext
5097 && i
.tm
.opcode_modifier
.immext
)
5099 dest
= i
.operands
- 2;
5100 gas_assert (dest
== 3);
5103 dest
= i
.operands
- 1;
5106 /* There are 2 kinds of instructions:
5107 1. 5 operands: 4 register operands or 3 register operands
5108 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5109 VexW0 or VexW1. The destination must be either XMM or YMM
5111 2. 4 operands: 4 register operands or 3 register operands
5112 plus 1 memory operand, VexXDS, and VexImmExt */
5113 gas_assert ((i
.reg_operands
== 4
5114 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5115 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5116 && (i
.tm
.opcode_modifier
.veximmext
5117 || (i
.imm_operands
== 1
5118 && i
.types
[0].bitfield
.vec_imm4
5119 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5120 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5121 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5122 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5124 if (i
.imm_operands
== 0)
5126 /* When there is no immediate operand, generate an 8bit
5127 immediate operand to encode the first operand. */
5128 exp
= &im_expressions
[i
.imm_operands
++];
5129 i
.op
[i
.operands
].imms
= exp
;
5130 i
.types
[i
.operands
] = imm8
;
5132 /* If VexW1 is set, the first operand is the source and
5133 the second operand is encoded in the immediate operand. */
5134 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5145 /* FMA swaps REG and NDS. */
5146 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5154 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5156 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5158 exp
->X_op
= O_constant
;
5160 = ((i
.op
[reg_slot
].regs
->reg_num
5161 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5166 unsigned int imm_slot
;
5168 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5170 /* If VexW0 is set, the third operand is the source and
5171 the second operand is encoded in the immediate
5178 /* VexW1 is set, the second operand is the source and
5179 the third operand is encoded in the immediate
5185 if (i
.tm
.opcode_modifier
.immext
)
5187 /* When ImmExt is set, the immdiate byte is the last
5189 imm_slot
= i
.operands
- 1;
5197 /* Turn on Imm8 so that output_imm will generate it. */
5198 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5201 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5203 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5205 i
.op
[imm_slot
].imms
->X_add_number
5206 |= ((i
.op
[reg_slot
].regs
->reg_num
5207 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5211 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5212 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5214 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5219 /* i.reg_operands MUST be the number of real register operands;
5220 implicit registers do not count. If there are 3 register
5221 operands, it must be a instruction with VexNDS. For a
5222 instruction with VexNDD, the destination register is encoded
5223 in VEX prefix. If there are 4 register operands, it must be
5224 a instruction with VEX prefix and 3 sources. */
5225 if (i
.mem_operands
== 0
5226 && ((i
.reg_operands
== 2
5227 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5228 || (i
.reg_operands
== 3
5229 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5230 || (i
.reg_operands
== 4 && vex_3_sources
)))
5238 /* When there are 3 operands, one of them may be immediate,
5239 which may be the first or the last operand. Otherwise,
5240 the first operand must be shift count register (cl) or it
5241 is an instruction with VexNDS. */
5242 gas_assert (i
.imm_operands
== 1
5243 || (i
.imm_operands
== 0
5244 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5245 || i
.types
[0].bitfield
.shiftcount
)));
5246 if (operand_type_check (i
.types
[0], imm
)
5247 || i
.types
[0].bitfield
.shiftcount
)
5253 /* When there are 4 operands, the first two must be 8bit
5254 immediate operands. The source operand will be the 3rd
5257 For instructions with VexNDS, if the first operand
5258 an imm8, the source operand is the 2nd one. If the last
5259 operand is imm8, the source operand is the first one. */
5260 gas_assert ((i
.imm_operands
== 2
5261 && i
.types
[0].bitfield
.imm8
5262 && i
.types
[1].bitfield
.imm8
)
5263 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5264 && i
.imm_operands
== 1
5265 && (i
.types
[0].bitfield
.imm8
5266 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5267 if (i
.imm_operands
== 2)
5271 if (i
.types
[0].bitfield
.imm8
)
5287 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5289 /* For instructions with VexNDS, the register-only
5290 source operand must be XMM or YMM register. It is
5291 encoded in VEX prefix. We need to clear RegMem bit
5292 before calling operand_type_equal. */
5293 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5294 op
.bitfield
.regmem
= 0;
5295 if ((dest
+ 1) >= i
.operands
5296 || (!operand_type_equal (&op
, ®xmm
)
5297 && !operand_type_equal (&op
, ®ymm
)))
5299 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5305 /* One of the register operands will be encoded in the i.tm.reg
5306 field, the other in the combined i.tm.mode and i.tm.regmem
5307 fields. If no form of this instruction supports a memory
5308 destination operand, then we assume the source operand may
5309 sometimes be a memory operand and so we need to store the
5310 destination in the i.rm.reg field. */
5311 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5312 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5314 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5315 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5316 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5318 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5323 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5324 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5325 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5327 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5330 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5332 if (!i
.types
[0].bitfield
.control
5333 && !i
.types
[1].bitfield
.control
)
5335 i
.rex
&= ~(REX_R
| REX_B
);
5336 add_prefix (LOCK_PREFIX_OPCODE
);
5340 { /* If it's not 2 reg operands... */
5345 unsigned int fake_zero_displacement
= 0;
5348 for (op
= 0; op
< i
.operands
; op
++)
5349 if (operand_type_check (i
.types
[op
], anymem
))
5351 gas_assert (op
< i
.operands
);
5355 if (i
.base_reg
== 0)
5358 if (!i
.disp_operands
)
5359 fake_zero_displacement
= 1;
5360 if (i
.index_reg
== 0)
5362 /* Operand is just <disp> */
5363 if (flag_code
== CODE_64BIT
)
5365 /* 64bit mode overwrites the 32bit absolute
5366 addressing by RIP relative addressing and
5367 absolute addressing is encoded by one of the
5368 redundant SIB forms. */
5369 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5370 i
.sib
.base
= NO_BASE_REGISTER
;
5371 i
.sib
.index
= NO_INDEX_REGISTER
;
5372 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5373 ? disp32s
: disp32
);
5375 else if ((flag_code
== CODE_16BIT
)
5376 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5378 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5379 i
.types
[op
] = disp16
;
5383 i
.rm
.regmem
= NO_BASE_REGISTER
;
5384 i
.types
[op
] = disp32
;
5387 else /* !i.base_reg && i.index_reg */
5389 if (i
.index_reg
->reg_num
== RegEiz
5390 || i
.index_reg
->reg_num
== RegRiz
)
5391 i
.sib
.index
= NO_INDEX_REGISTER
;
5393 i
.sib
.index
= i
.index_reg
->reg_num
;
5394 i
.sib
.base
= NO_BASE_REGISTER
;
5395 i
.sib
.scale
= i
.log2_scale_factor
;
5396 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5397 i
.types
[op
].bitfield
.disp8
= 0;
5398 i
.types
[op
].bitfield
.disp16
= 0;
5399 i
.types
[op
].bitfield
.disp64
= 0;
5400 if (flag_code
!= CODE_64BIT
)
5402 /* Must be 32 bit */
5403 i
.types
[op
].bitfield
.disp32
= 1;
5404 i
.types
[op
].bitfield
.disp32s
= 0;
5408 i
.types
[op
].bitfield
.disp32
= 0;
5409 i
.types
[op
].bitfield
.disp32s
= 1;
5411 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5415 /* RIP addressing for 64bit mode. */
5416 else if (i
.base_reg
->reg_num
== RegRip
||
5417 i
.base_reg
->reg_num
== RegEip
)
5419 i
.rm
.regmem
= NO_BASE_REGISTER
;
5420 i
.types
[op
].bitfield
.disp8
= 0;
5421 i
.types
[op
].bitfield
.disp16
= 0;
5422 i
.types
[op
].bitfield
.disp32
= 0;
5423 i
.types
[op
].bitfield
.disp32s
= 1;
5424 i
.types
[op
].bitfield
.disp64
= 0;
5425 i
.flags
[op
] |= Operand_PCrel
;
5426 if (! i
.disp_operands
)
5427 fake_zero_displacement
= 1;
5429 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5431 switch (i
.base_reg
->reg_num
)
5434 if (i
.index_reg
== 0)
5436 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5437 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5441 if (i
.index_reg
== 0)
5444 if (operand_type_check (i
.types
[op
], disp
) == 0)
5446 /* fake (%bp) into 0(%bp) */
5447 i
.types
[op
].bitfield
.disp8
= 1;
5448 fake_zero_displacement
= 1;
5451 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5452 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5454 default: /* (%si) -> 4 or (%di) -> 5 */
5455 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5457 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5459 else /* i.base_reg and 32/64 bit mode */
5461 if (flag_code
== CODE_64BIT
5462 && operand_type_check (i
.types
[op
], disp
))
5464 i386_operand_type temp
;
5465 operand_type_set (&temp
, 0);
5466 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5468 if (i
.prefix
[ADDR_PREFIX
] == 0)
5469 i
.types
[op
].bitfield
.disp32s
= 1;
5471 i
.types
[op
].bitfield
.disp32
= 1;
5474 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5475 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5477 i
.sib
.base
= i
.base_reg
->reg_num
;
5478 /* x86-64 ignores REX prefix bit here to avoid decoder
5480 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5483 if (i
.disp_operands
== 0)
5485 fake_zero_displacement
= 1;
5486 i
.types
[op
].bitfield
.disp8
= 1;
5489 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5493 i
.sib
.scale
= i
.log2_scale_factor
;
5494 if (i
.index_reg
== 0)
5496 /* <disp>(%esp) becomes two byte modrm with no index
5497 register. We've already stored the code for esp
5498 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5499 Any base register besides %esp will not use the
5500 extra modrm byte. */
5501 i
.sib
.index
= NO_INDEX_REGISTER
;
5505 if (i
.index_reg
->reg_num
== RegEiz
5506 || i
.index_reg
->reg_num
== RegRiz
)
5507 i
.sib
.index
= NO_INDEX_REGISTER
;
5509 i
.sib
.index
= i
.index_reg
->reg_num
;
5510 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5511 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5516 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5517 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5520 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5523 if (fake_zero_displacement
)
5525 /* Fakes a zero displacement assuming that i.types[op]
5526 holds the correct displacement size. */
5529 gas_assert (i
.op
[op
].disps
== 0);
5530 exp
= &disp_expressions
[i
.disp_operands
++];
5531 i
.op
[op
].disps
= exp
;
5532 exp
->X_op
= O_constant
;
5533 exp
->X_add_number
= 0;
5534 exp
->X_add_symbol
= (symbolS
*) 0;
5535 exp
->X_op_symbol
= (symbolS
*) 0;
5543 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5545 if (operand_type_check (i
.types
[0], imm
))
5546 i
.vex
.register_specifier
= NULL
;
5549 /* VEX.vvvv encodes one of the sources when the first
5550 operand is not an immediate. */
5551 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5552 i
.vex
.register_specifier
= i
.op
[0].regs
;
5554 i
.vex
.register_specifier
= i
.op
[1].regs
;
5557 /* Destination is a XMM register encoded in the ModRM.reg
5559 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5560 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5563 /* ModRM.rm and VEX.B encodes the other source. */
5564 if (!i
.mem_operands
)
5568 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5569 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5571 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5573 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5577 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5579 i
.vex
.register_specifier
= i
.op
[2].regs
;
5580 if (!i
.mem_operands
)
5583 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5584 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5588 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5589 (if any) based on i.tm.extension_opcode. Again, we must be
5590 careful to make sure that segment/control/debug/test/MMX
5591 registers are coded into the i.rm.reg field. */
5592 else if (i
.reg_operands
)
5595 unsigned int vex_reg
= ~0;
5597 for (op
= 0; op
< i
.operands
; op
++)
5598 if (i
.types
[op
].bitfield
.reg8
5599 || i
.types
[op
].bitfield
.reg16
5600 || i
.types
[op
].bitfield
.reg32
5601 || i
.types
[op
].bitfield
.reg64
5602 || i
.types
[op
].bitfield
.regmmx
5603 || i
.types
[op
].bitfield
.regxmm
5604 || i
.types
[op
].bitfield
.regymm
5605 || i
.types
[op
].bitfield
.sreg2
5606 || i
.types
[op
].bitfield
.sreg3
5607 || i
.types
[op
].bitfield
.control
5608 || i
.types
[op
].bitfield
.debug
5609 || i
.types
[op
].bitfield
.test
)
5614 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5616 /* For instructions with VexNDS, the register-only
5617 source operand is encoded in VEX prefix. */
5618 gas_assert (mem
!= (unsigned int) ~0);
5623 gas_assert (op
< i
.operands
);
5628 gas_assert (vex_reg
< i
.operands
);
5631 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5633 /* For instructions with VexNDD, there should be
5634 no memory operand and the register destination
5635 is encoded in VEX prefix. */
5636 gas_assert (i
.mem_operands
== 0
5637 && (op
+ 2) == i
.operands
);
5641 gas_assert (op
< i
.operands
);
5643 if (vex_reg
!= (unsigned int) ~0)
5645 gas_assert (i
.reg_operands
== 2);
5647 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5649 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5653 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5656 /* Don't set OP operand twice. */
5659 /* If there is an extension opcode to put here, the
5660 register number must be put into the regmem field. */
5661 if (i
.tm
.extension_opcode
!= None
)
5663 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5664 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5669 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5670 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5675 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5676 must set it to 3 to indicate this is a register operand
5677 in the regmem field. */
5678 if (!i
.mem_operands
)
5682 /* Fill in i.rm.reg field with extension opcode (if any). */
5683 if (i
.tm
.extension_opcode
!= None
)
5684 i
.rm
.reg
= i
.tm
.extension_opcode
;
5690 output_branch (void)
5695 relax_substateT subtype
;
5700 if (flag_code
== CODE_16BIT
)
5704 if (i
.prefix
[DATA_PREFIX
] != 0)
5710 /* Pentium4 branch hints. */
5711 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5712 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5717 if (i
.prefix
[REX_PREFIX
] != 0)
5723 if (i
.prefixes
!= 0 && !intel_syntax
)
5724 as_warn (_("skipping prefixes on this instruction"));
5726 /* It's always a symbol; End frag & setup for relax.
5727 Make sure there is enough room in this frag for the largest
5728 instruction we may generate in md_convert_frag. This is 2
5729 bytes for the opcode and room for the prefix and largest
5731 frag_grow (prefix
+ 2 + 4);
5732 /* Prefix and 1 opcode byte go in fr_fix. */
5733 p
= frag_more (prefix
+ 1);
5734 if (i
.prefix
[DATA_PREFIX
] != 0)
5735 *p
++ = DATA_PREFIX_OPCODE
;
5736 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5737 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5738 *p
++ = i
.prefix
[SEG_PREFIX
];
5739 if (i
.prefix
[REX_PREFIX
] != 0)
5740 *p
++ = i
.prefix
[REX_PREFIX
];
5741 *p
= i
.tm
.base_opcode
;
5743 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5744 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5745 else if (cpu_arch_flags
.bitfield
.cpui386
)
5746 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5748 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5751 sym
= i
.op
[0].disps
->X_add_symbol
;
5752 off
= i
.op
[0].disps
->X_add_number
;
5754 if (i
.op
[0].disps
->X_op
!= O_constant
5755 && i
.op
[0].disps
->X_op
!= O_symbol
)
5757 /* Handle complex expressions. */
5758 sym
= make_expr_symbol (i
.op
[0].disps
);
5762 /* 1 possible extra opcode + 4 byte displacement go in var part.
5763 Pass reloc in fr_var. */
5764 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5774 if (i
.tm
.opcode_modifier
.jumpbyte
)
5776 /* This is a loop or jecxz type instruction. */
5778 if (i
.prefix
[ADDR_PREFIX
] != 0)
5780 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5783 /* Pentium4 branch hints. */
5784 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5785 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5787 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5796 if (flag_code
== CODE_16BIT
)
5799 if (i
.prefix
[DATA_PREFIX
] != 0)
5801 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5811 if (i
.prefix
[REX_PREFIX
] != 0)
5813 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5817 if (i
.prefixes
!= 0 && !intel_syntax
)
5818 as_warn (_("skipping prefixes on this instruction"));
5820 p
= frag_more (1 + size
);
5821 *p
++ = i
.tm
.base_opcode
;
5823 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5824 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5826 /* All jumps handled here are signed, but don't use a signed limit
5827 check for 32 and 16 bit jumps as we want to allow wrap around at
5828 4G and 64k respectively. */
5830 fixP
->fx_signed
= 1;
5834 output_interseg_jump (void)
5842 if (flag_code
== CODE_16BIT
)
5846 if (i
.prefix
[DATA_PREFIX
] != 0)
5852 if (i
.prefix
[REX_PREFIX
] != 0)
5862 if (i
.prefixes
!= 0 && !intel_syntax
)
5863 as_warn (_("skipping prefixes on this instruction"));
5865 /* 1 opcode; 2 segment; offset */
5866 p
= frag_more (prefix
+ 1 + 2 + size
);
5868 if (i
.prefix
[DATA_PREFIX
] != 0)
5869 *p
++ = DATA_PREFIX_OPCODE
;
5871 if (i
.prefix
[REX_PREFIX
] != 0)
5872 *p
++ = i
.prefix
[REX_PREFIX
];
5874 *p
++ = i
.tm
.base_opcode
;
5875 if (i
.op
[1].imms
->X_op
== O_constant
)
5877 offsetT n
= i
.op
[1].imms
->X_add_number
;
5880 && !fits_in_unsigned_word (n
)
5881 && !fits_in_signed_word (n
))
5883 as_bad (_("16-bit jump out of range"));
5886 md_number_to_chars (p
, n
, size
);
5889 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5890 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5891 if (i
.op
[0].imms
->X_op
!= O_constant
)
5892 as_bad (_("can't handle non absolute segment in `%s'"),
5894 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5900 fragS
*insn_start_frag
;
5901 offsetT insn_start_off
;
5903 /* Tie dwarf2 debug info to the address at the start of the insn.
5904 We can't do this after the insn has been output as the current
5905 frag may have been closed off. eg. by frag_var. */
5906 dwarf2_emit_insn (0);
5908 insn_start_frag
= frag_now
;
5909 insn_start_off
= frag_now_fix ();
5912 if (i
.tm
.opcode_modifier
.jump
)
5914 else if (i
.tm
.opcode_modifier
.jumpbyte
5915 || i
.tm
.opcode_modifier
.jumpdword
)
5917 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5918 output_interseg_jump ();
5921 /* Output normal instructions here. */
5925 unsigned int prefix
;
5927 /* Since the VEX prefix contains the implicit prefix, we don't
5928 need the explicit prefix. */
5929 if (!i
.tm
.opcode_modifier
.vex
)
5931 switch (i
.tm
.opcode_length
)
5934 if (i
.tm
.base_opcode
& 0xff000000)
5936 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5941 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5943 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5944 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5947 if (prefix
!= REPE_PREFIX_OPCODE
5948 || (i
.prefix
[REP_PREFIX
]
5949 != REPE_PREFIX_OPCODE
))
5950 add_prefix (prefix
);
5953 add_prefix (prefix
);
5962 /* The prefix bytes. */
5963 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5965 FRAG_APPEND_1_CHAR (*q
);
5968 if (i
.tm
.opcode_modifier
.vex
)
5970 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5975 /* REX byte is encoded in VEX prefix. */
5979 FRAG_APPEND_1_CHAR (*q
);
5982 /* There should be no other prefixes for instructions
5987 /* Now the VEX prefix. */
5988 p
= frag_more (i
.vex
.length
);
5989 for (j
= 0; j
< i
.vex
.length
; j
++)
5990 p
[j
] = i
.vex
.bytes
[j
];
5993 /* Now the opcode; be careful about word order here! */
5994 if (i
.tm
.opcode_length
== 1)
5996 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6000 switch (i
.tm
.opcode_length
)
6004 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6014 /* Put out high byte first: can't use md_number_to_chars! */
6015 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6016 *p
= i
.tm
.base_opcode
& 0xff;
6019 /* Now the modrm byte and sib byte (if present). */
6020 if (i
.tm
.opcode_modifier
.modrm
)
6022 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6025 /* If i.rm.regmem == ESP (4)
6026 && i.rm.mode != (Register mode)
6028 ==> need second modrm byte. */
6029 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6031 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6032 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6034 | i
.sib
.scale
<< 6));
6037 if (i
.disp_operands
)
6038 output_disp (insn_start_frag
, insn_start_off
);
6041 output_imm (insn_start_frag
, insn_start_off
);
6047 pi ("" /*line*/, &i
);
6049 #endif /* DEBUG386 */
6052 /* Return the size of the displacement operand N. */
6055 disp_size (unsigned int n
)
6058 if (i
.types
[n
].bitfield
.disp64
)
6060 else if (i
.types
[n
].bitfield
.disp8
)
6062 else if (i
.types
[n
].bitfield
.disp16
)
6067 /* Return the size of the immediate operand N. */
6070 imm_size (unsigned int n
)
6073 if (i
.types
[n
].bitfield
.imm64
)
6075 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6077 else if (i
.types
[n
].bitfield
.imm16
)
6083 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6088 for (n
= 0; n
< i
.operands
; n
++)
6090 if (operand_type_check (i
.types
[n
], disp
))
6092 if (i
.op
[n
].disps
->X_op
== O_constant
)
6094 int size
= disp_size (n
);
6097 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6099 p
= frag_more (size
);
6100 md_number_to_chars (p
, val
, size
);
6104 enum bfd_reloc_code_real reloc_type
;
6105 int size
= disp_size (n
);
6106 int sign
= i
.types
[n
].bitfield
.disp32s
;
6107 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6109 /* We can't have 8 bit displacement here. */
6110 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6112 /* The PC relative address is computed relative
6113 to the instruction boundary, so in case immediate
6114 fields follows, we need to adjust the value. */
6115 if (pcrel
&& i
.imm_operands
)
6120 for (n1
= 0; n1
< i
.operands
; n1
++)
6121 if (operand_type_check (i
.types
[n1
], imm
))
6123 /* Only one immediate is allowed for PC
6124 relative address. */
6125 gas_assert (sz
== 0);
6127 i
.op
[n
].disps
->X_add_number
-= sz
;
6129 /* We should find the immediate. */
6130 gas_assert (sz
!= 0);
6133 p
= frag_more (size
);
6134 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6136 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6137 && (((reloc_type
== BFD_RELOC_32
6138 || reloc_type
== BFD_RELOC_X86_64_32S
6139 || (reloc_type
== BFD_RELOC_64
6141 && (i
.op
[n
].disps
->X_op
== O_symbol
6142 || (i
.op
[n
].disps
->X_op
== O_add
6143 && ((symbol_get_value_expression
6144 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6146 || reloc_type
== BFD_RELOC_32_PCREL
))
6150 if (insn_start_frag
== frag_now
)
6151 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6156 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6157 for (fr
= insn_start_frag
->fr_next
;
6158 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6160 add
+= p
- frag_now
->fr_literal
;
6165 reloc_type
= BFD_RELOC_386_GOTPC
;
6166 i
.op
[n
].imms
->X_add_number
+= add
;
6168 else if (reloc_type
== BFD_RELOC_64
)
6169 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6171 /* Don't do the adjustment for x86-64, as there
6172 the pcrel addressing is relative to the _next_
6173 insn, and that is taken care of in other code. */
6174 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6176 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6177 i
.op
[n
].disps
, pcrel
, reloc_type
);
6184 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6189 for (n
= 0; n
< i
.operands
; n
++)
6191 if (operand_type_check (i
.types
[n
], imm
))
6193 if (i
.op
[n
].imms
->X_op
== O_constant
)
6195 int size
= imm_size (n
);
6198 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6200 p
= frag_more (size
);
6201 md_number_to_chars (p
, val
, size
);
6205 /* Not absolute_section.
6206 Need a 32-bit fixup (don't support 8bit
6207 non-absolute imms). Try to support other
6209 enum bfd_reloc_code_real reloc_type
;
6210 int size
= imm_size (n
);
6213 if (i
.types
[n
].bitfield
.imm32s
6214 && (i
.suffix
== QWORD_MNEM_SUFFIX
6215 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6220 p
= frag_more (size
);
6221 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6223 /* This is tough to explain. We end up with this one if we
6224 * have operands that look like
6225 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6226 * obtain the absolute address of the GOT, and it is strongly
6227 * preferable from a performance point of view to avoid using
6228 * a runtime relocation for this. The actual sequence of
6229 * instructions often look something like:
6234 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6236 * The call and pop essentially return the absolute address
6237 * of the label .L66 and store it in %ebx. The linker itself
6238 * will ultimately change the first operand of the addl so
6239 * that %ebx points to the GOT, but to keep things simple, the
6240 * .o file must have this operand set so that it generates not
6241 * the absolute address of .L66, but the absolute address of
6242 * itself. This allows the linker itself simply treat a GOTPC
6243 * relocation as asking for a pcrel offset to the GOT to be
6244 * added in, and the addend of the relocation is stored in the
6245 * operand field for the instruction itself.
6247 * Our job here is to fix the operand so that it would add
6248 * the correct offset so that %ebx would point to itself. The
6249 * thing that is tricky is that .-.L66 will point to the
6250 * beginning of the instruction, so we need to further modify
6251 * the operand so that it will point to itself. There are
6252 * other cases where you have something like:
6254 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6256 * and here no correction would be required. Internally in
6257 * the assembler we treat operands of this form as not being
6258 * pcrel since the '.' is explicitly mentioned, and I wonder
6259 * whether it would simplify matters to do it this way. Who
6260 * knows. In earlier versions of the PIC patches, the
6261 * pcrel_adjust field was used to store the correction, but
6262 * since the expression is not pcrel, I felt it would be
6263 * confusing to do it this way. */
6265 if ((reloc_type
== BFD_RELOC_32
6266 || reloc_type
== BFD_RELOC_X86_64_32S
6267 || reloc_type
== BFD_RELOC_64
)
6269 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6270 && (i
.op
[n
].imms
->X_op
== O_symbol
6271 || (i
.op
[n
].imms
->X_op
== O_add
6272 && ((symbol_get_value_expression
6273 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6278 if (insn_start_frag
== frag_now
)
6279 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6284 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6285 for (fr
= insn_start_frag
->fr_next
;
6286 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6288 add
+= p
- frag_now
->fr_literal
;
6292 reloc_type
= BFD_RELOC_386_GOTPC
;
6294 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6296 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6297 i
.op
[n
].imms
->X_add_number
+= add
;
6299 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6300 i
.op
[n
].imms
, 0, reloc_type
);
6306 /* x86_cons_fix_new is called via the expression parsing code when a
6307 reloc is needed. We use this hook to get the correct .got reloc. */
6308 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6309 static int cons_sign
= -1;
6312 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6315 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6317 got_reloc
= NO_RELOC
;
6320 if (exp
->X_op
== O_secrel
)
6322 exp
->X_op
= O_symbol
;
6323 r
= BFD_RELOC_32_SECREL
;
6327 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6330 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6331 # define lex_got(reloc, adjust, types) NULL
6333 /* Parse operands of the form
6334 <symbol>@GOTOFF+<nnn>
6335 and similar .plt or .got references.
6337 If we find one, set up the correct relocation in RELOC and copy the
6338 input string, minus the `@GOTOFF' into a malloc'd buffer for
6339 parsing by the calling routine. Return this buffer, and if ADJUST
6340 is non-null set it to the length of the string we removed from the
6341 input line. Otherwise return NULL. */
6343 lex_got (enum bfd_reloc_code_real
*rel
,
6345 i386_operand_type
*types
)
6347 /* Some of the relocations depend on the size of what field is to
6348 be relocated. But in our callers i386_immediate and i386_displacement
6349 we don't yet know the operand size (this will be set by insn
6350 matching). Hence we record the word32 relocation here,
6351 and adjust the reloc according to the real size in reloc(). */
6352 static const struct {
6355 const enum bfd_reloc_code_real rel
[2];
6356 const i386_operand_type types64
;
6358 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6359 BFD_RELOC_X86_64_PLTOFF64
},
6360 OPERAND_TYPE_IMM64
},
6361 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6362 BFD_RELOC_X86_64_PLT32
},
6363 OPERAND_TYPE_IMM32_32S_DISP32
},
6364 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6365 BFD_RELOC_X86_64_GOTPLT64
},
6366 OPERAND_TYPE_IMM64_DISP64
},
6367 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6368 BFD_RELOC_X86_64_GOTOFF64
},
6369 OPERAND_TYPE_IMM64_DISP64
},
6370 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6371 BFD_RELOC_X86_64_GOTPCREL
},
6372 OPERAND_TYPE_IMM32_32S_DISP32
},
6373 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6374 BFD_RELOC_X86_64_TLSGD
},
6375 OPERAND_TYPE_IMM32_32S_DISP32
},
6376 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6377 _dummy_first_bfd_reloc_code_real
},
6378 OPERAND_TYPE_NONE
},
6379 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6380 BFD_RELOC_X86_64_TLSLD
},
6381 OPERAND_TYPE_IMM32_32S_DISP32
},
6382 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6383 BFD_RELOC_X86_64_GOTTPOFF
},
6384 OPERAND_TYPE_IMM32_32S_DISP32
},
6385 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6386 BFD_RELOC_X86_64_TPOFF32
},
6387 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6388 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6389 _dummy_first_bfd_reloc_code_real
},
6390 OPERAND_TYPE_NONE
},
6391 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6392 BFD_RELOC_X86_64_DTPOFF32
},
6393 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6394 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6395 _dummy_first_bfd_reloc_code_real
},
6396 OPERAND_TYPE_NONE
},
6397 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6398 _dummy_first_bfd_reloc_code_real
},
6399 OPERAND_TYPE_NONE
},
6400 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6401 BFD_RELOC_X86_64_GOT32
},
6402 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6403 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6404 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6405 OPERAND_TYPE_IMM32_32S_DISP32
},
6406 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6407 BFD_RELOC_X86_64_TLSDESC_CALL
},
6408 OPERAND_TYPE_IMM32_32S_DISP32
},
6416 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6417 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6420 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6422 int len
= gotrel
[j
].len
;
6423 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6425 if (gotrel
[j
].rel
[object_64bit
] != 0)
6428 char *tmpbuf
, *past_reloc
;
6430 *rel
= gotrel
[j
].rel
[object_64bit
];
6436 if (flag_code
!= CODE_64BIT
)
6438 types
->bitfield
.imm32
= 1;
6439 types
->bitfield
.disp32
= 1;
6442 *types
= gotrel
[j
].types64
;
6445 if (GOT_symbol
== NULL
)
6446 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6448 /* The length of the first part of our input line. */
6449 first
= cp
- input_line_pointer
;
6451 /* The second part goes from after the reloc token until
6452 (and including) an end_of_line char or comma. */
6453 past_reloc
= cp
+ 1 + len
;
6455 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6457 second
= cp
+ 1 - past_reloc
;
6459 /* Allocate and copy string. The trailing NUL shouldn't
6460 be necessary, but be safe. */
6461 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6462 memcpy (tmpbuf
, input_line_pointer
, first
);
6463 if (second
!= 0 && *past_reloc
!= ' ')
6464 /* Replace the relocation token with ' ', so that
6465 errors like foo@GOTOFF1 will be detected. */
6466 tmpbuf
[first
++] = ' ';
6467 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6468 tmpbuf
[first
+ second
] = '\0';
6472 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6473 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6478 /* Might be a symbol version string. Don't as_bad here. */
6483 x86_cons (expressionS
*exp
, int size
)
6485 intel_syntax
= -intel_syntax
;
6488 if (size
== 4 || (object_64bit
&& size
== 8))
6490 /* Handle @GOTOFF and the like in an expression. */
6492 char *gotfree_input_line
;
6495 save
= input_line_pointer
;
6496 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6497 if (gotfree_input_line
)
6498 input_line_pointer
= gotfree_input_line
;
6502 if (gotfree_input_line
)
6504 /* expression () has merrily parsed up to the end of line,
6505 or a comma - in the wrong buffer. Transfer how far
6506 input_line_pointer has moved to the right buffer. */
6507 input_line_pointer
= (save
6508 + (input_line_pointer
- gotfree_input_line
)
6510 free (gotfree_input_line
);
6511 if (exp
->X_op
== O_constant
6512 || exp
->X_op
== O_absent
6513 || exp
->X_op
== O_illegal
6514 || exp
->X_op
== O_register
6515 || exp
->X_op
== O_big
)
6517 char c
= *input_line_pointer
;
6518 *input_line_pointer
= 0;
6519 as_bad (_("missing or invalid expression `%s'"), save
);
6520 *input_line_pointer
= c
;
6527 intel_syntax
= -intel_syntax
;
6530 i386_intel_simplify (exp
);
6535 signed_cons (int size
)
6537 if (flag_code
== CODE_64BIT
)
6545 pe_directive_secrel (dummy
)
6546 int dummy ATTRIBUTE_UNUSED
;
6553 if (exp
.X_op
== O_symbol
)
6554 exp
.X_op
= O_secrel
;
6556 emit_expr (&exp
, 4);
6558 while (*input_line_pointer
++ == ',');
6560 input_line_pointer
--;
6561 demand_empty_rest_of_line ();
6566 i386_immediate (char *imm_start
)
6568 char *save_input_line_pointer
;
6569 char *gotfree_input_line
;
6572 i386_operand_type types
;
6574 operand_type_set (&types
, ~0);
6576 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6578 as_bad (_("at most %d immediate operands are allowed"),
6579 MAX_IMMEDIATE_OPERANDS
);
6583 exp
= &im_expressions
[i
.imm_operands
++];
6584 i
.op
[this_operand
].imms
= exp
;
6586 if (is_space_char (*imm_start
))
6589 save_input_line_pointer
= input_line_pointer
;
6590 input_line_pointer
= imm_start
;
6592 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6593 if (gotfree_input_line
)
6594 input_line_pointer
= gotfree_input_line
;
6596 exp_seg
= expression (exp
);
6599 if (*input_line_pointer
)
6600 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6602 input_line_pointer
= save_input_line_pointer
;
6603 if (gotfree_input_line
)
6605 free (gotfree_input_line
);
6607 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6608 exp
->X_op
= O_illegal
;
6611 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6615 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6616 i386_operand_type types
, const char *imm_start
)
6618 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6621 as_bad (_("missing or invalid immediate expression `%s'"),
6625 else if (exp
->X_op
== O_constant
)
6627 /* Size it properly later. */
6628 i
.types
[this_operand
].bitfield
.imm64
= 1;
6629 /* If BFD64, sign extend val. */
6630 if (!use_rela_relocations
6631 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6633 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6635 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6636 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6637 && exp_seg
!= absolute_section
6638 && exp_seg
!= text_section
6639 && exp_seg
!= data_section
6640 && exp_seg
!= bss_section
6641 && exp_seg
!= undefined_section
6642 && !bfd_is_com_section (exp_seg
))
6644 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6648 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6651 as_bad (_("illegal immediate register operand %s"), imm_start
);
6656 /* This is an address. The size of the address will be
6657 determined later, depending on destination register,
6658 suffix, or the default for the section. */
6659 i
.types
[this_operand
].bitfield
.imm8
= 1;
6660 i
.types
[this_operand
].bitfield
.imm16
= 1;
6661 i
.types
[this_operand
].bitfield
.imm32
= 1;
6662 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6663 i
.types
[this_operand
].bitfield
.imm64
= 1;
6664 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6672 i386_scale (char *scale
)
6675 char *save
= input_line_pointer
;
6677 input_line_pointer
= scale
;
6678 val
= get_absolute_expression ();
6683 i
.log2_scale_factor
= 0;
6686 i
.log2_scale_factor
= 1;
6689 i
.log2_scale_factor
= 2;
6692 i
.log2_scale_factor
= 3;
6696 char sep
= *input_line_pointer
;
6698 *input_line_pointer
= '\0';
6699 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6701 *input_line_pointer
= sep
;
6702 input_line_pointer
= save
;
6706 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6708 as_warn (_("scale factor of %d without an index register"),
6709 1 << i
.log2_scale_factor
);
6710 i
.log2_scale_factor
= 0;
6712 scale
= input_line_pointer
;
6713 input_line_pointer
= save
;
6718 i386_displacement (char *disp_start
, char *disp_end
)
6722 char *save_input_line_pointer
;
6723 char *gotfree_input_line
;
6725 i386_operand_type bigdisp
, types
= anydisp
;
6728 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6730 as_bad (_("at most %d displacement operands are allowed"),
6731 MAX_MEMORY_OPERANDS
);
6735 operand_type_set (&bigdisp
, 0);
6736 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6737 || (!current_templates
->start
->opcode_modifier
.jump
6738 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6740 bigdisp
.bitfield
.disp32
= 1;
6741 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6742 if (flag_code
== CODE_64BIT
)
6746 bigdisp
.bitfield
.disp32s
= 1;
6747 bigdisp
.bitfield
.disp64
= 1;
6750 else if ((flag_code
== CODE_16BIT
) ^ override
)
6752 bigdisp
.bitfield
.disp32
= 0;
6753 bigdisp
.bitfield
.disp16
= 1;
6758 /* For PC-relative branches, the width of the displacement
6759 is dependent upon data size, not address size. */
6760 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6761 if (flag_code
== CODE_64BIT
)
6763 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6764 bigdisp
.bitfield
.disp16
= 1;
6767 bigdisp
.bitfield
.disp32
= 1;
6768 bigdisp
.bitfield
.disp32s
= 1;
6774 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6776 : LONG_MNEM_SUFFIX
));
6777 bigdisp
.bitfield
.disp32
= 1;
6778 if ((flag_code
== CODE_16BIT
) ^ override
)
6780 bigdisp
.bitfield
.disp32
= 0;
6781 bigdisp
.bitfield
.disp16
= 1;
6785 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6788 exp
= &disp_expressions
[i
.disp_operands
];
6789 i
.op
[this_operand
].disps
= exp
;
6791 save_input_line_pointer
= input_line_pointer
;
6792 input_line_pointer
= disp_start
;
6793 END_STRING_AND_SAVE (disp_end
);
6795 #ifndef GCC_ASM_O_HACK
6796 #define GCC_ASM_O_HACK 0
6799 END_STRING_AND_SAVE (disp_end
+ 1);
6800 if (i
.types
[this_operand
].bitfield
.baseIndex
6801 && displacement_string_end
[-1] == '+')
6803 /* This hack is to avoid a warning when using the "o"
6804 constraint within gcc asm statements.
6807 #define _set_tssldt_desc(n,addr,limit,type) \
6808 __asm__ __volatile__ ( \
6810 "movw %w1,2+%0\n\t" \
6812 "movb %b1,4+%0\n\t" \
6813 "movb %4,5+%0\n\t" \
6814 "movb $0,6+%0\n\t" \
6815 "movb %h1,7+%0\n\t" \
6817 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6819 This works great except that the output assembler ends
6820 up looking a bit weird if it turns out that there is
6821 no offset. You end up producing code that looks like:
6834 So here we provide the missing zero. */
6836 *displacement_string_end
= '0';
6839 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6840 if (gotfree_input_line
)
6841 input_line_pointer
= gotfree_input_line
;
6843 exp_seg
= expression (exp
);
6846 if (*input_line_pointer
)
6847 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6849 RESTORE_END_STRING (disp_end
+ 1);
6851 input_line_pointer
= save_input_line_pointer
;
6852 if (gotfree_input_line
)
6854 free (gotfree_input_line
);
6856 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6857 exp
->X_op
= O_illegal
;
6860 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6862 RESTORE_END_STRING (disp_end
);
6868 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6869 i386_operand_type types
, const char *disp_start
)
6871 i386_operand_type bigdisp
;
6874 /* We do this to make sure that the section symbol is in
6875 the symbol table. We will ultimately change the relocation
6876 to be relative to the beginning of the section. */
6877 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6878 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6879 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6881 if (exp
->X_op
!= O_symbol
)
6884 if (S_IS_LOCAL (exp
->X_add_symbol
)
6885 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
6886 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
6887 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6888 exp
->X_op
= O_subtract
;
6889 exp
->X_op_symbol
= GOT_symbol
;
6890 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6891 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6892 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6893 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6895 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6898 else if (exp
->X_op
== O_absent
6899 || exp
->X_op
== O_illegal
6900 || exp
->X_op
== O_big
)
6903 as_bad (_("missing or invalid displacement expression `%s'"),
6908 else if (flag_code
== CODE_64BIT
6909 && !i
.prefix
[ADDR_PREFIX
]
6910 && exp
->X_op
== O_constant
)
6912 /* Since displacement is signed extended to 64bit, don't allow
6913 disp32 and turn off disp32s if they are out of range. */
6914 i
.types
[this_operand
].bitfield
.disp32
= 0;
6915 if (!fits_in_signed_long (exp
->X_add_number
))
6917 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6918 if (i
.types
[this_operand
].bitfield
.baseindex
)
6920 as_bad (_("0x%lx out range of signed 32bit displacement"),
6921 (long) exp
->X_add_number
);
6927 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6928 else if (exp
->X_op
!= O_constant
6929 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6930 && exp_seg
!= absolute_section
6931 && exp_seg
!= text_section
6932 && exp_seg
!= data_section
6933 && exp_seg
!= bss_section
6934 && exp_seg
!= undefined_section
6935 && !bfd_is_com_section (exp_seg
))
6937 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6942 /* Check if this is a displacement only operand. */
6943 bigdisp
= i
.types
[this_operand
];
6944 bigdisp
.bitfield
.disp8
= 0;
6945 bigdisp
.bitfield
.disp16
= 0;
6946 bigdisp
.bitfield
.disp32
= 0;
6947 bigdisp
.bitfield
.disp32s
= 0;
6948 bigdisp
.bitfield
.disp64
= 0;
6949 if (operand_type_all_zero (&bigdisp
))
6950 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6956 /* Make sure the memory operand we've been dealt is valid.
6957 Return 1 on success, 0 on a failure. */
6960 i386_index_check (const char *operand_string
)
6963 const char *kind
= "base/index";
6964 #if INFER_ADDR_PREFIX
6970 if (current_templates
->start
->opcode_modifier
.isstring
6971 && !current_templates
->start
->opcode_modifier
.immext
6972 && (current_templates
->end
[-1].opcode_modifier
.isstring
6975 /* Memory operands of string insns are special in that they only allow
6976 a single register (rDI, rSI, or rBX) as their memory address. */
6977 unsigned int expected
;
6979 kind
= "string address";
6981 if (current_templates
->start
->opcode_modifier
.w
)
6983 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6985 if (!type
.bitfield
.baseindex
6986 || ((!i
.mem_operands
!= !intel_syntax
)
6987 && current_templates
->end
[-1].operand_types
[1]
6988 .bitfield
.baseindex
))
6989 type
= current_templates
->end
[-1].operand_types
[1];
6990 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6993 expected
= 3 /* rBX */;
6995 if (!i
.base_reg
|| i
.index_reg
6996 || operand_type_check (i
.types
[this_operand
], disp
))
6998 else if (!(flag_code
== CODE_64BIT
6999 ? i
.prefix
[ADDR_PREFIX
]
7000 ? i
.base_reg
->reg_type
.bitfield
.reg32
7001 : i
.base_reg
->reg_type
.bitfield
.reg64
7002 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7003 ? i
.base_reg
->reg_type
.bitfield
.reg32
7004 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7006 else if (i
.base_reg
->reg_num
!= expected
)
7013 for (j
= 0; j
< i386_regtab_size
; ++j
)
7014 if ((flag_code
== CODE_64BIT
7015 ? i
.prefix
[ADDR_PREFIX
]
7016 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7017 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7018 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7019 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7020 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7021 && i386_regtab
[j
].reg_num
== expected
)
7023 gas_assert (j
< i386_regtab_size
);
7024 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7026 intel_syntax
? '[' : '(',
7028 i386_regtab
[j
].reg_name
,
7029 intel_syntax
? ']' : ')');
7033 else if (flag_code
== CODE_64BIT
)
7036 && ((i
.prefix
[ADDR_PREFIX
] == 0
7037 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7038 || (i
.prefix
[ADDR_PREFIX
]
7039 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7041 || i
.base_reg
->reg_num
!=
7042 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7044 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7045 || (i
.prefix
[ADDR_PREFIX
] == 0
7046 && i
.index_reg
->reg_num
!= RegRiz
7047 && !i
.index_reg
->reg_type
.bitfield
.reg64
7049 || (i
.prefix
[ADDR_PREFIX
]
7050 && i
.index_reg
->reg_num
!= RegEiz
7051 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7056 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7060 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7061 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7063 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7064 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7066 && i
.base_reg
->reg_num
< 6
7067 && i
.index_reg
->reg_num
>= 6
7068 && i
.log2_scale_factor
== 0))))
7075 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7077 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7078 && i
.index_reg
->reg_num
!= RegEiz
)
7079 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7085 #if INFER_ADDR_PREFIX
7086 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7088 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7090 /* Change the size of any displacement too. At most one of
7091 Disp16 or Disp32 is set.
7092 FIXME. There doesn't seem to be any real need for separate
7093 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7094 Removing them would probably clean up the code quite a lot. */
7095 if (flag_code
!= CODE_64BIT
7096 && (i
.types
[this_operand
].bitfield
.disp16
7097 || i
.types
[this_operand
].bitfield
.disp32
))
7098 i
.types
[this_operand
]
7099 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7104 as_bad (_("`%s' is not a valid %s expression"),
7109 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7111 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7112 ? flag_code
== CODE_32BIT
7121 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7125 i386_att_operand (char *operand_string
)
7129 char *op_string
= operand_string
;
7131 if (is_space_char (*op_string
))
7134 /* We check for an absolute prefix (differentiating,
7135 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7136 if (*op_string
== ABSOLUTE_PREFIX
)
7139 if (is_space_char (*op_string
))
7141 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7144 /* Check if operand is a register. */
7145 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7147 i386_operand_type temp
;
7149 /* Check for a segment override by searching for ':' after a
7150 segment register. */
7152 if (is_space_char (*op_string
))
7154 if (*op_string
== ':'
7155 && (r
->reg_type
.bitfield
.sreg2
7156 || r
->reg_type
.bitfield
.sreg3
))
7161 i
.seg
[i
.mem_operands
] = &es
;
7164 i
.seg
[i
.mem_operands
] = &cs
;
7167 i
.seg
[i
.mem_operands
] = &ss
;
7170 i
.seg
[i
.mem_operands
] = &ds
;
7173 i
.seg
[i
.mem_operands
] = &fs
;
7176 i
.seg
[i
.mem_operands
] = &gs
;
7180 /* Skip the ':' and whitespace. */
7182 if (is_space_char (*op_string
))
7185 if (!is_digit_char (*op_string
)
7186 && !is_identifier_char (*op_string
)
7187 && *op_string
!= '('
7188 && *op_string
!= ABSOLUTE_PREFIX
)
7190 as_bad (_("bad memory operand `%s'"), op_string
);
7193 /* Handle case of %es:*foo. */
7194 if (*op_string
== ABSOLUTE_PREFIX
)
7197 if (is_space_char (*op_string
))
7199 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7201 goto do_memory_reference
;
7205 as_bad (_("junk `%s' after register"), op_string
);
7209 temp
.bitfield
.baseindex
= 0;
7210 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7212 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7213 i
.op
[this_operand
].regs
= r
;
7216 else if (*op_string
== REGISTER_PREFIX
)
7218 as_bad (_("bad register name `%s'"), op_string
);
7221 else if (*op_string
== IMMEDIATE_PREFIX
)
7224 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7226 as_bad (_("immediate operand illegal with absolute jump"));
7229 if (!i386_immediate (op_string
))
7232 else if (is_digit_char (*op_string
)
7233 || is_identifier_char (*op_string
)
7234 || *op_string
== '(')
7236 /* This is a memory reference of some sort. */
7239 /* Start and end of displacement string expression (if found). */
7240 char *displacement_string_start
;
7241 char *displacement_string_end
;
7243 do_memory_reference
:
7244 if ((i
.mem_operands
== 1
7245 && !current_templates
->start
->opcode_modifier
.isstring
)
7246 || i
.mem_operands
== 2)
7248 as_bad (_("too many memory references for `%s'"),
7249 current_templates
->start
->name
);
7253 /* Check for base index form. We detect the base index form by
7254 looking for an ')' at the end of the operand, searching
7255 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7257 base_string
= op_string
+ strlen (op_string
);
7260 if (is_space_char (*base_string
))
7263 /* If we only have a displacement, set-up for it to be parsed later. */
7264 displacement_string_start
= op_string
;
7265 displacement_string_end
= base_string
+ 1;
7267 if (*base_string
== ')')
7270 unsigned int parens_balanced
= 1;
7271 /* We've already checked that the number of left & right ()'s are
7272 equal, so this loop will not be infinite. */
7276 if (*base_string
== ')')
7278 if (*base_string
== '(')
7281 while (parens_balanced
);
7283 temp_string
= base_string
;
7285 /* Skip past '(' and whitespace. */
7287 if (is_space_char (*base_string
))
7290 if (*base_string
== ','
7291 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7294 displacement_string_end
= temp_string
;
7296 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7300 base_string
= end_op
;
7301 if (is_space_char (*base_string
))
7305 /* There may be an index reg or scale factor here. */
7306 if (*base_string
== ',')
7309 if (is_space_char (*base_string
))
7312 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7315 base_string
= end_op
;
7316 if (is_space_char (*base_string
))
7318 if (*base_string
== ',')
7321 if (is_space_char (*base_string
))
7324 else if (*base_string
!= ')')
7326 as_bad (_("expecting `,' or `)' "
7327 "after index register in `%s'"),
7332 else if (*base_string
== REGISTER_PREFIX
)
7334 as_bad (_("bad register name `%s'"), base_string
);
7338 /* Check for scale factor. */
7339 if (*base_string
!= ')')
7341 char *end_scale
= i386_scale (base_string
);
7346 base_string
= end_scale
;
7347 if (is_space_char (*base_string
))
7349 if (*base_string
!= ')')
7351 as_bad (_("expecting `)' "
7352 "after scale factor in `%s'"),
7357 else if (!i
.index_reg
)
7359 as_bad (_("expecting index register or scale factor "
7360 "after `,'; got '%c'"),
7365 else if (*base_string
!= ')')
7367 as_bad (_("expecting `,' or `)' "
7368 "after base register in `%s'"),
7373 else if (*base_string
== REGISTER_PREFIX
)
7375 as_bad (_("bad register name `%s'"), base_string
);
7380 /* If there's an expression beginning the operand, parse it,
7381 assuming displacement_string_start and
7382 displacement_string_end are meaningful. */
7383 if (displacement_string_start
!= displacement_string_end
)
7385 if (!i386_displacement (displacement_string_start
,
7386 displacement_string_end
))
7390 /* Special case for (%dx) while doing input/output op. */
7392 && operand_type_equal (&i
.base_reg
->reg_type
,
7393 ®16_inoutportreg
)
7395 && i
.log2_scale_factor
== 0
7396 && i
.seg
[i
.mem_operands
] == 0
7397 && !operand_type_check (i
.types
[this_operand
], disp
))
7399 i
.types
[this_operand
] = inoutportreg
;
7403 if (i386_index_check (operand_string
) == 0)
7405 i
.types
[this_operand
].bitfield
.mem
= 1;
7410 /* It's not a memory operand; argh! */
7411 as_bad (_("invalid char %s beginning operand %d `%s'"),
7412 output_invalid (*op_string
),
7417 return 1; /* Normal return. */
7420 /* md_estimate_size_before_relax()
7422 Called just before relax() for rs_machine_dependent frags. The x86
7423 assembler uses these frags to handle variable size jump
7426 Any symbol that is now undefined will not become defined.
7427 Return the correct fr_subtype in the frag.
7428 Return the initial "guess for variable size of frag" to caller.
7429 The guess is actually the growth beyond the fixed part. Whatever
7430 we do to grow the fixed or variable part contributes to our
7434 md_estimate_size_before_relax (fragP
, segment
)
7438 /* We've already got fragP->fr_subtype right; all we have to do is
7439 check for un-relaxable symbols. On an ELF system, we can't relax
7440 an externally visible symbol, because it may be overridden by a
7442 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7443 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7445 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7446 || S_IS_WEAK (fragP
->fr_symbol
)
7447 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7448 & BSF_GNU_INDIRECT_FUNCTION
))))
7450 #if defined (OBJ_COFF) && defined (TE_PE)
7451 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7452 && S_IS_WEAK (fragP
->fr_symbol
))
7456 /* Symbol is undefined in this segment, or we need to keep a
7457 reloc so that weak symbols can be overridden. */
7458 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7459 enum bfd_reloc_code_real reloc_type
;
7460 unsigned char *opcode
;
7463 if (fragP
->fr_var
!= NO_RELOC
)
7464 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7466 reloc_type
= BFD_RELOC_16_PCREL
;
7468 reloc_type
= BFD_RELOC_32_PCREL
;
7470 old_fr_fix
= fragP
->fr_fix
;
7471 opcode
= (unsigned char *) fragP
->fr_opcode
;
7473 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7476 /* Make jmp (0xeb) a (d)word displacement jump. */
7478 fragP
->fr_fix
+= size
;
7479 fix_new (fragP
, old_fr_fix
, size
,
7481 fragP
->fr_offset
, 1,
7487 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7489 /* Negate the condition, and branch past an
7490 unconditional jump. */
7493 /* Insert an unconditional jump. */
7495 /* We added two extra opcode bytes, and have a two byte
7497 fragP
->fr_fix
+= 2 + 2;
7498 fix_new (fragP
, old_fr_fix
+ 2, 2,
7500 fragP
->fr_offset
, 1,
7507 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7512 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7514 fragP
->fr_offset
, 1,
7516 fixP
->fx_signed
= 1;
7520 /* This changes the byte-displacement jump 0x7N
7521 to the (d)word-displacement jump 0x0f,0x8N. */
7522 opcode
[1] = opcode
[0] + 0x10;
7523 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7524 /* We've added an opcode byte. */
7525 fragP
->fr_fix
+= 1 + size
;
7526 fix_new (fragP
, old_fr_fix
+ 1, size
,
7528 fragP
->fr_offset
, 1,
7533 BAD_CASE (fragP
->fr_subtype
);
7537 return fragP
->fr_fix
- old_fr_fix
;
7540 /* Guess size depending on current relax state. Initially the relax
7541 state will correspond to a short jump and we return 1, because
7542 the variable part of the frag (the branch offset) is one byte
7543 long. However, we can relax a section more than once and in that
7544 case we must either set fr_subtype back to the unrelaxed state,
7545 or return the value for the appropriate branch. */
7546 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7549 /* Called after relax() is finished.
7551 In: Address of frag.
7552 fr_type == rs_machine_dependent.
7553 fr_subtype is what the address relaxed to.
7555 Out: Any fixSs and constants are set up.
7556 Caller will turn frag into a ".space 0". */
7559 md_convert_frag (abfd
, sec
, fragP
)
7560 bfd
*abfd ATTRIBUTE_UNUSED
;
7561 segT sec ATTRIBUTE_UNUSED
;
7564 unsigned char *opcode
;
7565 unsigned char *where_to_put_displacement
= NULL
;
7566 offsetT target_address
;
7567 offsetT opcode_address
;
7568 unsigned int extension
= 0;
7569 offsetT displacement_from_opcode_start
;
7571 opcode
= (unsigned char *) fragP
->fr_opcode
;
7573 /* Address we want to reach in file space. */
7574 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7576 /* Address opcode resides at in file space. */
7577 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7579 /* Displacement from opcode start to fill into instruction. */
7580 displacement_from_opcode_start
= target_address
- opcode_address
;
7582 if ((fragP
->fr_subtype
& BIG
) == 0)
7584 /* Don't have to change opcode. */
7585 extension
= 1; /* 1 opcode + 1 displacement */
7586 where_to_put_displacement
= &opcode
[1];
7590 if (no_cond_jump_promotion
7591 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7592 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7593 _("long jump required"));
7595 switch (fragP
->fr_subtype
)
7597 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7598 extension
= 4; /* 1 opcode + 4 displacement */
7600 where_to_put_displacement
= &opcode
[1];
7603 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7604 extension
= 2; /* 1 opcode + 2 displacement */
7606 where_to_put_displacement
= &opcode
[1];
7609 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7610 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7611 extension
= 5; /* 2 opcode + 4 displacement */
7612 opcode
[1] = opcode
[0] + 0x10;
7613 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7614 where_to_put_displacement
= &opcode
[2];
7617 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7618 extension
= 3; /* 2 opcode + 2 displacement */
7619 opcode
[1] = opcode
[0] + 0x10;
7620 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7621 where_to_put_displacement
= &opcode
[2];
7624 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7629 where_to_put_displacement
= &opcode
[3];
7633 BAD_CASE (fragP
->fr_subtype
);
7638 /* If size if less then four we are sure that the operand fits,
7639 but if it's 4, then it could be that the displacement is larger
7641 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7643 && ((addressT
) (displacement_from_opcode_start
- extension
7644 + ((addressT
) 1 << 31))
7645 > (((addressT
) 2 << 31) - 1)))
7647 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7648 _("jump target out of range"));
7649 /* Make us emit 0. */
7650 displacement_from_opcode_start
= extension
;
7652 /* Now put displacement after opcode. */
7653 md_number_to_chars ((char *) where_to_put_displacement
,
7654 (valueT
) (displacement_from_opcode_start
- extension
),
7655 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7656 fragP
->fr_fix
+= extension
;
7659 /* Apply a fixup (fixS) to segment data, once it has been determined
7660 by our caller that we have all the info we need to fix it up.
7662 On the 386, immediates, displacements, and data pointers are all in
7663 the same (little-endian) format, so we don't need to care about which
7667 md_apply_fix (fixP
, valP
, seg
)
7668 /* The fix we're to put in. */
7670 /* Pointer to the value of the bits. */
7672 /* Segment fix is from. */
7673 segT seg ATTRIBUTE_UNUSED
;
7675 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7676 valueT value
= *valP
;
7678 #if !defined (TE_Mach)
7681 switch (fixP
->fx_r_type
)
7687 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7690 case BFD_RELOC_X86_64_32S
:
7691 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7694 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7697 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7702 if (fixP
->fx_addsy
!= NULL
7703 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7704 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7705 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7706 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7707 && !use_rela_relocations
)
7709 /* This is a hack. There should be a better way to handle this.
7710 This covers for the fact that bfd_install_relocation will
7711 subtract the current location (for partial_inplace, PC relative
7712 relocations); see more below. */
7716 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7719 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7721 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7724 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7727 || (symbol_section_p (fixP
->fx_addsy
)
7728 && sym_seg
!= absolute_section
))
7729 && !generic_force_reloc (fixP
))
7731 /* Yes, we add the values in twice. This is because
7732 bfd_install_relocation subtracts them out again. I think
7733 bfd_install_relocation is broken, but I don't dare change
7735 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7739 #if defined (OBJ_COFF) && defined (TE_PE)
7740 /* For some reason, the PE format does not store a
7741 section address offset for a PC relative symbol. */
7742 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7743 || S_IS_WEAK (fixP
->fx_addsy
))
7744 value
+= md_pcrel_from (fixP
);
7747 #if defined (OBJ_COFF) && defined (TE_PE)
7748 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7750 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7754 /* Fix a few things - the dynamic linker expects certain values here,
7755 and we must not disappoint it. */
7756 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7757 if (IS_ELF
&& fixP
->fx_addsy
)
7758 switch (fixP
->fx_r_type
)
7760 case BFD_RELOC_386_PLT32
:
7761 case BFD_RELOC_X86_64_PLT32
:
7762 /* Make the jump instruction point to the address of the operand. At
7763 runtime we merely add the offset to the actual PLT entry. */
7767 case BFD_RELOC_386_TLS_GD
:
7768 case BFD_RELOC_386_TLS_LDM
:
7769 case BFD_RELOC_386_TLS_IE_32
:
7770 case BFD_RELOC_386_TLS_IE
:
7771 case BFD_RELOC_386_TLS_GOTIE
:
7772 case BFD_RELOC_386_TLS_GOTDESC
:
7773 case BFD_RELOC_X86_64_TLSGD
:
7774 case BFD_RELOC_X86_64_TLSLD
:
7775 case BFD_RELOC_X86_64_GOTTPOFF
:
7776 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7777 value
= 0; /* Fully resolved at runtime. No addend. */
7779 case BFD_RELOC_386_TLS_LE
:
7780 case BFD_RELOC_386_TLS_LDO_32
:
7781 case BFD_RELOC_386_TLS_LE_32
:
7782 case BFD_RELOC_X86_64_DTPOFF32
:
7783 case BFD_RELOC_X86_64_DTPOFF64
:
7784 case BFD_RELOC_X86_64_TPOFF32
:
7785 case BFD_RELOC_X86_64_TPOFF64
:
7786 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7789 case BFD_RELOC_386_TLS_DESC_CALL
:
7790 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7791 value
= 0; /* Fully resolved at runtime. No addend. */
7792 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7796 case BFD_RELOC_386_GOT32
:
7797 case BFD_RELOC_X86_64_GOT32
:
7798 value
= 0; /* Fully resolved at runtime. No addend. */
7801 case BFD_RELOC_VTABLE_INHERIT
:
7802 case BFD_RELOC_VTABLE_ENTRY
:
7809 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7811 #endif /* !defined (TE_Mach) */
7813 /* Are we finished with this relocation now? */
7814 if (fixP
->fx_addsy
== NULL
)
7816 #if defined (OBJ_COFF) && defined (TE_PE)
7817 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7820 /* Remember value for tc_gen_reloc. */
7821 fixP
->fx_addnumber
= value
;
7822 /* Clear out the frag for now. */
7826 else if (use_rela_relocations
)
7828 fixP
->fx_no_overflow
= 1;
7829 /* Remember value for tc_gen_reloc. */
7830 fixP
->fx_addnumber
= value
;
7834 md_number_to_chars (p
, value
, fixP
->fx_size
);
7838 md_atof (int type
, char *litP
, int *sizeP
)
7840 /* This outputs the LITTLENUMs in REVERSE order;
7841 in accord with the bigendian 386. */
7842 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7845 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7848 output_invalid (int c
)
7851 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7854 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7855 "(0x%x)", (unsigned char) c
);
7856 return output_invalid_buf
;
7859 /* REG_STRING starts *before* REGISTER_PREFIX. */
7861 static const reg_entry
*
7862 parse_real_register (char *reg_string
, char **end_op
)
7864 char *s
= reg_string
;
7866 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7869 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7870 if (*s
== REGISTER_PREFIX
)
7873 if (is_space_char (*s
))
7877 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7879 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7880 return (const reg_entry
*) NULL
;
7884 /* For naked regs, make sure that we are not dealing with an identifier.
7885 This prevents confusing an identifier like `eax_var' with register
7887 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7888 return (const reg_entry
*) NULL
;
7892 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7894 /* Handle floating point regs, allowing spaces in the (i) part. */
7895 if (r
== i386_regtab
/* %st is first entry of table */)
7897 if (is_space_char (*s
))
7902 if (is_space_char (*s
))
7904 if (*s
>= '0' && *s
<= '7')
7908 if (is_space_char (*s
))
7913 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7918 /* We have "%st(" then garbage. */
7919 return (const reg_entry
*) NULL
;
7923 if (r
== NULL
|| allow_pseudo_reg
)
7926 if (operand_type_all_zero (&r
->reg_type
))
7927 return (const reg_entry
*) NULL
;
7929 if ((r
->reg_type
.bitfield
.reg32
7930 || r
->reg_type
.bitfield
.sreg3
7931 || r
->reg_type
.bitfield
.control
7932 || r
->reg_type
.bitfield
.debug
7933 || r
->reg_type
.bitfield
.test
)
7934 && !cpu_arch_flags
.bitfield
.cpui386
)
7935 return (const reg_entry
*) NULL
;
7937 if (r
->reg_type
.bitfield
.floatreg
7938 && !cpu_arch_flags
.bitfield
.cpu8087
7939 && !cpu_arch_flags
.bitfield
.cpu287
7940 && !cpu_arch_flags
.bitfield
.cpu387
)
7941 return (const reg_entry
*) NULL
;
7943 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7944 return (const reg_entry
*) NULL
;
7946 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7947 return (const reg_entry
*) NULL
;
7949 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7950 return (const reg_entry
*) NULL
;
7952 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7953 if (!allow_index_reg
7954 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7955 return (const reg_entry
*) NULL
;
7957 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7958 || r
->reg_type
.bitfield
.reg64
)
7959 && (!cpu_arch_flags
.bitfield
.cpulm
7960 || !operand_type_equal (&r
->reg_type
, &control
))
7961 && flag_code
!= CODE_64BIT
)
7962 return (const reg_entry
*) NULL
;
7964 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7965 return (const reg_entry
*) NULL
;
7970 /* REG_STRING starts *before* REGISTER_PREFIX. */
7972 static const reg_entry
*
7973 parse_register (char *reg_string
, char **end_op
)
7977 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7978 r
= parse_real_register (reg_string
, end_op
);
7983 char *save
= input_line_pointer
;
7987 input_line_pointer
= reg_string
;
7988 c
= get_symbol_end ();
7989 symbolP
= symbol_find (reg_string
);
7990 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7992 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7994 know (e
->X_op
== O_register
);
7995 know (e
->X_add_number
>= 0
7996 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7997 r
= i386_regtab
+ e
->X_add_number
;
7998 *end_op
= input_line_pointer
;
8000 *input_line_pointer
= c
;
8001 input_line_pointer
= save
;
8007 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8010 char *end
= input_line_pointer
;
8013 r
= parse_register (name
, &input_line_pointer
);
8014 if (r
&& end
<= input_line_pointer
)
8016 *nextcharP
= *input_line_pointer
;
8017 *input_line_pointer
= 0;
8018 e
->X_op
= O_register
;
8019 e
->X_add_number
= r
- i386_regtab
;
8022 input_line_pointer
= end
;
8024 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8028 md_operand (expressionS
*e
)
8033 switch (*input_line_pointer
)
8035 case REGISTER_PREFIX
:
8036 r
= parse_real_register (input_line_pointer
, &end
);
8039 e
->X_op
= O_register
;
8040 e
->X_add_number
= r
- i386_regtab
;
8041 input_line_pointer
= end
;
8046 gas_assert (intel_syntax
);
8047 end
= input_line_pointer
++;
8049 if (*input_line_pointer
== ']')
8051 ++input_line_pointer
;
8052 e
->X_op_symbol
= make_expr_symbol (e
);
8053 e
->X_add_symbol
= NULL
;
8054 e
->X_add_number
= 0;
8060 input_line_pointer
= end
;
8067 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8068 const char *md_shortopts
= "kVQ:sqn";
8070 const char *md_shortopts
= "qn";
8073 #define OPTION_32 (OPTION_MD_BASE + 0)
8074 #define OPTION_64 (OPTION_MD_BASE + 1)
8075 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8076 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8077 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8078 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8079 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8080 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8081 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8082 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8083 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8084 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8085 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8087 struct option md_longopts
[] =
8089 {"32", no_argument
, NULL
, OPTION_32
},
8090 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8091 || defined (TE_PE) || defined (TE_PEP))
8092 {"64", no_argument
, NULL
, OPTION_64
},
8094 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8095 {"march", required_argument
, NULL
, OPTION_MARCH
},
8096 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8097 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8098 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8099 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8100 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8101 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8102 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8103 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8104 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8105 {NULL
, no_argument
, NULL
, 0}
8107 size_t md_longopts_size
= sizeof (md_longopts
);
8110 md_parse_option (int c
, char *arg
)
8118 optimize_align_code
= 0;
8125 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8126 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8127 should be emitted or not. FIXME: Not implemented. */
8131 /* -V: SVR4 argument to print version ID. */
8133 print_version_id ();
8136 /* -k: Ignore for FreeBSD compatibility. */
8141 /* -s: On i386 Solaris, this tells the native assembler to use
8142 .stab instead of .stab.excl. We always use .stab anyhow. */
8145 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8146 || defined (TE_PE) || defined (TE_PEP))
8149 const char **list
, **l
;
8151 list
= bfd_target_list ();
8152 for (l
= list
; *l
!= NULL
; l
++)
8153 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8154 || strcmp (*l
, "coff-x86-64") == 0
8155 || strcmp (*l
, "pe-x86-64") == 0
8156 || strcmp (*l
, "pei-x86-64") == 0)
8158 default_arch
= "x86_64";
8162 as_fatal (_("No compiled in support for x86_64"));
8169 default_arch
= "i386";
8173 #ifdef SVR4_COMMENT_CHARS
8178 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8180 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8184 i386_comment_chars
= n
;
8190 arch
= xstrdup (arg
);
8194 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8195 next
= strchr (arch
, '+');
8198 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8200 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8203 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8206 cpu_arch_name
= cpu_arch
[j
].name
;
8207 cpu_sub_arch_name
= NULL
;
8208 cpu_arch_flags
= cpu_arch
[j
].flags
;
8209 cpu_arch_isa
= cpu_arch
[j
].type
;
8210 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8211 if (!cpu_arch_tune_set
)
8213 cpu_arch_tune
= cpu_arch_isa
;
8214 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8218 else if (*cpu_arch
[j
].name
== '.'
8219 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8221 /* ISA entension. */
8222 i386_cpu_flags flags
;
8224 if (!cpu_arch
[j
].negated
)
8225 flags
= cpu_flags_or (cpu_arch_flags
,
8228 flags
= cpu_flags_and_not (cpu_arch_flags
,
8230 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8232 if (cpu_sub_arch_name
)
8234 char *name
= cpu_sub_arch_name
;
8235 cpu_sub_arch_name
= concat (name
,
8237 (const char *) NULL
);
8241 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8242 cpu_arch_flags
= flags
;
8248 if (j
>= ARRAY_SIZE (cpu_arch
))
8249 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8253 while (next
!= NULL
);
8258 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8259 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8261 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8263 cpu_arch_tune_set
= 1;
8264 cpu_arch_tune
= cpu_arch
[j
].type
;
8265 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8269 if (j
>= ARRAY_SIZE (cpu_arch
))
8270 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8273 case OPTION_MMNEMONIC
:
8274 if (strcasecmp (arg
, "att") == 0)
8276 else if (strcasecmp (arg
, "intel") == 0)
8279 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8282 case OPTION_MSYNTAX
:
8283 if (strcasecmp (arg
, "att") == 0)
8285 else if (strcasecmp (arg
, "intel") == 0)
8288 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8291 case OPTION_MINDEX_REG
:
8292 allow_index_reg
= 1;
8295 case OPTION_MNAKED_REG
:
8296 allow_naked_reg
= 1;
8299 case OPTION_MOLD_GCC
:
8303 case OPTION_MSSE2AVX
:
8307 case OPTION_MSSE_CHECK
:
8308 if (strcasecmp (arg
, "error") == 0)
8309 sse_check
= sse_check_error
;
8310 else if (strcasecmp (arg
, "warning") == 0)
8311 sse_check
= sse_check_warning
;
8312 else if (strcasecmp (arg
, "none") == 0)
8313 sse_check
= sse_check_none
;
8315 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8318 case OPTION_MAVXSCALAR
:
8319 if (strcasecmp (arg
, "128") == 0)
8321 else if (strcasecmp (arg
, "256") == 0)
8324 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8333 #define MESSAGE_TEMPLATE \
8337 show_arch (FILE *stream
, int ext
, int check
)
8339 static char message
[] = MESSAGE_TEMPLATE
;
8340 char *start
= message
+ 27;
8342 int size
= sizeof (MESSAGE_TEMPLATE
);
8349 left
= size
- (start
- message
);
8350 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8352 /* Should it be skipped? */
8353 if (cpu_arch
[j
].skip
)
8356 name
= cpu_arch
[j
].name
;
8357 len
= cpu_arch
[j
].len
;
8360 /* It is an extension. Skip if we aren't asked to show it. */
8371 /* It is an processor. Skip if we show only extension. */
8374 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8376 /* It is an impossible processor - skip. */
8380 /* Reserve 2 spaces for ", " or ",\0" */
8383 /* Check if there is any room. */
8391 p
= mempcpy (p
, name
, len
);
8395 /* Output the current message now and start a new one. */
8398 fprintf (stream
, "%s\n", message
);
8400 left
= size
- (start
- message
) - len
- 2;
8402 gas_assert (left
>= 0);
8404 p
= mempcpy (p
, name
, len
);
8409 fprintf (stream
, "%s\n", message
);
8413 md_show_usage (FILE *stream
)
8415 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8416 fprintf (stream
, _("\
8418 -V print assembler version number\n\
8421 fprintf (stream
, _("\
8422 -n Do not optimize code alignment\n\
8423 -q quieten some warnings\n"));
8424 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8425 fprintf (stream
, _("\
8428 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8429 || defined (TE_PE) || defined (TE_PEP))
8430 fprintf (stream
, _("\
8431 --32/--64 generate 32bit/64bit code\n"));
8433 #ifdef SVR4_COMMENT_CHARS
8434 fprintf (stream
, _("\
8435 --divide do not treat `/' as a comment character\n"));
8437 fprintf (stream
, _("\
8438 --divide ignored\n"));
8440 fprintf (stream
, _("\
8441 -march=CPU[,+EXTENSION...]\n\
8442 generate code for CPU and EXTENSION, CPU is one of:\n"));
8443 show_arch (stream
, 0, 1);
8444 fprintf (stream
, _("\
8445 EXTENSION is combination of:\n"));
8446 show_arch (stream
, 1, 0);
8447 fprintf (stream
, _("\
8448 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8449 show_arch (stream
, 0, 0);
8450 fprintf (stream
, _("\
8451 -msse2avx encode SSE instructions with VEX prefix\n"));
8452 fprintf (stream
, _("\
8453 -msse-check=[none|error|warning]\n\
8454 check SSE instructions\n"));
8455 fprintf (stream
, _("\
8456 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8458 fprintf (stream
, _("\
8459 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8460 fprintf (stream
, _("\
8461 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8462 fprintf (stream
, _("\
8463 -mindex-reg support pseudo index registers\n"));
8464 fprintf (stream
, _("\
8465 -mnaked-reg don't require `%%' prefix for registers\n"));
8466 fprintf (stream
, _("\
8467 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8470 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8471 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8472 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8474 /* Pick the target format to use. */
8477 i386_target_format (void)
8479 if (!strcmp (default_arch
, "x86_64"))
8480 update_code_flag (CODE_64BIT
, 1);
8481 else if (!strcmp (default_arch
, "i386"))
8482 update_code_flag (CODE_32BIT
, 1);
8484 as_fatal (_("Unknown architecture"));
8486 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8487 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8488 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8489 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8491 switch (OUTPUT_FLAVOR
)
8493 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8494 case bfd_target_aout_flavour
:
8495 return AOUT_TARGET_FORMAT
;
8497 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8498 # if defined (TE_PE) || defined (TE_PEP)
8499 case bfd_target_coff_flavour
:
8500 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8501 # elif defined (TE_GO32)
8502 case bfd_target_coff_flavour
:
8505 case bfd_target_coff_flavour
:
8509 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8510 case bfd_target_elf_flavour
:
8512 if (flag_code
== CODE_64BIT
)
8515 use_rela_relocations
= 1;
8517 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8519 if (flag_code
!= CODE_64BIT
)
8520 as_fatal (_("Intel L1OM is 64bit only"));
8521 return ELF_TARGET_L1OM_FORMAT
;
8524 return (flag_code
== CODE_64BIT
8525 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8528 #if defined (OBJ_MACH_O)
8529 case bfd_target_mach_o_flavour
:
8530 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8538 #endif /* OBJ_MAYBE_ more than one */
8540 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8542 i386_elf_emit_arch_note (void)
8544 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8547 asection
*seg
= now_seg
;
8548 subsegT subseg
= now_subseg
;
8549 Elf_Internal_Note i_note
;
8550 Elf_External_Note e_note
;
8551 asection
*note_secp
;
8554 /* Create the .note section. */
8555 note_secp
= subseg_new (".note", 0);
8556 bfd_set_section_flags (stdoutput
,
8558 SEC_HAS_CONTENTS
| SEC_READONLY
);
8560 /* Process the arch string. */
8561 len
= strlen (cpu_arch_name
);
8563 i_note
.namesz
= len
+ 1;
8565 i_note
.type
= NT_ARCH
;
8566 p
= frag_more (sizeof (e_note
.namesz
));
8567 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8568 p
= frag_more (sizeof (e_note
.descsz
));
8569 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8570 p
= frag_more (sizeof (e_note
.type
));
8571 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8572 p
= frag_more (len
+ 1);
8573 strcpy (p
, cpu_arch_name
);
8575 frag_align (2, 0, 0);
8577 subseg_set (seg
, subseg
);
8583 md_undefined_symbol (name
)
8586 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8587 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8588 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8589 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8593 if (symbol_find (name
))
8594 as_bad (_("GOT already in symbol table"));
8595 GOT_symbol
= symbol_new (name
, undefined_section
,
8596 (valueT
) 0, &zero_address_frag
);
8603 /* Round up a section size to the appropriate boundary. */
8606 md_section_align (segment
, size
)
8607 segT segment ATTRIBUTE_UNUSED
;
8610 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8611 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8613 /* For a.out, force the section size to be aligned. If we don't do
8614 this, BFD will align it for us, but it will not write out the
8615 final bytes of the section. This may be a bug in BFD, but it is
8616 easier to fix it here since that is how the other a.out targets
8620 align
= bfd_get_section_alignment (stdoutput
, segment
);
8621 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8628 /* On the i386, PC-relative offsets are relative to the start of the
8629 next instruction. That is, the address of the offset, plus its
8630 size, since the offset is always the last part of the insn. */
8633 md_pcrel_from (fixS
*fixP
)
8635 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8641 s_bss (int ignore ATTRIBUTE_UNUSED
)
8645 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8647 obj_elf_section_change_hook ();
8649 temp
= get_absolute_expression ();
8650 subseg_set (bss_section
, (subsegT
) temp
);
8651 demand_empty_rest_of_line ();
8657 i386_validate_fix (fixS
*fixp
)
8659 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8661 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8665 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8670 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8672 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8679 tc_gen_reloc (section
, fixp
)
8680 asection
*section ATTRIBUTE_UNUSED
;
8684 bfd_reloc_code_real_type code
;
8686 switch (fixp
->fx_r_type
)
8688 case BFD_RELOC_X86_64_PLT32
:
8689 case BFD_RELOC_X86_64_GOT32
:
8690 case BFD_RELOC_X86_64_GOTPCREL
:
8691 case BFD_RELOC_386_PLT32
:
8692 case BFD_RELOC_386_GOT32
:
8693 case BFD_RELOC_386_GOTOFF
:
8694 case BFD_RELOC_386_GOTPC
:
8695 case BFD_RELOC_386_TLS_GD
:
8696 case BFD_RELOC_386_TLS_LDM
:
8697 case BFD_RELOC_386_TLS_LDO_32
:
8698 case BFD_RELOC_386_TLS_IE_32
:
8699 case BFD_RELOC_386_TLS_IE
:
8700 case BFD_RELOC_386_TLS_GOTIE
:
8701 case BFD_RELOC_386_TLS_LE_32
:
8702 case BFD_RELOC_386_TLS_LE
:
8703 case BFD_RELOC_386_TLS_GOTDESC
:
8704 case BFD_RELOC_386_TLS_DESC_CALL
:
8705 case BFD_RELOC_X86_64_TLSGD
:
8706 case BFD_RELOC_X86_64_TLSLD
:
8707 case BFD_RELOC_X86_64_DTPOFF32
:
8708 case BFD_RELOC_X86_64_DTPOFF64
:
8709 case BFD_RELOC_X86_64_GOTTPOFF
:
8710 case BFD_RELOC_X86_64_TPOFF32
:
8711 case BFD_RELOC_X86_64_TPOFF64
:
8712 case BFD_RELOC_X86_64_GOTOFF64
:
8713 case BFD_RELOC_X86_64_GOTPC32
:
8714 case BFD_RELOC_X86_64_GOT64
:
8715 case BFD_RELOC_X86_64_GOTPCREL64
:
8716 case BFD_RELOC_X86_64_GOTPC64
:
8717 case BFD_RELOC_X86_64_GOTPLT64
:
8718 case BFD_RELOC_X86_64_PLTOFF64
:
8719 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8720 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8722 case BFD_RELOC_VTABLE_ENTRY
:
8723 case BFD_RELOC_VTABLE_INHERIT
:
8725 case BFD_RELOC_32_SECREL
:
8727 code
= fixp
->fx_r_type
;
8729 case BFD_RELOC_X86_64_32S
:
8730 if (!fixp
->fx_pcrel
)
8732 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8733 code
= fixp
->fx_r_type
;
8739 switch (fixp
->fx_size
)
8742 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8743 _("can not do %d byte pc-relative relocation"),
8745 code
= BFD_RELOC_32_PCREL
;
8747 case 1: code
= BFD_RELOC_8_PCREL
; break;
8748 case 2: code
= BFD_RELOC_16_PCREL
; break;
8749 case 4: code
= BFD_RELOC_32_PCREL
; break;
8751 case 8: code
= BFD_RELOC_64_PCREL
; break;
8757 switch (fixp
->fx_size
)
8760 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8761 _("can not do %d byte relocation"),
8763 code
= BFD_RELOC_32
;
8765 case 1: code
= BFD_RELOC_8
; break;
8766 case 2: code
= BFD_RELOC_16
; break;
8767 case 4: code
= BFD_RELOC_32
; break;
8769 case 8: code
= BFD_RELOC_64
; break;
8776 if ((code
== BFD_RELOC_32
8777 || code
== BFD_RELOC_32_PCREL
8778 || code
== BFD_RELOC_X86_64_32S
)
8780 && fixp
->fx_addsy
== GOT_symbol
)
8783 code
= BFD_RELOC_386_GOTPC
;
8785 code
= BFD_RELOC_X86_64_GOTPC32
;
8787 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8789 && fixp
->fx_addsy
== GOT_symbol
)
8791 code
= BFD_RELOC_X86_64_GOTPC64
;
8794 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8795 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8796 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8798 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8800 if (!use_rela_relocations
)
8802 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8803 vtable entry to be used in the relocation's section offset. */
8804 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8805 rel
->address
= fixp
->fx_offset
;
8806 #if defined (OBJ_COFF) && defined (TE_PE)
8807 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8808 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8813 /* Use the rela in 64bit mode. */
8816 if (!fixp
->fx_pcrel
)
8817 rel
->addend
= fixp
->fx_offset
;
8821 case BFD_RELOC_X86_64_PLT32
:
8822 case BFD_RELOC_X86_64_GOT32
:
8823 case BFD_RELOC_X86_64_GOTPCREL
:
8824 case BFD_RELOC_X86_64_TLSGD
:
8825 case BFD_RELOC_X86_64_TLSLD
:
8826 case BFD_RELOC_X86_64_GOTTPOFF
:
8827 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8828 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8829 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8832 rel
->addend
= (section
->vma
8834 + fixp
->fx_addnumber
8835 + md_pcrel_from (fixp
));
8840 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8841 if (rel
->howto
== NULL
)
8843 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8844 _("cannot represent relocation type %s"),
8845 bfd_get_reloc_code_name (code
));
8846 /* Set howto to a garbage value so that we can keep going. */
8847 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8848 gas_assert (rel
->howto
!= NULL
);
8854 #include "tc-i386-intel.c"
8857 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8859 int saved_naked_reg
;
8860 char saved_register_dot
;
8862 saved_naked_reg
= allow_naked_reg
;
8863 allow_naked_reg
= 1;
8864 saved_register_dot
= register_chars
['.'];
8865 register_chars
['.'] = '.';
8866 allow_pseudo_reg
= 1;
8867 expression_and_evaluate (exp
);
8868 allow_pseudo_reg
= 0;
8869 register_chars
['.'] = saved_register_dot
;
8870 allow_naked_reg
= saved_naked_reg
;
8872 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8874 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8876 exp
->X_op
= O_constant
;
8877 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8878 .dw2_regnum
[flag_code
>> 1];
8881 exp
->X_op
= O_illegal
;
8886 tc_x86_frame_initial_instructions (void)
8888 static unsigned int sp_regno
[2];
8890 if (!sp_regno
[flag_code
>> 1])
8892 char *saved_input
= input_line_pointer
;
8893 char sp
[][4] = {"esp", "rsp"};
8896 input_line_pointer
= sp
[flag_code
>> 1];
8897 tc_x86_parse_to_dw2regnum (&exp
);
8898 gas_assert (exp
.X_op
== O_constant
);
8899 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8900 input_line_pointer
= saved_input
;
8903 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8904 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8908 i386_elf_section_type (const char *str
, size_t len
)
8910 if (flag_code
== CODE_64BIT
8911 && len
== sizeof ("unwind") - 1
8912 && strncmp (str
, "unwind", 6) == 0)
8913 return SHT_X86_64_UNWIND
;
8920 i386_solaris_fix_up_eh_frame (segT sec
)
8922 if (flag_code
== CODE_64BIT
)
8923 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8929 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8933 exp
.X_op
= O_secrel
;
8934 exp
.X_add_symbol
= symbol
;
8935 exp
.X_add_number
= 0;
8936 emit_expr (&exp
, size
);
8940 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8941 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8944 x86_64_section_letter (int letter
, char **ptr_msg
)
8946 if (flag_code
== CODE_64BIT
)
8949 return SHF_X86_64_LARGE
;
8951 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8954 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8959 x86_64_section_word (char *str
, size_t len
)
8961 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8962 return SHF_X86_64_LARGE
;
8968 handle_large_common (int small ATTRIBUTE_UNUSED
)
8970 if (flag_code
!= CODE_64BIT
)
8972 s_comm_internal (0, elf_common_parse
);
8973 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8977 static segT lbss_section
;
8978 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8979 asection
*saved_bss_section
= bss_section
;
8981 if (lbss_section
== NULL
)
8983 flagword applicable
;
8985 subsegT subseg
= now_subseg
;
8987 /* The .lbss section is for local .largecomm symbols. */
8988 lbss_section
= subseg_new (".lbss", 0);
8989 applicable
= bfd_applicable_section_flags (stdoutput
);
8990 bfd_set_section_flags (stdoutput
, lbss_section
,
8991 applicable
& SEC_ALLOC
);
8992 seg_info (lbss_section
)->bss
= 1;
8994 subseg_set (seg
, subseg
);
8997 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8998 bss_section
= lbss_section
;
9000 s_comm_internal (0, elf_common_parse
);
9002 elf_com_section_ptr
= saved_com_section_ptr
;
9003 bss_section
= saved_bss_section
;
9006 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */