1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void set_code_flag (int);
139 static void set_16bit_gcc_code_flag (int);
140 static void set_intel_syntax (int);
141 static void set_intel_mnemonic (int);
142 static void set_allow_index_reg (int);
143 static void set_sse_check (int);
144 static void set_cpu_arch (int);
146 static void pe_directive_secrel (int);
148 static void signed_cons (int);
149 static char *output_invalid (int c
);
150 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
152 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
154 static int i386_att_operand (char *);
155 static int i386_intel_operand (char *, int);
156 static int i386_intel_simplify (expressionS
*);
157 static int i386_intel_parse_name (const char *, expressionS
*);
158 static const reg_entry
*parse_register (char *, char **);
159 static char *parse_insn (char *, char *);
160 static char *parse_operands (char *, const char *);
161 static void swap_operands (void);
162 static void swap_2_operands (int, int);
163 static void optimize_imm (void);
164 static void optimize_disp (void);
165 static const insn_template
*match_template (void);
166 static int check_string (void);
167 static int process_suffix (void);
168 static int check_byte_reg (void);
169 static int check_long_reg (void);
170 static int check_qword_reg (void);
171 static int check_word_reg (void);
172 static int finalize_imm (void);
173 static int process_operands (void);
174 static const seg_entry
*build_modrm_byte (void);
175 static void output_insn (void);
176 static void output_imm (fragS
*, offsetT
);
177 static void output_disp (fragS
*, offsetT
);
179 static void s_bss (int);
181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
185 static const char *default_arch
= DEFAULT_ARCH
;
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes
[3];
193 /* Destination or source register specifier. */
194 const reg_entry
*register_specifier
;
197 /* 'md_assemble ()' gathers together information and puts it into a
204 const reg_entry
*regs
;
209 /* TM holds the template for the insn were currently assembling. */
212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
216 /* OPERANDS gives the number of given operands. */
217 unsigned int operands
;
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
222 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
224 /* TYPES [i] is the type (see above #defines) which tells us how to
225 use OP[i] for the corresponding operand. */
226 i386_operand_type types
[MAX_OPERANDS
];
228 /* Displacement expression, immediate expression, or register for each
230 union i386_op op
[MAX_OPERANDS
];
232 /* Flags for operands. */
233 unsigned int flags
[MAX_OPERANDS
];
234 #define Operand_PCrel 1
236 /* Relocation type for operand */
237 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry
*base_reg
;
242 const reg_entry
*index_reg
;
243 unsigned int log2_scale_factor
;
245 /* SEG gives the seg_entries of this insn. They are zero unless
246 explicit segment overrides are given. */
247 const seg_entry
*seg
[2];
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes
;
252 unsigned char prefix
[MAX_PREFIXES
];
254 /* RM and SIB are the modrm byte and the sib byte where the
255 addressing modes of this insn are encoded. */
261 /* Swap operand in encoding. */
262 unsigned int swap_operand
;
265 typedef struct _i386_insn i386_insn
;
267 /* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
269 const char extra_symbol_chars
[] = "*%-(["
278 #if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
280 && !defined (TE_GNU) \
281 && !defined (TE_LINUX) \
282 && !defined (TE_NETWARE) \
283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
285 /* This array holds the chars that always start a comment. If the
286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288 const char *i386_comment_chars
= "#/";
289 #define SVR4_COMMENT_CHARS 1
290 #define PREFIX_SEPARATOR '\\'
293 const char *i386_comment_chars
= "#";
294 #define PREFIX_SEPARATOR '/'
297 /* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
301 first line of the input file. This is because the compiler outputs
302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
304 '/' isn't otherwise defined. */
305 const char line_comment_chars
[] = "#/";
307 const char line_separator_chars
[] = ";";
309 /* Chars that can be used to separate mant from exp in floating point
311 const char EXP_CHARS
[] = "eE";
313 /* Chars that mean this number is a floating point constant
316 const char FLT_CHARS
[] = "fFdDxX";
318 /* Tables for lexical analysis. */
319 static char mnemonic_chars
[256];
320 static char register_chars
[256];
321 static char operand_chars
[256];
322 static char identifier_chars
[256];
323 static char digit_chars
[256];
325 /* Lexical macros. */
326 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327 #define is_operand_char(x) (operand_chars[(unsigned char) x])
328 #define is_register_char(x) (register_chars[(unsigned char) x])
329 #define is_space_char(x) ((x) == ' ')
330 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331 #define is_digit_char(x) (digit_chars[(unsigned char) x])
333 /* All non-digit non-letter characters that may occur in an operand. */
334 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
336 /* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
339 assembler instruction). */
340 static char save_stack
[32];
341 static char *save_stack_p
;
342 #define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344 #define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
347 /* The instruction we're assembling. */
350 /* Possible templates for current insn. */
351 static const templates
*current_templates
;
353 /* Per instruction expressionS buffers: max displacements & immediates. */
354 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
355 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
357 /* Current operand we are working on. */
358 static int this_operand
= -1;
360 /* We support four different modes. FLAG_CODE variable is used to distinguish
368 static enum flag_code flag_code
;
369 static unsigned int object_64bit
;
370 static int use_rela_relocations
= 0;
372 /* The names used to print error messages. */
373 static const char *flag_code_names
[] =
380 /* 1 for intel syntax,
382 static int intel_syntax
= 0;
384 /* 1 for intel mnemonic,
385 0 if att mnemonic. */
386 static int intel_mnemonic
= !SYSV386_COMPAT
;
388 /* 1 if support old (<= 2.8.1) versions of gcc. */
389 static int old_gcc
= OLDGCC_COMPAT
;
391 /* 1 if pseudo registers are permitted. */
392 static int allow_pseudo_reg
= 0;
394 /* 1 if register prefix % not required. */
395 static int allow_naked_reg
= 0;
397 /* 1 if pseudo index register, eiz/riz, is allowed . */
398 static int allow_index_reg
= 0;
408 /* Register prefix used for error message. */
409 static const char *register_prefix
= "%";
411 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414 static char stackop_size
= '\0';
416 /* Non-zero to optimize code alignment. */
417 int optimize_align_code
= 1;
419 /* Non-zero to quieten some warnings. */
420 static int quiet_warnings
= 0;
423 static const char *cpu_arch_name
= NULL
;
424 static char *cpu_sub_arch_name
= NULL
;
426 /* CPU feature flags. */
427 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
429 /* If we have selected a cpu we are generating instructions for. */
430 static int cpu_arch_tune_set
= 0;
432 /* Cpu we are generating instructions for. */
433 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
435 /* CPU feature flags of cpu we are generating instructions for. */
436 static i386_cpu_flags cpu_arch_tune_flags
;
438 /* CPU instruction set architecture used. */
439 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
441 /* CPU feature flags of instruction set architecture used. */
442 i386_cpu_flags cpu_arch_isa_flags
;
444 /* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446 static unsigned int no_cond_jump_promotion
= 0;
448 /* Encode SSE instructions with VEX prefix. */
449 static unsigned int sse2avx
;
451 /* Encode scalar AVX instructions with specific vector length. */
458 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
459 static symbolS
*GOT_symbol
;
461 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
462 unsigned int x86_dwarf2_return_column
;
464 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
465 int x86_cie_data_alignment
;
467 /* Interface to relax_segment.
468 There are 3 major relax states for 386 jump insns because the
469 different types of jumps add different sizes to frags when we're
470 figuring out what sort of jump to choose to reach a given label. */
473 #define UNCOND_JUMP 0
475 #define COND_JUMP86 2
480 #define SMALL16 (SMALL | CODE16)
482 #define BIG16 (BIG | CODE16)
486 #define INLINE __inline__
492 #define ENCODE_RELAX_STATE(type, size) \
493 ((relax_substateT) (((type) << 2) | (size)))
494 #define TYPE_FROM_RELAX_STATE(s) \
496 #define DISP_SIZE_FROM_RELAX_STATE(s) \
497 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
499 /* This table is used by relax_frag to promote short jumps to long
500 ones where necessary. SMALL (short) jumps may be promoted to BIG
501 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
502 don't allow a short jump in a 32 bit code segment to be promoted to
503 a 16 bit offset jump because it's slower (requires data size
504 prefix), and doesn't work, unless the destination is in the bottom
505 64k of the code segment (The top 16 bits of eip are zeroed). */
507 const relax_typeS md_relax_table
[] =
510 1) most positive reach of this state,
511 2) most negative reach of this state,
512 3) how many bytes this mode will have in the variable part of the frag
513 4) which index into the table to try if we can't fit into this one. */
515 /* UNCOND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
518 /* dword jmp adds 4 bytes to frag:
519 0 extra opcode bytes, 4 displacement bytes. */
521 /* word jmp adds 2 byte2 to frag:
522 0 extra opcode bytes, 2 displacement bytes. */
525 /* COND_JUMP states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 3 bytes to frag:
532 1 extra opcode byte, 2 displacement bytes. */
535 /* COND_JUMP86 states. */
536 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
537 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
538 /* dword conditionals adds 5 bytes to frag:
539 1 extra opcode byte, 4 displacement bytes. */
541 /* word conditionals add 4 bytes to frag:
542 1 displacement byte and a 3 byte long branch insn. */
546 static const arch_entry cpu_arch
[] =
548 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
549 CPU_GENERIC32_FLAGS
, 0 },
550 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
551 CPU_GENERIC64_FLAGS
, 0 },
552 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
554 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
556 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
558 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
560 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
562 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
564 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
566 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
568 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
570 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
572 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
574 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
576 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
578 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
579 CPU_NOCONA_FLAGS
, 0 },
580 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
582 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
584 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
585 CPU_CORE2_FLAGS
, 1 },
586 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
587 CPU_CORE2_FLAGS
, 0 },
588 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
589 CPU_COREI7_FLAGS
, 0 },
590 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
592 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
594 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
596 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
597 CPU_ATHLON_FLAGS
, 0 },
598 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
600 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
602 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
604 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
605 CPU_AMDFAM10_FLAGS
, 0 },
606 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
607 CPU_BDVER1_FLAGS
, 0 },
608 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
610 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
612 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
614 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
615 CPU_ANY87_FLAGS
, 0 },
616 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
618 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
619 CPU_3DNOWA_FLAGS
, 0 },
620 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
622 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
624 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
626 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
627 CPU_SSSE3_FLAGS
, 0 },
628 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
629 CPU_SSE4_1_FLAGS
, 0 },
630 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
631 CPU_SSE4_2_FLAGS
, 0 },
632 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
633 CPU_SSE4_2_FLAGS
, 0 },
634 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
635 CPU_ANY_SSE_FLAGS
, 0 },
636 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
638 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
639 CPU_ANY_AVX_FLAGS
, 0 },
640 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
642 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
644 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
645 CPU_XSAVE_FLAGS
, 0 },
646 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
648 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
649 CPU_PCLMUL_FLAGS
, 0 },
650 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
651 CPU_PCLMUL_FLAGS
, 1 },
652 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
654 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
656 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
658 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
660 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
661 CPU_MOVBE_FLAGS
, 0 },
662 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
664 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
665 CPU_CLFLUSH_FLAGS
, 0 },
666 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
667 CPU_SYSCALL_FLAGS
, 0 },
668 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
669 CPU_RDTSCP_FLAGS
, 0 },
670 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
671 CPU_3DNOW_FLAGS
, 0 },
672 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
673 CPU_3DNOWA_FLAGS
, 0 },
674 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
675 CPU_PADLOCK_FLAGS
, 0 },
676 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
678 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
680 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
681 CPU_SSE4A_FLAGS
, 0 },
682 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
687 /* Like s_lcomm_internal in gas/read.c but the alignment string
688 is allowed to be optional. */
691 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
698 && *input_line_pointer
== ',')
700 align
= parse_align (needs_align
- 1);
702 if (align
== (addressT
) -1)
717 bss_alloc (symbolP
, size
, align
);
722 pe_lcomm (int needs_align
)
724 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
728 const pseudo_typeS md_pseudo_table
[] =
730 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
731 {"align", s_align_bytes
, 0},
733 {"align", s_align_ptwo
, 0},
735 {"arch", set_cpu_arch
, 0},
739 {"lcomm", pe_lcomm
, 1},
741 {"ffloat", float_cons
, 'f'},
742 {"dfloat", float_cons
, 'd'},
743 {"tfloat", float_cons
, 'x'},
745 {"slong", signed_cons
, 4},
746 {"noopt", s_ignore
, 0},
747 {"optim", s_ignore
, 0},
748 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
749 {"code16", set_code_flag
, CODE_16BIT
},
750 {"code32", set_code_flag
, CODE_32BIT
},
751 {"code64", set_code_flag
, CODE_64BIT
},
752 {"intel_syntax", set_intel_syntax
, 1},
753 {"att_syntax", set_intel_syntax
, 0},
754 {"intel_mnemonic", set_intel_mnemonic
, 1},
755 {"att_mnemonic", set_intel_mnemonic
, 0},
756 {"allow_index_reg", set_allow_index_reg
, 1},
757 {"disallow_index_reg", set_allow_index_reg
, 0},
758 {"sse_check", set_sse_check
, 0},
759 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
760 {"largecomm", handle_large_common
, 0},
762 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
763 {"loc", dwarf2_directive_loc
, 0},
764 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
767 {"secrel32", pe_directive_secrel
, 0},
772 /* For interface with expression (). */
773 extern char *input_line_pointer
;
775 /* Hash table for instruction mnemonic lookup. */
776 static struct hash_control
*op_hash
;
778 /* Hash table for register lookup. */
779 static struct hash_control
*reg_hash
;
782 i386_align_code (fragS
*fragP
, int count
)
784 /* Various efficient no-op patterns for aligning code labels.
785 Note: Don't try to assemble the instructions in the comments.
786 0L and 0w are not legal. */
787 static const char f32_1
[] =
789 static const char f32_2
[] =
790 {0x66,0x90}; /* xchg %ax,%ax */
791 static const char f32_3
[] =
792 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
793 static const char f32_4
[] =
794 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
795 static const char f32_5
[] =
797 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
798 static const char f32_6
[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
800 static const char f32_7
[] =
801 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
802 static const char f32_8
[] =
804 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
805 static const char f32_9
[] =
806 {0x89,0xf6, /* movl %esi,%esi */
807 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
808 static const char f32_10
[] =
809 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_11
[] =
812 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
814 static const char f32_12
[] =
815 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
816 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
817 static const char f32_13
[] =
818 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
819 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
820 static const char f32_14
[] =
821 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
822 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
823 static const char f16_3
[] =
824 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
825 static const char f16_4
[] =
826 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
827 static const char f16_5
[] =
829 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
830 static const char f16_6
[] =
831 {0x89,0xf6, /* mov %si,%si */
832 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
833 static const char f16_7
[] =
834 {0x8d,0x74,0x00, /* lea 0(%si),%si */
835 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
836 static const char f16_8
[] =
837 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
838 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
839 static const char jump_31
[] =
840 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
841 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
842 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
843 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
844 static const char *const f32_patt
[] = {
845 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
846 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
848 static const char *const f16_patt
[] = {
849 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
852 static const char alt_3
[] =
854 /* nopl 0(%[re]ax) */
855 static const char alt_4
[] =
856 {0x0f,0x1f,0x40,0x00};
857 /* nopl 0(%[re]ax,%[re]ax,1) */
858 static const char alt_5
[] =
859 {0x0f,0x1f,0x44,0x00,0x00};
860 /* nopw 0(%[re]ax,%[re]ax,1) */
861 static const char alt_6
[] =
862 {0x66,0x0f,0x1f,0x44,0x00,0x00};
863 /* nopl 0L(%[re]ax) */
864 static const char alt_7
[] =
865 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
866 /* nopl 0L(%[re]ax,%[re]ax,1) */
867 static const char alt_8
[] =
868 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 /* nopw 0L(%[re]ax,%[re]ax,1) */
870 static const char alt_9
[] =
871 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
872 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
873 static const char alt_10
[] =
874 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
876 nopw %cs:0L(%[re]ax,%[re]ax,1) */
877 static const char alt_long_11
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
882 nopw %cs:0L(%[re]ax,%[re]ax,1) */
883 static const char alt_long_12
[] =
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
890 nopw %cs:0L(%[re]ax,%[re]ax,1) */
891 static const char alt_long_13
[] =
895 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 nopw %cs:0L(%[re]ax,%[re]ax,1) */
901 static const char alt_long_14
[] =
906 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
912 nopw %cs:0L(%[re]ax,%[re]ax,1) */
913 static const char alt_long_15
[] =
919 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
920 /* nopl 0(%[re]ax,%[re]ax,1)
921 nopw 0(%[re]ax,%[re]ax,1) */
922 static const char alt_short_11
[] =
923 {0x0f,0x1f,0x44,0x00,0x00,
924 0x66,0x0f,0x1f,0x44,0x00,0x00};
925 /* nopw 0(%[re]ax,%[re]ax,1)
926 nopw 0(%[re]ax,%[re]ax,1) */
927 static const char alt_short_12
[] =
928 {0x66,0x0f,0x1f,0x44,0x00,0x00,
929 0x66,0x0f,0x1f,0x44,0x00,0x00};
930 /* nopw 0(%[re]ax,%[re]ax,1)
932 static const char alt_short_13
[] =
933 {0x66,0x0f,0x1f,0x44,0x00,0x00,
934 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
937 static const char alt_short_14
[] =
938 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
939 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
941 nopl 0L(%[re]ax,%[re]ax,1) */
942 static const char alt_short_15
[] =
943 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
944 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
945 static const char *const alt_short_patt
[] = {
946 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
947 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
948 alt_short_14
, alt_short_15
950 static const char *const alt_long_patt
[] = {
951 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
952 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
953 alt_long_14
, alt_long_15
956 /* Only align for at least a positive non-zero boundary. */
957 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
960 /* We need to decide which NOP sequence to use for 32bit and
961 64bit. When -mtune= is used:
963 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
964 PROCESSOR_GENERIC32, f32_patt will be used.
965 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
966 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
967 PROCESSOR_GENERIC64, alt_long_patt will be used.
968 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
969 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
972 When -mtune= isn't used, alt_long_patt will be used if
973 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
976 When -march= or .arch is used, we can't use anything beyond
977 cpu_arch_isa_flags. */
979 if (flag_code
== CODE_16BIT
)
983 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
985 /* Adjust jump offset. */
986 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
989 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
990 f16_patt
[count
- 1], count
);
994 const char *const *patt
= NULL
;
996 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
998 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
999 switch (cpu_arch_tune
)
1001 case PROCESSOR_UNKNOWN
:
1002 /* We use cpu_arch_isa_flags to check if we SHOULD
1003 optimize for Cpu686. */
1004 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1005 patt
= alt_long_patt
;
1009 case PROCESSOR_PENTIUMPRO
:
1010 case PROCESSOR_PENTIUM4
:
1011 case PROCESSOR_NOCONA
:
1012 case PROCESSOR_CORE
:
1013 case PROCESSOR_CORE2
:
1014 case PROCESSOR_COREI7
:
1015 case PROCESSOR_L1OM
:
1016 case PROCESSOR_GENERIC64
:
1017 patt
= alt_long_patt
;
1020 case PROCESSOR_ATHLON
:
1022 case PROCESSOR_AMDFAM10
:
1023 case PROCESSOR_BDVER1
:
1024 patt
= alt_short_patt
;
1026 case PROCESSOR_I386
:
1027 case PROCESSOR_I486
:
1028 case PROCESSOR_PENTIUM
:
1029 case PROCESSOR_GENERIC32
:
1036 switch (fragP
->tc_frag_data
.tune
)
1038 case PROCESSOR_UNKNOWN
:
1039 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1040 PROCESSOR_UNKNOWN. */
1044 case PROCESSOR_I386
:
1045 case PROCESSOR_I486
:
1046 case PROCESSOR_PENTIUM
:
1048 case PROCESSOR_ATHLON
:
1050 case PROCESSOR_AMDFAM10
:
1051 case PROCESSOR_BDVER1
:
1052 case PROCESSOR_GENERIC32
:
1053 /* We use cpu_arch_isa_flags to check if we CAN optimize
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_short_patt
;
1060 case PROCESSOR_PENTIUMPRO
:
1061 case PROCESSOR_PENTIUM4
:
1062 case PROCESSOR_NOCONA
:
1063 case PROCESSOR_CORE
:
1064 case PROCESSOR_CORE2
:
1065 case PROCESSOR_COREI7
:
1066 case PROCESSOR_L1OM
:
1067 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1068 patt
= alt_long_patt
;
1072 case PROCESSOR_GENERIC64
:
1073 patt
= alt_long_patt
;
1078 if (patt
== f32_patt
)
1080 /* If the padding is less than 15 bytes, we use the normal
1081 ones. Otherwise, we use a jump instruction and adjust
1085 /* For 64bit, the limit is 3 bytes. */
1086 if (flag_code
== CODE_64BIT
1087 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1092 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1093 patt
[count
- 1], count
);
1096 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1098 /* Adjust jump offset. */
1099 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1104 /* Maximum length of an instruction is 15 byte. If the
1105 padding is greater than 15 bytes and we don't use jump,
1106 we have to break it into smaller pieces. */
1107 int padding
= count
;
1108 while (padding
> 15)
1111 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1116 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1117 patt
[padding
- 1], padding
);
1120 fragP
->fr_var
= count
;
1124 operand_type_all_zero (const union i386_operand_type
*x
)
1126 switch (ARRAY_SIZE(x
->array
))
1135 return !x
->array
[0];
1142 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1144 switch (ARRAY_SIZE(x
->array
))
1159 operand_type_equal (const union i386_operand_type
*x
,
1160 const union i386_operand_type
*y
)
1162 switch (ARRAY_SIZE(x
->array
))
1165 if (x
->array
[2] != y
->array
[2])
1168 if (x
->array
[1] != y
->array
[1])
1171 return x
->array
[0] == y
->array
[0];
1179 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1181 switch (ARRAY_SIZE(x
->array
))
1190 return !x
->array
[0];
1197 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1199 switch (ARRAY_SIZE(x
->array
))
1214 cpu_flags_equal (const union i386_cpu_flags
*x
,
1215 const union i386_cpu_flags
*y
)
1217 switch (ARRAY_SIZE(x
->array
))
1220 if (x
->array
[2] != y
->array
[2])
1223 if (x
->array
[1] != y
->array
[1])
1226 return x
->array
[0] == y
->array
[0];
1234 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1236 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1237 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1240 static INLINE i386_cpu_flags
1241 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1243 switch (ARRAY_SIZE (x
.array
))
1246 x
.array
[2] &= y
.array
[2];
1248 x
.array
[1] &= y
.array
[1];
1250 x
.array
[0] &= y
.array
[0];
1258 static INLINE i386_cpu_flags
1259 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1261 switch (ARRAY_SIZE (x
.array
))
1264 x
.array
[2] |= y
.array
[2];
1266 x
.array
[1] |= y
.array
[1];
1268 x
.array
[0] |= y
.array
[0];
1276 static INLINE i386_cpu_flags
1277 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1279 switch (ARRAY_SIZE (x
.array
))
1282 x
.array
[2] &= ~y
.array
[2];
1284 x
.array
[1] &= ~y
.array
[1];
1286 x
.array
[0] &= ~y
.array
[0];
1294 #define CPU_FLAGS_ARCH_MATCH 0x1
1295 #define CPU_FLAGS_64BIT_MATCH 0x2
1296 #define CPU_FLAGS_AES_MATCH 0x4
1297 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1298 #define CPU_FLAGS_AVX_MATCH 0x10
1300 #define CPU_FLAGS_32BIT_MATCH \
1301 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1302 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1303 #define CPU_FLAGS_PERFECT_MATCH \
1304 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1306 /* Return CPU flags match bits. */
1309 cpu_flags_match (const insn_template
*t
)
1311 i386_cpu_flags x
= t
->cpu_flags
;
1312 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1314 x
.bitfield
.cpu64
= 0;
1315 x
.bitfield
.cpuno64
= 0;
1317 if (cpu_flags_all_zero (&x
))
1319 /* This instruction is available on all archs. */
1320 match
|= CPU_FLAGS_32BIT_MATCH
;
1324 /* This instruction is available only on some archs. */
1325 i386_cpu_flags cpu
= cpu_arch_flags
;
1327 cpu
.bitfield
.cpu64
= 0;
1328 cpu
.bitfield
.cpuno64
= 0;
1329 cpu
= cpu_flags_and (x
, cpu
);
1330 if (!cpu_flags_all_zero (&cpu
))
1332 if (x
.bitfield
.cpuavx
)
1334 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1335 if (cpu
.bitfield
.cpuavx
)
1337 /* Check SSE2AVX. */
1338 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1340 match
|= (CPU_FLAGS_ARCH_MATCH
1341 | CPU_FLAGS_AVX_MATCH
);
1343 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1344 match
|= CPU_FLAGS_AES_MATCH
;
1346 if (!x
.bitfield
.cpupclmul
1347 || cpu
.bitfield
.cpupclmul
)
1348 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1352 match
|= CPU_FLAGS_ARCH_MATCH
;
1355 match
|= CPU_FLAGS_32BIT_MATCH
;
1361 static INLINE i386_operand_type
1362 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1364 switch (ARRAY_SIZE (x
.array
))
1367 x
.array
[2] &= y
.array
[2];
1369 x
.array
[1] &= y
.array
[1];
1371 x
.array
[0] &= y
.array
[0];
1379 static INLINE i386_operand_type
1380 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1382 switch (ARRAY_SIZE (x
.array
))
1385 x
.array
[2] |= y
.array
[2];
1387 x
.array
[1] |= y
.array
[1];
1389 x
.array
[0] |= y
.array
[0];
1397 static INLINE i386_operand_type
1398 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1400 switch (ARRAY_SIZE (x
.array
))
1403 x
.array
[2] ^= y
.array
[2];
1405 x
.array
[1] ^= y
.array
[1];
1407 x
.array
[0] ^= y
.array
[0];
1415 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1416 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1417 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1418 static const i386_operand_type inoutportreg
1419 = OPERAND_TYPE_INOUTPORTREG
;
1420 static const i386_operand_type reg16_inoutportreg
1421 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1422 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1423 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1424 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1425 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1426 static const i386_operand_type anydisp
1427 = OPERAND_TYPE_ANYDISP
;
1428 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1429 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1430 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1431 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1432 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1433 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1434 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1435 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1436 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1437 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1438 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1439 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1450 operand_type_check (i386_operand_type t
, enum operand_type c
)
1455 return (t
.bitfield
.reg8
1458 || t
.bitfield
.reg64
);
1461 return (t
.bitfield
.imm8
1465 || t
.bitfield
.imm32s
1466 || t
.bitfield
.imm64
);
1469 return (t
.bitfield
.disp8
1470 || t
.bitfield
.disp16
1471 || t
.bitfield
.disp32
1472 || t
.bitfield
.disp32s
1473 || t
.bitfield
.disp64
);
1476 return (t
.bitfield
.disp8
1477 || t
.bitfield
.disp16
1478 || t
.bitfield
.disp32
1479 || t
.bitfield
.disp32s
1480 || t
.bitfield
.disp64
1481 || t
.bitfield
.baseindex
);
1490 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1491 operand J for instruction template T. */
1494 match_reg_size (const insn_template
*t
, unsigned int j
)
1496 return !((i
.types
[j
].bitfield
.byte
1497 && !t
->operand_types
[j
].bitfield
.byte
)
1498 || (i
.types
[j
].bitfield
.word
1499 && !t
->operand_types
[j
].bitfield
.word
)
1500 || (i
.types
[j
].bitfield
.dword
1501 && !t
->operand_types
[j
].bitfield
.dword
)
1502 || (i
.types
[j
].bitfield
.qword
1503 && !t
->operand_types
[j
].bitfield
.qword
));
1506 /* Return 1 if there is no conflict in any size on operand J for
1507 instruction template T. */
1510 match_mem_size (const insn_template
*t
, unsigned int j
)
1512 return (match_reg_size (t
, j
)
1513 && !((i
.types
[j
].bitfield
.unspecified
1514 && !t
->operand_types
[j
].bitfield
.unspecified
)
1515 || (i
.types
[j
].bitfield
.fword
1516 && !t
->operand_types
[j
].bitfield
.fword
)
1517 || (i
.types
[j
].bitfield
.tbyte
1518 && !t
->operand_types
[j
].bitfield
.tbyte
)
1519 || (i
.types
[j
].bitfield
.xmmword
1520 && !t
->operand_types
[j
].bitfield
.xmmword
)
1521 || (i
.types
[j
].bitfield
.ymmword
1522 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1525 /* Return 1 if there is no size conflict on any operands for
1526 instruction template T. */
1529 operand_size_match (const insn_template
*t
)
1534 /* Don't check jump instructions. */
1535 if (t
->opcode_modifier
.jump
1536 || t
->opcode_modifier
.jumpbyte
1537 || t
->opcode_modifier
.jumpdword
1538 || t
->opcode_modifier
.jumpintersegment
)
1541 /* Check memory and accumulator operand size. */
1542 for (j
= 0; j
< i
.operands
; j
++)
1544 if (t
->operand_types
[j
].bitfield
.anysize
)
1547 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1553 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1561 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1564 /* Check reverse. */
1565 gas_assert (i
.operands
== 2);
1568 for (j
= 0; j
< 2; j
++)
1570 if (t
->operand_types
[j
].bitfield
.acc
1571 && !match_reg_size (t
, j
? 0 : 1))
1577 if (i
.types
[j
].bitfield
.mem
1578 && !match_mem_size (t
, j
? 0 : 1))
1589 operand_type_match (i386_operand_type overlap
,
1590 i386_operand_type given
)
1592 i386_operand_type temp
= overlap
;
1594 temp
.bitfield
.jumpabsolute
= 0;
1595 temp
.bitfield
.unspecified
= 0;
1596 temp
.bitfield
.byte
= 0;
1597 temp
.bitfield
.word
= 0;
1598 temp
.bitfield
.dword
= 0;
1599 temp
.bitfield
.fword
= 0;
1600 temp
.bitfield
.qword
= 0;
1601 temp
.bitfield
.tbyte
= 0;
1602 temp
.bitfield
.xmmword
= 0;
1603 temp
.bitfield
.ymmword
= 0;
1604 if (operand_type_all_zero (&temp
))
1607 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1608 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1611 /* If given types g0 and g1 are registers they must be of the same type
1612 unless the expected operand type register overlap is null.
1613 Note that Acc in a template matches every size of reg. */
1616 operand_type_register_match (i386_operand_type m0
,
1617 i386_operand_type g0
,
1618 i386_operand_type t0
,
1619 i386_operand_type m1
,
1620 i386_operand_type g1
,
1621 i386_operand_type t1
)
1623 if (!operand_type_check (g0
, reg
))
1626 if (!operand_type_check (g1
, reg
))
1629 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1630 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1631 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1632 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1635 if (m0
.bitfield
.acc
)
1637 t0
.bitfield
.reg8
= 1;
1638 t0
.bitfield
.reg16
= 1;
1639 t0
.bitfield
.reg32
= 1;
1640 t0
.bitfield
.reg64
= 1;
1643 if (m1
.bitfield
.acc
)
1645 t1
.bitfield
.reg8
= 1;
1646 t1
.bitfield
.reg16
= 1;
1647 t1
.bitfield
.reg32
= 1;
1648 t1
.bitfield
.reg64
= 1;
1651 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1652 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1653 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1654 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1657 static INLINE
unsigned int
1658 mode_from_disp_size (i386_operand_type t
)
1660 if (t
.bitfield
.disp8
)
1662 else if (t
.bitfield
.disp16
1663 || t
.bitfield
.disp32
1664 || t
.bitfield
.disp32s
)
1671 fits_in_signed_byte (offsetT num
)
1673 return (num
>= -128) && (num
<= 127);
1677 fits_in_unsigned_byte (offsetT num
)
1679 return (num
& 0xff) == num
;
1683 fits_in_unsigned_word (offsetT num
)
1685 return (num
& 0xffff) == num
;
1689 fits_in_signed_word (offsetT num
)
1691 return (-32768 <= num
) && (num
<= 32767);
1695 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1700 return (!(((offsetT
) -1 << 31) & num
)
1701 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1703 } /* fits_in_signed_long() */
1706 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1711 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1713 } /* fits_in_unsigned_long() */
1716 fits_in_imm4 (offsetT num
)
1718 return (num
& 0xf) == num
;
1721 static i386_operand_type
1722 smallest_imm_type (offsetT num
)
1724 i386_operand_type t
;
1726 operand_type_set (&t
, 0);
1727 t
.bitfield
.imm64
= 1;
1729 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1731 /* This code is disabled on the 486 because all the Imm1 forms
1732 in the opcode table are slower on the i486. They're the
1733 versions with the implicitly specified single-position
1734 displacement, which has another syntax if you really want to
1736 t
.bitfield
.imm1
= 1;
1737 t
.bitfield
.imm8
= 1;
1738 t
.bitfield
.imm8s
= 1;
1739 t
.bitfield
.imm16
= 1;
1740 t
.bitfield
.imm32
= 1;
1741 t
.bitfield
.imm32s
= 1;
1743 else if (fits_in_signed_byte (num
))
1745 t
.bitfield
.imm8
= 1;
1746 t
.bitfield
.imm8s
= 1;
1747 t
.bitfield
.imm16
= 1;
1748 t
.bitfield
.imm32
= 1;
1749 t
.bitfield
.imm32s
= 1;
1751 else if (fits_in_unsigned_byte (num
))
1753 t
.bitfield
.imm8
= 1;
1754 t
.bitfield
.imm16
= 1;
1755 t
.bitfield
.imm32
= 1;
1756 t
.bitfield
.imm32s
= 1;
1758 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1760 t
.bitfield
.imm16
= 1;
1761 t
.bitfield
.imm32
= 1;
1762 t
.bitfield
.imm32s
= 1;
1764 else if (fits_in_signed_long (num
))
1766 t
.bitfield
.imm32
= 1;
1767 t
.bitfield
.imm32s
= 1;
1769 else if (fits_in_unsigned_long (num
))
1770 t
.bitfield
.imm32
= 1;
1776 offset_in_range (offsetT val
, int size
)
1782 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1783 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1784 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1786 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1792 /* If BFD64, sign extend val for 32bit address mode. */
1793 if (flag_code
!= CODE_64BIT
1794 || i
.prefix
[ADDR_PREFIX
])
1795 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1796 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1799 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1801 char buf1
[40], buf2
[40];
1803 sprint_value (buf1
, val
);
1804 sprint_value (buf2
, val
& mask
);
1805 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1819 a. PREFIX_EXIST if attempting to add a prefix where one from the
1820 same class already exists.
1821 b. PREFIX_LOCK if lock prefix is added.
1822 c. PREFIX_REP if rep/repne prefix is added.
1823 d. PREFIX_OTHER if other prefix is added.
1826 static enum PREFIX_GROUP
1827 add_prefix (unsigned int prefix
)
1829 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1832 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1833 && flag_code
== CODE_64BIT
)
1835 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1836 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1837 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1848 case CS_PREFIX_OPCODE
:
1849 case DS_PREFIX_OPCODE
:
1850 case ES_PREFIX_OPCODE
:
1851 case FS_PREFIX_OPCODE
:
1852 case GS_PREFIX_OPCODE
:
1853 case SS_PREFIX_OPCODE
:
1857 case REPNE_PREFIX_OPCODE
:
1858 case REPE_PREFIX_OPCODE
:
1863 case LOCK_PREFIX_OPCODE
:
1872 case ADDR_PREFIX_OPCODE
:
1876 case DATA_PREFIX_OPCODE
:
1880 if (i
.prefix
[q
] != 0)
1888 i
.prefix
[q
] |= prefix
;
1891 as_bad (_("same type of prefix used twice"));
1897 set_code_flag (int value
)
1899 flag_code
= (enum flag_code
) value
;
1900 if (flag_code
== CODE_64BIT
)
1902 cpu_arch_flags
.bitfield
.cpu64
= 1;
1903 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1907 cpu_arch_flags
.bitfield
.cpu64
= 0;
1908 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1910 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1912 as_bad (_("64bit mode not supported on this CPU."));
1914 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1916 as_bad (_("32bit mode not supported on this CPU."));
1918 stackop_size
= '\0';
1922 set_16bit_gcc_code_flag (int new_code_flag
)
1924 flag_code
= (enum flag_code
) new_code_flag
;
1925 if (flag_code
!= CODE_16BIT
)
1927 cpu_arch_flags
.bitfield
.cpu64
= 0;
1928 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1929 stackop_size
= LONG_MNEM_SUFFIX
;
1933 set_intel_syntax (int syntax_flag
)
1935 /* Find out if register prefixing is specified. */
1936 int ask_naked_reg
= 0;
1939 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1941 char *string
= input_line_pointer
;
1942 int e
= get_symbol_end ();
1944 if (strcmp (string
, "prefix") == 0)
1946 else if (strcmp (string
, "noprefix") == 0)
1949 as_bad (_("bad argument to syntax directive."));
1950 *input_line_pointer
= e
;
1952 demand_empty_rest_of_line ();
1954 intel_syntax
= syntax_flag
;
1956 if (ask_naked_reg
== 0)
1957 allow_naked_reg
= (intel_syntax
1958 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1960 allow_naked_reg
= (ask_naked_reg
< 0);
1962 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1964 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1965 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1966 register_prefix
= allow_naked_reg
? "" : "%";
1970 set_intel_mnemonic (int mnemonic_flag
)
1972 intel_mnemonic
= mnemonic_flag
;
1976 set_allow_index_reg (int flag
)
1978 allow_index_reg
= flag
;
1982 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1986 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1988 char *string
= input_line_pointer
;
1989 int e
= get_symbol_end ();
1991 if (strcmp (string
, "none") == 0)
1992 sse_check
= sse_check_none
;
1993 else if (strcmp (string
, "warning") == 0)
1994 sse_check
= sse_check_warning
;
1995 else if (strcmp (string
, "error") == 0)
1996 sse_check
= sse_check_error
;
1998 as_bad (_("bad argument to sse_check directive."));
1999 *input_line_pointer
= e
;
2002 as_bad (_("missing argument for sse_check directive"));
2004 demand_empty_rest_of_line ();
2008 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2009 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2011 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2012 static const char *arch
;
2014 /* Intel LIOM is only supported on ELF. */
2020 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2021 use default_arch. */
2022 arch
= cpu_arch_name
;
2024 arch
= default_arch
;
2027 /* If we are targeting Intel L1OM, we must enable it. */
2028 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2029 || new_flag
.bitfield
.cpul1om
)
2032 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2037 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2041 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2043 char *string
= input_line_pointer
;
2044 int e
= get_symbol_end ();
2046 i386_cpu_flags flags
;
2048 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2050 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2052 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2056 cpu_arch_name
= cpu_arch
[j
].name
;
2057 cpu_sub_arch_name
= NULL
;
2058 cpu_arch_flags
= cpu_arch
[j
].flags
;
2059 if (flag_code
== CODE_64BIT
)
2061 cpu_arch_flags
.bitfield
.cpu64
= 1;
2062 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2066 cpu_arch_flags
.bitfield
.cpu64
= 0;
2067 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2069 cpu_arch_isa
= cpu_arch
[j
].type
;
2070 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2071 if (!cpu_arch_tune_set
)
2073 cpu_arch_tune
= cpu_arch_isa
;
2074 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2079 if (strncmp (string
+ 1, "no", 2))
2080 flags
= cpu_flags_or (cpu_arch_flags
,
2083 flags
= cpu_flags_and_not (cpu_arch_flags
,
2085 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2087 if (cpu_sub_arch_name
)
2089 char *name
= cpu_sub_arch_name
;
2090 cpu_sub_arch_name
= concat (name
,
2092 (const char *) NULL
);
2096 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2097 cpu_arch_flags
= flags
;
2099 *input_line_pointer
= e
;
2100 demand_empty_rest_of_line ();
2104 if (j
>= ARRAY_SIZE (cpu_arch
))
2105 as_bad (_("no such architecture: `%s'"), string
);
2107 *input_line_pointer
= e
;
2110 as_bad (_("missing cpu architecture"));
2112 no_cond_jump_promotion
= 0;
2113 if (*input_line_pointer
== ','
2114 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2116 char *string
= ++input_line_pointer
;
2117 int e
= get_symbol_end ();
2119 if (strcmp (string
, "nojumps") == 0)
2120 no_cond_jump_promotion
= 1;
2121 else if (strcmp (string
, "jumps") == 0)
2124 as_bad (_("no such architecture modifier: `%s'"), string
);
2126 *input_line_pointer
= e
;
2129 demand_empty_rest_of_line ();
2132 enum bfd_architecture
2135 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2137 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2138 || flag_code
!= CODE_64BIT
)
2139 as_fatal (_("Intel L1OM is 64bit ELF only"));
2140 return bfd_arch_l1om
;
2143 return bfd_arch_i386
;
2149 if (!strcmp (default_arch
, "x86_64"))
2151 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2153 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2154 as_fatal (_("Intel L1OM is 64bit ELF only"));
2155 return bfd_mach_l1om
;
2158 return bfd_mach_x86_64
;
2160 else if (!strcmp (default_arch
, "i386"))
2161 return bfd_mach_i386_i386
;
2163 as_fatal (_("Unknown architecture"));
2169 const char *hash_err
;
2171 /* Initialize op_hash hash table. */
2172 op_hash
= hash_new ();
2175 const insn_template
*optab
;
2176 templates
*core_optab
;
2178 /* Setup for loop. */
2180 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2181 core_optab
->start
= optab
;
2186 if (optab
->name
== NULL
2187 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2189 /* different name --> ship out current template list;
2190 add to hash table; & begin anew. */
2191 core_optab
->end
= optab
;
2192 hash_err
= hash_insert (op_hash
,
2194 (void *) core_optab
);
2197 as_fatal (_("Internal Error: Can't hash %s: %s"),
2201 if (optab
->name
== NULL
)
2203 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2204 core_optab
->start
= optab
;
2209 /* Initialize reg_hash hash table. */
2210 reg_hash
= hash_new ();
2212 const reg_entry
*regtab
;
2213 unsigned int regtab_size
= i386_regtab_size
;
2215 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2217 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2219 as_fatal (_("Internal Error: Can't hash %s: %s"),
2225 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2230 for (c
= 0; c
< 256; c
++)
2235 mnemonic_chars
[c
] = c
;
2236 register_chars
[c
] = c
;
2237 operand_chars
[c
] = c
;
2239 else if (ISLOWER (c
))
2241 mnemonic_chars
[c
] = c
;
2242 register_chars
[c
] = c
;
2243 operand_chars
[c
] = c
;
2245 else if (ISUPPER (c
))
2247 mnemonic_chars
[c
] = TOLOWER (c
);
2248 register_chars
[c
] = mnemonic_chars
[c
];
2249 operand_chars
[c
] = c
;
2252 if (ISALPHA (c
) || ISDIGIT (c
))
2253 identifier_chars
[c
] = c
;
2256 identifier_chars
[c
] = c
;
2257 operand_chars
[c
] = c
;
2262 identifier_chars
['@'] = '@';
2265 identifier_chars
['?'] = '?';
2266 operand_chars
['?'] = '?';
2268 digit_chars
['-'] = '-';
2269 mnemonic_chars
['_'] = '_';
2270 mnemonic_chars
['-'] = '-';
2271 mnemonic_chars
['.'] = '.';
2272 identifier_chars
['_'] = '_';
2273 identifier_chars
['.'] = '.';
2275 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2276 operand_chars
[(unsigned char) *p
] = *p
;
2279 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2282 record_alignment (text_section
, 2);
2283 record_alignment (data_section
, 2);
2284 record_alignment (bss_section
, 2);
2288 if (flag_code
== CODE_64BIT
)
2290 x86_dwarf2_return_column
= 16;
2291 x86_cie_data_alignment
= -8;
2295 x86_dwarf2_return_column
= 8;
2296 x86_cie_data_alignment
= -4;
2301 i386_print_statistics (FILE *file
)
2303 hash_print_statistics (file
, "i386 opcode", op_hash
);
2304 hash_print_statistics (file
, "i386 register", reg_hash
);
2309 /* Debugging routines for md_assemble. */
2310 static void pte (insn_template
*);
2311 static void pt (i386_operand_type
);
2312 static void pe (expressionS
*);
2313 static void ps (symbolS
*);
2316 pi (char *line
, i386_insn
*x
)
2320 fprintf (stdout
, "%s: template ", line
);
2322 fprintf (stdout
, " address: base %s index %s scale %x\n",
2323 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2324 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2325 x
->log2_scale_factor
);
2326 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2327 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2328 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2329 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2330 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2331 (x
->rex
& REX_W
) != 0,
2332 (x
->rex
& REX_R
) != 0,
2333 (x
->rex
& REX_X
) != 0,
2334 (x
->rex
& REX_B
) != 0);
2335 for (i
= 0; i
< x
->operands
; i
++)
2337 fprintf (stdout
, " #%d: ", i
+ 1);
2339 fprintf (stdout
, "\n");
2340 if (x
->types
[i
].bitfield
.reg8
2341 || x
->types
[i
].bitfield
.reg16
2342 || x
->types
[i
].bitfield
.reg32
2343 || x
->types
[i
].bitfield
.reg64
2344 || x
->types
[i
].bitfield
.regmmx
2345 || x
->types
[i
].bitfield
.regxmm
2346 || x
->types
[i
].bitfield
.regymm
2347 || x
->types
[i
].bitfield
.sreg2
2348 || x
->types
[i
].bitfield
.sreg3
2349 || x
->types
[i
].bitfield
.control
2350 || x
->types
[i
].bitfield
.debug
2351 || x
->types
[i
].bitfield
.test
)
2352 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2353 if (operand_type_check (x
->types
[i
], imm
))
2355 if (operand_type_check (x
->types
[i
], disp
))
2356 pe (x
->op
[i
].disps
);
2361 pte (insn_template
*t
)
2364 fprintf (stdout
, " %d operands ", t
->operands
);
2365 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2366 if (t
->extension_opcode
!= None
)
2367 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2368 if (t
->opcode_modifier
.d
)
2369 fprintf (stdout
, "D");
2370 if (t
->opcode_modifier
.w
)
2371 fprintf (stdout
, "W");
2372 fprintf (stdout
, "\n");
2373 for (i
= 0; i
< t
->operands
; i
++)
2375 fprintf (stdout
, " #%d type ", i
+ 1);
2376 pt (t
->operand_types
[i
]);
2377 fprintf (stdout
, "\n");
2384 fprintf (stdout
, " operation %d\n", e
->X_op
);
2385 fprintf (stdout
, " add_number %ld (%lx)\n",
2386 (long) e
->X_add_number
, (long) e
->X_add_number
);
2387 if (e
->X_add_symbol
)
2389 fprintf (stdout
, " add_symbol ");
2390 ps (e
->X_add_symbol
);
2391 fprintf (stdout
, "\n");
2395 fprintf (stdout
, " op_symbol ");
2396 ps (e
->X_op_symbol
);
2397 fprintf (stdout
, "\n");
2404 fprintf (stdout
, "%s type %s%s",
2406 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2407 segment_name (S_GET_SEGMENT (s
)));
2410 static struct type_name
2412 i386_operand_type mask
;
2415 const type_names
[] =
2417 { OPERAND_TYPE_REG8
, "r8" },
2418 { OPERAND_TYPE_REG16
, "r16" },
2419 { OPERAND_TYPE_REG32
, "r32" },
2420 { OPERAND_TYPE_REG64
, "r64" },
2421 { OPERAND_TYPE_IMM8
, "i8" },
2422 { OPERAND_TYPE_IMM8
, "i8s" },
2423 { OPERAND_TYPE_IMM16
, "i16" },
2424 { OPERAND_TYPE_IMM32
, "i32" },
2425 { OPERAND_TYPE_IMM32S
, "i32s" },
2426 { OPERAND_TYPE_IMM64
, "i64" },
2427 { OPERAND_TYPE_IMM1
, "i1" },
2428 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2429 { OPERAND_TYPE_DISP8
, "d8" },
2430 { OPERAND_TYPE_DISP16
, "d16" },
2431 { OPERAND_TYPE_DISP32
, "d32" },
2432 { OPERAND_TYPE_DISP32S
, "d32s" },
2433 { OPERAND_TYPE_DISP64
, "d64" },
2434 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2435 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2436 { OPERAND_TYPE_CONTROL
, "control reg" },
2437 { OPERAND_TYPE_TEST
, "test reg" },
2438 { OPERAND_TYPE_DEBUG
, "debug reg" },
2439 { OPERAND_TYPE_FLOATREG
, "FReg" },
2440 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2441 { OPERAND_TYPE_SREG2
, "SReg2" },
2442 { OPERAND_TYPE_SREG3
, "SReg3" },
2443 { OPERAND_TYPE_ACC
, "Acc" },
2444 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2445 { OPERAND_TYPE_REGMMX
, "rMMX" },
2446 { OPERAND_TYPE_REGXMM
, "rXMM" },
2447 { OPERAND_TYPE_REGYMM
, "rYMM" },
2448 { OPERAND_TYPE_ESSEG
, "es" },
2452 pt (i386_operand_type t
)
2455 i386_operand_type a
;
2457 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2459 a
= operand_type_and (t
, type_names
[j
].mask
);
2460 if (!operand_type_all_zero (&a
))
2461 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2466 #endif /* DEBUG386 */
2468 static bfd_reloc_code_real_type
2469 reloc (unsigned int size
,
2472 bfd_reloc_code_real_type other
)
2474 if (other
!= NO_RELOC
)
2476 reloc_howto_type
*rel
;
2481 case BFD_RELOC_X86_64_GOT32
:
2482 return BFD_RELOC_X86_64_GOT64
;
2484 case BFD_RELOC_X86_64_PLTOFF64
:
2485 return BFD_RELOC_X86_64_PLTOFF64
;
2487 case BFD_RELOC_X86_64_GOTPC32
:
2488 other
= BFD_RELOC_X86_64_GOTPC64
;
2490 case BFD_RELOC_X86_64_GOTPCREL
:
2491 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2493 case BFD_RELOC_X86_64_TPOFF32
:
2494 other
= BFD_RELOC_X86_64_TPOFF64
;
2496 case BFD_RELOC_X86_64_DTPOFF32
:
2497 other
= BFD_RELOC_X86_64_DTPOFF64
;
2503 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2504 if (size
== 4 && flag_code
!= CODE_64BIT
)
2507 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2509 as_bad (_("unknown relocation (%u)"), other
);
2510 else if (size
!= bfd_get_reloc_size (rel
))
2511 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2512 bfd_get_reloc_size (rel
),
2514 else if (pcrel
&& !rel
->pc_relative
)
2515 as_bad (_("non-pc-relative relocation for pc-relative field"));
2516 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2518 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2520 as_bad (_("relocated field and relocation type differ in signedness"));
2529 as_bad (_("there are no unsigned pc-relative relocations"));
2532 case 1: return BFD_RELOC_8_PCREL
;
2533 case 2: return BFD_RELOC_16_PCREL
;
2534 case 4: return BFD_RELOC_32_PCREL
;
2535 case 8: return BFD_RELOC_64_PCREL
;
2537 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2544 case 4: return BFD_RELOC_X86_64_32S
;
2549 case 1: return BFD_RELOC_8
;
2550 case 2: return BFD_RELOC_16
;
2551 case 4: return BFD_RELOC_32
;
2552 case 8: return BFD_RELOC_64
;
2554 as_bad (_("cannot do %s %u byte relocation"),
2555 sign
> 0 ? "signed" : "unsigned", size
);
2561 /* Here we decide which fixups can be adjusted to make them relative to
2562 the beginning of the section instead of the symbol. Basically we need
2563 to make sure that the dynamic relocations are done correctly, so in
2564 some cases we force the original symbol to be used. */
2567 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2569 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2573 /* Don't adjust pc-relative references to merge sections in 64-bit
2575 if (use_rela_relocations
2576 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2580 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2581 and changed later by validate_fix. */
2582 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2583 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2586 /* adjust_reloc_syms doesn't know about the GOT. */
2587 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2588 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2589 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2590 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2591 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2592 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2593 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2594 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2595 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2596 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2597 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2598 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2599 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2600 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2601 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2602 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2603 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2604 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2605 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2606 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2607 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2608 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2609 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2610 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2611 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2612 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2613 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2614 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2621 intel_float_operand (const char *mnemonic
)
2623 /* Note that the value returned is meaningful only for opcodes with (memory)
2624 operands, hence the code here is free to improperly handle opcodes that
2625 have no operands (for better performance and smaller code). */
2627 if (mnemonic
[0] != 'f')
2628 return 0; /* non-math */
2630 switch (mnemonic
[1])
2632 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2633 the fs segment override prefix not currently handled because no
2634 call path can make opcodes without operands get here */
2636 return 2 /* integer op */;
2638 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2639 return 3; /* fldcw/fldenv */
2642 if (mnemonic
[2] != 'o' /* fnop */)
2643 return 3; /* non-waiting control op */
2646 if (mnemonic
[2] == 's')
2647 return 3; /* frstor/frstpm */
2650 if (mnemonic
[2] == 'a')
2651 return 3; /* fsave */
2652 if (mnemonic
[2] == 't')
2654 switch (mnemonic
[3])
2656 case 'c': /* fstcw */
2657 case 'd': /* fstdw */
2658 case 'e': /* fstenv */
2659 case 's': /* fsts[gw] */
2665 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2666 return 0; /* fxsave/fxrstor are not really math ops */
2673 /* Build the VEX prefix. */
2676 build_vex_prefix (const insn_template
*t
)
2678 unsigned int register_specifier
;
2679 unsigned int implied_prefix
;
2680 unsigned int vector_length
;
2682 /* Check register specifier. */
2683 if (i
.vex
.register_specifier
)
2685 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2686 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2687 register_specifier
+= 8;
2688 register_specifier
= ~register_specifier
& 0xf;
2691 register_specifier
= 0xf;
2693 /* Use 2-byte VEX prefix by swappping destination and source
2696 && i
.operands
== i
.reg_operands
2697 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2698 && i
.tm
.opcode_modifier
.s
2701 unsigned int xchg
= i
.operands
- 1;
2702 union i386_op temp_op
;
2703 i386_operand_type temp_type
;
2705 temp_type
= i
.types
[xchg
];
2706 i
.types
[xchg
] = i
.types
[0];
2707 i
.types
[0] = temp_type
;
2708 temp_op
= i
.op
[xchg
];
2709 i
.op
[xchg
] = i
.op
[0];
2712 gas_assert (i
.rm
.mode
== 3);
2716 i
.rm
.regmem
= i
.rm
.reg
;
2719 /* Use the next insn. */
2723 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2724 vector_length
= avxscalar
;
2726 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2728 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2733 case DATA_PREFIX_OPCODE
:
2736 case REPE_PREFIX_OPCODE
:
2739 case REPNE_PREFIX_OPCODE
:
2746 /* Use 2-byte VEX prefix if possible. */
2747 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2748 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2750 /* 2-byte VEX prefix. */
2754 i
.vex
.bytes
[0] = 0xc5;
2756 /* Check the REX.R bit. */
2757 r
= (i
.rex
& REX_R
) ? 0 : 1;
2758 i
.vex
.bytes
[1] = (r
<< 7
2759 | register_specifier
<< 3
2760 | vector_length
<< 2
2765 /* 3-byte VEX prefix. */
2770 switch (i
.tm
.opcode_modifier
.vexopcode
)
2774 i
.vex
.bytes
[0] = 0xc4;
2778 i
.vex
.bytes
[0] = 0xc4;
2782 i
.vex
.bytes
[0] = 0xc4;
2786 i
.vex
.bytes
[0] = 0x8f;
2790 i
.vex
.bytes
[0] = 0x8f;
2794 i
.vex
.bytes
[0] = 0x8f;
2800 /* The high 3 bits of the second VEX byte are 1's compliment
2801 of RXB bits from REX. */
2802 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2804 /* Check the REX.W bit. */
2805 w
= (i
.rex
& REX_W
) ? 1 : 0;
2806 if (i
.tm
.opcode_modifier
.vexw
)
2811 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2815 i
.vex
.bytes
[2] = (w
<< 7
2816 | register_specifier
<< 3
2817 | vector_length
<< 2
2823 process_immext (void)
2827 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2829 /* SSE3 Instructions have the fixed operands with an opcode
2830 suffix which is coded in the same place as an 8-bit immediate
2831 field would be. Here we check those operands and remove them
2835 for (x
= 0; x
< i
.operands
; x
++)
2836 if (i
.op
[x
].regs
->reg_num
!= x
)
2837 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2838 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2844 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2845 which is coded in the same place as an 8-bit immediate field
2846 would be. Here we fake an 8-bit immediate operand from the
2847 opcode suffix stored in tm.extension_opcode.
2849 AVX instructions also use this encoding, for some of
2850 3 argument instructions. */
2852 gas_assert (i
.imm_operands
== 0
2854 || (i
.tm
.opcode_modifier
.vex
2855 && i
.operands
<= 4)));
2857 exp
= &im_expressions
[i
.imm_operands
++];
2858 i
.op
[i
.operands
].imms
= exp
;
2859 i
.types
[i
.operands
] = imm8
;
2861 exp
->X_op
= O_constant
;
2862 exp
->X_add_number
= i
.tm
.extension_opcode
;
2863 i
.tm
.extension_opcode
= None
;
2866 /* This is the guts of the machine-dependent assembler. LINE points to a
2867 machine dependent instruction. This function is supposed to emit
2868 the frags/bytes it assembles to. */
2871 md_assemble (char *line
)
2874 char mnemonic
[MAX_MNEM_SIZE
];
2875 const insn_template
*t
;
2877 /* Initialize globals. */
2878 memset (&i
, '\0', sizeof (i
));
2879 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2880 i
.reloc
[j
] = NO_RELOC
;
2881 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2882 memset (im_expressions
, '\0', sizeof (im_expressions
));
2883 save_stack_p
= save_stack
;
2885 /* First parse an instruction mnemonic & call i386_operand for the operands.
2886 We assume that the scrubber has arranged it so that line[0] is the valid
2887 start of a (possibly prefixed) mnemonic. */
2889 line
= parse_insn (line
, mnemonic
);
2893 line
= parse_operands (line
, mnemonic
);
2898 /* Now we've parsed the mnemonic into a set of templates, and have the
2899 operands at hand. */
2901 /* All intel opcodes have reversed operands except for "bound" and
2902 "enter". We also don't reverse intersegment "jmp" and "call"
2903 instructions with 2 immediate operands so that the immediate segment
2904 precedes the offset, as it does when in AT&T mode. */
2907 && (strcmp (mnemonic
, "bound") != 0)
2908 && (strcmp (mnemonic
, "invlpga") != 0)
2909 && !(operand_type_check (i
.types
[0], imm
)
2910 && operand_type_check (i
.types
[1], imm
)))
2913 /* The order of the immediates should be reversed
2914 for 2 immediates extrq and insertq instructions */
2915 if (i
.imm_operands
== 2
2916 && (strcmp (mnemonic
, "extrq") == 0
2917 || strcmp (mnemonic
, "insertq") == 0))
2918 swap_2_operands (0, 1);
2923 /* Don't optimize displacement for movabs since it only takes 64bit
2926 && (flag_code
!= CODE_64BIT
2927 || strcmp (mnemonic
, "movabs") != 0))
2930 /* Next, we find a template that matches the given insn,
2931 making sure the overlap of the given operands types is consistent
2932 with the template operand types. */
2934 if (!(t
= match_template ()))
2937 if (sse_check
!= sse_check_none
2938 && !i
.tm
.opcode_modifier
.noavx
2939 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2940 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2941 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2942 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2943 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2944 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2946 (sse_check
== sse_check_warning
2948 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2951 /* Zap movzx and movsx suffix. The suffix has been set from
2952 "word ptr" or "byte ptr" on the source operand in Intel syntax
2953 or extracted from mnemonic in AT&T syntax. But we'll use
2954 the destination register to choose the suffix for encoding. */
2955 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2957 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2958 there is no suffix, the default will be byte extension. */
2959 if (i
.reg_operands
!= 2
2962 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2967 if (i
.tm
.opcode_modifier
.fwait
)
2968 if (!add_prefix (FWAIT_OPCODE
))
2971 /* Check for lock without a lockable instruction. Destination operand
2972 must be memory unless it is xchg (0x86). */
2973 if (i
.prefix
[LOCK_PREFIX
]
2974 && (!i
.tm
.opcode_modifier
.islockable
2975 || i
.mem_operands
== 0
2976 || (i
.tm
.base_opcode
!= 0x86
2977 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2979 as_bad (_("expecting lockable instruction after `lock'"));
2983 /* Check string instruction segment overrides. */
2984 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2986 if (!check_string ())
2988 i
.disp_operands
= 0;
2991 if (!process_suffix ())
2994 /* Update operand types. */
2995 for (j
= 0; j
< i
.operands
; j
++)
2996 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2998 /* Make still unresolved immediate matches conform to size of immediate
2999 given in i.suffix. */
3000 if (!finalize_imm ())
3003 if (i
.types
[0].bitfield
.imm1
)
3004 i
.imm_operands
= 0; /* kludge for shift insns. */
3006 /* We only need to check those implicit registers for instructions
3007 with 3 operands or less. */
3008 if (i
.operands
<= 3)
3009 for (j
= 0; j
< i
.operands
; j
++)
3010 if (i
.types
[j
].bitfield
.inoutportreg
3011 || i
.types
[j
].bitfield
.shiftcount
3012 || i
.types
[j
].bitfield
.acc
3013 || i
.types
[j
].bitfield
.floatacc
)
3016 /* ImmExt should be processed after SSE2AVX. */
3017 if (!i
.tm
.opcode_modifier
.sse2avx
3018 && i
.tm
.opcode_modifier
.immext
)
3021 /* For insns with operands there are more diddles to do to the opcode. */
3024 if (!process_operands ())
3027 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3029 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3030 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3033 if (i
.tm
.opcode_modifier
.vex
)
3034 build_vex_prefix (t
);
3036 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3037 instructions may define INT_OPCODE as well, so avoid this corner
3038 case for those instructions that use MODRM. */
3039 if (i
.tm
.base_opcode
== INT_OPCODE
3040 && !i
.tm
.opcode_modifier
.modrm
3041 && i
.op
[0].imms
->X_add_number
== 3)
3043 i
.tm
.base_opcode
= INT3_OPCODE
;
3047 if ((i
.tm
.opcode_modifier
.jump
3048 || i
.tm
.opcode_modifier
.jumpbyte
3049 || i
.tm
.opcode_modifier
.jumpdword
)
3050 && i
.op
[0].disps
->X_op
== O_constant
)
3052 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3053 the absolute address given by the constant. Since ix86 jumps and
3054 calls are pc relative, we need to generate a reloc. */
3055 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3056 i
.op
[0].disps
->X_op
= O_symbol
;
3059 if (i
.tm
.opcode_modifier
.rex64
)
3062 /* For 8 bit registers we need an empty rex prefix. Also if the
3063 instruction already has a prefix, we need to convert old
3064 registers to new ones. */
3066 if ((i
.types
[0].bitfield
.reg8
3067 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3068 || (i
.types
[1].bitfield
.reg8
3069 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3070 || ((i
.types
[0].bitfield
.reg8
3071 || i
.types
[1].bitfield
.reg8
)
3076 i
.rex
|= REX_OPCODE
;
3077 for (x
= 0; x
< 2; x
++)
3079 /* Look for 8 bit operand that uses old registers. */
3080 if (i
.types
[x
].bitfield
.reg8
3081 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3083 /* In case it is "hi" register, give up. */
3084 if (i
.op
[x
].regs
->reg_num
> 3)
3085 as_bad (_("can't encode register '%s%s' in an "
3086 "instruction requiring REX prefix."),
3087 register_prefix
, i
.op
[x
].regs
->reg_name
);
3089 /* Otherwise it is equivalent to the extended register.
3090 Since the encoding doesn't change this is merely
3091 cosmetic cleanup for debug output. */
3093 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3099 add_prefix (REX_OPCODE
| i
.rex
);
3101 /* We are ready to output the insn. */
3106 parse_insn (char *line
, char *mnemonic
)
3109 char *token_start
= l
;
3112 const insn_template
*t
;
3115 /* Non-zero if we found a prefix only acceptable with string insns. */
3116 const char *expecting_string_instruction
= NULL
;
3121 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3126 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3128 as_bad (_("no such instruction: `%s'"), token_start
);
3133 if (!is_space_char (*l
)
3134 && *l
!= END_OF_INSN
3136 || (*l
!= PREFIX_SEPARATOR
3139 as_bad (_("invalid character %s in mnemonic"),
3140 output_invalid (*l
));
3143 if (token_start
== l
)
3145 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3146 as_bad (_("expecting prefix; got nothing"));
3148 as_bad (_("expecting mnemonic; got nothing"));
3152 /* Look up instruction (or prefix) via hash table. */
3153 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3155 if (*l
!= END_OF_INSN
3156 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3157 && current_templates
3158 && current_templates
->start
->opcode_modifier
.isprefix
)
3160 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3162 as_bad ((flag_code
!= CODE_64BIT
3163 ? _("`%s' is only supported in 64-bit mode")
3164 : _("`%s' is not supported in 64-bit mode")),
3165 current_templates
->start
->name
);
3168 /* If we are in 16-bit mode, do not allow addr16 or data16.
3169 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3170 if ((current_templates
->start
->opcode_modifier
.size16
3171 || current_templates
->start
->opcode_modifier
.size32
)
3172 && flag_code
!= CODE_64BIT
3173 && (current_templates
->start
->opcode_modifier
.size32
3174 ^ (flag_code
== CODE_16BIT
)))
3176 as_bad (_("redundant %s prefix"),
3177 current_templates
->start
->name
);
3180 /* Add prefix, checking for repeated prefixes. */
3181 switch (add_prefix (current_templates
->start
->base_opcode
))
3186 expecting_string_instruction
= current_templates
->start
->name
;
3191 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3198 if (!current_templates
)
3200 /* Check if we should swap operand in encoding. */
3201 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3207 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3210 if (!current_templates
)
3213 /* See if we can get a match by trimming off a suffix. */
3216 case WORD_MNEM_SUFFIX
:
3217 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3218 i
.suffix
= SHORT_MNEM_SUFFIX
;
3220 case BYTE_MNEM_SUFFIX
:
3221 case QWORD_MNEM_SUFFIX
:
3222 i
.suffix
= mnem_p
[-1];
3224 current_templates
= (const templates
*) hash_find (op_hash
,
3227 case SHORT_MNEM_SUFFIX
:
3228 case LONG_MNEM_SUFFIX
:
3231 i
.suffix
= mnem_p
[-1];
3233 current_templates
= (const templates
*) hash_find (op_hash
,
3242 if (intel_float_operand (mnemonic
) == 1)
3243 i
.suffix
= SHORT_MNEM_SUFFIX
;
3245 i
.suffix
= LONG_MNEM_SUFFIX
;
3247 current_templates
= (const templates
*) hash_find (op_hash
,
3252 if (!current_templates
)
3254 as_bad (_("no such instruction: `%s'"), token_start
);
3259 if (current_templates
->start
->opcode_modifier
.jump
3260 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3262 /* Check for a branch hint. We allow ",pt" and ",pn" for
3263 predict taken and predict not taken respectively.
3264 I'm not sure that branch hints actually do anything on loop
3265 and jcxz insns (JumpByte) for current Pentium4 chips. They
3266 may work in the future and it doesn't hurt to accept them
3268 if (l
[0] == ',' && l
[1] == 'p')
3272 if (!add_prefix (DS_PREFIX_OPCODE
))
3276 else if (l
[2] == 'n')
3278 if (!add_prefix (CS_PREFIX_OPCODE
))
3284 /* Any other comma loses. */
3287 as_bad (_("invalid character %s in mnemonic"),
3288 output_invalid (*l
));
3292 /* Check if instruction is supported on specified architecture. */
3294 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3296 supported
|= cpu_flags_match (t
);
3297 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3301 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3303 as_bad (flag_code
== CODE_64BIT
3304 ? _("`%s' is not supported in 64-bit mode")
3305 : _("`%s' is only supported in 64-bit mode"),
3306 current_templates
->start
->name
);
3309 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3311 as_bad (_("`%s' is not supported on `%s%s'"),
3312 current_templates
->start
->name
,
3313 cpu_arch_name
? cpu_arch_name
: default_arch
,
3314 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3319 if (!cpu_arch_flags
.bitfield
.cpui386
3320 && (flag_code
!= CODE_16BIT
))
3322 as_warn (_("use .code16 to ensure correct addressing mode"));
3325 /* Check for rep/repne without a string instruction. */
3326 if (expecting_string_instruction
)
3328 static templates override
;
3330 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3331 if (t
->opcode_modifier
.isstring
)
3333 if (t
>= current_templates
->end
)
3335 as_bad (_("expecting string instruction after `%s'"),
3336 expecting_string_instruction
);
3339 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3340 if (!t
->opcode_modifier
.isstring
)
3343 current_templates
= &override
;
3350 parse_operands (char *l
, const char *mnemonic
)
3354 /* 1 if operand is pending after ','. */
3355 unsigned int expecting_operand
= 0;
3357 /* Non-zero if operand parens not balanced. */
3358 unsigned int paren_not_balanced
;
3360 while (*l
!= END_OF_INSN
)
3362 /* Skip optional white space before operand. */
3363 if (is_space_char (*l
))
3365 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3367 as_bad (_("invalid character %s before operand %d"),
3368 output_invalid (*l
),
3372 token_start
= l
; /* after white space */
3373 paren_not_balanced
= 0;
3374 while (paren_not_balanced
|| *l
!= ',')
3376 if (*l
== END_OF_INSN
)
3378 if (paren_not_balanced
)
3381 as_bad (_("unbalanced parenthesis in operand %d."),
3384 as_bad (_("unbalanced brackets in operand %d."),
3389 break; /* we are done */
3391 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3393 as_bad (_("invalid character %s in operand %d"),
3394 output_invalid (*l
),
3401 ++paren_not_balanced
;
3403 --paren_not_balanced
;
3408 ++paren_not_balanced
;
3410 --paren_not_balanced
;
3414 if (l
!= token_start
)
3415 { /* Yes, we've read in another operand. */
3416 unsigned int operand_ok
;
3417 this_operand
= i
.operands
++;
3418 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3419 if (i
.operands
> MAX_OPERANDS
)
3421 as_bad (_("spurious operands; (%d operands/instruction max)"),
3425 /* Now parse operand adding info to 'i' as we go along. */
3426 END_STRING_AND_SAVE (l
);
3430 i386_intel_operand (token_start
,
3431 intel_float_operand (mnemonic
));
3433 operand_ok
= i386_att_operand (token_start
);
3435 RESTORE_END_STRING (l
);
3441 if (expecting_operand
)
3443 expecting_operand_after_comma
:
3444 as_bad (_("expecting operand after ','; got nothing"));
3449 as_bad (_("expecting operand before ','; got nothing"));
3454 /* Now *l must be either ',' or END_OF_INSN. */
3457 if (*++l
== END_OF_INSN
)
3459 /* Just skip it, if it's \n complain. */
3460 goto expecting_operand_after_comma
;
3462 expecting_operand
= 1;
3469 swap_2_operands (int xchg1
, int xchg2
)
3471 union i386_op temp_op
;
3472 i386_operand_type temp_type
;
3473 enum bfd_reloc_code_real temp_reloc
;
3475 temp_type
= i
.types
[xchg2
];
3476 i
.types
[xchg2
] = i
.types
[xchg1
];
3477 i
.types
[xchg1
] = temp_type
;
3478 temp_op
= i
.op
[xchg2
];
3479 i
.op
[xchg2
] = i
.op
[xchg1
];
3480 i
.op
[xchg1
] = temp_op
;
3481 temp_reloc
= i
.reloc
[xchg2
];
3482 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3483 i
.reloc
[xchg1
] = temp_reloc
;
3487 swap_operands (void)
3493 swap_2_operands (1, i
.operands
- 2);
3496 swap_2_operands (0, i
.operands
- 1);
3502 if (i
.mem_operands
== 2)
3504 const seg_entry
*temp_seg
;
3505 temp_seg
= i
.seg
[0];
3506 i
.seg
[0] = i
.seg
[1];
3507 i
.seg
[1] = temp_seg
;
3511 /* Try to ensure constant immediates are represented in the smallest
3516 char guess_suffix
= 0;
3520 guess_suffix
= i
.suffix
;
3521 else if (i
.reg_operands
)
3523 /* Figure out a suffix from the last register operand specified.
3524 We can't do this properly yet, ie. excluding InOutPortReg,
3525 but the following works for instructions with immediates.
3526 In any case, we can't set i.suffix yet. */
3527 for (op
= i
.operands
; --op
>= 0;)
3528 if (i
.types
[op
].bitfield
.reg8
)
3530 guess_suffix
= BYTE_MNEM_SUFFIX
;
3533 else if (i
.types
[op
].bitfield
.reg16
)
3535 guess_suffix
= WORD_MNEM_SUFFIX
;
3538 else if (i
.types
[op
].bitfield
.reg32
)
3540 guess_suffix
= LONG_MNEM_SUFFIX
;
3543 else if (i
.types
[op
].bitfield
.reg64
)
3545 guess_suffix
= QWORD_MNEM_SUFFIX
;
3549 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3550 guess_suffix
= WORD_MNEM_SUFFIX
;
3552 for (op
= i
.operands
; --op
>= 0;)
3553 if (operand_type_check (i
.types
[op
], imm
))
3555 switch (i
.op
[op
].imms
->X_op
)
3558 /* If a suffix is given, this operand may be shortened. */
3559 switch (guess_suffix
)
3561 case LONG_MNEM_SUFFIX
:
3562 i
.types
[op
].bitfield
.imm32
= 1;
3563 i
.types
[op
].bitfield
.imm64
= 1;
3565 case WORD_MNEM_SUFFIX
:
3566 i
.types
[op
].bitfield
.imm16
= 1;
3567 i
.types
[op
].bitfield
.imm32
= 1;
3568 i
.types
[op
].bitfield
.imm32s
= 1;
3569 i
.types
[op
].bitfield
.imm64
= 1;
3571 case BYTE_MNEM_SUFFIX
:
3572 i
.types
[op
].bitfield
.imm8
= 1;
3573 i
.types
[op
].bitfield
.imm8s
= 1;
3574 i
.types
[op
].bitfield
.imm16
= 1;
3575 i
.types
[op
].bitfield
.imm32
= 1;
3576 i
.types
[op
].bitfield
.imm32s
= 1;
3577 i
.types
[op
].bitfield
.imm64
= 1;
3581 /* If this operand is at most 16 bits, convert it
3582 to a signed 16 bit number before trying to see
3583 whether it will fit in an even smaller size.
3584 This allows a 16-bit operand such as $0xffe0 to
3585 be recognised as within Imm8S range. */
3586 if ((i
.types
[op
].bitfield
.imm16
)
3587 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3589 i
.op
[op
].imms
->X_add_number
=
3590 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3592 if ((i
.types
[op
].bitfield
.imm32
)
3593 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3596 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3597 ^ ((offsetT
) 1 << 31))
3598 - ((offsetT
) 1 << 31));
3601 = operand_type_or (i
.types
[op
],
3602 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3604 /* We must avoid matching of Imm32 templates when 64bit
3605 only immediate is available. */
3606 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3607 i
.types
[op
].bitfield
.imm32
= 0;
3614 /* Symbols and expressions. */
3616 /* Convert symbolic operand to proper sizes for matching, but don't
3617 prevent matching a set of insns that only supports sizes other
3618 than those matching the insn suffix. */
3620 i386_operand_type mask
, allowed
;
3621 const insn_template
*t
;
3623 operand_type_set (&mask
, 0);
3624 operand_type_set (&allowed
, 0);
3626 for (t
= current_templates
->start
;
3627 t
< current_templates
->end
;
3629 allowed
= operand_type_or (allowed
,
3630 t
->operand_types
[op
]);
3631 switch (guess_suffix
)
3633 case QWORD_MNEM_SUFFIX
:
3634 mask
.bitfield
.imm64
= 1;
3635 mask
.bitfield
.imm32s
= 1;
3637 case LONG_MNEM_SUFFIX
:
3638 mask
.bitfield
.imm32
= 1;
3640 case WORD_MNEM_SUFFIX
:
3641 mask
.bitfield
.imm16
= 1;
3643 case BYTE_MNEM_SUFFIX
:
3644 mask
.bitfield
.imm8
= 1;
3649 allowed
= operand_type_and (mask
, allowed
);
3650 if (!operand_type_all_zero (&allowed
))
3651 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3658 /* Try to use the smallest displacement type too. */
3660 optimize_disp (void)
3664 for (op
= i
.operands
; --op
>= 0;)
3665 if (operand_type_check (i
.types
[op
], disp
))
3667 if (i
.op
[op
].disps
->X_op
== O_constant
)
3669 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3671 if (i
.types
[op
].bitfield
.disp16
3672 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3674 /* If this operand is at most 16 bits, convert
3675 to a signed 16 bit number and don't use 64bit
3677 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3678 i
.types
[op
].bitfield
.disp64
= 0;
3680 if (i
.types
[op
].bitfield
.disp32
3681 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3683 /* If this operand is at most 32 bits, convert
3684 to a signed 32 bit number and don't use 64bit
3686 op_disp
&= (((offsetT
) 2 << 31) - 1);
3687 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3688 i
.types
[op
].bitfield
.disp64
= 0;
3690 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3692 i
.types
[op
].bitfield
.disp8
= 0;
3693 i
.types
[op
].bitfield
.disp16
= 0;
3694 i
.types
[op
].bitfield
.disp32
= 0;
3695 i
.types
[op
].bitfield
.disp32s
= 0;
3696 i
.types
[op
].bitfield
.disp64
= 0;
3700 else if (flag_code
== CODE_64BIT
)
3702 if (fits_in_signed_long (op_disp
))
3704 i
.types
[op
].bitfield
.disp64
= 0;
3705 i
.types
[op
].bitfield
.disp32s
= 1;
3707 if (i
.prefix
[ADDR_PREFIX
]
3708 && fits_in_unsigned_long (op_disp
))
3709 i
.types
[op
].bitfield
.disp32
= 1;
3711 if ((i
.types
[op
].bitfield
.disp32
3712 || i
.types
[op
].bitfield
.disp32s
3713 || i
.types
[op
].bitfield
.disp16
)
3714 && fits_in_signed_byte (op_disp
))
3715 i
.types
[op
].bitfield
.disp8
= 1;
3717 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3718 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3720 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3721 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3722 i
.types
[op
].bitfield
.disp8
= 0;
3723 i
.types
[op
].bitfield
.disp16
= 0;
3724 i
.types
[op
].bitfield
.disp32
= 0;
3725 i
.types
[op
].bitfield
.disp32s
= 0;
3726 i
.types
[op
].bitfield
.disp64
= 0;
3729 /* We only support 64bit displacement on constants. */
3730 i
.types
[op
].bitfield
.disp64
= 0;
3734 /* Check if operands are valid for the instrucrtion. Update VEX
3738 VEX_check_operands (const insn_template
*t
)
3740 if (!t
->opcode_modifier
.vex
)
3743 /* Only check VEX_Imm4, which must be the first operand. */
3744 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3746 if (i
.op
[0].imms
->X_op
!= O_constant
3747 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3750 /* Turn off Imm8 so that update_imm won't complain. */
3751 i
.types
[0] = vec_imm4
;
3757 static const insn_template
*
3758 match_template (void)
3760 /* Points to template once we've found it. */
3761 const insn_template
*t
;
3762 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3763 i386_operand_type overlap4
;
3764 unsigned int found_reverse_match
;
3765 i386_opcode_modifier suffix_check
;
3766 i386_operand_type operand_types
[MAX_OPERANDS
];
3767 int addr_prefix_disp
;
3769 unsigned int found_cpu_match
;
3770 unsigned int check_register
;
3772 #if MAX_OPERANDS != 5
3773 # error "MAX_OPERANDS must be 5."
3776 found_reverse_match
= 0;
3777 addr_prefix_disp
= -1;
3779 memset (&suffix_check
, 0, sizeof (suffix_check
));
3780 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3781 suffix_check
.no_bsuf
= 1;
3782 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3783 suffix_check
.no_wsuf
= 1;
3784 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3785 suffix_check
.no_ssuf
= 1;
3786 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3787 suffix_check
.no_lsuf
= 1;
3788 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3789 suffix_check
.no_qsuf
= 1;
3790 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3791 suffix_check
.no_ldsuf
= 1;
3793 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3795 addr_prefix_disp
= -1;
3797 /* Must have right number of operands. */
3798 if (i
.operands
!= t
->operands
)
3801 /* Check processor support. */
3802 found_cpu_match
= (cpu_flags_match (t
)
3803 == CPU_FLAGS_PERFECT_MATCH
);
3804 if (!found_cpu_match
)
3807 /* Check old gcc support. */
3808 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3811 /* Check AT&T mnemonic. */
3812 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3815 /* Check AT&T syntax Intel syntax. */
3816 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3817 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3820 /* Check the suffix, except for some instructions in intel mode. */
3821 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3822 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3823 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3824 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3825 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3826 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3827 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3830 if (!operand_size_match (t
))
3833 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3834 operand_types
[j
] = t
->operand_types
[j
];
3836 /* In general, don't allow 64-bit operands in 32-bit mode. */
3837 if (i
.suffix
== QWORD_MNEM_SUFFIX
3838 && flag_code
!= CODE_64BIT
3840 ? (!t
->opcode_modifier
.ignoresize
3841 && !intel_float_operand (t
->name
))
3842 : intel_float_operand (t
->name
) != 2)
3843 && ((!operand_types
[0].bitfield
.regmmx
3844 && !operand_types
[0].bitfield
.regxmm
3845 && !operand_types
[0].bitfield
.regymm
)
3846 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3847 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3848 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3849 && (t
->base_opcode
!= 0x0fc7
3850 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3853 /* In general, don't allow 32-bit operands on pre-386. */
3854 else if (i
.suffix
== LONG_MNEM_SUFFIX
3855 && !cpu_arch_flags
.bitfield
.cpui386
3857 ? (!t
->opcode_modifier
.ignoresize
3858 && !intel_float_operand (t
->name
))
3859 : intel_float_operand (t
->name
) != 2)
3860 && ((!operand_types
[0].bitfield
.regmmx
3861 && !operand_types
[0].bitfield
.regxmm
)
3862 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3863 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3866 /* Do not verify operands when there are none. */
3870 /* We've found a match; break out of loop. */
3874 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3875 into Disp32/Disp16/Disp32 operand. */
3876 if (i
.prefix
[ADDR_PREFIX
] != 0)
3878 /* There should be only one Disp operand. */
3882 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3884 if (operand_types
[j
].bitfield
.disp16
)
3886 addr_prefix_disp
= j
;
3887 operand_types
[j
].bitfield
.disp32
= 1;
3888 operand_types
[j
].bitfield
.disp16
= 0;
3894 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3896 if (operand_types
[j
].bitfield
.disp32
)
3898 addr_prefix_disp
= j
;
3899 operand_types
[j
].bitfield
.disp32
= 0;
3900 operand_types
[j
].bitfield
.disp16
= 1;
3906 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3908 if (operand_types
[j
].bitfield
.disp64
)
3910 addr_prefix_disp
= j
;
3911 operand_types
[j
].bitfield
.disp64
= 0;
3912 operand_types
[j
].bitfield
.disp32
= 1;
3920 /* We check register size only if size of operands can be
3921 encoded the canonical way. */
3922 check_register
= t
->opcode_modifier
.w
;
3923 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3924 switch (t
->operands
)
3927 if (!operand_type_match (overlap0
, i
.types
[0]))
3931 /* xchg %eax, %eax is a special case. It is an aliase for nop
3932 only in 32bit mode and we can use opcode 0x90. In 64bit
3933 mode, we can't use 0x90 for xchg %eax, %eax since it should
3934 zero-extend %eax to %rax. */
3935 if (flag_code
== CODE_64BIT
3936 && t
->base_opcode
== 0x90
3937 && operand_type_equal (&i
.types
[0], &acc32
)
3938 && operand_type_equal (&i
.types
[1], &acc32
))
3942 /* If we swap operand in encoding, we either match
3943 the next one or reverse direction of operands. */
3944 if (t
->opcode_modifier
.s
)
3946 else if (t
->opcode_modifier
.d
)
3951 /* If we swap operand in encoding, we match the next one. */
3952 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3956 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3957 if (!operand_type_match (overlap0
, i
.types
[0])
3958 || !operand_type_match (overlap1
, i
.types
[1])
3960 && !operand_type_register_match (overlap0
, i
.types
[0],
3962 overlap1
, i
.types
[1],
3965 /* Check if other direction is valid ... */
3966 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3970 /* Try reversing direction of operands. */
3971 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3972 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3973 if (!operand_type_match (overlap0
, i
.types
[0])
3974 || !operand_type_match (overlap1
, i
.types
[1])
3976 && !operand_type_register_match (overlap0
,
3983 /* Does not match either direction. */
3986 /* found_reverse_match holds which of D or FloatDR
3988 if (t
->opcode_modifier
.d
)
3989 found_reverse_match
= Opcode_D
;
3990 else if (t
->opcode_modifier
.floatd
)
3991 found_reverse_match
= Opcode_FloatD
;
3993 found_reverse_match
= 0;
3994 if (t
->opcode_modifier
.floatr
)
3995 found_reverse_match
|= Opcode_FloatR
;
3999 /* Found a forward 2 operand match here. */
4000 switch (t
->operands
)
4003 overlap4
= operand_type_and (i
.types
[4],
4006 overlap3
= operand_type_and (i
.types
[3],
4009 overlap2
= operand_type_and (i
.types
[2],
4014 switch (t
->operands
)
4017 if (!operand_type_match (overlap4
, i
.types
[4])
4018 || !operand_type_register_match (overlap3
,
4026 if (!operand_type_match (overlap3
, i
.types
[3])
4028 && !operand_type_register_match (overlap2
,
4036 /* Here we make use of the fact that there are no
4037 reverse match 3 operand instructions, and all 3
4038 operand instructions only need to be checked for
4039 register consistency between operands 2 and 3. */
4040 if (!operand_type_match (overlap2
, i
.types
[2])
4042 && !operand_type_register_match (overlap1
,
4052 /* Found either forward/reverse 2, 3 or 4 operand match here:
4053 slip through to break. */
4055 if (!found_cpu_match
)
4057 found_reverse_match
= 0;
4061 /* Check if VEX operands are valid. */
4062 if (VEX_check_operands (t
))
4065 /* We've found a match; break out of loop. */
4069 if (t
== current_templates
->end
)
4071 /* We found no match. */
4073 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4074 current_templates
->start
->name
);
4076 as_bad (_("suffix or operands invalid for `%s'"),
4077 current_templates
->start
->name
);
4081 if (!quiet_warnings
)
4084 && (i
.types
[0].bitfield
.jumpabsolute
4085 != operand_types
[0].bitfield
.jumpabsolute
))
4087 as_warn (_("indirect %s without `*'"), t
->name
);
4090 if (t
->opcode_modifier
.isprefix
4091 && t
->opcode_modifier
.ignoresize
)
4093 /* Warn them that a data or address size prefix doesn't
4094 affect assembly of the next line of code. */
4095 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4099 /* Copy the template we found. */
4102 if (addr_prefix_disp
!= -1)
4103 i
.tm
.operand_types
[addr_prefix_disp
]
4104 = operand_types
[addr_prefix_disp
];
4106 if (found_reverse_match
)
4108 /* If we found a reverse match we must alter the opcode
4109 direction bit. found_reverse_match holds bits to change
4110 (different for int & float insns). */
4112 i
.tm
.base_opcode
^= found_reverse_match
;
4114 i
.tm
.operand_types
[0] = operand_types
[1];
4115 i
.tm
.operand_types
[1] = operand_types
[0];
4124 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4125 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4127 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4129 as_bad (_("`%s' operand %d must use `%ses' segment"),
4135 /* There's only ever one segment override allowed per instruction.
4136 This instruction possibly has a legal segment override on the
4137 second operand, so copy the segment to where non-string
4138 instructions store it, allowing common code. */
4139 i
.seg
[0] = i
.seg
[1];
4141 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4143 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4145 as_bad (_("`%s' operand %d must use `%ses' segment"),
4156 process_suffix (void)
4158 /* If matched instruction specifies an explicit instruction mnemonic
4160 if (i
.tm
.opcode_modifier
.size16
)
4161 i
.suffix
= WORD_MNEM_SUFFIX
;
4162 else if (i
.tm
.opcode_modifier
.size32
)
4163 i
.suffix
= LONG_MNEM_SUFFIX
;
4164 else if (i
.tm
.opcode_modifier
.size64
)
4165 i
.suffix
= QWORD_MNEM_SUFFIX
;
4166 else if (i
.reg_operands
)
4168 /* If there's no instruction mnemonic suffix we try to invent one
4169 based on register operands. */
4172 /* We take i.suffix from the last register operand specified,
4173 Destination register type is more significant than source
4174 register type. crc32 in SSE4.2 prefers source register
4176 if (i
.tm
.base_opcode
== 0xf20f38f1)
4178 if (i
.types
[0].bitfield
.reg16
)
4179 i
.suffix
= WORD_MNEM_SUFFIX
;
4180 else if (i
.types
[0].bitfield
.reg32
)
4181 i
.suffix
= LONG_MNEM_SUFFIX
;
4182 else if (i
.types
[0].bitfield
.reg64
)
4183 i
.suffix
= QWORD_MNEM_SUFFIX
;
4185 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4187 if (i
.types
[0].bitfield
.reg8
)
4188 i
.suffix
= BYTE_MNEM_SUFFIX
;
4195 if (i
.tm
.base_opcode
== 0xf20f38f1
4196 || i
.tm
.base_opcode
== 0xf20f38f0)
4198 /* We have to know the operand size for crc32. */
4199 as_bad (_("ambiguous memory operand size for `%s`"),
4204 for (op
= i
.operands
; --op
>= 0;)
4205 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4207 if (i
.types
[op
].bitfield
.reg8
)
4209 i
.suffix
= BYTE_MNEM_SUFFIX
;
4212 else if (i
.types
[op
].bitfield
.reg16
)
4214 i
.suffix
= WORD_MNEM_SUFFIX
;
4217 else if (i
.types
[op
].bitfield
.reg32
)
4219 i
.suffix
= LONG_MNEM_SUFFIX
;
4222 else if (i
.types
[op
].bitfield
.reg64
)
4224 i
.suffix
= QWORD_MNEM_SUFFIX
;
4230 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4233 && i
.tm
.opcode_modifier
.ignoresize
4234 && i
.tm
.opcode_modifier
.no_bsuf
)
4236 else if (!check_byte_reg ())
4239 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4242 && i
.tm
.opcode_modifier
.ignoresize
4243 && i
.tm
.opcode_modifier
.no_lsuf
)
4245 else if (!check_long_reg ())
4248 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4251 && i
.tm
.opcode_modifier
.ignoresize
4252 && i
.tm
.opcode_modifier
.no_qsuf
)
4254 else if (!check_qword_reg ())
4257 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4260 && i
.tm
.opcode_modifier
.ignoresize
4261 && i
.tm
.opcode_modifier
.no_wsuf
)
4263 else if (!check_word_reg ())
4266 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4267 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4269 /* Skip if the instruction has x/y suffix. match_template
4270 should check if it is a valid suffix. */
4272 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4273 /* Do nothing if the instruction is going to ignore the prefix. */
4278 else if (i
.tm
.opcode_modifier
.defaultsize
4280 /* exclude fldenv/frstor/fsave/fstenv */
4281 && i
.tm
.opcode_modifier
.no_ssuf
)
4283 i
.suffix
= stackop_size
;
4285 else if (intel_syntax
4287 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4288 || i
.tm
.opcode_modifier
.jumpbyte
4289 || i
.tm
.opcode_modifier
.jumpintersegment
4290 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4291 && i
.tm
.extension_opcode
<= 3)))
4296 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4298 i
.suffix
= QWORD_MNEM_SUFFIX
;
4302 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4303 i
.suffix
= LONG_MNEM_SUFFIX
;
4306 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4307 i
.suffix
= WORD_MNEM_SUFFIX
;
4316 if (i
.tm
.opcode_modifier
.w
)
4318 as_bad (_("no instruction mnemonic suffix given and "
4319 "no register operands; can't size instruction"));
4325 unsigned int suffixes
;
4327 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4328 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4330 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4332 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4334 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4336 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4339 /* There are more than suffix matches. */
4340 if (i
.tm
.opcode_modifier
.w
4341 || ((suffixes
& (suffixes
- 1))
4342 && !i
.tm
.opcode_modifier
.defaultsize
4343 && !i
.tm
.opcode_modifier
.ignoresize
))
4345 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4351 /* Change the opcode based on the operand size given by i.suffix;
4352 We don't need to change things for byte insns. */
4355 && i
.suffix
!= BYTE_MNEM_SUFFIX
4356 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4357 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4359 /* It's not a byte, select word/dword operation. */
4360 if (i
.tm
.opcode_modifier
.w
)
4362 if (i
.tm
.opcode_modifier
.shortform
)
4363 i
.tm
.base_opcode
|= 8;
4365 i
.tm
.base_opcode
|= 1;
4368 /* Now select between word & dword operations via the operand
4369 size prefix, except for instructions that will ignore this
4371 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4373 /* The address size override prefix changes the size of the
4375 if ((flag_code
== CODE_32BIT
4376 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4377 || (flag_code
!= CODE_32BIT
4378 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4379 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4382 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4383 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4384 && !i
.tm
.opcode_modifier
.ignoresize
4385 && !i
.tm
.opcode_modifier
.floatmf
4386 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4387 || (flag_code
== CODE_64BIT
4388 && i
.tm
.opcode_modifier
.jumpbyte
)))
4390 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4392 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4393 prefix
= ADDR_PREFIX_OPCODE
;
4395 if (!add_prefix (prefix
))
4399 /* Set mode64 for an operand. */
4400 if (i
.suffix
== QWORD_MNEM_SUFFIX
4401 && flag_code
== CODE_64BIT
4402 && !i
.tm
.opcode_modifier
.norex64
)
4404 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4405 need rex64. cmpxchg8b is also a special case. */
4406 if (! (i
.operands
== 2
4407 && i
.tm
.base_opcode
== 0x90
4408 && i
.tm
.extension_opcode
== None
4409 && operand_type_equal (&i
.types
[0], &acc64
)
4410 && operand_type_equal (&i
.types
[1], &acc64
))
4411 && ! (i
.operands
== 1
4412 && i
.tm
.base_opcode
== 0xfc7
4413 && i
.tm
.extension_opcode
== 1
4414 && !operand_type_check (i
.types
[0], reg
)
4415 && operand_type_check (i
.types
[0], anymem
)))
4419 /* Size floating point instruction. */
4420 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4421 if (i
.tm
.opcode_modifier
.floatmf
)
4422 i
.tm
.base_opcode
^= 4;
4429 check_byte_reg (void)
4433 for (op
= i
.operands
; --op
>= 0;)
4435 /* If this is an eight bit register, it's OK. If it's the 16 or
4436 32 bit version of an eight bit register, we will just use the
4437 low portion, and that's OK too. */
4438 if (i
.types
[op
].bitfield
.reg8
)
4441 /* crc32 doesn't generate this warning. */
4442 if (i
.tm
.base_opcode
== 0xf20f38f0)
4445 if ((i
.types
[op
].bitfield
.reg16
4446 || i
.types
[op
].bitfield
.reg32
4447 || i
.types
[op
].bitfield
.reg64
)
4448 && i
.op
[op
].regs
->reg_num
< 4)
4450 /* Prohibit these changes in the 64bit mode, since the
4451 lowering is more complicated. */
4452 if (flag_code
== CODE_64BIT
4453 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4455 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4456 register_prefix
, i
.op
[op
].regs
->reg_name
,
4460 #if REGISTER_WARNINGS
4462 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4463 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4465 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4466 ? REGNAM_AL
- REGNAM_AX
4467 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4469 i
.op
[op
].regs
->reg_name
,
4474 /* Any other register is bad. */
4475 if (i
.types
[op
].bitfield
.reg16
4476 || i
.types
[op
].bitfield
.reg32
4477 || i
.types
[op
].bitfield
.reg64
4478 || i
.types
[op
].bitfield
.regmmx
4479 || i
.types
[op
].bitfield
.regxmm
4480 || i
.types
[op
].bitfield
.regymm
4481 || i
.types
[op
].bitfield
.sreg2
4482 || i
.types
[op
].bitfield
.sreg3
4483 || i
.types
[op
].bitfield
.control
4484 || i
.types
[op
].bitfield
.debug
4485 || i
.types
[op
].bitfield
.test
4486 || i
.types
[op
].bitfield
.floatreg
4487 || i
.types
[op
].bitfield
.floatacc
)
4489 as_bad (_("`%s%s' not allowed with `%s%c'"),
4491 i
.op
[op
].regs
->reg_name
,
4501 check_long_reg (void)
4505 for (op
= i
.operands
; --op
>= 0;)
4506 /* Reject eight bit registers, except where the template requires
4507 them. (eg. movzb) */
4508 if (i
.types
[op
].bitfield
.reg8
4509 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4510 || i
.tm
.operand_types
[op
].bitfield
.reg32
4511 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4513 as_bad (_("`%s%s' not allowed with `%s%c'"),
4515 i
.op
[op
].regs
->reg_name
,
4520 /* Warn if the e prefix on a general reg is missing. */
4521 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4522 && i
.types
[op
].bitfield
.reg16
4523 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4524 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4526 /* Prohibit these changes in the 64bit mode, since the
4527 lowering is more complicated. */
4528 if (flag_code
== CODE_64BIT
)
4530 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4531 register_prefix
, i
.op
[op
].regs
->reg_name
,
4535 #if REGISTER_WARNINGS
4537 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4539 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4541 i
.op
[op
].regs
->reg_name
,
4545 /* Warn if the r prefix on a general reg is missing. */
4546 else if (i
.types
[op
].bitfield
.reg64
4547 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4548 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4551 && i
.tm
.opcode_modifier
.toqword
4552 && !i
.types
[0].bitfield
.regxmm
)
4554 /* Convert to QWORD. We want REX byte. */
4555 i
.suffix
= QWORD_MNEM_SUFFIX
;
4559 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4560 register_prefix
, i
.op
[op
].regs
->reg_name
,
4569 check_qword_reg (void)
4573 for (op
= i
.operands
; --op
>= 0; )
4574 /* Reject eight bit registers, except where the template requires
4575 them. (eg. movzb) */
4576 if (i
.types
[op
].bitfield
.reg8
4577 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4578 || i
.tm
.operand_types
[op
].bitfield
.reg32
4579 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4581 as_bad (_("`%s%s' not allowed with `%s%c'"),
4583 i
.op
[op
].regs
->reg_name
,
4588 /* Warn if the e prefix on a general reg is missing. */
4589 else if ((i
.types
[op
].bitfield
.reg16
4590 || i
.types
[op
].bitfield
.reg32
)
4591 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4592 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4594 /* Prohibit these changes in the 64bit mode, since the
4595 lowering is more complicated. */
4597 && i
.tm
.opcode_modifier
.todword
4598 && !i
.types
[0].bitfield
.regxmm
)
4600 /* Convert to DWORD. We don't want REX byte. */
4601 i
.suffix
= LONG_MNEM_SUFFIX
;
4605 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4606 register_prefix
, i
.op
[op
].regs
->reg_name
,
4615 check_word_reg (void)
4618 for (op
= i
.operands
; --op
>= 0;)
4619 /* Reject eight bit registers, except where the template requires
4620 them. (eg. movzb) */
4621 if (i
.types
[op
].bitfield
.reg8
4622 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4623 || i
.tm
.operand_types
[op
].bitfield
.reg32
4624 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4626 as_bad (_("`%s%s' not allowed with `%s%c'"),
4628 i
.op
[op
].regs
->reg_name
,
4633 /* Warn if the e prefix on a general reg is present. */
4634 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4635 && i
.types
[op
].bitfield
.reg32
4636 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4637 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4639 /* Prohibit these changes in the 64bit mode, since the
4640 lowering is more complicated. */
4641 if (flag_code
== CODE_64BIT
)
4643 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4644 register_prefix
, i
.op
[op
].regs
->reg_name
,
4649 #if REGISTER_WARNINGS
4650 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4652 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4654 i
.op
[op
].regs
->reg_name
,
4662 update_imm (unsigned int j
)
4664 i386_operand_type overlap
= i
.types
[j
];
4665 if ((overlap
.bitfield
.imm8
4666 || overlap
.bitfield
.imm8s
4667 || overlap
.bitfield
.imm16
4668 || overlap
.bitfield
.imm32
4669 || overlap
.bitfield
.imm32s
4670 || overlap
.bitfield
.imm64
)
4671 && !operand_type_equal (&overlap
, &imm8
)
4672 && !operand_type_equal (&overlap
, &imm8s
)
4673 && !operand_type_equal (&overlap
, &imm16
)
4674 && !operand_type_equal (&overlap
, &imm32
)
4675 && !operand_type_equal (&overlap
, &imm32s
)
4676 && !operand_type_equal (&overlap
, &imm64
))
4680 i386_operand_type temp
;
4682 operand_type_set (&temp
, 0);
4683 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4685 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4686 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4688 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4689 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4690 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4692 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4693 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4696 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4699 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4700 || operand_type_equal (&overlap
, &imm16_32
)
4701 || operand_type_equal (&overlap
, &imm16_32s
))
4703 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4708 if (!operand_type_equal (&overlap
, &imm8
)
4709 && !operand_type_equal (&overlap
, &imm8s
)
4710 && !operand_type_equal (&overlap
, &imm16
)
4711 && !operand_type_equal (&overlap
, &imm32
)
4712 && !operand_type_equal (&overlap
, &imm32s
)
4713 && !operand_type_equal (&overlap
, &imm64
))
4715 as_bad (_("no instruction mnemonic suffix given; "
4716 "can't determine immediate size"));
4720 i
.types
[j
] = overlap
;
4730 /* Update the first 2 immediate operands. */
4731 n
= i
.operands
> 2 ? 2 : i
.operands
;
4734 for (j
= 0; j
< n
; j
++)
4735 if (update_imm (j
) == 0)
4738 /* The 3rd operand can't be immediate operand. */
4739 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4746 bad_implicit_operand (int xmm
)
4748 const char *ireg
= xmm
? "xmm0" : "ymm0";
4751 as_bad (_("the last operand of `%s' must be `%s%s'"),
4752 i
.tm
.name
, register_prefix
, ireg
);
4754 as_bad (_("the first operand of `%s' must be `%s%s'"),
4755 i
.tm
.name
, register_prefix
, ireg
);
4760 process_operands (void)
4762 /* Default segment register this instruction will use for memory
4763 accesses. 0 means unknown. This is only for optimizing out
4764 unnecessary segment overrides. */
4765 const seg_entry
*default_seg
= 0;
4767 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4769 unsigned int dupl
= i
.operands
;
4770 unsigned int dest
= dupl
- 1;
4773 /* The destination must be an xmm register. */
4774 gas_assert (i
.reg_operands
4775 && MAX_OPERANDS
> dupl
4776 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4778 if (i
.tm
.opcode_modifier
.firstxmm0
)
4780 /* The first operand is implicit and must be xmm0. */
4781 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4782 if (i
.op
[0].regs
->reg_num
!= 0)
4783 return bad_implicit_operand (1);
4785 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4787 /* Keep xmm0 for instructions with VEX prefix and 3
4793 /* We remove the first xmm0 and keep the number of
4794 operands unchanged, which in fact duplicates the
4796 for (j
= 1; j
< i
.operands
; j
++)
4798 i
.op
[j
- 1] = i
.op
[j
];
4799 i
.types
[j
- 1] = i
.types
[j
];
4800 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4804 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4806 gas_assert ((MAX_OPERANDS
- 1) > dupl
4807 && (i
.tm
.opcode_modifier
.vexsources
4810 /* Add the implicit xmm0 for instructions with VEX prefix
4812 for (j
= i
.operands
; j
> 0; j
--)
4814 i
.op
[j
] = i
.op
[j
- 1];
4815 i
.types
[j
] = i
.types
[j
- 1];
4816 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4819 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4820 i
.types
[0] = regxmm
;
4821 i
.tm
.operand_types
[0] = regxmm
;
4824 i
.reg_operands
+= 2;
4829 i
.op
[dupl
] = i
.op
[dest
];
4830 i
.types
[dupl
] = i
.types
[dest
];
4831 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4840 i
.op
[dupl
] = i
.op
[dest
];
4841 i
.types
[dupl
] = i
.types
[dest
];
4842 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4845 if (i
.tm
.opcode_modifier
.immext
)
4848 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4852 /* The first operand is implicit and must be xmm0/ymm0. */
4853 gas_assert (i
.reg_operands
4854 && (operand_type_equal (&i
.types
[0], ®xmm
)
4855 || operand_type_equal (&i
.types
[0], ®ymm
)));
4856 if (i
.op
[0].regs
->reg_num
!= 0)
4857 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4859 for (j
= 1; j
< i
.operands
; j
++)
4861 i
.op
[j
- 1] = i
.op
[j
];
4862 i
.types
[j
- 1] = i
.types
[j
];
4864 /* We need to adjust fields in i.tm since they are used by
4865 build_modrm_byte. */
4866 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4873 else if (i
.tm
.opcode_modifier
.regkludge
)
4875 /* The imul $imm, %reg instruction is converted into
4876 imul $imm, %reg, %reg, and the clr %reg instruction
4877 is converted into xor %reg, %reg. */
4879 unsigned int first_reg_op
;
4881 if (operand_type_check (i
.types
[0], reg
))
4885 /* Pretend we saw the extra register operand. */
4886 gas_assert (i
.reg_operands
== 1
4887 && i
.op
[first_reg_op
+ 1].regs
== 0);
4888 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4889 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4894 if (i
.tm
.opcode_modifier
.shortform
)
4896 if (i
.types
[0].bitfield
.sreg2
4897 || i
.types
[0].bitfield
.sreg3
)
4899 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4900 && i
.op
[0].regs
->reg_num
== 1)
4902 as_bad (_("you can't `pop %scs'"), register_prefix
);
4905 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4906 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4911 /* The register or float register operand is in operand
4915 if (i
.types
[0].bitfield
.floatreg
4916 || operand_type_check (i
.types
[0], reg
))
4920 /* Register goes in low 3 bits of opcode. */
4921 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4922 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4924 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4926 /* Warn about some common errors, but press on regardless.
4927 The first case can be generated by gcc (<= 2.8.1). */
4928 if (i
.operands
== 2)
4930 /* Reversed arguments on faddp, fsubp, etc. */
4931 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4932 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4933 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4937 /* Extraneous `l' suffix on fp insn. */
4938 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4939 register_prefix
, i
.op
[0].regs
->reg_name
);
4944 else if (i
.tm
.opcode_modifier
.modrm
)
4946 /* The opcode is completed (modulo i.tm.extension_opcode which
4947 must be put into the modrm byte). Now, we make the modrm and
4948 index base bytes based on all the info we've collected. */
4950 default_seg
= build_modrm_byte ();
4952 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4956 else if (i
.tm
.opcode_modifier
.isstring
)
4958 /* For the string instructions that allow a segment override
4959 on one of their operands, the default segment is ds. */
4963 if (i
.tm
.base_opcode
== 0x8d /* lea */
4966 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4968 /* If a segment was explicitly specified, and the specified segment
4969 is not the default, use an opcode prefix to select it. If we
4970 never figured out what the default segment is, then default_seg
4971 will be zero at this point, and the specified segment prefix will
4973 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4975 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4981 static const seg_entry
*
4982 build_modrm_byte (void)
4984 const seg_entry
*default_seg
= 0;
4985 unsigned int source
, dest
;
4988 /* The first operand of instructions with VEX prefix and 3 sources
4989 must be VEX_Imm4. */
4990 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
4993 unsigned int nds
, reg_slot
;
4996 if (i
.tm
.opcode_modifier
.veximmext
4997 && i
.tm
.opcode_modifier
.immext
)
4999 dest
= i
.operands
- 2;
5000 gas_assert (dest
== 3);
5003 dest
= i
.operands
- 1;
5006 /* There are 2 kinds of instructions:
5007 1. 5 operands: 4 register operands or 3 register operands
5008 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5009 VexW0 or VexW1. The destination must be either XMM or YMM
5011 2. 4 operands: 4 register operands or 3 register operands
5012 plus 1 memory operand, VexXDS, and VexImmExt */
5013 gas_assert ((i
.reg_operands
== 4
5014 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5015 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5016 && (i
.tm
.opcode_modifier
.veximmext
5017 || (i
.imm_operands
== 1
5018 && i
.types
[0].bitfield
.vec_imm4
5019 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5020 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5021 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5022 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5024 if (i
.imm_operands
== 0)
5026 /* When there is no immediate operand, generate an 8bit
5027 immediate operand to encode the first operand. */
5028 exp
= &im_expressions
[i
.imm_operands
++];
5029 i
.op
[i
.operands
].imms
= exp
;
5030 i
.types
[i
.operands
] = imm8
;
5032 /* If VexW1 is set, the first operand is the source and
5033 the second operand is encoded in the immediate operand. */
5034 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5045 /* FMA swaps REG and NDS. */
5046 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5054 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
], ®xmm
)
5055 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5057 exp
->X_op
= O_constant
;
5059 = ((i
.op
[reg_slot
].regs
->reg_num
5060 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5064 unsigned int imm_slot
;
5066 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5068 /* If VexW0 is set, the third operand is the source and
5069 the second operand is encoded in the immediate
5076 /* VexW1 is set, the second operand is the source and
5077 the third operand is encoded in the immediate
5083 if (i
.tm
.opcode_modifier
.immext
)
5085 /* When ImmExt is set, the immdiate byte is the last
5087 imm_slot
= i
.operands
- 1;
5095 /* Turn on Imm8 so that output_imm will generate it. */
5096 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5099 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
], ®xmm
)
5100 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5102 i
.op
[imm_slot
].imms
->X_add_number
5103 |= ((i
.op
[reg_slot
].regs
->reg_num
5104 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5107 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5108 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5110 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5115 /* i.reg_operands MUST be the number of real register operands;
5116 implicit registers do not count. If there are 3 register
5117 operands, it must be a instruction with VexNDS. For a
5118 instruction with VexNDD, the destination register is encoded
5119 in VEX prefix. If there are 4 register operands, it must be
5120 a instruction with VEX prefix and 3 sources. */
5121 if (i
.mem_operands
== 0
5122 && ((i
.reg_operands
== 2
5123 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5124 || (i
.reg_operands
== 3
5125 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5126 || (i
.reg_operands
== 4 && vex_3_sources
)))
5134 /* When there are 3 operands, one of them may be immediate,
5135 which may be the first or the last operand. Otherwise,
5136 the first operand must be shift count register (cl) or it
5137 is an instruction with VexNDS. */
5138 gas_assert (i
.imm_operands
== 1
5139 || (i
.imm_operands
== 0
5140 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5141 || i
.types
[0].bitfield
.shiftcount
)));
5142 if (operand_type_check (i
.types
[0], imm
)
5143 || i
.types
[0].bitfield
.shiftcount
)
5149 /* When there are 4 operands, the first two must be 8bit
5150 immediate operands. The source operand will be the 3rd
5153 For instructions with VexNDS, if the first operand
5154 an imm8, the source operand is the 2nd one. If the last
5155 operand is imm8, the source operand is the first one. */
5156 gas_assert ((i
.imm_operands
== 2
5157 && i
.types
[0].bitfield
.imm8
5158 && i
.types
[1].bitfield
.imm8
)
5159 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5160 && i
.imm_operands
== 1
5161 && (i
.types
[0].bitfield
.imm8
5162 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5163 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5165 if (i
.types
[0].bitfield
.imm8
)
5183 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5185 /* For instructions with VexNDS, the register-only
5186 source operand must be XMM or YMM register. It is
5187 encoded in VEX prefix. We need to clear RegMem bit
5188 before calling operand_type_equal. */
5189 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5190 op
.bitfield
.regmem
= 0;
5191 if ((dest
+ 1) >= i
.operands
5192 || (!operand_type_equal (&op
, ®xmm
)
5193 && !operand_type_equal (&op
, ®ymm
)))
5195 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5201 /* One of the register operands will be encoded in the i.tm.reg
5202 field, the other in the combined i.tm.mode and i.tm.regmem
5203 fields. If no form of this instruction supports a memory
5204 destination operand, then we assume the source operand may
5205 sometimes be a memory operand and so we need to store the
5206 destination in the i.rm.reg field. */
5207 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5208 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5210 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5211 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5212 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5214 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5219 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5220 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5221 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5223 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5226 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5228 if (!i
.types
[0].bitfield
.control
5229 && !i
.types
[1].bitfield
.control
)
5231 i
.rex
&= ~(REX_R
| REX_B
);
5232 add_prefix (LOCK_PREFIX_OPCODE
);
5236 { /* If it's not 2 reg operands... */
5241 unsigned int fake_zero_displacement
= 0;
5244 for (op
= 0; op
< i
.operands
; op
++)
5245 if (operand_type_check (i
.types
[op
], anymem
))
5247 gas_assert (op
< i
.operands
);
5251 if (i
.base_reg
== 0)
5254 if (!i
.disp_operands
)
5255 fake_zero_displacement
= 1;
5256 if (i
.index_reg
== 0)
5258 /* Operand is just <disp> */
5259 if (flag_code
== CODE_64BIT
)
5261 /* 64bit mode overwrites the 32bit absolute
5262 addressing by RIP relative addressing and
5263 absolute addressing is encoded by one of the
5264 redundant SIB forms. */
5265 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5266 i
.sib
.base
= NO_BASE_REGISTER
;
5267 i
.sib
.index
= NO_INDEX_REGISTER
;
5268 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5269 ? disp32s
: disp32
);
5271 else if ((flag_code
== CODE_16BIT
)
5272 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5274 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5275 i
.types
[op
] = disp16
;
5279 i
.rm
.regmem
= NO_BASE_REGISTER
;
5280 i
.types
[op
] = disp32
;
5283 else /* !i.base_reg && i.index_reg */
5285 if (i
.index_reg
->reg_num
== RegEiz
5286 || i
.index_reg
->reg_num
== RegRiz
)
5287 i
.sib
.index
= NO_INDEX_REGISTER
;
5289 i
.sib
.index
= i
.index_reg
->reg_num
;
5290 i
.sib
.base
= NO_BASE_REGISTER
;
5291 i
.sib
.scale
= i
.log2_scale_factor
;
5292 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5293 i
.types
[op
].bitfield
.disp8
= 0;
5294 i
.types
[op
].bitfield
.disp16
= 0;
5295 i
.types
[op
].bitfield
.disp64
= 0;
5296 if (flag_code
!= CODE_64BIT
)
5298 /* Must be 32 bit */
5299 i
.types
[op
].bitfield
.disp32
= 1;
5300 i
.types
[op
].bitfield
.disp32s
= 0;
5304 i
.types
[op
].bitfield
.disp32
= 0;
5305 i
.types
[op
].bitfield
.disp32s
= 1;
5307 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5311 /* RIP addressing for 64bit mode. */
5312 else if (i
.base_reg
->reg_num
== RegRip
||
5313 i
.base_reg
->reg_num
== RegEip
)
5315 i
.rm
.regmem
= NO_BASE_REGISTER
;
5316 i
.types
[op
].bitfield
.disp8
= 0;
5317 i
.types
[op
].bitfield
.disp16
= 0;
5318 i
.types
[op
].bitfield
.disp32
= 0;
5319 i
.types
[op
].bitfield
.disp32s
= 1;
5320 i
.types
[op
].bitfield
.disp64
= 0;
5321 i
.flags
[op
] |= Operand_PCrel
;
5322 if (! i
.disp_operands
)
5323 fake_zero_displacement
= 1;
5325 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5327 switch (i
.base_reg
->reg_num
)
5330 if (i
.index_reg
== 0)
5332 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5333 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5337 if (i
.index_reg
== 0)
5340 if (operand_type_check (i
.types
[op
], disp
) == 0)
5342 /* fake (%bp) into 0(%bp) */
5343 i
.types
[op
].bitfield
.disp8
= 1;
5344 fake_zero_displacement
= 1;
5347 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5348 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5350 default: /* (%si) -> 4 or (%di) -> 5 */
5351 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5353 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5355 else /* i.base_reg and 32/64 bit mode */
5357 if (flag_code
== CODE_64BIT
5358 && operand_type_check (i
.types
[op
], disp
))
5360 i386_operand_type temp
;
5361 operand_type_set (&temp
, 0);
5362 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5364 if (i
.prefix
[ADDR_PREFIX
] == 0)
5365 i
.types
[op
].bitfield
.disp32s
= 1;
5367 i
.types
[op
].bitfield
.disp32
= 1;
5370 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5371 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5373 i
.sib
.base
= i
.base_reg
->reg_num
;
5374 /* x86-64 ignores REX prefix bit here to avoid decoder
5376 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5379 if (i
.disp_operands
== 0)
5381 fake_zero_displacement
= 1;
5382 i
.types
[op
].bitfield
.disp8
= 1;
5385 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5389 i
.sib
.scale
= i
.log2_scale_factor
;
5390 if (i
.index_reg
== 0)
5392 /* <disp>(%esp) becomes two byte modrm with no index
5393 register. We've already stored the code for esp
5394 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5395 Any base register besides %esp will not use the
5396 extra modrm byte. */
5397 i
.sib
.index
= NO_INDEX_REGISTER
;
5401 if (i
.index_reg
->reg_num
== RegEiz
5402 || i
.index_reg
->reg_num
== RegRiz
)
5403 i
.sib
.index
= NO_INDEX_REGISTER
;
5405 i
.sib
.index
= i
.index_reg
->reg_num
;
5406 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5407 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5412 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5413 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5416 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5419 if (fake_zero_displacement
)
5421 /* Fakes a zero displacement assuming that i.types[op]
5422 holds the correct displacement size. */
5425 gas_assert (i
.op
[op
].disps
== 0);
5426 exp
= &disp_expressions
[i
.disp_operands
++];
5427 i
.op
[op
].disps
= exp
;
5428 exp
->X_op
= O_constant
;
5429 exp
->X_add_number
= 0;
5430 exp
->X_add_symbol
= (symbolS
*) 0;
5431 exp
->X_op_symbol
= (symbolS
*) 0;
5439 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5441 if (operand_type_check (i
.types
[0], imm
))
5442 i
.vex
.register_specifier
= NULL
;
5445 /* VEX.vvvv encodes one of the sources when the first
5446 operand is not an immediate. */
5447 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5448 i
.vex
.register_specifier
= i
.op
[0].regs
;
5450 i
.vex
.register_specifier
= i
.op
[1].regs
;
5453 /* Destination is a XMM register encoded in the ModRM.reg
5455 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5456 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5459 /* ModRM.rm and VEX.B encodes the other source. */
5460 if (!i
.mem_operands
)
5464 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5465 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5467 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5469 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5473 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5475 i
.vex
.register_specifier
= i
.op
[2].regs
;
5476 if (!i
.mem_operands
)
5479 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5480 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5484 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5485 (if any) based on i.tm.extension_opcode. Again, we must be
5486 careful to make sure that segment/control/debug/test/MMX
5487 registers are coded into the i.rm.reg field. */
5488 else if (i
.reg_operands
)
5491 unsigned int vex_reg
= ~0;
5493 for (op
= 0; op
< i
.operands
; op
++)
5494 if (i
.types
[op
].bitfield
.reg8
5495 || i
.types
[op
].bitfield
.reg16
5496 || i
.types
[op
].bitfield
.reg32
5497 || i
.types
[op
].bitfield
.reg64
5498 || i
.types
[op
].bitfield
.regmmx
5499 || i
.types
[op
].bitfield
.regxmm
5500 || i
.types
[op
].bitfield
.regymm
5501 || i
.types
[op
].bitfield
.sreg2
5502 || i
.types
[op
].bitfield
.sreg3
5503 || i
.types
[op
].bitfield
.control
5504 || i
.types
[op
].bitfield
.debug
5505 || i
.types
[op
].bitfield
.test
)
5510 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5512 /* For instructions with VexNDS, the register-only
5513 source operand is encoded in VEX prefix. */
5514 gas_assert (mem
!= (unsigned int) ~0);
5519 gas_assert (op
< i
.operands
);
5524 gas_assert (vex_reg
< i
.operands
);
5527 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5529 /* For instructions with VexNDD, there should be
5530 no memory operand and the register destination
5531 is encoded in VEX prefix. */
5532 gas_assert (i
.mem_operands
== 0
5533 && (op
+ 2) == i
.operands
);
5537 gas_assert (op
< i
.operands
);
5539 if (vex_reg
!= (unsigned int) ~0)
5541 gas_assert (i
.reg_operands
== 2);
5543 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5545 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5549 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5552 /* Don't set OP operand twice. */
5555 /* If there is an extension opcode to put here, the
5556 register number must be put into the regmem field. */
5557 if (i
.tm
.extension_opcode
!= None
)
5559 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5560 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5565 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5566 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5571 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5572 must set it to 3 to indicate this is a register operand
5573 in the regmem field. */
5574 if (!i
.mem_operands
)
5578 /* Fill in i.rm.reg field with extension opcode (if any). */
5579 if (i
.tm
.extension_opcode
!= None
)
5580 i
.rm
.reg
= i
.tm
.extension_opcode
;
5586 output_branch (void)
5591 relax_substateT subtype
;
5596 if (flag_code
== CODE_16BIT
)
5600 if (i
.prefix
[DATA_PREFIX
] != 0)
5606 /* Pentium4 branch hints. */
5607 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5608 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5613 if (i
.prefix
[REX_PREFIX
] != 0)
5619 if (i
.prefixes
!= 0 && !intel_syntax
)
5620 as_warn (_("skipping prefixes on this instruction"));
5622 /* It's always a symbol; End frag & setup for relax.
5623 Make sure there is enough room in this frag for the largest
5624 instruction we may generate in md_convert_frag. This is 2
5625 bytes for the opcode and room for the prefix and largest
5627 frag_grow (prefix
+ 2 + 4);
5628 /* Prefix and 1 opcode byte go in fr_fix. */
5629 p
= frag_more (prefix
+ 1);
5630 if (i
.prefix
[DATA_PREFIX
] != 0)
5631 *p
++ = DATA_PREFIX_OPCODE
;
5632 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5633 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5634 *p
++ = i
.prefix
[SEG_PREFIX
];
5635 if (i
.prefix
[REX_PREFIX
] != 0)
5636 *p
++ = i
.prefix
[REX_PREFIX
];
5637 *p
= i
.tm
.base_opcode
;
5639 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5640 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5641 else if (cpu_arch_flags
.bitfield
.cpui386
)
5642 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5644 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5647 sym
= i
.op
[0].disps
->X_add_symbol
;
5648 off
= i
.op
[0].disps
->X_add_number
;
5650 if (i
.op
[0].disps
->X_op
!= O_constant
5651 && i
.op
[0].disps
->X_op
!= O_symbol
)
5653 /* Handle complex expressions. */
5654 sym
= make_expr_symbol (i
.op
[0].disps
);
5658 /* 1 possible extra opcode + 4 byte displacement go in var part.
5659 Pass reloc in fr_var. */
5660 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5670 if (i
.tm
.opcode_modifier
.jumpbyte
)
5672 /* This is a loop or jecxz type instruction. */
5674 if (i
.prefix
[ADDR_PREFIX
] != 0)
5676 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5679 /* Pentium4 branch hints. */
5680 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5681 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5683 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5692 if (flag_code
== CODE_16BIT
)
5695 if (i
.prefix
[DATA_PREFIX
] != 0)
5697 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5707 if (i
.prefix
[REX_PREFIX
] != 0)
5709 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5713 if (i
.prefixes
!= 0 && !intel_syntax
)
5714 as_warn (_("skipping prefixes on this instruction"));
5716 p
= frag_more (1 + size
);
5717 *p
++ = i
.tm
.base_opcode
;
5719 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5720 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5722 /* All jumps handled here are signed, but don't use a signed limit
5723 check for 32 and 16 bit jumps as we want to allow wrap around at
5724 4G and 64k respectively. */
5726 fixP
->fx_signed
= 1;
5730 output_interseg_jump (void)
5738 if (flag_code
== CODE_16BIT
)
5742 if (i
.prefix
[DATA_PREFIX
] != 0)
5748 if (i
.prefix
[REX_PREFIX
] != 0)
5758 if (i
.prefixes
!= 0 && !intel_syntax
)
5759 as_warn (_("skipping prefixes on this instruction"));
5761 /* 1 opcode; 2 segment; offset */
5762 p
= frag_more (prefix
+ 1 + 2 + size
);
5764 if (i
.prefix
[DATA_PREFIX
] != 0)
5765 *p
++ = DATA_PREFIX_OPCODE
;
5767 if (i
.prefix
[REX_PREFIX
] != 0)
5768 *p
++ = i
.prefix
[REX_PREFIX
];
5770 *p
++ = i
.tm
.base_opcode
;
5771 if (i
.op
[1].imms
->X_op
== O_constant
)
5773 offsetT n
= i
.op
[1].imms
->X_add_number
;
5776 && !fits_in_unsigned_word (n
)
5777 && !fits_in_signed_word (n
))
5779 as_bad (_("16-bit jump out of range"));
5782 md_number_to_chars (p
, n
, size
);
5785 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5786 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5787 if (i
.op
[0].imms
->X_op
!= O_constant
)
5788 as_bad (_("can't handle non absolute segment in `%s'"),
5790 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5796 fragS
*insn_start_frag
;
5797 offsetT insn_start_off
;
5799 /* Tie dwarf2 debug info to the address at the start of the insn.
5800 We can't do this after the insn has been output as the current
5801 frag may have been closed off. eg. by frag_var. */
5802 dwarf2_emit_insn (0);
5804 insn_start_frag
= frag_now
;
5805 insn_start_off
= frag_now_fix ();
5808 if (i
.tm
.opcode_modifier
.jump
)
5810 else if (i
.tm
.opcode_modifier
.jumpbyte
5811 || i
.tm
.opcode_modifier
.jumpdword
)
5813 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5814 output_interseg_jump ();
5817 /* Output normal instructions here. */
5821 unsigned int prefix
;
5823 /* Since the VEX prefix contains the implicit prefix, we don't
5824 need the explicit prefix. */
5825 if (!i
.tm
.opcode_modifier
.vex
)
5827 switch (i
.tm
.opcode_length
)
5830 if (i
.tm
.base_opcode
& 0xff000000)
5832 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5837 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5839 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5840 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5843 if (prefix
!= REPE_PREFIX_OPCODE
5844 || (i
.prefix
[REP_PREFIX
]
5845 != REPE_PREFIX_OPCODE
))
5846 add_prefix (prefix
);
5849 add_prefix (prefix
);
5858 /* The prefix bytes. */
5859 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5861 FRAG_APPEND_1_CHAR (*q
);
5864 if (i
.tm
.opcode_modifier
.vex
)
5866 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5871 /* REX byte is encoded in VEX prefix. */
5875 FRAG_APPEND_1_CHAR (*q
);
5878 /* There should be no other prefixes for instructions
5883 /* Now the VEX prefix. */
5884 p
= frag_more (i
.vex
.length
);
5885 for (j
= 0; j
< i
.vex
.length
; j
++)
5886 p
[j
] = i
.vex
.bytes
[j
];
5889 /* Now the opcode; be careful about word order here! */
5890 if (i
.tm
.opcode_length
== 1)
5892 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5896 switch (i
.tm
.opcode_length
)
5900 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5910 /* Put out high byte first: can't use md_number_to_chars! */
5911 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5912 *p
= i
.tm
.base_opcode
& 0xff;
5915 /* Now the modrm byte and sib byte (if present). */
5916 if (i
.tm
.opcode_modifier
.modrm
)
5918 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5921 /* If i.rm.regmem == ESP (4)
5922 && i.rm.mode != (Register mode)
5924 ==> need second modrm byte. */
5925 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5927 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5928 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5930 | i
.sib
.scale
<< 6));
5933 if (i
.disp_operands
)
5934 output_disp (insn_start_frag
, insn_start_off
);
5937 output_imm (insn_start_frag
, insn_start_off
);
5943 pi ("" /*line*/, &i
);
5945 #endif /* DEBUG386 */
5948 /* Return the size of the displacement operand N. */
5951 disp_size (unsigned int n
)
5954 if (i
.types
[n
].bitfield
.disp64
)
5956 else if (i
.types
[n
].bitfield
.disp8
)
5958 else if (i
.types
[n
].bitfield
.disp16
)
5963 /* Return the size of the immediate operand N. */
5966 imm_size (unsigned int n
)
5969 if (i
.types
[n
].bitfield
.imm64
)
5971 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5973 else if (i
.types
[n
].bitfield
.imm16
)
5979 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5984 for (n
= 0; n
< i
.operands
; n
++)
5986 if (operand_type_check (i
.types
[n
], disp
))
5988 if (i
.op
[n
].disps
->X_op
== O_constant
)
5990 int size
= disp_size (n
);
5993 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5995 p
= frag_more (size
);
5996 md_number_to_chars (p
, val
, size
);
6000 enum bfd_reloc_code_real reloc_type
;
6001 int size
= disp_size (n
);
6002 int sign
= i
.types
[n
].bitfield
.disp32s
;
6003 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6005 /* We can't have 8 bit displacement here. */
6006 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6008 /* The PC relative address is computed relative
6009 to the instruction boundary, so in case immediate
6010 fields follows, we need to adjust the value. */
6011 if (pcrel
&& i
.imm_operands
)
6016 for (n1
= 0; n1
< i
.operands
; n1
++)
6017 if (operand_type_check (i
.types
[n1
], imm
))
6019 /* Only one immediate is allowed for PC
6020 relative address. */
6021 gas_assert (sz
== 0);
6023 i
.op
[n
].disps
->X_add_number
-= sz
;
6025 /* We should find the immediate. */
6026 gas_assert (sz
!= 0);
6029 p
= frag_more (size
);
6030 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6032 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6033 && (((reloc_type
== BFD_RELOC_32
6034 || reloc_type
== BFD_RELOC_X86_64_32S
6035 || (reloc_type
== BFD_RELOC_64
6037 && (i
.op
[n
].disps
->X_op
== O_symbol
6038 || (i
.op
[n
].disps
->X_op
== O_add
6039 && ((symbol_get_value_expression
6040 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6042 || reloc_type
== BFD_RELOC_32_PCREL
))
6046 if (insn_start_frag
== frag_now
)
6047 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6052 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6053 for (fr
= insn_start_frag
->fr_next
;
6054 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6056 add
+= p
- frag_now
->fr_literal
;
6061 reloc_type
= BFD_RELOC_386_GOTPC
;
6062 i
.op
[n
].imms
->X_add_number
+= add
;
6064 else if (reloc_type
== BFD_RELOC_64
)
6065 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6067 /* Don't do the adjustment for x86-64, as there
6068 the pcrel addressing is relative to the _next_
6069 insn, and that is taken care of in other code. */
6070 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6072 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6073 i
.op
[n
].disps
, pcrel
, reloc_type
);
6080 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6085 for (n
= 0; n
< i
.operands
; n
++)
6087 if (operand_type_check (i
.types
[n
], imm
))
6089 if (i
.op
[n
].imms
->X_op
== O_constant
)
6091 int size
= imm_size (n
);
6094 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6096 p
= frag_more (size
);
6097 md_number_to_chars (p
, val
, size
);
6101 /* Not absolute_section.
6102 Need a 32-bit fixup (don't support 8bit
6103 non-absolute imms). Try to support other
6105 enum bfd_reloc_code_real reloc_type
;
6106 int size
= imm_size (n
);
6109 if (i
.types
[n
].bitfield
.imm32s
6110 && (i
.suffix
== QWORD_MNEM_SUFFIX
6111 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6116 p
= frag_more (size
);
6117 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6119 /* This is tough to explain. We end up with this one if we
6120 * have operands that look like
6121 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6122 * obtain the absolute address of the GOT, and it is strongly
6123 * preferable from a performance point of view to avoid using
6124 * a runtime relocation for this. The actual sequence of
6125 * instructions often look something like:
6130 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6132 * The call and pop essentially return the absolute address
6133 * of the label .L66 and store it in %ebx. The linker itself
6134 * will ultimately change the first operand of the addl so
6135 * that %ebx points to the GOT, but to keep things simple, the
6136 * .o file must have this operand set so that it generates not
6137 * the absolute address of .L66, but the absolute address of
6138 * itself. This allows the linker itself simply treat a GOTPC
6139 * relocation as asking for a pcrel offset to the GOT to be
6140 * added in, and the addend of the relocation is stored in the
6141 * operand field for the instruction itself.
6143 * Our job here is to fix the operand so that it would add
6144 * the correct offset so that %ebx would point to itself. The
6145 * thing that is tricky is that .-.L66 will point to the
6146 * beginning of the instruction, so we need to further modify
6147 * the operand so that it will point to itself. There are
6148 * other cases where you have something like:
6150 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6152 * and here no correction would be required. Internally in
6153 * the assembler we treat operands of this form as not being
6154 * pcrel since the '.' is explicitly mentioned, and I wonder
6155 * whether it would simplify matters to do it this way. Who
6156 * knows. In earlier versions of the PIC patches, the
6157 * pcrel_adjust field was used to store the correction, but
6158 * since the expression is not pcrel, I felt it would be
6159 * confusing to do it this way. */
6161 if ((reloc_type
== BFD_RELOC_32
6162 || reloc_type
== BFD_RELOC_X86_64_32S
6163 || reloc_type
== BFD_RELOC_64
)
6165 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6166 && (i
.op
[n
].imms
->X_op
== O_symbol
6167 || (i
.op
[n
].imms
->X_op
== O_add
6168 && ((symbol_get_value_expression
6169 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6174 if (insn_start_frag
== frag_now
)
6175 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6180 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6181 for (fr
= insn_start_frag
->fr_next
;
6182 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6184 add
+= p
- frag_now
->fr_literal
;
6188 reloc_type
= BFD_RELOC_386_GOTPC
;
6190 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6192 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6193 i
.op
[n
].imms
->X_add_number
+= add
;
6195 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6196 i
.op
[n
].imms
, 0, reloc_type
);
6202 /* x86_cons_fix_new is called via the expression parsing code when a
6203 reloc is needed. We use this hook to get the correct .got reloc. */
6204 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6205 static int cons_sign
= -1;
6208 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6211 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6213 got_reloc
= NO_RELOC
;
6216 if (exp
->X_op
== O_secrel
)
6218 exp
->X_op
= O_symbol
;
6219 r
= BFD_RELOC_32_SECREL
;
6223 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6226 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6227 # define lex_got(reloc, adjust, types) NULL
6229 /* Parse operands of the form
6230 <symbol>@GOTOFF+<nnn>
6231 and similar .plt or .got references.
6233 If we find one, set up the correct relocation in RELOC and copy the
6234 input string, minus the `@GOTOFF' into a malloc'd buffer for
6235 parsing by the calling routine. Return this buffer, and if ADJUST
6236 is non-null set it to the length of the string we removed from the
6237 input line. Otherwise return NULL. */
6239 lex_got (enum bfd_reloc_code_real
*rel
,
6241 i386_operand_type
*types
)
6243 /* Some of the relocations depend on the size of what field is to
6244 be relocated. But in our callers i386_immediate and i386_displacement
6245 we don't yet know the operand size (this will be set by insn
6246 matching). Hence we record the word32 relocation here,
6247 and adjust the reloc according to the real size in reloc(). */
6248 static const struct {
6250 const enum bfd_reloc_code_real rel
[2];
6251 const i386_operand_type types64
;
6253 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6254 BFD_RELOC_X86_64_PLTOFF64
},
6255 OPERAND_TYPE_IMM64
},
6256 { "PLT", { BFD_RELOC_386_PLT32
,
6257 BFD_RELOC_X86_64_PLT32
},
6258 OPERAND_TYPE_IMM32_32S_DISP32
},
6259 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6260 BFD_RELOC_X86_64_GOTPLT64
},
6261 OPERAND_TYPE_IMM64_DISP64
},
6262 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6263 BFD_RELOC_X86_64_GOTOFF64
},
6264 OPERAND_TYPE_IMM64_DISP64
},
6265 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6266 BFD_RELOC_X86_64_GOTPCREL
},
6267 OPERAND_TYPE_IMM32_32S_DISP32
},
6268 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6269 BFD_RELOC_X86_64_TLSGD
},
6270 OPERAND_TYPE_IMM32_32S_DISP32
},
6271 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6272 _dummy_first_bfd_reloc_code_real
},
6273 OPERAND_TYPE_NONE
},
6274 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6275 BFD_RELOC_X86_64_TLSLD
},
6276 OPERAND_TYPE_IMM32_32S_DISP32
},
6277 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6278 BFD_RELOC_X86_64_GOTTPOFF
},
6279 OPERAND_TYPE_IMM32_32S_DISP32
},
6280 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6281 BFD_RELOC_X86_64_TPOFF32
},
6282 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6283 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6284 _dummy_first_bfd_reloc_code_real
},
6285 OPERAND_TYPE_NONE
},
6286 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6287 BFD_RELOC_X86_64_DTPOFF32
},
6289 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6290 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6291 _dummy_first_bfd_reloc_code_real
},
6292 OPERAND_TYPE_NONE
},
6293 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6294 _dummy_first_bfd_reloc_code_real
},
6295 OPERAND_TYPE_NONE
},
6296 { "GOT", { BFD_RELOC_386_GOT32
,
6297 BFD_RELOC_X86_64_GOT32
},
6298 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6299 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6300 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6301 OPERAND_TYPE_IMM32_32S_DISP32
},
6302 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6303 BFD_RELOC_X86_64_TLSDESC_CALL
},
6304 OPERAND_TYPE_IMM32_32S_DISP32
},
6312 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6313 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6316 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6320 len
= strlen (gotrel
[j
].str
);
6321 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6323 if (gotrel
[j
].rel
[object_64bit
] != 0)
6326 char *tmpbuf
, *past_reloc
;
6328 *rel
= gotrel
[j
].rel
[object_64bit
];
6334 if (flag_code
!= CODE_64BIT
)
6336 types
->bitfield
.imm32
= 1;
6337 types
->bitfield
.disp32
= 1;
6340 *types
= gotrel
[j
].types64
;
6343 if (GOT_symbol
== NULL
)
6344 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6346 /* The length of the first part of our input line. */
6347 first
= cp
- input_line_pointer
;
6349 /* The second part goes from after the reloc token until
6350 (and including) an end_of_line char or comma. */
6351 past_reloc
= cp
+ 1 + len
;
6353 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6355 second
= cp
+ 1 - past_reloc
;
6357 /* Allocate and copy string. The trailing NUL shouldn't
6358 be necessary, but be safe. */
6359 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6360 memcpy (tmpbuf
, input_line_pointer
, first
);
6361 if (second
!= 0 && *past_reloc
!= ' ')
6362 /* Replace the relocation token with ' ', so that
6363 errors like foo@GOTOFF1 will be detected. */
6364 tmpbuf
[first
++] = ' ';
6365 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6366 tmpbuf
[first
+ second
] = '\0';
6370 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6371 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6376 /* Might be a symbol version string. Don't as_bad here. */
6381 x86_cons (expressionS
*exp
, int size
)
6383 intel_syntax
= -intel_syntax
;
6385 if (size
== 4 || (object_64bit
&& size
== 8))
6387 /* Handle @GOTOFF and the like in an expression. */
6389 char *gotfree_input_line
;
6392 save
= input_line_pointer
;
6393 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6394 if (gotfree_input_line
)
6395 input_line_pointer
= gotfree_input_line
;
6399 if (gotfree_input_line
)
6401 /* expression () has merrily parsed up to the end of line,
6402 or a comma - in the wrong buffer. Transfer how far
6403 input_line_pointer has moved to the right buffer. */
6404 input_line_pointer
= (save
6405 + (input_line_pointer
- gotfree_input_line
)
6407 free (gotfree_input_line
);
6408 if (exp
->X_op
== O_constant
6409 || exp
->X_op
== O_absent
6410 || exp
->X_op
== O_illegal
6411 || exp
->X_op
== O_register
6412 || exp
->X_op
== O_big
)
6414 char c
= *input_line_pointer
;
6415 *input_line_pointer
= 0;
6416 as_bad (_("missing or invalid expression `%s'"), save
);
6417 *input_line_pointer
= c
;
6424 intel_syntax
= -intel_syntax
;
6427 i386_intel_simplify (exp
);
6432 signed_cons (int size
)
6434 if (flag_code
== CODE_64BIT
)
6442 pe_directive_secrel (dummy
)
6443 int dummy ATTRIBUTE_UNUSED
;
6450 if (exp
.X_op
== O_symbol
)
6451 exp
.X_op
= O_secrel
;
6453 emit_expr (&exp
, 4);
6455 while (*input_line_pointer
++ == ',');
6457 input_line_pointer
--;
6458 demand_empty_rest_of_line ();
6463 i386_immediate (char *imm_start
)
6465 char *save_input_line_pointer
;
6466 char *gotfree_input_line
;
6469 i386_operand_type types
;
6471 operand_type_set (&types
, ~0);
6473 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6475 as_bad (_("at most %d immediate operands are allowed"),
6476 MAX_IMMEDIATE_OPERANDS
);
6480 exp
= &im_expressions
[i
.imm_operands
++];
6481 i
.op
[this_operand
].imms
= exp
;
6483 if (is_space_char (*imm_start
))
6486 save_input_line_pointer
= input_line_pointer
;
6487 input_line_pointer
= imm_start
;
6489 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6490 if (gotfree_input_line
)
6491 input_line_pointer
= gotfree_input_line
;
6493 exp_seg
= expression (exp
);
6496 if (*input_line_pointer
)
6497 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6499 input_line_pointer
= save_input_line_pointer
;
6500 if (gotfree_input_line
)
6502 free (gotfree_input_line
);
6504 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6505 exp
->X_op
= O_illegal
;
6508 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6512 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6513 i386_operand_type types
, const char *imm_start
)
6515 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6518 as_bad (_("missing or invalid immediate expression `%s'"),
6522 else if (exp
->X_op
== O_constant
)
6524 /* Size it properly later. */
6525 i
.types
[this_operand
].bitfield
.imm64
= 1;
6526 /* If BFD64, sign extend val. */
6527 if (!use_rela_relocations
6528 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6530 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6532 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6533 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6534 && exp_seg
!= absolute_section
6535 && exp_seg
!= text_section
6536 && exp_seg
!= data_section
6537 && exp_seg
!= bss_section
6538 && exp_seg
!= undefined_section
6539 && !bfd_is_com_section (exp_seg
))
6541 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6545 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6548 as_bad (_("illegal immediate register operand %s"), imm_start
);
6553 /* This is an address. The size of the address will be
6554 determined later, depending on destination register,
6555 suffix, or the default for the section. */
6556 i
.types
[this_operand
].bitfield
.imm8
= 1;
6557 i
.types
[this_operand
].bitfield
.imm16
= 1;
6558 i
.types
[this_operand
].bitfield
.imm32
= 1;
6559 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6560 i
.types
[this_operand
].bitfield
.imm64
= 1;
6561 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6569 i386_scale (char *scale
)
6572 char *save
= input_line_pointer
;
6574 input_line_pointer
= scale
;
6575 val
= get_absolute_expression ();
6580 i
.log2_scale_factor
= 0;
6583 i
.log2_scale_factor
= 1;
6586 i
.log2_scale_factor
= 2;
6589 i
.log2_scale_factor
= 3;
6593 char sep
= *input_line_pointer
;
6595 *input_line_pointer
= '\0';
6596 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6598 *input_line_pointer
= sep
;
6599 input_line_pointer
= save
;
6603 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6605 as_warn (_("scale factor of %d without an index register"),
6606 1 << i
.log2_scale_factor
);
6607 i
.log2_scale_factor
= 0;
6609 scale
= input_line_pointer
;
6610 input_line_pointer
= save
;
6615 i386_displacement (char *disp_start
, char *disp_end
)
6619 char *save_input_line_pointer
;
6620 char *gotfree_input_line
;
6622 i386_operand_type bigdisp
, types
= anydisp
;
6625 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6627 as_bad (_("at most %d displacement operands are allowed"),
6628 MAX_MEMORY_OPERANDS
);
6632 operand_type_set (&bigdisp
, 0);
6633 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6634 || (!current_templates
->start
->opcode_modifier
.jump
6635 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6637 bigdisp
.bitfield
.disp32
= 1;
6638 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6639 if (flag_code
== CODE_64BIT
)
6643 bigdisp
.bitfield
.disp32s
= 1;
6644 bigdisp
.bitfield
.disp64
= 1;
6647 else if ((flag_code
== CODE_16BIT
) ^ override
)
6649 bigdisp
.bitfield
.disp32
= 0;
6650 bigdisp
.bitfield
.disp16
= 1;
6655 /* For PC-relative branches, the width of the displacement
6656 is dependent upon data size, not address size. */
6657 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6658 if (flag_code
== CODE_64BIT
)
6660 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6661 bigdisp
.bitfield
.disp16
= 1;
6664 bigdisp
.bitfield
.disp32
= 1;
6665 bigdisp
.bitfield
.disp32s
= 1;
6671 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6673 : LONG_MNEM_SUFFIX
));
6674 bigdisp
.bitfield
.disp32
= 1;
6675 if ((flag_code
== CODE_16BIT
) ^ override
)
6677 bigdisp
.bitfield
.disp32
= 0;
6678 bigdisp
.bitfield
.disp16
= 1;
6682 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6685 exp
= &disp_expressions
[i
.disp_operands
];
6686 i
.op
[this_operand
].disps
= exp
;
6688 save_input_line_pointer
= input_line_pointer
;
6689 input_line_pointer
= disp_start
;
6690 END_STRING_AND_SAVE (disp_end
);
6692 #ifndef GCC_ASM_O_HACK
6693 #define GCC_ASM_O_HACK 0
6696 END_STRING_AND_SAVE (disp_end
+ 1);
6697 if (i
.types
[this_operand
].bitfield
.baseIndex
6698 && displacement_string_end
[-1] == '+')
6700 /* This hack is to avoid a warning when using the "o"
6701 constraint within gcc asm statements.
6704 #define _set_tssldt_desc(n,addr,limit,type) \
6705 __asm__ __volatile__ ( \
6707 "movw %w1,2+%0\n\t" \
6709 "movb %b1,4+%0\n\t" \
6710 "movb %4,5+%0\n\t" \
6711 "movb $0,6+%0\n\t" \
6712 "movb %h1,7+%0\n\t" \
6714 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6716 This works great except that the output assembler ends
6717 up looking a bit weird if it turns out that there is
6718 no offset. You end up producing code that looks like:
6731 So here we provide the missing zero. */
6733 *displacement_string_end
= '0';
6736 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6737 if (gotfree_input_line
)
6738 input_line_pointer
= gotfree_input_line
;
6740 exp_seg
= expression (exp
);
6743 if (*input_line_pointer
)
6744 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6746 RESTORE_END_STRING (disp_end
+ 1);
6748 input_line_pointer
= save_input_line_pointer
;
6749 if (gotfree_input_line
)
6751 free (gotfree_input_line
);
6753 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6754 exp
->X_op
= O_illegal
;
6757 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6759 RESTORE_END_STRING (disp_end
);
6765 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6766 i386_operand_type types
, const char *disp_start
)
6768 i386_operand_type bigdisp
;
6771 /* We do this to make sure that the section symbol is in
6772 the symbol table. We will ultimately change the relocation
6773 to be relative to the beginning of the section. */
6774 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6775 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6776 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6778 if (exp
->X_op
!= O_symbol
)
6781 if (S_IS_LOCAL (exp
->X_add_symbol
)
6782 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6783 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6784 exp
->X_op
= O_subtract
;
6785 exp
->X_op_symbol
= GOT_symbol
;
6786 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6787 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6788 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6789 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6791 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6794 else if (exp
->X_op
== O_absent
6795 || exp
->X_op
== O_illegal
6796 || exp
->X_op
== O_big
)
6799 as_bad (_("missing or invalid displacement expression `%s'"),
6804 else if (flag_code
== CODE_64BIT
6805 && !i
.prefix
[ADDR_PREFIX
]
6806 && exp
->X_op
== O_constant
)
6808 /* Since displacement is signed extended to 64bit, don't allow
6809 disp32 and turn off disp32s if they are out of range. */
6810 i
.types
[this_operand
].bitfield
.disp32
= 0;
6811 if (!fits_in_signed_long (exp
->X_add_number
))
6813 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6814 if (i
.types
[this_operand
].bitfield
.baseindex
)
6816 as_bad (_("0x%lx out range of signed 32bit displacement"),
6817 (long) exp
->X_add_number
);
6823 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6824 else if (exp
->X_op
!= O_constant
6825 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6826 && exp_seg
!= absolute_section
6827 && exp_seg
!= text_section
6828 && exp_seg
!= data_section
6829 && exp_seg
!= bss_section
6830 && exp_seg
!= undefined_section
6831 && !bfd_is_com_section (exp_seg
))
6833 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6838 /* Check if this is a displacement only operand. */
6839 bigdisp
= i
.types
[this_operand
];
6840 bigdisp
.bitfield
.disp8
= 0;
6841 bigdisp
.bitfield
.disp16
= 0;
6842 bigdisp
.bitfield
.disp32
= 0;
6843 bigdisp
.bitfield
.disp32s
= 0;
6844 bigdisp
.bitfield
.disp64
= 0;
6845 if (operand_type_all_zero (&bigdisp
))
6846 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6852 /* Make sure the memory operand we've been dealt is valid.
6853 Return 1 on success, 0 on a failure. */
6856 i386_index_check (const char *operand_string
)
6859 const char *kind
= "base/index";
6860 #if INFER_ADDR_PREFIX
6866 if (current_templates
->start
->opcode_modifier
.isstring
6867 && !current_templates
->start
->opcode_modifier
.immext
6868 && (current_templates
->end
[-1].opcode_modifier
.isstring
6871 /* Memory operands of string insns are special in that they only allow
6872 a single register (rDI, rSI, or rBX) as their memory address. */
6873 unsigned int expected
;
6875 kind
= "string address";
6877 if (current_templates
->start
->opcode_modifier
.w
)
6879 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6881 if (!type
.bitfield
.baseindex
6882 || ((!i
.mem_operands
!= !intel_syntax
)
6883 && current_templates
->end
[-1].operand_types
[1]
6884 .bitfield
.baseindex
))
6885 type
= current_templates
->end
[-1].operand_types
[1];
6886 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6889 expected
= 3 /* rBX */;
6891 if (!i
.base_reg
|| i
.index_reg
6892 || operand_type_check (i
.types
[this_operand
], disp
))
6894 else if (!(flag_code
== CODE_64BIT
6895 ? i
.prefix
[ADDR_PREFIX
]
6896 ? i
.base_reg
->reg_type
.bitfield
.reg32
6897 : i
.base_reg
->reg_type
.bitfield
.reg64
6898 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6899 ? i
.base_reg
->reg_type
.bitfield
.reg32
6900 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6902 else if (i
.base_reg
->reg_num
!= expected
)
6909 for (j
= 0; j
< i386_regtab_size
; ++j
)
6910 if ((flag_code
== CODE_64BIT
6911 ? i
.prefix
[ADDR_PREFIX
]
6912 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6913 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6914 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6915 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6916 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6917 && i386_regtab
[j
].reg_num
== expected
)
6919 gas_assert (j
< i386_regtab_size
);
6920 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6922 intel_syntax
? '[' : '(',
6924 i386_regtab
[j
].reg_name
,
6925 intel_syntax
? ']' : ')');
6929 else if (flag_code
== CODE_64BIT
)
6932 && ((i
.prefix
[ADDR_PREFIX
] == 0
6933 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6934 || (i
.prefix
[ADDR_PREFIX
]
6935 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6937 || i
.base_reg
->reg_num
!=
6938 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6940 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6941 || (i
.prefix
[ADDR_PREFIX
] == 0
6942 && i
.index_reg
->reg_num
!= RegRiz
6943 && !i
.index_reg
->reg_type
.bitfield
.reg64
6945 || (i
.prefix
[ADDR_PREFIX
]
6946 && i
.index_reg
->reg_num
!= RegEiz
6947 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6952 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6956 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6957 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6959 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6960 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6962 && i
.base_reg
->reg_num
< 6
6963 && i
.index_reg
->reg_num
>= 6
6964 && i
.log2_scale_factor
== 0))))
6971 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6973 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6974 && i
.index_reg
->reg_num
!= RegEiz
)
6975 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6981 #if INFER_ADDR_PREFIX
6982 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6984 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6986 /* Change the size of any displacement too. At most one of
6987 Disp16 or Disp32 is set.
6988 FIXME. There doesn't seem to be any real need for separate
6989 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6990 Removing them would probably clean up the code quite a lot. */
6991 if (flag_code
!= CODE_64BIT
6992 && (i
.types
[this_operand
].bitfield
.disp16
6993 || i
.types
[this_operand
].bitfield
.disp32
))
6994 i
.types
[this_operand
]
6995 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7000 as_bad (_("`%s' is not a valid %s expression"),
7005 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7007 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7008 ? flag_code
== CODE_32BIT
7017 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7021 i386_att_operand (char *operand_string
)
7025 char *op_string
= operand_string
;
7027 if (is_space_char (*op_string
))
7030 /* We check for an absolute prefix (differentiating,
7031 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7032 if (*op_string
== ABSOLUTE_PREFIX
)
7035 if (is_space_char (*op_string
))
7037 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7040 /* Check if operand is a register. */
7041 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7043 i386_operand_type temp
;
7045 /* Check for a segment override by searching for ':' after a
7046 segment register. */
7048 if (is_space_char (*op_string
))
7050 if (*op_string
== ':'
7051 && (r
->reg_type
.bitfield
.sreg2
7052 || r
->reg_type
.bitfield
.sreg3
))
7057 i
.seg
[i
.mem_operands
] = &es
;
7060 i
.seg
[i
.mem_operands
] = &cs
;
7063 i
.seg
[i
.mem_operands
] = &ss
;
7066 i
.seg
[i
.mem_operands
] = &ds
;
7069 i
.seg
[i
.mem_operands
] = &fs
;
7072 i
.seg
[i
.mem_operands
] = &gs
;
7076 /* Skip the ':' and whitespace. */
7078 if (is_space_char (*op_string
))
7081 if (!is_digit_char (*op_string
)
7082 && !is_identifier_char (*op_string
)
7083 && *op_string
!= '('
7084 && *op_string
!= ABSOLUTE_PREFIX
)
7086 as_bad (_("bad memory operand `%s'"), op_string
);
7089 /* Handle case of %es:*foo. */
7090 if (*op_string
== ABSOLUTE_PREFIX
)
7093 if (is_space_char (*op_string
))
7095 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7097 goto do_memory_reference
;
7101 as_bad (_("junk `%s' after register"), op_string
);
7105 temp
.bitfield
.baseindex
= 0;
7106 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7108 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7109 i
.op
[this_operand
].regs
= r
;
7112 else if (*op_string
== REGISTER_PREFIX
)
7114 as_bad (_("bad register name `%s'"), op_string
);
7117 else if (*op_string
== IMMEDIATE_PREFIX
)
7120 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7122 as_bad (_("immediate operand illegal with absolute jump"));
7125 if (!i386_immediate (op_string
))
7128 else if (is_digit_char (*op_string
)
7129 || is_identifier_char (*op_string
)
7130 || *op_string
== '(')
7132 /* This is a memory reference of some sort. */
7135 /* Start and end of displacement string expression (if found). */
7136 char *displacement_string_start
;
7137 char *displacement_string_end
;
7139 do_memory_reference
:
7140 if ((i
.mem_operands
== 1
7141 && !current_templates
->start
->opcode_modifier
.isstring
)
7142 || i
.mem_operands
== 2)
7144 as_bad (_("too many memory references for `%s'"),
7145 current_templates
->start
->name
);
7149 /* Check for base index form. We detect the base index form by
7150 looking for an ')' at the end of the operand, searching
7151 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7153 base_string
= op_string
+ strlen (op_string
);
7156 if (is_space_char (*base_string
))
7159 /* If we only have a displacement, set-up for it to be parsed later. */
7160 displacement_string_start
= op_string
;
7161 displacement_string_end
= base_string
+ 1;
7163 if (*base_string
== ')')
7166 unsigned int parens_balanced
= 1;
7167 /* We've already checked that the number of left & right ()'s are
7168 equal, so this loop will not be infinite. */
7172 if (*base_string
== ')')
7174 if (*base_string
== '(')
7177 while (parens_balanced
);
7179 temp_string
= base_string
;
7181 /* Skip past '(' and whitespace. */
7183 if (is_space_char (*base_string
))
7186 if (*base_string
== ','
7187 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7190 displacement_string_end
= temp_string
;
7192 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7196 base_string
= end_op
;
7197 if (is_space_char (*base_string
))
7201 /* There may be an index reg or scale factor here. */
7202 if (*base_string
== ',')
7205 if (is_space_char (*base_string
))
7208 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7211 base_string
= end_op
;
7212 if (is_space_char (*base_string
))
7214 if (*base_string
== ',')
7217 if (is_space_char (*base_string
))
7220 else if (*base_string
!= ')')
7222 as_bad (_("expecting `,' or `)' "
7223 "after index register in `%s'"),
7228 else if (*base_string
== REGISTER_PREFIX
)
7230 as_bad (_("bad register name `%s'"), base_string
);
7234 /* Check for scale factor. */
7235 if (*base_string
!= ')')
7237 char *end_scale
= i386_scale (base_string
);
7242 base_string
= end_scale
;
7243 if (is_space_char (*base_string
))
7245 if (*base_string
!= ')')
7247 as_bad (_("expecting `)' "
7248 "after scale factor in `%s'"),
7253 else if (!i
.index_reg
)
7255 as_bad (_("expecting index register or scale factor "
7256 "after `,'; got '%c'"),
7261 else if (*base_string
!= ')')
7263 as_bad (_("expecting `,' or `)' "
7264 "after base register in `%s'"),
7269 else if (*base_string
== REGISTER_PREFIX
)
7271 as_bad (_("bad register name `%s'"), base_string
);
7276 /* If there's an expression beginning the operand, parse it,
7277 assuming displacement_string_start and
7278 displacement_string_end are meaningful. */
7279 if (displacement_string_start
!= displacement_string_end
)
7281 if (!i386_displacement (displacement_string_start
,
7282 displacement_string_end
))
7286 /* Special case for (%dx) while doing input/output op. */
7288 && operand_type_equal (&i
.base_reg
->reg_type
,
7289 ®16_inoutportreg
)
7291 && i
.log2_scale_factor
== 0
7292 && i
.seg
[i
.mem_operands
] == 0
7293 && !operand_type_check (i
.types
[this_operand
], disp
))
7295 i
.types
[this_operand
] = inoutportreg
;
7299 if (i386_index_check (operand_string
) == 0)
7301 i
.types
[this_operand
].bitfield
.mem
= 1;
7306 /* It's not a memory operand; argh! */
7307 as_bad (_("invalid char %s beginning operand %d `%s'"),
7308 output_invalid (*op_string
),
7313 return 1; /* Normal return. */
7316 /* md_estimate_size_before_relax()
7318 Called just before relax() for rs_machine_dependent frags. The x86
7319 assembler uses these frags to handle variable size jump
7322 Any symbol that is now undefined will not become defined.
7323 Return the correct fr_subtype in the frag.
7324 Return the initial "guess for variable size of frag" to caller.
7325 The guess is actually the growth beyond the fixed part. Whatever
7326 we do to grow the fixed or variable part contributes to our
7330 md_estimate_size_before_relax (fragP
, segment
)
7334 /* We've already got fragP->fr_subtype right; all we have to do is
7335 check for un-relaxable symbols. On an ELF system, we can't relax
7336 an externally visible symbol, because it may be overridden by a
7338 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7339 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7341 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7342 || S_IS_WEAK (fragP
->fr_symbol
)
7343 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7344 & BSF_GNU_INDIRECT_FUNCTION
))))
7346 #if defined (OBJ_COFF) && defined (TE_PE)
7347 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7348 && S_IS_WEAK (fragP
->fr_symbol
))
7352 /* Symbol is undefined in this segment, or we need to keep a
7353 reloc so that weak symbols can be overridden. */
7354 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7355 enum bfd_reloc_code_real reloc_type
;
7356 unsigned char *opcode
;
7359 if (fragP
->fr_var
!= NO_RELOC
)
7360 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7362 reloc_type
= BFD_RELOC_16_PCREL
;
7364 reloc_type
= BFD_RELOC_32_PCREL
;
7366 old_fr_fix
= fragP
->fr_fix
;
7367 opcode
= (unsigned char *) fragP
->fr_opcode
;
7369 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7372 /* Make jmp (0xeb) a (d)word displacement jump. */
7374 fragP
->fr_fix
+= size
;
7375 fix_new (fragP
, old_fr_fix
, size
,
7377 fragP
->fr_offset
, 1,
7383 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7385 /* Negate the condition, and branch past an
7386 unconditional jump. */
7389 /* Insert an unconditional jump. */
7391 /* We added two extra opcode bytes, and have a two byte
7393 fragP
->fr_fix
+= 2 + 2;
7394 fix_new (fragP
, old_fr_fix
+ 2, 2,
7396 fragP
->fr_offset
, 1,
7403 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7408 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7410 fragP
->fr_offset
, 1,
7412 fixP
->fx_signed
= 1;
7416 /* This changes the byte-displacement jump 0x7N
7417 to the (d)word-displacement jump 0x0f,0x8N. */
7418 opcode
[1] = opcode
[0] + 0x10;
7419 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7420 /* We've added an opcode byte. */
7421 fragP
->fr_fix
+= 1 + size
;
7422 fix_new (fragP
, old_fr_fix
+ 1, size
,
7424 fragP
->fr_offset
, 1,
7429 BAD_CASE (fragP
->fr_subtype
);
7433 return fragP
->fr_fix
- old_fr_fix
;
7436 /* Guess size depending on current relax state. Initially the relax
7437 state will correspond to a short jump and we return 1, because
7438 the variable part of the frag (the branch offset) is one byte
7439 long. However, we can relax a section more than once and in that
7440 case we must either set fr_subtype back to the unrelaxed state,
7441 or return the value for the appropriate branch. */
7442 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7445 /* Called after relax() is finished.
7447 In: Address of frag.
7448 fr_type == rs_machine_dependent.
7449 fr_subtype is what the address relaxed to.
7451 Out: Any fixSs and constants are set up.
7452 Caller will turn frag into a ".space 0". */
7455 md_convert_frag (abfd
, sec
, fragP
)
7456 bfd
*abfd ATTRIBUTE_UNUSED
;
7457 segT sec ATTRIBUTE_UNUSED
;
7460 unsigned char *opcode
;
7461 unsigned char *where_to_put_displacement
= NULL
;
7462 offsetT target_address
;
7463 offsetT opcode_address
;
7464 unsigned int extension
= 0;
7465 offsetT displacement_from_opcode_start
;
7467 opcode
= (unsigned char *) fragP
->fr_opcode
;
7469 /* Address we want to reach in file space. */
7470 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7472 /* Address opcode resides at in file space. */
7473 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7475 /* Displacement from opcode start to fill into instruction. */
7476 displacement_from_opcode_start
= target_address
- opcode_address
;
7478 if ((fragP
->fr_subtype
& BIG
) == 0)
7480 /* Don't have to change opcode. */
7481 extension
= 1; /* 1 opcode + 1 displacement */
7482 where_to_put_displacement
= &opcode
[1];
7486 if (no_cond_jump_promotion
7487 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7488 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7489 _("long jump required"));
7491 switch (fragP
->fr_subtype
)
7493 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7494 extension
= 4; /* 1 opcode + 4 displacement */
7496 where_to_put_displacement
= &opcode
[1];
7499 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7500 extension
= 2; /* 1 opcode + 2 displacement */
7502 where_to_put_displacement
= &opcode
[1];
7505 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7506 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7507 extension
= 5; /* 2 opcode + 4 displacement */
7508 opcode
[1] = opcode
[0] + 0x10;
7509 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7510 where_to_put_displacement
= &opcode
[2];
7513 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7514 extension
= 3; /* 2 opcode + 2 displacement */
7515 opcode
[1] = opcode
[0] + 0x10;
7516 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7517 where_to_put_displacement
= &opcode
[2];
7520 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7525 where_to_put_displacement
= &opcode
[3];
7529 BAD_CASE (fragP
->fr_subtype
);
7534 /* If size if less then four we are sure that the operand fits,
7535 but if it's 4, then it could be that the displacement is larger
7537 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7539 && ((addressT
) (displacement_from_opcode_start
- extension
7540 + ((addressT
) 1 << 31))
7541 > (((addressT
) 2 << 31) - 1)))
7543 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7544 _("jump target out of range"));
7545 /* Make us emit 0. */
7546 displacement_from_opcode_start
= extension
;
7548 /* Now put displacement after opcode. */
7549 md_number_to_chars ((char *) where_to_put_displacement
,
7550 (valueT
) (displacement_from_opcode_start
- extension
),
7551 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7552 fragP
->fr_fix
+= extension
;
7555 /* Apply a fixup (fixS) to segment data, once it has been determined
7556 by our caller that we have all the info we need to fix it up.
7558 On the 386, immediates, displacements, and data pointers are all in
7559 the same (little-endian) format, so we don't need to care about which
7563 md_apply_fix (fixP
, valP
, seg
)
7564 /* The fix we're to put in. */
7566 /* Pointer to the value of the bits. */
7568 /* Segment fix is from. */
7569 segT seg ATTRIBUTE_UNUSED
;
7571 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7572 valueT value
= *valP
;
7574 #if !defined (TE_Mach)
7577 switch (fixP
->fx_r_type
)
7583 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7586 case BFD_RELOC_X86_64_32S
:
7587 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7590 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7593 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7598 if (fixP
->fx_addsy
!= NULL
7599 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7600 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7601 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7602 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7603 && !use_rela_relocations
)
7605 /* This is a hack. There should be a better way to handle this.
7606 This covers for the fact that bfd_install_relocation will
7607 subtract the current location (for partial_inplace, PC relative
7608 relocations); see more below. */
7612 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7615 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7617 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7620 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7623 || (symbol_section_p (fixP
->fx_addsy
)
7624 && sym_seg
!= absolute_section
))
7625 && !generic_force_reloc (fixP
))
7627 /* Yes, we add the values in twice. This is because
7628 bfd_install_relocation subtracts them out again. I think
7629 bfd_install_relocation is broken, but I don't dare change
7631 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7635 #if defined (OBJ_COFF) && defined (TE_PE)
7636 /* For some reason, the PE format does not store a
7637 section address offset for a PC relative symbol. */
7638 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7639 || S_IS_WEAK (fixP
->fx_addsy
))
7640 value
+= md_pcrel_from (fixP
);
7643 #if defined (OBJ_COFF) && defined (TE_PE)
7644 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7646 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7650 /* Fix a few things - the dynamic linker expects certain values here,
7651 and we must not disappoint it. */
7652 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7653 if (IS_ELF
&& fixP
->fx_addsy
)
7654 switch (fixP
->fx_r_type
)
7656 case BFD_RELOC_386_PLT32
:
7657 case BFD_RELOC_X86_64_PLT32
:
7658 /* Make the jump instruction point to the address of the operand. At
7659 runtime we merely add the offset to the actual PLT entry. */
7663 case BFD_RELOC_386_TLS_GD
:
7664 case BFD_RELOC_386_TLS_LDM
:
7665 case BFD_RELOC_386_TLS_IE_32
:
7666 case BFD_RELOC_386_TLS_IE
:
7667 case BFD_RELOC_386_TLS_GOTIE
:
7668 case BFD_RELOC_386_TLS_GOTDESC
:
7669 case BFD_RELOC_X86_64_TLSGD
:
7670 case BFD_RELOC_X86_64_TLSLD
:
7671 case BFD_RELOC_X86_64_GOTTPOFF
:
7672 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7673 value
= 0; /* Fully resolved at runtime. No addend. */
7675 case BFD_RELOC_386_TLS_LE
:
7676 case BFD_RELOC_386_TLS_LDO_32
:
7677 case BFD_RELOC_386_TLS_LE_32
:
7678 case BFD_RELOC_X86_64_DTPOFF32
:
7679 case BFD_RELOC_X86_64_DTPOFF64
:
7680 case BFD_RELOC_X86_64_TPOFF32
:
7681 case BFD_RELOC_X86_64_TPOFF64
:
7682 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7685 case BFD_RELOC_386_TLS_DESC_CALL
:
7686 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7687 value
= 0; /* Fully resolved at runtime. No addend. */
7688 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7692 case BFD_RELOC_386_GOT32
:
7693 case BFD_RELOC_X86_64_GOT32
:
7694 value
= 0; /* Fully resolved at runtime. No addend. */
7697 case BFD_RELOC_VTABLE_INHERIT
:
7698 case BFD_RELOC_VTABLE_ENTRY
:
7705 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7707 #endif /* !defined (TE_Mach) */
7709 /* Are we finished with this relocation now? */
7710 if (fixP
->fx_addsy
== NULL
)
7712 #if defined (OBJ_COFF) && defined (TE_PE)
7713 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7716 /* Remember value for tc_gen_reloc. */
7717 fixP
->fx_addnumber
= value
;
7718 /* Clear out the frag for now. */
7722 else if (use_rela_relocations
)
7724 fixP
->fx_no_overflow
= 1;
7725 /* Remember value for tc_gen_reloc. */
7726 fixP
->fx_addnumber
= value
;
7730 md_number_to_chars (p
, value
, fixP
->fx_size
);
7734 md_atof (int type
, char *litP
, int *sizeP
)
7736 /* This outputs the LITTLENUMs in REVERSE order;
7737 in accord with the bigendian 386. */
7738 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7741 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7744 output_invalid (int c
)
7747 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7750 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7751 "(0x%x)", (unsigned char) c
);
7752 return output_invalid_buf
;
7755 /* REG_STRING starts *before* REGISTER_PREFIX. */
7757 static const reg_entry
*
7758 parse_real_register (char *reg_string
, char **end_op
)
7760 char *s
= reg_string
;
7762 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7765 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7766 if (*s
== REGISTER_PREFIX
)
7769 if (is_space_char (*s
))
7773 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7775 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7776 return (const reg_entry
*) NULL
;
7780 /* For naked regs, make sure that we are not dealing with an identifier.
7781 This prevents confusing an identifier like `eax_var' with register
7783 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7784 return (const reg_entry
*) NULL
;
7788 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7790 /* Handle floating point regs, allowing spaces in the (i) part. */
7791 if (r
== i386_regtab
/* %st is first entry of table */)
7793 if (is_space_char (*s
))
7798 if (is_space_char (*s
))
7800 if (*s
>= '0' && *s
<= '7')
7804 if (is_space_char (*s
))
7809 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7814 /* We have "%st(" then garbage. */
7815 return (const reg_entry
*) NULL
;
7819 if (r
== NULL
|| allow_pseudo_reg
)
7822 if (operand_type_all_zero (&r
->reg_type
))
7823 return (const reg_entry
*) NULL
;
7825 if ((r
->reg_type
.bitfield
.reg32
7826 || r
->reg_type
.bitfield
.sreg3
7827 || r
->reg_type
.bitfield
.control
7828 || r
->reg_type
.bitfield
.debug
7829 || r
->reg_type
.bitfield
.test
)
7830 && !cpu_arch_flags
.bitfield
.cpui386
)
7831 return (const reg_entry
*) NULL
;
7833 if (r
->reg_type
.bitfield
.floatreg
7834 && !cpu_arch_flags
.bitfield
.cpu8087
7835 && !cpu_arch_flags
.bitfield
.cpu287
7836 && !cpu_arch_flags
.bitfield
.cpu387
)
7837 return (const reg_entry
*) NULL
;
7839 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7840 return (const reg_entry
*) NULL
;
7842 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7843 return (const reg_entry
*) NULL
;
7845 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7846 return (const reg_entry
*) NULL
;
7848 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7849 if (!allow_index_reg
7850 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7851 return (const reg_entry
*) NULL
;
7853 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7854 || r
->reg_type
.bitfield
.reg64
)
7855 && (!cpu_arch_flags
.bitfield
.cpulm
7856 || !operand_type_equal (&r
->reg_type
, &control
))
7857 && flag_code
!= CODE_64BIT
)
7858 return (const reg_entry
*) NULL
;
7860 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7861 return (const reg_entry
*) NULL
;
7866 /* REG_STRING starts *before* REGISTER_PREFIX. */
7868 static const reg_entry
*
7869 parse_register (char *reg_string
, char **end_op
)
7873 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7874 r
= parse_real_register (reg_string
, end_op
);
7879 char *save
= input_line_pointer
;
7883 input_line_pointer
= reg_string
;
7884 c
= get_symbol_end ();
7885 symbolP
= symbol_find (reg_string
);
7886 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7888 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7890 know (e
->X_op
== O_register
);
7891 know (e
->X_add_number
>= 0
7892 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7893 r
= i386_regtab
+ e
->X_add_number
;
7894 *end_op
= input_line_pointer
;
7896 *input_line_pointer
= c
;
7897 input_line_pointer
= save
;
7903 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7906 char *end
= input_line_pointer
;
7909 r
= parse_register (name
, &input_line_pointer
);
7910 if (r
&& end
<= input_line_pointer
)
7912 *nextcharP
= *input_line_pointer
;
7913 *input_line_pointer
= 0;
7914 e
->X_op
= O_register
;
7915 e
->X_add_number
= r
- i386_regtab
;
7918 input_line_pointer
= end
;
7920 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7924 md_operand (expressionS
*e
)
7929 switch (*input_line_pointer
)
7931 case REGISTER_PREFIX
:
7932 r
= parse_real_register (input_line_pointer
, &end
);
7935 e
->X_op
= O_register
;
7936 e
->X_add_number
= r
- i386_regtab
;
7937 input_line_pointer
= end
;
7942 gas_assert (intel_syntax
);
7943 end
= input_line_pointer
++;
7945 if (*input_line_pointer
== ']')
7947 ++input_line_pointer
;
7948 e
->X_op_symbol
= make_expr_symbol (e
);
7949 e
->X_add_symbol
= NULL
;
7950 e
->X_add_number
= 0;
7956 input_line_pointer
= end
;
7963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7964 const char *md_shortopts
= "kVQ:sqn";
7966 const char *md_shortopts
= "qn";
7969 #define OPTION_32 (OPTION_MD_BASE + 0)
7970 #define OPTION_64 (OPTION_MD_BASE + 1)
7971 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7972 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7973 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7974 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7975 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7976 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7977 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7978 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7979 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7980 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7981 #define OPTION_MAVXSCALAR (OPTION_MSSE_CHECK + 11)
7983 struct option md_longopts
[] =
7985 {"32", no_argument
, NULL
, OPTION_32
},
7986 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7987 || defined (TE_PE) || defined (TE_PEP))
7988 {"64", no_argument
, NULL
, OPTION_64
},
7990 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7991 {"march", required_argument
, NULL
, OPTION_MARCH
},
7992 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7993 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7994 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7995 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7996 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7997 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7998 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7999 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8000 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8001 {NULL
, no_argument
, NULL
, 0}
8003 size_t md_longopts_size
= sizeof (md_longopts
);
8006 md_parse_option (int c
, char *arg
)
8014 optimize_align_code
= 0;
8021 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8022 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8023 should be emitted or not. FIXME: Not implemented. */
8027 /* -V: SVR4 argument to print version ID. */
8029 print_version_id ();
8032 /* -k: Ignore for FreeBSD compatibility. */
8037 /* -s: On i386 Solaris, this tells the native assembler to use
8038 .stab instead of .stab.excl. We always use .stab anyhow. */
8041 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8042 || defined (TE_PE) || defined (TE_PEP))
8045 const char **list
, **l
;
8047 list
= bfd_target_list ();
8048 for (l
= list
; *l
!= NULL
; l
++)
8049 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8050 || strcmp (*l
, "coff-x86-64") == 0
8051 || strcmp (*l
, "pe-x86-64") == 0
8052 || strcmp (*l
, "pei-x86-64") == 0)
8054 default_arch
= "x86_64";
8058 as_fatal (_("No compiled in support for x86_64"));
8065 default_arch
= "i386";
8069 #ifdef SVR4_COMMENT_CHARS
8074 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8076 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8080 i386_comment_chars
= n
;
8086 arch
= xstrdup (arg
);
8090 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8091 next
= strchr (arch
, '+');
8094 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8096 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8099 cpu_arch_name
= cpu_arch
[j
].name
;
8100 cpu_sub_arch_name
= NULL
;
8101 cpu_arch_flags
= cpu_arch
[j
].flags
;
8102 cpu_arch_isa
= cpu_arch
[j
].type
;
8103 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8104 if (!cpu_arch_tune_set
)
8106 cpu_arch_tune
= cpu_arch_isa
;
8107 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8111 else if (*cpu_arch
[j
].name
== '.'
8112 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8114 /* ISA entension. */
8115 i386_cpu_flags flags
;
8117 if (strncmp (arch
, "no", 2))
8118 flags
= cpu_flags_or (cpu_arch_flags
,
8121 flags
= cpu_flags_and_not (cpu_arch_flags
,
8123 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8125 if (cpu_sub_arch_name
)
8127 char *name
= cpu_sub_arch_name
;
8128 cpu_sub_arch_name
= concat (name
,
8130 (const char *) NULL
);
8134 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8135 cpu_arch_flags
= flags
;
8141 if (j
>= ARRAY_SIZE (cpu_arch
))
8142 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8146 while (next
!= NULL
);
8151 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8152 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8154 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8156 cpu_arch_tune_set
= 1;
8157 cpu_arch_tune
= cpu_arch
[j
].type
;
8158 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8162 if (j
>= ARRAY_SIZE (cpu_arch
))
8163 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8166 case OPTION_MMNEMONIC
:
8167 if (strcasecmp (arg
, "att") == 0)
8169 else if (strcasecmp (arg
, "intel") == 0)
8172 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8175 case OPTION_MSYNTAX
:
8176 if (strcasecmp (arg
, "att") == 0)
8178 else if (strcasecmp (arg
, "intel") == 0)
8181 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8184 case OPTION_MINDEX_REG
:
8185 allow_index_reg
= 1;
8188 case OPTION_MNAKED_REG
:
8189 allow_naked_reg
= 1;
8192 case OPTION_MOLD_GCC
:
8196 case OPTION_MSSE2AVX
:
8200 case OPTION_MSSE_CHECK
:
8201 if (strcasecmp (arg
, "error") == 0)
8202 sse_check
= sse_check_error
;
8203 else if (strcasecmp (arg
, "warning") == 0)
8204 sse_check
= sse_check_warning
;
8205 else if (strcasecmp (arg
, "none") == 0)
8206 sse_check
= sse_check_none
;
8208 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8211 case OPTION_MAVXSCALAR
:
8212 if (strcasecmp (arg
, "128") == 0)
8214 else if (strcasecmp (arg
, "256") == 0)
8217 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8226 #define MESSAGE_TEMPLATE \
8230 show_arch (FILE *stream
, int ext
)
8232 static char message
[] = MESSAGE_TEMPLATE
;
8233 char *start
= message
+ 27;
8235 int size
= sizeof (MESSAGE_TEMPLATE
);
8242 left
= size
- (start
- message
);
8243 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8245 /* Should it be skipped? */
8246 if (cpu_arch
[j
].skip
)
8249 name
= cpu_arch
[j
].name
;
8250 len
= cpu_arch
[j
].len
;
8253 /* It is an extension. Skip if we aren't asked to show it. */
8264 /* It is an processor. Skip if we show only extension. */
8268 /* Reserve 2 spaces for ", " or ",\0" */
8271 /* Check if there is any room. */
8279 p
= mempcpy (p
, name
, len
);
8283 /* Output the current message now and start a new one. */
8286 fprintf (stream
, "%s\n", message
);
8288 left
= size
- (start
- message
) - len
- 2;
8290 gas_assert (left
>= 0);
8292 p
= mempcpy (p
, name
, len
);
8297 fprintf (stream
, "%s\n", message
);
8301 md_show_usage (FILE *stream
)
8303 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8304 fprintf (stream
, _("\
8306 -V print assembler version number\n\
8309 fprintf (stream
, _("\
8310 -n Do not optimize code alignment\n\
8311 -q quieten some warnings\n"));
8312 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8313 fprintf (stream
, _("\
8316 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8317 || defined (TE_PE) || defined (TE_PEP))
8318 fprintf (stream
, _("\
8319 --32/--64 generate 32bit/64bit code\n"));
8321 #ifdef SVR4_COMMENT_CHARS
8322 fprintf (stream
, _("\
8323 --divide do not treat `/' as a comment character\n"));
8325 fprintf (stream
, _("\
8326 --divide ignored\n"));
8328 fprintf (stream
, _("\
8329 -march=CPU[,+EXTENSION...]\n\
8330 generate code for CPU and EXTENSION, CPU is one of:\n"));
8331 show_arch (stream
, 0);
8332 fprintf (stream
, _("\
8333 EXTENSION is combination of:\n"));
8334 show_arch (stream
, 1);
8335 fprintf (stream
, _("\
8336 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8337 show_arch (stream
, 0);
8338 fprintf (stream
, _("\
8339 -msse2avx encode SSE instructions with VEX prefix\n"));
8340 fprintf (stream
, _("\
8341 -msse-check=[none|error|warning]\n\
8342 check SSE instructions\n"));
8343 fprintf (stream
, _("\
8344 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8346 fprintf (stream
, _("\
8347 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8348 fprintf (stream
, _("\
8349 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8350 fprintf (stream
, _("\
8351 -mindex-reg support pseudo index registers\n"));
8352 fprintf (stream
, _("\
8353 -mnaked-reg don't require `%%' prefix for registers\n"));
8354 fprintf (stream
, _("\
8355 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8358 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8359 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8360 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8362 /* Pick the target format to use. */
8365 i386_target_format (void)
8367 if (!strcmp (default_arch
, "x86_64"))
8369 set_code_flag (CODE_64BIT
);
8370 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8372 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8373 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8374 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8375 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8376 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8377 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8378 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8379 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8380 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8381 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8382 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8384 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8386 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8387 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8388 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8389 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8390 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8391 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8392 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8393 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8394 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8395 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8398 else if (!strcmp (default_arch
, "i386"))
8400 set_code_flag (CODE_32BIT
);
8401 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8403 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8404 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8405 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8407 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8409 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8410 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8411 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8415 as_fatal (_("Unknown architecture"));
8416 switch (OUTPUT_FLAVOR
)
8418 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8419 case bfd_target_aout_flavour
:
8420 return AOUT_TARGET_FORMAT
;
8422 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8423 # if defined (TE_PE) || defined (TE_PEP)
8424 case bfd_target_coff_flavour
:
8425 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8426 # elif defined (TE_GO32)
8427 case bfd_target_coff_flavour
:
8430 case bfd_target_coff_flavour
:
8434 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8435 case bfd_target_elf_flavour
:
8437 if (flag_code
== CODE_64BIT
)
8440 use_rela_relocations
= 1;
8442 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8444 if (flag_code
!= CODE_64BIT
)
8445 as_fatal (_("Intel L1OM is 64bit only"));
8446 return ELF_TARGET_L1OM_FORMAT
;
8449 return (flag_code
== CODE_64BIT
8450 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8453 #if defined (OBJ_MACH_O)
8454 case bfd_target_mach_o_flavour
:
8455 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8463 #endif /* OBJ_MAYBE_ more than one */
8465 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8467 i386_elf_emit_arch_note (void)
8469 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8472 asection
*seg
= now_seg
;
8473 subsegT subseg
= now_subseg
;
8474 Elf_Internal_Note i_note
;
8475 Elf_External_Note e_note
;
8476 asection
*note_secp
;
8479 /* Create the .note section. */
8480 note_secp
= subseg_new (".note", 0);
8481 bfd_set_section_flags (stdoutput
,
8483 SEC_HAS_CONTENTS
| SEC_READONLY
);
8485 /* Process the arch string. */
8486 len
= strlen (cpu_arch_name
);
8488 i_note
.namesz
= len
+ 1;
8490 i_note
.type
= NT_ARCH
;
8491 p
= frag_more (sizeof (e_note
.namesz
));
8492 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8493 p
= frag_more (sizeof (e_note
.descsz
));
8494 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8495 p
= frag_more (sizeof (e_note
.type
));
8496 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8497 p
= frag_more (len
+ 1);
8498 strcpy (p
, cpu_arch_name
);
8500 frag_align (2, 0, 0);
8502 subseg_set (seg
, subseg
);
8508 md_undefined_symbol (name
)
8511 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8512 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8513 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8514 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8518 if (symbol_find (name
))
8519 as_bad (_("GOT already in symbol table"));
8520 GOT_symbol
= symbol_new (name
, undefined_section
,
8521 (valueT
) 0, &zero_address_frag
);
8528 /* Round up a section size to the appropriate boundary. */
8531 md_section_align (segment
, size
)
8532 segT segment ATTRIBUTE_UNUSED
;
8535 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8536 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8538 /* For a.out, force the section size to be aligned. If we don't do
8539 this, BFD will align it for us, but it will not write out the
8540 final bytes of the section. This may be a bug in BFD, but it is
8541 easier to fix it here since that is how the other a.out targets
8545 align
= bfd_get_section_alignment (stdoutput
, segment
);
8546 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8553 /* On the i386, PC-relative offsets are relative to the start of the
8554 next instruction. That is, the address of the offset, plus its
8555 size, since the offset is always the last part of the insn. */
8558 md_pcrel_from (fixS
*fixP
)
8560 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8566 s_bss (int ignore ATTRIBUTE_UNUSED
)
8570 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8572 obj_elf_section_change_hook ();
8574 temp
= get_absolute_expression ();
8575 subseg_set (bss_section
, (subsegT
) temp
);
8576 demand_empty_rest_of_line ();
8582 i386_validate_fix (fixS
*fixp
)
8584 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8586 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8590 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8595 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8597 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8604 tc_gen_reloc (section
, fixp
)
8605 asection
*section ATTRIBUTE_UNUSED
;
8609 bfd_reloc_code_real_type code
;
8611 switch (fixp
->fx_r_type
)
8613 case BFD_RELOC_X86_64_PLT32
:
8614 case BFD_RELOC_X86_64_GOT32
:
8615 case BFD_RELOC_X86_64_GOTPCREL
:
8616 case BFD_RELOC_386_PLT32
:
8617 case BFD_RELOC_386_GOT32
:
8618 case BFD_RELOC_386_GOTOFF
:
8619 case BFD_RELOC_386_GOTPC
:
8620 case BFD_RELOC_386_TLS_GD
:
8621 case BFD_RELOC_386_TLS_LDM
:
8622 case BFD_RELOC_386_TLS_LDO_32
:
8623 case BFD_RELOC_386_TLS_IE_32
:
8624 case BFD_RELOC_386_TLS_IE
:
8625 case BFD_RELOC_386_TLS_GOTIE
:
8626 case BFD_RELOC_386_TLS_LE_32
:
8627 case BFD_RELOC_386_TLS_LE
:
8628 case BFD_RELOC_386_TLS_GOTDESC
:
8629 case BFD_RELOC_386_TLS_DESC_CALL
:
8630 case BFD_RELOC_X86_64_TLSGD
:
8631 case BFD_RELOC_X86_64_TLSLD
:
8632 case BFD_RELOC_X86_64_DTPOFF32
:
8633 case BFD_RELOC_X86_64_DTPOFF64
:
8634 case BFD_RELOC_X86_64_GOTTPOFF
:
8635 case BFD_RELOC_X86_64_TPOFF32
:
8636 case BFD_RELOC_X86_64_TPOFF64
:
8637 case BFD_RELOC_X86_64_GOTOFF64
:
8638 case BFD_RELOC_X86_64_GOTPC32
:
8639 case BFD_RELOC_X86_64_GOT64
:
8640 case BFD_RELOC_X86_64_GOTPCREL64
:
8641 case BFD_RELOC_X86_64_GOTPC64
:
8642 case BFD_RELOC_X86_64_GOTPLT64
:
8643 case BFD_RELOC_X86_64_PLTOFF64
:
8644 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8645 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8647 case BFD_RELOC_VTABLE_ENTRY
:
8648 case BFD_RELOC_VTABLE_INHERIT
:
8650 case BFD_RELOC_32_SECREL
:
8652 code
= fixp
->fx_r_type
;
8654 case BFD_RELOC_X86_64_32S
:
8655 if (!fixp
->fx_pcrel
)
8657 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8658 code
= fixp
->fx_r_type
;
8664 switch (fixp
->fx_size
)
8667 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8668 _("can not do %d byte pc-relative relocation"),
8670 code
= BFD_RELOC_32_PCREL
;
8672 case 1: code
= BFD_RELOC_8_PCREL
; break;
8673 case 2: code
= BFD_RELOC_16_PCREL
; break;
8674 case 4: code
= BFD_RELOC_32_PCREL
; break;
8676 case 8: code
= BFD_RELOC_64_PCREL
; break;
8682 switch (fixp
->fx_size
)
8685 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8686 _("can not do %d byte relocation"),
8688 code
= BFD_RELOC_32
;
8690 case 1: code
= BFD_RELOC_8
; break;
8691 case 2: code
= BFD_RELOC_16
; break;
8692 case 4: code
= BFD_RELOC_32
; break;
8694 case 8: code
= BFD_RELOC_64
; break;
8701 if ((code
== BFD_RELOC_32
8702 || code
== BFD_RELOC_32_PCREL
8703 || code
== BFD_RELOC_X86_64_32S
)
8705 && fixp
->fx_addsy
== GOT_symbol
)
8708 code
= BFD_RELOC_386_GOTPC
;
8710 code
= BFD_RELOC_X86_64_GOTPC32
;
8712 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8714 && fixp
->fx_addsy
== GOT_symbol
)
8716 code
= BFD_RELOC_X86_64_GOTPC64
;
8719 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8720 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8721 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8723 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8725 if (!use_rela_relocations
)
8727 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8728 vtable entry to be used in the relocation's section offset. */
8729 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8730 rel
->address
= fixp
->fx_offset
;
8731 #if defined (OBJ_COFF) && defined (TE_PE)
8732 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8733 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8738 /* Use the rela in 64bit mode. */
8741 if (!fixp
->fx_pcrel
)
8742 rel
->addend
= fixp
->fx_offset
;
8746 case BFD_RELOC_X86_64_PLT32
:
8747 case BFD_RELOC_X86_64_GOT32
:
8748 case BFD_RELOC_X86_64_GOTPCREL
:
8749 case BFD_RELOC_X86_64_TLSGD
:
8750 case BFD_RELOC_X86_64_TLSLD
:
8751 case BFD_RELOC_X86_64_GOTTPOFF
:
8752 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8753 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8754 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8757 rel
->addend
= (section
->vma
8759 + fixp
->fx_addnumber
8760 + md_pcrel_from (fixp
));
8765 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8766 if (rel
->howto
== NULL
)
8768 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8769 _("cannot represent relocation type %s"),
8770 bfd_get_reloc_code_name (code
));
8771 /* Set howto to a garbage value so that we can keep going. */
8772 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8773 gas_assert (rel
->howto
!= NULL
);
8779 #include "tc-i386-intel.c"
8782 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8784 int saved_naked_reg
;
8785 char saved_register_dot
;
8787 saved_naked_reg
= allow_naked_reg
;
8788 allow_naked_reg
= 1;
8789 saved_register_dot
= register_chars
['.'];
8790 register_chars
['.'] = '.';
8791 allow_pseudo_reg
= 1;
8792 expression_and_evaluate (exp
);
8793 allow_pseudo_reg
= 0;
8794 register_chars
['.'] = saved_register_dot
;
8795 allow_naked_reg
= saved_naked_reg
;
8797 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8799 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8801 exp
->X_op
= O_constant
;
8802 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8803 .dw2_regnum
[flag_code
>> 1];
8806 exp
->X_op
= O_illegal
;
8811 tc_x86_frame_initial_instructions (void)
8813 static unsigned int sp_regno
[2];
8815 if (!sp_regno
[flag_code
>> 1])
8817 char *saved_input
= input_line_pointer
;
8818 char sp
[][4] = {"esp", "rsp"};
8821 input_line_pointer
= sp
[flag_code
>> 1];
8822 tc_x86_parse_to_dw2regnum (&exp
);
8823 gas_assert (exp
.X_op
== O_constant
);
8824 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8825 input_line_pointer
= saved_input
;
8828 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8829 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8833 i386_elf_section_type (const char *str
, size_t len
)
8835 if (flag_code
== CODE_64BIT
8836 && len
== sizeof ("unwind") - 1
8837 && strncmp (str
, "unwind", 6) == 0)
8838 return SHT_X86_64_UNWIND
;
8845 i386_solaris_fix_up_eh_frame (segT sec
)
8847 if (flag_code
== CODE_64BIT
)
8848 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8854 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8858 exp
.X_op
= O_secrel
;
8859 exp
.X_add_symbol
= symbol
;
8860 exp
.X_add_number
= 0;
8861 emit_expr (&exp
, size
);
8865 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8866 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8869 x86_64_section_letter (int letter
, char **ptr_msg
)
8871 if (flag_code
== CODE_64BIT
)
8874 return SHF_X86_64_LARGE
;
8876 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8879 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8884 x86_64_section_word (char *str
, size_t len
)
8886 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8887 return SHF_X86_64_LARGE
;
8893 handle_large_common (int small ATTRIBUTE_UNUSED
)
8895 if (flag_code
!= CODE_64BIT
)
8897 s_comm_internal (0, elf_common_parse
);
8898 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8902 static segT lbss_section
;
8903 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8904 asection
*saved_bss_section
= bss_section
;
8906 if (lbss_section
== NULL
)
8908 flagword applicable
;
8910 subsegT subseg
= now_subseg
;
8912 /* The .lbss section is for local .largecomm symbols. */
8913 lbss_section
= subseg_new (".lbss", 0);
8914 applicable
= bfd_applicable_section_flags (stdoutput
);
8915 bfd_set_section_flags (stdoutput
, lbss_section
,
8916 applicable
& SEC_ALLOC
);
8917 seg_info (lbss_section
)->bss
= 1;
8919 subseg_set (seg
, subseg
);
8922 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8923 bss_section
= lbss_section
;
8925 s_comm_internal (0, elf_common_parse
);
8927 elf_com_section_ptr
= saved_com_section_ptr
;
8928 bss_section
= saved_bss_section
;
8931 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */