1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void update_code_flag (int, int);
139 static void set_code_flag (int);
140 static void set_16bit_gcc_code_flag (int);
141 static void set_intel_syntax (int);
142 static void set_intel_mnemonic (int);
143 static void set_allow_index_reg (int);
144 static void set_sse_check (int);
145 static void set_cpu_arch (int);
147 static void pe_directive_secrel (int);
149 static void signed_cons (int);
150 static char *output_invalid (int c
);
151 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
153 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
155 static int i386_att_operand (char *);
156 static int i386_intel_operand (char *, int);
157 static int i386_intel_simplify (expressionS
*);
158 static int i386_intel_parse_name (const char *, expressionS
*);
159 static const reg_entry
*parse_register (char *, char **);
160 static char *parse_insn (char *, char *);
161 static char *parse_operands (char *, const char *);
162 static void swap_operands (void);
163 static void swap_2_operands (int, int);
164 static void optimize_imm (void);
165 static void optimize_disp (void);
166 static const insn_template
*match_template (void);
167 static int check_string (void);
168 static int process_suffix (void);
169 static int check_byte_reg (void);
170 static int check_long_reg (void);
171 static int check_qword_reg (void);
172 static int check_word_reg (void);
173 static int finalize_imm (void);
174 static int process_operands (void);
175 static const seg_entry
*build_modrm_byte (void);
176 static void output_insn (void);
177 static void output_imm (fragS
*, offsetT
);
178 static void output_disp (fragS
*, offsetT
);
180 static void s_bss (int);
182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
183 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
186 static const char *default_arch
= DEFAULT_ARCH
;
191 /* VEX prefix is either 2 byte or 3 byte. */
192 unsigned char bytes
[3];
194 /* Destination or source register specifier. */
195 const reg_entry
*register_specifier
;
198 /* 'md_assemble ()' gathers together information and puts it into a
205 const reg_entry
*regs
;
210 operand_size_mismatch
,
211 operand_type_mismatch
,
212 register_type_mismatch
,
213 number_of_operands_mismatch
,
214 invalid_instruction_suffix
,
217 unsupported_with_intel_mnemonic
,
224 /* TM holds the template for the insn were currently assembling. */
227 /* SUFFIX holds the instruction size suffix for byte, word, dword
228 or qword, if given. */
231 /* OPERANDS gives the number of given operands. */
232 unsigned int operands
;
234 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
235 of given register, displacement, memory operands and immediate
237 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
239 /* TYPES [i] is the type (see above #defines) which tells us how to
240 use OP[i] for the corresponding operand. */
241 i386_operand_type types
[MAX_OPERANDS
];
243 /* Displacement expression, immediate expression, or register for each
245 union i386_op op
[MAX_OPERANDS
];
247 /* Flags for operands. */
248 unsigned int flags
[MAX_OPERANDS
];
249 #define Operand_PCrel 1
251 /* Relocation type for operand */
252 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
254 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
255 the base index byte below. */
256 const reg_entry
*base_reg
;
257 const reg_entry
*index_reg
;
258 unsigned int log2_scale_factor
;
260 /* SEG gives the seg_entries of this insn. They are zero unless
261 explicit segment overrides are given. */
262 const seg_entry
*seg
[2];
264 /* PREFIX holds all the given prefix opcodes (usually null).
265 PREFIXES is the number of prefix opcodes. */
266 unsigned int prefixes
;
267 unsigned char prefix
[MAX_PREFIXES
];
269 /* RM and SIB are the modrm byte and the sib byte where the
270 addressing modes of this insn are encoded. */
276 /* Swap operand in encoding. */
277 unsigned int swap_operand
;
280 enum i386_error error
;
283 typedef struct _i386_insn i386_insn
;
285 /* List of chars besides those in app.c:symbol_chars that can start an
286 operand. Used to prevent the scrubber eating vital white-space. */
287 const char extra_symbol_chars
[] = "*%-(["
296 #if (defined (TE_I386AIX) \
297 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
298 && !defined (TE_GNU) \
299 && !defined (TE_LINUX) \
300 && !defined (TE_NETWARE) \
301 && !defined (TE_FreeBSD) \
302 && !defined (TE_NetBSD)))
303 /* This array holds the chars that always start a comment. If the
304 pre-processor is disabled, these aren't very useful. The option
305 --divide will remove '/' from this list. */
306 const char *i386_comment_chars
= "#/";
307 #define SVR4_COMMENT_CHARS 1
308 #define PREFIX_SEPARATOR '\\'
311 const char *i386_comment_chars
= "#";
312 #define PREFIX_SEPARATOR '/'
315 /* This array holds the chars that only start a comment at the beginning of
316 a line. If the line seems to have the form '# 123 filename'
317 .line and .file directives will appear in the pre-processed output.
318 Note that input_file.c hand checks for '#' at the beginning of the
319 first line of the input file. This is because the compiler outputs
320 #NO_APP at the beginning of its output.
321 Also note that comments started like this one will always work if
322 '/' isn't otherwise defined. */
323 const char line_comment_chars
[] = "#/";
325 const char line_separator_chars
[] = ";";
327 /* Chars that can be used to separate mant from exp in floating point
329 const char EXP_CHARS
[] = "eE";
331 /* Chars that mean this number is a floating point constant
334 const char FLT_CHARS
[] = "fFdDxX";
336 /* Tables for lexical analysis. */
337 static char mnemonic_chars
[256];
338 static char register_chars
[256];
339 static char operand_chars
[256];
340 static char identifier_chars
[256];
341 static char digit_chars
[256];
343 /* Lexical macros. */
344 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
345 #define is_operand_char(x) (operand_chars[(unsigned char) x])
346 #define is_register_char(x) (register_chars[(unsigned char) x])
347 #define is_space_char(x) ((x) == ' ')
348 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
349 #define is_digit_char(x) (digit_chars[(unsigned char) x])
351 /* All non-digit non-letter characters that may occur in an operand. */
352 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
354 /* md_assemble() always leaves the strings it's passed unaltered. To
355 effect this we maintain a stack of saved characters that we've smashed
356 with '\0's (indicating end of strings for various sub-fields of the
357 assembler instruction). */
358 static char save_stack
[32];
359 static char *save_stack_p
;
360 #define END_STRING_AND_SAVE(s) \
361 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
362 #define RESTORE_END_STRING(s) \
363 do { *(s) = *--save_stack_p; } while (0)
365 /* The instruction we're assembling. */
368 /* Possible templates for current insn. */
369 static const templates
*current_templates
;
371 /* Per instruction expressionS buffers: max displacements & immediates. */
372 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
373 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
375 /* Current operand we are working on. */
376 static int this_operand
= -1;
378 /* We support four different modes. FLAG_CODE variable is used to distinguish
386 static enum flag_code flag_code
;
387 static unsigned int object_64bit
;
388 static int use_rela_relocations
= 0;
390 /* The names used to print error messages. */
391 static const char *flag_code_names
[] =
398 /* 1 for intel syntax,
400 static int intel_syntax
= 0;
402 /* 1 for intel mnemonic,
403 0 if att mnemonic. */
404 static int intel_mnemonic
= !SYSV386_COMPAT
;
406 /* 1 if support old (<= 2.8.1) versions of gcc. */
407 static int old_gcc
= OLDGCC_COMPAT
;
409 /* 1 if pseudo registers are permitted. */
410 static int allow_pseudo_reg
= 0;
412 /* 1 if register prefix % not required. */
413 static int allow_naked_reg
= 0;
415 /* 1 if pseudo index register, eiz/riz, is allowed . */
416 static int allow_index_reg
= 0;
426 /* Register prefix used for error message. */
427 static const char *register_prefix
= "%";
429 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
430 leave, push, and pop instructions so that gcc has the same stack
431 frame as in 32 bit mode. */
432 static char stackop_size
= '\0';
434 /* Non-zero to optimize code alignment. */
435 int optimize_align_code
= 1;
437 /* Non-zero to quieten some warnings. */
438 static int quiet_warnings
= 0;
441 static const char *cpu_arch_name
= NULL
;
442 static char *cpu_sub_arch_name
= NULL
;
444 /* CPU feature flags. */
445 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
447 /* If we have selected a cpu we are generating instructions for. */
448 static int cpu_arch_tune_set
= 0;
450 /* Cpu we are generating instructions for. */
451 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
453 /* CPU feature flags of cpu we are generating instructions for. */
454 static i386_cpu_flags cpu_arch_tune_flags
;
456 /* CPU instruction set architecture used. */
457 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
459 /* CPU feature flags of instruction set architecture used. */
460 i386_cpu_flags cpu_arch_isa_flags
;
462 /* If set, conditional jumps are not automatically promoted to handle
463 larger than a byte offset. */
464 static unsigned int no_cond_jump_promotion
= 0;
466 /* Encode SSE instructions with VEX prefix. */
467 static unsigned int sse2avx
;
469 /* Encode scalar AVX instructions with specific vector length. */
476 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
477 static symbolS
*GOT_symbol
;
479 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
480 unsigned int x86_dwarf2_return_column
;
482 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
483 int x86_cie_data_alignment
;
485 /* Interface to relax_segment.
486 There are 3 major relax states for 386 jump insns because the
487 different types of jumps add different sizes to frags when we're
488 figuring out what sort of jump to choose to reach a given label. */
491 #define UNCOND_JUMP 0
493 #define COND_JUMP86 2
498 #define SMALL16 (SMALL | CODE16)
500 #define BIG16 (BIG | CODE16)
504 #define INLINE __inline__
510 #define ENCODE_RELAX_STATE(type, size) \
511 ((relax_substateT) (((type) << 2) | (size)))
512 #define TYPE_FROM_RELAX_STATE(s) \
514 #define DISP_SIZE_FROM_RELAX_STATE(s) \
515 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
517 /* This table is used by relax_frag to promote short jumps to long
518 ones where necessary. SMALL (short) jumps may be promoted to BIG
519 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
520 don't allow a short jump in a 32 bit code segment to be promoted to
521 a 16 bit offset jump because it's slower (requires data size
522 prefix), and doesn't work, unless the destination is in the bottom
523 64k of the code segment (The top 16 bits of eip are zeroed). */
525 const relax_typeS md_relax_table
[] =
528 1) most positive reach of this state,
529 2) most negative reach of this state,
530 3) how many bytes this mode will have in the variable part of the frag
531 4) which index into the table to try if we can't fit into this one. */
533 /* UNCOND_JUMP states. */
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
535 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
536 /* dword jmp adds 4 bytes to frag:
537 0 extra opcode bytes, 4 displacement bytes. */
539 /* word jmp adds 2 byte2 to frag:
540 0 extra opcode bytes, 2 displacement bytes. */
543 /* COND_JUMP states. */
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
545 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
546 /* dword conditionals adds 5 bytes to frag:
547 1 extra opcode byte, 4 displacement bytes. */
549 /* word conditionals add 3 bytes to frag:
550 1 extra opcode byte, 2 displacement bytes. */
553 /* COND_JUMP86 states. */
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
556 /* dword conditionals adds 5 bytes to frag:
557 1 extra opcode byte, 4 displacement bytes. */
559 /* word conditionals add 4 bytes to frag:
560 1 displacement byte and a 3 byte long branch insn. */
564 static const arch_entry cpu_arch
[] =
566 /* Do not replace the first two entries - i386_target_format()
567 relies on them being there in this order. */
568 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
569 CPU_GENERIC32_FLAGS
, 0 },
570 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
571 CPU_GENERIC64_FLAGS
, 0 },
572 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
574 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
576 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
578 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
580 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
582 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
584 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
586 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
588 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
590 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
592 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
594 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
596 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
598 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
599 CPU_NOCONA_FLAGS
, 0 },
600 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
602 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
604 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
605 CPU_CORE2_FLAGS
, 1 },
606 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
607 CPU_CORE2_FLAGS
, 0 },
608 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
609 CPU_COREI7_FLAGS
, 0 },
610 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
612 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
614 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
616 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
617 CPU_ATHLON_FLAGS
, 0 },
618 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
620 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
622 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
624 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
625 CPU_AMDFAM10_FLAGS
, 0 },
626 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
627 CPU_BDVER1_FLAGS
, 0 },
628 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
630 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
632 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
634 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
635 CPU_ANY87_FLAGS
, 0 },
636 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
638 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
639 CPU_3DNOWA_FLAGS
, 0 },
640 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
642 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
644 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
646 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
647 CPU_SSSE3_FLAGS
, 0 },
648 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
649 CPU_SSE4_1_FLAGS
, 0 },
650 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
651 CPU_SSE4_2_FLAGS
, 0 },
652 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
653 CPU_SSE4_2_FLAGS
, 0 },
654 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
655 CPU_ANY_SSE_FLAGS
, 0 },
656 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
658 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
659 CPU_ANY_AVX_FLAGS
, 0 },
660 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
662 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
664 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
665 CPU_XSAVE_FLAGS
, 0 },
666 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
668 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
669 CPU_PCLMUL_FLAGS
, 0 },
670 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
671 CPU_PCLMUL_FLAGS
, 1 },
672 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
674 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
676 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
678 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
680 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
681 CPU_MOVBE_FLAGS
, 0 },
682 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
684 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
685 CPU_CLFLUSH_FLAGS
, 0 },
686 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
687 CPU_SYSCALL_FLAGS
, 0 },
688 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
689 CPU_RDTSCP_FLAGS
, 0 },
690 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
691 CPU_3DNOW_FLAGS
, 0 },
692 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
693 CPU_3DNOWA_FLAGS
, 0 },
694 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
695 CPU_PADLOCK_FLAGS
, 0 },
696 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
698 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
700 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
701 CPU_SSE4A_FLAGS
, 0 },
702 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
707 /* Like s_lcomm_internal in gas/read.c but the alignment string
708 is allowed to be optional. */
711 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
718 && *input_line_pointer
== ',')
720 align
= parse_align (needs_align
- 1);
722 if (align
== (addressT
) -1)
737 bss_alloc (symbolP
, size
, align
);
742 pe_lcomm (int needs_align
)
744 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
748 const pseudo_typeS md_pseudo_table
[] =
750 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
751 {"align", s_align_bytes
, 0},
753 {"align", s_align_ptwo
, 0},
755 {"arch", set_cpu_arch
, 0},
759 {"lcomm", pe_lcomm
, 1},
761 {"ffloat", float_cons
, 'f'},
762 {"dfloat", float_cons
, 'd'},
763 {"tfloat", float_cons
, 'x'},
765 {"slong", signed_cons
, 4},
766 {"noopt", s_ignore
, 0},
767 {"optim", s_ignore
, 0},
768 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
769 {"code16", set_code_flag
, CODE_16BIT
},
770 {"code32", set_code_flag
, CODE_32BIT
},
771 {"code64", set_code_flag
, CODE_64BIT
},
772 {"intel_syntax", set_intel_syntax
, 1},
773 {"att_syntax", set_intel_syntax
, 0},
774 {"intel_mnemonic", set_intel_mnemonic
, 1},
775 {"att_mnemonic", set_intel_mnemonic
, 0},
776 {"allow_index_reg", set_allow_index_reg
, 1},
777 {"disallow_index_reg", set_allow_index_reg
, 0},
778 {"sse_check", set_sse_check
, 0},
779 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
780 {"largecomm", handle_large_common
, 0},
782 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
783 {"loc", dwarf2_directive_loc
, 0},
784 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
787 {"secrel32", pe_directive_secrel
, 0},
792 /* For interface with expression (). */
793 extern char *input_line_pointer
;
795 /* Hash table for instruction mnemonic lookup. */
796 static struct hash_control
*op_hash
;
798 /* Hash table for register lookup. */
799 static struct hash_control
*reg_hash
;
802 i386_align_code (fragS
*fragP
, int count
)
804 /* Various efficient no-op patterns for aligning code labels.
805 Note: Don't try to assemble the instructions in the comments.
806 0L and 0w are not legal. */
807 static const char f32_1
[] =
809 static const char f32_2
[] =
810 {0x66,0x90}; /* xchg %ax,%ax */
811 static const char f32_3
[] =
812 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
813 static const char f32_4
[] =
814 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
815 static const char f32_5
[] =
817 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
818 static const char f32_6
[] =
819 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
820 static const char f32_7
[] =
821 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
822 static const char f32_8
[] =
824 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
825 static const char f32_9
[] =
826 {0x89,0xf6, /* movl %esi,%esi */
827 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
828 static const char f32_10
[] =
829 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
830 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
831 static const char f32_11
[] =
832 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
833 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
834 static const char f32_12
[] =
835 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
836 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
837 static const char f32_13
[] =
838 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
839 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
840 static const char f32_14
[] =
841 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
842 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
843 static const char f16_3
[] =
844 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
845 static const char f16_4
[] =
846 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
847 static const char f16_5
[] =
849 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
850 static const char f16_6
[] =
851 {0x89,0xf6, /* mov %si,%si */
852 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
853 static const char f16_7
[] =
854 {0x8d,0x74,0x00, /* lea 0(%si),%si */
855 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
856 static const char f16_8
[] =
857 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
858 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
859 static const char jump_31
[] =
860 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
861 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
862 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
863 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
864 static const char *const f32_patt
[] = {
865 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
866 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
868 static const char *const f16_patt
[] = {
869 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
872 static const char alt_3
[] =
874 /* nopl 0(%[re]ax) */
875 static const char alt_4
[] =
876 {0x0f,0x1f,0x40,0x00};
877 /* nopl 0(%[re]ax,%[re]ax,1) */
878 static const char alt_5
[] =
879 {0x0f,0x1f,0x44,0x00,0x00};
880 /* nopw 0(%[re]ax,%[re]ax,1) */
881 static const char alt_6
[] =
882 {0x66,0x0f,0x1f,0x44,0x00,0x00};
883 /* nopl 0L(%[re]ax) */
884 static const char alt_7
[] =
885 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
886 /* nopl 0L(%[re]ax,%[re]ax,1) */
887 static const char alt_8
[] =
888 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 /* nopw 0L(%[re]ax,%[re]ax,1) */
890 static const char alt_9
[] =
891 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
892 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
893 static const char alt_10
[] =
894 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_11
[] =
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 nopw %cs:0L(%[re]ax,%[re]ax,1) */
903 static const char alt_long_12
[] =
906 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
910 nopw %cs:0L(%[re]ax,%[re]ax,1) */
911 static const char alt_long_13
[] =
915 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
920 nopw %cs:0L(%[re]ax,%[re]ax,1) */
921 static const char alt_long_14
[] =
926 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
932 nopw %cs:0L(%[re]ax,%[re]ax,1) */
933 static const char alt_long_15
[] =
939 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
940 /* nopl 0(%[re]ax,%[re]ax,1)
941 nopw 0(%[re]ax,%[re]ax,1) */
942 static const char alt_short_11
[] =
943 {0x0f,0x1f,0x44,0x00,0x00,
944 0x66,0x0f,0x1f,0x44,0x00,0x00};
945 /* nopw 0(%[re]ax,%[re]ax,1)
946 nopw 0(%[re]ax,%[re]ax,1) */
947 static const char alt_short_12
[] =
948 {0x66,0x0f,0x1f,0x44,0x00,0x00,
949 0x66,0x0f,0x1f,0x44,0x00,0x00};
950 /* nopw 0(%[re]ax,%[re]ax,1)
952 static const char alt_short_13
[] =
953 {0x66,0x0f,0x1f,0x44,0x00,0x00,
954 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
957 static const char alt_short_14
[] =
958 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
959 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
961 nopl 0L(%[re]ax,%[re]ax,1) */
962 static const char alt_short_15
[] =
963 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
964 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
965 static const char *const alt_short_patt
[] = {
966 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
967 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
968 alt_short_14
, alt_short_15
970 static const char *const alt_long_patt
[] = {
971 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
972 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
973 alt_long_14
, alt_long_15
976 /* Only align for at least a positive non-zero boundary. */
977 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
980 /* We need to decide which NOP sequence to use for 32bit and
981 64bit. When -mtune= is used:
983 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
984 PROCESSOR_GENERIC32, f32_patt will be used.
985 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
986 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
987 PROCESSOR_GENERIC64, alt_long_patt will be used.
988 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
989 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
992 When -mtune= isn't used, alt_long_patt will be used if
993 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
996 When -march= or .arch is used, we can't use anything beyond
997 cpu_arch_isa_flags. */
999 if (flag_code
== CODE_16BIT
)
1003 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1005 /* Adjust jump offset. */
1006 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1009 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1010 f16_patt
[count
- 1], count
);
1014 const char *const *patt
= NULL
;
1016 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1018 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1019 switch (cpu_arch_tune
)
1021 case PROCESSOR_UNKNOWN
:
1022 /* We use cpu_arch_isa_flags to check if we SHOULD
1023 optimize for Cpu686. */
1024 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1025 patt
= alt_long_patt
;
1029 case PROCESSOR_PENTIUMPRO
:
1030 case PROCESSOR_PENTIUM4
:
1031 case PROCESSOR_NOCONA
:
1032 case PROCESSOR_CORE
:
1033 case PROCESSOR_CORE2
:
1034 case PROCESSOR_COREI7
:
1035 case PROCESSOR_L1OM
:
1036 case PROCESSOR_GENERIC64
:
1037 patt
= alt_long_patt
;
1040 case PROCESSOR_ATHLON
:
1042 case PROCESSOR_AMDFAM10
:
1043 case PROCESSOR_BDVER1
:
1044 patt
= alt_short_patt
;
1046 case PROCESSOR_I386
:
1047 case PROCESSOR_I486
:
1048 case PROCESSOR_PENTIUM
:
1049 case PROCESSOR_GENERIC32
:
1056 switch (fragP
->tc_frag_data
.tune
)
1058 case PROCESSOR_UNKNOWN
:
1059 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1060 PROCESSOR_UNKNOWN. */
1064 case PROCESSOR_I386
:
1065 case PROCESSOR_I486
:
1066 case PROCESSOR_PENTIUM
:
1068 case PROCESSOR_ATHLON
:
1070 case PROCESSOR_AMDFAM10
:
1071 case PROCESSOR_BDVER1
:
1072 case PROCESSOR_GENERIC32
:
1073 /* We use cpu_arch_isa_flags to check if we CAN optimize
1075 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1076 patt
= alt_short_patt
;
1080 case PROCESSOR_PENTIUMPRO
:
1081 case PROCESSOR_PENTIUM4
:
1082 case PROCESSOR_NOCONA
:
1083 case PROCESSOR_CORE
:
1084 case PROCESSOR_CORE2
:
1085 case PROCESSOR_COREI7
:
1086 case PROCESSOR_L1OM
:
1087 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1088 patt
= alt_long_patt
;
1092 case PROCESSOR_GENERIC64
:
1093 patt
= alt_long_patt
;
1098 if (patt
== f32_patt
)
1100 /* If the padding is less than 15 bytes, we use the normal
1101 ones. Otherwise, we use a jump instruction and adjust
1105 /* For 64bit, the limit is 3 bytes. */
1106 if (flag_code
== CODE_64BIT
1107 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1112 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1113 patt
[count
- 1], count
);
1116 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1118 /* Adjust jump offset. */
1119 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1124 /* Maximum length of an instruction is 15 byte. If the
1125 padding is greater than 15 bytes and we don't use jump,
1126 we have to break it into smaller pieces. */
1127 int padding
= count
;
1128 while (padding
> 15)
1131 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1136 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1137 patt
[padding
- 1], padding
);
1140 fragP
->fr_var
= count
;
1144 operand_type_all_zero (const union i386_operand_type
*x
)
1146 switch (ARRAY_SIZE(x
->array
))
1155 return !x
->array
[0];
1162 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1164 switch (ARRAY_SIZE(x
->array
))
1179 operand_type_equal (const union i386_operand_type
*x
,
1180 const union i386_operand_type
*y
)
1182 switch (ARRAY_SIZE(x
->array
))
1185 if (x
->array
[2] != y
->array
[2])
1188 if (x
->array
[1] != y
->array
[1])
1191 return x
->array
[0] == y
->array
[0];
1199 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1201 switch (ARRAY_SIZE(x
->array
))
1210 return !x
->array
[0];
1217 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1219 switch (ARRAY_SIZE(x
->array
))
1234 cpu_flags_equal (const union i386_cpu_flags
*x
,
1235 const union i386_cpu_flags
*y
)
1237 switch (ARRAY_SIZE(x
->array
))
1240 if (x
->array
[2] != y
->array
[2])
1243 if (x
->array
[1] != y
->array
[1])
1246 return x
->array
[0] == y
->array
[0];
1254 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1256 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1257 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1260 static INLINE i386_cpu_flags
1261 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1263 switch (ARRAY_SIZE (x
.array
))
1266 x
.array
[2] &= y
.array
[2];
1268 x
.array
[1] &= y
.array
[1];
1270 x
.array
[0] &= y
.array
[0];
1278 static INLINE i386_cpu_flags
1279 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1281 switch (ARRAY_SIZE (x
.array
))
1284 x
.array
[2] |= y
.array
[2];
1286 x
.array
[1] |= y
.array
[1];
1288 x
.array
[0] |= y
.array
[0];
1296 static INLINE i386_cpu_flags
1297 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1299 switch (ARRAY_SIZE (x
.array
))
1302 x
.array
[2] &= ~y
.array
[2];
1304 x
.array
[1] &= ~y
.array
[1];
1306 x
.array
[0] &= ~y
.array
[0];
1314 #define CPU_FLAGS_ARCH_MATCH 0x1
1315 #define CPU_FLAGS_64BIT_MATCH 0x2
1316 #define CPU_FLAGS_AES_MATCH 0x4
1317 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1318 #define CPU_FLAGS_AVX_MATCH 0x10
1320 #define CPU_FLAGS_32BIT_MATCH \
1321 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1322 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1323 #define CPU_FLAGS_PERFECT_MATCH \
1324 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1326 /* Return CPU flags match bits. */
1329 cpu_flags_match (const insn_template
*t
)
1331 i386_cpu_flags x
= t
->cpu_flags
;
1332 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1334 x
.bitfield
.cpu64
= 0;
1335 x
.bitfield
.cpuno64
= 0;
1337 if (cpu_flags_all_zero (&x
))
1339 /* This instruction is available on all archs. */
1340 match
|= CPU_FLAGS_32BIT_MATCH
;
1344 /* This instruction is available only on some archs. */
1345 i386_cpu_flags cpu
= cpu_arch_flags
;
1347 cpu
.bitfield
.cpu64
= 0;
1348 cpu
.bitfield
.cpuno64
= 0;
1349 cpu
= cpu_flags_and (x
, cpu
);
1350 if (!cpu_flags_all_zero (&cpu
))
1352 if (x
.bitfield
.cpuavx
)
1354 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1355 if (cpu
.bitfield
.cpuavx
)
1357 /* Check SSE2AVX. */
1358 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1360 match
|= (CPU_FLAGS_ARCH_MATCH
1361 | CPU_FLAGS_AVX_MATCH
);
1363 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1364 match
|= CPU_FLAGS_AES_MATCH
;
1366 if (!x
.bitfield
.cpupclmul
1367 || cpu
.bitfield
.cpupclmul
)
1368 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1372 match
|= CPU_FLAGS_ARCH_MATCH
;
1375 match
|= CPU_FLAGS_32BIT_MATCH
;
1381 static INLINE i386_operand_type
1382 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1384 switch (ARRAY_SIZE (x
.array
))
1387 x
.array
[2] &= y
.array
[2];
1389 x
.array
[1] &= y
.array
[1];
1391 x
.array
[0] &= y
.array
[0];
1399 static INLINE i386_operand_type
1400 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1402 switch (ARRAY_SIZE (x
.array
))
1405 x
.array
[2] |= y
.array
[2];
1407 x
.array
[1] |= y
.array
[1];
1409 x
.array
[0] |= y
.array
[0];
1417 static INLINE i386_operand_type
1418 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1420 switch (ARRAY_SIZE (x
.array
))
1423 x
.array
[2] ^= y
.array
[2];
1425 x
.array
[1] ^= y
.array
[1];
1427 x
.array
[0] ^= y
.array
[0];
1435 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1436 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1437 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1438 static const i386_operand_type inoutportreg
1439 = OPERAND_TYPE_INOUTPORTREG
;
1440 static const i386_operand_type reg16_inoutportreg
1441 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1442 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1443 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1444 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1445 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1446 static const i386_operand_type anydisp
1447 = OPERAND_TYPE_ANYDISP
;
1448 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1449 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1450 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1451 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1452 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1453 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1454 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1455 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1456 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1457 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1458 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1459 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1470 operand_type_check (i386_operand_type t
, enum operand_type c
)
1475 return (t
.bitfield
.reg8
1478 || t
.bitfield
.reg64
);
1481 return (t
.bitfield
.imm8
1485 || t
.bitfield
.imm32s
1486 || t
.bitfield
.imm64
);
1489 return (t
.bitfield
.disp8
1490 || t
.bitfield
.disp16
1491 || t
.bitfield
.disp32
1492 || t
.bitfield
.disp32s
1493 || t
.bitfield
.disp64
);
1496 return (t
.bitfield
.disp8
1497 || t
.bitfield
.disp16
1498 || t
.bitfield
.disp32
1499 || t
.bitfield
.disp32s
1500 || t
.bitfield
.disp64
1501 || t
.bitfield
.baseindex
);
1510 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1511 operand J for instruction template T. */
1514 match_reg_size (const insn_template
*t
, unsigned int j
)
1516 return !((i
.types
[j
].bitfield
.byte
1517 && !t
->operand_types
[j
].bitfield
.byte
)
1518 || (i
.types
[j
].bitfield
.word
1519 && !t
->operand_types
[j
].bitfield
.word
)
1520 || (i
.types
[j
].bitfield
.dword
1521 && !t
->operand_types
[j
].bitfield
.dword
)
1522 || (i
.types
[j
].bitfield
.qword
1523 && !t
->operand_types
[j
].bitfield
.qword
));
1526 /* Return 1 if there is no conflict in any size on operand J for
1527 instruction template T. */
1530 match_mem_size (const insn_template
*t
, unsigned int j
)
1532 return (match_reg_size (t
, j
)
1533 && !((i
.types
[j
].bitfield
.unspecified
1534 && !t
->operand_types
[j
].bitfield
.unspecified
)
1535 || (i
.types
[j
].bitfield
.fword
1536 && !t
->operand_types
[j
].bitfield
.fword
)
1537 || (i
.types
[j
].bitfield
.tbyte
1538 && !t
->operand_types
[j
].bitfield
.tbyte
)
1539 || (i
.types
[j
].bitfield
.xmmword
1540 && !t
->operand_types
[j
].bitfield
.xmmword
)
1541 || (i
.types
[j
].bitfield
.ymmword
1542 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1545 /* Return 1 if there is no size conflict on any operands for
1546 instruction template T. */
1549 operand_size_match (const insn_template
*t
)
1554 /* Don't check jump instructions. */
1555 if (t
->opcode_modifier
.jump
1556 || t
->opcode_modifier
.jumpbyte
1557 || t
->opcode_modifier
.jumpdword
1558 || t
->opcode_modifier
.jumpintersegment
)
1561 /* Check memory and accumulator operand size. */
1562 for (j
= 0; j
< i
.operands
; j
++)
1564 if (t
->operand_types
[j
].bitfield
.anysize
)
1567 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1573 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1582 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1585 i
.error
= operand_size_mismatch
;
1589 /* Check reverse. */
1590 gas_assert (i
.operands
== 2);
1593 for (j
= 0; j
< 2; j
++)
1595 if (t
->operand_types
[j
].bitfield
.acc
1596 && !match_reg_size (t
, j
? 0 : 1))
1599 if (i
.types
[j
].bitfield
.mem
1600 && !match_mem_size (t
, j
? 0 : 1))
1608 operand_type_match (i386_operand_type overlap
,
1609 i386_operand_type given
)
1611 i386_operand_type temp
= overlap
;
1613 temp
.bitfield
.jumpabsolute
= 0;
1614 temp
.bitfield
.unspecified
= 0;
1615 temp
.bitfield
.byte
= 0;
1616 temp
.bitfield
.word
= 0;
1617 temp
.bitfield
.dword
= 0;
1618 temp
.bitfield
.fword
= 0;
1619 temp
.bitfield
.qword
= 0;
1620 temp
.bitfield
.tbyte
= 0;
1621 temp
.bitfield
.xmmword
= 0;
1622 temp
.bitfield
.ymmword
= 0;
1623 if (operand_type_all_zero (&temp
))
1626 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1627 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1631 i
.error
= operand_type_mismatch
;
1635 /* If given types g0 and g1 are registers they must be of the same type
1636 unless the expected operand type register overlap is null.
1637 Note that Acc in a template matches every size of reg. */
1640 operand_type_register_match (i386_operand_type m0
,
1641 i386_operand_type g0
,
1642 i386_operand_type t0
,
1643 i386_operand_type m1
,
1644 i386_operand_type g1
,
1645 i386_operand_type t1
)
1647 if (!operand_type_check (g0
, reg
))
1650 if (!operand_type_check (g1
, reg
))
1653 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1654 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1655 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1656 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1659 if (m0
.bitfield
.acc
)
1661 t0
.bitfield
.reg8
= 1;
1662 t0
.bitfield
.reg16
= 1;
1663 t0
.bitfield
.reg32
= 1;
1664 t0
.bitfield
.reg64
= 1;
1667 if (m1
.bitfield
.acc
)
1669 t1
.bitfield
.reg8
= 1;
1670 t1
.bitfield
.reg16
= 1;
1671 t1
.bitfield
.reg32
= 1;
1672 t1
.bitfield
.reg64
= 1;
1675 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1676 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1677 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1678 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1681 i
.error
= register_type_mismatch
;
1686 static INLINE
unsigned int
1687 mode_from_disp_size (i386_operand_type t
)
1689 if (t
.bitfield
.disp8
)
1691 else if (t
.bitfield
.disp16
1692 || t
.bitfield
.disp32
1693 || t
.bitfield
.disp32s
)
1700 fits_in_signed_byte (offsetT num
)
1702 return (num
>= -128) && (num
<= 127);
1706 fits_in_unsigned_byte (offsetT num
)
1708 return (num
& 0xff) == num
;
1712 fits_in_unsigned_word (offsetT num
)
1714 return (num
& 0xffff) == num
;
1718 fits_in_signed_word (offsetT num
)
1720 return (-32768 <= num
) && (num
<= 32767);
1724 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1729 return (!(((offsetT
) -1 << 31) & num
)
1730 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1732 } /* fits_in_signed_long() */
1735 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1740 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1742 } /* fits_in_unsigned_long() */
1745 fits_in_imm4 (offsetT num
)
1747 return (num
& 0xf) == num
;
1750 static i386_operand_type
1751 smallest_imm_type (offsetT num
)
1753 i386_operand_type t
;
1755 operand_type_set (&t
, 0);
1756 t
.bitfield
.imm64
= 1;
1758 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1760 /* This code is disabled on the 486 because all the Imm1 forms
1761 in the opcode table are slower on the i486. They're the
1762 versions with the implicitly specified single-position
1763 displacement, which has another syntax if you really want to
1765 t
.bitfield
.imm1
= 1;
1766 t
.bitfield
.imm8
= 1;
1767 t
.bitfield
.imm8s
= 1;
1768 t
.bitfield
.imm16
= 1;
1769 t
.bitfield
.imm32
= 1;
1770 t
.bitfield
.imm32s
= 1;
1772 else if (fits_in_signed_byte (num
))
1774 t
.bitfield
.imm8
= 1;
1775 t
.bitfield
.imm8s
= 1;
1776 t
.bitfield
.imm16
= 1;
1777 t
.bitfield
.imm32
= 1;
1778 t
.bitfield
.imm32s
= 1;
1780 else if (fits_in_unsigned_byte (num
))
1782 t
.bitfield
.imm8
= 1;
1783 t
.bitfield
.imm16
= 1;
1784 t
.bitfield
.imm32
= 1;
1785 t
.bitfield
.imm32s
= 1;
1787 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1789 t
.bitfield
.imm16
= 1;
1790 t
.bitfield
.imm32
= 1;
1791 t
.bitfield
.imm32s
= 1;
1793 else if (fits_in_signed_long (num
))
1795 t
.bitfield
.imm32
= 1;
1796 t
.bitfield
.imm32s
= 1;
1798 else if (fits_in_unsigned_long (num
))
1799 t
.bitfield
.imm32
= 1;
1805 offset_in_range (offsetT val
, int size
)
1811 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1812 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1813 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1815 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1821 /* If BFD64, sign extend val for 32bit address mode. */
1822 if (flag_code
!= CODE_64BIT
1823 || i
.prefix
[ADDR_PREFIX
])
1824 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1825 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1828 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1830 char buf1
[40], buf2
[40];
1832 sprint_value (buf1
, val
);
1833 sprint_value (buf2
, val
& mask
);
1834 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1848 a. PREFIX_EXIST if attempting to add a prefix where one from the
1849 same class already exists.
1850 b. PREFIX_LOCK if lock prefix is added.
1851 c. PREFIX_REP if rep/repne prefix is added.
1852 d. PREFIX_OTHER if other prefix is added.
1855 static enum PREFIX_GROUP
1856 add_prefix (unsigned int prefix
)
1858 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1861 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1862 && flag_code
== CODE_64BIT
)
1864 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1865 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1866 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1877 case CS_PREFIX_OPCODE
:
1878 case DS_PREFIX_OPCODE
:
1879 case ES_PREFIX_OPCODE
:
1880 case FS_PREFIX_OPCODE
:
1881 case GS_PREFIX_OPCODE
:
1882 case SS_PREFIX_OPCODE
:
1886 case REPNE_PREFIX_OPCODE
:
1887 case REPE_PREFIX_OPCODE
:
1892 case LOCK_PREFIX_OPCODE
:
1901 case ADDR_PREFIX_OPCODE
:
1905 case DATA_PREFIX_OPCODE
:
1909 if (i
.prefix
[q
] != 0)
1917 i
.prefix
[q
] |= prefix
;
1920 as_bad (_("same type of prefix used twice"));
1926 update_code_flag (int value
, int check
)
1928 PRINTF_LIKE ((*as_error
));
1930 flag_code
= (enum flag_code
) value
;
1931 if (flag_code
== CODE_64BIT
)
1933 cpu_arch_flags
.bitfield
.cpu64
= 1;
1934 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1938 cpu_arch_flags
.bitfield
.cpu64
= 0;
1939 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1941 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1944 as_error
= as_fatal
;
1947 (*as_error
) (_("64bit mode not supported on `%s'."),
1948 cpu_arch_name
? cpu_arch_name
: default_arch
);
1950 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1953 as_error
= as_fatal
;
1956 (*as_error
) (_("32bit mode not supported on `%s'."),
1957 cpu_arch_name
? cpu_arch_name
: default_arch
);
1959 stackop_size
= '\0';
1963 set_code_flag (int value
)
1965 update_code_flag (value
, 0);
1969 set_16bit_gcc_code_flag (int new_code_flag
)
1971 flag_code
= (enum flag_code
) new_code_flag
;
1972 if (flag_code
!= CODE_16BIT
)
1974 cpu_arch_flags
.bitfield
.cpu64
= 0;
1975 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1976 stackop_size
= LONG_MNEM_SUFFIX
;
1980 set_intel_syntax (int syntax_flag
)
1982 /* Find out if register prefixing is specified. */
1983 int ask_naked_reg
= 0;
1986 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1988 char *string
= input_line_pointer
;
1989 int e
= get_symbol_end ();
1991 if (strcmp (string
, "prefix") == 0)
1993 else if (strcmp (string
, "noprefix") == 0)
1996 as_bad (_("bad argument to syntax directive."));
1997 *input_line_pointer
= e
;
1999 demand_empty_rest_of_line ();
2001 intel_syntax
= syntax_flag
;
2003 if (ask_naked_reg
== 0)
2004 allow_naked_reg
= (intel_syntax
2005 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2007 allow_naked_reg
= (ask_naked_reg
< 0);
2009 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2011 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2012 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2013 register_prefix
= allow_naked_reg
? "" : "%";
2017 set_intel_mnemonic (int mnemonic_flag
)
2019 intel_mnemonic
= mnemonic_flag
;
2023 set_allow_index_reg (int flag
)
2025 allow_index_reg
= flag
;
2029 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2033 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2035 char *string
= input_line_pointer
;
2036 int e
= get_symbol_end ();
2038 if (strcmp (string
, "none") == 0)
2039 sse_check
= sse_check_none
;
2040 else if (strcmp (string
, "warning") == 0)
2041 sse_check
= sse_check_warning
;
2042 else if (strcmp (string
, "error") == 0)
2043 sse_check
= sse_check_error
;
2045 as_bad (_("bad argument to sse_check directive."));
2046 *input_line_pointer
= e
;
2049 as_bad (_("missing argument for sse_check directive"));
2051 demand_empty_rest_of_line ();
2055 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2056 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2058 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2059 static const char *arch
;
2061 /* Intel LIOM is only supported on ELF. */
2067 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2068 use default_arch. */
2069 arch
= cpu_arch_name
;
2071 arch
= default_arch
;
2074 /* If we are targeting Intel L1OM, we must enable it. */
2075 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2076 || new_flag
.bitfield
.cpul1om
)
2079 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2084 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2088 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2090 char *string
= input_line_pointer
;
2091 int e
= get_symbol_end ();
2093 i386_cpu_flags flags
;
2095 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2097 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2099 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2103 cpu_arch_name
= cpu_arch
[j
].name
;
2104 cpu_sub_arch_name
= NULL
;
2105 cpu_arch_flags
= cpu_arch
[j
].flags
;
2106 if (flag_code
== CODE_64BIT
)
2108 cpu_arch_flags
.bitfield
.cpu64
= 1;
2109 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2113 cpu_arch_flags
.bitfield
.cpu64
= 0;
2114 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2116 cpu_arch_isa
= cpu_arch
[j
].type
;
2117 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2118 if (!cpu_arch_tune_set
)
2120 cpu_arch_tune
= cpu_arch_isa
;
2121 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2126 if (strncmp (string
+ 1, "no", 2))
2127 flags
= cpu_flags_or (cpu_arch_flags
,
2130 flags
= cpu_flags_and_not (cpu_arch_flags
,
2132 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2134 if (cpu_sub_arch_name
)
2136 char *name
= cpu_sub_arch_name
;
2137 cpu_sub_arch_name
= concat (name
,
2139 (const char *) NULL
);
2143 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2144 cpu_arch_flags
= flags
;
2146 *input_line_pointer
= e
;
2147 demand_empty_rest_of_line ();
2151 if (j
>= ARRAY_SIZE (cpu_arch
))
2152 as_bad (_("no such architecture: `%s'"), string
);
2154 *input_line_pointer
= e
;
2157 as_bad (_("missing cpu architecture"));
2159 no_cond_jump_promotion
= 0;
2160 if (*input_line_pointer
== ','
2161 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2163 char *string
= ++input_line_pointer
;
2164 int e
= get_symbol_end ();
2166 if (strcmp (string
, "nojumps") == 0)
2167 no_cond_jump_promotion
= 1;
2168 else if (strcmp (string
, "jumps") == 0)
2171 as_bad (_("no such architecture modifier: `%s'"), string
);
2173 *input_line_pointer
= e
;
2176 demand_empty_rest_of_line ();
2179 enum bfd_architecture
2182 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2184 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2185 || flag_code
!= CODE_64BIT
)
2186 as_fatal (_("Intel L1OM is 64bit ELF only"));
2187 return bfd_arch_l1om
;
2190 return bfd_arch_i386
;
2196 if (!strcmp (default_arch
, "x86_64"))
2198 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2200 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2201 as_fatal (_("Intel L1OM is 64bit ELF only"));
2202 return bfd_mach_l1om
;
2205 return bfd_mach_x86_64
;
2207 else if (!strcmp (default_arch
, "i386"))
2208 return bfd_mach_i386_i386
;
2210 as_fatal (_("Unknown architecture"));
2216 const char *hash_err
;
2218 /* Initialize op_hash hash table. */
2219 op_hash
= hash_new ();
2222 const insn_template
*optab
;
2223 templates
*core_optab
;
2225 /* Setup for loop. */
2227 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2228 core_optab
->start
= optab
;
2233 if (optab
->name
== NULL
2234 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2236 /* different name --> ship out current template list;
2237 add to hash table; & begin anew. */
2238 core_optab
->end
= optab
;
2239 hash_err
= hash_insert (op_hash
,
2241 (void *) core_optab
);
2244 as_fatal (_("Internal Error: Can't hash %s: %s"),
2248 if (optab
->name
== NULL
)
2250 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2251 core_optab
->start
= optab
;
2256 /* Initialize reg_hash hash table. */
2257 reg_hash
= hash_new ();
2259 const reg_entry
*regtab
;
2260 unsigned int regtab_size
= i386_regtab_size
;
2262 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2264 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2266 as_fatal (_("Internal Error: Can't hash %s: %s"),
2272 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2277 for (c
= 0; c
< 256; c
++)
2282 mnemonic_chars
[c
] = c
;
2283 register_chars
[c
] = c
;
2284 operand_chars
[c
] = c
;
2286 else if (ISLOWER (c
))
2288 mnemonic_chars
[c
] = c
;
2289 register_chars
[c
] = c
;
2290 operand_chars
[c
] = c
;
2292 else if (ISUPPER (c
))
2294 mnemonic_chars
[c
] = TOLOWER (c
);
2295 register_chars
[c
] = mnemonic_chars
[c
];
2296 operand_chars
[c
] = c
;
2299 if (ISALPHA (c
) || ISDIGIT (c
))
2300 identifier_chars
[c
] = c
;
2303 identifier_chars
[c
] = c
;
2304 operand_chars
[c
] = c
;
2309 identifier_chars
['@'] = '@';
2312 identifier_chars
['?'] = '?';
2313 operand_chars
['?'] = '?';
2315 digit_chars
['-'] = '-';
2316 mnemonic_chars
['_'] = '_';
2317 mnemonic_chars
['-'] = '-';
2318 mnemonic_chars
['.'] = '.';
2319 identifier_chars
['_'] = '_';
2320 identifier_chars
['.'] = '.';
2322 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2323 operand_chars
[(unsigned char) *p
] = *p
;
2326 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2329 record_alignment (text_section
, 2);
2330 record_alignment (data_section
, 2);
2331 record_alignment (bss_section
, 2);
2335 if (flag_code
== CODE_64BIT
)
2337 x86_dwarf2_return_column
= 16;
2338 x86_cie_data_alignment
= -8;
2342 x86_dwarf2_return_column
= 8;
2343 x86_cie_data_alignment
= -4;
2348 i386_print_statistics (FILE *file
)
2350 hash_print_statistics (file
, "i386 opcode", op_hash
);
2351 hash_print_statistics (file
, "i386 register", reg_hash
);
2356 /* Debugging routines for md_assemble. */
2357 static void pte (insn_template
*);
2358 static void pt (i386_operand_type
);
2359 static void pe (expressionS
*);
2360 static void ps (symbolS
*);
2363 pi (char *line
, i386_insn
*x
)
2367 fprintf (stdout
, "%s: template ", line
);
2369 fprintf (stdout
, " address: base %s index %s scale %x\n",
2370 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2371 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2372 x
->log2_scale_factor
);
2373 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2374 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2375 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2376 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2377 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2378 (x
->rex
& REX_W
) != 0,
2379 (x
->rex
& REX_R
) != 0,
2380 (x
->rex
& REX_X
) != 0,
2381 (x
->rex
& REX_B
) != 0);
2382 for (j
= 0; j
< x
->operands
; j
++)
2384 fprintf (stdout
, " #%d: ", j
+ 1);
2386 fprintf (stdout
, "\n");
2387 if (x
->types
[j
].bitfield
.reg8
2388 || x
->types
[j
].bitfield
.reg16
2389 || x
->types
[j
].bitfield
.reg32
2390 || x
->types
[j
].bitfield
.reg64
2391 || x
->types
[j
].bitfield
.regmmx
2392 || x
->types
[j
].bitfield
.regxmm
2393 || x
->types
[j
].bitfield
.regymm
2394 || x
->types
[j
].bitfield
.sreg2
2395 || x
->types
[j
].bitfield
.sreg3
2396 || x
->types
[j
].bitfield
.control
2397 || x
->types
[j
].bitfield
.debug
2398 || x
->types
[j
].bitfield
.test
)
2399 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2400 if (operand_type_check (x
->types
[j
], imm
))
2402 if (operand_type_check (x
->types
[j
], disp
))
2403 pe (x
->op
[j
].disps
);
2408 pte (insn_template
*t
)
2411 fprintf (stdout
, " %d operands ", t
->operands
);
2412 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2413 if (t
->extension_opcode
!= None
)
2414 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2415 if (t
->opcode_modifier
.d
)
2416 fprintf (stdout
, "D");
2417 if (t
->opcode_modifier
.w
)
2418 fprintf (stdout
, "W");
2419 fprintf (stdout
, "\n");
2420 for (j
= 0; j
< t
->operands
; j
++)
2422 fprintf (stdout
, " #%d type ", j
+ 1);
2423 pt (t
->operand_types
[j
]);
2424 fprintf (stdout
, "\n");
2431 fprintf (stdout
, " operation %d\n", e
->X_op
);
2432 fprintf (stdout
, " add_number %ld (%lx)\n",
2433 (long) e
->X_add_number
, (long) e
->X_add_number
);
2434 if (e
->X_add_symbol
)
2436 fprintf (stdout
, " add_symbol ");
2437 ps (e
->X_add_symbol
);
2438 fprintf (stdout
, "\n");
2442 fprintf (stdout
, " op_symbol ");
2443 ps (e
->X_op_symbol
);
2444 fprintf (stdout
, "\n");
2451 fprintf (stdout
, "%s type %s%s",
2453 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2454 segment_name (S_GET_SEGMENT (s
)));
2457 static struct type_name
2459 i386_operand_type mask
;
2462 const type_names
[] =
2464 { OPERAND_TYPE_REG8
, "r8" },
2465 { OPERAND_TYPE_REG16
, "r16" },
2466 { OPERAND_TYPE_REG32
, "r32" },
2467 { OPERAND_TYPE_REG64
, "r64" },
2468 { OPERAND_TYPE_IMM8
, "i8" },
2469 { OPERAND_TYPE_IMM8
, "i8s" },
2470 { OPERAND_TYPE_IMM16
, "i16" },
2471 { OPERAND_TYPE_IMM32
, "i32" },
2472 { OPERAND_TYPE_IMM32S
, "i32s" },
2473 { OPERAND_TYPE_IMM64
, "i64" },
2474 { OPERAND_TYPE_IMM1
, "i1" },
2475 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2476 { OPERAND_TYPE_DISP8
, "d8" },
2477 { OPERAND_TYPE_DISP16
, "d16" },
2478 { OPERAND_TYPE_DISP32
, "d32" },
2479 { OPERAND_TYPE_DISP32S
, "d32s" },
2480 { OPERAND_TYPE_DISP64
, "d64" },
2481 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2482 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2483 { OPERAND_TYPE_CONTROL
, "control reg" },
2484 { OPERAND_TYPE_TEST
, "test reg" },
2485 { OPERAND_TYPE_DEBUG
, "debug reg" },
2486 { OPERAND_TYPE_FLOATREG
, "FReg" },
2487 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2488 { OPERAND_TYPE_SREG2
, "SReg2" },
2489 { OPERAND_TYPE_SREG3
, "SReg3" },
2490 { OPERAND_TYPE_ACC
, "Acc" },
2491 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2492 { OPERAND_TYPE_REGMMX
, "rMMX" },
2493 { OPERAND_TYPE_REGXMM
, "rXMM" },
2494 { OPERAND_TYPE_REGYMM
, "rYMM" },
2495 { OPERAND_TYPE_ESSEG
, "es" },
2499 pt (i386_operand_type t
)
2502 i386_operand_type a
;
2504 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2506 a
= operand_type_and (t
, type_names
[j
].mask
);
2507 if (!operand_type_all_zero (&a
))
2508 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2513 #endif /* DEBUG386 */
2515 static bfd_reloc_code_real_type
2516 reloc (unsigned int size
,
2519 bfd_reloc_code_real_type other
)
2521 if (other
!= NO_RELOC
)
2523 reloc_howto_type
*rel
;
2528 case BFD_RELOC_X86_64_GOT32
:
2529 return BFD_RELOC_X86_64_GOT64
;
2531 case BFD_RELOC_X86_64_PLTOFF64
:
2532 return BFD_RELOC_X86_64_PLTOFF64
;
2534 case BFD_RELOC_X86_64_GOTPC32
:
2535 other
= BFD_RELOC_X86_64_GOTPC64
;
2537 case BFD_RELOC_X86_64_GOTPCREL
:
2538 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2540 case BFD_RELOC_X86_64_TPOFF32
:
2541 other
= BFD_RELOC_X86_64_TPOFF64
;
2543 case BFD_RELOC_X86_64_DTPOFF32
:
2544 other
= BFD_RELOC_X86_64_DTPOFF64
;
2550 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2551 if (size
== 4 && flag_code
!= CODE_64BIT
)
2554 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2556 as_bad (_("unknown relocation (%u)"), other
);
2557 else if (size
!= bfd_get_reloc_size (rel
))
2558 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2559 bfd_get_reloc_size (rel
),
2561 else if (pcrel
&& !rel
->pc_relative
)
2562 as_bad (_("non-pc-relative relocation for pc-relative field"));
2563 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2565 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2567 as_bad (_("relocated field and relocation type differ in signedness"));
2576 as_bad (_("there are no unsigned pc-relative relocations"));
2579 case 1: return BFD_RELOC_8_PCREL
;
2580 case 2: return BFD_RELOC_16_PCREL
;
2581 case 4: return BFD_RELOC_32_PCREL
;
2582 case 8: return BFD_RELOC_64_PCREL
;
2584 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2591 case 4: return BFD_RELOC_X86_64_32S
;
2596 case 1: return BFD_RELOC_8
;
2597 case 2: return BFD_RELOC_16
;
2598 case 4: return BFD_RELOC_32
;
2599 case 8: return BFD_RELOC_64
;
2601 as_bad (_("cannot do %s %u byte relocation"),
2602 sign
> 0 ? "signed" : "unsigned", size
);
2608 /* Here we decide which fixups can be adjusted to make them relative to
2609 the beginning of the section instead of the symbol. Basically we need
2610 to make sure that the dynamic relocations are done correctly, so in
2611 some cases we force the original symbol to be used. */
2614 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2616 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2620 /* Don't adjust pc-relative references to merge sections in 64-bit
2622 if (use_rela_relocations
2623 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2627 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2628 and changed later by validate_fix. */
2629 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2630 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2633 /* adjust_reloc_syms doesn't know about the GOT. */
2634 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2635 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2636 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2637 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2638 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2639 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2640 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2641 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2642 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2643 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2644 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2645 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2646 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2647 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2648 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2649 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2650 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2651 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2652 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2653 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2654 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2655 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2656 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2657 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2658 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2659 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2660 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2661 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2668 intel_float_operand (const char *mnemonic
)
2670 /* Note that the value returned is meaningful only for opcodes with (memory)
2671 operands, hence the code here is free to improperly handle opcodes that
2672 have no operands (for better performance and smaller code). */
2674 if (mnemonic
[0] != 'f')
2675 return 0; /* non-math */
2677 switch (mnemonic
[1])
2679 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2680 the fs segment override prefix not currently handled because no
2681 call path can make opcodes without operands get here */
2683 return 2 /* integer op */;
2685 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2686 return 3; /* fldcw/fldenv */
2689 if (mnemonic
[2] != 'o' /* fnop */)
2690 return 3; /* non-waiting control op */
2693 if (mnemonic
[2] == 's')
2694 return 3; /* frstor/frstpm */
2697 if (mnemonic
[2] == 'a')
2698 return 3; /* fsave */
2699 if (mnemonic
[2] == 't')
2701 switch (mnemonic
[3])
2703 case 'c': /* fstcw */
2704 case 'd': /* fstdw */
2705 case 'e': /* fstenv */
2706 case 's': /* fsts[gw] */
2712 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2713 return 0; /* fxsave/fxrstor are not really math ops */
2720 /* Build the VEX prefix. */
2723 build_vex_prefix (const insn_template
*t
)
2725 unsigned int register_specifier
;
2726 unsigned int implied_prefix
;
2727 unsigned int vector_length
;
2729 /* Check register specifier. */
2730 if (i
.vex
.register_specifier
)
2732 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2733 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2734 register_specifier
+= 8;
2735 register_specifier
= ~register_specifier
& 0xf;
2738 register_specifier
= 0xf;
2740 /* Use 2-byte VEX prefix by swappping destination and source
2743 && i
.operands
== i
.reg_operands
2744 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2745 && i
.tm
.opcode_modifier
.s
2748 unsigned int xchg
= i
.operands
- 1;
2749 union i386_op temp_op
;
2750 i386_operand_type temp_type
;
2752 temp_type
= i
.types
[xchg
];
2753 i
.types
[xchg
] = i
.types
[0];
2754 i
.types
[0] = temp_type
;
2755 temp_op
= i
.op
[xchg
];
2756 i
.op
[xchg
] = i
.op
[0];
2759 gas_assert (i
.rm
.mode
== 3);
2763 i
.rm
.regmem
= i
.rm
.reg
;
2766 /* Use the next insn. */
2770 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2771 vector_length
= avxscalar
;
2773 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2775 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2780 case DATA_PREFIX_OPCODE
:
2783 case REPE_PREFIX_OPCODE
:
2786 case REPNE_PREFIX_OPCODE
:
2793 /* Use 2-byte VEX prefix if possible. */
2794 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2795 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2797 /* 2-byte VEX prefix. */
2801 i
.vex
.bytes
[0] = 0xc5;
2803 /* Check the REX.R bit. */
2804 r
= (i
.rex
& REX_R
) ? 0 : 1;
2805 i
.vex
.bytes
[1] = (r
<< 7
2806 | register_specifier
<< 3
2807 | vector_length
<< 2
2812 /* 3-byte VEX prefix. */
2817 switch (i
.tm
.opcode_modifier
.vexopcode
)
2821 i
.vex
.bytes
[0] = 0xc4;
2825 i
.vex
.bytes
[0] = 0xc4;
2829 i
.vex
.bytes
[0] = 0xc4;
2833 i
.vex
.bytes
[0] = 0x8f;
2837 i
.vex
.bytes
[0] = 0x8f;
2841 i
.vex
.bytes
[0] = 0x8f;
2847 /* The high 3 bits of the second VEX byte are 1's compliment
2848 of RXB bits from REX. */
2849 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2851 /* Check the REX.W bit. */
2852 w
= (i
.rex
& REX_W
) ? 1 : 0;
2853 if (i
.tm
.opcode_modifier
.vexw
)
2858 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2862 i
.vex
.bytes
[2] = (w
<< 7
2863 | register_specifier
<< 3
2864 | vector_length
<< 2
2870 process_immext (void)
2874 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2876 /* SSE3 Instructions have the fixed operands with an opcode
2877 suffix which is coded in the same place as an 8-bit immediate
2878 field would be. Here we check those operands and remove them
2882 for (x
= 0; x
< i
.operands
; x
++)
2883 if (i
.op
[x
].regs
->reg_num
!= x
)
2884 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2885 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2891 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2892 which is coded in the same place as an 8-bit immediate field
2893 would be. Here we fake an 8-bit immediate operand from the
2894 opcode suffix stored in tm.extension_opcode.
2896 AVX instructions also use this encoding, for some of
2897 3 argument instructions. */
2899 gas_assert (i
.imm_operands
== 0
2901 || (i
.tm
.opcode_modifier
.vex
2902 && i
.operands
<= 4)));
2904 exp
= &im_expressions
[i
.imm_operands
++];
2905 i
.op
[i
.operands
].imms
= exp
;
2906 i
.types
[i
.operands
] = imm8
;
2908 exp
->X_op
= O_constant
;
2909 exp
->X_add_number
= i
.tm
.extension_opcode
;
2910 i
.tm
.extension_opcode
= None
;
2913 /* This is the guts of the machine-dependent assembler. LINE points to a
2914 machine dependent instruction. This function is supposed to emit
2915 the frags/bytes it assembles to. */
2918 md_assemble (char *line
)
2921 char mnemonic
[MAX_MNEM_SIZE
];
2922 const insn_template
*t
;
2924 /* Initialize globals. */
2925 memset (&i
, '\0', sizeof (i
));
2926 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2927 i
.reloc
[j
] = NO_RELOC
;
2928 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2929 memset (im_expressions
, '\0', sizeof (im_expressions
));
2930 save_stack_p
= save_stack
;
2932 /* First parse an instruction mnemonic & call i386_operand for the operands.
2933 We assume that the scrubber has arranged it so that line[0] is the valid
2934 start of a (possibly prefixed) mnemonic. */
2936 line
= parse_insn (line
, mnemonic
);
2940 line
= parse_operands (line
, mnemonic
);
2945 /* Now we've parsed the mnemonic into a set of templates, and have the
2946 operands at hand. */
2948 /* All intel opcodes have reversed operands except for "bound" and
2949 "enter". We also don't reverse intersegment "jmp" and "call"
2950 instructions with 2 immediate operands so that the immediate segment
2951 precedes the offset, as it does when in AT&T mode. */
2954 && (strcmp (mnemonic
, "bound") != 0)
2955 && (strcmp (mnemonic
, "invlpga") != 0)
2956 && !(operand_type_check (i
.types
[0], imm
)
2957 && operand_type_check (i
.types
[1], imm
)))
2960 /* The order of the immediates should be reversed
2961 for 2 immediates extrq and insertq instructions */
2962 if (i
.imm_operands
== 2
2963 && (strcmp (mnemonic
, "extrq") == 0
2964 || strcmp (mnemonic
, "insertq") == 0))
2965 swap_2_operands (0, 1);
2970 /* Don't optimize displacement for movabs since it only takes 64bit
2973 && (flag_code
!= CODE_64BIT
2974 || strcmp (mnemonic
, "movabs") != 0))
2977 /* Next, we find a template that matches the given insn,
2978 making sure the overlap of the given operands types is consistent
2979 with the template operand types. */
2981 if (!(t
= match_template ()))
2984 if (sse_check
!= sse_check_none
2985 && !i
.tm
.opcode_modifier
.noavx
2986 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2987 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2988 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2989 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2990 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2991 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2993 (sse_check
== sse_check_warning
2995 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2998 /* Zap movzx and movsx suffix. The suffix has been set from
2999 "word ptr" or "byte ptr" on the source operand in Intel syntax
3000 or extracted from mnemonic in AT&T syntax. But we'll use
3001 the destination register to choose the suffix for encoding. */
3002 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3004 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3005 there is no suffix, the default will be byte extension. */
3006 if (i
.reg_operands
!= 2
3009 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3014 if (i
.tm
.opcode_modifier
.fwait
)
3015 if (!add_prefix (FWAIT_OPCODE
))
3018 /* Check for lock without a lockable instruction. Destination operand
3019 must be memory unless it is xchg (0x86). */
3020 if (i
.prefix
[LOCK_PREFIX
]
3021 && (!i
.tm
.opcode_modifier
.islockable
3022 || i
.mem_operands
== 0
3023 || (i
.tm
.base_opcode
!= 0x86
3024 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3026 as_bad (_("expecting lockable instruction after `lock'"));
3030 /* Check string instruction segment overrides. */
3031 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3033 if (!check_string ())
3035 i
.disp_operands
= 0;
3038 if (!process_suffix ())
3041 /* Update operand types. */
3042 for (j
= 0; j
< i
.operands
; j
++)
3043 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3045 /* Make still unresolved immediate matches conform to size of immediate
3046 given in i.suffix. */
3047 if (!finalize_imm ())
3050 if (i
.types
[0].bitfield
.imm1
)
3051 i
.imm_operands
= 0; /* kludge for shift insns. */
3053 /* We only need to check those implicit registers for instructions
3054 with 3 operands or less. */
3055 if (i
.operands
<= 3)
3056 for (j
= 0; j
< i
.operands
; j
++)
3057 if (i
.types
[j
].bitfield
.inoutportreg
3058 || i
.types
[j
].bitfield
.shiftcount
3059 || i
.types
[j
].bitfield
.acc
3060 || i
.types
[j
].bitfield
.floatacc
)
3063 /* ImmExt should be processed after SSE2AVX. */
3064 if (!i
.tm
.opcode_modifier
.sse2avx
3065 && i
.tm
.opcode_modifier
.immext
)
3068 /* For insns with operands there are more diddles to do to the opcode. */
3071 if (!process_operands ())
3074 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3076 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3077 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3080 if (i
.tm
.opcode_modifier
.vex
)
3081 build_vex_prefix (t
);
3083 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3084 instructions may define INT_OPCODE as well, so avoid this corner
3085 case for those instructions that use MODRM. */
3086 if (i
.tm
.base_opcode
== INT_OPCODE
3087 && !i
.tm
.opcode_modifier
.modrm
3088 && i
.op
[0].imms
->X_add_number
== 3)
3090 i
.tm
.base_opcode
= INT3_OPCODE
;
3094 if ((i
.tm
.opcode_modifier
.jump
3095 || i
.tm
.opcode_modifier
.jumpbyte
3096 || i
.tm
.opcode_modifier
.jumpdword
)
3097 && i
.op
[0].disps
->X_op
== O_constant
)
3099 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3100 the absolute address given by the constant. Since ix86 jumps and
3101 calls are pc relative, we need to generate a reloc. */
3102 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3103 i
.op
[0].disps
->X_op
= O_symbol
;
3106 if (i
.tm
.opcode_modifier
.rex64
)
3109 /* For 8 bit registers we need an empty rex prefix. Also if the
3110 instruction already has a prefix, we need to convert old
3111 registers to new ones. */
3113 if ((i
.types
[0].bitfield
.reg8
3114 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3115 || (i
.types
[1].bitfield
.reg8
3116 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3117 || ((i
.types
[0].bitfield
.reg8
3118 || i
.types
[1].bitfield
.reg8
)
3123 i
.rex
|= REX_OPCODE
;
3124 for (x
= 0; x
< 2; x
++)
3126 /* Look for 8 bit operand that uses old registers. */
3127 if (i
.types
[x
].bitfield
.reg8
3128 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3130 /* In case it is "hi" register, give up. */
3131 if (i
.op
[x
].regs
->reg_num
> 3)
3132 as_bad (_("can't encode register '%s%s' in an "
3133 "instruction requiring REX prefix."),
3134 register_prefix
, i
.op
[x
].regs
->reg_name
);
3136 /* Otherwise it is equivalent to the extended register.
3137 Since the encoding doesn't change this is merely
3138 cosmetic cleanup for debug output. */
3140 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3146 add_prefix (REX_OPCODE
| i
.rex
);
3148 /* We are ready to output the insn. */
3153 parse_insn (char *line
, char *mnemonic
)
3156 char *token_start
= l
;
3159 const insn_template
*t
;
3162 /* Non-zero if we found a prefix only acceptable with string insns. */
3163 const char *expecting_string_instruction
= NULL
;
3168 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3173 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3175 as_bad (_("no such instruction: `%s'"), token_start
);
3180 if (!is_space_char (*l
)
3181 && *l
!= END_OF_INSN
3183 || (*l
!= PREFIX_SEPARATOR
3186 as_bad (_("invalid character %s in mnemonic"),
3187 output_invalid (*l
));
3190 if (token_start
== l
)
3192 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3193 as_bad (_("expecting prefix; got nothing"));
3195 as_bad (_("expecting mnemonic; got nothing"));
3199 /* Look up instruction (or prefix) via hash table. */
3200 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3202 if (*l
!= END_OF_INSN
3203 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3204 && current_templates
3205 && current_templates
->start
->opcode_modifier
.isprefix
)
3207 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3209 as_bad ((flag_code
!= CODE_64BIT
3210 ? _("`%s' is only supported in 64-bit mode")
3211 : _("`%s' is not supported in 64-bit mode")),
3212 current_templates
->start
->name
);
3215 /* If we are in 16-bit mode, do not allow addr16 or data16.
3216 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3217 if ((current_templates
->start
->opcode_modifier
.size16
3218 || current_templates
->start
->opcode_modifier
.size32
)
3219 && flag_code
!= CODE_64BIT
3220 && (current_templates
->start
->opcode_modifier
.size32
3221 ^ (flag_code
== CODE_16BIT
)))
3223 as_bad (_("redundant %s prefix"),
3224 current_templates
->start
->name
);
3227 /* Add prefix, checking for repeated prefixes. */
3228 switch (add_prefix (current_templates
->start
->base_opcode
))
3233 expecting_string_instruction
= current_templates
->start
->name
;
3238 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3245 if (!current_templates
)
3247 /* Check if we should swap operand in encoding. */
3248 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3254 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3257 if (!current_templates
)
3260 /* See if we can get a match by trimming off a suffix. */
3263 case WORD_MNEM_SUFFIX
:
3264 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3265 i
.suffix
= SHORT_MNEM_SUFFIX
;
3267 case BYTE_MNEM_SUFFIX
:
3268 case QWORD_MNEM_SUFFIX
:
3269 i
.suffix
= mnem_p
[-1];
3271 current_templates
= (const templates
*) hash_find (op_hash
,
3274 case SHORT_MNEM_SUFFIX
:
3275 case LONG_MNEM_SUFFIX
:
3278 i
.suffix
= mnem_p
[-1];
3280 current_templates
= (const templates
*) hash_find (op_hash
,
3289 if (intel_float_operand (mnemonic
) == 1)
3290 i
.suffix
= SHORT_MNEM_SUFFIX
;
3292 i
.suffix
= LONG_MNEM_SUFFIX
;
3294 current_templates
= (const templates
*) hash_find (op_hash
,
3299 if (!current_templates
)
3301 as_bad (_("no such instruction: `%s'"), token_start
);
3306 if (current_templates
->start
->opcode_modifier
.jump
3307 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3309 /* Check for a branch hint. We allow ",pt" and ",pn" for
3310 predict taken and predict not taken respectively.
3311 I'm not sure that branch hints actually do anything on loop
3312 and jcxz insns (JumpByte) for current Pentium4 chips. They
3313 may work in the future and it doesn't hurt to accept them
3315 if (l
[0] == ',' && l
[1] == 'p')
3319 if (!add_prefix (DS_PREFIX_OPCODE
))
3323 else if (l
[2] == 'n')
3325 if (!add_prefix (CS_PREFIX_OPCODE
))
3331 /* Any other comma loses. */
3334 as_bad (_("invalid character %s in mnemonic"),
3335 output_invalid (*l
));
3339 /* Check if instruction is supported on specified architecture. */
3341 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3343 supported
|= cpu_flags_match (t
);
3344 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3348 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3350 as_bad (flag_code
== CODE_64BIT
3351 ? _("`%s' is not supported in 64-bit mode")
3352 : _("`%s' is only supported in 64-bit mode"),
3353 current_templates
->start
->name
);
3356 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3358 as_bad (_("`%s' is not supported on `%s%s'"),
3359 current_templates
->start
->name
,
3360 cpu_arch_name
? cpu_arch_name
: default_arch
,
3361 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3366 if (!cpu_arch_flags
.bitfield
.cpui386
3367 && (flag_code
!= CODE_16BIT
))
3369 as_warn (_("use .code16 to ensure correct addressing mode"));
3372 /* Check for rep/repne without a string instruction. */
3373 if (expecting_string_instruction
)
3375 static templates override
;
3377 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3378 if (t
->opcode_modifier
.isstring
)
3380 if (t
>= current_templates
->end
)
3382 as_bad (_("expecting string instruction after `%s'"),
3383 expecting_string_instruction
);
3386 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3387 if (!t
->opcode_modifier
.isstring
)
3390 current_templates
= &override
;
3397 parse_operands (char *l
, const char *mnemonic
)
3401 /* 1 if operand is pending after ','. */
3402 unsigned int expecting_operand
= 0;
3404 /* Non-zero if operand parens not balanced. */
3405 unsigned int paren_not_balanced
;
3407 while (*l
!= END_OF_INSN
)
3409 /* Skip optional white space before operand. */
3410 if (is_space_char (*l
))
3412 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3414 as_bad (_("invalid character %s before operand %d"),
3415 output_invalid (*l
),
3419 token_start
= l
; /* after white space */
3420 paren_not_balanced
= 0;
3421 while (paren_not_balanced
|| *l
!= ',')
3423 if (*l
== END_OF_INSN
)
3425 if (paren_not_balanced
)
3428 as_bad (_("unbalanced parenthesis in operand %d."),
3431 as_bad (_("unbalanced brackets in operand %d."),
3436 break; /* we are done */
3438 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3440 as_bad (_("invalid character %s in operand %d"),
3441 output_invalid (*l
),
3448 ++paren_not_balanced
;
3450 --paren_not_balanced
;
3455 ++paren_not_balanced
;
3457 --paren_not_balanced
;
3461 if (l
!= token_start
)
3462 { /* Yes, we've read in another operand. */
3463 unsigned int operand_ok
;
3464 this_operand
= i
.operands
++;
3465 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3466 if (i
.operands
> MAX_OPERANDS
)
3468 as_bad (_("spurious operands; (%d operands/instruction max)"),
3472 /* Now parse operand adding info to 'i' as we go along. */
3473 END_STRING_AND_SAVE (l
);
3477 i386_intel_operand (token_start
,
3478 intel_float_operand (mnemonic
));
3480 operand_ok
= i386_att_operand (token_start
);
3482 RESTORE_END_STRING (l
);
3488 if (expecting_operand
)
3490 expecting_operand_after_comma
:
3491 as_bad (_("expecting operand after ','; got nothing"));
3496 as_bad (_("expecting operand before ','; got nothing"));
3501 /* Now *l must be either ',' or END_OF_INSN. */
3504 if (*++l
== END_OF_INSN
)
3506 /* Just skip it, if it's \n complain. */
3507 goto expecting_operand_after_comma
;
3509 expecting_operand
= 1;
3516 swap_2_operands (int xchg1
, int xchg2
)
3518 union i386_op temp_op
;
3519 i386_operand_type temp_type
;
3520 enum bfd_reloc_code_real temp_reloc
;
3522 temp_type
= i
.types
[xchg2
];
3523 i
.types
[xchg2
] = i
.types
[xchg1
];
3524 i
.types
[xchg1
] = temp_type
;
3525 temp_op
= i
.op
[xchg2
];
3526 i
.op
[xchg2
] = i
.op
[xchg1
];
3527 i
.op
[xchg1
] = temp_op
;
3528 temp_reloc
= i
.reloc
[xchg2
];
3529 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3530 i
.reloc
[xchg1
] = temp_reloc
;
3534 swap_operands (void)
3540 swap_2_operands (1, i
.operands
- 2);
3543 swap_2_operands (0, i
.operands
- 1);
3549 if (i
.mem_operands
== 2)
3551 const seg_entry
*temp_seg
;
3552 temp_seg
= i
.seg
[0];
3553 i
.seg
[0] = i
.seg
[1];
3554 i
.seg
[1] = temp_seg
;
3558 /* Try to ensure constant immediates are represented in the smallest
3563 char guess_suffix
= 0;
3567 guess_suffix
= i
.suffix
;
3568 else if (i
.reg_operands
)
3570 /* Figure out a suffix from the last register operand specified.
3571 We can't do this properly yet, ie. excluding InOutPortReg,
3572 but the following works for instructions with immediates.
3573 In any case, we can't set i.suffix yet. */
3574 for (op
= i
.operands
; --op
>= 0;)
3575 if (i
.types
[op
].bitfield
.reg8
)
3577 guess_suffix
= BYTE_MNEM_SUFFIX
;
3580 else if (i
.types
[op
].bitfield
.reg16
)
3582 guess_suffix
= WORD_MNEM_SUFFIX
;
3585 else if (i
.types
[op
].bitfield
.reg32
)
3587 guess_suffix
= LONG_MNEM_SUFFIX
;
3590 else if (i
.types
[op
].bitfield
.reg64
)
3592 guess_suffix
= QWORD_MNEM_SUFFIX
;
3596 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3597 guess_suffix
= WORD_MNEM_SUFFIX
;
3599 for (op
= i
.operands
; --op
>= 0;)
3600 if (operand_type_check (i
.types
[op
], imm
))
3602 switch (i
.op
[op
].imms
->X_op
)
3605 /* If a suffix is given, this operand may be shortened. */
3606 switch (guess_suffix
)
3608 case LONG_MNEM_SUFFIX
:
3609 i
.types
[op
].bitfield
.imm32
= 1;
3610 i
.types
[op
].bitfield
.imm64
= 1;
3612 case WORD_MNEM_SUFFIX
:
3613 i
.types
[op
].bitfield
.imm16
= 1;
3614 i
.types
[op
].bitfield
.imm32
= 1;
3615 i
.types
[op
].bitfield
.imm32s
= 1;
3616 i
.types
[op
].bitfield
.imm64
= 1;
3618 case BYTE_MNEM_SUFFIX
:
3619 i
.types
[op
].bitfield
.imm8
= 1;
3620 i
.types
[op
].bitfield
.imm8s
= 1;
3621 i
.types
[op
].bitfield
.imm16
= 1;
3622 i
.types
[op
].bitfield
.imm32
= 1;
3623 i
.types
[op
].bitfield
.imm32s
= 1;
3624 i
.types
[op
].bitfield
.imm64
= 1;
3628 /* If this operand is at most 16 bits, convert it
3629 to a signed 16 bit number before trying to see
3630 whether it will fit in an even smaller size.
3631 This allows a 16-bit operand such as $0xffe0 to
3632 be recognised as within Imm8S range. */
3633 if ((i
.types
[op
].bitfield
.imm16
)
3634 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3636 i
.op
[op
].imms
->X_add_number
=
3637 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3639 if ((i
.types
[op
].bitfield
.imm32
)
3640 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3643 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3644 ^ ((offsetT
) 1 << 31))
3645 - ((offsetT
) 1 << 31));
3648 = operand_type_or (i
.types
[op
],
3649 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3651 /* We must avoid matching of Imm32 templates when 64bit
3652 only immediate is available. */
3653 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3654 i
.types
[op
].bitfield
.imm32
= 0;
3661 /* Symbols and expressions. */
3663 /* Convert symbolic operand to proper sizes for matching, but don't
3664 prevent matching a set of insns that only supports sizes other
3665 than those matching the insn suffix. */
3667 i386_operand_type mask
, allowed
;
3668 const insn_template
*t
;
3670 operand_type_set (&mask
, 0);
3671 operand_type_set (&allowed
, 0);
3673 for (t
= current_templates
->start
;
3674 t
< current_templates
->end
;
3676 allowed
= operand_type_or (allowed
,
3677 t
->operand_types
[op
]);
3678 switch (guess_suffix
)
3680 case QWORD_MNEM_SUFFIX
:
3681 mask
.bitfield
.imm64
= 1;
3682 mask
.bitfield
.imm32s
= 1;
3684 case LONG_MNEM_SUFFIX
:
3685 mask
.bitfield
.imm32
= 1;
3687 case WORD_MNEM_SUFFIX
:
3688 mask
.bitfield
.imm16
= 1;
3690 case BYTE_MNEM_SUFFIX
:
3691 mask
.bitfield
.imm8
= 1;
3696 allowed
= operand_type_and (mask
, allowed
);
3697 if (!operand_type_all_zero (&allowed
))
3698 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3705 /* Try to use the smallest displacement type too. */
3707 optimize_disp (void)
3711 for (op
= i
.operands
; --op
>= 0;)
3712 if (operand_type_check (i
.types
[op
], disp
))
3714 if (i
.op
[op
].disps
->X_op
== O_constant
)
3716 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3718 if (i
.types
[op
].bitfield
.disp16
3719 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3721 /* If this operand is at most 16 bits, convert
3722 to a signed 16 bit number and don't use 64bit
3724 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3725 i
.types
[op
].bitfield
.disp64
= 0;
3727 if (i
.types
[op
].bitfield
.disp32
3728 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3730 /* If this operand is at most 32 bits, convert
3731 to a signed 32 bit number and don't use 64bit
3733 op_disp
&= (((offsetT
) 2 << 31) - 1);
3734 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3735 i
.types
[op
].bitfield
.disp64
= 0;
3737 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3739 i
.types
[op
].bitfield
.disp8
= 0;
3740 i
.types
[op
].bitfield
.disp16
= 0;
3741 i
.types
[op
].bitfield
.disp32
= 0;
3742 i
.types
[op
].bitfield
.disp32s
= 0;
3743 i
.types
[op
].bitfield
.disp64
= 0;
3747 else if (flag_code
== CODE_64BIT
)
3749 if (fits_in_signed_long (op_disp
))
3751 i
.types
[op
].bitfield
.disp64
= 0;
3752 i
.types
[op
].bitfield
.disp32s
= 1;
3754 if (i
.prefix
[ADDR_PREFIX
]
3755 && fits_in_unsigned_long (op_disp
))
3756 i
.types
[op
].bitfield
.disp32
= 1;
3758 if ((i
.types
[op
].bitfield
.disp32
3759 || i
.types
[op
].bitfield
.disp32s
3760 || i
.types
[op
].bitfield
.disp16
)
3761 && fits_in_signed_byte (op_disp
))
3762 i
.types
[op
].bitfield
.disp8
= 1;
3764 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3765 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3767 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3768 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3769 i
.types
[op
].bitfield
.disp8
= 0;
3770 i
.types
[op
].bitfield
.disp16
= 0;
3771 i
.types
[op
].bitfield
.disp32
= 0;
3772 i
.types
[op
].bitfield
.disp32s
= 0;
3773 i
.types
[op
].bitfield
.disp64
= 0;
3776 /* We only support 64bit displacement on constants. */
3777 i
.types
[op
].bitfield
.disp64
= 0;
3781 /* Check if operands are valid for the instrucrtion. Update VEX
3785 VEX_check_operands (const insn_template
*t
)
3787 if (!t
->opcode_modifier
.vex
)
3790 /* Only check VEX_Imm4, which must be the first operand. */
3791 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3793 if (i
.op
[0].imms
->X_op
!= O_constant
3794 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3800 /* Turn off Imm8 so that update_imm won't complain. */
3801 i
.types
[0] = vec_imm4
;
3807 static const insn_template
*
3808 match_template (void)
3810 /* Points to template once we've found it. */
3811 const insn_template
*t
;
3812 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3813 i386_operand_type overlap4
;
3814 unsigned int found_reverse_match
;
3815 i386_opcode_modifier suffix_check
;
3816 i386_operand_type operand_types
[MAX_OPERANDS
];
3817 int addr_prefix_disp
;
3819 unsigned int found_cpu_match
;
3820 unsigned int check_register
;
3822 #if MAX_OPERANDS != 5
3823 # error "MAX_OPERANDS must be 5."
3826 found_reverse_match
= 0;
3827 addr_prefix_disp
= -1;
3829 memset (&suffix_check
, 0, sizeof (suffix_check
));
3830 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3831 suffix_check
.no_bsuf
= 1;
3832 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3833 suffix_check
.no_wsuf
= 1;
3834 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3835 suffix_check
.no_ssuf
= 1;
3836 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3837 suffix_check
.no_lsuf
= 1;
3838 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3839 suffix_check
.no_qsuf
= 1;
3840 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3841 suffix_check
.no_ldsuf
= 1;
3843 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3845 addr_prefix_disp
= -1;
3847 /* Must have right number of operands. */
3848 i
.error
= number_of_operands_mismatch
;
3849 if (i
.operands
!= t
->operands
)
3852 /* Check processor support. */
3853 i
.error
= unsupported
;
3854 found_cpu_match
= (cpu_flags_match (t
)
3855 == CPU_FLAGS_PERFECT_MATCH
);
3856 if (!found_cpu_match
)
3859 /* Check old gcc support. */
3860 i
.error
= old_gcc_only
;
3861 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3864 /* Check AT&T mnemonic. */
3865 i
.error
= unsupported_with_intel_mnemonic
;
3866 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3869 /* Check AT&T/Intel syntax. */
3870 i
.error
= unsupported_syntax
;
3871 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3872 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3875 /* Check the suffix, except for some instructions in intel mode. */
3876 i
.error
= invalid_instruction_suffix
;
3877 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3878 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3879 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3880 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3881 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3882 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3883 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3886 if (!operand_size_match (t
))
3889 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3890 operand_types
[j
] = t
->operand_types
[j
];
3892 /* In general, don't allow 64-bit operands in 32-bit mode. */
3893 if (i
.suffix
== QWORD_MNEM_SUFFIX
3894 && flag_code
!= CODE_64BIT
3896 ? (!t
->opcode_modifier
.ignoresize
3897 && !intel_float_operand (t
->name
))
3898 : intel_float_operand (t
->name
) != 2)
3899 && ((!operand_types
[0].bitfield
.regmmx
3900 && !operand_types
[0].bitfield
.regxmm
3901 && !operand_types
[0].bitfield
.regymm
)
3902 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3903 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3904 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3905 && (t
->base_opcode
!= 0x0fc7
3906 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3909 /* In general, don't allow 32-bit operands on pre-386. */
3910 else if (i
.suffix
== LONG_MNEM_SUFFIX
3911 && !cpu_arch_flags
.bitfield
.cpui386
3913 ? (!t
->opcode_modifier
.ignoresize
3914 && !intel_float_operand (t
->name
))
3915 : intel_float_operand (t
->name
) != 2)
3916 && ((!operand_types
[0].bitfield
.regmmx
3917 && !operand_types
[0].bitfield
.regxmm
)
3918 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3919 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3922 /* Do not verify operands when there are none. */
3926 /* We've found a match; break out of loop. */
3930 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3931 into Disp32/Disp16/Disp32 operand. */
3932 if (i
.prefix
[ADDR_PREFIX
] != 0)
3934 /* There should be only one Disp operand. */
3938 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3940 if (operand_types
[j
].bitfield
.disp16
)
3942 addr_prefix_disp
= j
;
3943 operand_types
[j
].bitfield
.disp32
= 1;
3944 operand_types
[j
].bitfield
.disp16
= 0;
3950 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3952 if (operand_types
[j
].bitfield
.disp32
)
3954 addr_prefix_disp
= j
;
3955 operand_types
[j
].bitfield
.disp32
= 0;
3956 operand_types
[j
].bitfield
.disp16
= 1;
3962 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3964 if (operand_types
[j
].bitfield
.disp64
)
3966 addr_prefix_disp
= j
;
3967 operand_types
[j
].bitfield
.disp64
= 0;
3968 operand_types
[j
].bitfield
.disp32
= 1;
3976 /* We check register size only if size of operands can be
3977 encoded the canonical way. */
3978 check_register
= t
->opcode_modifier
.w
;
3979 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3980 switch (t
->operands
)
3983 if (!operand_type_match (overlap0
, i
.types
[0]))
3987 /* xchg %eax, %eax is a special case. It is an aliase for nop
3988 only in 32bit mode and we can use opcode 0x90. In 64bit
3989 mode, we can't use 0x90 for xchg %eax, %eax since it should
3990 zero-extend %eax to %rax. */
3991 if (flag_code
== CODE_64BIT
3992 && t
->base_opcode
== 0x90
3993 && operand_type_equal (&i
.types
[0], &acc32
)
3994 && operand_type_equal (&i
.types
[1], &acc32
))
3998 /* If we swap operand in encoding, we either match
3999 the next one or reverse direction of operands. */
4000 if (t
->opcode_modifier
.s
)
4002 else if (t
->opcode_modifier
.d
)
4007 /* If we swap operand in encoding, we match the next one. */
4008 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4012 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4013 if (!operand_type_match (overlap0
, i
.types
[0])
4014 || !operand_type_match (overlap1
, i
.types
[1])
4016 && !operand_type_register_match (overlap0
, i
.types
[0],
4018 overlap1
, i
.types
[1],
4021 /* Check if other direction is valid ... */
4022 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4026 /* Try reversing direction of operands. */
4027 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4028 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4029 if (!operand_type_match (overlap0
, i
.types
[0])
4030 || !operand_type_match (overlap1
, i
.types
[1])
4032 && !operand_type_register_match (overlap0
,
4039 /* Does not match either direction. */
4042 /* found_reverse_match holds which of D or FloatDR
4044 if (t
->opcode_modifier
.d
)
4045 found_reverse_match
= Opcode_D
;
4046 else if (t
->opcode_modifier
.floatd
)
4047 found_reverse_match
= Opcode_FloatD
;
4049 found_reverse_match
= 0;
4050 if (t
->opcode_modifier
.floatr
)
4051 found_reverse_match
|= Opcode_FloatR
;
4055 /* Found a forward 2 operand match here. */
4056 switch (t
->operands
)
4059 overlap4
= operand_type_and (i
.types
[4],
4062 overlap3
= operand_type_and (i
.types
[3],
4065 overlap2
= operand_type_and (i
.types
[2],
4070 switch (t
->operands
)
4073 if (!operand_type_match (overlap4
, i
.types
[4])
4074 || !operand_type_register_match (overlap3
,
4082 if (!operand_type_match (overlap3
, i
.types
[3])
4084 && !operand_type_register_match (overlap2
,
4092 /* Here we make use of the fact that there are no
4093 reverse match 3 operand instructions, and all 3
4094 operand instructions only need to be checked for
4095 register consistency between operands 2 and 3. */
4096 if (!operand_type_match (overlap2
, i
.types
[2])
4098 && !operand_type_register_match (overlap1
,
4108 /* Found either forward/reverse 2, 3 or 4 operand match here:
4109 slip through to break. */
4111 if (!found_cpu_match
)
4113 found_reverse_match
= 0;
4117 /* Check if VEX operands are valid. */
4118 if (VEX_check_operands (t
))
4121 /* We've found a match; break out of loop. */
4125 if (t
== current_templates
->end
)
4127 /* We found no match. */
4128 const char *err_msg
;
4133 case operand_size_mismatch
:
4134 err_msg
= _("operand size mismatch");
4136 case operand_type_mismatch
:
4137 err_msg
= _("operand type mismatch");
4139 case register_type_mismatch
:
4140 err_msg
= _("register type mismatch");
4142 case number_of_operands_mismatch
:
4143 err_msg
= _("number of operands mismatch");
4145 case invalid_instruction_suffix
:
4146 err_msg
= _("invalid instruction suffix");
4149 err_msg
= _("Imm4 isn't the first operand");
4152 err_msg
= _("only supported with old gcc");
4154 case unsupported_with_intel_mnemonic
:
4155 err_msg
= _("unsupported with Intel mnemonic");
4157 case unsupported_syntax
:
4158 err_msg
= _("unsupported syntax");
4161 err_msg
= _("unsupported");
4164 as_bad (_("%s for `%s'"), err_msg
,
4165 current_templates
->start
->name
);
4169 if (!quiet_warnings
)
4172 && (i
.types
[0].bitfield
.jumpabsolute
4173 != operand_types
[0].bitfield
.jumpabsolute
))
4175 as_warn (_("indirect %s without `*'"), t
->name
);
4178 if (t
->opcode_modifier
.isprefix
4179 && t
->opcode_modifier
.ignoresize
)
4181 /* Warn them that a data or address size prefix doesn't
4182 affect assembly of the next line of code. */
4183 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4187 /* Copy the template we found. */
4190 if (addr_prefix_disp
!= -1)
4191 i
.tm
.operand_types
[addr_prefix_disp
]
4192 = operand_types
[addr_prefix_disp
];
4194 if (found_reverse_match
)
4196 /* If we found a reverse match we must alter the opcode
4197 direction bit. found_reverse_match holds bits to change
4198 (different for int & float insns). */
4200 i
.tm
.base_opcode
^= found_reverse_match
;
4202 i
.tm
.operand_types
[0] = operand_types
[1];
4203 i
.tm
.operand_types
[1] = operand_types
[0];
4212 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4213 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4215 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4217 as_bad (_("`%s' operand %d must use `%ses' segment"),
4223 /* There's only ever one segment override allowed per instruction.
4224 This instruction possibly has a legal segment override on the
4225 second operand, so copy the segment to where non-string
4226 instructions store it, allowing common code. */
4227 i
.seg
[0] = i
.seg
[1];
4229 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4231 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4233 as_bad (_("`%s' operand %d must use `%ses' segment"),
4244 process_suffix (void)
4246 /* If matched instruction specifies an explicit instruction mnemonic
4248 if (i
.tm
.opcode_modifier
.size16
)
4249 i
.suffix
= WORD_MNEM_SUFFIX
;
4250 else if (i
.tm
.opcode_modifier
.size32
)
4251 i
.suffix
= LONG_MNEM_SUFFIX
;
4252 else if (i
.tm
.opcode_modifier
.size64
)
4253 i
.suffix
= QWORD_MNEM_SUFFIX
;
4254 else if (i
.reg_operands
)
4256 /* If there's no instruction mnemonic suffix we try to invent one
4257 based on register operands. */
4260 /* We take i.suffix from the last register operand specified,
4261 Destination register type is more significant than source
4262 register type. crc32 in SSE4.2 prefers source register
4264 if (i
.tm
.base_opcode
== 0xf20f38f1)
4266 if (i
.types
[0].bitfield
.reg16
)
4267 i
.suffix
= WORD_MNEM_SUFFIX
;
4268 else if (i
.types
[0].bitfield
.reg32
)
4269 i
.suffix
= LONG_MNEM_SUFFIX
;
4270 else if (i
.types
[0].bitfield
.reg64
)
4271 i
.suffix
= QWORD_MNEM_SUFFIX
;
4273 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4275 if (i
.types
[0].bitfield
.reg8
)
4276 i
.suffix
= BYTE_MNEM_SUFFIX
;
4283 if (i
.tm
.base_opcode
== 0xf20f38f1
4284 || i
.tm
.base_opcode
== 0xf20f38f0)
4286 /* We have to know the operand size for crc32. */
4287 as_bad (_("ambiguous memory operand size for `%s`"),
4292 for (op
= i
.operands
; --op
>= 0;)
4293 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4295 if (i
.types
[op
].bitfield
.reg8
)
4297 i
.suffix
= BYTE_MNEM_SUFFIX
;
4300 else if (i
.types
[op
].bitfield
.reg16
)
4302 i
.suffix
= WORD_MNEM_SUFFIX
;
4305 else if (i
.types
[op
].bitfield
.reg32
)
4307 i
.suffix
= LONG_MNEM_SUFFIX
;
4310 else if (i
.types
[op
].bitfield
.reg64
)
4312 i
.suffix
= QWORD_MNEM_SUFFIX
;
4318 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4321 && i
.tm
.opcode_modifier
.ignoresize
4322 && i
.tm
.opcode_modifier
.no_bsuf
)
4324 else if (!check_byte_reg ())
4327 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4330 && i
.tm
.opcode_modifier
.ignoresize
4331 && i
.tm
.opcode_modifier
.no_lsuf
)
4333 else if (!check_long_reg ())
4336 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4339 && i
.tm
.opcode_modifier
.ignoresize
4340 && i
.tm
.opcode_modifier
.no_qsuf
)
4342 else if (!check_qword_reg ())
4345 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4348 && i
.tm
.opcode_modifier
.ignoresize
4349 && i
.tm
.opcode_modifier
.no_wsuf
)
4351 else if (!check_word_reg ())
4354 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4355 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4357 /* Skip if the instruction has x/y suffix. match_template
4358 should check if it is a valid suffix. */
4360 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4361 /* Do nothing if the instruction is going to ignore the prefix. */
4366 else if (i
.tm
.opcode_modifier
.defaultsize
4368 /* exclude fldenv/frstor/fsave/fstenv */
4369 && i
.tm
.opcode_modifier
.no_ssuf
)
4371 i
.suffix
= stackop_size
;
4373 else if (intel_syntax
4375 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4376 || i
.tm
.opcode_modifier
.jumpbyte
4377 || i
.tm
.opcode_modifier
.jumpintersegment
4378 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4379 && i
.tm
.extension_opcode
<= 3)))
4384 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4386 i
.suffix
= QWORD_MNEM_SUFFIX
;
4390 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4391 i
.suffix
= LONG_MNEM_SUFFIX
;
4394 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4395 i
.suffix
= WORD_MNEM_SUFFIX
;
4404 if (i
.tm
.opcode_modifier
.w
)
4406 as_bad (_("no instruction mnemonic suffix given and "
4407 "no register operands; can't size instruction"));
4413 unsigned int suffixes
;
4415 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4416 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4418 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4420 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4422 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4424 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4427 /* There are more than suffix matches. */
4428 if (i
.tm
.opcode_modifier
.w
4429 || ((suffixes
& (suffixes
- 1))
4430 && !i
.tm
.opcode_modifier
.defaultsize
4431 && !i
.tm
.opcode_modifier
.ignoresize
))
4433 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4439 /* Change the opcode based on the operand size given by i.suffix;
4440 We don't need to change things for byte insns. */
4443 && i
.suffix
!= BYTE_MNEM_SUFFIX
4444 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4445 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4447 /* It's not a byte, select word/dword operation. */
4448 if (i
.tm
.opcode_modifier
.w
)
4450 if (i
.tm
.opcode_modifier
.shortform
)
4451 i
.tm
.base_opcode
|= 8;
4453 i
.tm
.base_opcode
|= 1;
4456 /* Now select between word & dword operations via the operand
4457 size prefix, except for instructions that will ignore this
4459 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4461 /* The address size override prefix changes the size of the
4463 if ((flag_code
== CODE_32BIT
4464 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4465 || (flag_code
!= CODE_32BIT
4466 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4467 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4470 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4471 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4472 && !i
.tm
.opcode_modifier
.ignoresize
4473 && !i
.tm
.opcode_modifier
.floatmf
4474 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4475 || (flag_code
== CODE_64BIT
4476 && i
.tm
.opcode_modifier
.jumpbyte
)))
4478 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4480 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4481 prefix
= ADDR_PREFIX_OPCODE
;
4483 if (!add_prefix (prefix
))
4487 /* Set mode64 for an operand. */
4488 if (i
.suffix
== QWORD_MNEM_SUFFIX
4489 && flag_code
== CODE_64BIT
4490 && !i
.tm
.opcode_modifier
.norex64
)
4492 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4493 need rex64. cmpxchg8b is also a special case. */
4494 if (! (i
.operands
== 2
4495 && i
.tm
.base_opcode
== 0x90
4496 && i
.tm
.extension_opcode
== None
4497 && operand_type_equal (&i
.types
[0], &acc64
)
4498 && operand_type_equal (&i
.types
[1], &acc64
))
4499 && ! (i
.operands
== 1
4500 && i
.tm
.base_opcode
== 0xfc7
4501 && i
.tm
.extension_opcode
== 1
4502 && !operand_type_check (i
.types
[0], reg
)
4503 && operand_type_check (i
.types
[0], anymem
)))
4507 /* Size floating point instruction. */
4508 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4509 if (i
.tm
.opcode_modifier
.floatmf
)
4510 i
.tm
.base_opcode
^= 4;
4517 check_byte_reg (void)
4521 for (op
= i
.operands
; --op
>= 0;)
4523 /* If this is an eight bit register, it's OK. If it's the 16 or
4524 32 bit version of an eight bit register, we will just use the
4525 low portion, and that's OK too. */
4526 if (i
.types
[op
].bitfield
.reg8
)
4529 /* crc32 doesn't generate this warning. */
4530 if (i
.tm
.base_opcode
== 0xf20f38f0)
4533 if ((i
.types
[op
].bitfield
.reg16
4534 || i
.types
[op
].bitfield
.reg32
4535 || i
.types
[op
].bitfield
.reg64
)
4536 && i
.op
[op
].regs
->reg_num
< 4)
4538 /* Prohibit these changes in the 64bit mode, since the
4539 lowering is more complicated. */
4540 if (flag_code
== CODE_64BIT
4541 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4543 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4544 register_prefix
, i
.op
[op
].regs
->reg_name
,
4548 #if REGISTER_WARNINGS
4550 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4551 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4553 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4554 ? REGNAM_AL
- REGNAM_AX
4555 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4557 i
.op
[op
].regs
->reg_name
,
4562 /* Any other register is bad. */
4563 if (i
.types
[op
].bitfield
.reg16
4564 || i
.types
[op
].bitfield
.reg32
4565 || i
.types
[op
].bitfield
.reg64
4566 || i
.types
[op
].bitfield
.regmmx
4567 || i
.types
[op
].bitfield
.regxmm
4568 || i
.types
[op
].bitfield
.regymm
4569 || i
.types
[op
].bitfield
.sreg2
4570 || i
.types
[op
].bitfield
.sreg3
4571 || i
.types
[op
].bitfield
.control
4572 || i
.types
[op
].bitfield
.debug
4573 || i
.types
[op
].bitfield
.test
4574 || i
.types
[op
].bitfield
.floatreg
4575 || i
.types
[op
].bitfield
.floatacc
)
4577 as_bad (_("`%s%s' not allowed with `%s%c'"),
4579 i
.op
[op
].regs
->reg_name
,
4589 check_long_reg (void)
4593 for (op
= i
.operands
; --op
>= 0;)
4594 /* Reject eight bit registers, except where the template requires
4595 them. (eg. movzb) */
4596 if (i
.types
[op
].bitfield
.reg8
4597 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4598 || i
.tm
.operand_types
[op
].bitfield
.reg32
4599 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4601 as_bad (_("`%s%s' not allowed with `%s%c'"),
4603 i
.op
[op
].regs
->reg_name
,
4608 /* Warn if the e prefix on a general reg is missing. */
4609 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4610 && i
.types
[op
].bitfield
.reg16
4611 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4612 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4614 /* Prohibit these changes in the 64bit mode, since the
4615 lowering is more complicated. */
4616 if (flag_code
== CODE_64BIT
)
4618 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4619 register_prefix
, i
.op
[op
].regs
->reg_name
,
4623 #if REGISTER_WARNINGS
4625 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4627 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4629 i
.op
[op
].regs
->reg_name
,
4633 /* Warn if the r prefix on a general reg is missing. */
4634 else if (i
.types
[op
].bitfield
.reg64
4635 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4636 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4639 && i
.tm
.opcode_modifier
.toqword
4640 && !i
.types
[0].bitfield
.regxmm
)
4642 /* Convert to QWORD. We want REX byte. */
4643 i
.suffix
= QWORD_MNEM_SUFFIX
;
4647 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4648 register_prefix
, i
.op
[op
].regs
->reg_name
,
4657 check_qword_reg (void)
4661 for (op
= i
.operands
; --op
>= 0; )
4662 /* Reject eight bit registers, except where the template requires
4663 them. (eg. movzb) */
4664 if (i
.types
[op
].bitfield
.reg8
4665 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4666 || i
.tm
.operand_types
[op
].bitfield
.reg32
4667 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4669 as_bad (_("`%s%s' not allowed with `%s%c'"),
4671 i
.op
[op
].regs
->reg_name
,
4676 /* Warn if the e prefix on a general reg is missing. */
4677 else if ((i
.types
[op
].bitfield
.reg16
4678 || i
.types
[op
].bitfield
.reg32
)
4679 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4680 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4682 /* Prohibit these changes in the 64bit mode, since the
4683 lowering is more complicated. */
4685 && i
.tm
.opcode_modifier
.todword
4686 && !i
.types
[0].bitfield
.regxmm
)
4688 /* Convert to DWORD. We don't want REX byte. */
4689 i
.suffix
= LONG_MNEM_SUFFIX
;
4693 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4694 register_prefix
, i
.op
[op
].regs
->reg_name
,
4703 check_word_reg (void)
4706 for (op
= i
.operands
; --op
>= 0;)
4707 /* Reject eight bit registers, except where the template requires
4708 them. (eg. movzb) */
4709 if (i
.types
[op
].bitfield
.reg8
4710 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4711 || i
.tm
.operand_types
[op
].bitfield
.reg32
4712 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4714 as_bad (_("`%s%s' not allowed with `%s%c'"),
4716 i
.op
[op
].regs
->reg_name
,
4721 /* Warn if the e prefix on a general reg is present. */
4722 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4723 && i
.types
[op
].bitfield
.reg32
4724 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4725 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4727 /* Prohibit these changes in the 64bit mode, since the
4728 lowering is more complicated. */
4729 if (flag_code
== CODE_64BIT
)
4731 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4732 register_prefix
, i
.op
[op
].regs
->reg_name
,
4737 #if REGISTER_WARNINGS
4738 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4740 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4742 i
.op
[op
].regs
->reg_name
,
4750 update_imm (unsigned int j
)
4752 i386_operand_type overlap
= i
.types
[j
];
4753 if ((overlap
.bitfield
.imm8
4754 || overlap
.bitfield
.imm8s
4755 || overlap
.bitfield
.imm16
4756 || overlap
.bitfield
.imm32
4757 || overlap
.bitfield
.imm32s
4758 || overlap
.bitfield
.imm64
)
4759 && !operand_type_equal (&overlap
, &imm8
)
4760 && !operand_type_equal (&overlap
, &imm8s
)
4761 && !operand_type_equal (&overlap
, &imm16
)
4762 && !operand_type_equal (&overlap
, &imm32
)
4763 && !operand_type_equal (&overlap
, &imm32s
)
4764 && !operand_type_equal (&overlap
, &imm64
))
4768 i386_operand_type temp
;
4770 operand_type_set (&temp
, 0);
4771 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4773 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4774 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4776 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4777 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4778 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4780 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4781 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4784 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4787 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4788 || operand_type_equal (&overlap
, &imm16_32
)
4789 || operand_type_equal (&overlap
, &imm16_32s
))
4791 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4796 if (!operand_type_equal (&overlap
, &imm8
)
4797 && !operand_type_equal (&overlap
, &imm8s
)
4798 && !operand_type_equal (&overlap
, &imm16
)
4799 && !operand_type_equal (&overlap
, &imm32
)
4800 && !operand_type_equal (&overlap
, &imm32s
)
4801 && !operand_type_equal (&overlap
, &imm64
))
4803 as_bad (_("no instruction mnemonic suffix given; "
4804 "can't determine immediate size"));
4808 i
.types
[j
] = overlap
;
4818 /* Update the first 2 immediate operands. */
4819 n
= i
.operands
> 2 ? 2 : i
.operands
;
4822 for (j
= 0; j
< n
; j
++)
4823 if (update_imm (j
) == 0)
4826 /* The 3rd operand can't be immediate operand. */
4827 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4834 bad_implicit_operand (int xmm
)
4836 const char *ireg
= xmm
? "xmm0" : "ymm0";
4839 as_bad (_("the last operand of `%s' must be `%s%s'"),
4840 i
.tm
.name
, register_prefix
, ireg
);
4842 as_bad (_("the first operand of `%s' must be `%s%s'"),
4843 i
.tm
.name
, register_prefix
, ireg
);
4848 process_operands (void)
4850 /* Default segment register this instruction will use for memory
4851 accesses. 0 means unknown. This is only for optimizing out
4852 unnecessary segment overrides. */
4853 const seg_entry
*default_seg
= 0;
4855 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4857 unsigned int dupl
= i
.operands
;
4858 unsigned int dest
= dupl
- 1;
4861 /* The destination must be an xmm register. */
4862 gas_assert (i
.reg_operands
4863 && MAX_OPERANDS
> dupl
4864 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4866 if (i
.tm
.opcode_modifier
.firstxmm0
)
4868 /* The first operand is implicit and must be xmm0. */
4869 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4870 if (i
.op
[0].regs
->reg_num
!= 0)
4871 return bad_implicit_operand (1);
4873 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4875 /* Keep xmm0 for instructions with VEX prefix and 3
4881 /* We remove the first xmm0 and keep the number of
4882 operands unchanged, which in fact duplicates the
4884 for (j
= 1; j
< i
.operands
; j
++)
4886 i
.op
[j
- 1] = i
.op
[j
];
4887 i
.types
[j
- 1] = i
.types
[j
];
4888 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4892 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4894 gas_assert ((MAX_OPERANDS
- 1) > dupl
4895 && (i
.tm
.opcode_modifier
.vexsources
4898 /* Add the implicit xmm0 for instructions with VEX prefix
4900 for (j
= i
.operands
; j
> 0; j
--)
4902 i
.op
[j
] = i
.op
[j
- 1];
4903 i
.types
[j
] = i
.types
[j
- 1];
4904 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4907 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4908 i
.types
[0] = regxmm
;
4909 i
.tm
.operand_types
[0] = regxmm
;
4912 i
.reg_operands
+= 2;
4917 i
.op
[dupl
] = i
.op
[dest
];
4918 i
.types
[dupl
] = i
.types
[dest
];
4919 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4928 i
.op
[dupl
] = i
.op
[dest
];
4929 i
.types
[dupl
] = i
.types
[dest
];
4930 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4933 if (i
.tm
.opcode_modifier
.immext
)
4936 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4940 /* The first operand is implicit and must be xmm0/ymm0. */
4941 gas_assert (i
.reg_operands
4942 && (operand_type_equal (&i
.types
[0], ®xmm
)
4943 || operand_type_equal (&i
.types
[0], ®ymm
)));
4944 if (i
.op
[0].regs
->reg_num
!= 0)
4945 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4947 for (j
= 1; j
< i
.operands
; j
++)
4949 i
.op
[j
- 1] = i
.op
[j
];
4950 i
.types
[j
- 1] = i
.types
[j
];
4952 /* We need to adjust fields in i.tm since they are used by
4953 build_modrm_byte. */
4954 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4961 else if (i
.tm
.opcode_modifier
.regkludge
)
4963 /* The imul $imm, %reg instruction is converted into
4964 imul $imm, %reg, %reg, and the clr %reg instruction
4965 is converted into xor %reg, %reg. */
4967 unsigned int first_reg_op
;
4969 if (operand_type_check (i
.types
[0], reg
))
4973 /* Pretend we saw the extra register operand. */
4974 gas_assert (i
.reg_operands
== 1
4975 && i
.op
[first_reg_op
+ 1].regs
== 0);
4976 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4977 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4982 if (i
.tm
.opcode_modifier
.shortform
)
4984 if (i
.types
[0].bitfield
.sreg2
4985 || i
.types
[0].bitfield
.sreg3
)
4987 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4988 && i
.op
[0].regs
->reg_num
== 1)
4990 as_bad (_("you can't `pop %scs'"), register_prefix
);
4993 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4994 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4999 /* The register or float register operand is in operand
5003 if (i
.types
[0].bitfield
.floatreg
5004 || operand_type_check (i
.types
[0], reg
))
5008 /* Register goes in low 3 bits of opcode. */
5009 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5010 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5012 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5014 /* Warn about some common errors, but press on regardless.
5015 The first case can be generated by gcc (<= 2.8.1). */
5016 if (i
.operands
== 2)
5018 /* Reversed arguments on faddp, fsubp, etc. */
5019 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5020 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5021 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5025 /* Extraneous `l' suffix on fp insn. */
5026 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5027 register_prefix
, i
.op
[0].regs
->reg_name
);
5032 else if (i
.tm
.opcode_modifier
.modrm
)
5034 /* The opcode is completed (modulo i.tm.extension_opcode which
5035 must be put into the modrm byte). Now, we make the modrm and
5036 index base bytes based on all the info we've collected. */
5038 default_seg
= build_modrm_byte ();
5040 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5044 else if (i
.tm
.opcode_modifier
.isstring
)
5046 /* For the string instructions that allow a segment override
5047 on one of their operands, the default segment is ds. */
5051 if (i
.tm
.base_opcode
== 0x8d /* lea */
5054 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5056 /* If a segment was explicitly specified, and the specified segment
5057 is not the default, use an opcode prefix to select it. If we
5058 never figured out what the default segment is, then default_seg
5059 will be zero at this point, and the specified segment prefix will
5061 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5063 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5069 static const seg_entry
*
5070 build_modrm_byte (void)
5072 const seg_entry
*default_seg
= 0;
5073 unsigned int source
, dest
;
5076 /* The first operand of instructions with VEX prefix and 3 sources
5077 must be VEX_Imm4. */
5078 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5081 unsigned int nds
, reg_slot
;
5084 if (i
.tm
.opcode_modifier
.veximmext
5085 && i
.tm
.opcode_modifier
.immext
)
5087 dest
= i
.operands
- 2;
5088 gas_assert (dest
== 3);
5091 dest
= i
.operands
- 1;
5094 /* There are 2 kinds of instructions:
5095 1. 5 operands: 4 register operands or 3 register operands
5096 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5097 VexW0 or VexW1. The destination must be either XMM or YMM
5099 2. 4 operands: 4 register operands or 3 register operands
5100 plus 1 memory operand, VexXDS, and VexImmExt */
5101 gas_assert ((i
.reg_operands
== 4
5102 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5103 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5104 && (i
.tm
.opcode_modifier
.veximmext
5105 || (i
.imm_operands
== 1
5106 && i
.types
[0].bitfield
.vec_imm4
5107 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5108 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5109 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5110 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5112 if (i
.imm_operands
== 0)
5114 /* When there is no immediate operand, generate an 8bit
5115 immediate operand to encode the first operand. */
5116 exp
= &im_expressions
[i
.imm_operands
++];
5117 i
.op
[i
.operands
].imms
= exp
;
5118 i
.types
[i
.operands
] = imm8
;
5120 /* If VexW1 is set, the first operand is the source and
5121 the second operand is encoded in the immediate operand. */
5122 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5133 /* FMA swaps REG and NDS. */
5134 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5142 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5144 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5146 exp
->X_op
= O_constant
;
5148 = ((i
.op
[reg_slot
].regs
->reg_num
5149 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5154 unsigned int imm_slot
;
5156 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5158 /* If VexW0 is set, the third operand is the source and
5159 the second operand is encoded in the immediate
5166 /* VexW1 is set, the second operand is the source and
5167 the third operand is encoded in the immediate
5173 if (i
.tm
.opcode_modifier
.immext
)
5175 /* When ImmExt is set, the immdiate byte is the last
5177 imm_slot
= i
.operands
- 1;
5185 /* Turn on Imm8 so that output_imm will generate it. */
5186 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5189 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5191 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5193 i
.op
[imm_slot
].imms
->X_add_number
5194 |= ((i
.op
[reg_slot
].regs
->reg_num
5195 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5199 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5200 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5202 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5207 /* i.reg_operands MUST be the number of real register operands;
5208 implicit registers do not count. If there are 3 register
5209 operands, it must be a instruction with VexNDS. For a
5210 instruction with VexNDD, the destination register is encoded
5211 in VEX prefix. If there are 4 register operands, it must be
5212 a instruction with VEX prefix and 3 sources. */
5213 if (i
.mem_operands
== 0
5214 && ((i
.reg_operands
== 2
5215 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5216 || (i
.reg_operands
== 3
5217 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5218 || (i
.reg_operands
== 4 && vex_3_sources
)))
5226 /* When there are 3 operands, one of them may be immediate,
5227 which may be the first or the last operand. Otherwise,
5228 the first operand must be shift count register (cl) or it
5229 is an instruction with VexNDS. */
5230 gas_assert (i
.imm_operands
== 1
5231 || (i
.imm_operands
== 0
5232 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5233 || i
.types
[0].bitfield
.shiftcount
)));
5234 if (operand_type_check (i
.types
[0], imm
)
5235 || i
.types
[0].bitfield
.shiftcount
)
5241 /* When there are 4 operands, the first two must be 8bit
5242 immediate operands. The source operand will be the 3rd
5245 For instructions with VexNDS, if the first operand
5246 an imm8, the source operand is the 2nd one. If the last
5247 operand is imm8, the source operand is the first one. */
5248 gas_assert ((i
.imm_operands
== 2
5249 && i
.types
[0].bitfield
.imm8
5250 && i
.types
[1].bitfield
.imm8
)
5251 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5252 && i
.imm_operands
== 1
5253 && (i
.types
[0].bitfield
.imm8
5254 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5255 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5257 if (i
.types
[0].bitfield
.imm8
)
5275 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5277 /* For instructions with VexNDS, the register-only
5278 source operand must be XMM or YMM register. It is
5279 encoded in VEX prefix. We need to clear RegMem bit
5280 before calling operand_type_equal. */
5281 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5282 op
.bitfield
.regmem
= 0;
5283 if ((dest
+ 1) >= i
.operands
5284 || (!operand_type_equal (&op
, ®xmm
)
5285 && !operand_type_equal (&op
, ®ymm
)))
5287 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5293 /* One of the register operands will be encoded in the i.tm.reg
5294 field, the other in the combined i.tm.mode and i.tm.regmem
5295 fields. If no form of this instruction supports a memory
5296 destination operand, then we assume the source operand may
5297 sometimes be a memory operand and so we need to store the
5298 destination in the i.rm.reg field. */
5299 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5300 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5302 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5303 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5304 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5306 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5311 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5312 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5313 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5315 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5318 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5320 if (!i
.types
[0].bitfield
.control
5321 && !i
.types
[1].bitfield
.control
)
5323 i
.rex
&= ~(REX_R
| REX_B
);
5324 add_prefix (LOCK_PREFIX_OPCODE
);
5328 { /* If it's not 2 reg operands... */
5333 unsigned int fake_zero_displacement
= 0;
5336 for (op
= 0; op
< i
.operands
; op
++)
5337 if (operand_type_check (i
.types
[op
], anymem
))
5339 gas_assert (op
< i
.operands
);
5343 if (i
.base_reg
== 0)
5346 if (!i
.disp_operands
)
5347 fake_zero_displacement
= 1;
5348 if (i
.index_reg
== 0)
5350 /* Operand is just <disp> */
5351 if (flag_code
== CODE_64BIT
)
5353 /* 64bit mode overwrites the 32bit absolute
5354 addressing by RIP relative addressing and
5355 absolute addressing is encoded by one of the
5356 redundant SIB forms. */
5357 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5358 i
.sib
.base
= NO_BASE_REGISTER
;
5359 i
.sib
.index
= NO_INDEX_REGISTER
;
5360 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5361 ? disp32s
: disp32
);
5363 else if ((flag_code
== CODE_16BIT
)
5364 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5366 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5367 i
.types
[op
] = disp16
;
5371 i
.rm
.regmem
= NO_BASE_REGISTER
;
5372 i
.types
[op
] = disp32
;
5375 else /* !i.base_reg && i.index_reg */
5377 if (i
.index_reg
->reg_num
== RegEiz
5378 || i
.index_reg
->reg_num
== RegRiz
)
5379 i
.sib
.index
= NO_INDEX_REGISTER
;
5381 i
.sib
.index
= i
.index_reg
->reg_num
;
5382 i
.sib
.base
= NO_BASE_REGISTER
;
5383 i
.sib
.scale
= i
.log2_scale_factor
;
5384 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5385 i
.types
[op
].bitfield
.disp8
= 0;
5386 i
.types
[op
].bitfield
.disp16
= 0;
5387 i
.types
[op
].bitfield
.disp64
= 0;
5388 if (flag_code
!= CODE_64BIT
)
5390 /* Must be 32 bit */
5391 i
.types
[op
].bitfield
.disp32
= 1;
5392 i
.types
[op
].bitfield
.disp32s
= 0;
5396 i
.types
[op
].bitfield
.disp32
= 0;
5397 i
.types
[op
].bitfield
.disp32s
= 1;
5399 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5403 /* RIP addressing for 64bit mode. */
5404 else if (i
.base_reg
->reg_num
== RegRip
||
5405 i
.base_reg
->reg_num
== RegEip
)
5407 i
.rm
.regmem
= NO_BASE_REGISTER
;
5408 i
.types
[op
].bitfield
.disp8
= 0;
5409 i
.types
[op
].bitfield
.disp16
= 0;
5410 i
.types
[op
].bitfield
.disp32
= 0;
5411 i
.types
[op
].bitfield
.disp32s
= 1;
5412 i
.types
[op
].bitfield
.disp64
= 0;
5413 i
.flags
[op
] |= Operand_PCrel
;
5414 if (! i
.disp_operands
)
5415 fake_zero_displacement
= 1;
5417 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5419 switch (i
.base_reg
->reg_num
)
5422 if (i
.index_reg
== 0)
5424 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5425 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5429 if (i
.index_reg
== 0)
5432 if (operand_type_check (i
.types
[op
], disp
) == 0)
5434 /* fake (%bp) into 0(%bp) */
5435 i
.types
[op
].bitfield
.disp8
= 1;
5436 fake_zero_displacement
= 1;
5439 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5440 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5442 default: /* (%si) -> 4 or (%di) -> 5 */
5443 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5445 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5447 else /* i.base_reg and 32/64 bit mode */
5449 if (flag_code
== CODE_64BIT
5450 && operand_type_check (i
.types
[op
], disp
))
5452 i386_operand_type temp
;
5453 operand_type_set (&temp
, 0);
5454 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5456 if (i
.prefix
[ADDR_PREFIX
] == 0)
5457 i
.types
[op
].bitfield
.disp32s
= 1;
5459 i
.types
[op
].bitfield
.disp32
= 1;
5462 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5463 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5465 i
.sib
.base
= i
.base_reg
->reg_num
;
5466 /* x86-64 ignores REX prefix bit here to avoid decoder
5468 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5471 if (i
.disp_operands
== 0)
5473 fake_zero_displacement
= 1;
5474 i
.types
[op
].bitfield
.disp8
= 1;
5477 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5481 i
.sib
.scale
= i
.log2_scale_factor
;
5482 if (i
.index_reg
== 0)
5484 /* <disp>(%esp) becomes two byte modrm with no index
5485 register. We've already stored the code for esp
5486 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5487 Any base register besides %esp will not use the
5488 extra modrm byte. */
5489 i
.sib
.index
= NO_INDEX_REGISTER
;
5493 if (i
.index_reg
->reg_num
== RegEiz
5494 || i
.index_reg
->reg_num
== RegRiz
)
5495 i
.sib
.index
= NO_INDEX_REGISTER
;
5497 i
.sib
.index
= i
.index_reg
->reg_num
;
5498 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5499 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5504 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5505 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5508 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5511 if (fake_zero_displacement
)
5513 /* Fakes a zero displacement assuming that i.types[op]
5514 holds the correct displacement size. */
5517 gas_assert (i
.op
[op
].disps
== 0);
5518 exp
= &disp_expressions
[i
.disp_operands
++];
5519 i
.op
[op
].disps
= exp
;
5520 exp
->X_op
= O_constant
;
5521 exp
->X_add_number
= 0;
5522 exp
->X_add_symbol
= (symbolS
*) 0;
5523 exp
->X_op_symbol
= (symbolS
*) 0;
5531 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5533 if (operand_type_check (i
.types
[0], imm
))
5534 i
.vex
.register_specifier
= NULL
;
5537 /* VEX.vvvv encodes one of the sources when the first
5538 operand is not an immediate. */
5539 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5540 i
.vex
.register_specifier
= i
.op
[0].regs
;
5542 i
.vex
.register_specifier
= i
.op
[1].regs
;
5545 /* Destination is a XMM register encoded in the ModRM.reg
5547 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5548 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5551 /* ModRM.rm and VEX.B encodes the other source. */
5552 if (!i
.mem_operands
)
5556 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5557 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5559 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5561 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5565 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5567 i
.vex
.register_specifier
= i
.op
[2].regs
;
5568 if (!i
.mem_operands
)
5571 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5572 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5576 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5577 (if any) based on i.tm.extension_opcode. Again, we must be
5578 careful to make sure that segment/control/debug/test/MMX
5579 registers are coded into the i.rm.reg field. */
5580 else if (i
.reg_operands
)
5583 unsigned int vex_reg
= ~0;
5585 for (op
= 0; op
< i
.operands
; op
++)
5586 if (i
.types
[op
].bitfield
.reg8
5587 || i
.types
[op
].bitfield
.reg16
5588 || i
.types
[op
].bitfield
.reg32
5589 || i
.types
[op
].bitfield
.reg64
5590 || i
.types
[op
].bitfield
.regmmx
5591 || i
.types
[op
].bitfield
.regxmm
5592 || i
.types
[op
].bitfield
.regymm
5593 || i
.types
[op
].bitfield
.sreg2
5594 || i
.types
[op
].bitfield
.sreg3
5595 || i
.types
[op
].bitfield
.control
5596 || i
.types
[op
].bitfield
.debug
5597 || i
.types
[op
].bitfield
.test
)
5602 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5604 /* For instructions with VexNDS, the register-only
5605 source operand is encoded in VEX prefix. */
5606 gas_assert (mem
!= (unsigned int) ~0);
5611 gas_assert (op
< i
.operands
);
5616 gas_assert (vex_reg
< i
.operands
);
5619 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5621 /* For instructions with VexNDD, there should be
5622 no memory operand and the register destination
5623 is encoded in VEX prefix. */
5624 gas_assert (i
.mem_operands
== 0
5625 && (op
+ 2) == i
.operands
);
5629 gas_assert (op
< i
.operands
);
5631 if (vex_reg
!= (unsigned int) ~0)
5633 gas_assert (i
.reg_operands
== 2);
5635 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5637 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5641 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5644 /* Don't set OP operand twice. */
5647 /* If there is an extension opcode to put here, the
5648 register number must be put into the regmem field. */
5649 if (i
.tm
.extension_opcode
!= None
)
5651 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5652 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5657 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5658 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5663 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5664 must set it to 3 to indicate this is a register operand
5665 in the regmem field. */
5666 if (!i
.mem_operands
)
5670 /* Fill in i.rm.reg field with extension opcode (if any). */
5671 if (i
.tm
.extension_opcode
!= None
)
5672 i
.rm
.reg
= i
.tm
.extension_opcode
;
5678 output_branch (void)
5683 relax_substateT subtype
;
5688 if (flag_code
== CODE_16BIT
)
5692 if (i
.prefix
[DATA_PREFIX
] != 0)
5698 /* Pentium4 branch hints. */
5699 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5700 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5705 if (i
.prefix
[REX_PREFIX
] != 0)
5711 if (i
.prefixes
!= 0 && !intel_syntax
)
5712 as_warn (_("skipping prefixes on this instruction"));
5714 /* It's always a symbol; End frag & setup for relax.
5715 Make sure there is enough room in this frag for the largest
5716 instruction we may generate in md_convert_frag. This is 2
5717 bytes for the opcode and room for the prefix and largest
5719 frag_grow (prefix
+ 2 + 4);
5720 /* Prefix and 1 opcode byte go in fr_fix. */
5721 p
= frag_more (prefix
+ 1);
5722 if (i
.prefix
[DATA_PREFIX
] != 0)
5723 *p
++ = DATA_PREFIX_OPCODE
;
5724 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5725 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5726 *p
++ = i
.prefix
[SEG_PREFIX
];
5727 if (i
.prefix
[REX_PREFIX
] != 0)
5728 *p
++ = i
.prefix
[REX_PREFIX
];
5729 *p
= i
.tm
.base_opcode
;
5731 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5732 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5733 else if (cpu_arch_flags
.bitfield
.cpui386
)
5734 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5736 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5739 sym
= i
.op
[0].disps
->X_add_symbol
;
5740 off
= i
.op
[0].disps
->X_add_number
;
5742 if (i
.op
[0].disps
->X_op
!= O_constant
5743 && i
.op
[0].disps
->X_op
!= O_symbol
)
5745 /* Handle complex expressions. */
5746 sym
= make_expr_symbol (i
.op
[0].disps
);
5750 /* 1 possible extra opcode + 4 byte displacement go in var part.
5751 Pass reloc in fr_var. */
5752 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5762 if (i
.tm
.opcode_modifier
.jumpbyte
)
5764 /* This is a loop or jecxz type instruction. */
5766 if (i
.prefix
[ADDR_PREFIX
] != 0)
5768 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5771 /* Pentium4 branch hints. */
5772 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5773 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5775 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5784 if (flag_code
== CODE_16BIT
)
5787 if (i
.prefix
[DATA_PREFIX
] != 0)
5789 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5799 if (i
.prefix
[REX_PREFIX
] != 0)
5801 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5805 if (i
.prefixes
!= 0 && !intel_syntax
)
5806 as_warn (_("skipping prefixes on this instruction"));
5808 p
= frag_more (1 + size
);
5809 *p
++ = i
.tm
.base_opcode
;
5811 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5812 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5814 /* All jumps handled here are signed, but don't use a signed limit
5815 check for 32 and 16 bit jumps as we want to allow wrap around at
5816 4G and 64k respectively. */
5818 fixP
->fx_signed
= 1;
5822 output_interseg_jump (void)
5830 if (flag_code
== CODE_16BIT
)
5834 if (i
.prefix
[DATA_PREFIX
] != 0)
5840 if (i
.prefix
[REX_PREFIX
] != 0)
5850 if (i
.prefixes
!= 0 && !intel_syntax
)
5851 as_warn (_("skipping prefixes on this instruction"));
5853 /* 1 opcode; 2 segment; offset */
5854 p
= frag_more (prefix
+ 1 + 2 + size
);
5856 if (i
.prefix
[DATA_PREFIX
] != 0)
5857 *p
++ = DATA_PREFIX_OPCODE
;
5859 if (i
.prefix
[REX_PREFIX
] != 0)
5860 *p
++ = i
.prefix
[REX_PREFIX
];
5862 *p
++ = i
.tm
.base_opcode
;
5863 if (i
.op
[1].imms
->X_op
== O_constant
)
5865 offsetT n
= i
.op
[1].imms
->X_add_number
;
5868 && !fits_in_unsigned_word (n
)
5869 && !fits_in_signed_word (n
))
5871 as_bad (_("16-bit jump out of range"));
5874 md_number_to_chars (p
, n
, size
);
5877 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5878 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5879 if (i
.op
[0].imms
->X_op
!= O_constant
)
5880 as_bad (_("can't handle non absolute segment in `%s'"),
5882 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5888 fragS
*insn_start_frag
;
5889 offsetT insn_start_off
;
5891 /* Tie dwarf2 debug info to the address at the start of the insn.
5892 We can't do this after the insn has been output as the current
5893 frag may have been closed off. eg. by frag_var. */
5894 dwarf2_emit_insn (0);
5896 insn_start_frag
= frag_now
;
5897 insn_start_off
= frag_now_fix ();
5900 if (i
.tm
.opcode_modifier
.jump
)
5902 else if (i
.tm
.opcode_modifier
.jumpbyte
5903 || i
.tm
.opcode_modifier
.jumpdword
)
5905 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5906 output_interseg_jump ();
5909 /* Output normal instructions here. */
5913 unsigned int prefix
;
5915 /* Since the VEX prefix contains the implicit prefix, we don't
5916 need the explicit prefix. */
5917 if (!i
.tm
.opcode_modifier
.vex
)
5919 switch (i
.tm
.opcode_length
)
5922 if (i
.tm
.base_opcode
& 0xff000000)
5924 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5929 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5931 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5932 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5935 if (prefix
!= REPE_PREFIX_OPCODE
5936 || (i
.prefix
[REP_PREFIX
]
5937 != REPE_PREFIX_OPCODE
))
5938 add_prefix (prefix
);
5941 add_prefix (prefix
);
5950 /* The prefix bytes. */
5951 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5953 FRAG_APPEND_1_CHAR (*q
);
5956 if (i
.tm
.opcode_modifier
.vex
)
5958 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5963 /* REX byte is encoded in VEX prefix. */
5967 FRAG_APPEND_1_CHAR (*q
);
5970 /* There should be no other prefixes for instructions
5975 /* Now the VEX prefix. */
5976 p
= frag_more (i
.vex
.length
);
5977 for (j
= 0; j
< i
.vex
.length
; j
++)
5978 p
[j
] = i
.vex
.bytes
[j
];
5981 /* Now the opcode; be careful about word order here! */
5982 if (i
.tm
.opcode_length
== 1)
5984 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5988 switch (i
.tm
.opcode_length
)
5992 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6002 /* Put out high byte first: can't use md_number_to_chars! */
6003 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6004 *p
= i
.tm
.base_opcode
& 0xff;
6007 /* Now the modrm byte and sib byte (if present). */
6008 if (i
.tm
.opcode_modifier
.modrm
)
6010 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6013 /* If i.rm.regmem == ESP (4)
6014 && i.rm.mode != (Register mode)
6016 ==> need second modrm byte. */
6017 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6019 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6020 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6022 | i
.sib
.scale
<< 6));
6025 if (i
.disp_operands
)
6026 output_disp (insn_start_frag
, insn_start_off
);
6029 output_imm (insn_start_frag
, insn_start_off
);
6035 pi ("" /*line*/, &i
);
6037 #endif /* DEBUG386 */
6040 /* Return the size of the displacement operand N. */
6043 disp_size (unsigned int n
)
6046 if (i
.types
[n
].bitfield
.disp64
)
6048 else if (i
.types
[n
].bitfield
.disp8
)
6050 else if (i
.types
[n
].bitfield
.disp16
)
6055 /* Return the size of the immediate operand N. */
6058 imm_size (unsigned int n
)
6061 if (i
.types
[n
].bitfield
.imm64
)
6063 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6065 else if (i
.types
[n
].bitfield
.imm16
)
6071 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6076 for (n
= 0; n
< i
.operands
; n
++)
6078 if (operand_type_check (i
.types
[n
], disp
))
6080 if (i
.op
[n
].disps
->X_op
== O_constant
)
6082 int size
= disp_size (n
);
6085 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6087 p
= frag_more (size
);
6088 md_number_to_chars (p
, val
, size
);
6092 enum bfd_reloc_code_real reloc_type
;
6093 int size
= disp_size (n
);
6094 int sign
= i
.types
[n
].bitfield
.disp32s
;
6095 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6097 /* We can't have 8 bit displacement here. */
6098 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6100 /* The PC relative address is computed relative
6101 to the instruction boundary, so in case immediate
6102 fields follows, we need to adjust the value. */
6103 if (pcrel
&& i
.imm_operands
)
6108 for (n1
= 0; n1
< i
.operands
; n1
++)
6109 if (operand_type_check (i
.types
[n1
], imm
))
6111 /* Only one immediate is allowed for PC
6112 relative address. */
6113 gas_assert (sz
== 0);
6115 i
.op
[n
].disps
->X_add_number
-= sz
;
6117 /* We should find the immediate. */
6118 gas_assert (sz
!= 0);
6121 p
= frag_more (size
);
6122 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6124 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6125 && (((reloc_type
== BFD_RELOC_32
6126 || reloc_type
== BFD_RELOC_X86_64_32S
6127 || (reloc_type
== BFD_RELOC_64
6129 && (i
.op
[n
].disps
->X_op
== O_symbol
6130 || (i
.op
[n
].disps
->X_op
== O_add
6131 && ((symbol_get_value_expression
6132 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6134 || reloc_type
== BFD_RELOC_32_PCREL
))
6138 if (insn_start_frag
== frag_now
)
6139 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6144 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6145 for (fr
= insn_start_frag
->fr_next
;
6146 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6148 add
+= p
- frag_now
->fr_literal
;
6153 reloc_type
= BFD_RELOC_386_GOTPC
;
6154 i
.op
[n
].imms
->X_add_number
+= add
;
6156 else if (reloc_type
== BFD_RELOC_64
)
6157 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6159 /* Don't do the adjustment for x86-64, as there
6160 the pcrel addressing is relative to the _next_
6161 insn, and that is taken care of in other code. */
6162 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6164 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6165 i
.op
[n
].disps
, pcrel
, reloc_type
);
6172 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6177 for (n
= 0; n
< i
.operands
; n
++)
6179 if (operand_type_check (i
.types
[n
], imm
))
6181 if (i
.op
[n
].imms
->X_op
== O_constant
)
6183 int size
= imm_size (n
);
6186 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6188 p
= frag_more (size
);
6189 md_number_to_chars (p
, val
, size
);
6193 /* Not absolute_section.
6194 Need a 32-bit fixup (don't support 8bit
6195 non-absolute imms). Try to support other
6197 enum bfd_reloc_code_real reloc_type
;
6198 int size
= imm_size (n
);
6201 if (i
.types
[n
].bitfield
.imm32s
6202 && (i
.suffix
== QWORD_MNEM_SUFFIX
6203 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6208 p
= frag_more (size
);
6209 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6211 /* This is tough to explain. We end up with this one if we
6212 * have operands that look like
6213 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6214 * obtain the absolute address of the GOT, and it is strongly
6215 * preferable from a performance point of view to avoid using
6216 * a runtime relocation for this. The actual sequence of
6217 * instructions often look something like:
6222 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6224 * The call and pop essentially return the absolute address
6225 * of the label .L66 and store it in %ebx. The linker itself
6226 * will ultimately change the first operand of the addl so
6227 * that %ebx points to the GOT, but to keep things simple, the
6228 * .o file must have this operand set so that it generates not
6229 * the absolute address of .L66, but the absolute address of
6230 * itself. This allows the linker itself simply treat a GOTPC
6231 * relocation as asking for a pcrel offset to the GOT to be
6232 * added in, and the addend of the relocation is stored in the
6233 * operand field for the instruction itself.
6235 * Our job here is to fix the operand so that it would add
6236 * the correct offset so that %ebx would point to itself. The
6237 * thing that is tricky is that .-.L66 will point to the
6238 * beginning of the instruction, so we need to further modify
6239 * the operand so that it will point to itself. There are
6240 * other cases where you have something like:
6242 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6244 * and here no correction would be required. Internally in
6245 * the assembler we treat operands of this form as not being
6246 * pcrel since the '.' is explicitly mentioned, and I wonder
6247 * whether it would simplify matters to do it this way. Who
6248 * knows. In earlier versions of the PIC patches, the
6249 * pcrel_adjust field was used to store the correction, but
6250 * since the expression is not pcrel, I felt it would be
6251 * confusing to do it this way. */
6253 if ((reloc_type
== BFD_RELOC_32
6254 || reloc_type
== BFD_RELOC_X86_64_32S
6255 || reloc_type
== BFD_RELOC_64
)
6257 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6258 && (i
.op
[n
].imms
->X_op
== O_symbol
6259 || (i
.op
[n
].imms
->X_op
== O_add
6260 && ((symbol_get_value_expression
6261 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6266 if (insn_start_frag
== frag_now
)
6267 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6272 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6273 for (fr
= insn_start_frag
->fr_next
;
6274 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6276 add
+= p
- frag_now
->fr_literal
;
6280 reloc_type
= BFD_RELOC_386_GOTPC
;
6282 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6284 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6285 i
.op
[n
].imms
->X_add_number
+= add
;
6287 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6288 i
.op
[n
].imms
, 0, reloc_type
);
6294 /* x86_cons_fix_new is called via the expression parsing code when a
6295 reloc is needed. We use this hook to get the correct .got reloc. */
6296 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6297 static int cons_sign
= -1;
6300 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6303 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6305 got_reloc
= NO_RELOC
;
6308 if (exp
->X_op
== O_secrel
)
6310 exp
->X_op
= O_symbol
;
6311 r
= BFD_RELOC_32_SECREL
;
6315 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6318 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6319 # define lex_got(reloc, adjust, types) NULL
6321 /* Parse operands of the form
6322 <symbol>@GOTOFF+<nnn>
6323 and similar .plt or .got references.
6325 If we find one, set up the correct relocation in RELOC and copy the
6326 input string, minus the `@GOTOFF' into a malloc'd buffer for
6327 parsing by the calling routine. Return this buffer, and if ADJUST
6328 is non-null set it to the length of the string we removed from the
6329 input line. Otherwise return NULL. */
6331 lex_got (enum bfd_reloc_code_real
*rel
,
6333 i386_operand_type
*types
)
6335 /* Some of the relocations depend on the size of what field is to
6336 be relocated. But in our callers i386_immediate and i386_displacement
6337 we don't yet know the operand size (this will be set by insn
6338 matching). Hence we record the word32 relocation here,
6339 and adjust the reloc according to the real size in reloc(). */
6340 static const struct {
6343 const enum bfd_reloc_code_real rel
[2];
6344 const i386_operand_type types64
;
6346 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6347 BFD_RELOC_X86_64_PLTOFF64
},
6348 OPERAND_TYPE_IMM64
},
6349 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6350 BFD_RELOC_X86_64_PLT32
},
6351 OPERAND_TYPE_IMM32_32S_DISP32
},
6352 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6353 BFD_RELOC_X86_64_GOTPLT64
},
6354 OPERAND_TYPE_IMM64_DISP64
},
6355 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6356 BFD_RELOC_X86_64_GOTOFF64
},
6357 OPERAND_TYPE_IMM64_DISP64
},
6358 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6359 BFD_RELOC_X86_64_GOTPCREL
},
6360 OPERAND_TYPE_IMM32_32S_DISP32
},
6361 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6362 BFD_RELOC_X86_64_TLSGD
},
6363 OPERAND_TYPE_IMM32_32S_DISP32
},
6364 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6365 _dummy_first_bfd_reloc_code_real
},
6366 OPERAND_TYPE_NONE
},
6367 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6368 BFD_RELOC_X86_64_TLSLD
},
6369 OPERAND_TYPE_IMM32_32S_DISP32
},
6370 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6371 BFD_RELOC_X86_64_GOTTPOFF
},
6372 OPERAND_TYPE_IMM32_32S_DISP32
},
6373 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6374 BFD_RELOC_X86_64_TPOFF32
},
6375 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6376 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6377 _dummy_first_bfd_reloc_code_real
},
6378 OPERAND_TYPE_NONE
},
6379 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6380 BFD_RELOC_X86_64_DTPOFF32
},
6381 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6382 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6383 _dummy_first_bfd_reloc_code_real
},
6384 OPERAND_TYPE_NONE
},
6385 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6386 _dummy_first_bfd_reloc_code_real
},
6387 OPERAND_TYPE_NONE
},
6388 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6389 BFD_RELOC_X86_64_GOT32
},
6390 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6391 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6392 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6393 OPERAND_TYPE_IMM32_32S_DISP32
},
6394 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6395 BFD_RELOC_X86_64_TLSDESC_CALL
},
6396 OPERAND_TYPE_IMM32_32S_DISP32
},
6404 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6405 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6408 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6410 int len
= gotrel
[j
].len
;
6411 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6413 if (gotrel
[j
].rel
[object_64bit
] != 0)
6416 char *tmpbuf
, *past_reloc
;
6418 *rel
= gotrel
[j
].rel
[object_64bit
];
6424 if (flag_code
!= CODE_64BIT
)
6426 types
->bitfield
.imm32
= 1;
6427 types
->bitfield
.disp32
= 1;
6430 *types
= gotrel
[j
].types64
;
6433 if (GOT_symbol
== NULL
)
6434 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6436 /* The length of the first part of our input line. */
6437 first
= cp
- input_line_pointer
;
6439 /* The second part goes from after the reloc token until
6440 (and including) an end_of_line char or comma. */
6441 past_reloc
= cp
+ 1 + len
;
6443 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6445 second
= cp
+ 1 - past_reloc
;
6447 /* Allocate and copy string. The trailing NUL shouldn't
6448 be necessary, but be safe. */
6449 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6450 memcpy (tmpbuf
, input_line_pointer
, first
);
6451 if (second
!= 0 && *past_reloc
!= ' ')
6452 /* Replace the relocation token with ' ', so that
6453 errors like foo@GOTOFF1 will be detected. */
6454 tmpbuf
[first
++] = ' ';
6455 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6456 tmpbuf
[first
+ second
] = '\0';
6460 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6461 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6466 /* Might be a symbol version string. Don't as_bad here. */
6471 x86_cons (expressionS
*exp
, int size
)
6473 intel_syntax
= -intel_syntax
;
6476 if (size
== 4 || (object_64bit
&& size
== 8))
6478 /* Handle @GOTOFF and the like in an expression. */
6480 char *gotfree_input_line
;
6483 save
= input_line_pointer
;
6484 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6485 if (gotfree_input_line
)
6486 input_line_pointer
= gotfree_input_line
;
6490 if (gotfree_input_line
)
6492 /* expression () has merrily parsed up to the end of line,
6493 or a comma - in the wrong buffer. Transfer how far
6494 input_line_pointer has moved to the right buffer. */
6495 input_line_pointer
= (save
6496 + (input_line_pointer
- gotfree_input_line
)
6498 free (gotfree_input_line
);
6499 if (exp
->X_op
== O_constant
6500 || exp
->X_op
== O_absent
6501 || exp
->X_op
== O_illegal
6502 || exp
->X_op
== O_register
6503 || exp
->X_op
== O_big
)
6505 char c
= *input_line_pointer
;
6506 *input_line_pointer
= 0;
6507 as_bad (_("missing or invalid expression `%s'"), save
);
6508 *input_line_pointer
= c
;
6515 intel_syntax
= -intel_syntax
;
6518 i386_intel_simplify (exp
);
6523 signed_cons (int size
)
6525 if (flag_code
== CODE_64BIT
)
6533 pe_directive_secrel (dummy
)
6534 int dummy ATTRIBUTE_UNUSED
;
6541 if (exp
.X_op
== O_symbol
)
6542 exp
.X_op
= O_secrel
;
6544 emit_expr (&exp
, 4);
6546 while (*input_line_pointer
++ == ',');
6548 input_line_pointer
--;
6549 demand_empty_rest_of_line ();
6554 i386_immediate (char *imm_start
)
6556 char *save_input_line_pointer
;
6557 char *gotfree_input_line
;
6560 i386_operand_type types
;
6562 operand_type_set (&types
, ~0);
6564 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6566 as_bad (_("at most %d immediate operands are allowed"),
6567 MAX_IMMEDIATE_OPERANDS
);
6571 exp
= &im_expressions
[i
.imm_operands
++];
6572 i
.op
[this_operand
].imms
= exp
;
6574 if (is_space_char (*imm_start
))
6577 save_input_line_pointer
= input_line_pointer
;
6578 input_line_pointer
= imm_start
;
6580 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6581 if (gotfree_input_line
)
6582 input_line_pointer
= gotfree_input_line
;
6584 exp_seg
= expression (exp
);
6587 if (*input_line_pointer
)
6588 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6590 input_line_pointer
= save_input_line_pointer
;
6591 if (gotfree_input_line
)
6593 free (gotfree_input_line
);
6595 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6596 exp
->X_op
= O_illegal
;
6599 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6603 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6604 i386_operand_type types
, const char *imm_start
)
6606 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6609 as_bad (_("missing or invalid immediate expression `%s'"),
6613 else if (exp
->X_op
== O_constant
)
6615 /* Size it properly later. */
6616 i
.types
[this_operand
].bitfield
.imm64
= 1;
6617 /* If BFD64, sign extend val. */
6618 if (!use_rela_relocations
6619 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6621 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6623 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6624 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6625 && exp_seg
!= absolute_section
6626 && exp_seg
!= text_section
6627 && exp_seg
!= data_section
6628 && exp_seg
!= bss_section
6629 && exp_seg
!= undefined_section
6630 && !bfd_is_com_section (exp_seg
))
6632 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6636 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6639 as_bad (_("illegal immediate register operand %s"), imm_start
);
6644 /* This is an address. The size of the address will be
6645 determined later, depending on destination register,
6646 suffix, or the default for the section. */
6647 i
.types
[this_operand
].bitfield
.imm8
= 1;
6648 i
.types
[this_operand
].bitfield
.imm16
= 1;
6649 i
.types
[this_operand
].bitfield
.imm32
= 1;
6650 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6651 i
.types
[this_operand
].bitfield
.imm64
= 1;
6652 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6660 i386_scale (char *scale
)
6663 char *save
= input_line_pointer
;
6665 input_line_pointer
= scale
;
6666 val
= get_absolute_expression ();
6671 i
.log2_scale_factor
= 0;
6674 i
.log2_scale_factor
= 1;
6677 i
.log2_scale_factor
= 2;
6680 i
.log2_scale_factor
= 3;
6684 char sep
= *input_line_pointer
;
6686 *input_line_pointer
= '\0';
6687 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6689 *input_line_pointer
= sep
;
6690 input_line_pointer
= save
;
6694 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6696 as_warn (_("scale factor of %d without an index register"),
6697 1 << i
.log2_scale_factor
);
6698 i
.log2_scale_factor
= 0;
6700 scale
= input_line_pointer
;
6701 input_line_pointer
= save
;
6706 i386_displacement (char *disp_start
, char *disp_end
)
6710 char *save_input_line_pointer
;
6711 char *gotfree_input_line
;
6713 i386_operand_type bigdisp
, types
= anydisp
;
6716 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6718 as_bad (_("at most %d displacement operands are allowed"),
6719 MAX_MEMORY_OPERANDS
);
6723 operand_type_set (&bigdisp
, 0);
6724 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6725 || (!current_templates
->start
->opcode_modifier
.jump
6726 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6728 bigdisp
.bitfield
.disp32
= 1;
6729 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6730 if (flag_code
== CODE_64BIT
)
6734 bigdisp
.bitfield
.disp32s
= 1;
6735 bigdisp
.bitfield
.disp64
= 1;
6738 else if ((flag_code
== CODE_16BIT
) ^ override
)
6740 bigdisp
.bitfield
.disp32
= 0;
6741 bigdisp
.bitfield
.disp16
= 1;
6746 /* For PC-relative branches, the width of the displacement
6747 is dependent upon data size, not address size. */
6748 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6749 if (flag_code
== CODE_64BIT
)
6751 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6752 bigdisp
.bitfield
.disp16
= 1;
6755 bigdisp
.bitfield
.disp32
= 1;
6756 bigdisp
.bitfield
.disp32s
= 1;
6762 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6764 : LONG_MNEM_SUFFIX
));
6765 bigdisp
.bitfield
.disp32
= 1;
6766 if ((flag_code
== CODE_16BIT
) ^ override
)
6768 bigdisp
.bitfield
.disp32
= 0;
6769 bigdisp
.bitfield
.disp16
= 1;
6773 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6776 exp
= &disp_expressions
[i
.disp_operands
];
6777 i
.op
[this_operand
].disps
= exp
;
6779 save_input_line_pointer
= input_line_pointer
;
6780 input_line_pointer
= disp_start
;
6781 END_STRING_AND_SAVE (disp_end
);
6783 #ifndef GCC_ASM_O_HACK
6784 #define GCC_ASM_O_HACK 0
6787 END_STRING_AND_SAVE (disp_end
+ 1);
6788 if (i
.types
[this_operand
].bitfield
.baseIndex
6789 && displacement_string_end
[-1] == '+')
6791 /* This hack is to avoid a warning when using the "o"
6792 constraint within gcc asm statements.
6795 #define _set_tssldt_desc(n,addr,limit,type) \
6796 __asm__ __volatile__ ( \
6798 "movw %w1,2+%0\n\t" \
6800 "movb %b1,4+%0\n\t" \
6801 "movb %4,5+%0\n\t" \
6802 "movb $0,6+%0\n\t" \
6803 "movb %h1,7+%0\n\t" \
6805 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6807 This works great except that the output assembler ends
6808 up looking a bit weird if it turns out that there is
6809 no offset. You end up producing code that looks like:
6822 So here we provide the missing zero. */
6824 *displacement_string_end
= '0';
6827 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6828 if (gotfree_input_line
)
6829 input_line_pointer
= gotfree_input_line
;
6831 exp_seg
= expression (exp
);
6834 if (*input_line_pointer
)
6835 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6837 RESTORE_END_STRING (disp_end
+ 1);
6839 input_line_pointer
= save_input_line_pointer
;
6840 if (gotfree_input_line
)
6842 free (gotfree_input_line
);
6844 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6845 exp
->X_op
= O_illegal
;
6848 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6850 RESTORE_END_STRING (disp_end
);
6856 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6857 i386_operand_type types
, const char *disp_start
)
6859 i386_operand_type bigdisp
;
6862 /* We do this to make sure that the section symbol is in
6863 the symbol table. We will ultimately change the relocation
6864 to be relative to the beginning of the section. */
6865 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6866 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6867 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6869 if (exp
->X_op
!= O_symbol
)
6872 if (S_IS_LOCAL (exp
->X_add_symbol
)
6873 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6874 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6875 exp
->X_op
= O_subtract
;
6876 exp
->X_op_symbol
= GOT_symbol
;
6877 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6878 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6879 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6880 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6882 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6885 else if (exp
->X_op
== O_absent
6886 || exp
->X_op
== O_illegal
6887 || exp
->X_op
== O_big
)
6890 as_bad (_("missing or invalid displacement expression `%s'"),
6895 else if (flag_code
== CODE_64BIT
6896 && !i
.prefix
[ADDR_PREFIX
]
6897 && exp
->X_op
== O_constant
)
6899 /* Since displacement is signed extended to 64bit, don't allow
6900 disp32 and turn off disp32s if they are out of range. */
6901 i
.types
[this_operand
].bitfield
.disp32
= 0;
6902 if (!fits_in_signed_long (exp
->X_add_number
))
6904 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6905 if (i
.types
[this_operand
].bitfield
.baseindex
)
6907 as_bad (_("0x%lx out range of signed 32bit displacement"),
6908 (long) exp
->X_add_number
);
6914 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6915 else if (exp
->X_op
!= O_constant
6916 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6917 && exp_seg
!= absolute_section
6918 && exp_seg
!= text_section
6919 && exp_seg
!= data_section
6920 && exp_seg
!= bss_section
6921 && exp_seg
!= undefined_section
6922 && !bfd_is_com_section (exp_seg
))
6924 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6929 /* Check if this is a displacement only operand. */
6930 bigdisp
= i
.types
[this_operand
];
6931 bigdisp
.bitfield
.disp8
= 0;
6932 bigdisp
.bitfield
.disp16
= 0;
6933 bigdisp
.bitfield
.disp32
= 0;
6934 bigdisp
.bitfield
.disp32s
= 0;
6935 bigdisp
.bitfield
.disp64
= 0;
6936 if (operand_type_all_zero (&bigdisp
))
6937 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6943 /* Make sure the memory operand we've been dealt is valid.
6944 Return 1 on success, 0 on a failure. */
6947 i386_index_check (const char *operand_string
)
6950 const char *kind
= "base/index";
6951 #if INFER_ADDR_PREFIX
6957 if (current_templates
->start
->opcode_modifier
.isstring
6958 && !current_templates
->start
->opcode_modifier
.immext
6959 && (current_templates
->end
[-1].opcode_modifier
.isstring
6962 /* Memory operands of string insns are special in that they only allow
6963 a single register (rDI, rSI, or rBX) as their memory address. */
6964 unsigned int expected
;
6966 kind
= "string address";
6968 if (current_templates
->start
->opcode_modifier
.w
)
6970 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6972 if (!type
.bitfield
.baseindex
6973 || ((!i
.mem_operands
!= !intel_syntax
)
6974 && current_templates
->end
[-1].operand_types
[1]
6975 .bitfield
.baseindex
))
6976 type
= current_templates
->end
[-1].operand_types
[1];
6977 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6980 expected
= 3 /* rBX */;
6982 if (!i
.base_reg
|| i
.index_reg
6983 || operand_type_check (i
.types
[this_operand
], disp
))
6985 else if (!(flag_code
== CODE_64BIT
6986 ? i
.prefix
[ADDR_PREFIX
]
6987 ? i
.base_reg
->reg_type
.bitfield
.reg32
6988 : i
.base_reg
->reg_type
.bitfield
.reg64
6989 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6990 ? i
.base_reg
->reg_type
.bitfield
.reg32
6991 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6993 else if (i
.base_reg
->reg_num
!= expected
)
7000 for (j
= 0; j
< i386_regtab_size
; ++j
)
7001 if ((flag_code
== CODE_64BIT
7002 ? i
.prefix
[ADDR_PREFIX
]
7003 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7004 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7005 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7006 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7007 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7008 && i386_regtab
[j
].reg_num
== expected
)
7010 gas_assert (j
< i386_regtab_size
);
7011 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7013 intel_syntax
? '[' : '(',
7015 i386_regtab
[j
].reg_name
,
7016 intel_syntax
? ']' : ')');
7020 else if (flag_code
== CODE_64BIT
)
7023 && ((i
.prefix
[ADDR_PREFIX
] == 0
7024 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7025 || (i
.prefix
[ADDR_PREFIX
]
7026 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7028 || i
.base_reg
->reg_num
!=
7029 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7031 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7032 || (i
.prefix
[ADDR_PREFIX
] == 0
7033 && i
.index_reg
->reg_num
!= RegRiz
7034 && !i
.index_reg
->reg_type
.bitfield
.reg64
7036 || (i
.prefix
[ADDR_PREFIX
]
7037 && i
.index_reg
->reg_num
!= RegEiz
7038 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7043 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7047 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7048 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7050 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7051 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7053 && i
.base_reg
->reg_num
< 6
7054 && i
.index_reg
->reg_num
>= 6
7055 && i
.log2_scale_factor
== 0))))
7062 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7064 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7065 && i
.index_reg
->reg_num
!= RegEiz
)
7066 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7072 #if INFER_ADDR_PREFIX
7073 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7075 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7077 /* Change the size of any displacement too. At most one of
7078 Disp16 or Disp32 is set.
7079 FIXME. There doesn't seem to be any real need for separate
7080 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7081 Removing them would probably clean up the code quite a lot. */
7082 if (flag_code
!= CODE_64BIT
7083 && (i
.types
[this_operand
].bitfield
.disp16
7084 || i
.types
[this_operand
].bitfield
.disp32
))
7085 i
.types
[this_operand
]
7086 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7091 as_bad (_("`%s' is not a valid %s expression"),
7096 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7098 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7099 ? flag_code
== CODE_32BIT
7108 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7112 i386_att_operand (char *operand_string
)
7116 char *op_string
= operand_string
;
7118 if (is_space_char (*op_string
))
7121 /* We check for an absolute prefix (differentiating,
7122 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7123 if (*op_string
== ABSOLUTE_PREFIX
)
7126 if (is_space_char (*op_string
))
7128 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7131 /* Check if operand is a register. */
7132 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7134 i386_operand_type temp
;
7136 /* Check for a segment override by searching for ':' after a
7137 segment register. */
7139 if (is_space_char (*op_string
))
7141 if (*op_string
== ':'
7142 && (r
->reg_type
.bitfield
.sreg2
7143 || r
->reg_type
.bitfield
.sreg3
))
7148 i
.seg
[i
.mem_operands
] = &es
;
7151 i
.seg
[i
.mem_operands
] = &cs
;
7154 i
.seg
[i
.mem_operands
] = &ss
;
7157 i
.seg
[i
.mem_operands
] = &ds
;
7160 i
.seg
[i
.mem_operands
] = &fs
;
7163 i
.seg
[i
.mem_operands
] = &gs
;
7167 /* Skip the ':' and whitespace. */
7169 if (is_space_char (*op_string
))
7172 if (!is_digit_char (*op_string
)
7173 && !is_identifier_char (*op_string
)
7174 && *op_string
!= '('
7175 && *op_string
!= ABSOLUTE_PREFIX
)
7177 as_bad (_("bad memory operand `%s'"), op_string
);
7180 /* Handle case of %es:*foo. */
7181 if (*op_string
== ABSOLUTE_PREFIX
)
7184 if (is_space_char (*op_string
))
7186 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7188 goto do_memory_reference
;
7192 as_bad (_("junk `%s' after register"), op_string
);
7196 temp
.bitfield
.baseindex
= 0;
7197 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7199 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7200 i
.op
[this_operand
].regs
= r
;
7203 else if (*op_string
== REGISTER_PREFIX
)
7205 as_bad (_("bad register name `%s'"), op_string
);
7208 else if (*op_string
== IMMEDIATE_PREFIX
)
7211 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7213 as_bad (_("immediate operand illegal with absolute jump"));
7216 if (!i386_immediate (op_string
))
7219 else if (is_digit_char (*op_string
)
7220 || is_identifier_char (*op_string
)
7221 || *op_string
== '(')
7223 /* This is a memory reference of some sort. */
7226 /* Start and end of displacement string expression (if found). */
7227 char *displacement_string_start
;
7228 char *displacement_string_end
;
7230 do_memory_reference
:
7231 if ((i
.mem_operands
== 1
7232 && !current_templates
->start
->opcode_modifier
.isstring
)
7233 || i
.mem_operands
== 2)
7235 as_bad (_("too many memory references for `%s'"),
7236 current_templates
->start
->name
);
7240 /* Check for base index form. We detect the base index form by
7241 looking for an ')' at the end of the operand, searching
7242 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7244 base_string
= op_string
+ strlen (op_string
);
7247 if (is_space_char (*base_string
))
7250 /* If we only have a displacement, set-up for it to be parsed later. */
7251 displacement_string_start
= op_string
;
7252 displacement_string_end
= base_string
+ 1;
7254 if (*base_string
== ')')
7257 unsigned int parens_balanced
= 1;
7258 /* We've already checked that the number of left & right ()'s are
7259 equal, so this loop will not be infinite. */
7263 if (*base_string
== ')')
7265 if (*base_string
== '(')
7268 while (parens_balanced
);
7270 temp_string
= base_string
;
7272 /* Skip past '(' and whitespace. */
7274 if (is_space_char (*base_string
))
7277 if (*base_string
== ','
7278 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7281 displacement_string_end
= temp_string
;
7283 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7287 base_string
= end_op
;
7288 if (is_space_char (*base_string
))
7292 /* There may be an index reg or scale factor here. */
7293 if (*base_string
== ',')
7296 if (is_space_char (*base_string
))
7299 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7302 base_string
= end_op
;
7303 if (is_space_char (*base_string
))
7305 if (*base_string
== ',')
7308 if (is_space_char (*base_string
))
7311 else if (*base_string
!= ')')
7313 as_bad (_("expecting `,' or `)' "
7314 "after index register in `%s'"),
7319 else if (*base_string
== REGISTER_PREFIX
)
7321 as_bad (_("bad register name `%s'"), base_string
);
7325 /* Check for scale factor. */
7326 if (*base_string
!= ')')
7328 char *end_scale
= i386_scale (base_string
);
7333 base_string
= end_scale
;
7334 if (is_space_char (*base_string
))
7336 if (*base_string
!= ')')
7338 as_bad (_("expecting `)' "
7339 "after scale factor in `%s'"),
7344 else if (!i
.index_reg
)
7346 as_bad (_("expecting index register or scale factor "
7347 "after `,'; got '%c'"),
7352 else if (*base_string
!= ')')
7354 as_bad (_("expecting `,' or `)' "
7355 "after base register in `%s'"),
7360 else if (*base_string
== REGISTER_PREFIX
)
7362 as_bad (_("bad register name `%s'"), base_string
);
7367 /* If there's an expression beginning the operand, parse it,
7368 assuming displacement_string_start and
7369 displacement_string_end are meaningful. */
7370 if (displacement_string_start
!= displacement_string_end
)
7372 if (!i386_displacement (displacement_string_start
,
7373 displacement_string_end
))
7377 /* Special case for (%dx) while doing input/output op. */
7379 && operand_type_equal (&i
.base_reg
->reg_type
,
7380 ®16_inoutportreg
)
7382 && i
.log2_scale_factor
== 0
7383 && i
.seg
[i
.mem_operands
] == 0
7384 && !operand_type_check (i
.types
[this_operand
], disp
))
7386 i
.types
[this_operand
] = inoutportreg
;
7390 if (i386_index_check (operand_string
) == 0)
7392 i
.types
[this_operand
].bitfield
.mem
= 1;
7397 /* It's not a memory operand; argh! */
7398 as_bad (_("invalid char %s beginning operand %d `%s'"),
7399 output_invalid (*op_string
),
7404 return 1; /* Normal return. */
7407 /* md_estimate_size_before_relax()
7409 Called just before relax() for rs_machine_dependent frags. The x86
7410 assembler uses these frags to handle variable size jump
7413 Any symbol that is now undefined will not become defined.
7414 Return the correct fr_subtype in the frag.
7415 Return the initial "guess for variable size of frag" to caller.
7416 The guess is actually the growth beyond the fixed part. Whatever
7417 we do to grow the fixed or variable part contributes to our
7421 md_estimate_size_before_relax (fragP
, segment
)
7425 /* We've already got fragP->fr_subtype right; all we have to do is
7426 check for un-relaxable symbols. On an ELF system, we can't relax
7427 an externally visible symbol, because it may be overridden by a
7429 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7430 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7432 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7433 || S_IS_WEAK (fragP
->fr_symbol
)
7434 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7435 & BSF_GNU_INDIRECT_FUNCTION
))))
7437 #if defined (OBJ_COFF) && defined (TE_PE)
7438 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7439 && S_IS_WEAK (fragP
->fr_symbol
))
7443 /* Symbol is undefined in this segment, or we need to keep a
7444 reloc so that weak symbols can be overridden. */
7445 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7446 enum bfd_reloc_code_real reloc_type
;
7447 unsigned char *opcode
;
7450 if (fragP
->fr_var
!= NO_RELOC
)
7451 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7453 reloc_type
= BFD_RELOC_16_PCREL
;
7455 reloc_type
= BFD_RELOC_32_PCREL
;
7457 old_fr_fix
= fragP
->fr_fix
;
7458 opcode
= (unsigned char *) fragP
->fr_opcode
;
7460 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7463 /* Make jmp (0xeb) a (d)word displacement jump. */
7465 fragP
->fr_fix
+= size
;
7466 fix_new (fragP
, old_fr_fix
, size
,
7468 fragP
->fr_offset
, 1,
7474 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7476 /* Negate the condition, and branch past an
7477 unconditional jump. */
7480 /* Insert an unconditional jump. */
7482 /* We added two extra opcode bytes, and have a two byte
7484 fragP
->fr_fix
+= 2 + 2;
7485 fix_new (fragP
, old_fr_fix
+ 2, 2,
7487 fragP
->fr_offset
, 1,
7494 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7499 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7501 fragP
->fr_offset
, 1,
7503 fixP
->fx_signed
= 1;
7507 /* This changes the byte-displacement jump 0x7N
7508 to the (d)word-displacement jump 0x0f,0x8N. */
7509 opcode
[1] = opcode
[0] + 0x10;
7510 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7511 /* We've added an opcode byte. */
7512 fragP
->fr_fix
+= 1 + size
;
7513 fix_new (fragP
, old_fr_fix
+ 1, size
,
7515 fragP
->fr_offset
, 1,
7520 BAD_CASE (fragP
->fr_subtype
);
7524 return fragP
->fr_fix
- old_fr_fix
;
7527 /* Guess size depending on current relax state. Initially the relax
7528 state will correspond to a short jump and we return 1, because
7529 the variable part of the frag (the branch offset) is one byte
7530 long. However, we can relax a section more than once and in that
7531 case we must either set fr_subtype back to the unrelaxed state,
7532 or return the value for the appropriate branch. */
7533 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7536 /* Called after relax() is finished.
7538 In: Address of frag.
7539 fr_type == rs_machine_dependent.
7540 fr_subtype is what the address relaxed to.
7542 Out: Any fixSs and constants are set up.
7543 Caller will turn frag into a ".space 0". */
7546 md_convert_frag (abfd
, sec
, fragP
)
7547 bfd
*abfd ATTRIBUTE_UNUSED
;
7548 segT sec ATTRIBUTE_UNUSED
;
7551 unsigned char *opcode
;
7552 unsigned char *where_to_put_displacement
= NULL
;
7553 offsetT target_address
;
7554 offsetT opcode_address
;
7555 unsigned int extension
= 0;
7556 offsetT displacement_from_opcode_start
;
7558 opcode
= (unsigned char *) fragP
->fr_opcode
;
7560 /* Address we want to reach in file space. */
7561 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7563 /* Address opcode resides at in file space. */
7564 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7566 /* Displacement from opcode start to fill into instruction. */
7567 displacement_from_opcode_start
= target_address
- opcode_address
;
7569 if ((fragP
->fr_subtype
& BIG
) == 0)
7571 /* Don't have to change opcode. */
7572 extension
= 1; /* 1 opcode + 1 displacement */
7573 where_to_put_displacement
= &opcode
[1];
7577 if (no_cond_jump_promotion
7578 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7579 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7580 _("long jump required"));
7582 switch (fragP
->fr_subtype
)
7584 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7585 extension
= 4; /* 1 opcode + 4 displacement */
7587 where_to_put_displacement
= &opcode
[1];
7590 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7591 extension
= 2; /* 1 opcode + 2 displacement */
7593 where_to_put_displacement
= &opcode
[1];
7596 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7597 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7598 extension
= 5; /* 2 opcode + 4 displacement */
7599 opcode
[1] = opcode
[0] + 0x10;
7600 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7601 where_to_put_displacement
= &opcode
[2];
7604 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7605 extension
= 3; /* 2 opcode + 2 displacement */
7606 opcode
[1] = opcode
[0] + 0x10;
7607 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7608 where_to_put_displacement
= &opcode
[2];
7611 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7616 where_to_put_displacement
= &opcode
[3];
7620 BAD_CASE (fragP
->fr_subtype
);
7625 /* If size if less then four we are sure that the operand fits,
7626 but if it's 4, then it could be that the displacement is larger
7628 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7630 && ((addressT
) (displacement_from_opcode_start
- extension
7631 + ((addressT
) 1 << 31))
7632 > (((addressT
) 2 << 31) - 1)))
7634 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7635 _("jump target out of range"));
7636 /* Make us emit 0. */
7637 displacement_from_opcode_start
= extension
;
7639 /* Now put displacement after opcode. */
7640 md_number_to_chars ((char *) where_to_put_displacement
,
7641 (valueT
) (displacement_from_opcode_start
- extension
),
7642 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7643 fragP
->fr_fix
+= extension
;
7646 /* Apply a fixup (fixS) to segment data, once it has been determined
7647 by our caller that we have all the info we need to fix it up.
7649 On the 386, immediates, displacements, and data pointers are all in
7650 the same (little-endian) format, so we don't need to care about which
7654 md_apply_fix (fixP
, valP
, seg
)
7655 /* The fix we're to put in. */
7657 /* Pointer to the value of the bits. */
7659 /* Segment fix is from. */
7660 segT seg ATTRIBUTE_UNUSED
;
7662 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7663 valueT value
= *valP
;
7665 #if !defined (TE_Mach)
7668 switch (fixP
->fx_r_type
)
7674 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7677 case BFD_RELOC_X86_64_32S
:
7678 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7681 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7684 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7689 if (fixP
->fx_addsy
!= NULL
7690 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7691 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7692 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7693 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7694 && !use_rela_relocations
)
7696 /* This is a hack. There should be a better way to handle this.
7697 This covers for the fact that bfd_install_relocation will
7698 subtract the current location (for partial_inplace, PC relative
7699 relocations); see more below. */
7703 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7706 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7708 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7711 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7714 || (symbol_section_p (fixP
->fx_addsy
)
7715 && sym_seg
!= absolute_section
))
7716 && !generic_force_reloc (fixP
))
7718 /* Yes, we add the values in twice. This is because
7719 bfd_install_relocation subtracts them out again. I think
7720 bfd_install_relocation is broken, but I don't dare change
7722 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7726 #if defined (OBJ_COFF) && defined (TE_PE)
7727 /* For some reason, the PE format does not store a
7728 section address offset for a PC relative symbol. */
7729 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7730 || S_IS_WEAK (fixP
->fx_addsy
))
7731 value
+= md_pcrel_from (fixP
);
7734 #if defined (OBJ_COFF) && defined (TE_PE)
7735 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7737 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7741 /* Fix a few things - the dynamic linker expects certain values here,
7742 and we must not disappoint it. */
7743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7744 if (IS_ELF
&& fixP
->fx_addsy
)
7745 switch (fixP
->fx_r_type
)
7747 case BFD_RELOC_386_PLT32
:
7748 case BFD_RELOC_X86_64_PLT32
:
7749 /* Make the jump instruction point to the address of the operand. At
7750 runtime we merely add the offset to the actual PLT entry. */
7754 case BFD_RELOC_386_TLS_GD
:
7755 case BFD_RELOC_386_TLS_LDM
:
7756 case BFD_RELOC_386_TLS_IE_32
:
7757 case BFD_RELOC_386_TLS_IE
:
7758 case BFD_RELOC_386_TLS_GOTIE
:
7759 case BFD_RELOC_386_TLS_GOTDESC
:
7760 case BFD_RELOC_X86_64_TLSGD
:
7761 case BFD_RELOC_X86_64_TLSLD
:
7762 case BFD_RELOC_X86_64_GOTTPOFF
:
7763 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7764 value
= 0; /* Fully resolved at runtime. No addend. */
7766 case BFD_RELOC_386_TLS_LE
:
7767 case BFD_RELOC_386_TLS_LDO_32
:
7768 case BFD_RELOC_386_TLS_LE_32
:
7769 case BFD_RELOC_X86_64_DTPOFF32
:
7770 case BFD_RELOC_X86_64_DTPOFF64
:
7771 case BFD_RELOC_X86_64_TPOFF32
:
7772 case BFD_RELOC_X86_64_TPOFF64
:
7773 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7776 case BFD_RELOC_386_TLS_DESC_CALL
:
7777 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7778 value
= 0; /* Fully resolved at runtime. No addend. */
7779 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7783 case BFD_RELOC_386_GOT32
:
7784 case BFD_RELOC_X86_64_GOT32
:
7785 value
= 0; /* Fully resolved at runtime. No addend. */
7788 case BFD_RELOC_VTABLE_INHERIT
:
7789 case BFD_RELOC_VTABLE_ENTRY
:
7796 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7798 #endif /* !defined (TE_Mach) */
7800 /* Are we finished with this relocation now? */
7801 if (fixP
->fx_addsy
== NULL
)
7803 #if defined (OBJ_COFF) && defined (TE_PE)
7804 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7807 /* Remember value for tc_gen_reloc. */
7808 fixP
->fx_addnumber
= value
;
7809 /* Clear out the frag for now. */
7813 else if (use_rela_relocations
)
7815 fixP
->fx_no_overflow
= 1;
7816 /* Remember value for tc_gen_reloc. */
7817 fixP
->fx_addnumber
= value
;
7821 md_number_to_chars (p
, value
, fixP
->fx_size
);
7825 md_atof (int type
, char *litP
, int *sizeP
)
7827 /* This outputs the LITTLENUMs in REVERSE order;
7828 in accord with the bigendian 386. */
7829 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7832 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7835 output_invalid (int c
)
7838 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7841 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7842 "(0x%x)", (unsigned char) c
);
7843 return output_invalid_buf
;
7846 /* REG_STRING starts *before* REGISTER_PREFIX. */
7848 static const reg_entry
*
7849 parse_real_register (char *reg_string
, char **end_op
)
7851 char *s
= reg_string
;
7853 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7856 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7857 if (*s
== REGISTER_PREFIX
)
7860 if (is_space_char (*s
))
7864 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7866 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7867 return (const reg_entry
*) NULL
;
7871 /* For naked regs, make sure that we are not dealing with an identifier.
7872 This prevents confusing an identifier like `eax_var' with register
7874 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7875 return (const reg_entry
*) NULL
;
7879 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7881 /* Handle floating point regs, allowing spaces in the (i) part. */
7882 if (r
== i386_regtab
/* %st is first entry of table */)
7884 if (is_space_char (*s
))
7889 if (is_space_char (*s
))
7891 if (*s
>= '0' && *s
<= '7')
7895 if (is_space_char (*s
))
7900 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7905 /* We have "%st(" then garbage. */
7906 return (const reg_entry
*) NULL
;
7910 if (r
== NULL
|| allow_pseudo_reg
)
7913 if (operand_type_all_zero (&r
->reg_type
))
7914 return (const reg_entry
*) NULL
;
7916 if ((r
->reg_type
.bitfield
.reg32
7917 || r
->reg_type
.bitfield
.sreg3
7918 || r
->reg_type
.bitfield
.control
7919 || r
->reg_type
.bitfield
.debug
7920 || r
->reg_type
.bitfield
.test
)
7921 && !cpu_arch_flags
.bitfield
.cpui386
)
7922 return (const reg_entry
*) NULL
;
7924 if (r
->reg_type
.bitfield
.floatreg
7925 && !cpu_arch_flags
.bitfield
.cpu8087
7926 && !cpu_arch_flags
.bitfield
.cpu287
7927 && !cpu_arch_flags
.bitfield
.cpu387
)
7928 return (const reg_entry
*) NULL
;
7930 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7931 return (const reg_entry
*) NULL
;
7933 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7934 return (const reg_entry
*) NULL
;
7936 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7937 return (const reg_entry
*) NULL
;
7939 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7940 if (!allow_index_reg
7941 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7942 return (const reg_entry
*) NULL
;
7944 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7945 || r
->reg_type
.bitfield
.reg64
)
7946 && (!cpu_arch_flags
.bitfield
.cpulm
7947 || !operand_type_equal (&r
->reg_type
, &control
))
7948 && flag_code
!= CODE_64BIT
)
7949 return (const reg_entry
*) NULL
;
7951 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7952 return (const reg_entry
*) NULL
;
7957 /* REG_STRING starts *before* REGISTER_PREFIX. */
7959 static const reg_entry
*
7960 parse_register (char *reg_string
, char **end_op
)
7964 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7965 r
= parse_real_register (reg_string
, end_op
);
7970 char *save
= input_line_pointer
;
7974 input_line_pointer
= reg_string
;
7975 c
= get_symbol_end ();
7976 symbolP
= symbol_find (reg_string
);
7977 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7979 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7981 know (e
->X_op
== O_register
);
7982 know (e
->X_add_number
>= 0
7983 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7984 r
= i386_regtab
+ e
->X_add_number
;
7985 *end_op
= input_line_pointer
;
7987 *input_line_pointer
= c
;
7988 input_line_pointer
= save
;
7994 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7997 char *end
= input_line_pointer
;
8000 r
= parse_register (name
, &input_line_pointer
);
8001 if (r
&& end
<= input_line_pointer
)
8003 *nextcharP
= *input_line_pointer
;
8004 *input_line_pointer
= 0;
8005 e
->X_op
= O_register
;
8006 e
->X_add_number
= r
- i386_regtab
;
8009 input_line_pointer
= end
;
8011 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8015 md_operand (expressionS
*e
)
8020 switch (*input_line_pointer
)
8022 case REGISTER_PREFIX
:
8023 r
= parse_real_register (input_line_pointer
, &end
);
8026 e
->X_op
= O_register
;
8027 e
->X_add_number
= r
- i386_regtab
;
8028 input_line_pointer
= end
;
8033 gas_assert (intel_syntax
);
8034 end
= input_line_pointer
++;
8036 if (*input_line_pointer
== ']')
8038 ++input_line_pointer
;
8039 e
->X_op_symbol
= make_expr_symbol (e
);
8040 e
->X_add_symbol
= NULL
;
8041 e
->X_add_number
= 0;
8047 input_line_pointer
= end
;
8054 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8055 const char *md_shortopts
= "kVQ:sqn";
8057 const char *md_shortopts
= "qn";
8060 #define OPTION_32 (OPTION_MD_BASE + 0)
8061 #define OPTION_64 (OPTION_MD_BASE + 1)
8062 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8063 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8064 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8065 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8066 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8067 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8068 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8069 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8070 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8071 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8072 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8074 struct option md_longopts
[] =
8076 {"32", no_argument
, NULL
, OPTION_32
},
8077 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8078 || defined (TE_PE) || defined (TE_PEP))
8079 {"64", no_argument
, NULL
, OPTION_64
},
8081 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8082 {"march", required_argument
, NULL
, OPTION_MARCH
},
8083 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8084 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8085 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8086 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8087 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8088 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8089 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8090 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8091 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8092 {NULL
, no_argument
, NULL
, 0}
8094 size_t md_longopts_size
= sizeof (md_longopts
);
8097 md_parse_option (int c
, char *arg
)
8105 optimize_align_code
= 0;
8112 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8113 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8114 should be emitted or not. FIXME: Not implemented. */
8118 /* -V: SVR4 argument to print version ID. */
8120 print_version_id ();
8123 /* -k: Ignore for FreeBSD compatibility. */
8128 /* -s: On i386 Solaris, this tells the native assembler to use
8129 .stab instead of .stab.excl. We always use .stab anyhow. */
8132 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8133 || defined (TE_PE) || defined (TE_PEP))
8136 const char **list
, **l
;
8138 list
= bfd_target_list ();
8139 for (l
= list
; *l
!= NULL
; l
++)
8140 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8141 || strcmp (*l
, "coff-x86-64") == 0
8142 || strcmp (*l
, "pe-x86-64") == 0
8143 || strcmp (*l
, "pei-x86-64") == 0)
8145 default_arch
= "x86_64";
8149 as_fatal (_("No compiled in support for x86_64"));
8156 default_arch
= "i386";
8160 #ifdef SVR4_COMMENT_CHARS
8165 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8167 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8171 i386_comment_chars
= n
;
8177 arch
= xstrdup (arg
);
8181 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8182 next
= strchr (arch
, '+');
8185 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8187 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8190 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8193 cpu_arch_name
= cpu_arch
[j
].name
;
8194 cpu_sub_arch_name
= NULL
;
8195 cpu_arch_flags
= cpu_arch
[j
].flags
;
8196 cpu_arch_isa
= cpu_arch
[j
].type
;
8197 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8198 if (!cpu_arch_tune_set
)
8200 cpu_arch_tune
= cpu_arch_isa
;
8201 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8205 else if (*cpu_arch
[j
].name
== '.'
8206 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8208 /* ISA entension. */
8209 i386_cpu_flags flags
;
8211 if (strncmp (arch
, "no", 2))
8212 flags
= cpu_flags_or (cpu_arch_flags
,
8215 flags
= cpu_flags_and_not (cpu_arch_flags
,
8217 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8219 if (cpu_sub_arch_name
)
8221 char *name
= cpu_sub_arch_name
;
8222 cpu_sub_arch_name
= concat (name
,
8224 (const char *) NULL
);
8228 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8229 cpu_arch_flags
= flags
;
8235 if (j
>= ARRAY_SIZE (cpu_arch
))
8236 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8240 while (next
!= NULL
);
8245 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8246 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8248 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8250 cpu_arch_tune_set
= 1;
8251 cpu_arch_tune
= cpu_arch
[j
].type
;
8252 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8256 if (j
>= ARRAY_SIZE (cpu_arch
))
8257 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8260 case OPTION_MMNEMONIC
:
8261 if (strcasecmp (arg
, "att") == 0)
8263 else if (strcasecmp (arg
, "intel") == 0)
8266 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8269 case OPTION_MSYNTAX
:
8270 if (strcasecmp (arg
, "att") == 0)
8272 else if (strcasecmp (arg
, "intel") == 0)
8275 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8278 case OPTION_MINDEX_REG
:
8279 allow_index_reg
= 1;
8282 case OPTION_MNAKED_REG
:
8283 allow_naked_reg
= 1;
8286 case OPTION_MOLD_GCC
:
8290 case OPTION_MSSE2AVX
:
8294 case OPTION_MSSE_CHECK
:
8295 if (strcasecmp (arg
, "error") == 0)
8296 sse_check
= sse_check_error
;
8297 else if (strcasecmp (arg
, "warning") == 0)
8298 sse_check
= sse_check_warning
;
8299 else if (strcasecmp (arg
, "none") == 0)
8300 sse_check
= sse_check_none
;
8302 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8305 case OPTION_MAVXSCALAR
:
8306 if (strcasecmp (arg
, "128") == 0)
8308 else if (strcasecmp (arg
, "256") == 0)
8311 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8320 #define MESSAGE_TEMPLATE \
8324 show_arch (FILE *stream
, int ext
, int check
)
8326 static char message
[] = MESSAGE_TEMPLATE
;
8327 char *start
= message
+ 27;
8329 int size
= sizeof (MESSAGE_TEMPLATE
);
8336 left
= size
- (start
- message
);
8337 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8339 /* Should it be skipped? */
8340 if (cpu_arch
[j
].skip
)
8343 name
= cpu_arch
[j
].name
;
8344 len
= cpu_arch
[j
].len
;
8347 /* It is an extension. Skip if we aren't asked to show it. */
8358 /* It is an processor. Skip if we show only extension. */
8361 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8363 /* It is an impossible processor - skip. */
8367 /* Reserve 2 spaces for ", " or ",\0" */
8370 /* Check if there is any room. */
8378 p
= mempcpy (p
, name
, len
);
8382 /* Output the current message now and start a new one. */
8385 fprintf (stream
, "%s\n", message
);
8387 left
= size
- (start
- message
) - len
- 2;
8389 gas_assert (left
>= 0);
8391 p
= mempcpy (p
, name
, len
);
8396 fprintf (stream
, "%s\n", message
);
8400 md_show_usage (FILE *stream
)
8402 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8403 fprintf (stream
, _("\
8405 -V print assembler version number\n\
8408 fprintf (stream
, _("\
8409 -n Do not optimize code alignment\n\
8410 -q quieten some warnings\n"));
8411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8412 fprintf (stream
, _("\
8415 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8416 || defined (TE_PE) || defined (TE_PEP))
8417 fprintf (stream
, _("\
8418 --32/--64 generate 32bit/64bit code\n"));
8420 #ifdef SVR4_COMMENT_CHARS
8421 fprintf (stream
, _("\
8422 --divide do not treat `/' as a comment character\n"));
8424 fprintf (stream
, _("\
8425 --divide ignored\n"));
8427 fprintf (stream
, _("\
8428 -march=CPU[,+EXTENSION...]\n\
8429 generate code for CPU and EXTENSION, CPU is one of:\n"));
8430 show_arch (stream
, 0, 1);
8431 fprintf (stream
, _("\
8432 EXTENSION is combination of:\n"));
8433 show_arch (stream
, 1, 0);
8434 fprintf (stream
, _("\
8435 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8436 show_arch (stream
, 0, 0);
8437 fprintf (stream
, _("\
8438 -msse2avx encode SSE instructions with VEX prefix\n"));
8439 fprintf (stream
, _("\
8440 -msse-check=[none|error|warning]\n\
8441 check SSE instructions\n"));
8442 fprintf (stream
, _("\
8443 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8445 fprintf (stream
, _("\
8446 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8447 fprintf (stream
, _("\
8448 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8449 fprintf (stream
, _("\
8450 -mindex-reg support pseudo index registers\n"));
8451 fprintf (stream
, _("\
8452 -mnaked-reg don't require `%%' prefix for registers\n"));
8453 fprintf (stream
, _("\
8454 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8457 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8458 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8459 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8461 /* Pick the target format to use. */
8464 i386_target_format (void)
8466 if (!strcmp (default_arch
, "x86_64"))
8467 update_code_flag (CODE_64BIT
, 1);
8468 else if (!strcmp (default_arch
, "i386"))
8469 update_code_flag (CODE_32BIT
, 1);
8471 as_fatal (_("Unknown architecture"));
8473 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8474 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8475 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8476 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8478 switch (OUTPUT_FLAVOR
)
8480 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8481 case bfd_target_aout_flavour
:
8482 return AOUT_TARGET_FORMAT
;
8484 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8485 # if defined (TE_PE) || defined (TE_PEP)
8486 case bfd_target_coff_flavour
:
8487 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8488 # elif defined (TE_GO32)
8489 case bfd_target_coff_flavour
:
8492 case bfd_target_coff_flavour
:
8496 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8497 case bfd_target_elf_flavour
:
8499 if (flag_code
== CODE_64BIT
)
8502 use_rela_relocations
= 1;
8504 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8506 if (flag_code
!= CODE_64BIT
)
8507 as_fatal (_("Intel L1OM is 64bit only"));
8508 return ELF_TARGET_L1OM_FORMAT
;
8511 return (flag_code
== CODE_64BIT
8512 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8515 #if defined (OBJ_MACH_O)
8516 case bfd_target_mach_o_flavour
:
8517 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8525 #endif /* OBJ_MAYBE_ more than one */
8527 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8529 i386_elf_emit_arch_note (void)
8531 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8534 asection
*seg
= now_seg
;
8535 subsegT subseg
= now_subseg
;
8536 Elf_Internal_Note i_note
;
8537 Elf_External_Note e_note
;
8538 asection
*note_secp
;
8541 /* Create the .note section. */
8542 note_secp
= subseg_new (".note", 0);
8543 bfd_set_section_flags (stdoutput
,
8545 SEC_HAS_CONTENTS
| SEC_READONLY
);
8547 /* Process the arch string. */
8548 len
= strlen (cpu_arch_name
);
8550 i_note
.namesz
= len
+ 1;
8552 i_note
.type
= NT_ARCH
;
8553 p
= frag_more (sizeof (e_note
.namesz
));
8554 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8555 p
= frag_more (sizeof (e_note
.descsz
));
8556 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8557 p
= frag_more (sizeof (e_note
.type
));
8558 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8559 p
= frag_more (len
+ 1);
8560 strcpy (p
, cpu_arch_name
);
8562 frag_align (2, 0, 0);
8564 subseg_set (seg
, subseg
);
8570 md_undefined_symbol (name
)
8573 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8574 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8575 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8576 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8580 if (symbol_find (name
))
8581 as_bad (_("GOT already in symbol table"));
8582 GOT_symbol
= symbol_new (name
, undefined_section
,
8583 (valueT
) 0, &zero_address_frag
);
8590 /* Round up a section size to the appropriate boundary. */
8593 md_section_align (segment
, size
)
8594 segT segment ATTRIBUTE_UNUSED
;
8597 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8598 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8600 /* For a.out, force the section size to be aligned. If we don't do
8601 this, BFD will align it for us, but it will not write out the
8602 final bytes of the section. This may be a bug in BFD, but it is
8603 easier to fix it here since that is how the other a.out targets
8607 align
= bfd_get_section_alignment (stdoutput
, segment
);
8608 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8615 /* On the i386, PC-relative offsets are relative to the start of the
8616 next instruction. That is, the address of the offset, plus its
8617 size, since the offset is always the last part of the insn. */
8620 md_pcrel_from (fixS
*fixP
)
8622 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8628 s_bss (int ignore ATTRIBUTE_UNUSED
)
8632 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8634 obj_elf_section_change_hook ();
8636 temp
= get_absolute_expression ();
8637 subseg_set (bss_section
, (subsegT
) temp
);
8638 demand_empty_rest_of_line ();
8644 i386_validate_fix (fixS
*fixp
)
8646 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8648 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8652 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8657 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8659 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8666 tc_gen_reloc (section
, fixp
)
8667 asection
*section ATTRIBUTE_UNUSED
;
8671 bfd_reloc_code_real_type code
;
8673 switch (fixp
->fx_r_type
)
8675 case BFD_RELOC_X86_64_PLT32
:
8676 case BFD_RELOC_X86_64_GOT32
:
8677 case BFD_RELOC_X86_64_GOTPCREL
:
8678 case BFD_RELOC_386_PLT32
:
8679 case BFD_RELOC_386_GOT32
:
8680 case BFD_RELOC_386_GOTOFF
:
8681 case BFD_RELOC_386_GOTPC
:
8682 case BFD_RELOC_386_TLS_GD
:
8683 case BFD_RELOC_386_TLS_LDM
:
8684 case BFD_RELOC_386_TLS_LDO_32
:
8685 case BFD_RELOC_386_TLS_IE_32
:
8686 case BFD_RELOC_386_TLS_IE
:
8687 case BFD_RELOC_386_TLS_GOTIE
:
8688 case BFD_RELOC_386_TLS_LE_32
:
8689 case BFD_RELOC_386_TLS_LE
:
8690 case BFD_RELOC_386_TLS_GOTDESC
:
8691 case BFD_RELOC_386_TLS_DESC_CALL
:
8692 case BFD_RELOC_X86_64_TLSGD
:
8693 case BFD_RELOC_X86_64_TLSLD
:
8694 case BFD_RELOC_X86_64_DTPOFF32
:
8695 case BFD_RELOC_X86_64_DTPOFF64
:
8696 case BFD_RELOC_X86_64_GOTTPOFF
:
8697 case BFD_RELOC_X86_64_TPOFF32
:
8698 case BFD_RELOC_X86_64_TPOFF64
:
8699 case BFD_RELOC_X86_64_GOTOFF64
:
8700 case BFD_RELOC_X86_64_GOTPC32
:
8701 case BFD_RELOC_X86_64_GOT64
:
8702 case BFD_RELOC_X86_64_GOTPCREL64
:
8703 case BFD_RELOC_X86_64_GOTPC64
:
8704 case BFD_RELOC_X86_64_GOTPLT64
:
8705 case BFD_RELOC_X86_64_PLTOFF64
:
8706 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8707 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8709 case BFD_RELOC_VTABLE_ENTRY
:
8710 case BFD_RELOC_VTABLE_INHERIT
:
8712 case BFD_RELOC_32_SECREL
:
8714 code
= fixp
->fx_r_type
;
8716 case BFD_RELOC_X86_64_32S
:
8717 if (!fixp
->fx_pcrel
)
8719 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8720 code
= fixp
->fx_r_type
;
8726 switch (fixp
->fx_size
)
8729 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8730 _("can not do %d byte pc-relative relocation"),
8732 code
= BFD_RELOC_32_PCREL
;
8734 case 1: code
= BFD_RELOC_8_PCREL
; break;
8735 case 2: code
= BFD_RELOC_16_PCREL
; break;
8736 case 4: code
= BFD_RELOC_32_PCREL
; break;
8738 case 8: code
= BFD_RELOC_64_PCREL
; break;
8744 switch (fixp
->fx_size
)
8747 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8748 _("can not do %d byte relocation"),
8750 code
= BFD_RELOC_32
;
8752 case 1: code
= BFD_RELOC_8
; break;
8753 case 2: code
= BFD_RELOC_16
; break;
8754 case 4: code
= BFD_RELOC_32
; break;
8756 case 8: code
= BFD_RELOC_64
; break;
8763 if ((code
== BFD_RELOC_32
8764 || code
== BFD_RELOC_32_PCREL
8765 || code
== BFD_RELOC_X86_64_32S
)
8767 && fixp
->fx_addsy
== GOT_symbol
)
8770 code
= BFD_RELOC_386_GOTPC
;
8772 code
= BFD_RELOC_X86_64_GOTPC32
;
8774 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8776 && fixp
->fx_addsy
== GOT_symbol
)
8778 code
= BFD_RELOC_X86_64_GOTPC64
;
8781 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8782 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8783 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8785 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8787 if (!use_rela_relocations
)
8789 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8790 vtable entry to be used in the relocation's section offset. */
8791 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8792 rel
->address
= fixp
->fx_offset
;
8793 #if defined (OBJ_COFF) && defined (TE_PE)
8794 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8795 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8800 /* Use the rela in 64bit mode. */
8803 if (!fixp
->fx_pcrel
)
8804 rel
->addend
= fixp
->fx_offset
;
8808 case BFD_RELOC_X86_64_PLT32
:
8809 case BFD_RELOC_X86_64_GOT32
:
8810 case BFD_RELOC_X86_64_GOTPCREL
:
8811 case BFD_RELOC_X86_64_TLSGD
:
8812 case BFD_RELOC_X86_64_TLSLD
:
8813 case BFD_RELOC_X86_64_GOTTPOFF
:
8814 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8815 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8816 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8819 rel
->addend
= (section
->vma
8821 + fixp
->fx_addnumber
8822 + md_pcrel_from (fixp
));
8827 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8828 if (rel
->howto
== NULL
)
8830 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8831 _("cannot represent relocation type %s"),
8832 bfd_get_reloc_code_name (code
));
8833 /* Set howto to a garbage value so that we can keep going. */
8834 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8835 gas_assert (rel
->howto
!= NULL
);
8841 #include "tc-i386-intel.c"
8844 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8846 int saved_naked_reg
;
8847 char saved_register_dot
;
8849 saved_naked_reg
= allow_naked_reg
;
8850 allow_naked_reg
= 1;
8851 saved_register_dot
= register_chars
['.'];
8852 register_chars
['.'] = '.';
8853 allow_pseudo_reg
= 1;
8854 expression_and_evaluate (exp
);
8855 allow_pseudo_reg
= 0;
8856 register_chars
['.'] = saved_register_dot
;
8857 allow_naked_reg
= saved_naked_reg
;
8859 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8861 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8863 exp
->X_op
= O_constant
;
8864 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8865 .dw2_regnum
[flag_code
>> 1];
8868 exp
->X_op
= O_illegal
;
8873 tc_x86_frame_initial_instructions (void)
8875 static unsigned int sp_regno
[2];
8877 if (!sp_regno
[flag_code
>> 1])
8879 char *saved_input
= input_line_pointer
;
8880 char sp
[][4] = {"esp", "rsp"};
8883 input_line_pointer
= sp
[flag_code
>> 1];
8884 tc_x86_parse_to_dw2regnum (&exp
);
8885 gas_assert (exp
.X_op
== O_constant
);
8886 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8887 input_line_pointer
= saved_input
;
8890 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8891 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8895 i386_elf_section_type (const char *str
, size_t len
)
8897 if (flag_code
== CODE_64BIT
8898 && len
== sizeof ("unwind") - 1
8899 && strncmp (str
, "unwind", 6) == 0)
8900 return SHT_X86_64_UNWIND
;
8907 i386_solaris_fix_up_eh_frame (segT sec
)
8909 if (flag_code
== CODE_64BIT
)
8910 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8916 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8920 exp
.X_op
= O_secrel
;
8921 exp
.X_add_symbol
= symbol
;
8922 exp
.X_add_number
= 0;
8923 emit_expr (&exp
, size
);
8927 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8928 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8931 x86_64_section_letter (int letter
, char **ptr_msg
)
8933 if (flag_code
== CODE_64BIT
)
8936 return SHF_X86_64_LARGE
;
8938 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8941 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8946 x86_64_section_word (char *str
, size_t len
)
8948 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8949 return SHF_X86_64_LARGE
;
8955 handle_large_common (int small ATTRIBUTE_UNUSED
)
8957 if (flag_code
!= CODE_64BIT
)
8959 s_comm_internal (0, elf_common_parse
);
8960 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8964 static segT lbss_section
;
8965 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8966 asection
*saved_bss_section
= bss_section
;
8968 if (lbss_section
== NULL
)
8970 flagword applicable
;
8972 subsegT subseg
= now_subseg
;
8974 /* The .lbss section is for local .largecomm symbols. */
8975 lbss_section
= subseg_new (".lbss", 0);
8976 applicable
= bfd_applicable_section_flags (stdoutput
);
8977 bfd_set_section_flags (stdoutput
, lbss_section
,
8978 applicable
& SEC_ALLOC
);
8979 seg_info (lbss_section
)->bss
= 1;
8981 subseg_set (seg
, subseg
);
8984 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8985 bss_section
= lbss_section
;
8987 s_comm_internal (0, elf_common_parse
);
8989 elf_com_section_ptr
= saved_com_section_ptr
;
8990 bss_section
= saved_bss_section
;
8993 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */