1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void set_code_flag (int);
139 static void set_16bit_gcc_code_flag (int);
140 static void set_intel_syntax (int);
141 static void set_intel_mnemonic (int);
142 static void set_allow_index_reg (int);
143 static void set_sse_check (int);
144 static void set_cpu_arch (int);
146 static void pe_directive_secrel (int);
148 static void signed_cons (int);
149 static char *output_invalid (int c
);
150 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
152 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
154 static int i386_att_operand (char *);
155 static int i386_intel_operand (char *, int);
156 static int i386_intel_simplify (expressionS
*);
157 static int i386_intel_parse_name (const char *, expressionS
*);
158 static const reg_entry
*parse_register (char *, char **);
159 static char *parse_insn (char *, char *);
160 static char *parse_operands (char *, const char *);
161 static void swap_operands (void);
162 static void swap_2_operands (int, int);
163 static void optimize_imm (void);
164 static void optimize_disp (void);
165 static const insn_template
*match_template (void);
166 static int check_string (void);
167 static int process_suffix (void);
168 static int check_byte_reg (void);
169 static int check_long_reg (void);
170 static int check_qword_reg (void);
171 static int check_word_reg (void);
172 static int finalize_imm (void);
173 static int process_operands (void);
174 static const seg_entry
*build_modrm_byte (void);
175 static void output_insn (void);
176 static void output_imm (fragS
*, offsetT
);
177 static void output_disp (fragS
*, offsetT
);
179 static void s_bss (int);
181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
185 static const char *default_arch
= DEFAULT_ARCH
;
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes
[3];
193 /* Destination or source register specifier. */
194 const reg_entry
*register_specifier
;
197 /* 'md_assemble ()' gathers together information and puts it into a
204 const reg_entry
*regs
;
209 /* TM holds the template for the insn were currently assembling. */
212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
216 /* OPERANDS gives the number of given operands. */
217 unsigned int operands
;
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
222 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
224 /* TYPES [i] is the type (see above #defines) which tells us how to
225 use OP[i] for the corresponding operand. */
226 i386_operand_type types
[MAX_OPERANDS
];
228 /* Displacement expression, immediate expression, or register for each
230 union i386_op op
[MAX_OPERANDS
];
232 /* Flags for operands. */
233 unsigned int flags
[MAX_OPERANDS
];
234 #define Operand_PCrel 1
236 /* Relocation type for operand */
237 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry
*base_reg
;
242 const reg_entry
*index_reg
;
243 unsigned int log2_scale_factor
;
245 /* SEG gives the seg_entries of this insn. They are zero unless
246 explicit segment overrides are given. */
247 const seg_entry
*seg
[2];
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes
;
252 unsigned char prefix
[MAX_PREFIXES
];
254 /* RM and SIB are the modrm byte and the sib byte where the
255 addressing modes of this insn are encoded. */
261 /* Swap operand in encoding. */
262 unsigned int swap_operand
;
265 typedef struct _i386_insn i386_insn
;
267 /* List of chars besides those in app.c:symbol_chars that can start an
268 operand. Used to prevent the scrubber eating vital white-space. */
269 const char extra_symbol_chars
[] = "*%-(["
278 #if (defined (TE_I386AIX) \
279 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
280 && !defined (TE_GNU) \
281 && !defined (TE_LINUX) \
282 && !defined (TE_NETWARE) \
283 && !defined (TE_FreeBSD) \
284 && !defined (TE_NetBSD)))
285 /* This array holds the chars that always start a comment. If the
286 pre-processor is disabled, these aren't very useful. The option
287 --divide will remove '/' from this list. */
288 const char *i386_comment_chars
= "#/";
289 #define SVR4_COMMENT_CHARS 1
290 #define PREFIX_SEPARATOR '\\'
293 const char *i386_comment_chars
= "#";
294 #define PREFIX_SEPARATOR '/'
297 /* This array holds the chars that only start a comment at the beginning of
298 a line. If the line seems to have the form '# 123 filename'
299 .line and .file directives will appear in the pre-processed output.
300 Note that input_file.c hand checks for '#' at the beginning of the
301 first line of the input file. This is because the compiler outputs
302 #NO_APP at the beginning of its output.
303 Also note that comments started like this one will always work if
304 '/' isn't otherwise defined. */
305 const char line_comment_chars
[] = "#/";
307 const char line_separator_chars
[] = ";";
309 /* Chars that can be used to separate mant from exp in floating point
311 const char EXP_CHARS
[] = "eE";
313 /* Chars that mean this number is a floating point constant
316 const char FLT_CHARS
[] = "fFdDxX";
318 /* Tables for lexical analysis. */
319 static char mnemonic_chars
[256];
320 static char register_chars
[256];
321 static char operand_chars
[256];
322 static char identifier_chars
[256];
323 static char digit_chars
[256];
325 /* Lexical macros. */
326 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
327 #define is_operand_char(x) (operand_chars[(unsigned char) x])
328 #define is_register_char(x) (register_chars[(unsigned char) x])
329 #define is_space_char(x) ((x) == ' ')
330 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
331 #define is_digit_char(x) (digit_chars[(unsigned char) x])
333 /* All non-digit non-letter characters that may occur in an operand. */
334 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
336 /* md_assemble() always leaves the strings it's passed unaltered. To
337 effect this we maintain a stack of saved characters that we've smashed
338 with '\0's (indicating end of strings for various sub-fields of the
339 assembler instruction). */
340 static char save_stack
[32];
341 static char *save_stack_p
;
342 #define END_STRING_AND_SAVE(s) \
343 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
344 #define RESTORE_END_STRING(s) \
345 do { *(s) = *--save_stack_p; } while (0)
347 /* The instruction we're assembling. */
350 /* Possible templates for current insn. */
351 static const templates
*current_templates
;
353 /* Per instruction expressionS buffers: max displacements & immediates. */
354 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
355 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
357 /* Current operand we are working on. */
358 static int this_operand
= -1;
360 /* We support four different modes. FLAG_CODE variable is used to distinguish
368 static enum flag_code flag_code
;
369 static unsigned int object_64bit
;
370 static int use_rela_relocations
= 0;
372 /* The names used to print error messages. */
373 static const char *flag_code_names
[] =
380 /* 1 for intel syntax,
382 static int intel_syntax
= 0;
384 /* 1 for intel mnemonic,
385 0 if att mnemonic. */
386 static int intel_mnemonic
= !SYSV386_COMPAT
;
388 /* 1 if support old (<= 2.8.1) versions of gcc. */
389 static int old_gcc
= OLDGCC_COMPAT
;
391 /* 1 if pseudo registers are permitted. */
392 static int allow_pseudo_reg
= 0;
394 /* 1 if register prefix % not required. */
395 static int allow_naked_reg
= 0;
397 /* 1 if pseudo index register, eiz/riz, is allowed . */
398 static int allow_index_reg
= 0;
408 /* Register prefix used for error message. */
409 static const char *register_prefix
= "%";
411 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
412 leave, push, and pop instructions so that gcc has the same stack
413 frame as in 32 bit mode. */
414 static char stackop_size
= '\0';
416 /* Non-zero to optimize code alignment. */
417 int optimize_align_code
= 1;
419 /* Non-zero to quieten some warnings. */
420 static int quiet_warnings
= 0;
423 static const char *cpu_arch_name
= NULL
;
424 static char *cpu_sub_arch_name
= NULL
;
426 /* CPU feature flags. */
427 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
429 /* If we have selected a cpu we are generating instructions for. */
430 static int cpu_arch_tune_set
= 0;
432 /* Cpu we are generating instructions for. */
433 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
435 /* CPU feature flags of cpu we are generating instructions for. */
436 static i386_cpu_flags cpu_arch_tune_flags
;
438 /* CPU instruction set architecture used. */
439 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
441 /* CPU feature flags of instruction set architecture used. */
442 i386_cpu_flags cpu_arch_isa_flags
;
444 /* If set, conditional jumps are not automatically promoted to handle
445 larger than a byte offset. */
446 static unsigned int no_cond_jump_promotion
= 0;
448 /* Encode SSE instructions with VEX prefix. */
449 static unsigned int sse2avx
;
451 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
452 static symbolS
*GOT_symbol
;
454 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
455 unsigned int x86_dwarf2_return_column
;
457 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
458 int x86_cie_data_alignment
;
460 /* Interface to relax_segment.
461 There are 3 major relax states for 386 jump insns because the
462 different types of jumps add different sizes to frags when we're
463 figuring out what sort of jump to choose to reach a given label. */
466 #define UNCOND_JUMP 0
468 #define COND_JUMP86 2
473 #define SMALL16 (SMALL | CODE16)
475 #define BIG16 (BIG | CODE16)
479 #define INLINE __inline__
485 #define ENCODE_RELAX_STATE(type, size) \
486 ((relax_substateT) (((type) << 2) | (size)))
487 #define TYPE_FROM_RELAX_STATE(s) \
489 #define DISP_SIZE_FROM_RELAX_STATE(s) \
490 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
492 /* This table is used by relax_frag to promote short jumps to long
493 ones where necessary. SMALL (short) jumps may be promoted to BIG
494 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
495 don't allow a short jump in a 32 bit code segment to be promoted to
496 a 16 bit offset jump because it's slower (requires data size
497 prefix), and doesn't work, unless the destination is in the bottom
498 64k of the code segment (The top 16 bits of eip are zeroed). */
500 const relax_typeS md_relax_table
[] =
503 1) most positive reach of this state,
504 2) most negative reach of this state,
505 3) how many bytes this mode will have in the variable part of the frag
506 4) which index into the table to try if we can't fit into this one. */
508 /* UNCOND_JUMP states. */
509 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
510 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
511 /* dword jmp adds 4 bytes to frag:
512 0 extra opcode bytes, 4 displacement bytes. */
514 /* word jmp adds 2 byte2 to frag:
515 0 extra opcode bytes, 2 displacement bytes. */
518 /* COND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
521 /* dword conditionals adds 5 bytes to frag:
522 1 extra opcode byte, 4 displacement bytes. */
524 /* word conditionals add 3 bytes to frag:
525 1 extra opcode byte, 2 displacement bytes. */
528 /* COND_JUMP86 states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
534 /* word conditionals add 4 bytes to frag:
535 1 displacement byte and a 3 byte long branch insn. */
539 static const arch_entry cpu_arch
[] =
541 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
542 CPU_GENERIC32_FLAGS
, 0 },
543 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
544 CPU_GENERIC64_FLAGS
, 0 },
545 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
547 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
549 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
551 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
553 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
555 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
557 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
559 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
561 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
563 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
565 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
567 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
569 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
571 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
572 CPU_NOCONA_FLAGS
, 0 },
573 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
575 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
577 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
578 CPU_CORE2_FLAGS
, 1 },
579 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
580 CPU_CORE2_FLAGS
, 0 },
581 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
582 CPU_COREI7_FLAGS
, 0 },
583 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
585 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
587 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
589 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
590 CPU_ATHLON_FLAGS
, 0 },
591 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
593 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
595 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
597 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
598 CPU_AMDFAM10_FLAGS
, 0 },
599 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
601 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
603 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
605 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
606 CPU_ANY87_FLAGS
, 0 },
607 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
609 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
610 CPU_3DNOWA_FLAGS
, 0 },
611 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
613 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
615 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
617 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
618 CPU_SSSE3_FLAGS
, 0 },
619 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
620 CPU_SSE4_1_FLAGS
, 0 },
621 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
622 CPU_SSE4_2_FLAGS
, 0 },
623 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
624 CPU_SSE4_2_FLAGS
, 0 },
625 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
626 CPU_ANY_SSE_FLAGS
, 0 },
627 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
629 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
630 CPU_ANY_AVX_FLAGS
, 0 },
631 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
633 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
635 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
636 CPU_XSAVE_FLAGS
, 0 },
637 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
639 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
640 CPU_PCLMUL_FLAGS
, 0 },
641 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
642 CPU_PCLMUL_FLAGS
, 1 },
643 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
645 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
647 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
649 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
651 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
652 CPU_MOVBE_FLAGS
, 0 },
653 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
655 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
656 CPU_CLFLUSH_FLAGS
, 0 },
657 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
658 CPU_SYSCALL_FLAGS
, 0 },
659 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
660 CPU_RDTSCP_FLAGS
, 0 },
661 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
662 CPU_3DNOW_FLAGS
, 0 },
663 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
664 CPU_3DNOWA_FLAGS
, 0 },
665 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
666 CPU_PADLOCK_FLAGS
, 0 },
667 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
669 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
671 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
672 CPU_SSE4A_FLAGS
, 0 },
673 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
678 /* Like s_lcomm_internal in gas/read.c but the alignment string
679 is allowed to be optional. */
682 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
689 && *input_line_pointer
== ',')
691 align
= parse_align (needs_align
- 1);
693 if (align
== (addressT
) -1)
708 bss_alloc (symbolP
, size
, align
);
713 pe_lcomm (int needs_align
)
715 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
719 const pseudo_typeS md_pseudo_table
[] =
721 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
722 {"align", s_align_bytes
, 0},
724 {"align", s_align_ptwo
, 0},
726 {"arch", set_cpu_arch
, 0},
730 {"lcomm", pe_lcomm
, 1},
732 {"ffloat", float_cons
, 'f'},
733 {"dfloat", float_cons
, 'd'},
734 {"tfloat", float_cons
, 'x'},
736 {"slong", signed_cons
, 4},
737 {"noopt", s_ignore
, 0},
738 {"optim", s_ignore
, 0},
739 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
740 {"code16", set_code_flag
, CODE_16BIT
},
741 {"code32", set_code_flag
, CODE_32BIT
},
742 {"code64", set_code_flag
, CODE_64BIT
},
743 {"intel_syntax", set_intel_syntax
, 1},
744 {"att_syntax", set_intel_syntax
, 0},
745 {"intel_mnemonic", set_intel_mnemonic
, 1},
746 {"att_mnemonic", set_intel_mnemonic
, 0},
747 {"allow_index_reg", set_allow_index_reg
, 1},
748 {"disallow_index_reg", set_allow_index_reg
, 0},
749 {"sse_check", set_sse_check
, 0},
750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
751 {"largecomm", handle_large_common
, 0},
753 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
754 {"loc", dwarf2_directive_loc
, 0},
755 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
758 {"secrel32", pe_directive_secrel
, 0},
763 /* For interface with expression (). */
764 extern char *input_line_pointer
;
766 /* Hash table for instruction mnemonic lookup. */
767 static struct hash_control
*op_hash
;
769 /* Hash table for register lookup. */
770 static struct hash_control
*reg_hash
;
773 i386_align_code (fragS
*fragP
, int count
)
775 /* Various efficient no-op patterns for aligning code labels.
776 Note: Don't try to assemble the instructions in the comments.
777 0L and 0w are not legal. */
778 static const char f32_1
[] =
780 static const char f32_2
[] =
781 {0x66,0x90}; /* xchg %ax,%ax */
782 static const char f32_3
[] =
783 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
784 static const char f32_4
[] =
785 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
786 static const char f32_5
[] =
788 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
789 static const char f32_6
[] =
790 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
791 static const char f32_7
[] =
792 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
793 static const char f32_8
[] =
795 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
796 static const char f32_9
[] =
797 {0x89,0xf6, /* movl %esi,%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_10
[] =
800 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_11
[] =
803 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_12
[] =
806 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
807 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
808 static const char f32_13
[] =
809 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_14
[] =
812 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
814 static const char f16_3
[] =
815 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
816 static const char f16_4
[] =
817 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
818 static const char f16_5
[] =
820 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
821 static const char f16_6
[] =
822 {0x89,0xf6, /* mov %si,%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char f16_7
[] =
825 {0x8d,0x74,0x00, /* lea 0(%si),%si */
826 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
827 static const char f16_8
[] =
828 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
829 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
830 static const char jump_31
[] =
831 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
833 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
835 static const char *const f32_patt
[] = {
836 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
837 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
839 static const char *const f16_patt
[] = {
840 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
843 static const char alt_3
[] =
845 /* nopl 0(%[re]ax) */
846 static const char alt_4
[] =
847 {0x0f,0x1f,0x40,0x00};
848 /* nopl 0(%[re]ax,%[re]ax,1) */
849 static const char alt_5
[] =
850 {0x0f,0x1f,0x44,0x00,0x00};
851 /* nopw 0(%[re]ax,%[re]ax,1) */
852 static const char alt_6
[] =
853 {0x66,0x0f,0x1f,0x44,0x00,0x00};
854 /* nopl 0L(%[re]ax) */
855 static const char alt_7
[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
857 /* nopl 0L(%[re]ax,%[re]ax,1) */
858 static const char alt_8
[] =
859 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 /* nopw 0L(%[re]ax,%[re]ax,1) */
861 static const char alt_9
[] =
862 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_10
[] =
865 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_11
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 nopw %cs:0L(%[re]ax,%[re]ax,1) */
874 static const char alt_long_12
[] =
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_13
[] =
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
891 nopw %cs:0L(%[re]ax,%[re]ax,1) */
892 static const char alt_long_14
[] =
897 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_long_15
[] =
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* nopl 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_11
[] =
914 {0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
917 nopw 0(%[re]ax,%[re]ax,1) */
918 static const char alt_short_12
[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x66,0x0f,0x1f,0x44,0x00,0x00};
921 /* nopw 0(%[re]ax,%[re]ax,1)
923 static const char alt_short_13
[] =
924 {0x66,0x0f,0x1f,0x44,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 static const char alt_short_14
[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
932 nopl 0L(%[re]ax,%[re]ax,1) */
933 static const char alt_short_15
[] =
934 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
935 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
936 static const char *const alt_short_patt
[] = {
937 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
938 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
939 alt_short_14
, alt_short_15
941 static const char *const alt_long_patt
[] = {
942 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
943 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
944 alt_long_14
, alt_long_15
947 /* Only align for at least a positive non-zero boundary. */
948 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
951 /* We need to decide which NOP sequence to use for 32bit and
952 64bit. When -mtune= is used:
954 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
955 PROCESSOR_GENERIC32, f32_patt will be used.
956 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
957 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
958 PROCESSOR_GENERIC64, alt_long_patt will be used.
959 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
960 PROCESSOR_AMDFAM10, alt_short_patt will be used.
962 When -mtune= isn't used, alt_long_patt will be used if
963 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
966 When -march= or .arch is used, we can't use anything beyond
967 cpu_arch_isa_flags. */
969 if (flag_code
== CODE_16BIT
)
973 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
975 /* Adjust jump offset. */
976 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
979 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
980 f16_patt
[count
- 1], count
);
984 const char *const *patt
= NULL
;
986 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
988 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
989 switch (cpu_arch_tune
)
991 case PROCESSOR_UNKNOWN
:
992 /* We use cpu_arch_isa_flags to check if we SHOULD
993 optimize for Cpu686. */
994 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
995 patt
= alt_long_patt
;
999 case PROCESSOR_PENTIUMPRO
:
1000 case PROCESSOR_PENTIUM4
:
1001 case PROCESSOR_NOCONA
:
1002 case PROCESSOR_CORE
:
1003 case PROCESSOR_CORE2
:
1004 case PROCESSOR_COREI7
:
1005 case PROCESSOR_L1OM
:
1006 case PROCESSOR_GENERIC64
:
1007 patt
= alt_long_patt
;
1010 case PROCESSOR_ATHLON
:
1012 case PROCESSOR_AMDFAM10
:
1013 patt
= alt_short_patt
;
1015 case PROCESSOR_I386
:
1016 case PROCESSOR_I486
:
1017 case PROCESSOR_PENTIUM
:
1018 case PROCESSOR_GENERIC32
:
1025 switch (fragP
->tc_frag_data
.tune
)
1027 case PROCESSOR_UNKNOWN
:
1028 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1029 PROCESSOR_UNKNOWN. */
1033 case PROCESSOR_I386
:
1034 case PROCESSOR_I486
:
1035 case PROCESSOR_PENTIUM
:
1037 case PROCESSOR_ATHLON
:
1039 case PROCESSOR_AMDFAM10
:
1040 case PROCESSOR_GENERIC32
:
1041 /* We use cpu_arch_isa_flags to check if we CAN optimize
1043 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1044 patt
= alt_short_patt
;
1048 case PROCESSOR_PENTIUMPRO
:
1049 case PROCESSOR_PENTIUM4
:
1050 case PROCESSOR_NOCONA
:
1051 case PROCESSOR_CORE
:
1052 case PROCESSOR_CORE2
:
1053 case PROCESSOR_COREI7
:
1054 case PROCESSOR_L1OM
:
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1066 if (patt
== f32_patt
)
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1073 /* For 64bit, the limit is 3 bytes. */
1074 if (flag_code
== CODE_64BIT
1075 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1080 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1081 patt
[count
- 1], count
);
1084 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1086 /* Adjust jump offset. */
1087 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1092 /* Maximum length of an instruction is 15 byte. If the
1093 padding is greater than 15 bytes and we don't use jump,
1094 we have to break it into smaller pieces. */
1095 int padding
= count
;
1096 while (padding
> 15)
1099 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1104 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1105 patt
[padding
- 1], padding
);
1108 fragP
->fr_var
= count
;
1112 operand_type_all_zero (const union i386_operand_type
*x
)
1114 switch (ARRAY_SIZE(x
->array
))
1123 return !x
->array
[0];
1130 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1132 switch (ARRAY_SIZE(x
->array
))
1147 operand_type_equal (const union i386_operand_type
*x
,
1148 const union i386_operand_type
*y
)
1150 switch (ARRAY_SIZE(x
->array
))
1153 if (x
->array
[2] != y
->array
[2])
1156 if (x
->array
[1] != y
->array
[1])
1159 return x
->array
[0] == y
->array
[0];
1167 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1169 switch (ARRAY_SIZE(x
->array
))
1178 return !x
->array
[0];
1185 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1187 switch (ARRAY_SIZE(x
->array
))
1202 cpu_flags_equal (const union i386_cpu_flags
*x
,
1203 const union i386_cpu_flags
*y
)
1205 switch (ARRAY_SIZE(x
->array
))
1208 if (x
->array
[2] != y
->array
[2])
1211 if (x
->array
[1] != y
->array
[1])
1214 return x
->array
[0] == y
->array
[0];
1222 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1224 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1225 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1228 static INLINE i386_cpu_flags
1229 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1231 switch (ARRAY_SIZE (x
.array
))
1234 x
.array
[2] &= y
.array
[2];
1236 x
.array
[1] &= y
.array
[1];
1238 x
.array
[0] &= y
.array
[0];
1246 static INLINE i386_cpu_flags
1247 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1249 switch (ARRAY_SIZE (x
.array
))
1252 x
.array
[2] |= y
.array
[2];
1254 x
.array
[1] |= y
.array
[1];
1256 x
.array
[0] |= y
.array
[0];
1264 static INLINE i386_cpu_flags
1265 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1267 switch (ARRAY_SIZE (x
.array
))
1270 x
.array
[2] &= ~y
.array
[2];
1272 x
.array
[1] &= ~y
.array
[1];
1274 x
.array
[0] &= ~y
.array
[0];
1282 #define CPU_FLAGS_ARCH_MATCH 0x1
1283 #define CPU_FLAGS_64BIT_MATCH 0x2
1284 #define CPU_FLAGS_AES_MATCH 0x4
1285 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1286 #define CPU_FLAGS_AVX_MATCH 0x10
1288 #define CPU_FLAGS_32BIT_MATCH \
1289 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1290 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1291 #define CPU_FLAGS_PERFECT_MATCH \
1292 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1294 /* Return CPU flags match bits. */
1297 cpu_flags_match (const insn_template
*t
)
1299 i386_cpu_flags x
= t
->cpu_flags
;
1300 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1302 x
.bitfield
.cpu64
= 0;
1303 x
.bitfield
.cpuno64
= 0;
1305 if (cpu_flags_all_zero (&x
))
1307 /* This instruction is available on all archs. */
1308 match
|= CPU_FLAGS_32BIT_MATCH
;
1312 /* This instruction is available only on some archs. */
1313 i386_cpu_flags cpu
= cpu_arch_flags
;
1315 cpu
.bitfield
.cpu64
= 0;
1316 cpu
.bitfield
.cpuno64
= 0;
1317 cpu
= cpu_flags_and (x
, cpu
);
1318 if (!cpu_flags_all_zero (&cpu
))
1320 if (x
.bitfield
.cpuavx
)
1322 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1323 if (cpu
.bitfield
.cpuavx
)
1325 /* Check SSE2AVX. */
1326 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1328 match
|= (CPU_FLAGS_ARCH_MATCH
1329 | CPU_FLAGS_AVX_MATCH
);
1331 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1332 match
|= CPU_FLAGS_AES_MATCH
;
1334 if (!x
.bitfield
.cpupclmul
1335 || cpu
.bitfield
.cpupclmul
)
1336 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1340 match
|= CPU_FLAGS_ARCH_MATCH
;
1343 match
|= CPU_FLAGS_32BIT_MATCH
;
1349 static INLINE i386_operand_type
1350 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1352 switch (ARRAY_SIZE (x
.array
))
1355 x
.array
[2] &= y
.array
[2];
1357 x
.array
[1] &= y
.array
[1];
1359 x
.array
[0] &= y
.array
[0];
1367 static INLINE i386_operand_type
1368 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1370 switch (ARRAY_SIZE (x
.array
))
1373 x
.array
[2] |= y
.array
[2];
1375 x
.array
[1] |= y
.array
[1];
1377 x
.array
[0] |= y
.array
[0];
1385 static INLINE i386_operand_type
1386 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1388 switch (ARRAY_SIZE (x
.array
))
1391 x
.array
[2] ^= y
.array
[2];
1393 x
.array
[1] ^= y
.array
[1];
1395 x
.array
[0] ^= y
.array
[0];
1403 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1404 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1405 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1406 static const i386_operand_type inoutportreg
1407 = OPERAND_TYPE_INOUTPORTREG
;
1408 static const i386_operand_type reg16_inoutportreg
1409 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1410 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1411 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1412 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1413 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1414 static const i386_operand_type anydisp
1415 = OPERAND_TYPE_ANYDISP
;
1416 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1417 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1418 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1419 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1420 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1421 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1422 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1423 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1424 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1425 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1426 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1437 operand_type_check (i386_operand_type t
, enum operand_type c
)
1442 return (t
.bitfield
.reg8
1445 || t
.bitfield
.reg64
);
1448 return (t
.bitfield
.imm8
1452 || t
.bitfield
.imm32s
1453 || t
.bitfield
.imm64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
);
1463 return (t
.bitfield
.disp8
1464 || t
.bitfield
.disp16
1465 || t
.bitfield
.disp32
1466 || t
.bitfield
.disp32s
1467 || t
.bitfield
.disp64
1468 || t
.bitfield
.baseindex
);
1477 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1478 operand J for instruction template T. */
1481 match_reg_size (const insn_template
*t
, unsigned int j
)
1483 return !((i
.types
[j
].bitfield
.byte
1484 && !t
->operand_types
[j
].bitfield
.byte
)
1485 || (i
.types
[j
].bitfield
.word
1486 && !t
->operand_types
[j
].bitfield
.word
)
1487 || (i
.types
[j
].bitfield
.dword
1488 && !t
->operand_types
[j
].bitfield
.dword
)
1489 || (i
.types
[j
].bitfield
.qword
1490 && !t
->operand_types
[j
].bitfield
.qword
));
1493 /* Return 1 if there is no conflict in any size on operand J for
1494 instruction template T. */
1497 match_mem_size (const insn_template
*t
, unsigned int j
)
1499 return (match_reg_size (t
, j
)
1500 && !((i
.types
[j
].bitfield
.unspecified
1501 && !t
->operand_types
[j
].bitfield
.unspecified
)
1502 || (i
.types
[j
].bitfield
.fword
1503 && !t
->operand_types
[j
].bitfield
.fword
)
1504 || (i
.types
[j
].bitfield
.tbyte
1505 && !t
->operand_types
[j
].bitfield
.tbyte
)
1506 || (i
.types
[j
].bitfield
.xmmword
1507 && !t
->operand_types
[j
].bitfield
.xmmword
)
1508 || (i
.types
[j
].bitfield
.ymmword
1509 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1512 /* Return 1 if there is no size conflict on any operands for
1513 instruction template T. */
1516 operand_size_match (const insn_template
*t
)
1521 /* Don't check jump instructions. */
1522 if (t
->opcode_modifier
.jump
1523 || t
->opcode_modifier
.jumpbyte
1524 || t
->opcode_modifier
.jumpdword
1525 || t
->opcode_modifier
.jumpintersegment
)
1528 /* Check memory and accumulator operand size. */
1529 for (j
= 0; j
< i
.operands
; j
++)
1531 if (t
->operand_types
[j
].bitfield
.anysize
)
1534 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1540 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1548 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1551 /* Check reverse. */
1552 gas_assert (i
.operands
== 2);
1555 for (j
= 0; j
< 2; j
++)
1557 if (t
->operand_types
[j
].bitfield
.acc
1558 && !match_reg_size (t
, j
? 0 : 1))
1564 if (i
.types
[j
].bitfield
.mem
1565 && !match_mem_size (t
, j
? 0 : 1))
1576 operand_type_match (i386_operand_type overlap
,
1577 i386_operand_type given
)
1579 i386_operand_type temp
= overlap
;
1581 temp
.bitfield
.jumpabsolute
= 0;
1582 temp
.bitfield
.unspecified
= 0;
1583 temp
.bitfield
.byte
= 0;
1584 temp
.bitfield
.word
= 0;
1585 temp
.bitfield
.dword
= 0;
1586 temp
.bitfield
.fword
= 0;
1587 temp
.bitfield
.qword
= 0;
1588 temp
.bitfield
.tbyte
= 0;
1589 temp
.bitfield
.xmmword
= 0;
1590 temp
.bitfield
.ymmword
= 0;
1591 if (operand_type_all_zero (&temp
))
1594 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1595 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1598 /* If given types g0 and g1 are registers they must be of the same type
1599 unless the expected operand type register overlap is null.
1600 Note that Acc in a template matches every size of reg. */
1603 operand_type_register_match (i386_operand_type m0
,
1604 i386_operand_type g0
,
1605 i386_operand_type t0
,
1606 i386_operand_type m1
,
1607 i386_operand_type g1
,
1608 i386_operand_type t1
)
1610 if (!operand_type_check (g0
, reg
))
1613 if (!operand_type_check (g1
, reg
))
1616 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1617 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1618 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1619 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1622 if (m0
.bitfield
.acc
)
1624 t0
.bitfield
.reg8
= 1;
1625 t0
.bitfield
.reg16
= 1;
1626 t0
.bitfield
.reg32
= 1;
1627 t0
.bitfield
.reg64
= 1;
1630 if (m1
.bitfield
.acc
)
1632 t1
.bitfield
.reg8
= 1;
1633 t1
.bitfield
.reg16
= 1;
1634 t1
.bitfield
.reg32
= 1;
1635 t1
.bitfield
.reg64
= 1;
1638 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1639 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1640 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1641 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1644 static INLINE
unsigned int
1645 mode_from_disp_size (i386_operand_type t
)
1647 if (t
.bitfield
.disp8
)
1649 else if (t
.bitfield
.disp16
1650 || t
.bitfield
.disp32
1651 || t
.bitfield
.disp32s
)
1658 fits_in_signed_byte (offsetT num
)
1660 return (num
>= -128) && (num
<= 127);
1664 fits_in_unsigned_byte (offsetT num
)
1666 return (num
& 0xff) == num
;
1670 fits_in_unsigned_word (offsetT num
)
1672 return (num
& 0xffff) == num
;
1676 fits_in_signed_word (offsetT num
)
1678 return (-32768 <= num
) && (num
<= 32767);
1682 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1687 return (!(((offsetT
) -1 << 31) & num
)
1688 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1690 } /* fits_in_signed_long() */
1693 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1698 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1700 } /* fits_in_unsigned_long() */
1702 static i386_operand_type
1703 smallest_imm_type (offsetT num
)
1705 i386_operand_type t
;
1707 operand_type_set (&t
, 0);
1708 t
.bitfield
.imm64
= 1;
1710 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1712 /* This code is disabled on the 486 because all the Imm1 forms
1713 in the opcode table are slower on the i486. They're the
1714 versions with the implicitly specified single-position
1715 displacement, which has another syntax if you really want to
1717 t
.bitfield
.imm1
= 1;
1718 t
.bitfield
.imm8
= 1;
1719 t
.bitfield
.imm8s
= 1;
1720 t
.bitfield
.imm16
= 1;
1721 t
.bitfield
.imm32
= 1;
1722 t
.bitfield
.imm32s
= 1;
1724 else if (fits_in_signed_byte (num
))
1726 t
.bitfield
.imm8
= 1;
1727 t
.bitfield
.imm8s
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_unsigned_byte (num
))
1734 t
.bitfield
.imm8
= 1;
1735 t
.bitfield
.imm16
= 1;
1736 t
.bitfield
.imm32
= 1;
1737 t
.bitfield
.imm32s
= 1;
1739 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1741 t
.bitfield
.imm16
= 1;
1742 t
.bitfield
.imm32
= 1;
1743 t
.bitfield
.imm32s
= 1;
1745 else if (fits_in_signed_long (num
))
1747 t
.bitfield
.imm32
= 1;
1748 t
.bitfield
.imm32s
= 1;
1750 else if (fits_in_unsigned_long (num
))
1751 t
.bitfield
.imm32
= 1;
1757 offset_in_range (offsetT val
, int size
)
1763 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1764 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1765 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1767 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1773 /* If BFD64, sign extend val for 32bit address mode. */
1774 if (flag_code
!= CODE_64BIT
1775 || i
.prefix
[ADDR_PREFIX
])
1776 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1777 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1780 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1782 char buf1
[40], buf2
[40];
1784 sprint_value (buf1
, val
);
1785 sprint_value (buf2
, val
& mask
);
1786 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1800 a. PREFIX_EXIST if attempting to add a prefix where one from the
1801 same class already exists.
1802 b. PREFIX_LOCK if lock prefix is added.
1803 c. PREFIX_REP if rep/repne prefix is added.
1804 d. PREFIX_OTHER if other prefix is added.
1807 static enum PREFIX_GROUP
1808 add_prefix (unsigned int prefix
)
1810 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1813 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1814 && flag_code
== CODE_64BIT
)
1816 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1817 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1818 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1829 case CS_PREFIX_OPCODE
:
1830 case DS_PREFIX_OPCODE
:
1831 case ES_PREFIX_OPCODE
:
1832 case FS_PREFIX_OPCODE
:
1833 case GS_PREFIX_OPCODE
:
1834 case SS_PREFIX_OPCODE
:
1838 case REPNE_PREFIX_OPCODE
:
1839 case REPE_PREFIX_OPCODE
:
1844 case LOCK_PREFIX_OPCODE
:
1853 case ADDR_PREFIX_OPCODE
:
1857 case DATA_PREFIX_OPCODE
:
1861 if (i
.prefix
[q
] != 0)
1869 i
.prefix
[q
] |= prefix
;
1872 as_bad (_("same type of prefix used twice"));
1878 set_code_flag (int value
)
1880 flag_code
= (enum flag_code
) value
;
1881 if (flag_code
== CODE_64BIT
)
1883 cpu_arch_flags
.bitfield
.cpu64
= 1;
1884 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1888 cpu_arch_flags
.bitfield
.cpu64
= 0;
1889 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1891 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1893 as_bad (_("64bit mode not supported on this CPU."));
1895 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1897 as_bad (_("32bit mode not supported on this CPU."));
1899 stackop_size
= '\0';
1903 set_16bit_gcc_code_flag (int new_code_flag
)
1905 flag_code
= (enum flag_code
) new_code_flag
;
1906 if (flag_code
!= CODE_16BIT
)
1908 cpu_arch_flags
.bitfield
.cpu64
= 0;
1909 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1910 stackop_size
= LONG_MNEM_SUFFIX
;
1914 set_intel_syntax (int syntax_flag
)
1916 /* Find out if register prefixing is specified. */
1917 int ask_naked_reg
= 0;
1920 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1922 char *string
= input_line_pointer
;
1923 int e
= get_symbol_end ();
1925 if (strcmp (string
, "prefix") == 0)
1927 else if (strcmp (string
, "noprefix") == 0)
1930 as_bad (_("bad argument to syntax directive."));
1931 *input_line_pointer
= e
;
1933 demand_empty_rest_of_line ();
1935 intel_syntax
= syntax_flag
;
1937 if (ask_naked_reg
== 0)
1938 allow_naked_reg
= (intel_syntax
1939 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1941 allow_naked_reg
= (ask_naked_reg
< 0);
1943 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1945 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1946 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1947 register_prefix
= allow_naked_reg
? "" : "%";
1951 set_intel_mnemonic (int mnemonic_flag
)
1953 intel_mnemonic
= mnemonic_flag
;
1957 set_allow_index_reg (int flag
)
1959 allow_index_reg
= flag
;
1963 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1967 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1969 char *string
= input_line_pointer
;
1970 int e
= get_symbol_end ();
1972 if (strcmp (string
, "none") == 0)
1973 sse_check
= sse_check_none
;
1974 else if (strcmp (string
, "warning") == 0)
1975 sse_check
= sse_check_warning
;
1976 else if (strcmp (string
, "error") == 0)
1977 sse_check
= sse_check_error
;
1979 as_bad (_("bad argument to sse_check directive."));
1980 *input_line_pointer
= e
;
1983 as_bad (_("missing argument for sse_check directive"));
1985 demand_empty_rest_of_line ();
1989 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1990 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1993 static const char *arch
;
1995 /* Intel LIOM is only supported on ELF. */
2001 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2002 use default_arch. */
2003 arch
= cpu_arch_name
;
2005 arch
= default_arch
;
2008 /* If we are targeting Intel L1OM, we must enable it. */
2009 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2010 || new_flag
.bitfield
.cpul1om
)
2013 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2018 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2022 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2024 char *string
= input_line_pointer
;
2025 int e
= get_symbol_end ();
2027 i386_cpu_flags flags
;
2029 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2031 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2033 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2037 cpu_arch_name
= cpu_arch
[j
].name
;
2038 cpu_sub_arch_name
= NULL
;
2039 cpu_arch_flags
= cpu_arch
[j
].flags
;
2040 if (flag_code
== CODE_64BIT
)
2042 cpu_arch_flags
.bitfield
.cpu64
= 1;
2043 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2047 cpu_arch_flags
.bitfield
.cpu64
= 0;
2048 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2050 cpu_arch_isa
= cpu_arch
[j
].type
;
2051 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2052 if (!cpu_arch_tune_set
)
2054 cpu_arch_tune
= cpu_arch_isa
;
2055 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2060 if (strncmp (string
+ 1, "no", 2))
2061 flags
= cpu_flags_or (cpu_arch_flags
,
2064 flags
= cpu_flags_and_not (cpu_arch_flags
,
2066 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2068 if (cpu_sub_arch_name
)
2070 char *name
= cpu_sub_arch_name
;
2071 cpu_sub_arch_name
= concat (name
,
2073 (const char *) NULL
);
2077 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2078 cpu_arch_flags
= flags
;
2080 *input_line_pointer
= e
;
2081 demand_empty_rest_of_line ();
2085 if (j
>= ARRAY_SIZE (cpu_arch
))
2086 as_bad (_("no such architecture: `%s'"), string
);
2088 *input_line_pointer
= e
;
2091 as_bad (_("missing cpu architecture"));
2093 no_cond_jump_promotion
= 0;
2094 if (*input_line_pointer
== ','
2095 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2097 char *string
= ++input_line_pointer
;
2098 int e
= get_symbol_end ();
2100 if (strcmp (string
, "nojumps") == 0)
2101 no_cond_jump_promotion
= 1;
2102 else if (strcmp (string
, "jumps") == 0)
2105 as_bad (_("no such architecture modifier: `%s'"), string
);
2107 *input_line_pointer
= e
;
2110 demand_empty_rest_of_line ();
2113 enum bfd_architecture
2116 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2118 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2119 || flag_code
!= CODE_64BIT
)
2120 as_fatal (_("Intel L1OM is 64bit ELF only"));
2121 return bfd_arch_l1om
;
2124 return bfd_arch_i386
;
2130 if (!strcmp (default_arch
, "x86_64"))
2132 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2134 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2135 as_fatal (_("Intel L1OM is 64bit ELF only"));
2136 return bfd_mach_l1om
;
2139 return bfd_mach_x86_64
;
2141 else if (!strcmp (default_arch
, "i386"))
2142 return bfd_mach_i386_i386
;
2144 as_fatal (_("Unknown architecture"));
2150 const char *hash_err
;
2152 /* Initialize op_hash hash table. */
2153 op_hash
= hash_new ();
2156 const insn_template
*optab
;
2157 templates
*core_optab
;
2159 /* Setup for loop. */
2161 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2162 core_optab
->start
= optab
;
2167 if (optab
->name
== NULL
2168 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2170 /* different name --> ship out current template list;
2171 add to hash table; & begin anew. */
2172 core_optab
->end
= optab
;
2173 hash_err
= hash_insert (op_hash
,
2175 (void *) core_optab
);
2178 as_fatal (_("Internal Error: Can't hash %s: %s"),
2182 if (optab
->name
== NULL
)
2184 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2185 core_optab
->start
= optab
;
2190 /* Initialize reg_hash hash table. */
2191 reg_hash
= hash_new ();
2193 const reg_entry
*regtab
;
2194 unsigned int regtab_size
= i386_regtab_size
;
2196 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2198 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2200 as_fatal (_("Internal Error: Can't hash %s: %s"),
2206 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2211 for (c
= 0; c
< 256; c
++)
2216 mnemonic_chars
[c
] = c
;
2217 register_chars
[c
] = c
;
2218 operand_chars
[c
] = c
;
2220 else if (ISLOWER (c
))
2222 mnemonic_chars
[c
] = c
;
2223 register_chars
[c
] = c
;
2224 operand_chars
[c
] = c
;
2226 else if (ISUPPER (c
))
2228 mnemonic_chars
[c
] = TOLOWER (c
);
2229 register_chars
[c
] = mnemonic_chars
[c
];
2230 operand_chars
[c
] = c
;
2233 if (ISALPHA (c
) || ISDIGIT (c
))
2234 identifier_chars
[c
] = c
;
2237 identifier_chars
[c
] = c
;
2238 operand_chars
[c
] = c
;
2243 identifier_chars
['@'] = '@';
2246 identifier_chars
['?'] = '?';
2247 operand_chars
['?'] = '?';
2249 digit_chars
['-'] = '-';
2250 mnemonic_chars
['_'] = '_';
2251 mnemonic_chars
['-'] = '-';
2252 mnemonic_chars
['.'] = '.';
2253 identifier_chars
['_'] = '_';
2254 identifier_chars
['.'] = '.';
2256 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2257 operand_chars
[(unsigned char) *p
] = *p
;
2260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2263 record_alignment (text_section
, 2);
2264 record_alignment (data_section
, 2);
2265 record_alignment (bss_section
, 2);
2269 if (flag_code
== CODE_64BIT
)
2271 x86_dwarf2_return_column
= 16;
2272 x86_cie_data_alignment
= -8;
2276 x86_dwarf2_return_column
= 8;
2277 x86_cie_data_alignment
= -4;
2282 i386_print_statistics (FILE *file
)
2284 hash_print_statistics (file
, "i386 opcode", op_hash
);
2285 hash_print_statistics (file
, "i386 register", reg_hash
);
2290 /* Debugging routines for md_assemble. */
2291 static void pte (insn_template
*);
2292 static void pt (i386_operand_type
);
2293 static void pe (expressionS
*);
2294 static void ps (symbolS
*);
2297 pi (char *line
, i386_insn
*x
)
2301 fprintf (stdout
, "%s: template ", line
);
2303 fprintf (stdout
, " address: base %s index %s scale %x\n",
2304 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2305 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2306 x
->log2_scale_factor
);
2307 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2308 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2309 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2310 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2311 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2312 (x
->rex
& REX_W
) != 0,
2313 (x
->rex
& REX_R
) != 0,
2314 (x
->rex
& REX_X
) != 0,
2315 (x
->rex
& REX_B
) != 0);
2316 for (i
= 0; i
< x
->operands
; i
++)
2318 fprintf (stdout
, " #%d: ", i
+ 1);
2320 fprintf (stdout
, "\n");
2321 if (x
->types
[i
].bitfield
.reg8
2322 || x
->types
[i
].bitfield
.reg16
2323 || x
->types
[i
].bitfield
.reg32
2324 || x
->types
[i
].bitfield
.reg64
2325 || x
->types
[i
].bitfield
.regmmx
2326 || x
->types
[i
].bitfield
.regxmm
2327 || x
->types
[i
].bitfield
.regymm
2328 || x
->types
[i
].bitfield
.sreg2
2329 || x
->types
[i
].bitfield
.sreg3
2330 || x
->types
[i
].bitfield
.control
2331 || x
->types
[i
].bitfield
.debug
2332 || x
->types
[i
].bitfield
.test
)
2333 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2334 if (operand_type_check (x
->types
[i
], imm
))
2336 if (operand_type_check (x
->types
[i
], disp
))
2337 pe (x
->op
[i
].disps
);
2342 pte (insn_template
*t
)
2345 fprintf (stdout
, " %d operands ", t
->operands
);
2346 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2347 if (t
->extension_opcode
!= None
)
2348 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2349 if (t
->opcode_modifier
.d
)
2350 fprintf (stdout
, "D");
2351 if (t
->opcode_modifier
.w
)
2352 fprintf (stdout
, "W");
2353 fprintf (stdout
, "\n");
2354 for (i
= 0; i
< t
->operands
; i
++)
2356 fprintf (stdout
, " #%d type ", i
+ 1);
2357 pt (t
->operand_types
[i
]);
2358 fprintf (stdout
, "\n");
2365 fprintf (stdout
, " operation %d\n", e
->X_op
);
2366 fprintf (stdout
, " add_number %ld (%lx)\n",
2367 (long) e
->X_add_number
, (long) e
->X_add_number
);
2368 if (e
->X_add_symbol
)
2370 fprintf (stdout
, " add_symbol ");
2371 ps (e
->X_add_symbol
);
2372 fprintf (stdout
, "\n");
2376 fprintf (stdout
, " op_symbol ");
2377 ps (e
->X_op_symbol
);
2378 fprintf (stdout
, "\n");
2385 fprintf (stdout
, "%s type %s%s",
2387 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2388 segment_name (S_GET_SEGMENT (s
)));
2391 static struct type_name
2393 i386_operand_type mask
;
2396 const type_names
[] =
2398 { OPERAND_TYPE_REG8
, "r8" },
2399 { OPERAND_TYPE_REG16
, "r16" },
2400 { OPERAND_TYPE_REG32
, "r32" },
2401 { OPERAND_TYPE_REG64
, "r64" },
2402 { OPERAND_TYPE_IMM8
, "i8" },
2403 { OPERAND_TYPE_IMM8
, "i8s" },
2404 { OPERAND_TYPE_IMM16
, "i16" },
2405 { OPERAND_TYPE_IMM32
, "i32" },
2406 { OPERAND_TYPE_IMM32S
, "i32s" },
2407 { OPERAND_TYPE_IMM64
, "i64" },
2408 { OPERAND_TYPE_IMM1
, "i1" },
2409 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2410 { OPERAND_TYPE_DISP8
, "d8" },
2411 { OPERAND_TYPE_DISP16
, "d16" },
2412 { OPERAND_TYPE_DISP32
, "d32" },
2413 { OPERAND_TYPE_DISP32S
, "d32s" },
2414 { OPERAND_TYPE_DISP64
, "d64" },
2415 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2416 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2417 { OPERAND_TYPE_CONTROL
, "control reg" },
2418 { OPERAND_TYPE_TEST
, "test reg" },
2419 { OPERAND_TYPE_DEBUG
, "debug reg" },
2420 { OPERAND_TYPE_FLOATREG
, "FReg" },
2421 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2422 { OPERAND_TYPE_SREG2
, "SReg2" },
2423 { OPERAND_TYPE_SREG3
, "SReg3" },
2424 { OPERAND_TYPE_ACC
, "Acc" },
2425 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2426 { OPERAND_TYPE_REGMMX
, "rMMX" },
2427 { OPERAND_TYPE_REGXMM
, "rXMM" },
2428 { OPERAND_TYPE_REGYMM
, "rYMM" },
2429 { OPERAND_TYPE_ESSEG
, "es" },
2433 pt (i386_operand_type t
)
2436 i386_operand_type a
;
2438 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2440 a
= operand_type_and (t
, type_names
[j
].mask
);
2441 if (!operand_type_all_zero (&a
))
2442 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2447 #endif /* DEBUG386 */
2449 static bfd_reloc_code_real_type
2450 reloc (unsigned int size
,
2453 bfd_reloc_code_real_type other
)
2455 if (other
!= NO_RELOC
)
2457 reloc_howto_type
*rel
;
2462 case BFD_RELOC_X86_64_GOT32
:
2463 return BFD_RELOC_X86_64_GOT64
;
2465 case BFD_RELOC_X86_64_PLTOFF64
:
2466 return BFD_RELOC_X86_64_PLTOFF64
;
2468 case BFD_RELOC_X86_64_GOTPC32
:
2469 other
= BFD_RELOC_X86_64_GOTPC64
;
2471 case BFD_RELOC_X86_64_GOTPCREL
:
2472 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2474 case BFD_RELOC_X86_64_TPOFF32
:
2475 other
= BFD_RELOC_X86_64_TPOFF64
;
2477 case BFD_RELOC_X86_64_DTPOFF32
:
2478 other
= BFD_RELOC_X86_64_DTPOFF64
;
2484 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2485 if (size
== 4 && flag_code
!= CODE_64BIT
)
2488 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2490 as_bad (_("unknown relocation (%u)"), other
);
2491 else if (size
!= bfd_get_reloc_size (rel
))
2492 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2493 bfd_get_reloc_size (rel
),
2495 else if (pcrel
&& !rel
->pc_relative
)
2496 as_bad (_("non-pc-relative relocation for pc-relative field"));
2497 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2499 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2501 as_bad (_("relocated field and relocation type differ in signedness"));
2510 as_bad (_("there are no unsigned pc-relative relocations"));
2513 case 1: return BFD_RELOC_8_PCREL
;
2514 case 2: return BFD_RELOC_16_PCREL
;
2515 case 4: return BFD_RELOC_32_PCREL
;
2516 case 8: return BFD_RELOC_64_PCREL
;
2518 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2525 case 4: return BFD_RELOC_X86_64_32S
;
2530 case 1: return BFD_RELOC_8
;
2531 case 2: return BFD_RELOC_16
;
2532 case 4: return BFD_RELOC_32
;
2533 case 8: return BFD_RELOC_64
;
2535 as_bad (_("cannot do %s %u byte relocation"),
2536 sign
> 0 ? "signed" : "unsigned", size
);
2542 /* Here we decide which fixups can be adjusted to make them relative to
2543 the beginning of the section instead of the symbol. Basically we need
2544 to make sure that the dynamic relocations are done correctly, so in
2545 some cases we force the original symbol to be used. */
2548 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2550 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2554 /* Don't adjust pc-relative references to merge sections in 64-bit
2556 if (use_rela_relocations
2557 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2561 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2562 and changed later by validate_fix. */
2563 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2564 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2567 /* adjust_reloc_syms doesn't know about the GOT. */
2568 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2569 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2570 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2574 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2575 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2576 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2577 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2578 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2579 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2580 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2590 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2591 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2592 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2593 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2594 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2595 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2602 intel_float_operand (const char *mnemonic
)
2604 /* Note that the value returned is meaningful only for opcodes with (memory)
2605 operands, hence the code here is free to improperly handle opcodes that
2606 have no operands (for better performance and smaller code). */
2608 if (mnemonic
[0] != 'f')
2609 return 0; /* non-math */
2611 switch (mnemonic
[1])
2613 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2614 the fs segment override prefix not currently handled because no
2615 call path can make opcodes without operands get here */
2617 return 2 /* integer op */;
2619 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2620 return 3; /* fldcw/fldenv */
2623 if (mnemonic
[2] != 'o' /* fnop */)
2624 return 3; /* non-waiting control op */
2627 if (mnemonic
[2] == 's')
2628 return 3; /* frstor/frstpm */
2631 if (mnemonic
[2] == 'a')
2632 return 3; /* fsave */
2633 if (mnemonic
[2] == 't')
2635 switch (mnemonic
[3])
2637 case 'c': /* fstcw */
2638 case 'd': /* fstdw */
2639 case 'e': /* fstenv */
2640 case 's': /* fsts[gw] */
2646 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2647 return 0; /* fxsave/fxrstor are not really math ops */
2654 /* Build the VEX prefix. */
2657 build_vex_prefix (const insn_template
*t
)
2659 unsigned int register_specifier
;
2660 unsigned int implied_prefix
;
2661 unsigned int vector_length
;
2663 /* Check register specifier. */
2664 if (i
.vex
.register_specifier
)
2666 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2667 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2668 register_specifier
+= 8;
2669 register_specifier
= ~register_specifier
& 0xf;
2672 register_specifier
= 0xf;
2674 /* Use 2-byte VEX prefix by swappping destination and source
2677 && i
.operands
== i
.reg_operands
2678 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2679 && i
.tm
.opcode_modifier
.s
2682 unsigned int xchg
= i
.operands
- 1;
2683 union i386_op temp_op
;
2684 i386_operand_type temp_type
;
2686 temp_type
= i
.types
[xchg
];
2687 i
.types
[xchg
] = i
.types
[0];
2688 i
.types
[0] = temp_type
;
2689 temp_op
= i
.op
[xchg
];
2690 i
.op
[xchg
] = i
.op
[0];
2693 gas_assert (i
.rm
.mode
== 3);
2697 i
.rm
.regmem
= i
.rm
.reg
;
2700 /* Use the next insn. */
2704 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2706 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2711 case DATA_PREFIX_OPCODE
:
2714 case REPE_PREFIX_OPCODE
:
2717 case REPNE_PREFIX_OPCODE
:
2724 /* Use 2-byte VEX prefix if possible. */
2725 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2726 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2728 /* 2-byte VEX prefix. */
2732 i
.vex
.bytes
[0] = 0xc5;
2734 /* Check the REX.R bit. */
2735 r
= (i
.rex
& REX_R
) ? 0 : 1;
2736 i
.vex
.bytes
[1] = (r
<< 7
2737 | register_specifier
<< 3
2738 | vector_length
<< 2
2743 /* 3-byte VEX prefix. */
2747 i
.vex
.bytes
[0] = 0xc4;
2749 switch (i
.tm
.opcode_modifier
.vexopcode
)
2762 i
.vex
.bytes
[0] = 0x8f;
2766 i
.vex
.bytes
[0] = 0x8f;
2770 i
.vex
.bytes
[0] = 0x8f;
2776 /* The high 3 bits of the second VEX byte are 1's compliment
2777 of RXB bits from REX. */
2778 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2780 /* Check the REX.W bit. */
2781 w
= (i
.rex
& REX_W
) ? 1 : 0;
2782 if (i
.tm
.opcode_modifier
.vexw
)
2787 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2791 i
.vex
.bytes
[2] = (w
<< 7
2792 | register_specifier
<< 3
2793 | vector_length
<< 2
2799 process_immext (void)
2803 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2805 /* SSE3 Instructions have the fixed operands with an opcode
2806 suffix which is coded in the same place as an 8-bit immediate
2807 field would be. Here we check those operands and remove them
2811 for (x
= 0; x
< i
.operands
; x
++)
2812 if (i
.op
[x
].regs
->reg_num
!= x
)
2813 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2814 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2820 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2821 which is coded in the same place as an 8-bit immediate field
2822 would be. Here we fake an 8-bit immediate operand from the
2823 opcode suffix stored in tm.extension_opcode.
2825 AVX instructions also use this encoding, for some of
2826 3 argument instructions. */
2828 gas_assert (i
.imm_operands
== 0
2830 || (i
.tm
.opcode_modifier
.vex
2831 && i
.operands
<= 4)));
2833 exp
= &im_expressions
[i
.imm_operands
++];
2834 i
.op
[i
.operands
].imms
= exp
;
2835 i
.types
[i
.operands
] = imm8
;
2837 exp
->X_op
= O_constant
;
2838 exp
->X_add_number
= i
.tm
.extension_opcode
;
2839 i
.tm
.extension_opcode
= None
;
2842 /* This is the guts of the machine-dependent assembler. LINE points to a
2843 machine dependent instruction. This function is supposed to emit
2844 the frags/bytes it assembles to. */
2847 md_assemble (char *line
)
2850 char mnemonic
[MAX_MNEM_SIZE
];
2851 const insn_template
*t
;
2853 /* Initialize globals. */
2854 memset (&i
, '\0', sizeof (i
));
2855 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2856 i
.reloc
[j
] = NO_RELOC
;
2857 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2858 memset (im_expressions
, '\0', sizeof (im_expressions
));
2859 save_stack_p
= save_stack
;
2861 /* First parse an instruction mnemonic & call i386_operand for the operands.
2862 We assume that the scrubber has arranged it so that line[0] is the valid
2863 start of a (possibly prefixed) mnemonic. */
2865 line
= parse_insn (line
, mnemonic
);
2869 line
= parse_operands (line
, mnemonic
);
2874 /* Now we've parsed the mnemonic into a set of templates, and have the
2875 operands at hand. */
2877 /* All intel opcodes have reversed operands except for "bound" and
2878 "enter". We also don't reverse intersegment "jmp" and "call"
2879 instructions with 2 immediate operands so that the immediate segment
2880 precedes the offset, as it does when in AT&T mode. */
2883 && (strcmp (mnemonic
, "bound") != 0)
2884 && (strcmp (mnemonic
, "invlpga") != 0)
2885 && !(operand_type_check (i
.types
[0], imm
)
2886 && operand_type_check (i
.types
[1], imm
)))
2889 /* The order of the immediates should be reversed
2890 for 2 immediates extrq and insertq instructions */
2891 if (i
.imm_operands
== 2
2892 && (strcmp (mnemonic
, "extrq") == 0
2893 || strcmp (mnemonic
, "insertq") == 0))
2894 swap_2_operands (0, 1);
2899 /* Don't optimize displacement for movabs since it only takes 64bit
2902 && (flag_code
!= CODE_64BIT
2903 || strcmp (mnemonic
, "movabs") != 0))
2906 /* Next, we find a template that matches the given insn,
2907 making sure the overlap of the given operands types is consistent
2908 with the template operand types. */
2910 if (!(t
= match_template ()))
2913 if (sse_check
!= sse_check_none
2914 && !i
.tm
.opcode_modifier
.noavx
2915 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2916 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2917 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2918 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2919 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2920 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2922 (sse_check
== sse_check_warning
2924 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2927 /* Zap movzx and movsx suffix. The suffix has been set from
2928 "word ptr" or "byte ptr" on the source operand in Intel syntax
2929 or extracted from mnemonic in AT&T syntax. But we'll use
2930 the destination register to choose the suffix for encoding. */
2931 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2933 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2934 there is no suffix, the default will be byte extension. */
2935 if (i
.reg_operands
!= 2
2938 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2943 if (i
.tm
.opcode_modifier
.fwait
)
2944 if (!add_prefix (FWAIT_OPCODE
))
2947 /* Check for lock without a lockable instruction. Destination operand
2948 must be memory unless it is xchg (0x86). */
2949 if (i
.prefix
[LOCK_PREFIX
]
2950 && (!i
.tm
.opcode_modifier
.islockable
2951 || i
.mem_operands
== 0
2952 || (i
.tm
.base_opcode
!= 0x86
2953 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2955 as_bad (_("expecting lockable instruction after `lock'"));
2959 /* Check string instruction segment overrides. */
2960 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2962 if (!check_string ())
2964 i
.disp_operands
= 0;
2967 if (!process_suffix ())
2970 /* Update operand types. */
2971 for (j
= 0; j
< i
.operands
; j
++)
2972 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2974 /* Make still unresolved immediate matches conform to size of immediate
2975 given in i.suffix. */
2976 if (!finalize_imm ())
2979 if (i
.types
[0].bitfield
.imm1
)
2980 i
.imm_operands
= 0; /* kludge for shift insns. */
2982 /* We only need to check those implicit registers for instructions
2983 with 3 operands or less. */
2984 if (i
.operands
<= 3)
2985 for (j
= 0; j
< i
.operands
; j
++)
2986 if (i
.types
[j
].bitfield
.inoutportreg
2987 || i
.types
[j
].bitfield
.shiftcount
2988 || i
.types
[j
].bitfield
.acc
2989 || i
.types
[j
].bitfield
.floatacc
)
2992 /* ImmExt should be processed after SSE2AVX. */
2993 if (!i
.tm
.opcode_modifier
.sse2avx
2994 && i
.tm
.opcode_modifier
.immext
)
2997 /* For insns with operands there are more diddles to do to the opcode. */
3000 if (!process_operands ())
3003 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3005 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3006 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3009 if (i
.tm
.opcode_modifier
.vex
)
3010 build_vex_prefix (t
);
3012 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3013 instructions may define INT_OPCODE as well, so avoid this corner
3014 case for those instructions that use MODRM. */
3015 if (i
.tm
.base_opcode
== INT_OPCODE
3016 && i
.op
[0].imms
->X_add_number
== 3
3017 && !i
.tm
.opcode_modifier
.modrm
)
3019 i
.tm
.base_opcode
= INT3_OPCODE
;
3023 if ((i
.tm
.opcode_modifier
.jump
3024 || i
.tm
.opcode_modifier
.jumpbyte
3025 || i
.tm
.opcode_modifier
.jumpdword
)
3026 && i
.op
[0].disps
->X_op
== O_constant
)
3028 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3029 the absolute address given by the constant. Since ix86 jumps and
3030 calls are pc relative, we need to generate a reloc. */
3031 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3032 i
.op
[0].disps
->X_op
= O_symbol
;
3035 if (i
.tm
.opcode_modifier
.rex64
)
3038 /* For 8 bit registers we need an empty rex prefix. Also if the
3039 instruction already has a prefix, we need to convert old
3040 registers to new ones. */
3042 if ((i
.types
[0].bitfield
.reg8
3043 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3044 || (i
.types
[1].bitfield
.reg8
3045 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3046 || ((i
.types
[0].bitfield
.reg8
3047 || i
.types
[1].bitfield
.reg8
)
3052 i
.rex
|= REX_OPCODE
;
3053 for (x
= 0; x
< 2; x
++)
3055 /* Look for 8 bit operand that uses old registers. */
3056 if (i
.types
[x
].bitfield
.reg8
3057 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3059 /* In case it is "hi" register, give up. */
3060 if (i
.op
[x
].regs
->reg_num
> 3)
3061 as_bad (_("can't encode register '%s%s' in an "
3062 "instruction requiring REX prefix."),
3063 register_prefix
, i
.op
[x
].regs
->reg_name
);
3065 /* Otherwise it is equivalent to the extended register.
3066 Since the encoding doesn't change this is merely
3067 cosmetic cleanup for debug output. */
3069 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3075 add_prefix (REX_OPCODE
| i
.rex
);
3077 /* We are ready to output the insn. */
3082 parse_insn (char *line
, char *mnemonic
)
3085 char *token_start
= l
;
3088 const insn_template
*t
;
3091 /* Non-zero if we found a prefix only acceptable with string insns. */
3092 const char *expecting_string_instruction
= NULL
;
3097 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3102 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3104 as_bad (_("no such instruction: `%s'"), token_start
);
3109 if (!is_space_char (*l
)
3110 && *l
!= END_OF_INSN
3112 || (*l
!= PREFIX_SEPARATOR
3115 as_bad (_("invalid character %s in mnemonic"),
3116 output_invalid (*l
));
3119 if (token_start
== l
)
3121 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3122 as_bad (_("expecting prefix; got nothing"));
3124 as_bad (_("expecting mnemonic; got nothing"));
3128 /* Look up instruction (or prefix) via hash table. */
3129 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3131 if (*l
!= END_OF_INSN
3132 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3133 && current_templates
3134 && current_templates
->start
->opcode_modifier
.isprefix
)
3136 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3138 as_bad ((flag_code
!= CODE_64BIT
3139 ? _("`%s' is only supported in 64-bit mode")
3140 : _("`%s' is not supported in 64-bit mode")),
3141 current_templates
->start
->name
);
3144 /* If we are in 16-bit mode, do not allow addr16 or data16.
3145 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3146 if ((current_templates
->start
->opcode_modifier
.size16
3147 || current_templates
->start
->opcode_modifier
.size32
)
3148 && flag_code
!= CODE_64BIT
3149 && (current_templates
->start
->opcode_modifier
.size32
3150 ^ (flag_code
== CODE_16BIT
)))
3152 as_bad (_("redundant %s prefix"),
3153 current_templates
->start
->name
);
3156 /* Add prefix, checking for repeated prefixes. */
3157 switch (add_prefix (current_templates
->start
->base_opcode
))
3162 expecting_string_instruction
= current_templates
->start
->name
;
3167 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3174 if (!current_templates
)
3176 /* Check if we should swap operand in encoding. */
3177 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3183 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3186 if (!current_templates
)
3189 /* See if we can get a match by trimming off a suffix. */
3192 case WORD_MNEM_SUFFIX
:
3193 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3194 i
.suffix
= SHORT_MNEM_SUFFIX
;
3196 case BYTE_MNEM_SUFFIX
:
3197 case QWORD_MNEM_SUFFIX
:
3198 i
.suffix
= mnem_p
[-1];
3200 current_templates
= (const templates
*) hash_find (op_hash
,
3203 case SHORT_MNEM_SUFFIX
:
3204 case LONG_MNEM_SUFFIX
:
3207 i
.suffix
= mnem_p
[-1];
3209 current_templates
= (const templates
*) hash_find (op_hash
,
3218 if (intel_float_operand (mnemonic
) == 1)
3219 i
.suffix
= SHORT_MNEM_SUFFIX
;
3221 i
.suffix
= LONG_MNEM_SUFFIX
;
3223 current_templates
= (const templates
*) hash_find (op_hash
,
3228 if (!current_templates
)
3230 as_bad (_("no such instruction: `%s'"), token_start
);
3235 if (current_templates
->start
->opcode_modifier
.jump
3236 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3238 /* Check for a branch hint. We allow ",pt" and ",pn" for
3239 predict taken and predict not taken respectively.
3240 I'm not sure that branch hints actually do anything on loop
3241 and jcxz insns (JumpByte) for current Pentium4 chips. They
3242 may work in the future and it doesn't hurt to accept them
3244 if (l
[0] == ',' && l
[1] == 'p')
3248 if (!add_prefix (DS_PREFIX_OPCODE
))
3252 else if (l
[2] == 'n')
3254 if (!add_prefix (CS_PREFIX_OPCODE
))
3260 /* Any other comma loses. */
3263 as_bad (_("invalid character %s in mnemonic"),
3264 output_invalid (*l
));
3268 /* Check if instruction is supported on specified architecture. */
3270 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3272 supported
|= cpu_flags_match (t
);
3273 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3277 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3279 as_bad (flag_code
== CODE_64BIT
3280 ? _("`%s' is not supported in 64-bit mode")
3281 : _("`%s' is only supported in 64-bit mode"),
3282 current_templates
->start
->name
);
3285 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3287 as_bad (_("`%s' is not supported on `%s%s'"),
3288 current_templates
->start
->name
,
3289 cpu_arch_name
? cpu_arch_name
: default_arch
,
3290 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3295 if (!cpu_arch_flags
.bitfield
.cpui386
3296 && (flag_code
!= CODE_16BIT
))
3298 as_warn (_("use .code16 to ensure correct addressing mode"));
3301 /* Check for rep/repne without a string instruction. */
3302 if (expecting_string_instruction
)
3304 static templates override
;
3306 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3307 if (t
->opcode_modifier
.isstring
)
3309 if (t
>= current_templates
->end
)
3311 as_bad (_("expecting string instruction after `%s'"),
3312 expecting_string_instruction
);
3315 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3316 if (!t
->opcode_modifier
.isstring
)
3319 current_templates
= &override
;
3326 parse_operands (char *l
, const char *mnemonic
)
3330 /* 1 if operand is pending after ','. */
3331 unsigned int expecting_operand
= 0;
3333 /* Non-zero if operand parens not balanced. */
3334 unsigned int paren_not_balanced
;
3336 while (*l
!= END_OF_INSN
)
3338 /* Skip optional white space before operand. */
3339 if (is_space_char (*l
))
3341 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3343 as_bad (_("invalid character %s before operand %d"),
3344 output_invalid (*l
),
3348 token_start
= l
; /* after white space */
3349 paren_not_balanced
= 0;
3350 while (paren_not_balanced
|| *l
!= ',')
3352 if (*l
== END_OF_INSN
)
3354 if (paren_not_balanced
)
3357 as_bad (_("unbalanced parenthesis in operand %d."),
3360 as_bad (_("unbalanced brackets in operand %d."),
3365 break; /* we are done */
3367 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3369 as_bad (_("invalid character %s in operand %d"),
3370 output_invalid (*l
),
3377 ++paren_not_balanced
;
3379 --paren_not_balanced
;
3384 ++paren_not_balanced
;
3386 --paren_not_balanced
;
3390 if (l
!= token_start
)
3391 { /* Yes, we've read in another operand. */
3392 unsigned int operand_ok
;
3393 this_operand
= i
.operands
++;
3394 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3395 if (i
.operands
> MAX_OPERANDS
)
3397 as_bad (_("spurious operands; (%d operands/instruction max)"),
3401 /* Now parse operand adding info to 'i' as we go along. */
3402 END_STRING_AND_SAVE (l
);
3406 i386_intel_operand (token_start
,
3407 intel_float_operand (mnemonic
));
3409 operand_ok
= i386_att_operand (token_start
);
3411 RESTORE_END_STRING (l
);
3417 if (expecting_operand
)
3419 expecting_operand_after_comma
:
3420 as_bad (_("expecting operand after ','; got nothing"));
3425 as_bad (_("expecting operand before ','; got nothing"));
3430 /* Now *l must be either ',' or END_OF_INSN. */
3433 if (*++l
== END_OF_INSN
)
3435 /* Just skip it, if it's \n complain. */
3436 goto expecting_operand_after_comma
;
3438 expecting_operand
= 1;
3445 swap_2_operands (int xchg1
, int xchg2
)
3447 union i386_op temp_op
;
3448 i386_operand_type temp_type
;
3449 enum bfd_reloc_code_real temp_reloc
;
3451 temp_type
= i
.types
[xchg2
];
3452 i
.types
[xchg2
] = i
.types
[xchg1
];
3453 i
.types
[xchg1
] = temp_type
;
3454 temp_op
= i
.op
[xchg2
];
3455 i
.op
[xchg2
] = i
.op
[xchg1
];
3456 i
.op
[xchg1
] = temp_op
;
3457 temp_reloc
= i
.reloc
[xchg2
];
3458 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3459 i
.reloc
[xchg1
] = temp_reloc
;
3463 swap_operands (void)
3469 swap_2_operands (1, i
.operands
- 2);
3472 swap_2_operands (0, i
.operands
- 1);
3478 if (i
.mem_operands
== 2)
3480 const seg_entry
*temp_seg
;
3481 temp_seg
= i
.seg
[0];
3482 i
.seg
[0] = i
.seg
[1];
3483 i
.seg
[1] = temp_seg
;
3487 /* Try to ensure constant immediates are represented in the smallest
3492 char guess_suffix
= 0;
3496 guess_suffix
= i
.suffix
;
3497 else if (i
.reg_operands
)
3499 /* Figure out a suffix from the last register operand specified.
3500 We can't do this properly yet, ie. excluding InOutPortReg,
3501 but the following works for instructions with immediates.
3502 In any case, we can't set i.suffix yet. */
3503 for (op
= i
.operands
; --op
>= 0;)
3504 if (i
.types
[op
].bitfield
.reg8
)
3506 guess_suffix
= BYTE_MNEM_SUFFIX
;
3509 else if (i
.types
[op
].bitfield
.reg16
)
3511 guess_suffix
= WORD_MNEM_SUFFIX
;
3514 else if (i
.types
[op
].bitfield
.reg32
)
3516 guess_suffix
= LONG_MNEM_SUFFIX
;
3519 else if (i
.types
[op
].bitfield
.reg64
)
3521 guess_suffix
= QWORD_MNEM_SUFFIX
;
3525 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3526 guess_suffix
= WORD_MNEM_SUFFIX
;
3528 for (op
= i
.operands
; --op
>= 0;)
3529 if (operand_type_check (i
.types
[op
], imm
))
3531 switch (i
.op
[op
].imms
->X_op
)
3534 /* If a suffix is given, this operand may be shortened. */
3535 switch (guess_suffix
)
3537 case LONG_MNEM_SUFFIX
:
3538 i
.types
[op
].bitfield
.imm32
= 1;
3539 i
.types
[op
].bitfield
.imm64
= 1;
3541 case WORD_MNEM_SUFFIX
:
3542 i
.types
[op
].bitfield
.imm16
= 1;
3543 i
.types
[op
].bitfield
.imm32
= 1;
3544 i
.types
[op
].bitfield
.imm32s
= 1;
3545 i
.types
[op
].bitfield
.imm64
= 1;
3547 case BYTE_MNEM_SUFFIX
:
3548 i
.types
[op
].bitfield
.imm8
= 1;
3549 i
.types
[op
].bitfield
.imm8s
= 1;
3550 i
.types
[op
].bitfield
.imm16
= 1;
3551 i
.types
[op
].bitfield
.imm32
= 1;
3552 i
.types
[op
].bitfield
.imm32s
= 1;
3553 i
.types
[op
].bitfield
.imm64
= 1;
3557 /* If this operand is at most 16 bits, convert it
3558 to a signed 16 bit number before trying to see
3559 whether it will fit in an even smaller size.
3560 This allows a 16-bit operand such as $0xffe0 to
3561 be recognised as within Imm8S range. */
3562 if ((i
.types
[op
].bitfield
.imm16
)
3563 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3565 i
.op
[op
].imms
->X_add_number
=
3566 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3568 if ((i
.types
[op
].bitfield
.imm32
)
3569 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3572 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3573 ^ ((offsetT
) 1 << 31))
3574 - ((offsetT
) 1 << 31));
3577 = operand_type_or (i
.types
[op
],
3578 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3580 /* We must avoid matching of Imm32 templates when 64bit
3581 only immediate is available. */
3582 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3583 i
.types
[op
].bitfield
.imm32
= 0;
3590 /* Symbols and expressions. */
3592 /* Convert symbolic operand to proper sizes for matching, but don't
3593 prevent matching a set of insns that only supports sizes other
3594 than those matching the insn suffix. */
3596 i386_operand_type mask
, allowed
;
3597 const insn_template
*t
;
3599 operand_type_set (&mask
, 0);
3600 operand_type_set (&allowed
, 0);
3602 for (t
= current_templates
->start
;
3603 t
< current_templates
->end
;
3605 allowed
= operand_type_or (allowed
,
3606 t
->operand_types
[op
]);
3607 switch (guess_suffix
)
3609 case QWORD_MNEM_SUFFIX
:
3610 mask
.bitfield
.imm64
= 1;
3611 mask
.bitfield
.imm32s
= 1;
3613 case LONG_MNEM_SUFFIX
:
3614 mask
.bitfield
.imm32
= 1;
3616 case WORD_MNEM_SUFFIX
:
3617 mask
.bitfield
.imm16
= 1;
3619 case BYTE_MNEM_SUFFIX
:
3620 mask
.bitfield
.imm8
= 1;
3625 allowed
= operand_type_and (mask
, allowed
);
3626 if (!operand_type_all_zero (&allowed
))
3627 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3634 /* Try to use the smallest displacement type too. */
3636 optimize_disp (void)
3640 for (op
= i
.operands
; --op
>= 0;)
3641 if (operand_type_check (i
.types
[op
], disp
))
3643 if (i
.op
[op
].disps
->X_op
== O_constant
)
3645 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3647 if (i
.types
[op
].bitfield
.disp16
3648 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3650 /* If this operand is at most 16 bits, convert
3651 to a signed 16 bit number and don't use 64bit
3653 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3654 i
.types
[op
].bitfield
.disp64
= 0;
3656 if (i
.types
[op
].bitfield
.disp32
3657 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3659 /* If this operand is at most 32 bits, convert
3660 to a signed 32 bit number and don't use 64bit
3662 op_disp
&= (((offsetT
) 2 << 31) - 1);
3663 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3664 i
.types
[op
].bitfield
.disp64
= 0;
3666 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3668 i
.types
[op
].bitfield
.disp8
= 0;
3669 i
.types
[op
].bitfield
.disp16
= 0;
3670 i
.types
[op
].bitfield
.disp32
= 0;
3671 i
.types
[op
].bitfield
.disp32s
= 0;
3672 i
.types
[op
].bitfield
.disp64
= 0;
3676 else if (flag_code
== CODE_64BIT
)
3678 if (fits_in_signed_long (op_disp
))
3680 i
.types
[op
].bitfield
.disp64
= 0;
3681 i
.types
[op
].bitfield
.disp32s
= 1;
3683 if (i
.prefix
[ADDR_PREFIX
]
3684 && fits_in_unsigned_long (op_disp
))
3685 i
.types
[op
].bitfield
.disp32
= 1;
3687 if ((i
.types
[op
].bitfield
.disp32
3688 || i
.types
[op
].bitfield
.disp32s
3689 || i
.types
[op
].bitfield
.disp16
)
3690 && fits_in_signed_byte (op_disp
))
3691 i
.types
[op
].bitfield
.disp8
= 1;
3693 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3694 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3696 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3697 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3698 i
.types
[op
].bitfield
.disp8
= 0;
3699 i
.types
[op
].bitfield
.disp16
= 0;
3700 i
.types
[op
].bitfield
.disp32
= 0;
3701 i
.types
[op
].bitfield
.disp32s
= 0;
3702 i
.types
[op
].bitfield
.disp64
= 0;
3705 /* We only support 64bit displacement on constants. */
3706 i
.types
[op
].bitfield
.disp64
= 0;
3710 static const insn_template
*
3711 match_template (void)
3713 /* Points to template once we've found it. */
3714 const insn_template
*t
;
3715 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3716 i386_operand_type overlap4
;
3717 unsigned int found_reverse_match
;
3718 i386_opcode_modifier suffix_check
;
3719 i386_operand_type operand_types
[MAX_OPERANDS
];
3720 int addr_prefix_disp
;
3722 unsigned int found_cpu_match
;
3723 unsigned int check_register
;
3725 #if MAX_OPERANDS != 5
3726 # error "MAX_OPERANDS must be 5."
3729 found_reverse_match
= 0;
3730 addr_prefix_disp
= -1;
3732 memset (&suffix_check
, 0, sizeof (suffix_check
));
3733 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3734 suffix_check
.no_bsuf
= 1;
3735 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3736 suffix_check
.no_wsuf
= 1;
3737 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3738 suffix_check
.no_ssuf
= 1;
3739 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3740 suffix_check
.no_lsuf
= 1;
3741 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3742 suffix_check
.no_qsuf
= 1;
3743 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3744 suffix_check
.no_ldsuf
= 1;
3746 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3748 addr_prefix_disp
= -1;
3750 /* Must have right number of operands. */
3751 if (i
.operands
!= t
->operands
)
3754 /* Check processor support. */
3755 found_cpu_match
= (cpu_flags_match (t
)
3756 == CPU_FLAGS_PERFECT_MATCH
);
3757 if (!found_cpu_match
)
3760 /* Check old gcc support. */
3761 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3764 /* Check AT&T mnemonic. */
3765 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3768 /* Check AT&T syntax Intel syntax. */
3769 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3770 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3773 /* Check the suffix, except for some instructions in intel mode. */
3774 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3775 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3776 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3777 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3778 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3779 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3780 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3783 if (!operand_size_match (t
))
3786 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3787 operand_types
[j
] = t
->operand_types
[j
];
3789 /* In general, don't allow 64-bit operands in 32-bit mode. */
3790 if (i
.suffix
== QWORD_MNEM_SUFFIX
3791 && flag_code
!= CODE_64BIT
3793 ? (!t
->opcode_modifier
.ignoresize
3794 && !intel_float_operand (t
->name
))
3795 : intel_float_operand (t
->name
) != 2)
3796 && ((!operand_types
[0].bitfield
.regmmx
3797 && !operand_types
[0].bitfield
.regxmm
3798 && !operand_types
[0].bitfield
.regymm
)
3799 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3800 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3801 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3802 && (t
->base_opcode
!= 0x0fc7
3803 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3806 /* In general, don't allow 32-bit operands on pre-386. */
3807 else if (i
.suffix
== LONG_MNEM_SUFFIX
3808 && !cpu_arch_flags
.bitfield
.cpui386
3810 ? (!t
->opcode_modifier
.ignoresize
3811 && !intel_float_operand (t
->name
))
3812 : intel_float_operand (t
->name
) != 2)
3813 && ((!operand_types
[0].bitfield
.regmmx
3814 && !operand_types
[0].bitfield
.regxmm
)
3815 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3816 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3819 /* Do not verify operands when there are none. */
3823 /* We've found a match; break out of loop. */
3827 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3828 into Disp32/Disp16/Disp32 operand. */
3829 if (i
.prefix
[ADDR_PREFIX
] != 0)
3831 /* There should be only one Disp operand. */
3835 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3837 if (operand_types
[j
].bitfield
.disp16
)
3839 addr_prefix_disp
= j
;
3840 operand_types
[j
].bitfield
.disp32
= 1;
3841 operand_types
[j
].bitfield
.disp16
= 0;
3847 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3849 if (operand_types
[j
].bitfield
.disp32
)
3851 addr_prefix_disp
= j
;
3852 operand_types
[j
].bitfield
.disp32
= 0;
3853 operand_types
[j
].bitfield
.disp16
= 1;
3859 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3861 if (operand_types
[j
].bitfield
.disp64
)
3863 addr_prefix_disp
= j
;
3864 operand_types
[j
].bitfield
.disp64
= 0;
3865 operand_types
[j
].bitfield
.disp32
= 1;
3873 /* We check register size only if size of operands can be
3874 encoded the canonical way. */
3875 check_register
= t
->opcode_modifier
.w
;
3876 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3877 switch (t
->operands
)
3880 if (!operand_type_match (overlap0
, i
.types
[0]))
3884 /* xchg %eax, %eax is a special case. It is an aliase for nop
3885 only in 32bit mode and we can use opcode 0x90. In 64bit
3886 mode, we can't use 0x90 for xchg %eax, %eax since it should
3887 zero-extend %eax to %rax. */
3888 if (flag_code
== CODE_64BIT
3889 && t
->base_opcode
== 0x90
3890 && operand_type_equal (&i
.types
[0], &acc32
)
3891 && operand_type_equal (&i
.types
[1], &acc32
))
3895 /* If we swap operand in encoding, we either match
3896 the next one or reverse direction of operands. */
3897 if (t
->opcode_modifier
.s
)
3899 else if (t
->opcode_modifier
.d
)
3904 /* If we swap operand in encoding, we match the next one. */
3905 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3909 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3910 if (!operand_type_match (overlap0
, i
.types
[0])
3911 || !operand_type_match (overlap1
, i
.types
[1])
3913 && !operand_type_register_match (overlap0
, i
.types
[0],
3915 overlap1
, i
.types
[1],
3918 /* Check if other direction is valid ... */
3919 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3923 /* Try reversing direction of operands. */
3924 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3925 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3926 if (!operand_type_match (overlap0
, i
.types
[0])
3927 || !operand_type_match (overlap1
, i
.types
[1])
3929 && !operand_type_register_match (overlap0
,
3936 /* Does not match either direction. */
3939 /* found_reverse_match holds which of D or FloatDR
3941 if (t
->opcode_modifier
.d
)
3942 found_reverse_match
= Opcode_D
;
3943 else if (t
->opcode_modifier
.floatd
)
3944 found_reverse_match
= Opcode_FloatD
;
3946 found_reverse_match
= 0;
3947 if (t
->opcode_modifier
.floatr
)
3948 found_reverse_match
|= Opcode_FloatR
;
3952 /* Found a forward 2 operand match here. */
3953 switch (t
->operands
)
3956 overlap4
= operand_type_and (i
.types
[4],
3959 overlap3
= operand_type_and (i
.types
[3],
3962 overlap2
= operand_type_and (i
.types
[2],
3967 switch (t
->operands
)
3970 if (!operand_type_match (overlap4
, i
.types
[4])
3971 || !operand_type_register_match (overlap3
,
3979 if (!operand_type_match (overlap3
, i
.types
[3])
3981 && !operand_type_register_match (overlap2
,
3989 /* Here we make use of the fact that there are no
3990 reverse match 3 operand instructions, and all 3
3991 operand instructions only need to be checked for
3992 register consistency between operands 2 and 3. */
3993 if (!operand_type_match (overlap2
, i
.types
[2])
3995 && !operand_type_register_match (overlap1
,
4005 /* Found either forward/reverse 2, 3 or 4 operand match here:
4006 slip through to break. */
4008 if (!found_cpu_match
)
4010 found_reverse_match
= 0;
4014 /* We've found a match; break out of loop. */
4018 if (t
== current_templates
->end
)
4020 /* We found no match. */
4022 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4023 current_templates
->start
->name
);
4025 as_bad (_("suffix or operands invalid for `%s'"),
4026 current_templates
->start
->name
);
4030 if (!quiet_warnings
)
4033 && (i
.types
[0].bitfield
.jumpabsolute
4034 != operand_types
[0].bitfield
.jumpabsolute
))
4036 as_warn (_("indirect %s without `*'"), t
->name
);
4039 if (t
->opcode_modifier
.isprefix
4040 && t
->opcode_modifier
.ignoresize
)
4042 /* Warn them that a data or address size prefix doesn't
4043 affect assembly of the next line of code. */
4044 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4048 /* Copy the template we found. */
4051 if (addr_prefix_disp
!= -1)
4052 i
.tm
.operand_types
[addr_prefix_disp
]
4053 = operand_types
[addr_prefix_disp
];
4055 if (found_reverse_match
)
4057 /* If we found a reverse match we must alter the opcode
4058 direction bit. found_reverse_match holds bits to change
4059 (different for int & float insns). */
4061 i
.tm
.base_opcode
^= found_reverse_match
;
4063 i
.tm
.operand_types
[0] = operand_types
[1];
4064 i
.tm
.operand_types
[1] = operand_types
[0];
4073 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4074 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4076 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4078 as_bad (_("`%s' operand %d must use `%ses' segment"),
4084 /* There's only ever one segment override allowed per instruction.
4085 This instruction possibly has a legal segment override on the
4086 second operand, so copy the segment to where non-string
4087 instructions store it, allowing common code. */
4088 i
.seg
[0] = i
.seg
[1];
4090 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4092 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4094 as_bad (_("`%s' operand %d must use `%ses' segment"),
4105 process_suffix (void)
4107 /* If matched instruction specifies an explicit instruction mnemonic
4109 if (i
.tm
.opcode_modifier
.size16
)
4110 i
.suffix
= WORD_MNEM_SUFFIX
;
4111 else if (i
.tm
.opcode_modifier
.size32
)
4112 i
.suffix
= LONG_MNEM_SUFFIX
;
4113 else if (i
.tm
.opcode_modifier
.size64
)
4114 i
.suffix
= QWORD_MNEM_SUFFIX
;
4115 else if (i
.reg_operands
)
4117 /* If there's no instruction mnemonic suffix we try to invent one
4118 based on register operands. */
4121 /* We take i.suffix from the last register operand specified,
4122 Destination register type is more significant than source
4123 register type. crc32 in SSE4.2 prefers source register
4125 if (i
.tm
.base_opcode
== 0xf20f38f1)
4127 if (i
.types
[0].bitfield
.reg16
)
4128 i
.suffix
= WORD_MNEM_SUFFIX
;
4129 else if (i
.types
[0].bitfield
.reg32
)
4130 i
.suffix
= LONG_MNEM_SUFFIX
;
4131 else if (i
.types
[0].bitfield
.reg64
)
4132 i
.suffix
= QWORD_MNEM_SUFFIX
;
4134 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4136 if (i
.types
[0].bitfield
.reg8
)
4137 i
.suffix
= BYTE_MNEM_SUFFIX
;
4144 if (i
.tm
.base_opcode
== 0xf20f38f1
4145 || i
.tm
.base_opcode
== 0xf20f38f0)
4147 /* We have to know the operand size for crc32. */
4148 as_bad (_("ambiguous memory operand size for `%s`"),
4153 for (op
= i
.operands
; --op
>= 0;)
4154 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4156 if (i
.types
[op
].bitfield
.reg8
)
4158 i
.suffix
= BYTE_MNEM_SUFFIX
;
4161 else if (i
.types
[op
].bitfield
.reg16
)
4163 i
.suffix
= WORD_MNEM_SUFFIX
;
4166 else if (i
.types
[op
].bitfield
.reg32
)
4168 i
.suffix
= LONG_MNEM_SUFFIX
;
4171 else if (i
.types
[op
].bitfield
.reg64
)
4173 i
.suffix
= QWORD_MNEM_SUFFIX
;
4179 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4182 && i
.tm
.opcode_modifier
.ignoresize
4183 && i
.tm
.opcode_modifier
.no_bsuf
)
4185 else if (!check_byte_reg ())
4188 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4191 && i
.tm
.opcode_modifier
.ignoresize
4192 && i
.tm
.opcode_modifier
.no_lsuf
)
4194 else if (!check_long_reg ())
4197 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4200 && i
.tm
.opcode_modifier
.ignoresize
4201 && i
.tm
.opcode_modifier
.no_qsuf
)
4203 else if (!check_qword_reg ())
4206 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4209 && i
.tm
.opcode_modifier
.ignoresize
4210 && i
.tm
.opcode_modifier
.no_wsuf
)
4212 else if (!check_word_reg ())
4215 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4216 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4218 /* Skip if the instruction has x/y suffix. match_template
4219 should check if it is a valid suffix. */
4221 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4222 /* Do nothing if the instruction is going to ignore the prefix. */
4227 else if (i
.tm
.opcode_modifier
.defaultsize
4229 /* exclude fldenv/frstor/fsave/fstenv */
4230 && i
.tm
.opcode_modifier
.no_ssuf
)
4232 i
.suffix
= stackop_size
;
4234 else if (intel_syntax
4236 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4237 || i
.tm
.opcode_modifier
.jumpbyte
4238 || i
.tm
.opcode_modifier
.jumpintersegment
4239 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4240 && i
.tm
.extension_opcode
<= 3)))
4245 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4247 i
.suffix
= QWORD_MNEM_SUFFIX
;
4251 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4252 i
.suffix
= LONG_MNEM_SUFFIX
;
4255 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4256 i
.suffix
= WORD_MNEM_SUFFIX
;
4265 if (i
.tm
.opcode_modifier
.w
)
4267 as_bad (_("no instruction mnemonic suffix given and "
4268 "no register operands; can't size instruction"));
4274 unsigned int suffixes
;
4276 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4277 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4279 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4281 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4283 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4285 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4288 /* There are more than suffix matches. */
4289 if (i
.tm
.opcode_modifier
.w
4290 || ((suffixes
& (suffixes
- 1))
4291 && !i
.tm
.opcode_modifier
.defaultsize
4292 && !i
.tm
.opcode_modifier
.ignoresize
))
4294 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4300 /* Change the opcode based on the operand size given by i.suffix;
4301 We don't need to change things for byte insns. */
4304 && i
.suffix
!= BYTE_MNEM_SUFFIX
4305 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4306 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4308 /* It's not a byte, select word/dword operation. */
4309 if (i
.tm
.opcode_modifier
.w
)
4311 if (i
.tm
.opcode_modifier
.shortform
)
4312 i
.tm
.base_opcode
|= 8;
4314 i
.tm
.base_opcode
|= 1;
4317 /* Now select between word & dword operations via the operand
4318 size prefix, except for instructions that will ignore this
4320 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4322 /* The address size override prefix changes the size of the
4324 if ((flag_code
== CODE_32BIT
4325 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4326 || (flag_code
!= CODE_32BIT
4327 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4328 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4331 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4332 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4333 && !i
.tm
.opcode_modifier
.ignoresize
4334 && !i
.tm
.opcode_modifier
.floatmf
4335 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4336 || (flag_code
== CODE_64BIT
4337 && i
.tm
.opcode_modifier
.jumpbyte
)))
4339 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4341 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4342 prefix
= ADDR_PREFIX_OPCODE
;
4344 if (!add_prefix (prefix
))
4348 /* Set mode64 for an operand. */
4349 if (i
.suffix
== QWORD_MNEM_SUFFIX
4350 && flag_code
== CODE_64BIT
4351 && !i
.tm
.opcode_modifier
.norex64
)
4353 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4354 need rex64. cmpxchg8b is also a special case. */
4355 if (! (i
.operands
== 2
4356 && i
.tm
.base_opcode
== 0x90
4357 && i
.tm
.extension_opcode
== None
4358 && operand_type_equal (&i
.types
[0], &acc64
)
4359 && operand_type_equal (&i
.types
[1], &acc64
))
4360 && ! (i
.operands
== 1
4361 && i
.tm
.base_opcode
== 0xfc7
4362 && i
.tm
.extension_opcode
== 1
4363 && !operand_type_check (i
.types
[0], reg
)
4364 && operand_type_check (i
.types
[0], anymem
)))
4368 /* Size floating point instruction. */
4369 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4370 if (i
.tm
.opcode_modifier
.floatmf
)
4371 i
.tm
.base_opcode
^= 4;
4378 check_byte_reg (void)
4382 for (op
= i
.operands
; --op
>= 0;)
4384 /* If this is an eight bit register, it's OK. If it's the 16 or
4385 32 bit version of an eight bit register, we will just use the
4386 low portion, and that's OK too. */
4387 if (i
.types
[op
].bitfield
.reg8
)
4390 /* crc32 doesn't generate this warning. */
4391 if (i
.tm
.base_opcode
== 0xf20f38f0)
4394 if ((i
.types
[op
].bitfield
.reg16
4395 || i
.types
[op
].bitfield
.reg32
4396 || i
.types
[op
].bitfield
.reg64
)
4397 && i
.op
[op
].regs
->reg_num
< 4)
4399 /* Prohibit these changes in the 64bit mode, since the
4400 lowering is more complicated. */
4401 if (flag_code
== CODE_64BIT
4402 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4404 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4405 register_prefix
, i
.op
[op
].regs
->reg_name
,
4409 #if REGISTER_WARNINGS
4411 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4412 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4414 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4415 ? REGNAM_AL
- REGNAM_AX
4416 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4418 i
.op
[op
].regs
->reg_name
,
4423 /* Any other register is bad. */
4424 if (i
.types
[op
].bitfield
.reg16
4425 || i
.types
[op
].bitfield
.reg32
4426 || i
.types
[op
].bitfield
.reg64
4427 || i
.types
[op
].bitfield
.regmmx
4428 || i
.types
[op
].bitfield
.regxmm
4429 || i
.types
[op
].bitfield
.regymm
4430 || i
.types
[op
].bitfield
.sreg2
4431 || i
.types
[op
].bitfield
.sreg3
4432 || i
.types
[op
].bitfield
.control
4433 || i
.types
[op
].bitfield
.debug
4434 || i
.types
[op
].bitfield
.test
4435 || i
.types
[op
].bitfield
.floatreg
4436 || i
.types
[op
].bitfield
.floatacc
)
4438 as_bad (_("`%s%s' not allowed with `%s%c'"),
4440 i
.op
[op
].regs
->reg_name
,
4450 check_long_reg (void)
4454 for (op
= i
.operands
; --op
>= 0;)
4455 /* Reject eight bit registers, except where the template requires
4456 them. (eg. movzb) */
4457 if (i
.types
[op
].bitfield
.reg8
4458 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4459 || i
.tm
.operand_types
[op
].bitfield
.reg32
4460 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4462 as_bad (_("`%s%s' not allowed with `%s%c'"),
4464 i
.op
[op
].regs
->reg_name
,
4469 /* Warn if the e prefix on a general reg is missing. */
4470 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4471 && i
.types
[op
].bitfield
.reg16
4472 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4473 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4475 /* Prohibit these changes in the 64bit mode, since the
4476 lowering is more complicated. */
4477 if (flag_code
== CODE_64BIT
)
4479 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4480 register_prefix
, i
.op
[op
].regs
->reg_name
,
4484 #if REGISTER_WARNINGS
4486 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4488 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4490 i
.op
[op
].regs
->reg_name
,
4494 /* Warn if the r prefix on a general reg is missing. */
4495 else if (i
.types
[op
].bitfield
.reg64
4496 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4497 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4500 && i
.tm
.opcode_modifier
.toqword
4501 && !i
.types
[0].bitfield
.regxmm
)
4503 /* Convert to QWORD. We want REX byte. */
4504 i
.suffix
= QWORD_MNEM_SUFFIX
;
4508 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4509 register_prefix
, i
.op
[op
].regs
->reg_name
,
4518 check_qword_reg (void)
4522 for (op
= i
.operands
; --op
>= 0; )
4523 /* Reject eight bit registers, except where the template requires
4524 them. (eg. movzb) */
4525 if (i
.types
[op
].bitfield
.reg8
4526 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4527 || i
.tm
.operand_types
[op
].bitfield
.reg32
4528 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4530 as_bad (_("`%s%s' not allowed with `%s%c'"),
4532 i
.op
[op
].regs
->reg_name
,
4537 /* Warn if the e prefix on a general reg is missing. */
4538 else if ((i
.types
[op
].bitfield
.reg16
4539 || i
.types
[op
].bitfield
.reg32
)
4540 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4541 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4543 /* Prohibit these changes in the 64bit mode, since the
4544 lowering is more complicated. */
4546 && i
.tm
.opcode_modifier
.todword
4547 && !i
.types
[0].bitfield
.regxmm
)
4549 /* Convert to DWORD. We don't want REX byte. */
4550 i
.suffix
= LONG_MNEM_SUFFIX
;
4554 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4555 register_prefix
, i
.op
[op
].regs
->reg_name
,
4564 check_word_reg (void)
4567 for (op
= i
.operands
; --op
>= 0;)
4568 /* Reject eight bit registers, except where the template requires
4569 them. (eg. movzb) */
4570 if (i
.types
[op
].bitfield
.reg8
4571 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4572 || i
.tm
.operand_types
[op
].bitfield
.reg32
4573 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4575 as_bad (_("`%s%s' not allowed with `%s%c'"),
4577 i
.op
[op
].regs
->reg_name
,
4582 /* Warn if the e prefix on a general reg is present. */
4583 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4584 && i
.types
[op
].bitfield
.reg32
4585 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4586 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4588 /* Prohibit these changes in the 64bit mode, since the
4589 lowering is more complicated. */
4590 if (flag_code
== CODE_64BIT
)
4592 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4593 register_prefix
, i
.op
[op
].regs
->reg_name
,
4598 #if REGISTER_WARNINGS
4599 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4601 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4603 i
.op
[op
].regs
->reg_name
,
4611 update_imm (unsigned int j
)
4613 i386_operand_type overlap
= i
.types
[j
];
4614 if ((overlap
.bitfield
.imm8
4615 || overlap
.bitfield
.imm8s
4616 || overlap
.bitfield
.imm16
4617 || overlap
.bitfield
.imm32
4618 || overlap
.bitfield
.imm32s
4619 || overlap
.bitfield
.imm64
)
4620 && !operand_type_equal (&overlap
, &imm8
)
4621 && !operand_type_equal (&overlap
, &imm8s
)
4622 && !operand_type_equal (&overlap
, &imm16
)
4623 && !operand_type_equal (&overlap
, &imm32
)
4624 && !operand_type_equal (&overlap
, &imm32s
)
4625 && !operand_type_equal (&overlap
, &imm64
))
4629 i386_operand_type temp
;
4631 operand_type_set (&temp
, 0);
4632 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4634 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4635 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4637 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4638 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4639 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4641 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4642 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4645 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4648 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4649 || operand_type_equal (&overlap
, &imm16_32
)
4650 || operand_type_equal (&overlap
, &imm16_32s
))
4652 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4657 if (!operand_type_equal (&overlap
, &imm8
)
4658 && !operand_type_equal (&overlap
, &imm8s
)
4659 && !operand_type_equal (&overlap
, &imm16
)
4660 && !operand_type_equal (&overlap
, &imm32
)
4661 && !operand_type_equal (&overlap
, &imm32s
)
4662 && !operand_type_equal (&overlap
, &imm64
))
4664 as_bad (_("no instruction mnemonic suffix given; "
4665 "can't determine immediate size"));
4669 i
.types
[j
] = overlap
;
4679 /* Update the first 2 immediate operands. */
4680 n
= i
.operands
> 2 ? 2 : i
.operands
;
4683 for (j
= 0; j
< n
; j
++)
4684 if (update_imm (j
) == 0)
4687 /* The 3rd operand can't be immediate operand. */
4688 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4695 bad_implicit_operand (int xmm
)
4697 const char *ireg
= xmm
? "xmm0" : "ymm0";
4700 as_bad (_("the last operand of `%s' must be `%s%s'"),
4701 i
.tm
.name
, register_prefix
, ireg
);
4703 as_bad (_("the first operand of `%s' must be `%s%s'"),
4704 i
.tm
.name
, register_prefix
, ireg
);
4709 process_operands (void)
4711 /* Default segment register this instruction will use for memory
4712 accesses. 0 means unknown. This is only for optimizing out
4713 unnecessary segment overrides. */
4714 const seg_entry
*default_seg
= 0;
4716 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4718 unsigned int dupl
= i
.operands
;
4719 unsigned int dest
= dupl
- 1;
4722 /* The destination must be an xmm register. */
4723 gas_assert (i
.reg_operands
4724 && MAX_OPERANDS
> dupl
4725 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4727 if (i
.tm
.opcode_modifier
.firstxmm0
)
4729 /* The first operand is implicit and must be xmm0. */
4730 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4731 if (i
.op
[0].regs
->reg_num
!= 0)
4732 return bad_implicit_operand (1);
4734 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4736 /* Keep xmm0 for instructions with VEX prefix and 3
4742 /* We remove the first xmm0 and keep the number of
4743 operands unchanged, which in fact duplicates the
4745 for (j
= 1; j
< i
.operands
; j
++)
4747 i
.op
[j
- 1] = i
.op
[j
];
4748 i
.types
[j
- 1] = i
.types
[j
];
4749 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4753 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4755 gas_assert ((MAX_OPERANDS
- 1) > dupl
4756 && (i
.tm
.opcode_modifier
.vexsources
4759 /* Add the implicit xmm0 for instructions with VEX prefix
4761 for (j
= i
.operands
; j
> 0; j
--)
4763 i
.op
[j
] = i
.op
[j
- 1];
4764 i
.types
[j
] = i
.types
[j
- 1];
4765 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4768 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4769 i
.types
[0] = regxmm
;
4770 i
.tm
.operand_types
[0] = regxmm
;
4773 i
.reg_operands
+= 2;
4778 i
.op
[dupl
] = i
.op
[dest
];
4779 i
.types
[dupl
] = i
.types
[dest
];
4780 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4789 i
.op
[dupl
] = i
.op
[dest
];
4790 i
.types
[dupl
] = i
.types
[dest
];
4791 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4794 if (i
.tm
.opcode_modifier
.immext
)
4797 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4801 /* The first operand is implicit and must be xmm0/ymm0. */
4802 gas_assert (i
.reg_operands
4803 && (operand_type_equal (&i
.types
[0], ®xmm
)
4804 || operand_type_equal (&i
.types
[0], ®ymm
)));
4805 if (i
.op
[0].regs
->reg_num
!= 0)
4806 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4808 for (j
= 1; j
< i
.operands
; j
++)
4810 i
.op
[j
- 1] = i
.op
[j
];
4811 i
.types
[j
- 1] = i
.types
[j
];
4813 /* We need to adjust fields in i.tm since they are used by
4814 build_modrm_byte. */
4815 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4822 else if (i
.tm
.opcode_modifier
.regkludge
)
4824 /* The imul $imm, %reg instruction is converted into
4825 imul $imm, %reg, %reg, and the clr %reg instruction
4826 is converted into xor %reg, %reg. */
4828 unsigned int first_reg_op
;
4830 if (operand_type_check (i
.types
[0], reg
))
4834 /* Pretend we saw the extra register operand. */
4835 gas_assert (i
.reg_operands
== 1
4836 && i
.op
[first_reg_op
+ 1].regs
== 0);
4837 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4838 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4843 if (i
.tm
.opcode_modifier
.shortform
)
4845 if (i
.types
[0].bitfield
.sreg2
4846 || i
.types
[0].bitfield
.sreg3
)
4848 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4849 && i
.op
[0].regs
->reg_num
== 1)
4851 as_bad (_("you can't `pop %scs'"), register_prefix
);
4854 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4855 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4860 /* The register or float register operand is in operand
4864 if (i
.types
[0].bitfield
.floatreg
4865 || operand_type_check (i
.types
[0], reg
))
4869 /* Register goes in low 3 bits of opcode. */
4870 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4871 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4873 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4875 /* Warn about some common errors, but press on regardless.
4876 The first case can be generated by gcc (<= 2.8.1). */
4877 if (i
.operands
== 2)
4879 /* Reversed arguments on faddp, fsubp, etc. */
4880 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4881 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4882 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4886 /* Extraneous `l' suffix on fp insn. */
4887 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4888 register_prefix
, i
.op
[0].regs
->reg_name
);
4893 else if (i
.tm
.opcode_modifier
.modrm
)
4895 /* The opcode is completed (modulo i.tm.extension_opcode which
4896 must be put into the modrm byte). Now, we make the modrm and
4897 index base bytes based on all the info we've collected. */
4899 default_seg
= build_modrm_byte ();
4901 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4905 else if (i
.tm
.opcode_modifier
.isstring
)
4907 /* For the string instructions that allow a segment override
4908 on one of their operands, the default segment is ds. */
4912 if (i
.tm
.base_opcode
== 0x8d /* lea */
4915 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4917 /* If a segment was explicitly specified, and the specified segment
4918 is not the default, use an opcode prefix to select it. If we
4919 never figured out what the default segment is, then default_seg
4920 will be zero at this point, and the specified segment prefix will
4922 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4924 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4930 static const seg_entry
*
4931 build_modrm_byte (void)
4933 const seg_entry
*default_seg
= 0;
4934 unsigned int source
, dest
;
4937 /* The first operand of instructions with VEX prefix and 3 sources
4938 must be VEX_Imm4. */
4939 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
4942 unsigned int nds
, reg_slot
;
4945 if (i
.tm
.opcode_modifier
.veximmext
4946 && i
.tm
.opcode_modifier
.immext
)
4948 dest
= i
.operands
- 2;
4949 gas_assert (dest
== 3);
4952 dest
= i
.operands
- 1;
4955 /* This instruction must have 4 register operands
4956 or 3 register operands plus 1 memory operand.
4957 It must have VexNDS and VexImmExt. */
4958 gas_assert ((i
.reg_operands
== 4
4959 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4960 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
4961 && i
.tm
.opcode_modifier
.veximmext
4962 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4963 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4965 /* Generate an 8bit immediate operand to encode the register
4967 exp
= &im_expressions
[i
.imm_operands
++];
4968 i
.op
[i
.operands
].imms
= exp
;
4969 i
.types
[i
.operands
] = imm8
;
4971 /* If VexW1 is set, the first operand is the source and
4972 the second operand is encoded in the immediate operand. */
4973 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
4983 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg_slot
], ®xmm
)
4984 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
4986 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4987 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4989 exp
->X_op
= O_constant
;
4991 = ((i
.op
[reg_slot
].regs
->reg_num
4992 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4993 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4998 /* i.reg_operands MUST be the number of real register operands;
4999 implicit registers do not count. If there are 3 register
5000 operands, it must be a instruction with VexNDS. For a
5001 instruction with VexNDD, the destination register is encoded
5002 in VEX prefix. If there are 4 register operands, it must be
5003 a instruction with VEX prefix and 3 sources. */
5004 if (i
.mem_operands
== 0
5005 && ((i
.reg_operands
== 2
5006 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5007 || (i
.reg_operands
== 3
5008 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5009 || (i
.reg_operands
== 4 && vex_3_sources
)))
5017 /* When there are 3 operands, one of them may be immediate,
5018 which may be the first or the last operand. Otherwise,
5019 the first operand must be shift count register (cl) or it
5020 is an instruction with VexNDS. */
5021 gas_assert (i
.imm_operands
== 1
5022 || (i
.imm_operands
== 0
5023 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5024 || i
.types
[0].bitfield
.shiftcount
)));
5025 if (operand_type_check (i
.types
[0], imm
)
5026 || i
.types
[0].bitfield
.shiftcount
)
5032 /* When there are 4 operands, the first two must be 8bit
5033 immediate operands. The source operand will be the 3rd
5036 For instructions with VexNDS, if the first operand
5037 an imm8, the source operand is the 2nd one. If the last
5038 operand is imm8, the source operand is the first one. */
5039 gas_assert ((i
.imm_operands
== 2
5040 && i
.types
[0].bitfield
.imm8
5041 && i
.types
[1].bitfield
.imm8
)
5042 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5043 && i
.imm_operands
== 1
5044 && (i
.types
[0].bitfield
.imm8
5045 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5046 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5048 if (i
.types
[0].bitfield
.imm8
)
5066 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5068 /* For instructions with VexNDS, the register-only
5069 source operand must be XMM or YMM register. It is
5070 encoded in VEX prefix. We need to clear RegMem bit
5071 before calling operand_type_equal. */
5072 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5073 op
.bitfield
.regmem
= 0;
5074 if ((dest
+ 1) >= i
.operands
5075 || (!operand_type_equal (&op
, ®xmm
)
5076 && !operand_type_equal (&op
, ®ymm
)))
5078 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5084 /* One of the register operands will be encoded in the i.tm.reg
5085 field, the other in the combined i.tm.mode and i.tm.regmem
5086 fields. If no form of this instruction supports a memory
5087 destination operand, then we assume the source operand may
5088 sometimes be a memory operand and so we need to store the
5089 destination in the i.rm.reg field. */
5090 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5091 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5093 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5094 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5095 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5097 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5102 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5103 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5104 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5106 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5109 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5111 if (!i
.types
[0].bitfield
.control
5112 && !i
.types
[1].bitfield
.control
)
5114 i
.rex
&= ~(REX_R
| REX_B
);
5115 add_prefix (LOCK_PREFIX_OPCODE
);
5119 { /* If it's not 2 reg operands... */
5124 unsigned int fake_zero_displacement
= 0;
5127 for (op
= 0; op
< i
.operands
; op
++)
5128 if (operand_type_check (i
.types
[op
], anymem
))
5130 gas_assert (op
< i
.operands
);
5134 if (i
.base_reg
== 0)
5137 if (!i
.disp_operands
)
5138 fake_zero_displacement
= 1;
5139 if (i
.index_reg
== 0)
5141 /* Operand is just <disp> */
5142 if (flag_code
== CODE_64BIT
)
5144 /* 64bit mode overwrites the 32bit absolute
5145 addressing by RIP relative addressing and
5146 absolute addressing is encoded by one of the
5147 redundant SIB forms. */
5148 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5149 i
.sib
.base
= NO_BASE_REGISTER
;
5150 i
.sib
.index
= NO_INDEX_REGISTER
;
5151 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5152 ? disp32s
: disp32
);
5154 else if ((flag_code
== CODE_16BIT
)
5155 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5157 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5158 i
.types
[op
] = disp16
;
5162 i
.rm
.regmem
= NO_BASE_REGISTER
;
5163 i
.types
[op
] = disp32
;
5166 else /* !i.base_reg && i.index_reg */
5168 if (i
.index_reg
->reg_num
== RegEiz
5169 || i
.index_reg
->reg_num
== RegRiz
)
5170 i
.sib
.index
= NO_INDEX_REGISTER
;
5172 i
.sib
.index
= i
.index_reg
->reg_num
;
5173 i
.sib
.base
= NO_BASE_REGISTER
;
5174 i
.sib
.scale
= i
.log2_scale_factor
;
5175 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5176 i
.types
[op
].bitfield
.disp8
= 0;
5177 i
.types
[op
].bitfield
.disp16
= 0;
5178 i
.types
[op
].bitfield
.disp64
= 0;
5179 if (flag_code
!= CODE_64BIT
)
5181 /* Must be 32 bit */
5182 i
.types
[op
].bitfield
.disp32
= 1;
5183 i
.types
[op
].bitfield
.disp32s
= 0;
5187 i
.types
[op
].bitfield
.disp32
= 0;
5188 i
.types
[op
].bitfield
.disp32s
= 1;
5190 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5194 /* RIP addressing for 64bit mode. */
5195 else if (i
.base_reg
->reg_num
== RegRip
||
5196 i
.base_reg
->reg_num
== RegEip
)
5198 i
.rm
.regmem
= NO_BASE_REGISTER
;
5199 i
.types
[op
].bitfield
.disp8
= 0;
5200 i
.types
[op
].bitfield
.disp16
= 0;
5201 i
.types
[op
].bitfield
.disp32
= 0;
5202 i
.types
[op
].bitfield
.disp32s
= 1;
5203 i
.types
[op
].bitfield
.disp64
= 0;
5204 i
.flags
[op
] |= Operand_PCrel
;
5205 if (! i
.disp_operands
)
5206 fake_zero_displacement
= 1;
5208 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5210 switch (i
.base_reg
->reg_num
)
5213 if (i
.index_reg
== 0)
5215 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5216 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5220 if (i
.index_reg
== 0)
5223 if (operand_type_check (i
.types
[op
], disp
) == 0)
5225 /* fake (%bp) into 0(%bp) */
5226 i
.types
[op
].bitfield
.disp8
= 1;
5227 fake_zero_displacement
= 1;
5230 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5231 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5233 default: /* (%si) -> 4 or (%di) -> 5 */
5234 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5236 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5238 else /* i.base_reg and 32/64 bit mode */
5240 if (flag_code
== CODE_64BIT
5241 && operand_type_check (i
.types
[op
], disp
))
5243 i386_operand_type temp
;
5244 operand_type_set (&temp
, 0);
5245 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5247 if (i
.prefix
[ADDR_PREFIX
] == 0)
5248 i
.types
[op
].bitfield
.disp32s
= 1;
5250 i
.types
[op
].bitfield
.disp32
= 1;
5253 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5254 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5256 i
.sib
.base
= i
.base_reg
->reg_num
;
5257 /* x86-64 ignores REX prefix bit here to avoid decoder
5259 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5262 if (i
.disp_operands
== 0)
5264 fake_zero_displacement
= 1;
5265 i
.types
[op
].bitfield
.disp8
= 1;
5268 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5272 i
.sib
.scale
= i
.log2_scale_factor
;
5273 if (i
.index_reg
== 0)
5275 /* <disp>(%esp) becomes two byte modrm with no index
5276 register. We've already stored the code for esp
5277 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5278 Any base register besides %esp will not use the
5279 extra modrm byte. */
5280 i
.sib
.index
= NO_INDEX_REGISTER
;
5284 if (i
.index_reg
->reg_num
== RegEiz
5285 || i
.index_reg
->reg_num
== RegRiz
)
5286 i
.sib
.index
= NO_INDEX_REGISTER
;
5288 i
.sib
.index
= i
.index_reg
->reg_num
;
5289 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5290 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5295 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5296 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5299 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5302 if (fake_zero_displacement
)
5304 /* Fakes a zero displacement assuming that i.types[op]
5305 holds the correct displacement size. */
5308 gas_assert (i
.op
[op
].disps
== 0);
5309 exp
= &disp_expressions
[i
.disp_operands
++];
5310 i
.op
[op
].disps
= exp
;
5311 exp
->X_op
= O_constant
;
5312 exp
->X_add_number
= 0;
5313 exp
->X_add_symbol
= (symbolS
*) 0;
5314 exp
->X_op_symbol
= (symbolS
*) 0;
5322 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5324 if (operand_type_check (i
.types
[0], imm
))
5325 i
.vex
.register_specifier
= NULL
;
5328 /* VEX.vvvv encodes one of the sources when the first
5329 operand is not an immediate. */
5330 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5331 i
.vex
.register_specifier
= i
.op
[0].regs
;
5333 i
.vex
.register_specifier
= i
.op
[1].regs
;
5336 /* Destination is a XMM register encoded in the ModRM.reg
5338 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5339 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5342 /* ModRM.rm and VEX.B encodes the other source. */
5343 if (!i
.mem_operands
)
5347 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5348 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5350 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5352 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5356 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5358 i
.vex
.register_specifier
= i
.op
[2].regs
;
5359 if (!i
.mem_operands
)
5362 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5363 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5367 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5368 (if any) based on i.tm.extension_opcode. Again, we must be
5369 careful to make sure that segment/control/debug/test/MMX
5370 registers are coded into the i.rm.reg field. */
5371 else if (i
.reg_operands
)
5374 unsigned int vex_reg
= ~0;
5376 for (op
= 0; op
< i
.operands
; op
++)
5377 if (i
.types
[op
].bitfield
.reg8
5378 || i
.types
[op
].bitfield
.reg16
5379 || i
.types
[op
].bitfield
.reg32
5380 || i
.types
[op
].bitfield
.reg64
5381 || i
.types
[op
].bitfield
.regmmx
5382 || i
.types
[op
].bitfield
.regxmm
5383 || i
.types
[op
].bitfield
.regymm
5384 || i
.types
[op
].bitfield
.sreg2
5385 || i
.types
[op
].bitfield
.sreg3
5386 || i
.types
[op
].bitfield
.control
5387 || i
.types
[op
].bitfield
.debug
5388 || i
.types
[op
].bitfield
.test
)
5393 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5395 /* For instructions with VexNDS, the register-only
5396 source operand is encoded in VEX prefix. */
5397 gas_assert (mem
!= (unsigned int) ~0);
5402 gas_assert (op
< i
.operands
);
5407 gas_assert (vex_reg
< i
.operands
);
5410 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5412 /* For instructions with VexNDD, there should be
5413 no memory operand and the register destination
5414 is encoded in VEX prefix. */
5415 gas_assert (i
.mem_operands
== 0
5416 && (op
+ 2) == i
.operands
);
5420 gas_assert (op
< i
.operands
);
5422 if (vex_reg
!= (unsigned int) ~0)
5424 gas_assert (i
.reg_operands
== 2);
5426 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5428 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5432 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5435 /* Don't set OP operand twice. */
5438 /* If there is an extension opcode to put here, the
5439 register number must be put into the regmem field. */
5440 if (i
.tm
.extension_opcode
!= None
)
5442 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5443 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5448 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5449 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5454 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5455 must set it to 3 to indicate this is a register operand
5456 in the regmem field. */
5457 if (!i
.mem_operands
)
5461 /* Fill in i.rm.reg field with extension opcode (if any). */
5462 if (i
.tm
.extension_opcode
!= None
)
5463 i
.rm
.reg
= i
.tm
.extension_opcode
;
5469 output_branch (void)
5474 relax_substateT subtype
;
5479 if (flag_code
== CODE_16BIT
)
5483 if (i
.prefix
[DATA_PREFIX
] != 0)
5489 /* Pentium4 branch hints. */
5490 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5491 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5496 if (i
.prefix
[REX_PREFIX
] != 0)
5502 if (i
.prefixes
!= 0 && !intel_syntax
)
5503 as_warn (_("skipping prefixes on this instruction"));
5505 /* It's always a symbol; End frag & setup for relax.
5506 Make sure there is enough room in this frag for the largest
5507 instruction we may generate in md_convert_frag. This is 2
5508 bytes for the opcode and room for the prefix and largest
5510 frag_grow (prefix
+ 2 + 4);
5511 /* Prefix and 1 opcode byte go in fr_fix. */
5512 p
= frag_more (prefix
+ 1);
5513 if (i
.prefix
[DATA_PREFIX
] != 0)
5514 *p
++ = DATA_PREFIX_OPCODE
;
5515 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5516 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5517 *p
++ = i
.prefix
[SEG_PREFIX
];
5518 if (i
.prefix
[REX_PREFIX
] != 0)
5519 *p
++ = i
.prefix
[REX_PREFIX
];
5520 *p
= i
.tm
.base_opcode
;
5522 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5523 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5524 else if (cpu_arch_flags
.bitfield
.cpui386
)
5525 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5527 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5530 sym
= i
.op
[0].disps
->X_add_symbol
;
5531 off
= i
.op
[0].disps
->X_add_number
;
5533 if (i
.op
[0].disps
->X_op
!= O_constant
5534 && i
.op
[0].disps
->X_op
!= O_symbol
)
5536 /* Handle complex expressions. */
5537 sym
= make_expr_symbol (i
.op
[0].disps
);
5541 /* 1 possible extra opcode + 4 byte displacement go in var part.
5542 Pass reloc in fr_var. */
5543 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5553 if (i
.tm
.opcode_modifier
.jumpbyte
)
5555 /* This is a loop or jecxz type instruction. */
5557 if (i
.prefix
[ADDR_PREFIX
] != 0)
5559 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5562 /* Pentium4 branch hints. */
5563 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5564 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5566 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5575 if (flag_code
== CODE_16BIT
)
5578 if (i
.prefix
[DATA_PREFIX
] != 0)
5580 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5590 if (i
.prefix
[REX_PREFIX
] != 0)
5592 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5596 if (i
.prefixes
!= 0 && !intel_syntax
)
5597 as_warn (_("skipping prefixes on this instruction"));
5599 p
= frag_more (1 + size
);
5600 *p
++ = i
.tm
.base_opcode
;
5602 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5603 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5605 /* All jumps handled here are signed, but don't use a signed limit
5606 check for 32 and 16 bit jumps as we want to allow wrap around at
5607 4G and 64k respectively. */
5609 fixP
->fx_signed
= 1;
5613 output_interseg_jump (void)
5621 if (flag_code
== CODE_16BIT
)
5625 if (i
.prefix
[DATA_PREFIX
] != 0)
5631 if (i
.prefix
[REX_PREFIX
] != 0)
5641 if (i
.prefixes
!= 0 && !intel_syntax
)
5642 as_warn (_("skipping prefixes on this instruction"));
5644 /* 1 opcode; 2 segment; offset */
5645 p
= frag_more (prefix
+ 1 + 2 + size
);
5647 if (i
.prefix
[DATA_PREFIX
] != 0)
5648 *p
++ = DATA_PREFIX_OPCODE
;
5650 if (i
.prefix
[REX_PREFIX
] != 0)
5651 *p
++ = i
.prefix
[REX_PREFIX
];
5653 *p
++ = i
.tm
.base_opcode
;
5654 if (i
.op
[1].imms
->X_op
== O_constant
)
5656 offsetT n
= i
.op
[1].imms
->X_add_number
;
5659 && !fits_in_unsigned_word (n
)
5660 && !fits_in_signed_word (n
))
5662 as_bad (_("16-bit jump out of range"));
5665 md_number_to_chars (p
, n
, size
);
5668 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5669 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5670 if (i
.op
[0].imms
->X_op
!= O_constant
)
5671 as_bad (_("can't handle non absolute segment in `%s'"),
5673 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5679 fragS
*insn_start_frag
;
5680 offsetT insn_start_off
;
5682 /* Tie dwarf2 debug info to the address at the start of the insn.
5683 We can't do this after the insn has been output as the current
5684 frag may have been closed off. eg. by frag_var. */
5685 dwarf2_emit_insn (0);
5687 insn_start_frag
= frag_now
;
5688 insn_start_off
= frag_now_fix ();
5691 if (i
.tm
.opcode_modifier
.jump
)
5693 else if (i
.tm
.opcode_modifier
.jumpbyte
5694 || i
.tm
.opcode_modifier
.jumpdword
)
5696 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5697 output_interseg_jump ();
5700 /* Output normal instructions here. */
5704 unsigned int prefix
;
5706 /* Since the VEX prefix contains the implicit prefix, we don't
5707 need the explicit prefix. */
5708 if (!i
.tm
.opcode_modifier
.vex
)
5710 switch (i
.tm
.opcode_length
)
5713 if (i
.tm
.base_opcode
& 0xff000000)
5715 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5720 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5722 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5723 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5726 if (prefix
!= REPE_PREFIX_OPCODE
5727 || (i
.prefix
[REP_PREFIX
]
5728 != REPE_PREFIX_OPCODE
))
5729 add_prefix (prefix
);
5732 add_prefix (prefix
);
5741 /* The prefix bytes. */
5742 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5744 FRAG_APPEND_1_CHAR (*q
);
5747 if (i
.tm
.opcode_modifier
.vex
)
5749 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5754 /* REX byte is encoded in VEX prefix. */
5758 FRAG_APPEND_1_CHAR (*q
);
5761 /* There should be no other prefixes for instructions
5766 /* Now the VEX prefix. */
5767 p
= frag_more (i
.vex
.length
);
5768 for (j
= 0; j
< i
.vex
.length
; j
++)
5769 p
[j
] = i
.vex
.bytes
[j
];
5772 /* Now the opcode; be careful about word order here! */
5773 if (i
.tm
.opcode_length
== 1)
5775 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5779 switch (i
.tm
.opcode_length
)
5783 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5793 /* Put out high byte first: can't use md_number_to_chars! */
5794 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5795 *p
= i
.tm
.base_opcode
& 0xff;
5798 /* Now the modrm byte and sib byte (if present). */
5799 if (i
.tm
.opcode_modifier
.modrm
)
5801 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5804 /* If i.rm.regmem == ESP (4)
5805 && i.rm.mode != (Register mode)
5807 ==> need second modrm byte. */
5808 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5810 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5811 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5813 | i
.sib
.scale
<< 6));
5816 if (i
.disp_operands
)
5817 output_disp (insn_start_frag
, insn_start_off
);
5820 output_imm (insn_start_frag
, insn_start_off
);
5826 pi ("" /*line*/, &i
);
5828 #endif /* DEBUG386 */
5831 /* Return the size of the displacement operand N. */
5834 disp_size (unsigned int n
)
5837 if (i
.types
[n
].bitfield
.disp64
)
5839 else if (i
.types
[n
].bitfield
.disp8
)
5841 else if (i
.types
[n
].bitfield
.disp16
)
5846 /* Return the size of the immediate operand N. */
5849 imm_size (unsigned int n
)
5852 if (i
.types
[n
].bitfield
.imm64
)
5854 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5856 else if (i
.types
[n
].bitfield
.imm16
)
5862 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5867 for (n
= 0; n
< i
.operands
; n
++)
5869 if (operand_type_check (i
.types
[n
], disp
))
5871 if (i
.op
[n
].disps
->X_op
== O_constant
)
5873 int size
= disp_size (n
);
5876 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5878 p
= frag_more (size
);
5879 md_number_to_chars (p
, val
, size
);
5883 enum bfd_reloc_code_real reloc_type
;
5884 int size
= disp_size (n
);
5885 int sign
= i
.types
[n
].bitfield
.disp32s
;
5886 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5888 /* We can't have 8 bit displacement here. */
5889 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5891 /* The PC relative address is computed relative
5892 to the instruction boundary, so in case immediate
5893 fields follows, we need to adjust the value. */
5894 if (pcrel
&& i
.imm_operands
)
5899 for (n1
= 0; n1
< i
.operands
; n1
++)
5900 if (operand_type_check (i
.types
[n1
], imm
))
5902 /* Only one immediate is allowed for PC
5903 relative address. */
5904 gas_assert (sz
== 0);
5906 i
.op
[n
].disps
->X_add_number
-= sz
;
5908 /* We should find the immediate. */
5909 gas_assert (sz
!= 0);
5912 p
= frag_more (size
);
5913 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5915 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5916 && (((reloc_type
== BFD_RELOC_32
5917 || reloc_type
== BFD_RELOC_X86_64_32S
5918 || (reloc_type
== BFD_RELOC_64
5920 && (i
.op
[n
].disps
->X_op
== O_symbol
5921 || (i
.op
[n
].disps
->X_op
== O_add
5922 && ((symbol_get_value_expression
5923 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5925 || reloc_type
== BFD_RELOC_32_PCREL
))
5929 if (insn_start_frag
== frag_now
)
5930 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5935 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5936 for (fr
= insn_start_frag
->fr_next
;
5937 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5939 add
+= p
- frag_now
->fr_literal
;
5944 reloc_type
= BFD_RELOC_386_GOTPC
;
5945 i
.op
[n
].imms
->X_add_number
+= add
;
5947 else if (reloc_type
== BFD_RELOC_64
)
5948 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5950 /* Don't do the adjustment for x86-64, as there
5951 the pcrel addressing is relative to the _next_
5952 insn, and that is taken care of in other code. */
5953 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5955 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5956 i
.op
[n
].disps
, pcrel
, reloc_type
);
5963 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5968 for (n
= 0; n
< i
.operands
; n
++)
5970 if (operand_type_check (i
.types
[n
], imm
))
5972 if (i
.op
[n
].imms
->X_op
== O_constant
)
5974 int size
= imm_size (n
);
5977 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5979 p
= frag_more (size
);
5980 md_number_to_chars (p
, val
, size
);
5984 /* Not absolute_section.
5985 Need a 32-bit fixup (don't support 8bit
5986 non-absolute imms). Try to support other
5988 enum bfd_reloc_code_real reloc_type
;
5989 int size
= imm_size (n
);
5992 if (i
.types
[n
].bitfield
.imm32s
5993 && (i
.suffix
== QWORD_MNEM_SUFFIX
5994 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5999 p
= frag_more (size
);
6000 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6002 /* This is tough to explain. We end up with this one if we
6003 * have operands that look like
6004 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6005 * obtain the absolute address of the GOT, and it is strongly
6006 * preferable from a performance point of view to avoid using
6007 * a runtime relocation for this. The actual sequence of
6008 * instructions often look something like:
6013 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6015 * The call and pop essentially return the absolute address
6016 * of the label .L66 and store it in %ebx. The linker itself
6017 * will ultimately change the first operand of the addl so
6018 * that %ebx points to the GOT, but to keep things simple, the
6019 * .o file must have this operand set so that it generates not
6020 * the absolute address of .L66, but the absolute address of
6021 * itself. This allows the linker itself simply treat a GOTPC
6022 * relocation as asking for a pcrel offset to the GOT to be
6023 * added in, and the addend of the relocation is stored in the
6024 * operand field for the instruction itself.
6026 * Our job here is to fix the operand so that it would add
6027 * the correct offset so that %ebx would point to itself. The
6028 * thing that is tricky is that .-.L66 will point to the
6029 * beginning of the instruction, so we need to further modify
6030 * the operand so that it will point to itself. There are
6031 * other cases where you have something like:
6033 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6035 * and here no correction would be required. Internally in
6036 * the assembler we treat operands of this form as not being
6037 * pcrel since the '.' is explicitly mentioned, and I wonder
6038 * whether it would simplify matters to do it this way. Who
6039 * knows. In earlier versions of the PIC patches, the
6040 * pcrel_adjust field was used to store the correction, but
6041 * since the expression is not pcrel, I felt it would be
6042 * confusing to do it this way. */
6044 if ((reloc_type
== BFD_RELOC_32
6045 || reloc_type
== BFD_RELOC_X86_64_32S
6046 || reloc_type
== BFD_RELOC_64
)
6048 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6049 && (i
.op
[n
].imms
->X_op
== O_symbol
6050 || (i
.op
[n
].imms
->X_op
== O_add
6051 && ((symbol_get_value_expression
6052 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6057 if (insn_start_frag
== frag_now
)
6058 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6063 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6064 for (fr
= insn_start_frag
->fr_next
;
6065 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6067 add
+= p
- frag_now
->fr_literal
;
6071 reloc_type
= BFD_RELOC_386_GOTPC
;
6073 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6075 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6076 i
.op
[n
].imms
->X_add_number
+= add
;
6078 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6079 i
.op
[n
].imms
, 0, reloc_type
);
6085 /* x86_cons_fix_new is called via the expression parsing code when a
6086 reloc is needed. We use this hook to get the correct .got reloc. */
6087 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6088 static int cons_sign
= -1;
6091 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6094 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6096 got_reloc
= NO_RELOC
;
6099 if (exp
->X_op
== O_secrel
)
6101 exp
->X_op
= O_symbol
;
6102 r
= BFD_RELOC_32_SECREL
;
6106 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6109 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6110 # define lex_got(reloc, adjust, types) NULL
6112 /* Parse operands of the form
6113 <symbol>@GOTOFF+<nnn>
6114 and similar .plt or .got references.
6116 If we find one, set up the correct relocation in RELOC and copy the
6117 input string, minus the `@GOTOFF' into a malloc'd buffer for
6118 parsing by the calling routine. Return this buffer, and if ADJUST
6119 is non-null set it to the length of the string we removed from the
6120 input line. Otherwise return NULL. */
6122 lex_got (enum bfd_reloc_code_real
*rel
,
6124 i386_operand_type
*types
)
6126 /* Some of the relocations depend on the size of what field is to
6127 be relocated. But in our callers i386_immediate and i386_displacement
6128 we don't yet know the operand size (this will be set by insn
6129 matching). Hence we record the word32 relocation here,
6130 and adjust the reloc according to the real size in reloc(). */
6131 static const struct {
6133 const enum bfd_reloc_code_real rel
[2];
6134 const i386_operand_type types64
;
6136 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6137 BFD_RELOC_X86_64_PLTOFF64
},
6138 OPERAND_TYPE_IMM64
},
6139 { "PLT", { BFD_RELOC_386_PLT32
,
6140 BFD_RELOC_X86_64_PLT32
},
6141 OPERAND_TYPE_IMM32_32S_DISP32
},
6142 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6143 BFD_RELOC_X86_64_GOTPLT64
},
6144 OPERAND_TYPE_IMM64_DISP64
},
6145 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6146 BFD_RELOC_X86_64_GOTOFF64
},
6147 OPERAND_TYPE_IMM64_DISP64
},
6148 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6149 BFD_RELOC_X86_64_GOTPCREL
},
6150 OPERAND_TYPE_IMM32_32S_DISP32
},
6151 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6152 BFD_RELOC_X86_64_TLSGD
},
6153 OPERAND_TYPE_IMM32_32S_DISP32
},
6154 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6155 _dummy_first_bfd_reloc_code_real
},
6156 OPERAND_TYPE_NONE
},
6157 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6158 BFD_RELOC_X86_64_TLSLD
},
6159 OPERAND_TYPE_IMM32_32S_DISP32
},
6160 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6161 BFD_RELOC_X86_64_GOTTPOFF
},
6162 OPERAND_TYPE_IMM32_32S_DISP32
},
6163 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6164 BFD_RELOC_X86_64_TPOFF32
},
6165 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6166 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6167 _dummy_first_bfd_reloc_code_real
},
6168 OPERAND_TYPE_NONE
},
6169 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6170 BFD_RELOC_X86_64_DTPOFF32
},
6172 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6173 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6174 _dummy_first_bfd_reloc_code_real
},
6175 OPERAND_TYPE_NONE
},
6176 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6177 _dummy_first_bfd_reloc_code_real
},
6178 OPERAND_TYPE_NONE
},
6179 { "GOT", { BFD_RELOC_386_GOT32
,
6180 BFD_RELOC_X86_64_GOT32
},
6181 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6182 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6183 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6184 OPERAND_TYPE_IMM32_32S_DISP32
},
6185 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6186 BFD_RELOC_X86_64_TLSDESC_CALL
},
6187 OPERAND_TYPE_IMM32_32S_DISP32
},
6195 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6196 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6199 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6203 len
= strlen (gotrel
[j
].str
);
6204 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6206 if (gotrel
[j
].rel
[object_64bit
] != 0)
6209 char *tmpbuf
, *past_reloc
;
6211 *rel
= gotrel
[j
].rel
[object_64bit
];
6217 if (flag_code
!= CODE_64BIT
)
6219 types
->bitfield
.imm32
= 1;
6220 types
->bitfield
.disp32
= 1;
6223 *types
= gotrel
[j
].types64
;
6226 if (GOT_symbol
== NULL
)
6227 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6229 /* The length of the first part of our input line. */
6230 first
= cp
- input_line_pointer
;
6232 /* The second part goes from after the reloc token until
6233 (and including) an end_of_line char or comma. */
6234 past_reloc
= cp
+ 1 + len
;
6236 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6238 second
= cp
+ 1 - past_reloc
;
6240 /* Allocate and copy string. The trailing NUL shouldn't
6241 be necessary, but be safe. */
6242 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6243 memcpy (tmpbuf
, input_line_pointer
, first
);
6244 if (second
!= 0 && *past_reloc
!= ' ')
6245 /* Replace the relocation token with ' ', so that
6246 errors like foo@GOTOFF1 will be detected. */
6247 tmpbuf
[first
++] = ' ';
6248 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6249 tmpbuf
[first
+ second
] = '\0';
6253 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6254 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6259 /* Might be a symbol version string. Don't as_bad here. */
6264 x86_cons (expressionS
*exp
, int size
)
6266 intel_syntax
= -intel_syntax
;
6268 if (size
== 4 || (object_64bit
&& size
== 8))
6270 /* Handle @GOTOFF and the like in an expression. */
6272 char *gotfree_input_line
;
6275 save
= input_line_pointer
;
6276 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6277 if (gotfree_input_line
)
6278 input_line_pointer
= gotfree_input_line
;
6282 if (gotfree_input_line
)
6284 /* expression () has merrily parsed up to the end of line,
6285 or a comma - in the wrong buffer. Transfer how far
6286 input_line_pointer has moved to the right buffer. */
6287 input_line_pointer
= (save
6288 + (input_line_pointer
- gotfree_input_line
)
6290 free (gotfree_input_line
);
6291 if (exp
->X_op
== O_constant
6292 || exp
->X_op
== O_absent
6293 || exp
->X_op
== O_illegal
6294 || exp
->X_op
== O_register
6295 || exp
->X_op
== O_big
)
6297 char c
= *input_line_pointer
;
6298 *input_line_pointer
= 0;
6299 as_bad (_("missing or invalid expression `%s'"), save
);
6300 *input_line_pointer
= c
;
6307 intel_syntax
= -intel_syntax
;
6310 i386_intel_simplify (exp
);
6315 signed_cons (int size
)
6317 if (flag_code
== CODE_64BIT
)
6325 pe_directive_secrel (dummy
)
6326 int dummy ATTRIBUTE_UNUSED
;
6333 if (exp
.X_op
== O_symbol
)
6334 exp
.X_op
= O_secrel
;
6336 emit_expr (&exp
, 4);
6338 while (*input_line_pointer
++ == ',');
6340 input_line_pointer
--;
6341 demand_empty_rest_of_line ();
6346 i386_immediate (char *imm_start
)
6348 char *save_input_line_pointer
;
6349 char *gotfree_input_line
;
6352 i386_operand_type types
;
6354 operand_type_set (&types
, ~0);
6356 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6358 as_bad (_("at most %d immediate operands are allowed"),
6359 MAX_IMMEDIATE_OPERANDS
);
6363 exp
= &im_expressions
[i
.imm_operands
++];
6364 i
.op
[this_operand
].imms
= exp
;
6366 if (is_space_char (*imm_start
))
6369 save_input_line_pointer
= input_line_pointer
;
6370 input_line_pointer
= imm_start
;
6372 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6373 if (gotfree_input_line
)
6374 input_line_pointer
= gotfree_input_line
;
6376 exp_seg
= expression (exp
);
6379 if (*input_line_pointer
)
6380 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6382 input_line_pointer
= save_input_line_pointer
;
6383 if (gotfree_input_line
)
6385 free (gotfree_input_line
);
6387 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6388 exp
->X_op
= O_illegal
;
6391 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6395 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6396 i386_operand_type types
, const char *imm_start
)
6398 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6401 as_bad (_("missing or invalid immediate expression `%s'"),
6405 else if (exp
->X_op
== O_constant
)
6407 /* Size it properly later. */
6408 i
.types
[this_operand
].bitfield
.imm64
= 1;
6409 /* If BFD64, sign extend val. */
6410 if (!use_rela_relocations
6411 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6413 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6415 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6416 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6417 && exp_seg
!= absolute_section
6418 && exp_seg
!= text_section
6419 && exp_seg
!= data_section
6420 && exp_seg
!= bss_section
6421 && exp_seg
!= undefined_section
6422 && !bfd_is_com_section (exp_seg
))
6424 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6428 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6431 as_bad (_("illegal immediate register operand %s"), imm_start
);
6436 /* This is an address. The size of the address will be
6437 determined later, depending on destination register,
6438 suffix, or the default for the section. */
6439 i
.types
[this_operand
].bitfield
.imm8
= 1;
6440 i
.types
[this_operand
].bitfield
.imm16
= 1;
6441 i
.types
[this_operand
].bitfield
.imm32
= 1;
6442 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6443 i
.types
[this_operand
].bitfield
.imm64
= 1;
6444 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6452 i386_scale (char *scale
)
6455 char *save
= input_line_pointer
;
6457 input_line_pointer
= scale
;
6458 val
= get_absolute_expression ();
6463 i
.log2_scale_factor
= 0;
6466 i
.log2_scale_factor
= 1;
6469 i
.log2_scale_factor
= 2;
6472 i
.log2_scale_factor
= 3;
6476 char sep
= *input_line_pointer
;
6478 *input_line_pointer
= '\0';
6479 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6481 *input_line_pointer
= sep
;
6482 input_line_pointer
= save
;
6486 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6488 as_warn (_("scale factor of %d without an index register"),
6489 1 << i
.log2_scale_factor
);
6490 i
.log2_scale_factor
= 0;
6492 scale
= input_line_pointer
;
6493 input_line_pointer
= save
;
6498 i386_displacement (char *disp_start
, char *disp_end
)
6502 char *save_input_line_pointer
;
6503 char *gotfree_input_line
;
6505 i386_operand_type bigdisp
, types
= anydisp
;
6508 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6510 as_bad (_("at most %d displacement operands are allowed"),
6511 MAX_MEMORY_OPERANDS
);
6515 operand_type_set (&bigdisp
, 0);
6516 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6517 || (!current_templates
->start
->opcode_modifier
.jump
6518 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6520 bigdisp
.bitfield
.disp32
= 1;
6521 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6522 if (flag_code
== CODE_64BIT
)
6526 bigdisp
.bitfield
.disp32s
= 1;
6527 bigdisp
.bitfield
.disp64
= 1;
6530 else if ((flag_code
== CODE_16BIT
) ^ override
)
6532 bigdisp
.bitfield
.disp32
= 0;
6533 bigdisp
.bitfield
.disp16
= 1;
6538 /* For PC-relative branches, the width of the displacement
6539 is dependent upon data size, not address size. */
6540 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6541 if (flag_code
== CODE_64BIT
)
6543 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6544 bigdisp
.bitfield
.disp16
= 1;
6547 bigdisp
.bitfield
.disp32
= 1;
6548 bigdisp
.bitfield
.disp32s
= 1;
6554 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6556 : LONG_MNEM_SUFFIX
));
6557 bigdisp
.bitfield
.disp32
= 1;
6558 if ((flag_code
== CODE_16BIT
) ^ override
)
6560 bigdisp
.bitfield
.disp32
= 0;
6561 bigdisp
.bitfield
.disp16
= 1;
6565 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6568 exp
= &disp_expressions
[i
.disp_operands
];
6569 i
.op
[this_operand
].disps
= exp
;
6571 save_input_line_pointer
= input_line_pointer
;
6572 input_line_pointer
= disp_start
;
6573 END_STRING_AND_SAVE (disp_end
);
6575 #ifndef GCC_ASM_O_HACK
6576 #define GCC_ASM_O_HACK 0
6579 END_STRING_AND_SAVE (disp_end
+ 1);
6580 if (i
.types
[this_operand
].bitfield
.baseIndex
6581 && displacement_string_end
[-1] == '+')
6583 /* This hack is to avoid a warning when using the "o"
6584 constraint within gcc asm statements.
6587 #define _set_tssldt_desc(n,addr,limit,type) \
6588 __asm__ __volatile__ ( \
6590 "movw %w1,2+%0\n\t" \
6592 "movb %b1,4+%0\n\t" \
6593 "movb %4,5+%0\n\t" \
6594 "movb $0,6+%0\n\t" \
6595 "movb %h1,7+%0\n\t" \
6597 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6599 This works great except that the output assembler ends
6600 up looking a bit weird if it turns out that there is
6601 no offset. You end up producing code that looks like:
6614 So here we provide the missing zero. */
6616 *displacement_string_end
= '0';
6619 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6620 if (gotfree_input_line
)
6621 input_line_pointer
= gotfree_input_line
;
6623 exp_seg
= expression (exp
);
6626 if (*input_line_pointer
)
6627 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6629 RESTORE_END_STRING (disp_end
+ 1);
6631 input_line_pointer
= save_input_line_pointer
;
6632 if (gotfree_input_line
)
6634 free (gotfree_input_line
);
6636 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6637 exp
->X_op
= O_illegal
;
6640 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6642 RESTORE_END_STRING (disp_end
);
6648 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6649 i386_operand_type types
, const char *disp_start
)
6651 i386_operand_type bigdisp
;
6654 /* We do this to make sure that the section symbol is in
6655 the symbol table. We will ultimately change the relocation
6656 to be relative to the beginning of the section. */
6657 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6658 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6659 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6661 if (exp
->X_op
!= O_symbol
)
6664 if (S_IS_LOCAL (exp
->X_add_symbol
)
6665 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6666 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6667 exp
->X_op
= O_subtract
;
6668 exp
->X_op_symbol
= GOT_symbol
;
6669 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6670 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6671 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6672 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6674 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6677 else if (exp
->X_op
== O_absent
6678 || exp
->X_op
== O_illegal
6679 || exp
->X_op
== O_big
)
6682 as_bad (_("missing or invalid displacement expression `%s'"),
6687 else if (flag_code
== CODE_64BIT
6688 && !i
.prefix
[ADDR_PREFIX
]
6689 && exp
->X_op
== O_constant
)
6691 /* Since displacement is signed extended to 64bit, don't allow
6692 disp32 and turn off disp32s if they are out of range. */
6693 i
.types
[this_operand
].bitfield
.disp32
= 0;
6694 if (!fits_in_signed_long (exp
->X_add_number
))
6696 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6697 if (i
.types
[this_operand
].bitfield
.baseindex
)
6699 as_bad (_("0x%lx out range of signed 32bit displacement"),
6700 (long) exp
->X_add_number
);
6706 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6707 else if (exp
->X_op
!= O_constant
6708 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6709 && exp_seg
!= absolute_section
6710 && exp_seg
!= text_section
6711 && exp_seg
!= data_section
6712 && exp_seg
!= bss_section
6713 && exp_seg
!= undefined_section
6714 && !bfd_is_com_section (exp_seg
))
6716 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6721 /* Check if this is a displacement only operand. */
6722 bigdisp
= i
.types
[this_operand
];
6723 bigdisp
.bitfield
.disp8
= 0;
6724 bigdisp
.bitfield
.disp16
= 0;
6725 bigdisp
.bitfield
.disp32
= 0;
6726 bigdisp
.bitfield
.disp32s
= 0;
6727 bigdisp
.bitfield
.disp64
= 0;
6728 if (operand_type_all_zero (&bigdisp
))
6729 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6735 /* Make sure the memory operand we've been dealt is valid.
6736 Return 1 on success, 0 on a failure. */
6739 i386_index_check (const char *operand_string
)
6742 const char *kind
= "base/index";
6743 #if INFER_ADDR_PREFIX
6749 if (current_templates
->start
->opcode_modifier
.isstring
6750 && !current_templates
->start
->opcode_modifier
.immext
6751 && (current_templates
->end
[-1].opcode_modifier
.isstring
6754 /* Memory operands of string insns are special in that they only allow
6755 a single register (rDI, rSI, or rBX) as their memory address. */
6756 unsigned int expected
;
6758 kind
= "string address";
6760 if (current_templates
->start
->opcode_modifier
.w
)
6762 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6764 if (!type
.bitfield
.baseindex
6765 || ((!i
.mem_operands
!= !intel_syntax
)
6766 && current_templates
->end
[-1].operand_types
[1]
6767 .bitfield
.baseindex
))
6768 type
= current_templates
->end
[-1].operand_types
[1];
6769 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6772 expected
= 3 /* rBX */;
6774 if (!i
.base_reg
|| i
.index_reg
6775 || operand_type_check (i
.types
[this_operand
], disp
))
6777 else if (!(flag_code
== CODE_64BIT
6778 ? i
.prefix
[ADDR_PREFIX
]
6779 ? i
.base_reg
->reg_type
.bitfield
.reg32
6780 : i
.base_reg
->reg_type
.bitfield
.reg64
6781 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6782 ? i
.base_reg
->reg_type
.bitfield
.reg32
6783 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6785 else if (i
.base_reg
->reg_num
!= expected
)
6792 for (j
= 0; j
< i386_regtab_size
; ++j
)
6793 if ((flag_code
== CODE_64BIT
6794 ? i
.prefix
[ADDR_PREFIX
]
6795 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6796 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6797 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6798 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6799 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6800 && i386_regtab
[j
].reg_num
== expected
)
6802 gas_assert (j
< i386_regtab_size
);
6803 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6805 intel_syntax
? '[' : '(',
6807 i386_regtab
[j
].reg_name
,
6808 intel_syntax
? ']' : ')');
6812 else if (flag_code
== CODE_64BIT
)
6815 && ((i
.prefix
[ADDR_PREFIX
] == 0
6816 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6817 || (i
.prefix
[ADDR_PREFIX
]
6818 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6820 || i
.base_reg
->reg_num
!=
6821 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6823 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6824 || (i
.prefix
[ADDR_PREFIX
] == 0
6825 && i
.index_reg
->reg_num
!= RegRiz
6826 && !i
.index_reg
->reg_type
.bitfield
.reg64
6828 || (i
.prefix
[ADDR_PREFIX
]
6829 && i
.index_reg
->reg_num
!= RegEiz
6830 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6835 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6839 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6840 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6842 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6843 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6845 && i
.base_reg
->reg_num
< 6
6846 && i
.index_reg
->reg_num
>= 6
6847 && i
.log2_scale_factor
== 0))))
6854 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6856 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6857 && i
.index_reg
->reg_num
!= RegEiz
)
6858 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6864 #if INFER_ADDR_PREFIX
6865 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6867 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6869 /* Change the size of any displacement too. At most one of
6870 Disp16 or Disp32 is set.
6871 FIXME. There doesn't seem to be any real need for separate
6872 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6873 Removing them would probably clean up the code quite a lot. */
6874 if (flag_code
!= CODE_64BIT
6875 && (i
.types
[this_operand
].bitfield
.disp16
6876 || i
.types
[this_operand
].bitfield
.disp32
))
6877 i
.types
[this_operand
]
6878 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6883 as_bad (_("`%s' is not a valid %s expression"),
6888 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6890 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6891 ? flag_code
== CODE_32BIT
6900 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6904 i386_att_operand (char *operand_string
)
6908 char *op_string
= operand_string
;
6910 if (is_space_char (*op_string
))
6913 /* We check for an absolute prefix (differentiating,
6914 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6915 if (*op_string
== ABSOLUTE_PREFIX
)
6918 if (is_space_char (*op_string
))
6920 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6923 /* Check if operand is a register. */
6924 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6926 i386_operand_type temp
;
6928 /* Check for a segment override by searching for ':' after a
6929 segment register. */
6931 if (is_space_char (*op_string
))
6933 if (*op_string
== ':'
6934 && (r
->reg_type
.bitfield
.sreg2
6935 || r
->reg_type
.bitfield
.sreg3
))
6940 i
.seg
[i
.mem_operands
] = &es
;
6943 i
.seg
[i
.mem_operands
] = &cs
;
6946 i
.seg
[i
.mem_operands
] = &ss
;
6949 i
.seg
[i
.mem_operands
] = &ds
;
6952 i
.seg
[i
.mem_operands
] = &fs
;
6955 i
.seg
[i
.mem_operands
] = &gs
;
6959 /* Skip the ':' and whitespace. */
6961 if (is_space_char (*op_string
))
6964 if (!is_digit_char (*op_string
)
6965 && !is_identifier_char (*op_string
)
6966 && *op_string
!= '('
6967 && *op_string
!= ABSOLUTE_PREFIX
)
6969 as_bad (_("bad memory operand `%s'"), op_string
);
6972 /* Handle case of %es:*foo. */
6973 if (*op_string
== ABSOLUTE_PREFIX
)
6976 if (is_space_char (*op_string
))
6978 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6980 goto do_memory_reference
;
6984 as_bad (_("junk `%s' after register"), op_string
);
6988 temp
.bitfield
.baseindex
= 0;
6989 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6991 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6992 i
.op
[this_operand
].regs
= r
;
6995 else if (*op_string
== REGISTER_PREFIX
)
6997 as_bad (_("bad register name `%s'"), op_string
);
7000 else if (*op_string
== IMMEDIATE_PREFIX
)
7003 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7005 as_bad (_("immediate operand illegal with absolute jump"));
7008 if (!i386_immediate (op_string
))
7011 else if (is_digit_char (*op_string
)
7012 || is_identifier_char (*op_string
)
7013 || *op_string
== '(')
7015 /* This is a memory reference of some sort. */
7018 /* Start and end of displacement string expression (if found). */
7019 char *displacement_string_start
;
7020 char *displacement_string_end
;
7022 do_memory_reference
:
7023 if ((i
.mem_operands
== 1
7024 && !current_templates
->start
->opcode_modifier
.isstring
)
7025 || i
.mem_operands
== 2)
7027 as_bad (_("too many memory references for `%s'"),
7028 current_templates
->start
->name
);
7032 /* Check for base index form. We detect the base index form by
7033 looking for an ')' at the end of the operand, searching
7034 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7036 base_string
= op_string
+ strlen (op_string
);
7039 if (is_space_char (*base_string
))
7042 /* If we only have a displacement, set-up for it to be parsed later. */
7043 displacement_string_start
= op_string
;
7044 displacement_string_end
= base_string
+ 1;
7046 if (*base_string
== ')')
7049 unsigned int parens_balanced
= 1;
7050 /* We've already checked that the number of left & right ()'s are
7051 equal, so this loop will not be infinite. */
7055 if (*base_string
== ')')
7057 if (*base_string
== '(')
7060 while (parens_balanced
);
7062 temp_string
= base_string
;
7064 /* Skip past '(' and whitespace. */
7066 if (is_space_char (*base_string
))
7069 if (*base_string
== ','
7070 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7073 displacement_string_end
= temp_string
;
7075 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7079 base_string
= end_op
;
7080 if (is_space_char (*base_string
))
7084 /* There may be an index reg or scale factor here. */
7085 if (*base_string
== ',')
7088 if (is_space_char (*base_string
))
7091 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7094 base_string
= end_op
;
7095 if (is_space_char (*base_string
))
7097 if (*base_string
== ',')
7100 if (is_space_char (*base_string
))
7103 else if (*base_string
!= ')')
7105 as_bad (_("expecting `,' or `)' "
7106 "after index register in `%s'"),
7111 else if (*base_string
== REGISTER_PREFIX
)
7113 as_bad (_("bad register name `%s'"), base_string
);
7117 /* Check for scale factor. */
7118 if (*base_string
!= ')')
7120 char *end_scale
= i386_scale (base_string
);
7125 base_string
= end_scale
;
7126 if (is_space_char (*base_string
))
7128 if (*base_string
!= ')')
7130 as_bad (_("expecting `)' "
7131 "after scale factor in `%s'"),
7136 else if (!i
.index_reg
)
7138 as_bad (_("expecting index register or scale factor "
7139 "after `,'; got '%c'"),
7144 else if (*base_string
!= ')')
7146 as_bad (_("expecting `,' or `)' "
7147 "after base register in `%s'"),
7152 else if (*base_string
== REGISTER_PREFIX
)
7154 as_bad (_("bad register name `%s'"), base_string
);
7159 /* If there's an expression beginning the operand, parse it,
7160 assuming displacement_string_start and
7161 displacement_string_end are meaningful. */
7162 if (displacement_string_start
!= displacement_string_end
)
7164 if (!i386_displacement (displacement_string_start
,
7165 displacement_string_end
))
7169 /* Special case for (%dx) while doing input/output op. */
7171 && operand_type_equal (&i
.base_reg
->reg_type
,
7172 ®16_inoutportreg
)
7174 && i
.log2_scale_factor
== 0
7175 && i
.seg
[i
.mem_operands
] == 0
7176 && !operand_type_check (i
.types
[this_operand
], disp
))
7178 i
.types
[this_operand
] = inoutportreg
;
7182 if (i386_index_check (operand_string
) == 0)
7184 i
.types
[this_operand
].bitfield
.mem
= 1;
7189 /* It's not a memory operand; argh! */
7190 as_bad (_("invalid char %s beginning operand %d `%s'"),
7191 output_invalid (*op_string
),
7196 return 1; /* Normal return. */
7199 /* md_estimate_size_before_relax()
7201 Called just before relax() for rs_machine_dependent frags. The x86
7202 assembler uses these frags to handle variable size jump
7205 Any symbol that is now undefined will not become defined.
7206 Return the correct fr_subtype in the frag.
7207 Return the initial "guess for variable size of frag" to caller.
7208 The guess is actually the growth beyond the fixed part. Whatever
7209 we do to grow the fixed or variable part contributes to our
7213 md_estimate_size_before_relax (fragP
, segment
)
7217 /* We've already got fragP->fr_subtype right; all we have to do is
7218 check for un-relaxable symbols. On an ELF system, we can't relax
7219 an externally visible symbol, because it may be overridden by a
7221 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7222 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7224 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7225 || S_IS_WEAK (fragP
->fr_symbol
)
7226 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7227 & BSF_GNU_INDIRECT_FUNCTION
))))
7229 #if defined (OBJ_COFF) && defined (TE_PE)
7230 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7231 && S_IS_WEAK (fragP
->fr_symbol
))
7235 /* Symbol is undefined in this segment, or we need to keep a
7236 reloc so that weak symbols can be overridden. */
7237 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7238 enum bfd_reloc_code_real reloc_type
;
7239 unsigned char *opcode
;
7242 if (fragP
->fr_var
!= NO_RELOC
)
7243 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7245 reloc_type
= BFD_RELOC_16_PCREL
;
7247 reloc_type
= BFD_RELOC_32_PCREL
;
7249 old_fr_fix
= fragP
->fr_fix
;
7250 opcode
= (unsigned char *) fragP
->fr_opcode
;
7252 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7255 /* Make jmp (0xeb) a (d)word displacement jump. */
7257 fragP
->fr_fix
+= size
;
7258 fix_new (fragP
, old_fr_fix
, size
,
7260 fragP
->fr_offset
, 1,
7266 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7268 /* Negate the condition, and branch past an
7269 unconditional jump. */
7272 /* Insert an unconditional jump. */
7274 /* We added two extra opcode bytes, and have a two byte
7276 fragP
->fr_fix
+= 2 + 2;
7277 fix_new (fragP
, old_fr_fix
+ 2, 2,
7279 fragP
->fr_offset
, 1,
7286 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7291 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7293 fragP
->fr_offset
, 1,
7295 fixP
->fx_signed
= 1;
7299 /* This changes the byte-displacement jump 0x7N
7300 to the (d)word-displacement jump 0x0f,0x8N. */
7301 opcode
[1] = opcode
[0] + 0x10;
7302 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7303 /* We've added an opcode byte. */
7304 fragP
->fr_fix
+= 1 + size
;
7305 fix_new (fragP
, old_fr_fix
+ 1, size
,
7307 fragP
->fr_offset
, 1,
7312 BAD_CASE (fragP
->fr_subtype
);
7316 return fragP
->fr_fix
- old_fr_fix
;
7319 /* Guess size depending on current relax state. Initially the relax
7320 state will correspond to a short jump and we return 1, because
7321 the variable part of the frag (the branch offset) is one byte
7322 long. However, we can relax a section more than once and in that
7323 case we must either set fr_subtype back to the unrelaxed state,
7324 or return the value for the appropriate branch. */
7325 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7328 /* Called after relax() is finished.
7330 In: Address of frag.
7331 fr_type == rs_machine_dependent.
7332 fr_subtype is what the address relaxed to.
7334 Out: Any fixSs and constants are set up.
7335 Caller will turn frag into a ".space 0". */
7338 md_convert_frag (abfd
, sec
, fragP
)
7339 bfd
*abfd ATTRIBUTE_UNUSED
;
7340 segT sec ATTRIBUTE_UNUSED
;
7343 unsigned char *opcode
;
7344 unsigned char *where_to_put_displacement
= NULL
;
7345 offsetT target_address
;
7346 offsetT opcode_address
;
7347 unsigned int extension
= 0;
7348 offsetT displacement_from_opcode_start
;
7350 opcode
= (unsigned char *) fragP
->fr_opcode
;
7352 /* Address we want to reach in file space. */
7353 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7355 /* Address opcode resides at in file space. */
7356 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7358 /* Displacement from opcode start to fill into instruction. */
7359 displacement_from_opcode_start
= target_address
- opcode_address
;
7361 if ((fragP
->fr_subtype
& BIG
) == 0)
7363 /* Don't have to change opcode. */
7364 extension
= 1; /* 1 opcode + 1 displacement */
7365 where_to_put_displacement
= &opcode
[1];
7369 if (no_cond_jump_promotion
7370 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7371 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7372 _("long jump required"));
7374 switch (fragP
->fr_subtype
)
7376 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7377 extension
= 4; /* 1 opcode + 4 displacement */
7379 where_to_put_displacement
= &opcode
[1];
7382 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7383 extension
= 2; /* 1 opcode + 2 displacement */
7385 where_to_put_displacement
= &opcode
[1];
7388 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7389 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7390 extension
= 5; /* 2 opcode + 4 displacement */
7391 opcode
[1] = opcode
[0] + 0x10;
7392 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7393 where_to_put_displacement
= &opcode
[2];
7396 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7397 extension
= 3; /* 2 opcode + 2 displacement */
7398 opcode
[1] = opcode
[0] + 0x10;
7399 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7400 where_to_put_displacement
= &opcode
[2];
7403 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7408 where_to_put_displacement
= &opcode
[3];
7412 BAD_CASE (fragP
->fr_subtype
);
7417 /* If size if less then four we are sure that the operand fits,
7418 but if it's 4, then it could be that the displacement is larger
7420 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7422 && ((addressT
) (displacement_from_opcode_start
- extension
7423 + ((addressT
) 1 << 31))
7424 > (((addressT
) 2 << 31) - 1)))
7426 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7427 _("jump target out of range"));
7428 /* Make us emit 0. */
7429 displacement_from_opcode_start
= extension
;
7431 /* Now put displacement after opcode. */
7432 md_number_to_chars ((char *) where_to_put_displacement
,
7433 (valueT
) (displacement_from_opcode_start
- extension
),
7434 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7435 fragP
->fr_fix
+= extension
;
7438 /* Apply a fixup (fixS) to segment data, once it has been determined
7439 by our caller that we have all the info we need to fix it up.
7441 On the 386, immediates, displacements, and data pointers are all in
7442 the same (little-endian) format, so we don't need to care about which
7446 md_apply_fix (fixP
, valP
, seg
)
7447 /* The fix we're to put in. */
7449 /* Pointer to the value of the bits. */
7451 /* Segment fix is from. */
7452 segT seg ATTRIBUTE_UNUSED
;
7454 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7455 valueT value
= *valP
;
7457 #if !defined (TE_Mach)
7460 switch (fixP
->fx_r_type
)
7466 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7469 case BFD_RELOC_X86_64_32S
:
7470 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7473 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7476 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7481 if (fixP
->fx_addsy
!= NULL
7482 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7483 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7484 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7485 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7486 && !use_rela_relocations
)
7488 /* This is a hack. There should be a better way to handle this.
7489 This covers for the fact that bfd_install_relocation will
7490 subtract the current location (for partial_inplace, PC relative
7491 relocations); see more below. */
7495 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7498 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7500 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7503 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7506 || (symbol_section_p (fixP
->fx_addsy
)
7507 && sym_seg
!= absolute_section
))
7508 && !generic_force_reloc (fixP
))
7510 /* Yes, we add the values in twice. This is because
7511 bfd_install_relocation subtracts them out again. I think
7512 bfd_install_relocation is broken, but I don't dare change
7514 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7518 #if defined (OBJ_COFF) && defined (TE_PE)
7519 /* For some reason, the PE format does not store a
7520 section address offset for a PC relative symbol. */
7521 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7522 || S_IS_WEAK (fixP
->fx_addsy
))
7523 value
+= md_pcrel_from (fixP
);
7526 #if defined (OBJ_COFF) && defined (TE_PE)
7527 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7529 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7533 /* Fix a few things - the dynamic linker expects certain values here,
7534 and we must not disappoint it. */
7535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7536 if (IS_ELF
&& fixP
->fx_addsy
)
7537 switch (fixP
->fx_r_type
)
7539 case BFD_RELOC_386_PLT32
:
7540 case BFD_RELOC_X86_64_PLT32
:
7541 /* Make the jump instruction point to the address of the operand. At
7542 runtime we merely add the offset to the actual PLT entry. */
7546 case BFD_RELOC_386_TLS_GD
:
7547 case BFD_RELOC_386_TLS_LDM
:
7548 case BFD_RELOC_386_TLS_IE_32
:
7549 case BFD_RELOC_386_TLS_IE
:
7550 case BFD_RELOC_386_TLS_GOTIE
:
7551 case BFD_RELOC_386_TLS_GOTDESC
:
7552 case BFD_RELOC_X86_64_TLSGD
:
7553 case BFD_RELOC_X86_64_TLSLD
:
7554 case BFD_RELOC_X86_64_GOTTPOFF
:
7555 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7556 value
= 0; /* Fully resolved at runtime. No addend. */
7558 case BFD_RELOC_386_TLS_LE
:
7559 case BFD_RELOC_386_TLS_LDO_32
:
7560 case BFD_RELOC_386_TLS_LE_32
:
7561 case BFD_RELOC_X86_64_DTPOFF32
:
7562 case BFD_RELOC_X86_64_DTPOFF64
:
7563 case BFD_RELOC_X86_64_TPOFF32
:
7564 case BFD_RELOC_X86_64_TPOFF64
:
7565 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7568 case BFD_RELOC_386_TLS_DESC_CALL
:
7569 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7570 value
= 0; /* Fully resolved at runtime. No addend. */
7571 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7575 case BFD_RELOC_386_GOT32
:
7576 case BFD_RELOC_X86_64_GOT32
:
7577 value
= 0; /* Fully resolved at runtime. No addend. */
7580 case BFD_RELOC_VTABLE_INHERIT
:
7581 case BFD_RELOC_VTABLE_ENTRY
:
7588 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7590 #endif /* !defined (TE_Mach) */
7592 /* Are we finished with this relocation now? */
7593 if (fixP
->fx_addsy
== NULL
)
7595 #if defined (OBJ_COFF) && defined (TE_PE)
7596 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7599 /* Remember value for tc_gen_reloc. */
7600 fixP
->fx_addnumber
= value
;
7601 /* Clear out the frag for now. */
7605 else if (use_rela_relocations
)
7607 fixP
->fx_no_overflow
= 1;
7608 /* Remember value for tc_gen_reloc. */
7609 fixP
->fx_addnumber
= value
;
7613 md_number_to_chars (p
, value
, fixP
->fx_size
);
7617 md_atof (int type
, char *litP
, int *sizeP
)
7619 /* This outputs the LITTLENUMs in REVERSE order;
7620 in accord with the bigendian 386. */
7621 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7624 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7627 output_invalid (int c
)
7630 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7633 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7634 "(0x%x)", (unsigned char) c
);
7635 return output_invalid_buf
;
7638 /* REG_STRING starts *before* REGISTER_PREFIX. */
7640 static const reg_entry
*
7641 parse_real_register (char *reg_string
, char **end_op
)
7643 char *s
= reg_string
;
7645 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7648 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7649 if (*s
== REGISTER_PREFIX
)
7652 if (is_space_char (*s
))
7656 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7658 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7659 return (const reg_entry
*) NULL
;
7663 /* For naked regs, make sure that we are not dealing with an identifier.
7664 This prevents confusing an identifier like `eax_var' with register
7666 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7667 return (const reg_entry
*) NULL
;
7671 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7673 /* Handle floating point regs, allowing spaces in the (i) part. */
7674 if (r
== i386_regtab
/* %st is first entry of table */)
7676 if (is_space_char (*s
))
7681 if (is_space_char (*s
))
7683 if (*s
>= '0' && *s
<= '7')
7687 if (is_space_char (*s
))
7692 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7697 /* We have "%st(" then garbage. */
7698 return (const reg_entry
*) NULL
;
7702 if (r
== NULL
|| allow_pseudo_reg
)
7705 if (operand_type_all_zero (&r
->reg_type
))
7706 return (const reg_entry
*) NULL
;
7708 if ((r
->reg_type
.bitfield
.reg32
7709 || r
->reg_type
.bitfield
.sreg3
7710 || r
->reg_type
.bitfield
.control
7711 || r
->reg_type
.bitfield
.debug
7712 || r
->reg_type
.bitfield
.test
)
7713 && !cpu_arch_flags
.bitfield
.cpui386
)
7714 return (const reg_entry
*) NULL
;
7716 if (r
->reg_type
.bitfield
.floatreg
7717 && !cpu_arch_flags
.bitfield
.cpu8087
7718 && !cpu_arch_flags
.bitfield
.cpu287
7719 && !cpu_arch_flags
.bitfield
.cpu387
)
7720 return (const reg_entry
*) NULL
;
7722 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7723 return (const reg_entry
*) NULL
;
7725 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7726 return (const reg_entry
*) NULL
;
7728 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7729 return (const reg_entry
*) NULL
;
7731 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7732 if (!allow_index_reg
7733 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7734 return (const reg_entry
*) NULL
;
7736 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7737 || r
->reg_type
.bitfield
.reg64
)
7738 && (!cpu_arch_flags
.bitfield
.cpulm
7739 || !operand_type_equal (&r
->reg_type
, &control
))
7740 && flag_code
!= CODE_64BIT
)
7741 return (const reg_entry
*) NULL
;
7743 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7744 return (const reg_entry
*) NULL
;
7749 /* REG_STRING starts *before* REGISTER_PREFIX. */
7751 static const reg_entry
*
7752 parse_register (char *reg_string
, char **end_op
)
7756 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7757 r
= parse_real_register (reg_string
, end_op
);
7762 char *save
= input_line_pointer
;
7766 input_line_pointer
= reg_string
;
7767 c
= get_symbol_end ();
7768 symbolP
= symbol_find (reg_string
);
7769 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7771 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7773 know (e
->X_op
== O_register
);
7774 know (e
->X_add_number
>= 0
7775 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7776 r
= i386_regtab
+ e
->X_add_number
;
7777 *end_op
= input_line_pointer
;
7779 *input_line_pointer
= c
;
7780 input_line_pointer
= save
;
7786 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7789 char *end
= input_line_pointer
;
7792 r
= parse_register (name
, &input_line_pointer
);
7793 if (r
&& end
<= input_line_pointer
)
7795 *nextcharP
= *input_line_pointer
;
7796 *input_line_pointer
= 0;
7797 e
->X_op
= O_register
;
7798 e
->X_add_number
= r
- i386_regtab
;
7801 input_line_pointer
= end
;
7803 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7807 md_operand (expressionS
*e
)
7812 switch (*input_line_pointer
)
7814 case REGISTER_PREFIX
:
7815 r
= parse_real_register (input_line_pointer
, &end
);
7818 e
->X_op
= O_register
;
7819 e
->X_add_number
= r
- i386_regtab
;
7820 input_line_pointer
= end
;
7825 gas_assert (intel_syntax
);
7826 end
= input_line_pointer
++;
7828 if (*input_line_pointer
== ']')
7830 ++input_line_pointer
;
7831 e
->X_op_symbol
= make_expr_symbol (e
);
7832 e
->X_add_symbol
= NULL
;
7833 e
->X_add_number
= 0;
7839 input_line_pointer
= end
;
7846 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7847 const char *md_shortopts
= "kVQ:sqn";
7849 const char *md_shortopts
= "qn";
7852 #define OPTION_32 (OPTION_MD_BASE + 0)
7853 #define OPTION_64 (OPTION_MD_BASE + 1)
7854 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7855 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7856 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7857 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7858 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7859 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7860 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7861 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7862 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7863 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7865 struct option md_longopts
[] =
7867 {"32", no_argument
, NULL
, OPTION_32
},
7868 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7869 || defined (TE_PE) || defined (TE_PEP))
7870 {"64", no_argument
, NULL
, OPTION_64
},
7872 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7873 {"march", required_argument
, NULL
, OPTION_MARCH
},
7874 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7875 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7876 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7877 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7878 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7879 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7880 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7881 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7882 {NULL
, no_argument
, NULL
, 0}
7884 size_t md_longopts_size
= sizeof (md_longopts
);
7887 md_parse_option (int c
, char *arg
)
7895 optimize_align_code
= 0;
7902 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7903 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7904 should be emitted or not. FIXME: Not implemented. */
7908 /* -V: SVR4 argument to print version ID. */
7910 print_version_id ();
7913 /* -k: Ignore for FreeBSD compatibility. */
7918 /* -s: On i386 Solaris, this tells the native assembler to use
7919 .stab instead of .stab.excl. We always use .stab anyhow. */
7922 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7923 || defined (TE_PE) || defined (TE_PEP))
7926 const char **list
, **l
;
7928 list
= bfd_target_list ();
7929 for (l
= list
; *l
!= NULL
; l
++)
7930 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7931 || strcmp (*l
, "coff-x86-64") == 0
7932 || strcmp (*l
, "pe-x86-64") == 0
7933 || strcmp (*l
, "pei-x86-64") == 0)
7935 default_arch
= "x86_64";
7939 as_fatal (_("No compiled in support for x86_64"));
7946 default_arch
= "i386";
7950 #ifdef SVR4_COMMENT_CHARS
7955 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7957 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7961 i386_comment_chars
= n
;
7967 arch
= xstrdup (arg
);
7971 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7972 next
= strchr (arch
, '+');
7975 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
7977 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
7980 cpu_arch_name
= cpu_arch
[j
].name
;
7981 cpu_sub_arch_name
= NULL
;
7982 cpu_arch_flags
= cpu_arch
[j
].flags
;
7983 cpu_arch_isa
= cpu_arch
[j
].type
;
7984 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
7985 if (!cpu_arch_tune_set
)
7987 cpu_arch_tune
= cpu_arch_isa
;
7988 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7992 else if (*cpu_arch
[j
].name
== '.'
7993 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
7995 /* ISA entension. */
7996 i386_cpu_flags flags
;
7998 if (strncmp (arch
, "no", 2))
7999 flags
= cpu_flags_or (cpu_arch_flags
,
8002 flags
= cpu_flags_and_not (cpu_arch_flags
,
8004 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8006 if (cpu_sub_arch_name
)
8008 char *name
= cpu_sub_arch_name
;
8009 cpu_sub_arch_name
= concat (name
,
8011 (const char *) NULL
);
8015 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8016 cpu_arch_flags
= flags
;
8022 if (j
>= ARRAY_SIZE (cpu_arch
))
8023 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8027 while (next
!= NULL
);
8032 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8033 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8035 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8037 cpu_arch_tune_set
= 1;
8038 cpu_arch_tune
= cpu_arch
[j
].type
;
8039 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8043 if (j
>= ARRAY_SIZE (cpu_arch
))
8044 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8047 case OPTION_MMNEMONIC
:
8048 if (strcasecmp (arg
, "att") == 0)
8050 else if (strcasecmp (arg
, "intel") == 0)
8053 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8056 case OPTION_MSYNTAX
:
8057 if (strcasecmp (arg
, "att") == 0)
8059 else if (strcasecmp (arg
, "intel") == 0)
8062 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8065 case OPTION_MINDEX_REG
:
8066 allow_index_reg
= 1;
8069 case OPTION_MNAKED_REG
:
8070 allow_naked_reg
= 1;
8073 case OPTION_MOLD_GCC
:
8077 case OPTION_MSSE2AVX
:
8081 case OPTION_MSSE_CHECK
:
8082 if (strcasecmp (arg
, "error") == 0)
8083 sse_check
= sse_check_error
;
8084 else if (strcasecmp (arg
, "warning") == 0)
8085 sse_check
= sse_check_warning
;
8086 else if (strcasecmp (arg
, "none") == 0)
8087 sse_check
= sse_check_none
;
8089 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8098 #define MESSAGE_TEMPLATE \
8102 show_arch (FILE *stream
, int ext
)
8104 static char message
[] = MESSAGE_TEMPLATE
;
8105 char *start
= message
+ 27;
8107 int size
= sizeof (MESSAGE_TEMPLATE
);
8114 left
= size
- (start
- message
);
8115 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8117 /* Should it be skipped? */
8118 if (cpu_arch
[j
].skip
)
8121 name
= cpu_arch
[j
].name
;
8122 len
= cpu_arch
[j
].len
;
8125 /* It is an extension. Skip if we aren't asked to show it. */
8136 /* It is an processor. Skip if we show only extension. */
8140 /* Reserve 2 spaces for ", " or ",\0" */
8143 /* Check if there is any room. */
8151 p
= mempcpy (p
, name
, len
);
8155 /* Output the current message now and start a new one. */
8158 fprintf (stream
, "%s\n", message
);
8160 left
= size
- (start
- message
) - len
- 2;
8162 gas_assert (left
>= 0);
8164 p
= mempcpy (p
, name
, len
);
8169 fprintf (stream
, "%s\n", message
);
8173 md_show_usage (FILE *stream
)
8175 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8176 fprintf (stream
, _("\
8178 -V print assembler version number\n\
8181 fprintf (stream
, _("\
8182 -n Do not optimize code alignment\n\
8183 -q quieten some warnings\n"));
8184 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8185 fprintf (stream
, _("\
8188 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8189 || defined (TE_PE) || defined (TE_PEP))
8190 fprintf (stream
, _("\
8191 --32/--64 generate 32bit/64bit code\n"));
8193 #ifdef SVR4_COMMENT_CHARS
8194 fprintf (stream
, _("\
8195 --divide do not treat `/' as a comment character\n"));
8197 fprintf (stream
, _("\
8198 --divide ignored\n"));
8200 fprintf (stream
, _("\
8201 -march=CPU[,+EXTENSION...]\n\
8202 generate code for CPU and EXTENSION, CPU is one of:\n"));
8203 show_arch (stream
, 0);
8204 fprintf (stream
, _("\
8205 EXTENSION is combination of:\n"));
8206 show_arch (stream
, 1);
8207 fprintf (stream
, _("\
8208 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8209 show_arch (stream
, 0);
8210 fprintf (stream
, _("\
8211 -msse2avx encode SSE instructions with VEX prefix\n"));
8212 fprintf (stream
, _("\
8213 -msse-check=[none|error|warning]\n\
8214 check SSE instructions\n"));
8215 fprintf (stream
, _("\
8216 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8217 fprintf (stream
, _("\
8218 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8219 fprintf (stream
, _("\
8220 -mindex-reg support pseudo index registers\n"));
8221 fprintf (stream
, _("\
8222 -mnaked-reg don't require `%%' prefix for registers\n"));
8223 fprintf (stream
, _("\
8224 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8227 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8228 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8229 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8231 /* Pick the target format to use. */
8234 i386_target_format (void)
8236 if (!strcmp (default_arch
, "x86_64"))
8238 set_code_flag (CODE_64BIT
);
8239 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8241 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8242 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8243 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8244 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8245 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8246 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8247 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8248 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8249 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8250 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8251 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8253 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8255 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8256 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8257 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8258 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8259 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8260 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8261 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8262 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8263 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8264 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8267 else if (!strcmp (default_arch
, "i386"))
8269 set_code_flag (CODE_32BIT
);
8270 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8272 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8273 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8274 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8276 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8278 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8279 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8280 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8284 as_fatal (_("Unknown architecture"));
8285 switch (OUTPUT_FLAVOR
)
8287 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8288 case bfd_target_aout_flavour
:
8289 return AOUT_TARGET_FORMAT
;
8291 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8292 # if defined (TE_PE) || defined (TE_PEP)
8293 case bfd_target_coff_flavour
:
8294 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8295 # elif defined (TE_GO32)
8296 case bfd_target_coff_flavour
:
8299 case bfd_target_coff_flavour
:
8303 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8304 case bfd_target_elf_flavour
:
8306 if (flag_code
== CODE_64BIT
)
8309 use_rela_relocations
= 1;
8311 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8313 if (flag_code
!= CODE_64BIT
)
8314 as_fatal (_("Intel L1OM is 64bit only"));
8315 return ELF_TARGET_L1OM_FORMAT
;
8318 return (flag_code
== CODE_64BIT
8319 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8322 #if defined (OBJ_MACH_O)
8323 case bfd_target_mach_o_flavour
:
8324 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8332 #endif /* OBJ_MAYBE_ more than one */
8334 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8336 i386_elf_emit_arch_note (void)
8338 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8341 asection
*seg
= now_seg
;
8342 subsegT subseg
= now_subseg
;
8343 Elf_Internal_Note i_note
;
8344 Elf_External_Note e_note
;
8345 asection
*note_secp
;
8348 /* Create the .note section. */
8349 note_secp
= subseg_new (".note", 0);
8350 bfd_set_section_flags (stdoutput
,
8352 SEC_HAS_CONTENTS
| SEC_READONLY
);
8354 /* Process the arch string. */
8355 len
= strlen (cpu_arch_name
);
8357 i_note
.namesz
= len
+ 1;
8359 i_note
.type
= NT_ARCH
;
8360 p
= frag_more (sizeof (e_note
.namesz
));
8361 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8362 p
= frag_more (sizeof (e_note
.descsz
));
8363 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8364 p
= frag_more (sizeof (e_note
.type
));
8365 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8366 p
= frag_more (len
+ 1);
8367 strcpy (p
, cpu_arch_name
);
8369 frag_align (2, 0, 0);
8371 subseg_set (seg
, subseg
);
8377 md_undefined_symbol (name
)
8380 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8381 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8382 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8383 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8387 if (symbol_find (name
))
8388 as_bad (_("GOT already in symbol table"));
8389 GOT_symbol
= symbol_new (name
, undefined_section
,
8390 (valueT
) 0, &zero_address_frag
);
8397 /* Round up a section size to the appropriate boundary. */
8400 md_section_align (segment
, size
)
8401 segT segment ATTRIBUTE_UNUSED
;
8404 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8405 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8407 /* For a.out, force the section size to be aligned. If we don't do
8408 this, BFD will align it for us, but it will not write out the
8409 final bytes of the section. This may be a bug in BFD, but it is
8410 easier to fix it here since that is how the other a.out targets
8414 align
= bfd_get_section_alignment (stdoutput
, segment
);
8415 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8422 /* On the i386, PC-relative offsets are relative to the start of the
8423 next instruction. That is, the address of the offset, plus its
8424 size, since the offset is always the last part of the insn. */
8427 md_pcrel_from (fixS
*fixP
)
8429 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8435 s_bss (int ignore ATTRIBUTE_UNUSED
)
8439 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8441 obj_elf_section_change_hook ();
8443 temp
= get_absolute_expression ();
8444 subseg_set (bss_section
, (subsegT
) temp
);
8445 demand_empty_rest_of_line ();
8451 i386_validate_fix (fixS
*fixp
)
8453 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8455 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8459 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8464 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8466 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8473 tc_gen_reloc (section
, fixp
)
8474 asection
*section ATTRIBUTE_UNUSED
;
8478 bfd_reloc_code_real_type code
;
8480 switch (fixp
->fx_r_type
)
8482 case BFD_RELOC_X86_64_PLT32
:
8483 case BFD_RELOC_X86_64_GOT32
:
8484 case BFD_RELOC_X86_64_GOTPCREL
:
8485 case BFD_RELOC_386_PLT32
:
8486 case BFD_RELOC_386_GOT32
:
8487 case BFD_RELOC_386_GOTOFF
:
8488 case BFD_RELOC_386_GOTPC
:
8489 case BFD_RELOC_386_TLS_GD
:
8490 case BFD_RELOC_386_TLS_LDM
:
8491 case BFD_RELOC_386_TLS_LDO_32
:
8492 case BFD_RELOC_386_TLS_IE_32
:
8493 case BFD_RELOC_386_TLS_IE
:
8494 case BFD_RELOC_386_TLS_GOTIE
:
8495 case BFD_RELOC_386_TLS_LE_32
:
8496 case BFD_RELOC_386_TLS_LE
:
8497 case BFD_RELOC_386_TLS_GOTDESC
:
8498 case BFD_RELOC_386_TLS_DESC_CALL
:
8499 case BFD_RELOC_X86_64_TLSGD
:
8500 case BFD_RELOC_X86_64_TLSLD
:
8501 case BFD_RELOC_X86_64_DTPOFF32
:
8502 case BFD_RELOC_X86_64_DTPOFF64
:
8503 case BFD_RELOC_X86_64_GOTTPOFF
:
8504 case BFD_RELOC_X86_64_TPOFF32
:
8505 case BFD_RELOC_X86_64_TPOFF64
:
8506 case BFD_RELOC_X86_64_GOTOFF64
:
8507 case BFD_RELOC_X86_64_GOTPC32
:
8508 case BFD_RELOC_X86_64_GOT64
:
8509 case BFD_RELOC_X86_64_GOTPCREL64
:
8510 case BFD_RELOC_X86_64_GOTPC64
:
8511 case BFD_RELOC_X86_64_GOTPLT64
:
8512 case BFD_RELOC_X86_64_PLTOFF64
:
8513 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8514 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8516 case BFD_RELOC_VTABLE_ENTRY
:
8517 case BFD_RELOC_VTABLE_INHERIT
:
8519 case BFD_RELOC_32_SECREL
:
8521 code
= fixp
->fx_r_type
;
8523 case BFD_RELOC_X86_64_32S
:
8524 if (!fixp
->fx_pcrel
)
8526 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8527 code
= fixp
->fx_r_type
;
8533 switch (fixp
->fx_size
)
8536 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8537 _("can not do %d byte pc-relative relocation"),
8539 code
= BFD_RELOC_32_PCREL
;
8541 case 1: code
= BFD_RELOC_8_PCREL
; break;
8542 case 2: code
= BFD_RELOC_16_PCREL
; break;
8543 case 4: code
= BFD_RELOC_32_PCREL
; break;
8545 case 8: code
= BFD_RELOC_64_PCREL
; break;
8551 switch (fixp
->fx_size
)
8554 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8555 _("can not do %d byte relocation"),
8557 code
= BFD_RELOC_32
;
8559 case 1: code
= BFD_RELOC_8
; break;
8560 case 2: code
= BFD_RELOC_16
; break;
8561 case 4: code
= BFD_RELOC_32
; break;
8563 case 8: code
= BFD_RELOC_64
; break;
8570 if ((code
== BFD_RELOC_32
8571 || code
== BFD_RELOC_32_PCREL
8572 || code
== BFD_RELOC_X86_64_32S
)
8574 && fixp
->fx_addsy
== GOT_symbol
)
8577 code
= BFD_RELOC_386_GOTPC
;
8579 code
= BFD_RELOC_X86_64_GOTPC32
;
8581 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8583 && fixp
->fx_addsy
== GOT_symbol
)
8585 code
= BFD_RELOC_X86_64_GOTPC64
;
8588 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8589 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8590 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8592 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8594 if (!use_rela_relocations
)
8596 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8597 vtable entry to be used in the relocation's section offset. */
8598 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8599 rel
->address
= fixp
->fx_offset
;
8600 #if defined (OBJ_COFF) && defined (TE_PE)
8601 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8602 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8607 /* Use the rela in 64bit mode. */
8610 if (!fixp
->fx_pcrel
)
8611 rel
->addend
= fixp
->fx_offset
;
8615 case BFD_RELOC_X86_64_PLT32
:
8616 case BFD_RELOC_X86_64_GOT32
:
8617 case BFD_RELOC_X86_64_GOTPCREL
:
8618 case BFD_RELOC_X86_64_TLSGD
:
8619 case BFD_RELOC_X86_64_TLSLD
:
8620 case BFD_RELOC_X86_64_GOTTPOFF
:
8621 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8622 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8623 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8626 rel
->addend
= (section
->vma
8628 + fixp
->fx_addnumber
8629 + md_pcrel_from (fixp
));
8634 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8635 if (rel
->howto
== NULL
)
8637 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8638 _("cannot represent relocation type %s"),
8639 bfd_get_reloc_code_name (code
));
8640 /* Set howto to a garbage value so that we can keep going. */
8641 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8642 gas_assert (rel
->howto
!= NULL
);
8648 #include "tc-i386-intel.c"
8651 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8653 int saved_naked_reg
;
8654 char saved_register_dot
;
8656 saved_naked_reg
= allow_naked_reg
;
8657 allow_naked_reg
= 1;
8658 saved_register_dot
= register_chars
['.'];
8659 register_chars
['.'] = '.';
8660 allow_pseudo_reg
= 1;
8661 expression_and_evaluate (exp
);
8662 allow_pseudo_reg
= 0;
8663 register_chars
['.'] = saved_register_dot
;
8664 allow_naked_reg
= saved_naked_reg
;
8666 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8668 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8670 exp
->X_op
= O_constant
;
8671 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8672 .dw2_regnum
[flag_code
>> 1];
8675 exp
->X_op
= O_illegal
;
8680 tc_x86_frame_initial_instructions (void)
8682 static unsigned int sp_regno
[2];
8684 if (!sp_regno
[flag_code
>> 1])
8686 char *saved_input
= input_line_pointer
;
8687 char sp
[][4] = {"esp", "rsp"};
8690 input_line_pointer
= sp
[flag_code
>> 1];
8691 tc_x86_parse_to_dw2regnum (&exp
);
8692 gas_assert (exp
.X_op
== O_constant
);
8693 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8694 input_line_pointer
= saved_input
;
8697 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8698 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8702 i386_elf_section_type (const char *str
, size_t len
)
8704 if (flag_code
== CODE_64BIT
8705 && len
== sizeof ("unwind") - 1
8706 && strncmp (str
, "unwind", 6) == 0)
8707 return SHT_X86_64_UNWIND
;
8714 i386_solaris_fix_up_eh_frame (segT sec
)
8716 if (flag_code
== CODE_64BIT
)
8717 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8723 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8727 exp
.X_op
= O_secrel
;
8728 exp
.X_add_symbol
= symbol
;
8729 exp
.X_add_number
= 0;
8730 emit_expr (&exp
, size
);
8734 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8735 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8738 x86_64_section_letter (int letter
, char **ptr_msg
)
8740 if (flag_code
== CODE_64BIT
)
8743 return SHF_X86_64_LARGE
;
8745 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8748 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8753 x86_64_section_word (char *str
, size_t len
)
8755 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8756 return SHF_X86_64_LARGE
;
8762 handle_large_common (int small ATTRIBUTE_UNUSED
)
8764 if (flag_code
!= CODE_64BIT
)
8766 s_comm_internal (0, elf_common_parse
);
8767 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8771 static segT lbss_section
;
8772 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8773 asection
*saved_bss_section
= bss_section
;
8775 if (lbss_section
== NULL
)
8777 flagword applicable
;
8779 subsegT subseg
= now_subseg
;
8781 /* The .lbss section is for local .largecomm symbols. */
8782 lbss_section
= subseg_new (".lbss", 0);
8783 applicable
= bfd_applicable_section_flags (stdoutput
);
8784 bfd_set_section_flags (stdoutput
, lbss_section
,
8785 applicable
& SEC_ALLOC
);
8786 seg_info (lbss_section
)->bss
= 1;
8788 subseg_set (seg
, subseg
);
8791 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8792 bss_section
= lbss_section
;
8794 s_comm_internal (0, elf_common_parse
);
8796 elf_com_section_ptr
= saved_com_section_ptr
;
8797 bss_section
= saved_bss_section
;
8800 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */