1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 enum processor_type type
; /* arch type */
132 i386_cpu_flags flags
; /* cpu feature flags */
136 static void set_code_flag (int);
137 static void set_16bit_gcc_code_flag (int);
138 static void set_intel_syntax (int);
139 static void set_intel_mnemonic (int);
140 static void set_allow_index_reg (int);
141 static void set_sse_check (int);
142 static void set_cpu_arch (int);
144 static void pe_directive_secrel (int);
146 static void signed_cons (int);
147 static char *output_invalid (int c
);
148 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
150 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
152 static int i386_att_operand (char *);
153 static int i386_intel_operand (char *, int);
154 static int i386_intel_simplify (expressionS
*);
155 static int i386_intel_parse_name (const char *, expressionS
*);
156 static const reg_entry
*parse_register (char *, char **);
157 static char *parse_insn (char *, char *);
158 static char *parse_operands (char *, const char *);
159 static void swap_operands (void);
160 static void swap_2_operands (int, int);
161 static void optimize_imm (void);
162 static void optimize_disp (void);
163 static const insn_template
*match_template (void);
164 static int check_string (void);
165 static int process_suffix (void);
166 static int check_byte_reg (void);
167 static int check_long_reg (void);
168 static int check_qword_reg (void);
169 static int check_word_reg (void);
170 static int finalize_imm (void);
171 static int process_operands (void);
172 static const seg_entry
*build_modrm_byte (void);
173 static void output_insn (void);
174 static void output_imm (fragS
*, offsetT
);
175 static void output_disp (fragS
*, offsetT
);
177 static void s_bss (int);
179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
180 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
183 static const char *default_arch
= DEFAULT_ARCH
;
188 /* VEX prefix is either 2 byte or 3 byte. */
189 unsigned char bytes
[3];
191 /* Destination or source register specifier. */
192 const reg_entry
*register_specifier
;
195 /* 'md_assemble ()' gathers together information and puts it into a
202 const reg_entry
*regs
;
207 /* TM holds the template for the insn were currently assembling. */
210 /* SUFFIX holds the instruction size suffix for byte, word, dword
211 or qword, if given. */
214 /* OPERANDS gives the number of given operands. */
215 unsigned int operands
;
217 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
218 of given register, displacement, memory operands and immediate
220 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
222 /* TYPES [i] is the type (see above #defines) which tells us how to
223 use OP[i] for the corresponding operand. */
224 i386_operand_type types
[MAX_OPERANDS
];
226 /* Displacement expression, immediate expression, or register for each
228 union i386_op op
[MAX_OPERANDS
];
230 /* Flags for operands. */
231 unsigned int flags
[MAX_OPERANDS
];
232 #define Operand_PCrel 1
234 /* Relocation type for operand */
235 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
237 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
238 the base index byte below. */
239 const reg_entry
*base_reg
;
240 const reg_entry
*index_reg
;
241 unsigned int log2_scale_factor
;
243 /* SEG gives the seg_entries of this insn. They are zero unless
244 explicit segment overrides are given. */
245 const seg_entry
*seg
[2];
247 /* PREFIX holds all the given prefix opcodes (usually null).
248 PREFIXES is the number of prefix opcodes. */
249 unsigned int prefixes
;
250 unsigned char prefix
[MAX_PREFIXES
];
252 /* RM and SIB are the modrm byte and the sib byte where the
253 addressing modes of this insn are encoded. */
259 /* Swap operand in encoding. */
260 unsigned int swap_operand
;
263 typedef struct _i386_insn i386_insn
;
265 /* List of chars besides those in app.c:symbol_chars that can start an
266 operand. Used to prevent the scrubber eating vital white-space. */
267 const char extra_symbol_chars
[] = "*%-(["
276 #if (defined (TE_I386AIX) \
277 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
278 && !defined (TE_GNU) \
279 && !defined (TE_LINUX) \
280 && !defined (TE_NETWARE) \
281 && !defined (TE_FreeBSD) \
282 && !defined (TE_NetBSD)))
283 /* This array holds the chars that always start a comment. If the
284 pre-processor is disabled, these aren't very useful. The option
285 --divide will remove '/' from this list. */
286 const char *i386_comment_chars
= "#/";
287 #define SVR4_COMMENT_CHARS 1
288 #define PREFIX_SEPARATOR '\\'
291 const char *i386_comment_chars
= "#";
292 #define PREFIX_SEPARATOR '/'
295 /* This array holds the chars that only start a comment at the beginning of
296 a line. If the line seems to have the form '# 123 filename'
297 .line and .file directives will appear in the pre-processed output.
298 Note that input_file.c hand checks for '#' at the beginning of the
299 first line of the input file. This is because the compiler outputs
300 #NO_APP at the beginning of its output.
301 Also note that comments started like this one will always work if
302 '/' isn't otherwise defined. */
303 const char line_comment_chars
[] = "#/";
305 const char line_separator_chars
[] = ";";
307 /* Chars that can be used to separate mant from exp in floating point
309 const char EXP_CHARS
[] = "eE";
311 /* Chars that mean this number is a floating point constant
314 const char FLT_CHARS
[] = "fFdDxX";
316 /* Tables for lexical analysis. */
317 static char mnemonic_chars
[256];
318 static char register_chars
[256];
319 static char operand_chars
[256];
320 static char identifier_chars
[256];
321 static char digit_chars
[256];
323 /* Lexical macros. */
324 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
325 #define is_operand_char(x) (operand_chars[(unsigned char) x])
326 #define is_register_char(x) (register_chars[(unsigned char) x])
327 #define is_space_char(x) ((x) == ' ')
328 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
329 #define is_digit_char(x) (digit_chars[(unsigned char) x])
331 /* All non-digit non-letter characters that may occur in an operand. */
332 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
334 /* md_assemble() always leaves the strings it's passed unaltered. To
335 effect this we maintain a stack of saved characters that we've smashed
336 with '\0's (indicating end of strings for various sub-fields of the
337 assembler instruction). */
338 static char save_stack
[32];
339 static char *save_stack_p
;
340 #define END_STRING_AND_SAVE(s) \
341 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
342 #define RESTORE_END_STRING(s) \
343 do { *(s) = *--save_stack_p; } while (0)
345 /* The instruction we're assembling. */
348 /* Possible templates for current insn. */
349 static const templates
*current_templates
;
351 /* Per instruction expressionS buffers: max displacements & immediates. */
352 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
353 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
355 /* Current operand we are working on. */
356 static int this_operand
= -1;
358 /* We support four different modes. FLAG_CODE variable is used to distinguish
366 static enum flag_code flag_code
;
367 static unsigned int object_64bit
;
368 static int use_rela_relocations
= 0;
370 /* The names used to print error messages. */
371 static const char *flag_code_names
[] =
378 /* 1 for intel syntax,
380 static int intel_syntax
= 0;
382 /* 1 for intel mnemonic,
383 0 if att mnemonic. */
384 static int intel_mnemonic
= !SYSV386_COMPAT
;
386 /* 1 if support old (<= 2.8.1) versions of gcc. */
387 static int old_gcc
= OLDGCC_COMPAT
;
389 /* 1 if pseudo registers are permitted. */
390 static int allow_pseudo_reg
= 0;
392 /* 1 if register prefix % not required. */
393 static int allow_naked_reg
= 0;
395 /* 1 if pseudo index register, eiz/riz, is allowed . */
396 static int allow_index_reg
= 0;
406 /* Register prefix used for error message. */
407 static const char *register_prefix
= "%";
409 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
410 leave, push, and pop instructions so that gcc has the same stack
411 frame as in 32 bit mode. */
412 static char stackop_size
= '\0';
414 /* Non-zero to optimize code alignment. */
415 int optimize_align_code
= 1;
417 /* Non-zero to quieten some warnings. */
418 static int quiet_warnings
= 0;
421 static const char *cpu_arch_name
= NULL
;
422 static char *cpu_sub_arch_name
= NULL
;
424 /* CPU feature flags. */
425 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
427 /* If we have selected a cpu we are generating instructions for. */
428 static int cpu_arch_tune_set
= 0;
430 /* Cpu we are generating instructions for. */
431 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
433 /* CPU feature flags of cpu we are generating instructions for. */
434 static i386_cpu_flags cpu_arch_tune_flags
;
436 /* CPU instruction set architecture used. */
437 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
439 /* CPU feature flags of instruction set architecture used. */
440 i386_cpu_flags cpu_arch_isa_flags
;
442 /* If set, conditional jumps are not automatically promoted to handle
443 larger than a byte offset. */
444 static unsigned int no_cond_jump_promotion
= 0;
446 /* Encode SSE instructions with VEX prefix. */
447 static unsigned int sse2avx
;
449 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
450 static symbolS
*GOT_symbol
;
452 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
453 unsigned int x86_dwarf2_return_column
;
455 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
456 int x86_cie_data_alignment
;
458 /* Interface to relax_segment.
459 There are 3 major relax states for 386 jump insns because the
460 different types of jumps add different sizes to frags when we're
461 figuring out what sort of jump to choose to reach a given label. */
464 #define UNCOND_JUMP 0
466 #define COND_JUMP86 2
471 #define SMALL16 (SMALL | CODE16)
473 #define BIG16 (BIG | CODE16)
477 #define INLINE __inline__
483 #define ENCODE_RELAX_STATE(type, size) \
484 ((relax_substateT) (((type) << 2) | (size)))
485 #define TYPE_FROM_RELAX_STATE(s) \
487 #define DISP_SIZE_FROM_RELAX_STATE(s) \
488 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
490 /* This table is used by relax_frag to promote short jumps to long
491 ones where necessary. SMALL (short) jumps may be promoted to BIG
492 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
493 don't allow a short jump in a 32 bit code segment to be promoted to
494 a 16 bit offset jump because it's slower (requires data size
495 prefix), and doesn't work, unless the destination is in the bottom
496 64k of the code segment (The top 16 bits of eip are zeroed). */
498 const relax_typeS md_relax_table
[] =
501 1) most positive reach of this state,
502 2) most negative reach of this state,
503 3) how many bytes this mode will have in the variable part of the frag
504 4) which index into the table to try if we can't fit into this one. */
506 /* UNCOND_JUMP states. */
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
508 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
509 /* dword jmp adds 4 bytes to frag:
510 0 extra opcode bytes, 4 displacement bytes. */
512 /* word jmp adds 2 byte2 to frag:
513 0 extra opcode bytes, 2 displacement bytes. */
516 /* COND_JUMP states. */
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
518 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
519 /* dword conditionals adds 5 bytes to frag:
520 1 extra opcode byte, 4 displacement bytes. */
522 /* word conditionals add 3 bytes to frag:
523 1 extra opcode byte, 2 displacement bytes. */
526 /* COND_JUMP86 states. */
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
528 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
529 /* dword conditionals adds 5 bytes to frag:
530 1 extra opcode byte, 4 displacement bytes. */
532 /* word conditionals add 4 bytes to frag:
533 1 displacement byte and a 3 byte long branch insn. */
537 static const arch_entry cpu_arch
[] =
539 { "generic32", PROCESSOR_GENERIC32
,
540 CPU_GENERIC32_FLAGS
},
541 { "generic64", PROCESSOR_GENERIC64
,
542 CPU_GENERIC64_FLAGS
},
543 { "i8086", PROCESSOR_UNKNOWN
,
545 { "i186", PROCESSOR_UNKNOWN
,
547 { "i286", PROCESSOR_UNKNOWN
,
549 { "i386", PROCESSOR_I386
,
551 { "i486", PROCESSOR_I486
,
553 { "i586", PROCESSOR_PENTIUM
,
555 { "i686", PROCESSOR_PENTIUMPRO
,
557 { "pentium", PROCESSOR_PENTIUM
,
559 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
561 { "pentiumii", PROCESSOR_PENTIUMPRO
,
563 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
565 { "pentium4", PROCESSOR_PENTIUM4
,
567 { "prescott", PROCESSOR_NOCONA
,
569 { "nocona", PROCESSOR_NOCONA
,
571 { "yonah", PROCESSOR_CORE
,
573 { "core", PROCESSOR_CORE
,
575 { "merom", PROCESSOR_CORE2
,
577 { "core2", PROCESSOR_CORE2
,
579 { "corei7", PROCESSOR_COREI7
,
581 { "l1om", PROCESSOR_L1OM
,
583 { "k6", PROCESSOR_K6
,
585 { "k6_2", PROCESSOR_K6
,
587 { "athlon", PROCESSOR_ATHLON
,
589 { "sledgehammer", PROCESSOR_K8
,
591 { "opteron", PROCESSOR_K8
,
593 { "k8", PROCESSOR_K8
,
595 { "amdfam10", PROCESSOR_AMDFAM10
,
596 CPU_AMDFAM10_FLAGS
},
597 { ".8087", PROCESSOR_UNKNOWN
,
599 { ".287", PROCESSOR_UNKNOWN
,
601 { ".387", PROCESSOR_UNKNOWN
,
603 { ".no87", PROCESSOR_UNKNOWN
,
605 { ".mmx", PROCESSOR_UNKNOWN
,
607 { ".nommx", PROCESSOR_UNKNOWN
,
609 { ".sse", PROCESSOR_UNKNOWN
,
611 { ".sse2", PROCESSOR_UNKNOWN
,
613 { ".sse3", PROCESSOR_UNKNOWN
,
615 { ".ssse3", PROCESSOR_UNKNOWN
,
617 { ".sse4.1", PROCESSOR_UNKNOWN
,
619 { ".sse4.2", PROCESSOR_UNKNOWN
,
621 { ".sse4", PROCESSOR_UNKNOWN
,
623 { ".nosse", PROCESSOR_UNKNOWN
,
625 { ".avx", PROCESSOR_UNKNOWN
,
627 { ".noavx", PROCESSOR_UNKNOWN
,
629 { ".vmx", PROCESSOR_UNKNOWN
,
631 { ".smx", PROCESSOR_UNKNOWN
,
633 { ".xsave", PROCESSOR_UNKNOWN
,
635 { ".aes", PROCESSOR_UNKNOWN
,
637 { ".pclmul", PROCESSOR_UNKNOWN
,
639 { ".clmul", PROCESSOR_UNKNOWN
,
641 { ".fma", PROCESSOR_UNKNOWN
,
643 { ".fma4", PROCESSOR_UNKNOWN
,
645 { ".xop", PROCESSOR_UNKNOWN
,
647 { ".lwp", PROCESSOR_UNKNOWN
,
649 { ".movbe", PROCESSOR_UNKNOWN
,
651 { ".ept", PROCESSOR_UNKNOWN
,
653 { ".clflush", PROCESSOR_UNKNOWN
,
655 { ".syscall", PROCESSOR_UNKNOWN
,
657 { ".rdtscp", PROCESSOR_UNKNOWN
,
659 { ".3dnow", PROCESSOR_UNKNOWN
,
661 { ".3dnowa", PROCESSOR_UNKNOWN
,
663 { ".padlock", PROCESSOR_UNKNOWN
,
665 { ".pacifica", PROCESSOR_UNKNOWN
,
667 { ".svme", PROCESSOR_UNKNOWN
,
669 { ".sse4a", PROCESSOR_UNKNOWN
,
671 { ".abm", PROCESSOR_UNKNOWN
,
676 /* Like s_lcomm_internal in gas/read.c but the alignment string
677 is allowed to be optional. */
680 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
687 && *input_line_pointer
== ',')
689 align
= parse_align (needs_align
- 1);
691 if (align
== (addressT
) -1)
706 bss_alloc (symbolP
, size
, align
);
711 pe_lcomm (int needs_align
)
713 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
717 const pseudo_typeS md_pseudo_table
[] =
719 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
720 {"align", s_align_bytes
, 0},
722 {"align", s_align_ptwo
, 0},
724 {"arch", set_cpu_arch
, 0},
728 {"lcomm", pe_lcomm
, 1},
730 {"ffloat", float_cons
, 'f'},
731 {"dfloat", float_cons
, 'd'},
732 {"tfloat", float_cons
, 'x'},
734 {"slong", signed_cons
, 4},
735 {"noopt", s_ignore
, 0},
736 {"optim", s_ignore
, 0},
737 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
738 {"code16", set_code_flag
, CODE_16BIT
},
739 {"code32", set_code_flag
, CODE_32BIT
},
740 {"code64", set_code_flag
, CODE_64BIT
},
741 {"intel_syntax", set_intel_syntax
, 1},
742 {"att_syntax", set_intel_syntax
, 0},
743 {"intel_mnemonic", set_intel_mnemonic
, 1},
744 {"att_mnemonic", set_intel_mnemonic
, 0},
745 {"allow_index_reg", set_allow_index_reg
, 1},
746 {"disallow_index_reg", set_allow_index_reg
, 0},
747 {"sse_check", set_sse_check
, 0},
748 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
749 {"largecomm", handle_large_common
, 0},
751 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
752 {"loc", dwarf2_directive_loc
, 0},
753 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
756 {"secrel32", pe_directive_secrel
, 0},
761 /* For interface with expression (). */
762 extern char *input_line_pointer
;
764 /* Hash table for instruction mnemonic lookup. */
765 static struct hash_control
*op_hash
;
767 /* Hash table for register lookup. */
768 static struct hash_control
*reg_hash
;
771 i386_align_code (fragS
*fragP
, int count
)
773 /* Various efficient no-op patterns for aligning code labels.
774 Note: Don't try to assemble the instructions in the comments.
775 0L and 0w are not legal. */
776 static const char f32_1
[] =
778 static const char f32_2
[] =
779 {0x66,0x90}; /* xchg %ax,%ax */
780 static const char f32_3
[] =
781 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
782 static const char f32_4
[] =
783 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
784 static const char f32_5
[] =
786 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
787 static const char f32_6
[] =
788 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
789 static const char f32_7
[] =
790 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
791 static const char f32_8
[] =
793 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
794 static const char f32_9
[] =
795 {0x89,0xf6, /* movl %esi,%esi */
796 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
797 static const char f32_10
[] =
798 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
799 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
800 static const char f32_11
[] =
801 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
802 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
803 static const char f32_12
[] =
804 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
805 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
806 static const char f32_13
[] =
807 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
808 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
809 static const char f32_14
[] =
810 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
811 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
812 static const char f16_3
[] =
813 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
814 static const char f16_4
[] =
815 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
816 static const char f16_5
[] =
818 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
819 static const char f16_6
[] =
820 {0x89,0xf6, /* mov %si,%si */
821 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
822 static const char f16_7
[] =
823 {0x8d,0x74,0x00, /* lea 0(%si),%si */
824 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
825 static const char f16_8
[] =
826 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
827 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
828 static const char jump_31
[] =
829 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
830 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
831 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
833 static const char *const f32_patt
[] = {
834 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
835 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
837 static const char *const f16_patt
[] = {
838 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
841 static const char alt_3
[] =
843 /* nopl 0(%[re]ax) */
844 static const char alt_4
[] =
845 {0x0f,0x1f,0x40,0x00};
846 /* nopl 0(%[re]ax,%[re]ax,1) */
847 static const char alt_5
[] =
848 {0x0f,0x1f,0x44,0x00,0x00};
849 /* nopw 0(%[re]ax,%[re]ax,1) */
850 static const char alt_6
[] =
851 {0x66,0x0f,0x1f,0x44,0x00,0x00};
852 /* nopl 0L(%[re]ax) */
853 static const char alt_7
[] =
854 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
855 /* nopl 0L(%[re]ax,%[re]ax,1) */
856 static const char alt_8
[] =
857 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 /* nopw 0L(%[re]ax,%[re]ax,1) */
859 static const char alt_9
[] =
860 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
861 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
862 static const char alt_10
[] =
863 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_long_11
[] =
868 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 nopw %cs:0L(%[re]ax,%[re]ax,1) */
872 static const char alt_long_12
[] =
875 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
879 nopw %cs:0L(%[re]ax,%[re]ax,1) */
880 static const char alt_long_13
[] =
884 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 nopw %cs:0L(%[re]ax,%[re]ax,1) */
890 static const char alt_long_14
[] =
895 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
901 nopw %cs:0L(%[re]ax,%[re]ax,1) */
902 static const char alt_long_15
[] =
908 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
909 /* nopl 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_11
[] =
912 {0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
915 nopw 0(%[re]ax,%[re]ax,1) */
916 static const char alt_short_12
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x66,0x0f,0x1f,0x44,0x00,0x00};
919 /* nopw 0(%[re]ax,%[re]ax,1)
921 static const char alt_short_13
[] =
922 {0x66,0x0f,0x1f,0x44,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
926 static const char alt_short_14
[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
930 nopl 0L(%[re]ax,%[re]ax,1) */
931 static const char alt_short_15
[] =
932 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
933 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
934 static const char *const alt_short_patt
[] = {
935 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
936 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
937 alt_short_14
, alt_short_15
939 static const char *const alt_long_patt
[] = {
940 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
941 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
942 alt_long_14
, alt_long_15
945 /* Only align for at least a positive non-zero boundary. */
946 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
949 /* We need to decide which NOP sequence to use for 32bit and
950 64bit. When -mtune= is used:
952 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
953 PROCESSOR_GENERIC32, f32_patt will be used.
954 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
955 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
956 PROCESSOR_GENERIC64, alt_long_patt will be used.
957 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
958 PROCESSOR_AMDFAM10, alt_short_patt will be used.
960 When -mtune= isn't used, alt_long_patt will be used if
961 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
964 When -march= or .arch is used, we can't use anything beyond
965 cpu_arch_isa_flags. */
967 if (flag_code
== CODE_16BIT
)
971 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
973 /* Adjust jump offset. */
974 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
977 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
978 f16_patt
[count
- 1], count
);
982 const char *const *patt
= NULL
;
984 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
986 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
987 switch (cpu_arch_tune
)
989 case PROCESSOR_UNKNOWN
:
990 /* We use cpu_arch_isa_flags to check if we SHOULD
991 optimize for Cpu686. */
992 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
993 patt
= alt_long_patt
;
997 case PROCESSOR_PENTIUMPRO
:
998 case PROCESSOR_PENTIUM4
:
999 case PROCESSOR_NOCONA
:
1000 case PROCESSOR_CORE
:
1001 case PROCESSOR_CORE2
:
1002 case PROCESSOR_COREI7
:
1003 case PROCESSOR_L1OM
:
1004 case PROCESSOR_GENERIC64
:
1005 patt
= alt_long_patt
;
1008 case PROCESSOR_ATHLON
:
1010 case PROCESSOR_AMDFAM10
:
1011 patt
= alt_short_patt
;
1013 case PROCESSOR_I386
:
1014 case PROCESSOR_I486
:
1015 case PROCESSOR_PENTIUM
:
1016 case PROCESSOR_GENERIC32
:
1023 switch (fragP
->tc_frag_data
.tune
)
1025 case PROCESSOR_UNKNOWN
:
1026 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1027 PROCESSOR_UNKNOWN. */
1031 case PROCESSOR_I386
:
1032 case PROCESSOR_I486
:
1033 case PROCESSOR_PENTIUM
:
1035 case PROCESSOR_ATHLON
:
1037 case PROCESSOR_AMDFAM10
:
1038 case PROCESSOR_GENERIC32
:
1039 /* We use cpu_arch_isa_flags to check if we CAN optimize
1041 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1042 patt
= alt_short_patt
;
1046 case PROCESSOR_PENTIUMPRO
:
1047 case PROCESSOR_PENTIUM4
:
1048 case PROCESSOR_NOCONA
:
1049 case PROCESSOR_CORE
:
1050 case PROCESSOR_CORE2
:
1051 case PROCESSOR_COREI7
:
1052 case PROCESSOR_L1OM
:
1053 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1054 patt
= alt_long_patt
;
1058 case PROCESSOR_GENERIC64
:
1059 patt
= alt_long_patt
;
1064 if (patt
== f32_patt
)
1066 /* If the padding is less than 15 bytes, we use the normal
1067 ones. Otherwise, we use a jump instruction and adjust
1071 /* For 64bit, the limit is 3 bytes. */
1072 if (flag_code
== CODE_64BIT
1073 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1078 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1079 patt
[count
- 1], count
);
1082 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1084 /* Adjust jump offset. */
1085 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1090 /* Maximum length of an instruction is 15 byte. If the
1091 padding is greater than 15 bytes and we don't use jump,
1092 we have to break it into smaller pieces. */
1093 int padding
= count
;
1094 while (padding
> 15)
1097 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1102 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1103 patt
[padding
- 1], padding
);
1106 fragP
->fr_var
= count
;
1110 operand_type_all_zero (const union i386_operand_type
*x
)
1112 switch (ARRAY_SIZE(x
->array
))
1121 return !x
->array
[0];
1128 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1130 switch (ARRAY_SIZE(x
->array
))
1145 operand_type_equal (const union i386_operand_type
*x
,
1146 const union i386_operand_type
*y
)
1148 switch (ARRAY_SIZE(x
->array
))
1151 if (x
->array
[2] != y
->array
[2])
1154 if (x
->array
[1] != y
->array
[1])
1157 return x
->array
[0] == y
->array
[0];
1165 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1167 switch (ARRAY_SIZE(x
->array
))
1176 return !x
->array
[0];
1183 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1185 switch (ARRAY_SIZE(x
->array
))
1200 cpu_flags_equal (const union i386_cpu_flags
*x
,
1201 const union i386_cpu_flags
*y
)
1203 switch (ARRAY_SIZE(x
->array
))
1206 if (x
->array
[2] != y
->array
[2])
1209 if (x
->array
[1] != y
->array
[1])
1212 return x
->array
[0] == y
->array
[0];
1220 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1222 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1223 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1226 static INLINE i386_cpu_flags
1227 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1229 switch (ARRAY_SIZE (x
.array
))
1232 x
.array
[2] &= y
.array
[2];
1234 x
.array
[1] &= y
.array
[1];
1236 x
.array
[0] &= y
.array
[0];
1244 static INLINE i386_cpu_flags
1245 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1247 switch (ARRAY_SIZE (x
.array
))
1250 x
.array
[2] |= y
.array
[2];
1252 x
.array
[1] |= y
.array
[1];
1254 x
.array
[0] |= y
.array
[0];
1262 static INLINE i386_cpu_flags
1263 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1265 switch (ARRAY_SIZE (x
.array
))
1268 x
.array
[2] &= ~y
.array
[2];
1270 x
.array
[1] &= ~y
.array
[1];
1272 x
.array
[0] &= ~y
.array
[0];
1280 #define CPU_FLAGS_ARCH_MATCH 0x1
1281 #define CPU_FLAGS_64BIT_MATCH 0x2
1282 #define CPU_FLAGS_AES_MATCH 0x4
1283 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1284 #define CPU_FLAGS_AVX_MATCH 0x10
1286 #define CPU_FLAGS_32BIT_MATCH \
1287 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1288 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1289 #define CPU_FLAGS_PERFECT_MATCH \
1290 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1292 /* Return CPU flags match bits. */
1295 cpu_flags_match (const insn_template
*t
)
1297 i386_cpu_flags x
= t
->cpu_flags
;
1298 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1300 x
.bitfield
.cpu64
= 0;
1301 x
.bitfield
.cpuno64
= 0;
1303 if (cpu_flags_all_zero (&x
))
1305 /* This instruction is available on all archs. */
1306 match
|= CPU_FLAGS_32BIT_MATCH
;
1310 /* This instruction is available only on some archs. */
1311 i386_cpu_flags cpu
= cpu_arch_flags
;
1313 cpu
.bitfield
.cpu64
= 0;
1314 cpu
.bitfield
.cpuno64
= 0;
1315 cpu
= cpu_flags_and (x
, cpu
);
1316 if (!cpu_flags_all_zero (&cpu
))
1318 if (x
.bitfield
.cpuavx
)
1320 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1321 if (cpu
.bitfield
.cpuavx
)
1323 /* Check SSE2AVX. */
1324 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1326 match
|= (CPU_FLAGS_ARCH_MATCH
1327 | CPU_FLAGS_AVX_MATCH
);
1329 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1330 match
|= CPU_FLAGS_AES_MATCH
;
1332 if (!x
.bitfield
.cpupclmul
1333 || cpu
.bitfield
.cpupclmul
)
1334 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1338 match
|= CPU_FLAGS_ARCH_MATCH
;
1341 match
|= CPU_FLAGS_32BIT_MATCH
;
1347 static INLINE i386_operand_type
1348 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1350 switch (ARRAY_SIZE (x
.array
))
1353 x
.array
[2] &= y
.array
[2];
1355 x
.array
[1] &= y
.array
[1];
1357 x
.array
[0] &= y
.array
[0];
1365 static INLINE i386_operand_type
1366 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1368 switch (ARRAY_SIZE (x
.array
))
1371 x
.array
[2] |= y
.array
[2];
1373 x
.array
[1] |= y
.array
[1];
1375 x
.array
[0] |= y
.array
[0];
1383 static INLINE i386_operand_type
1384 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1386 switch (ARRAY_SIZE (x
.array
))
1389 x
.array
[2] ^= y
.array
[2];
1391 x
.array
[1] ^= y
.array
[1];
1393 x
.array
[0] ^= y
.array
[0];
1401 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1402 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1403 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1404 static const i386_operand_type inoutportreg
1405 = OPERAND_TYPE_INOUTPORTREG
;
1406 static const i386_operand_type reg16_inoutportreg
1407 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1408 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1409 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1410 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1411 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1412 static const i386_operand_type anydisp
1413 = OPERAND_TYPE_ANYDISP
;
1414 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1415 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1416 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1417 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1418 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1419 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1420 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1421 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1422 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1423 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1424 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1435 operand_type_check (i386_operand_type t
, enum operand_type c
)
1440 return (t
.bitfield
.reg8
1443 || t
.bitfield
.reg64
);
1446 return (t
.bitfield
.imm8
1450 || t
.bitfield
.imm32s
1451 || t
.bitfield
.imm64
);
1454 return (t
.bitfield
.disp8
1455 || t
.bitfield
.disp16
1456 || t
.bitfield
.disp32
1457 || t
.bitfield
.disp32s
1458 || t
.bitfield
.disp64
);
1461 return (t
.bitfield
.disp8
1462 || t
.bitfield
.disp16
1463 || t
.bitfield
.disp32
1464 || t
.bitfield
.disp32s
1465 || t
.bitfield
.disp64
1466 || t
.bitfield
.baseindex
);
1475 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1476 operand J for instruction template T. */
1479 match_reg_size (const insn_template
*t
, unsigned int j
)
1481 return !((i
.types
[j
].bitfield
.byte
1482 && !t
->operand_types
[j
].bitfield
.byte
)
1483 || (i
.types
[j
].bitfield
.word
1484 && !t
->operand_types
[j
].bitfield
.word
)
1485 || (i
.types
[j
].bitfield
.dword
1486 && !t
->operand_types
[j
].bitfield
.dword
)
1487 || (i
.types
[j
].bitfield
.qword
1488 && !t
->operand_types
[j
].bitfield
.qword
));
1491 /* Return 1 if there is no conflict in any size on operand J for
1492 instruction template T. */
1495 match_mem_size (const insn_template
*t
, unsigned int j
)
1497 return (match_reg_size (t
, j
)
1498 && !((i
.types
[j
].bitfield
.unspecified
1499 && !t
->operand_types
[j
].bitfield
.unspecified
)
1500 || (i
.types
[j
].bitfield
.fword
1501 && !t
->operand_types
[j
].bitfield
.fword
)
1502 || (i
.types
[j
].bitfield
.tbyte
1503 && !t
->operand_types
[j
].bitfield
.tbyte
)
1504 || (i
.types
[j
].bitfield
.xmmword
1505 && !t
->operand_types
[j
].bitfield
.xmmword
)
1506 || (i
.types
[j
].bitfield
.ymmword
1507 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1510 /* Return 1 if there is no size conflict on any operands for
1511 instruction template T. */
1514 operand_size_match (const insn_template
*t
)
1519 /* Don't check jump instructions. */
1520 if (t
->opcode_modifier
.jump
1521 || t
->opcode_modifier
.jumpbyte
1522 || t
->opcode_modifier
.jumpdword
1523 || t
->opcode_modifier
.jumpintersegment
)
1526 /* Check memory and accumulator operand size. */
1527 for (j
= 0; j
< i
.operands
; j
++)
1529 if (t
->operand_types
[j
].bitfield
.anysize
)
1532 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1538 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1546 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1549 /* Check reverse. */
1550 gas_assert (i
.operands
== 2);
1553 for (j
= 0; j
< 2; j
++)
1555 if (t
->operand_types
[j
].bitfield
.acc
1556 && !match_reg_size (t
, j
? 0 : 1))
1562 if (i
.types
[j
].bitfield
.mem
1563 && !match_mem_size (t
, j
? 0 : 1))
1574 operand_type_match (i386_operand_type overlap
,
1575 i386_operand_type given
)
1577 i386_operand_type temp
= overlap
;
1579 temp
.bitfield
.jumpabsolute
= 0;
1580 temp
.bitfield
.unspecified
= 0;
1581 temp
.bitfield
.byte
= 0;
1582 temp
.bitfield
.word
= 0;
1583 temp
.bitfield
.dword
= 0;
1584 temp
.bitfield
.fword
= 0;
1585 temp
.bitfield
.qword
= 0;
1586 temp
.bitfield
.tbyte
= 0;
1587 temp
.bitfield
.xmmword
= 0;
1588 temp
.bitfield
.ymmword
= 0;
1589 if (operand_type_all_zero (&temp
))
1592 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1593 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1596 /* If given types g0 and g1 are registers they must be of the same type
1597 unless the expected operand type register overlap is null.
1598 Note that Acc in a template matches every size of reg. */
1601 operand_type_register_match (i386_operand_type m0
,
1602 i386_operand_type g0
,
1603 i386_operand_type t0
,
1604 i386_operand_type m1
,
1605 i386_operand_type g1
,
1606 i386_operand_type t1
)
1608 if (!operand_type_check (g0
, reg
))
1611 if (!operand_type_check (g1
, reg
))
1614 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1615 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1616 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1617 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1620 if (m0
.bitfield
.acc
)
1622 t0
.bitfield
.reg8
= 1;
1623 t0
.bitfield
.reg16
= 1;
1624 t0
.bitfield
.reg32
= 1;
1625 t0
.bitfield
.reg64
= 1;
1628 if (m1
.bitfield
.acc
)
1630 t1
.bitfield
.reg8
= 1;
1631 t1
.bitfield
.reg16
= 1;
1632 t1
.bitfield
.reg32
= 1;
1633 t1
.bitfield
.reg64
= 1;
1636 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1637 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1638 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1639 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1642 static INLINE
unsigned int
1643 mode_from_disp_size (i386_operand_type t
)
1645 if (t
.bitfield
.disp8
)
1647 else if (t
.bitfield
.disp16
1648 || t
.bitfield
.disp32
1649 || t
.bitfield
.disp32s
)
1656 fits_in_signed_byte (offsetT num
)
1658 return (num
>= -128) && (num
<= 127);
1662 fits_in_unsigned_byte (offsetT num
)
1664 return (num
& 0xff) == num
;
1668 fits_in_unsigned_word (offsetT num
)
1670 return (num
& 0xffff) == num
;
1674 fits_in_signed_word (offsetT num
)
1676 return (-32768 <= num
) && (num
<= 32767);
1680 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1685 return (!(((offsetT
) -1 << 31) & num
)
1686 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1688 } /* fits_in_signed_long() */
1691 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1696 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1698 } /* fits_in_unsigned_long() */
1700 static i386_operand_type
1701 smallest_imm_type (offsetT num
)
1703 i386_operand_type t
;
1705 operand_type_set (&t
, 0);
1706 t
.bitfield
.imm64
= 1;
1708 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1710 /* This code is disabled on the 486 because all the Imm1 forms
1711 in the opcode table are slower on the i486. They're the
1712 versions with the implicitly specified single-position
1713 displacement, which has another syntax if you really want to
1715 t
.bitfield
.imm1
= 1;
1716 t
.bitfield
.imm8
= 1;
1717 t
.bitfield
.imm8s
= 1;
1718 t
.bitfield
.imm16
= 1;
1719 t
.bitfield
.imm32
= 1;
1720 t
.bitfield
.imm32s
= 1;
1722 else if (fits_in_signed_byte (num
))
1724 t
.bitfield
.imm8
= 1;
1725 t
.bitfield
.imm8s
= 1;
1726 t
.bitfield
.imm16
= 1;
1727 t
.bitfield
.imm32
= 1;
1728 t
.bitfield
.imm32s
= 1;
1730 else if (fits_in_unsigned_byte (num
))
1732 t
.bitfield
.imm8
= 1;
1733 t
.bitfield
.imm16
= 1;
1734 t
.bitfield
.imm32
= 1;
1735 t
.bitfield
.imm32s
= 1;
1737 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1739 t
.bitfield
.imm16
= 1;
1740 t
.bitfield
.imm32
= 1;
1741 t
.bitfield
.imm32s
= 1;
1743 else if (fits_in_signed_long (num
))
1745 t
.bitfield
.imm32
= 1;
1746 t
.bitfield
.imm32s
= 1;
1748 else if (fits_in_unsigned_long (num
))
1749 t
.bitfield
.imm32
= 1;
1755 offset_in_range (offsetT val
, int size
)
1761 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1762 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1763 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1765 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1771 /* If BFD64, sign extend val for 32bit address mode. */
1772 if (flag_code
!= CODE_64BIT
1773 || i
.prefix
[ADDR_PREFIX
])
1774 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1775 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1778 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1780 char buf1
[40], buf2
[40];
1782 sprint_value (buf1
, val
);
1783 sprint_value (buf2
, val
& mask
);
1784 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1798 a. PREFIX_EXIST if attempting to add a prefix where one from the
1799 same class already exists.
1800 b. PREFIX_LOCK if lock prefix is added.
1801 c. PREFIX_REP if rep/repne prefix is added.
1802 d. PREFIX_OTHER if other prefix is added.
1805 static enum PREFIX_GROUP
1806 add_prefix (unsigned int prefix
)
1808 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1811 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1812 && flag_code
== CODE_64BIT
)
1814 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1815 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1816 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1827 case CS_PREFIX_OPCODE
:
1828 case DS_PREFIX_OPCODE
:
1829 case ES_PREFIX_OPCODE
:
1830 case FS_PREFIX_OPCODE
:
1831 case GS_PREFIX_OPCODE
:
1832 case SS_PREFIX_OPCODE
:
1836 case REPNE_PREFIX_OPCODE
:
1837 case REPE_PREFIX_OPCODE
:
1842 case LOCK_PREFIX_OPCODE
:
1851 case ADDR_PREFIX_OPCODE
:
1855 case DATA_PREFIX_OPCODE
:
1859 if (i
.prefix
[q
] != 0)
1867 i
.prefix
[q
] |= prefix
;
1870 as_bad (_("same type of prefix used twice"));
1876 set_code_flag (int value
)
1878 flag_code
= (enum flag_code
) value
;
1879 if (flag_code
== CODE_64BIT
)
1881 cpu_arch_flags
.bitfield
.cpu64
= 1;
1882 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1886 cpu_arch_flags
.bitfield
.cpu64
= 0;
1887 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1889 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1891 as_bad (_("64bit mode not supported on this CPU."));
1893 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1895 as_bad (_("32bit mode not supported on this CPU."));
1897 stackop_size
= '\0';
1901 set_16bit_gcc_code_flag (int new_code_flag
)
1903 flag_code
= (enum flag_code
) new_code_flag
;
1904 if (flag_code
!= CODE_16BIT
)
1906 cpu_arch_flags
.bitfield
.cpu64
= 0;
1907 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1908 stackop_size
= LONG_MNEM_SUFFIX
;
1912 set_intel_syntax (int syntax_flag
)
1914 /* Find out if register prefixing is specified. */
1915 int ask_naked_reg
= 0;
1918 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1920 char *string
= input_line_pointer
;
1921 int e
= get_symbol_end ();
1923 if (strcmp (string
, "prefix") == 0)
1925 else if (strcmp (string
, "noprefix") == 0)
1928 as_bad (_("bad argument to syntax directive."));
1929 *input_line_pointer
= e
;
1931 demand_empty_rest_of_line ();
1933 intel_syntax
= syntax_flag
;
1935 if (ask_naked_reg
== 0)
1936 allow_naked_reg
= (intel_syntax
1937 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1939 allow_naked_reg
= (ask_naked_reg
< 0);
1941 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1943 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1944 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1945 register_prefix
= allow_naked_reg
? "" : "%";
1949 set_intel_mnemonic (int mnemonic_flag
)
1951 intel_mnemonic
= mnemonic_flag
;
1955 set_allow_index_reg (int flag
)
1957 allow_index_reg
= flag
;
1961 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1965 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1967 char *string
= input_line_pointer
;
1968 int e
= get_symbol_end ();
1970 if (strcmp (string
, "none") == 0)
1971 sse_check
= sse_check_none
;
1972 else if (strcmp (string
, "warning") == 0)
1973 sse_check
= sse_check_warning
;
1974 else if (strcmp (string
, "error") == 0)
1975 sse_check
= sse_check_error
;
1977 as_bad (_("bad argument to sse_check directive."));
1978 *input_line_pointer
= e
;
1981 as_bad (_("missing argument for sse_check directive"));
1983 demand_empty_rest_of_line ();
1987 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1988 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1990 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1991 static const char *arch
;
1993 /* Intel LIOM is only supported on ELF. */
1999 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2000 use default_arch. */
2001 arch
= cpu_arch_name
;
2003 arch
= default_arch
;
2006 /* If we are targeting Intel L1OM, we must enable it. */
2007 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2008 || new_flag
.bitfield
.cpul1om
)
2011 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2016 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2020 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2022 char *string
= input_line_pointer
;
2023 int e
= get_symbol_end ();
2025 i386_cpu_flags flags
;
2027 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2029 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2031 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2035 cpu_arch_name
= cpu_arch
[i
].name
;
2036 cpu_sub_arch_name
= NULL
;
2037 cpu_arch_flags
= cpu_arch
[i
].flags
;
2038 if (flag_code
== CODE_64BIT
)
2040 cpu_arch_flags
.bitfield
.cpu64
= 1;
2041 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2045 cpu_arch_flags
.bitfield
.cpu64
= 0;
2046 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2048 cpu_arch_isa
= cpu_arch
[i
].type
;
2049 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2050 if (!cpu_arch_tune_set
)
2052 cpu_arch_tune
= cpu_arch_isa
;
2053 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2058 if (strncmp (string
+ 1, "no", 2))
2059 flags
= cpu_flags_or (cpu_arch_flags
,
2062 flags
= cpu_flags_and_not (cpu_arch_flags
,
2064 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2066 if (cpu_sub_arch_name
)
2068 char *name
= cpu_sub_arch_name
;
2069 cpu_sub_arch_name
= concat (name
,
2071 (const char *) NULL
);
2075 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2076 cpu_arch_flags
= flags
;
2078 *input_line_pointer
= e
;
2079 demand_empty_rest_of_line ();
2083 if (i
>= ARRAY_SIZE (cpu_arch
))
2084 as_bad (_("no such architecture: `%s'"), string
);
2086 *input_line_pointer
= e
;
2089 as_bad (_("missing cpu architecture"));
2091 no_cond_jump_promotion
= 0;
2092 if (*input_line_pointer
== ','
2093 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2095 char *string
= ++input_line_pointer
;
2096 int e
= get_symbol_end ();
2098 if (strcmp (string
, "nojumps") == 0)
2099 no_cond_jump_promotion
= 1;
2100 else if (strcmp (string
, "jumps") == 0)
2103 as_bad (_("no such architecture modifier: `%s'"), string
);
2105 *input_line_pointer
= e
;
2108 demand_empty_rest_of_line ();
2111 enum bfd_architecture
2114 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2116 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2117 || flag_code
!= CODE_64BIT
)
2118 as_fatal (_("Intel L1OM is 64bit ELF only"));
2119 return bfd_arch_l1om
;
2122 return bfd_arch_i386
;
2128 if (!strcmp (default_arch
, "x86_64"))
2130 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2132 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2133 as_fatal (_("Intel L1OM is 64bit ELF only"));
2134 return bfd_mach_l1om
;
2137 return bfd_mach_x86_64
;
2139 else if (!strcmp (default_arch
, "i386"))
2140 return bfd_mach_i386_i386
;
2142 as_fatal (_("Unknown architecture"));
2148 const char *hash_err
;
2150 /* Initialize op_hash hash table. */
2151 op_hash
= hash_new ();
2154 const insn_template
*optab
;
2155 templates
*core_optab
;
2157 /* Setup for loop. */
2159 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2160 core_optab
->start
= optab
;
2165 if (optab
->name
== NULL
2166 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2168 /* different name --> ship out current template list;
2169 add to hash table; & begin anew. */
2170 core_optab
->end
= optab
;
2171 hash_err
= hash_insert (op_hash
,
2173 (void *) core_optab
);
2176 as_fatal (_("Internal Error: Can't hash %s: %s"),
2180 if (optab
->name
== NULL
)
2182 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2183 core_optab
->start
= optab
;
2188 /* Initialize reg_hash hash table. */
2189 reg_hash
= hash_new ();
2191 const reg_entry
*regtab
;
2192 unsigned int regtab_size
= i386_regtab_size
;
2194 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2196 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2198 as_fatal (_("Internal Error: Can't hash %s: %s"),
2204 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2209 for (c
= 0; c
< 256; c
++)
2214 mnemonic_chars
[c
] = c
;
2215 register_chars
[c
] = c
;
2216 operand_chars
[c
] = c
;
2218 else if (ISLOWER (c
))
2220 mnemonic_chars
[c
] = c
;
2221 register_chars
[c
] = c
;
2222 operand_chars
[c
] = c
;
2224 else if (ISUPPER (c
))
2226 mnemonic_chars
[c
] = TOLOWER (c
);
2227 register_chars
[c
] = mnemonic_chars
[c
];
2228 operand_chars
[c
] = c
;
2231 if (ISALPHA (c
) || ISDIGIT (c
))
2232 identifier_chars
[c
] = c
;
2235 identifier_chars
[c
] = c
;
2236 operand_chars
[c
] = c
;
2241 identifier_chars
['@'] = '@';
2244 identifier_chars
['?'] = '?';
2245 operand_chars
['?'] = '?';
2247 digit_chars
['-'] = '-';
2248 mnemonic_chars
['_'] = '_';
2249 mnemonic_chars
['-'] = '-';
2250 mnemonic_chars
['.'] = '.';
2251 identifier_chars
['_'] = '_';
2252 identifier_chars
['.'] = '.';
2254 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2255 operand_chars
[(unsigned char) *p
] = *p
;
2258 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2261 record_alignment (text_section
, 2);
2262 record_alignment (data_section
, 2);
2263 record_alignment (bss_section
, 2);
2267 if (flag_code
== CODE_64BIT
)
2269 x86_dwarf2_return_column
= 16;
2270 x86_cie_data_alignment
= -8;
2274 x86_dwarf2_return_column
= 8;
2275 x86_cie_data_alignment
= -4;
2280 i386_print_statistics (FILE *file
)
2282 hash_print_statistics (file
, "i386 opcode", op_hash
);
2283 hash_print_statistics (file
, "i386 register", reg_hash
);
2288 /* Debugging routines for md_assemble. */
2289 static void pte (insn_template
*);
2290 static void pt (i386_operand_type
);
2291 static void pe (expressionS
*);
2292 static void ps (symbolS
*);
2295 pi (char *line
, i386_insn
*x
)
2299 fprintf (stdout
, "%s: template ", line
);
2301 fprintf (stdout
, " address: base %s index %s scale %x\n",
2302 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2303 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2304 x
->log2_scale_factor
);
2305 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2306 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2307 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2308 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2309 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2310 (x
->rex
& REX_W
) != 0,
2311 (x
->rex
& REX_R
) != 0,
2312 (x
->rex
& REX_X
) != 0,
2313 (x
->rex
& REX_B
) != 0);
2314 for (i
= 0; i
< x
->operands
; i
++)
2316 fprintf (stdout
, " #%d: ", i
+ 1);
2318 fprintf (stdout
, "\n");
2319 if (x
->types
[i
].bitfield
.reg8
2320 || x
->types
[i
].bitfield
.reg16
2321 || x
->types
[i
].bitfield
.reg32
2322 || x
->types
[i
].bitfield
.reg64
2323 || x
->types
[i
].bitfield
.regmmx
2324 || x
->types
[i
].bitfield
.regxmm
2325 || x
->types
[i
].bitfield
.regymm
2326 || x
->types
[i
].bitfield
.sreg2
2327 || x
->types
[i
].bitfield
.sreg3
2328 || x
->types
[i
].bitfield
.control
2329 || x
->types
[i
].bitfield
.debug
2330 || x
->types
[i
].bitfield
.test
)
2331 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2332 if (operand_type_check (x
->types
[i
], imm
))
2334 if (operand_type_check (x
->types
[i
], disp
))
2335 pe (x
->op
[i
].disps
);
2340 pte (insn_template
*t
)
2343 fprintf (stdout
, " %d operands ", t
->operands
);
2344 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2345 if (t
->extension_opcode
!= None
)
2346 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2347 if (t
->opcode_modifier
.d
)
2348 fprintf (stdout
, "D");
2349 if (t
->opcode_modifier
.w
)
2350 fprintf (stdout
, "W");
2351 fprintf (stdout
, "\n");
2352 for (i
= 0; i
< t
->operands
; i
++)
2354 fprintf (stdout
, " #%d type ", i
+ 1);
2355 pt (t
->operand_types
[i
]);
2356 fprintf (stdout
, "\n");
2363 fprintf (stdout
, " operation %d\n", e
->X_op
);
2364 fprintf (stdout
, " add_number %ld (%lx)\n",
2365 (long) e
->X_add_number
, (long) e
->X_add_number
);
2366 if (e
->X_add_symbol
)
2368 fprintf (stdout
, " add_symbol ");
2369 ps (e
->X_add_symbol
);
2370 fprintf (stdout
, "\n");
2374 fprintf (stdout
, " op_symbol ");
2375 ps (e
->X_op_symbol
);
2376 fprintf (stdout
, "\n");
2383 fprintf (stdout
, "%s type %s%s",
2385 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2386 segment_name (S_GET_SEGMENT (s
)));
2389 static struct type_name
2391 i386_operand_type mask
;
2394 const type_names
[] =
2396 { OPERAND_TYPE_REG8
, "r8" },
2397 { OPERAND_TYPE_REG16
, "r16" },
2398 { OPERAND_TYPE_REG32
, "r32" },
2399 { OPERAND_TYPE_REG64
, "r64" },
2400 { OPERAND_TYPE_IMM8
, "i8" },
2401 { OPERAND_TYPE_IMM8
, "i8s" },
2402 { OPERAND_TYPE_IMM16
, "i16" },
2403 { OPERAND_TYPE_IMM32
, "i32" },
2404 { OPERAND_TYPE_IMM32S
, "i32s" },
2405 { OPERAND_TYPE_IMM64
, "i64" },
2406 { OPERAND_TYPE_IMM1
, "i1" },
2407 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2408 { OPERAND_TYPE_DISP8
, "d8" },
2409 { OPERAND_TYPE_DISP16
, "d16" },
2410 { OPERAND_TYPE_DISP32
, "d32" },
2411 { OPERAND_TYPE_DISP32S
, "d32s" },
2412 { OPERAND_TYPE_DISP64
, "d64" },
2413 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2414 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2415 { OPERAND_TYPE_CONTROL
, "control reg" },
2416 { OPERAND_TYPE_TEST
, "test reg" },
2417 { OPERAND_TYPE_DEBUG
, "debug reg" },
2418 { OPERAND_TYPE_FLOATREG
, "FReg" },
2419 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2420 { OPERAND_TYPE_SREG2
, "SReg2" },
2421 { OPERAND_TYPE_SREG3
, "SReg3" },
2422 { OPERAND_TYPE_ACC
, "Acc" },
2423 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2424 { OPERAND_TYPE_REGMMX
, "rMMX" },
2425 { OPERAND_TYPE_REGXMM
, "rXMM" },
2426 { OPERAND_TYPE_REGYMM
, "rYMM" },
2427 { OPERAND_TYPE_ESSEG
, "es" },
2431 pt (i386_operand_type t
)
2434 i386_operand_type a
;
2436 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2438 a
= operand_type_and (t
, type_names
[j
].mask
);
2439 if (!operand_type_all_zero (&a
))
2440 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2445 #endif /* DEBUG386 */
2447 static bfd_reloc_code_real_type
2448 reloc (unsigned int size
,
2451 bfd_reloc_code_real_type other
)
2453 if (other
!= NO_RELOC
)
2455 reloc_howto_type
*reloc
;
2460 case BFD_RELOC_X86_64_GOT32
:
2461 return BFD_RELOC_X86_64_GOT64
;
2463 case BFD_RELOC_X86_64_PLTOFF64
:
2464 return BFD_RELOC_X86_64_PLTOFF64
;
2466 case BFD_RELOC_X86_64_GOTPC32
:
2467 other
= BFD_RELOC_X86_64_GOTPC64
;
2469 case BFD_RELOC_X86_64_GOTPCREL
:
2470 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2472 case BFD_RELOC_X86_64_TPOFF32
:
2473 other
= BFD_RELOC_X86_64_TPOFF64
;
2475 case BFD_RELOC_X86_64_DTPOFF32
:
2476 other
= BFD_RELOC_X86_64_DTPOFF64
;
2482 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2483 if (size
== 4 && flag_code
!= CODE_64BIT
)
2486 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2488 as_bad (_("unknown relocation (%u)"), other
);
2489 else if (size
!= bfd_get_reloc_size (reloc
))
2490 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2491 bfd_get_reloc_size (reloc
),
2493 else if (pcrel
&& !reloc
->pc_relative
)
2494 as_bad (_("non-pc-relative relocation for pc-relative field"));
2495 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2497 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2499 as_bad (_("relocated field and relocation type differ in signedness"));
2508 as_bad (_("there are no unsigned pc-relative relocations"));
2511 case 1: return BFD_RELOC_8_PCREL
;
2512 case 2: return BFD_RELOC_16_PCREL
;
2513 case 4: return BFD_RELOC_32_PCREL
;
2514 case 8: return BFD_RELOC_64_PCREL
;
2516 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2523 case 4: return BFD_RELOC_X86_64_32S
;
2528 case 1: return BFD_RELOC_8
;
2529 case 2: return BFD_RELOC_16
;
2530 case 4: return BFD_RELOC_32
;
2531 case 8: return BFD_RELOC_64
;
2533 as_bad (_("cannot do %s %u byte relocation"),
2534 sign
> 0 ? "signed" : "unsigned", size
);
2540 /* Here we decide which fixups can be adjusted to make them relative to
2541 the beginning of the section instead of the symbol. Basically we need
2542 to make sure that the dynamic relocations are done correctly, so in
2543 some cases we force the original symbol to be used. */
2546 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2548 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2552 /* Don't adjust pc-relative references to merge sections in 64-bit
2554 if (use_rela_relocations
2555 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2559 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2560 and changed later by validate_fix. */
2561 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2562 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2565 /* adjust_reloc_syms doesn't know about the GOT. */
2566 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2567 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2568 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2569 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2570 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2574 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2575 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2576 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2577 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2578 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2579 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2580 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2590 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2591 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2592 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2593 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2600 intel_float_operand (const char *mnemonic
)
2602 /* Note that the value returned is meaningful only for opcodes with (memory)
2603 operands, hence the code here is free to improperly handle opcodes that
2604 have no operands (for better performance and smaller code). */
2606 if (mnemonic
[0] != 'f')
2607 return 0; /* non-math */
2609 switch (mnemonic
[1])
2611 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2612 the fs segment override prefix not currently handled because no
2613 call path can make opcodes without operands get here */
2615 return 2 /* integer op */;
2617 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2618 return 3; /* fldcw/fldenv */
2621 if (mnemonic
[2] != 'o' /* fnop */)
2622 return 3; /* non-waiting control op */
2625 if (mnemonic
[2] == 's')
2626 return 3; /* frstor/frstpm */
2629 if (mnemonic
[2] == 'a')
2630 return 3; /* fsave */
2631 if (mnemonic
[2] == 't')
2633 switch (mnemonic
[3])
2635 case 'c': /* fstcw */
2636 case 'd': /* fstdw */
2637 case 'e': /* fstenv */
2638 case 's': /* fsts[gw] */
2644 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2645 return 0; /* fxsave/fxrstor are not really math ops */
2652 /* Build the VEX prefix. */
2655 build_vex_prefix (const insn_template
*t
)
2657 unsigned int register_specifier
;
2658 unsigned int implied_prefix
;
2659 unsigned int vector_length
;
2661 /* Check register specifier. */
2662 if (i
.vex
.register_specifier
)
2664 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2665 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2666 register_specifier
+= 8;
2667 register_specifier
= ~register_specifier
& 0xf;
2670 register_specifier
= 0xf;
2672 /* Use 2-byte VEX prefix by swappping destination and source
2675 && i
.operands
== i
.reg_operands
2676 && i
.tm
.opcode_modifier
.vex0f
2677 && i
.tm
.opcode_modifier
.s
2680 unsigned int xchg
= i
.operands
- 1;
2681 union i386_op temp_op
;
2682 i386_operand_type temp_type
;
2684 temp_type
= i
.types
[xchg
];
2685 i
.types
[xchg
] = i
.types
[0];
2686 i
.types
[0] = temp_type
;
2687 temp_op
= i
.op
[xchg
];
2688 i
.op
[xchg
] = i
.op
[0];
2691 gas_assert (i
.rm
.mode
== 3);
2695 i
.rm
.regmem
= i
.rm
.reg
;
2698 /* Use the next insn. */
2702 vector_length
= i
.tm
.opcode_modifier
.vex
== 2 ? 1 : 0;
2704 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2709 case DATA_PREFIX_OPCODE
:
2712 case REPE_PREFIX_OPCODE
:
2715 case REPNE_PREFIX_OPCODE
:
2722 /* Use 2-byte VEX prefix if possible. */
2723 if (i
.tm
.opcode_modifier
.vex0f
2724 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2726 /* 2-byte VEX prefix. */
2730 i
.vex
.bytes
[0] = 0xc5;
2732 /* Check the REX.R bit. */
2733 r
= (i
.rex
& REX_R
) ? 0 : 1;
2734 i
.vex
.bytes
[1] = (r
<< 7
2735 | register_specifier
<< 3
2736 | vector_length
<< 2
2741 /* 3-byte VEX prefix. */
2745 i
.vex
.bytes
[0] = 0xc4;
2747 if (i
.tm
.opcode_modifier
.vex0f
)
2749 else if (i
.tm
.opcode_modifier
.vex0f38
)
2751 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2753 else if (i
.tm
.opcode_modifier
.xop08
)
2756 i
.vex
.bytes
[0] = 0x8f;
2758 else if (i
.tm
.opcode_modifier
.xop09
)
2761 i
.vex
.bytes
[0] = 0x8f;
2763 else if (i
.tm
.opcode_modifier
.xop0a
)
2766 i
.vex
.bytes
[0] = 0x8f;
2771 /* The high 3 bits of the second VEX byte are 1's compliment
2772 of RXB bits from REX. */
2773 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2775 /* Check the REX.W bit. */
2776 w
= (i
.rex
& REX_W
) ? 1 : 0;
2777 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2782 if (i
.tm
.opcode_modifier
.vexw1
)
2786 i
.vex
.bytes
[2] = (w
<< 7
2787 | register_specifier
<< 3
2788 | vector_length
<< 2
2794 process_immext (void)
2798 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2800 /* SSE3 Instructions have the fixed operands with an opcode
2801 suffix which is coded in the same place as an 8-bit immediate
2802 field would be. Here we check those operands and remove them
2806 for (x
= 0; x
< i
.operands
; x
++)
2807 if (i
.op
[x
].regs
->reg_num
!= x
)
2808 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2809 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2815 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2816 which is coded in the same place as an 8-bit immediate field
2817 would be. Here we fake an 8-bit immediate operand from the
2818 opcode suffix stored in tm.extension_opcode.
2820 AVX instructions also use this encoding, for some of
2821 3 argument instructions. */
2823 gas_assert (i
.imm_operands
== 0
2825 || (i
.tm
.opcode_modifier
.vex
2826 && i
.operands
<= 4)));
2828 exp
= &im_expressions
[i
.imm_operands
++];
2829 i
.op
[i
.operands
].imms
= exp
;
2830 i
.types
[i
.operands
] = imm8
;
2832 exp
->X_op
= O_constant
;
2833 exp
->X_add_number
= i
.tm
.extension_opcode
;
2834 i
.tm
.extension_opcode
= None
;
2837 /* This is the guts of the machine-dependent assembler. LINE points to a
2838 machine dependent instruction. This function is supposed to emit
2839 the frags/bytes it assembles to. */
2842 md_assemble (char *line
)
2845 char mnemonic
[MAX_MNEM_SIZE
];
2846 const insn_template
*t
;
2848 /* Initialize globals. */
2849 memset (&i
, '\0', sizeof (i
));
2850 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2851 i
.reloc
[j
] = NO_RELOC
;
2852 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2853 memset (im_expressions
, '\0', sizeof (im_expressions
));
2854 save_stack_p
= save_stack
;
2856 /* First parse an instruction mnemonic & call i386_operand for the operands.
2857 We assume that the scrubber has arranged it so that line[0] is the valid
2858 start of a (possibly prefixed) mnemonic. */
2860 line
= parse_insn (line
, mnemonic
);
2864 line
= parse_operands (line
, mnemonic
);
2869 /* Now we've parsed the mnemonic into a set of templates, and have the
2870 operands at hand. */
2872 /* All intel opcodes have reversed operands except for "bound" and
2873 "enter". We also don't reverse intersegment "jmp" and "call"
2874 instructions with 2 immediate operands so that the immediate segment
2875 precedes the offset, as it does when in AT&T mode. */
2878 && (strcmp (mnemonic
, "bound") != 0)
2879 && (strcmp (mnemonic
, "invlpga") != 0)
2880 && !(operand_type_check (i
.types
[0], imm
)
2881 && operand_type_check (i
.types
[1], imm
)))
2884 /* The order of the immediates should be reversed
2885 for 2 immediates extrq and insertq instructions */
2886 if (i
.imm_operands
== 2
2887 && (strcmp (mnemonic
, "extrq") == 0
2888 || strcmp (mnemonic
, "insertq") == 0))
2889 swap_2_operands (0, 1);
2894 /* Don't optimize displacement for movabs since it only takes 64bit
2897 && (flag_code
!= CODE_64BIT
2898 || strcmp (mnemonic
, "movabs") != 0))
2901 /* Next, we find a template that matches the given insn,
2902 making sure the overlap of the given operands types is consistent
2903 with the template operand types. */
2905 if (!(t
= match_template ()))
2908 if (sse_check
!= sse_check_none
2909 && !i
.tm
.opcode_modifier
.noavx
2910 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2911 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2912 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2913 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2914 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2915 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2917 (sse_check
== sse_check_warning
2919 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2922 /* Zap movzx and movsx suffix. The suffix has been set from
2923 "word ptr" or "byte ptr" on the source operand in Intel syntax
2924 or extracted from mnemonic in AT&T syntax. But we'll use
2925 the destination register to choose the suffix for encoding. */
2926 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2928 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2929 there is no suffix, the default will be byte extension. */
2930 if (i
.reg_operands
!= 2
2933 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2938 if (i
.tm
.opcode_modifier
.fwait
)
2939 if (!add_prefix (FWAIT_OPCODE
))
2942 /* Check for lock without a lockable instruction. Destination operand
2943 must be memory unless it is xchg (0x86). */
2944 if (i
.prefix
[LOCK_PREFIX
]
2945 && (!i
.tm
.opcode_modifier
.islockable
2946 || i
.mem_operands
== 0
2947 || (i
.tm
.base_opcode
!= 0x86
2948 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2950 as_bad (_("expecting lockable instruction after `lock'"));
2954 /* Check string instruction segment overrides. */
2955 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2957 if (!check_string ())
2959 i
.disp_operands
= 0;
2962 if (!process_suffix ())
2965 /* Update operand types. */
2966 for (j
= 0; j
< i
.operands
; j
++)
2967 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2969 /* Make still unresolved immediate matches conform to size of immediate
2970 given in i.suffix. */
2971 if (!finalize_imm ())
2974 if (i
.types
[0].bitfield
.imm1
)
2975 i
.imm_operands
= 0; /* kludge for shift insns. */
2977 /* We only need to check those implicit registers for instructions
2978 with 3 operands or less. */
2979 if (i
.operands
<= 3)
2980 for (j
= 0; j
< i
.operands
; j
++)
2981 if (i
.types
[j
].bitfield
.inoutportreg
2982 || i
.types
[j
].bitfield
.shiftcount
2983 || i
.types
[j
].bitfield
.acc
2984 || i
.types
[j
].bitfield
.floatacc
)
2987 /* ImmExt should be processed after SSE2AVX. */
2988 if (!i
.tm
.opcode_modifier
.sse2avx
2989 && i
.tm
.opcode_modifier
.immext
)
2992 /* For insns with operands there are more diddles to do to the opcode. */
2995 if (!process_operands ())
2998 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3000 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3001 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3004 if (i
.tm
.opcode_modifier
.vex
)
3005 build_vex_prefix (t
);
3007 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3008 instructions may define INT_OPCODE as well, so avoid this corner
3009 case for those instructions that use MODRM. */
3010 if (i
.tm
.base_opcode
== INT_OPCODE
3011 && i
.op
[0].imms
->X_add_number
== 3
3012 && !i
.tm
.opcode_modifier
.modrm
)
3014 i
.tm
.base_opcode
= INT3_OPCODE
;
3018 if ((i
.tm
.opcode_modifier
.jump
3019 || i
.tm
.opcode_modifier
.jumpbyte
3020 || i
.tm
.opcode_modifier
.jumpdword
)
3021 && i
.op
[0].disps
->X_op
== O_constant
)
3023 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3024 the absolute address given by the constant. Since ix86 jumps and
3025 calls are pc relative, we need to generate a reloc. */
3026 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3027 i
.op
[0].disps
->X_op
= O_symbol
;
3030 if (i
.tm
.opcode_modifier
.rex64
)
3033 /* For 8 bit registers we need an empty rex prefix. Also if the
3034 instruction already has a prefix, we need to convert old
3035 registers to new ones. */
3037 if ((i
.types
[0].bitfield
.reg8
3038 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3039 || (i
.types
[1].bitfield
.reg8
3040 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3041 || ((i
.types
[0].bitfield
.reg8
3042 || i
.types
[1].bitfield
.reg8
)
3047 i
.rex
|= REX_OPCODE
;
3048 for (x
= 0; x
< 2; x
++)
3050 /* Look for 8 bit operand that uses old registers. */
3051 if (i
.types
[x
].bitfield
.reg8
3052 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3054 /* In case it is "hi" register, give up. */
3055 if (i
.op
[x
].regs
->reg_num
> 3)
3056 as_bad (_("can't encode register '%s%s' in an "
3057 "instruction requiring REX prefix."),
3058 register_prefix
, i
.op
[x
].regs
->reg_name
);
3060 /* Otherwise it is equivalent to the extended register.
3061 Since the encoding doesn't change this is merely
3062 cosmetic cleanup for debug output. */
3064 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3070 add_prefix (REX_OPCODE
| i
.rex
);
3072 /* We are ready to output the insn. */
3077 parse_insn (char *line
, char *mnemonic
)
3080 char *token_start
= l
;
3083 const insn_template
*t
;
3086 /* Non-zero if we found a prefix only acceptable with string insns. */
3087 const char *expecting_string_instruction
= NULL
;
3092 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3097 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3099 as_bad (_("no such instruction: `%s'"), token_start
);
3104 if (!is_space_char (*l
)
3105 && *l
!= END_OF_INSN
3107 || (*l
!= PREFIX_SEPARATOR
3110 as_bad (_("invalid character %s in mnemonic"),
3111 output_invalid (*l
));
3114 if (token_start
== l
)
3116 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3117 as_bad (_("expecting prefix; got nothing"));
3119 as_bad (_("expecting mnemonic; got nothing"));
3123 /* Look up instruction (or prefix) via hash table. */
3124 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3126 if (*l
!= END_OF_INSN
3127 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3128 && current_templates
3129 && current_templates
->start
->opcode_modifier
.isprefix
)
3131 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3133 as_bad ((flag_code
!= CODE_64BIT
3134 ? _("`%s' is only supported in 64-bit mode")
3135 : _("`%s' is not supported in 64-bit mode")),
3136 current_templates
->start
->name
);
3139 /* If we are in 16-bit mode, do not allow addr16 or data16.
3140 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3141 if ((current_templates
->start
->opcode_modifier
.size16
3142 || current_templates
->start
->opcode_modifier
.size32
)
3143 && flag_code
!= CODE_64BIT
3144 && (current_templates
->start
->opcode_modifier
.size32
3145 ^ (flag_code
== CODE_16BIT
)))
3147 as_bad (_("redundant %s prefix"),
3148 current_templates
->start
->name
);
3151 /* Add prefix, checking for repeated prefixes. */
3152 switch (add_prefix (current_templates
->start
->base_opcode
))
3157 expecting_string_instruction
= current_templates
->start
->name
;
3162 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3169 if (!current_templates
)
3171 /* Check if we should swap operand in encoding. */
3172 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3178 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3181 if (!current_templates
)
3184 /* See if we can get a match by trimming off a suffix. */
3187 case WORD_MNEM_SUFFIX
:
3188 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3189 i
.suffix
= SHORT_MNEM_SUFFIX
;
3191 case BYTE_MNEM_SUFFIX
:
3192 case QWORD_MNEM_SUFFIX
:
3193 i
.suffix
= mnem_p
[-1];
3195 current_templates
= (const templates
*) hash_find (op_hash
,
3198 case SHORT_MNEM_SUFFIX
:
3199 case LONG_MNEM_SUFFIX
:
3202 i
.suffix
= mnem_p
[-1];
3204 current_templates
= (const templates
*) hash_find (op_hash
,
3213 if (intel_float_operand (mnemonic
) == 1)
3214 i
.suffix
= SHORT_MNEM_SUFFIX
;
3216 i
.suffix
= LONG_MNEM_SUFFIX
;
3218 current_templates
= (const templates
*) hash_find (op_hash
,
3223 if (!current_templates
)
3225 as_bad (_("no such instruction: `%s'"), token_start
);
3230 if (current_templates
->start
->opcode_modifier
.jump
3231 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3233 /* Check for a branch hint. We allow ",pt" and ",pn" for
3234 predict taken and predict not taken respectively.
3235 I'm not sure that branch hints actually do anything on loop
3236 and jcxz insns (JumpByte) for current Pentium4 chips. They
3237 may work in the future and it doesn't hurt to accept them
3239 if (l
[0] == ',' && l
[1] == 'p')
3243 if (!add_prefix (DS_PREFIX_OPCODE
))
3247 else if (l
[2] == 'n')
3249 if (!add_prefix (CS_PREFIX_OPCODE
))
3255 /* Any other comma loses. */
3258 as_bad (_("invalid character %s in mnemonic"),
3259 output_invalid (*l
));
3263 /* Check if instruction is supported on specified architecture. */
3265 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3267 supported
|= cpu_flags_match (t
);
3268 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3272 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3274 as_bad (flag_code
== CODE_64BIT
3275 ? _("`%s' is not supported in 64-bit mode")
3276 : _("`%s' is only supported in 64-bit mode"),
3277 current_templates
->start
->name
);
3280 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3282 as_bad (_("`%s' is not supported on `%s%s'"),
3283 current_templates
->start
->name
,
3284 cpu_arch_name
? cpu_arch_name
: default_arch
,
3285 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3290 if (!cpu_arch_flags
.bitfield
.cpui386
3291 && (flag_code
!= CODE_16BIT
))
3293 as_warn (_("use .code16 to ensure correct addressing mode"));
3296 /* Check for rep/repne without a string instruction. */
3297 if (expecting_string_instruction
)
3299 static templates override
;
3301 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3302 if (t
->opcode_modifier
.isstring
)
3304 if (t
>= current_templates
->end
)
3306 as_bad (_("expecting string instruction after `%s'"),
3307 expecting_string_instruction
);
3310 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3311 if (!t
->opcode_modifier
.isstring
)
3314 current_templates
= &override
;
3321 parse_operands (char *l
, const char *mnemonic
)
3325 /* 1 if operand is pending after ','. */
3326 unsigned int expecting_operand
= 0;
3328 /* Non-zero if operand parens not balanced. */
3329 unsigned int paren_not_balanced
;
3331 while (*l
!= END_OF_INSN
)
3333 /* Skip optional white space before operand. */
3334 if (is_space_char (*l
))
3336 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3338 as_bad (_("invalid character %s before operand %d"),
3339 output_invalid (*l
),
3343 token_start
= l
; /* after white space */
3344 paren_not_balanced
= 0;
3345 while (paren_not_balanced
|| *l
!= ',')
3347 if (*l
== END_OF_INSN
)
3349 if (paren_not_balanced
)
3352 as_bad (_("unbalanced parenthesis in operand %d."),
3355 as_bad (_("unbalanced brackets in operand %d."),
3360 break; /* we are done */
3362 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3364 as_bad (_("invalid character %s in operand %d"),
3365 output_invalid (*l
),
3372 ++paren_not_balanced
;
3374 --paren_not_balanced
;
3379 ++paren_not_balanced
;
3381 --paren_not_balanced
;
3385 if (l
!= token_start
)
3386 { /* Yes, we've read in another operand. */
3387 unsigned int operand_ok
;
3388 this_operand
= i
.operands
++;
3389 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3390 if (i
.operands
> MAX_OPERANDS
)
3392 as_bad (_("spurious operands; (%d operands/instruction max)"),
3396 /* Now parse operand adding info to 'i' as we go along. */
3397 END_STRING_AND_SAVE (l
);
3401 i386_intel_operand (token_start
,
3402 intel_float_operand (mnemonic
));
3404 operand_ok
= i386_att_operand (token_start
);
3406 RESTORE_END_STRING (l
);
3412 if (expecting_operand
)
3414 expecting_operand_after_comma
:
3415 as_bad (_("expecting operand after ','; got nothing"));
3420 as_bad (_("expecting operand before ','; got nothing"));
3425 /* Now *l must be either ',' or END_OF_INSN. */
3428 if (*++l
== END_OF_INSN
)
3430 /* Just skip it, if it's \n complain. */
3431 goto expecting_operand_after_comma
;
3433 expecting_operand
= 1;
3440 swap_2_operands (int xchg1
, int xchg2
)
3442 union i386_op temp_op
;
3443 i386_operand_type temp_type
;
3444 enum bfd_reloc_code_real temp_reloc
;
3446 temp_type
= i
.types
[xchg2
];
3447 i
.types
[xchg2
] = i
.types
[xchg1
];
3448 i
.types
[xchg1
] = temp_type
;
3449 temp_op
= i
.op
[xchg2
];
3450 i
.op
[xchg2
] = i
.op
[xchg1
];
3451 i
.op
[xchg1
] = temp_op
;
3452 temp_reloc
= i
.reloc
[xchg2
];
3453 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3454 i
.reloc
[xchg1
] = temp_reloc
;
3458 swap_operands (void)
3464 swap_2_operands (1, i
.operands
- 2);
3467 swap_2_operands (0, i
.operands
- 1);
3473 if (i
.mem_operands
== 2)
3475 const seg_entry
*temp_seg
;
3476 temp_seg
= i
.seg
[0];
3477 i
.seg
[0] = i
.seg
[1];
3478 i
.seg
[1] = temp_seg
;
3482 /* Try to ensure constant immediates are represented in the smallest
3487 char guess_suffix
= 0;
3491 guess_suffix
= i
.suffix
;
3492 else if (i
.reg_operands
)
3494 /* Figure out a suffix from the last register operand specified.
3495 We can't do this properly yet, ie. excluding InOutPortReg,
3496 but the following works for instructions with immediates.
3497 In any case, we can't set i.suffix yet. */
3498 for (op
= i
.operands
; --op
>= 0;)
3499 if (i
.types
[op
].bitfield
.reg8
)
3501 guess_suffix
= BYTE_MNEM_SUFFIX
;
3504 else if (i
.types
[op
].bitfield
.reg16
)
3506 guess_suffix
= WORD_MNEM_SUFFIX
;
3509 else if (i
.types
[op
].bitfield
.reg32
)
3511 guess_suffix
= LONG_MNEM_SUFFIX
;
3514 else if (i
.types
[op
].bitfield
.reg64
)
3516 guess_suffix
= QWORD_MNEM_SUFFIX
;
3520 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3521 guess_suffix
= WORD_MNEM_SUFFIX
;
3523 for (op
= i
.operands
; --op
>= 0;)
3524 if (operand_type_check (i
.types
[op
], imm
))
3526 switch (i
.op
[op
].imms
->X_op
)
3529 /* If a suffix is given, this operand may be shortened. */
3530 switch (guess_suffix
)
3532 case LONG_MNEM_SUFFIX
:
3533 i
.types
[op
].bitfield
.imm32
= 1;
3534 i
.types
[op
].bitfield
.imm64
= 1;
3536 case WORD_MNEM_SUFFIX
:
3537 i
.types
[op
].bitfield
.imm16
= 1;
3538 i
.types
[op
].bitfield
.imm32
= 1;
3539 i
.types
[op
].bitfield
.imm32s
= 1;
3540 i
.types
[op
].bitfield
.imm64
= 1;
3542 case BYTE_MNEM_SUFFIX
:
3543 i
.types
[op
].bitfield
.imm8
= 1;
3544 i
.types
[op
].bitfield
.imm8s
= 1;
3545 i
.types
[op
].bitfield
.imm16
= 1;
3546 i
.types
[op
].bitfield
.imm32
= 1;
3547 i
.types
[op
].bitfield
.imm32s
= 1;
3548 i
.types
[op
].bitfield
.imm64
= 1;
3552 /* If this operand is at most 16 bits, convert it
3553 to a signed 16 bit number before trying to see
3554 whether it will fit in an even smaller size.
3555 This allows a 16-bit operand such as $0xffe0 to
3556 be recognised as within Imm8S range. */
3557 if ((i
.types
[op
].bitfield
.imm16
)
3558 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3560 i
.op
[op
].imms
->X_add_number
=
3561 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3563 if ((i
.types
[op
].bitfield
.imm32
)
3564 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3567 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3568 ^ ((offsetT
) 1 << 31))
3569 - ((offsetT
) 1 << 31));
3572 = operand_type_or (i
.types
[op
],
3573 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3575 /* We must avoid matching of Imm32 templates when 64bit
3576 only immediate is available. */
3577 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3578 i
.types
[op
].bitfield
.imm32
= 0;
3585 /* Symbols and expressions. */
3587 /* Convert symbolic operand to proper sizes for matching, but don't
3588 prevent matching a set of insns that only supports sizes other
3589 than those matching the insn suffix. */
3591 i386_operand_type mask
, allowed
;
3592 const insn_template
*t
;
3594 operand_type_set (&mask
, 0);
3595 operand_type_set (&allowed
, 0);
3597 for (t
= current_templates
->start
;
3598 t
< current_templates
->end
;
3600 allowed
= operand_type_or (allowed
,
3601 t
->operand_types
[op
]);
3602 switch (guess_suffix
)
3604 case QWORD_MNEM_SUFFIX
:
3605 mask
.bitfield
.imm64
= 1;
3606 mask
.bitfield
.imm32s
= 1;
3608 case LONG_MNEM_SUFFIX
:
3609 mask
.bitfield
.imm32
= 1;
3611 case WORD_MNEM_SUFFIX
:
3612 mask
.bitfield
.imm16
= 1;
3614 case BYTE_MNEM_SUFFIX
:
3615 mask
.bitfield
.imm8
= 1;
3620 allowed
= operand_type_and (mask
, allowed
);
3621 if (!operand_type_all_zero (&allowed
))
3622 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3629 /* Try to use the smallest displacement type too. */
3631 optimize_disp (void)
3635 for (op
= i
.operands
; --op
>= 0;)
3636 if (operand_type_check (i
.types
[op
], disp
))
3638 if (i
.op
[op
].disps
->X_op
== O_constant
)
3640 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3642 if (i
.types
[op
].bitfield
.disp16
3643 && (disp
& ~(offsetT
) 0xffff) == 0)
3645 /* If this operand is at most 16 bits, convert
3646 to a signed 16 bit number and don't use 64bit
3648 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3649 i
.types
[op
].bitfield
.disp64
= 0;
3651 if (i
.types
[op
].bitfield
.disp32
3652 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3654 /* If this operand is at most 32 bits, convert
3655 to a signed 32 bit number and don't use 64bit
3657 disp
&= (((offsetT
) 2 << 31) - 1);
3658 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3659 i
.types
[op
].bitfield
.disp64
= 0;
3661 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3663 i
.types
[op
].bitfield
.disp8
= 0;
3664 i
.types
[op
].bitfield
.disp16
= 0;
3665 i
.types
[op
].bitfield
.disp32
= 0;
3666 i
.types
[op
].bitfield
.disp32s
= 0;
3667 i
.types
[op
].bitfield
.disp64
= 0;
3671 else if (flag_code
== CODE_64BIT
)
3673 if (fits_in_signed_long (disp
))
3675 i
.types
[op
].bitfield
.disp64
= 0;
3676 i
.types
[op
].bitfield
.disp32s
= 1;
3678 if (i
.prefix
[ADDR_PREFIX
]
3679 && fits_in_unsigned_long (disp
))
3680 i
.types
[op
].bitfield
.disp32
= 1;
3682 if ((i
.types
[op
].bitfield
.disp32
3683 || i
.types
[op
].bitfield
.disp32s
3684 || i
.types
[op
].bitfield
.disp16
)
3685 && fits_in_signed_byte (disp
))
3686 i
.types
[op
].bitfield
.disp8
= 1;
3688 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3689 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3691 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3692 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3693 i
.types
[op
].bitfield
.disp8
= 0;
3694 i
.types
[op
].bitfield
.disp16
= 0;
3695 i
.types
[op
].bitfield
.disp32
= 0;
3696 i
.types
[op
].bitfield
.disp32s
= 0;
3697 i
.types
[op
].bitfield
.disp64
= 0;
3700 /* We only support 64bit displacement on constants. */
3701 i
.types
[op
].bitfield
.disp64
= 0;
3705 static const insn_template
*
3706 match_template (void)
3708 /* Points to template once we've found it. */
3709 const insn_template
*t
;
3710 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3711 i386_operand_type overlap4
;
3712 unsigned int found_reverse_match
;
3713 i386_opcode_modifier suffix_check
;
3714 i386_operand_type operand_types
[MAX_OPERANDS
];
3715 int addr_prefix_disp
;
3717 unsigned int found_cpu_match
;
3718 unsigned int check_register
;
3720 #if MAX_OPERANDS != 5
3721 # error "MAX_OPERANDS must be 5."
3724 found_reverse_match
= 0;
3725 addr_prefix_disp
= -1;
3727 memset (&suffix_check
, 0, sizeof (suffix_check
));
3728 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3729 suffix_check
.no_bsuf
= 1;
3730 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3731 suffix_check
.no_wsuf
= 1;
3732 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3733 suffix_check
.no_ssuf
= 1;
3734 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3735 suffix_check
.no_lsuf
= 1;
3736 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3737 suffix_check
.no_qsuf
= 1;
3738 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3739 suffix_check
.no_ldsuf
= 1;
3741 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3743 addr_prefix_disp
= -1;
3745 /* Must have right number of operands. */
3746 if (i
.operands
!= t
->operands
)
3749 /* Check processor support. */
3750 found_cpu_match
= (cpu_flags_match (t
)
3751 == CPU_FLAGS_PERFECT_MATCH
);
3752 if (!found_cpu_match
)
3755 /* Check old gcc support. */
3756 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3759 /* Check AT&T mnemonic. */
3760 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3763 /* Check AT&T syntax Intel syntax. */
3764 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3765 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3768 /* Check the suffix, except for some instructions in intel mode. */
3769 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3770 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3771 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3772 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3773 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3774 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3775 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3778 if (!operand_size_match (t
))
3781 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3782 operand_types
[j
] = t
->operand_types
[j
];
3784 /* In general, don't allow 64-bit operands in 32-bit mode. */
3785 if (i
.suffix
== QWORD_MNEM_SUFFIX
3786 && flag_code
!= CODE_64BIT
3788 ? (!t
->opcode_modifier
.ignoresize
3789 && !intel_float_operand (t
->name
))
3790 : intel_float_operand (t
->name
) != 2)
3791 && ((!operand_types
[0].bitfield
.regmmx
3792 && !operand_types
[0].bitfield
.regxmm
3793 && !operand_types
[0].bitfield
.regymm
)
3794 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3795 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3796 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3797 && (t
->base_opcode
!= 0x0fc7
3798 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3801 /* In general, don't allow 32-bit operands on pre-386. */
3802 else if (i
.suffix
== LONG_MNEM_SUFFIX
3803 && !cpu_arch_flags
.bitfield
.cpui386
3805 ? (!t
->opcode_modifier
.ignoresize
3806 && !intel_float_operand (t
->name
))
3807 : intel_float_operand (t
->name
) != 2)
3808 && ((!operand_types
[0].bitfield
.regmmx
3809 && !operand_types
[0].bitfield
.regxmm
)
3810 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3811 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3814 /* Do not verify operands when there are none. */
3818 /* We've found a match; break out of loop. */
3822 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3823 into Disp32/Disp16/Disp32 operand. */
3824 if (i
.prefix
[ADDR_PREFIX
] != 0)
3826 /* There should be only one Disp operand. */
3830 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3832 if (operand_types
[j
].bitfield
.disp16
)
3834 addr_prefix_disp
= j
;
3835 operand_types
[j
].bitfield
.disp32
= 1;
3836 operand_types
[j
].bitfield
.disp16
= 0;
3842 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3844 if (operand_types
[j
].bitfield
.disp32
)
3846 addr_prefix_disp
= j
;
3847 operand_types
[j
].bitfield
.disp32
= 0;
3848 operand_types
[j
].bitfield
.disp16
= 1;
3854 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3856 if (operand_types
[j
].bitfield
.disp64
)
3858 addr_prefix_disp
= j
;
3859 operand_types
[j
].bitfield
.disp64
= 0;
3860 operand_types
[j
].bitfield
.disp32
= 1;
3868 /* We check register size only if size of operands can be
3869 encoded the canonical way. */
3870 check_register
= t
->opcode_modifier
.w
;
3871 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3872 switch (t
->operands
)
3875 if (!operand_type_match (overlap0
, i
.types
[0]))
3879 /* xchg %eax, %eax is a special case. It is an aliase for nop
3880 only in 32bit mode and we can use opcode 0x90. In 64bit
3881 mode, we can't use 0x90 for xchg %eax, %eax since it should
3882 zero-extend %eax to %rax. */
3883 if (flag_code
== CODE_64BIT
3884 && t
->base_opcode
== 0x90
3885 && operand_type_equal (&i
.types
[0], &acc32
)
3886 && operand_type_equal (&i
.types
[1], &acc32
))
3890 /* If we swap operand in encoding, we either match
3891 the next one or reverse direction of operands. */
3892 if (t
->opcode_modifier
.s
)
3894 else if (t
->opcode_modifier
.d
)
3899 /* If we swap operand in encoding, we match the next one. */
3900 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3904 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3905 if (!operand_type_match (overlap0
, i
.types
[0])
3906 || !operand_type_match (overlap1
, i
.types
[1])
3908 && !operand_type_register_match (overlap0
, i
.types
[0],
3910 overlap1
, i
.types
[1],
3913 /* Check if other direction is valid ... */
3914 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3918 /* Try reversing direction of operands. */
3919 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3920 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3921 if (!operand_type_match (overlap0
, i
.types
[0])
3922 || !operand_type_match (overlap1
, i
.types
[1])
3924 && !operand_type_register_match (overlap0
,
3931 /* Does not match either direction. */
3934 /* found_reverse_match holds which of D or FloatDR
3936 if (t
->opcode_modifier
.d
)
3937 found_reverse_match
= Opcode_D
;
3938 else if (t
->opcode_modifier
.floatd
)
3939 found_reverse_match
= Opcode_FloatD
;
3941 found_reverse_match
= 0;
3942 if (t
->opcode_modifier
.floatr
)
3943 found_reverse_match
|= Opcode_FloatR
;
3947 /* Found a forward 2 operand match here. */
3948 switch (t
->operands
)
3951 overlap4
= operand_type_and (i
.types
[4],
3954 overlap3
= operand_type_and (i
.types
[3],
3957 overlap2
= operand_type_and (i
.types
[2],
3962 switch (t
->operands
)
3965 if (!operand_type_match (overlap4
, i
.types
[4])
3966 || !operand_type_register_match (overlap3
,
3974 if (!operand_type_match (overlap3
, i
.types
[3])
3976 && !operand_type_register_match (overlap2
,
3984 /* Here we make use of the fact that there are no
3985 reverse match 3 operand instructions, and all 3
3986 operand instructions only need to be checked for
3987 register consistency between operands 2 and 3. */
3988 if (!operand_type_match (overlap2
, i
.types
[2])
3990 && !operand_type_register_match (overlap1
,
4000 /* Found either forward/reverse 2, 3 or 4 operand match here:
4001 slip through to break. */
4003 if (!found_cpu_match
)
4005 found_reverse_match
= 0;
4009 /* We've found a match; break out of loop. */
4013 if (t
== current_templates
->end
)
4015 /* We found no match. */
4017 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4018 current_templates
->start
->name
);
4020 as_bad (_("suffix or operands invalid for `%s'"),
4021 current_templates
->start
->name
);
4025 if (!quiet_warnings
)
4028 && (i
.types
[0].bitfield
.jumpabsolute
4029 != operand_types
[0].bitfield
.jumpabsolute
))
4031 as_warn (_("indirect %s without `*'"), t
->name
);
4034 if (t
->opcode_modifier
.isprefix
4035 && t
->opcode_modifier
.ignoresize
)
4037 /* Warn them that a data or address size prefix doesn't
4038 affect assembly of the next line of code. */
4039 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4043 /* Copy the template we found. */
4046 if (addr_prefix_disp
!= -1)
4047 i
.tm
.operand_types
[addr_prefix_disp
]
4048 = operand_types
[addr_prefix_disp
];
4050 if (found_reverse_match
)
4052 /* If we found a reverse match we must alter the opcode
4053 direction bit. found_reverse_match holds bits to change
4054 (different for int & float insns). */
4056 i
.tm
.base_opcode
^= found_reverse_match
;
4058 i
.tm
.operand_types
[0] = operand_types
[1];
4059 i
.tm
.operand_types
[1] = operand_types
[0];
4068 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4069 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4071 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4073 as_bad (_("`%s' operand %d must use `%ses' segment"),
4079 /* There's only ever one segment override allowed per instruction.
4080 This instruction possibly has a legal segment override on the
4081 second operand, so copy the segment to where non-string
4082 instructions store it, allowing common code. */
4083 i
.seg
[0] = i
.seg
[1];
4085 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4087 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4089 as_bad (_("`%s' operand %d must use `%ses' segment"),
4100 process_suffix (void)
4102 /* If matched instruction specifies an explicit instruction mnemonic
4104 if (i
.tm
.opcode_modifier
.size16
)
4105 i
.suffix
= WORD_MNEM_SUFFIX
;
4106 else if (i
.tm
.opcode_modifier
.size32
)
4107 i
.suffix
= LONG_MNEM_SUFFIX
;
4108 else if (i
.tm
.opcode_modifier
.size64
)
4109 i
.suffix
= QWORD_MNEM_SUFFIX
;
4110 else if (i
.reg_operands
)
4112 /* If there's no instruction mnemonic suffix we try to invent one
4113 based on register operands. */
4116 /* We take i.suffix from the last register operand specified,
4117 Destination register type is more significant than source
4118 register type. crc32 in SSE4.2 prefers source register
4120 if (i
.tm
.base_opcode
== 0xf20f38f1)
4122 if (i
.types
[0].bitfield
.reg16
)
4123 i
.suffix
= WORD_MNEM_SUFFIX
;
4124 else if (i
.types
[0].bitfield
.reg32
)
4125 i
.suffix
= LONG_MNEM_SUFFIX
;
4126 else if (i
.types
[0].bitfield
.reg64
)
4127 i
.suffix
= QWORD_MNEM_SUFFIX
;
4129 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4131 if (i
.types
[0].bitfield
.reg8
)
4132 i
.suffix
= BYTE_MNEM_SUFFIX
;
4139 if (i
.tm
.base_opcode
== 0xf20f38f1
4140 || i
.tm
.base_opcode
== 0xf20f38f0)
4142 /* We have to know the operand size for crc32. */
4143 as_bad (_("ambiguous memory operand size for `%s`"),
4148 for (op
= i
.operands
; --op
>= 0;)
4149 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4151 if (i
.types
[op
].bitfield
.reg8
)
4153 i
.suffix
= BYTE_MNEM_SUFFIX
;
4156 else if (i
.types
[op
].bitfield
.reg16
)
4158 i
.suffix
= WORD_MNEM_SUFFIX
;
4161 else if (i
.types
[op
].bitfield
.reg32
)
4163 i
.suffix
= LONG_MNEM_SUFFIX
;
4166 else if (i
.types
[op
].bitfield
.reg64
)
4168 i
.suffix
= QWORD_MNEM_SUFFIX
;
4174 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4176 if (!check_byte_reg ())
4179 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4181 if (!check_long_reg ())
4184 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4187 && i
.tm
.opcode_modifier
.ignoresize
4188 && i
.tm
.opcode_modifier
.no_qsuf
)
4190 else if (!check_qword_reg ())
4193 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4195 if (!check_word_reg ())
4198 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4199 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4201 /* Skip if the instruction has x/y suffix. match_template
4202 should check if it is a valid suffix. */
4204 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4205 /* Do nothing if the instruction is going to ignore the prefix. */
4210 else if (i
.tm
.opcode_modifier
.defaultsize
4212 /* exclude fldenv/frstor/fsave/fstenv */
4213 && i
.tm
.opcode_modifier
.no_ssuf
)
4215 i
.suffix
= stackop_size
;
4217 else if (intel_syntax
4219 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4220 || i
.tm
.opcode_modifier
.jumpbyte
4221 || i
.tm
.opcode_modifier
.jumpintersegment
4222 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4223 && i
.tm
.extension_opcode
<= 3)))
4228 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4230 i
.suffix
= QWORD_MNEM_SUFFIX
;
4234 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4235 i
.suffix
= LONG_MNEM_SUFFIX
;
4238 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4239 i
.suffix
= WORD_MNEM_SUFFIX
;
4248 if (i
.tm
.opcode_modifier
.w
)
4250 as_bad (_("no instruction mnemonic suffix given and "
4251 "no register operands; can't size instruction"));
4257 unsigned int suffixes
;
4259 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4260 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4262 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4264 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4266 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4268 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4271 /* There are more than suffix matches. */
4272 if (i
.tm
.opcode_modifier
.w
4273 || ((suffixes
& (suffixes
- 1))
4274 && !i
.tm
.opcode_modifier
.defaultsize
4275 && !i
.tm
.opcode_modifier
.ignoresize
))
4277 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4283 /* Change the opcode based on the operand size given by i.suffix;
4284 We don't need to change things for byte insns. */
4287 && i
.suffix
!= BYTE_MNEM_SUFFIX
4288 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4289 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4291 /* It's not a byte, select word/dword operation. */
4292 if (i
.tm
.opcode_modifier
.w
)
4294 if (i
.tm
.opcode_modifier
.shortform
)
4295 i
.tm
.base_opcode
|= 8;
4297 i
.tm
.base_opcode
|= 1;
4300 /* Now select between word & dword operations via the operand
4301 size prefix, except for instructions that will ignore this
4303 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4305 /* The address size override prefix changes the size of the
4307 if ((flag_code
== CODE_32BIT
4308 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4309 || (flag_code
!= CODE_32BIT
4310 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4311 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4314 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4315 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4316 && !i
.tm
.opcode_modifier
.ignoresize
4317 && !i
.tm
.opcode_modifier
.floatmf
4318 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4319 || (flag_code
== CODE_64BIT
4320 && i
.tm
.opcode_modifier
.jumpbyte
)))
4322 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4324 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4325 prefix
= ADDR_PREFIX_OPCODE
;
4327 if (!add_prefix (prefix
))
4331 /* Set mode64 for an operand. */
4332 if (i
.suffix
== QWORD_MNEM_SUFFIX
4333 && flag_code
== CODE_64BIT
4334 && !i
.tm
.opcode_modifier
.norex64
)
4336 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4337 need rex64. cmpxchg8b is also a special case. */
4338 if (! (i
.operands
== 2
4339 && i
.tm
.base_opcode
== 0x90
4340 && i
.tm
.extension_opcode
== None
4341 && operand_type_equal (&i
.types
[0], &acc64
)
4342 && operand_type_equal (&i
.types
[1], &acc64
))
4343 && ! (i
.operands
== 1
4344 && i
.tm
.base_opcode
== 0xfc7
4345 && i
.tm
.extension_opcode
== 1
4346 && !operand_type_check (i
.types
[0], reg
)
4347 && operand_type_check (i
.types
[0], anymem
)))
4351 /* Size floating point instruction. */
4352 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4353 if (i
.tm
.opcode_modifier
.floatmf
)
4354 i
.tm
.base_opcode
^= 4;
4361 check_byte_reg (void)
4365 for (op
= i
.operands
; --op
>= 0;)
4367 /* If this is an eight bit register, it's OK. If it's the 16 or
4368 32 bit version of an eight bit register, we will just use the
4369 low portion, and that's OK too. */
4370 if (i
.types
[op
].bitfield
.reg8
)
4373 /* Don't generate this warning if not needed. */
4374 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4377 /* crc32 doesn't generate this warning. */
4378 if (i
.tm
.base_opcode
== 0xf20f38f0)
4381 if ((i
.types
[op
].bitfield
.reg16
4382 || i
.types
[op
].bitfield
.reg32
4383 || i
.types
[op
].bitfield
.reg64
)
4384 && i
.op
[op
].regs
->reg_num
< 4)
4386 /* Prohibit these changes in the 64bit mode, since the
4387 lowering is more complicated. */
4388 if (flag_code
== CODE_64BIT
4389 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4391 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4392 register_prefix
, i
.op
[op
].regs
->reg_name
,
4396 #if REGISTER_WARNINGS
4398 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4399 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4401 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4402 ? REGNAM_AL
- REGNAM_AX
4403 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4405 i
.op
[op
].regs
->reg_name
,
4410 /* Any other register is bad. */
4411 if (i
.types
[op
].bitfield
.reg16
4412 || i
.types
[op
].bitfield
.reg32
4413 || i
.types
[op
].bitfield
.reg64
4414 || i
.types
[op
].bitfield
.regmmx
4415 || i
.types
[op
].bitfield
.regxmm
4416 || i
.types
[op
].bitfield
.regymm
4417 || i
.types
[op
].bitfield
.sreg2
4418 || i
.types
[op
].bitfield
.sreg3
4419 || i
.types
[op
].bitfield
.control
4420 || i
.types
[op
].bitfield
.debug
4421 || i
.types
[op
].bitfield
.test
4422 || i
.types
[op
].bitfield
.floatreg
4423 || i
.types
[op
].bitfield
.floatacc
)
4425 as_bad (_("`%s%s' not allowed with `%s%c'"),
4427 i
.op
[op
].regs
->reg_name
,
4437 check_long_reg (void)
4441 for (op
= i
.operands
; --op
>= 0;)
4442 /* Reject eight bit registers, except where the template requires
4443 them. (eg. movzb) */
4444 if (i
.types
[op
].bitfield
.reg8
4445 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4446 || i
.tm
.operand_types
[op
].bitfield
.reg32
4447 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4449 as_bad (_("`%s%s' not allowed with `%s%c'"),
4451 i
.op
[op
].regs
->reg_name
,
4456 /* Warn if the e prefix on a general reg is missing. */
4457 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4458 && i
.types
[op
].bitfield
.reg16
4459 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4460 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4462 /* Prohibit these changes in the 64bit mode, since the
4463 lowering is more complicated. */
4464 if (flag_code
== CODE_64BIT
)
4466 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4467 register_prefix
, i
.op
[op
].regs
->reg_name
,
4471 #if REGISTER_WARNINGS
4473 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4475 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4477 i
.op
[op
].regs
->reg_name
,
4481 /* Warn if the r prefix on a general reg is missing. */
4482 else if (i
.types
[op
].bitfield
.reg64
4483 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4484 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4487 && i
.tm
.opcode_modifier
.toqword
4488 && !i
.types
[0].bitfield
.regxmm
)
4490 /* Convert to QWORD. We want REX byte. */
4491 i
.suffix
= QWORD_MNEM_SUFFIX
;
4495 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4496 register_prefix
, i
.op
[op
].regs
->reg_name
,
4505 check_qword_reg (void)
4509 for (op
= i
.operands
; --op
>= 0; )
4510 /* Reject eight bit registers, except where the template requires
4511 them. (eg. movzb) */
4512 if (i
.types
[op
].bitfield
.reg8
4513 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4514 || i
.tm
.operand_types
[op
].bitfield
.reg32
4515 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4517 as_bad (_("`%s%s' not allowed with `%s%c'"),
4519 i
.op
[op
].regs
->reg_name
,
4524 /* Warn if the e prefix on a general reg is missing. */
4525 else if ((i
.types
[op
].bitfield
.reg16
4526 || i
.types
[op
].bitfield
.reg32
)
4527 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4528 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4530 /* Prohibit these changes in the 64bit mode, since the
4531 lowering is more complicated. */
4533 && i
.tm
.opcode_modifier
.todword
4534 && !i
.types
[0].bitfield
.regxmm
)
4536 /* Convert to DWORD. We don't want REX byte. */
4537 i
.suffix
= LONG_MNEM_SUFFIX
;
4541 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4542 register_prefix
, i
.op
[op
].regs
->reg_name
,
4551 check_word_reg (void)
4554 for (op
= i
.operands
; --op
>= 0;)
4555 /* Reject eight bit registers, except where the template requires
4556 them. (eg. movzb) */
4557 if (i
.types
[op
].bitfield
.reg8
4558 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4559 || i
.tm
.operand_types
[op
].bitfield
.reg32
4560 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4562 as_bad (_("`%s%s' not allowed with `%s%c'"),
4564 i
.op
[op
].regs
->reg_name
,
4569 /* Warn if the e prefix on a general reg is present. */
4570 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4571 && i
.types
[op
].bitfield
.reg32
4572 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4573 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4575 /* Prohibit these changes in the 64bit mode, since the
4576 lowering is more complicated. */
4577 if (flag_code
== CODE_64BIT
)
4579 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4580 register_prefix
, i
.op
[op
].regs
->reg_name
,
4585 #if REGISTER_WARNINGS
4586 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4588 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4590 i
.op
[op
].regs
->reg_name
,
4598 update_imm (unsigned int j
)
4600 i386_operand_type overlap
= i
.types
[j
];
4601 if ((overlap
.bitfield
.imm8
4602 || overlap
.bitfield
.imm8s
4603 || overlap
.bitfield
.imm16
4604 || overlap
.bitfield
.imm32
4605 || overlap
.bitfield
.imm32s
4606 || overlap
.bitfield
.imm64
)
4607 && !operand_type_equal (&overlap
, &imm8
)
4608 && !operand_type_equal (&overlap
, &imm8s
)
4609 && !operand_type_equal (&overlap
, &imm16
)
4610 && !operand_type_equal (&overlap
, &imm32
)
4611 && !operand_type_equal (&overlap
, &imm32s
)
4612 && !operand_type_equal (&overlap
, &imm64
))
4616 i386_operand_type temp
;
4618 operand_type_set (&temp
, 0);
4619 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4621 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4622 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4624 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4625 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4626 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4628 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4629 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4632 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4635 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4636 || operand_type_equal (&overlap
, &imm16_32
)
4637 || operand_type_equal (&overlap
, &imm16_32s
))
4639 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4644 if (!operand_type_equal (&overlap
, &imm8
)
4645 && !operand_type_equal (&overlap
, &imm8s
)
4646 && !operand_type_equal (&overlap
, &imm16
)
4647 && !operand_type_equal (&overlap
, &imm32
)
4648 && !operand_type_equal (&overlap
, &imm32s
)
4649 && !operand_type_equal (&overlap
, &imm64
))
4651 as_bad (_("no instruction mnemonic suffix given; "
4652 "can't determine immediate size"));
4656 i
.types
[j
] = overlap
;
4666 /* Update the first 2 immediate operands. */
4667 n
= i
.operands
> 2 ? 2 : i
.operands
;
4670 for (j
= 0; j
< n
; j
++)
4671 if (update_imm (j
) == 0)
4674 /* The 3rd operand can't be immediate operand. */
4675 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4682 bad_implicit_operand (int xmm
)
4684 const char *reg
= xmm
? "xmm0" : "ymm0";
4686 as_bad (_("the last operand of `%s' must be `%s%s'"),
4687 i
.tm
.name
, register_prefix
, reg
);
4689 as_bad (_("the first operand of `%s' must be `%s%s'"),
4690 i
.tm
.name
, register_prefix
, reg
);
4695 process_operands (void)
4697 /* Default segment register this instruction will use for memory
4698 accesses. 0 means unknown. This is only for optimizing out
4699 unnecessary segment overrides. */
4700 const seg_entry
*default_seg
= 0;
4702 if (i
.tm
.opcode_modifier
.sse2avx
4703 && (i
.tm
.opcode_modifier
.vexnds
4704 || i
.tm
.opcode_modifier
.vexndd
))
4706 unsigned int dup
= i
.operands
;
4707 unsigned int dest
= dup
- 1;
4710 /* The destination must be an xmm register. */
4711 gas_assert (i
.reg_operands
4712 && MAX_OPERANDS
> dup
4713 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4715 if (i
.tm
.opcode_modifier
.firstxmm0
)
4717 /* The first operand is implicit and must be xmm0. */
4718 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4719 if (i
.op
[0].regs
->reg_num
!= 0)
4720 return bad_implicit_operand (1);
4722 if (i
.tm
.opcode_modifier
.vex3sources
)
4724 /* Keep xmm0 for instructions with VEX prefix and 3
4730 /* We remove the first xmm0 and keep the number of
4731 operands unchanged, which in fact duplicates the
4733 for (j
= 1; j
< i
.operands
; j
++)
4735 i
.op
[j
- 1] = i
.op
[j
];
4736 i
.types
[j
- 1] = i
.types
[j
];
4737 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4741 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4743 gas_assert ((MAX_OPERANDS
- 1) > dup
4744 && i
.tm
.opcode_modifier
.vex3sources
);
4746 /* Add the implicit xmm0 for instructions with VEX prefix
4748 for (j
= i
.operands
; j
> 0; j
--)
4750 i
.op
[j
] = i
.op
[j
- 1];
4751 i
.types
[j
] = i
.types
[j
- 1];
4752 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4755 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4756 i
.types
[0] = regxmm
;
4757 i
.tm
.operand_types
[0] = regxmm
;
4760 i
.reg_operands
+= 2;
4765 i
.op
[dup
] = i
.op
[dest
];
4766 i
.types
[dup
] = i
.types
[dest
];
4767 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4776 i
.op
[dup
] = i
.op
[dest
];
4777 i
.types
[dup
] = i
.types
[dest
];
4778 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4781 if (i
.tm
.opcode_modifier
.immext
)
4784 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4788 /* The first operand is implicit and must be xmm0/ymm0. */
4789 gas_assert (i
.reg_operands
4790 && (operand_type_equal (&i
.types
[0], ®xmm
)
4791 || operand_type_equal (&i
.types
[0], ®ymm
)));
4792 if (i
.op
[0].regs
->reg_num
!= 0)
4793 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4795 for (j
= 1; j
< i
.operands
; j
++)
4797 i
.op
[j
- 1] = i
.op
[j
];
4798 i
.types
[j
- 1] = i
.types
[j
];
4800 /* We need to adjust fields in i.tm since they are used by
4801 build_modrm_byte. */
4802 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4809 else if (i
.tm
.opcode_modifier
.regkludge
)
4811 /* The imul $imm, %reg instruction is converted into
4812 imul $imm, %reg, %reg, and the clr %reg instruction
4813 is converted into xor %reg, %reg. */
4815 unsigned int first_reg_op
;
4817 if (operand_type_check (i
.types
[0], reg
))
4821 /* Pretend we saw the extra register operand. */
4822 gas_assert (i
.reg_operands
== 1
4823 && i
.op
[first_reg_op
+ 1].regs
== 0);
4824 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4825 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4830 if (i
.tm
.opcode_modifier
.shortform
)
4832 if (i
.types
[0].bitfield
.sreg2
4833 || i
.types
[0].bitfield
.sreg3
)
4835 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4836 && i
.op
[0].regs
->reg_num
== 1)
4838 as_bad (_("you can't `pop %scs'"), register_prefix
);
4841 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4842 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4847 /* The register or float register operand is in operand
4851 if (i
.types
[0].bitfield
.floatreg
4852 || operand_type_check (i
.types
[0], reg
))
4856 /* Register goes in low 3 bits of opcode. */
4857 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4858 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4860 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4862 /* Warn about some common errors, but press on regardless.
4863 The first case can be generated by gcc (<= 2.8.1). */
4864 if (i
.operands
== 2)
4866 /* Reversed arguments on faddp, fsubp, etc. */
4867 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4868 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4869 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4873 /* Extraneous `l' suffix on fp insn. */
4874 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4875 register_prefix
, i
.op
[0].regs
->reg_name
);
4880 else if (i
.tm
.opcode_modifier
.modrm
)
4882 /* The opcode is completed (modulo i.tm.extension_opcode which
4883 must be put into the modrm byte). Now, we make the modrm and
4884 index base bytes based on all the info we've collected. */
4886 default_seg
= build_modrm_byte ();
4888 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4892 else if (i
.tm
.opcode_modifier
.isstring
)
4894 /* For the string instructions that allow a segment override
4895 on one of their operands, the default segment is ds. */
4899 if (i
.tm
.base_opcode
== 0x8d /* lea */
4902 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4904 /* If a segment was explicitly specified, and the specified segment
4905 is not the default, use an opcode prefix to select it. If we
4906 never figured out what the default segment is, then default_seg
4907 will be zero at this point, and the specified segment prefix will
4909 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4911 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4917 static const seg_entry
*
4918 build_modrm_byte (void)
4920 const seg_entry
*default_seg
= 0;
4921 unsigned int source
, dest
;
4922 int vex_3_sources
, vex_2_sources
;
4924 /* The first operand of instructions with VEX prefix and 3 sources
4925 must be VEX_Imm4. */
4926 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4927 vex_2_sources
= i
.tm
.opcode_modifier
.vex2sources
;
4930 unsigned int nds
, reg
;
4933 if (i
.tm
.opcode_modifier
.veximmext
4934 && i
.tm
.opcode_modifier
.immext
)
4936 dest
= i
.operands
- 2;
4937 gas_assert (dest
== 3);
4940 dest
= i
.operands
- 1;
4943 /* This instruction must have 4 register operands
4944 or 3 register operands plus 1 memory operand.
4945 It must have VexNDS and VexImmExt. */
4946 gas_assert ((i
.reg_operands
== 4
4947 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4948 && i
.tm
.opcode_modifier
.vexnds
4949 && i
.tm
.opcode_modifier
.veximmext
4950 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4951 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4953 /* Generate an 8bit immediate operand to encode the register
4955 exp
= &im_expressions
[i
.imm_operands
++];
4956 i
.op
[i
.operands
].imms
= exp
;
4957 i
.types
[i
.operands
] = imm8
;
4959 /* If VexW1 is set, the first operand is the source and
4960 the second operand is encoded in the immediate operand. */
4961 if (i
.tm
.opcode_modifier
.vexw1
)
4971 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4972 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4974 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4975 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4977 exp
->X_op
= O_constant
;
4979 = ((i
.op
[reg
].regs
->reg_num
4980 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4981 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4986 /* i.reg_operands MUST be the number of real register operands;
4987 implicit registers do not count. If there are 3 register
4988 operands, it must be a instruction with VexNDS. For a
4989 instruction with VexNDD, the destination register is encoded
4990 in VEX prefix. If there are 4 register operands, it must be
4991 a instruction with VEX prefix and 3 sources. */
4992 if (i
.mem_operands
== 0
4993 && ((i
.reg_operands
== 2
4994 && !i
.tm
.opcode_modifier
.vexndd
4995 && !i
.tm
.opcode_modifier
.vexlwp
)
4996 || (i
.reg_operands
== 3
4997 && i
.tm
.opcode_modifier
.vexnds
)
4998 || (i
.reg_operands
== 4 && vex_3_sources
)))
5006 /* When there are 3 operands, one of them may be immediate,
5007 which may be the first or the last operand. Otherwise,
5008 the first operand must be shift count register (cl) or it
5009 is an instruction with VexNDS. */
5010 gas_assert (i
.imm_operands
== 1
5011 || (i
.imm_operands
== 0
5012 && (i
.tm
.opcode_modifier
.vexnds
5013 || i
.types
[0].bitfield
.shiftcount
)));
5014 if (operand_type_check (i
.types
[0], imm
)
5015 || i
.types
[0].bitfield
.shiftcount
)
5021 /* When there are 4 operands, the first two must be 8bit
5022 immediate operands. The source operand will be the 3rd
5025 For instructions with VexNDS, if the first operand
5026 an imm8, the source operand is the 2nd one. If the last
5027 operand is imm8, the source operand is the first one. */
5028 gas_assert ((i
.imm_operands
== 2
5029 && i
.types
[0].bitfield
.imm8
5030 && i
.types
[1].bitfield
.imm8
)
5031 || (i
.tm
.opcode_modifier
.vexnds
5032 && i
.imm_operands
== 1
5033 && (i
.types
[0].bitfield
.imm8
5034 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5035 if (i
.tm
.opcode_modifier
.vexnds
)
5037 if (i
.types
[0].bitfield
.imm8
)
5055 if (i
.tm
.opcode_modifier
.vexnds
)
5057 /* For instructions with VexNDS, the register-only
5058 source operand must be XMM or YMM register. It is
5059 encoded in VEX prefix. We need to clear RegMem bit
5060 before calling operand_type_equal. */
5061 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5062 op
.bitfield
.regmem
= 0;
5063 if ((dest
+ 1) >= i
.operands
5064 || (!operand_type_equal (&op
, ®xmm
)
5065 && !operand_type_equal (&op
, ®ymm
)))
5067 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5073 /* One of the register operands will be encoded in the i.tm.reg
5074 field, the other in the combined i.tm.mode and i.tm.regmem
5075 fields. If no form of this instruction supports a memory
5076 destination operand, then we assume the source operand may
5077 sometimes be a memory operand and so we need to store the
5078 destination in the i.rm.reg field. */
5079 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5080 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5082 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5083 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5084 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5086 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5091 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5092 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5093 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5095 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5098 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5100 if (!i
.types
[0].bitfield
.control
5101 && !i
.types
[1].bitfield
.control
)
5103 i
.rex
&= ~(REX_R
| REX_B
);
5104 add_prefix (LOCK_PREFIX_OPCODE
);
5108 { /* If it's not 2 reg operands... */
5113 unsigned int fake_zero_displacement
= 0;
5116 for (op
= 0; op
< i
.operands
; op
++)
5117 if (operand_type_check (i
.types
[op
], anymem
))
5119 gas_assert (op
< i
.operands
);
5123 if (i
.base_reg
== 0)
5126 if (!i
.disp_operands
)
5127 fake_zero_displacement
= 1;
5128 if (i
.index_reg
== 0)
5130 /* Operand is just <disp> */
5131 if (flag_code
== CODE_64BIT
)
5133 /* 64bit mode overwrites the 32bit absolute
5134 addressing by RIP relative addressing and
5135 absolute addressing is encoded by one of the
5136 redundant SIB forms. */
5137 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5138 i
.sib
.base
= NO_BASE_REGISTER
;
5139 i
.sib
.index
= NO_INDEX_REGISTER
;
5140 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5141 ? disp32s
: disp32
);
5143 else if ((flag_code
== CODE_16BIT
)
5144 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5146 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5147 i
.types
[op
] = disp16
;
5151 i
.rm
.regmem
= NO_BASE_REGISTER
;
5152 i
.types
[op
] = disp32
;
5155 else /* !i.base_reg && i.index_reg */
5157 if (i
.index_reg
->reg_num
== RegEiz
5158 || i
.index_reg
->reg_num
== RegRiz
)
5159 i
.sib
.index
= NO_INDEX_REGISTER
;
5161 i
.sib
.index
= i
.index_reg
->reg_num
;
5162 i
.sib
.base
= NO_BASE_REGISTER
;
5163 i
.sib
.scale
= i
.log2_scale_factor
;
5164 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5165 i
.types
[op
].bitfield
.disp8
= 0;
5166 i
.types
[op
].bitfield
.disp16
= 0;
5167 i
.types
[op
].bitfield
.disp64
= 0;
5168 if (flag_code
!= CODE_64BIT
)
5170 /* Must be 32 bit */
5171 i
.types
[op
].bitfield
.disp32
= 1;
5172 i
.types
[op
].bitfield
.disp32s
= 0;
5176 i
.types
[op
].bitfield
.disp32
= 0;
5177 i
.types
[op
].bitfield
.disp32s
= 1;
5179 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5183 /* RIP addressing for 64bit mode. */
5184 else if (i
.base_reg
->reg_num
== RegRip
||
5185 i
.base_reg
->reg_num
== RegEip
)
5187 i
.rm
.regmem
= NO_BASE_REGISTER
;
5188 i
.types
[op
].bitfield
.disp8
= 0;
5189 i
.types
[op
].bitfield
.disp16
= 0;
5190 i
.types
[op
].bitfield
.disp32
= 0;
5191 i
.types
[op
].bitfield
.disp32s
= 1;
5192 i
.types
[op
].bitfield
.disp64
= 0;
5193 i
.flags
[op
] |= Operand_PCrel
;
5194 if (! i
.disp_operands
)
5195 fake_zero_displacement
= 1;
5197 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5199 switch (i
.base_reg
->reg_num
)
5202 if (i
.index_reg
== 0)
5204 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5205 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5209 if (i
.index_reg
== 0)
5212 if (operand_type_check (i
.types
[op
], disp
) == 0)
5214 /* fake (%bp) into 0(%bp) */
5215 i
.types
[op
].bitfield
.disp8
= 1;
5216 fake_zero_displacement
= 1;
5219 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5220 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5222 default: /* (%si) -> 4 or (%di) -> 5 */
5223 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5225 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5227 else /* i.base_reg and 32/64 bit mode */
5229 if (flag_code
== CODE_64BIT
5230 && operand_type_check (i
.types
[op
], disp
))
5232 i386_operand_type temp
;
5233 operand_type_set (&temp
, 0);
5234 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5236 if (i
.prefix
[ADDR_PREFIX
] == 0)
5237 i
.types
[op
].bitfield
.disp32s
= 1;
5239 i
.types
[op
].bitfield
.disp32
= 1;
5242 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5243 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5245 i
.sib
.base
= i
.base_reg
->reg_num
;
5246 /* x86-64 ignores REX prefix bit here to avoid decoder
5248 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5251 if (i
.disp_operands
== 0)
5253 fake_zero_displacement
= 1;
5254 i
.types
[op
].bitfield
.disp8
= 1;
5257 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5261 i
.sib
.scale
= i
.log2_scale_factor
;
5262 if (i
.index_reg
== 0)
5264 /* <disp>(%esp) becomes two byte modrm with no index
5265 register. We've already stored the code for esp
5266 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5267 Any base register besides %esp will not use the
5268 extra modrm byte. */
5269 i
.sib
.index
= NO_INDEX_REGISTER
;
5273 if (i
.index_reg
->reg_num
== RegEiz
5274 || i
.index_reg
->reg_num
== RegRiz
)
5275 i
.sib
.index
= NO_INDEX_REGISTER
;
5277 i
.sib
.index
= i
.index_reg
->reg_num
;
5278 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5279 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5284 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5285 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5288 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5291 if (fake_zero_displacement
)
5293 /* Fakes a zero displacement assuming that i.types[op]
5294 holds the correct displacement size. */
5297 gas_assert (i
.op
[op
].disps
== 0);
5298 exp
= &disp_expressions
[i
.disp_operands
++];
5299 i
.op
[op
].disps
= exp
;
5300 exp
->X_op
= O_constant
;
5301 exp
->X_add_number
= 0;
5302 exp
->X_add_symbol
= (symbolS
*) 0;
5303 exp
->X_op_symbol
= (symbolS
*) 0;
5313 if (operand_type_check (i
.types
[0], imm
))
5314 i
.vex
.register_specifier
= NULL
;
5317 /* VEX.vvvv encodes one of the sources when the first
5318 operand is not an immediate. */
5319 if (i
.tm
.opcode_modifier
.vexw0
)
5320 i
.vex
.register_specifier
= i
.op
[0].regs
;
5322 i
.vex
.register_specifier
= i
.op
[1].regs
;
5325 /* Destination is a XMM register encoded in the ModRM.reg
5327 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5328 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5331 /* ModRM.rm and VEX.B encodes the other source. */
5332 if (!i
.mem_operands
)
5336 if (i
.tm
.opcode_modifier
.vexw0
)
5337 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5339 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5341 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5345 else if (i
.tm
.opcode_modifier
.vexlwp
)
5347 i
.vex
.register_specifier
= i
.op
[2].regs
;
5348 if (!i
.mem_operands
)
5351 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5352 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5356 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5357 (if any) based on i.tm.extension_opcode. Again, we must be
5358 careful to make sure that segment/control/debug/test/MMX
5359 registers are coded into the i.rm.reg field. */
5360 else if (i
.reg_operands
)
5363 unsigned int vex_reg
= ~0;
5365 for (op
= 0; op
< i
.operands
; op
++)
5366 if (i
.types
[op
].bitfield
.reg8
5367 || i
.types
[op
].bitfield
.reg16
5368 || i
.types
[op
].bitfield
.reg32
5369 || i
.types
[op
].bitfield
.reg64
5370 || i
.types
[op
].bitfield
.regmmx
5371 || i
.types
[op
].bitfield
.regxmm
5372 || i
.types
[op
].bitfield
.regymm
5373 || i
.types
[op
].bitfield
.sreg2
5374 || i
.types
[op
].bitfield
.sreg3
5375 || i
.types
[op
].bitfield
.control
5376 || i
.types
[op
].bitfield
.debug
5377 || i
.types
[op
].bitfield
.test
)
5382 else if (i
.tm
.opcode_modifier
.vexnds
)
5384 /* For instructions with VexNDS, the register-only
5385 source operand is encoded in VEX prefix. */
5386 gas_assert (mem
!= (unsigned int) ~0);
5391 gas_assert (op
< i
.operands
);
5396 gas_assert (vex_reg
< i
.operands
);
5399 else if (i
.tm
.opcode_modifier
.vexndd
)
5401 /* For instructions with VexNDD, there should be
5402 no memory operand and the register destination
5403 is encoded in VEX prefix. */
5404 gas_assert (i
.mem_operands
== 0
5405 && (op
+ 2) == i
.operands
);
5409 gas_assert (op
< i
.operands
);
5411 if (vex_reg
!= (unsigned int) ~0)
5413 gas_assert (i
.reg_operands
== 2);
5415 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5417 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5421 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5424 /* Don't set OP operand twice. */
5427 /* If there is an extension opcode to put here, the
5428 register number must be put into the regmem field. */
5429 if (i
.tm
.extension_opcode
!= None
)
5431 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5432 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5437 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5438 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5443 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5444 must set it to 3 to indicate this is a register operand
5445 in the regmem field. */
5446 if (!i
.mem_operands
)
5450 /* Fill in i.rm.reg field with extension opcode (if any). */
5451 if (i
.tm
.extension_opcode
!= None
)
5452 i
.rm
.reg
= i
.tm
.extension_opcode
;
5458 output_branch (void)
5463 relax_substateT subtype
;
5468 if (flag_code
== CODE_16BIT
)
5472 if (i
.prefix
[DATA_PREFIX
] != 0)
5478 /* Pentium4 branch hints. */
5479 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5480 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5485 if (i
.prefix
[REX_PREFIX
] != 0)
5491 if (i
.prefixes
!= 0 && !intel_syntax
)
5492 as_warn (_("skipping prefixes on this instruction"));
5494 /* It's always a symbol; End frag & setup for relax.
5495 Make sure there is enough room in this frag for the largest
5496 instruction we may generate in md_convert_frag. This is 2
5497 bytes for the opcode and room for the prefix and largest
5499 frag_grow (prefix
+ 2 + 4);
5500 /* Prefix and 1 opcode byte go in fr_fix. */
5501 p
= frag_more (prefix
+ 1);
5502 if (i
.prefix
[DATA_PREFIX
] != 0)
5503 *p
++ = DATA_PREFIX_OPCODE
;
5504 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5505 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5506 *p
++ = i
.prefix
[SEG_PREFIX
];
5507 if (i
.prefix
[REX_PREFIX
] != 0)
5508 *p
++ = i
.prefix
[REX_PREFIX
];
5509 *p
= i
.tm
.base_opcode
;
5511 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5512 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5513 else if (cpu_arch_flags
.bitfield
.cpui386
)
5514 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5516 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5519 sym
= i
.op
[0].disps
->X_add_symbol
;
5520 off
= i
.op
[0].disps
->X_add_number
;
5522 if (i
.op
[0].disps
->X_op
!= O_constant
5523 && i
.op
[0].disps
->X_op
!= O_symbol
)
5525 /* Handle complex expressions. */
5526 sym
= make_expr_symbol (i
.op
[0].disps
);
5530 /* 1 possible extra opcode + 4 byte displacement go in var part.
5531 Pass reloc in fr_var. */
5532 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5542 if (i
.tm
.opcode_modifier
.jumpbyte
)
5544 /* This is a loop or jecxz type instruction. */
5546 if (i
.prefix
[ADDR_PREFIX
] != 0)
5548 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5551 /* Pentium4 branch hints. */
5552 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5553 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5555 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5564 if (flag_code
== CODE_16BIT
)
5567 if (i
.prefix
[DATA_PREFIX
] != 0)
5569 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5579 if (i
.prefix
[REX_PREFIX
] != 0)
5581 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5585 if (i
.prefixes
!= 0 && !intel_syntax
)
5586 as_warn (_("skipping prefixes on this instruction"));
5588 p
= frag_more (1 + size
);
5589 *p
++ = i
.tm
.base_opcode
;
5591 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5592 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5594 /* All jumps handled here are signed, but don't use a signed limit
5595 check for 32 and 16 bit jumps as we want to allow wrap around at
5596 4G and 64k respectively. */
5598 fixP
->fx_signed
= 1;
5602 output_interseg_jump (void)
5610 if (flag_code
== CODE_16BIT
)
5614 if (i
.prefix
[DATA_PREFIX
] != 0)
5620 if (i
.prefix
[REX_PREFIX
] != 0)
5630 if (i
.prefixes
!= 0 && !intel_syntax
)
5631 as_warn (_("skipping prefixes on this instruction"));
5633 /* 1 opcode; 2 segment; offset */
5634 p
= frag_more (prefix
+ 1 + 2 + size
);
5636 if (i
.prefix
[DATA_PREFIX
] != 0)
5637 *p
++ = DATA_PREFIX_OPCODE
;
5639 if (i
.prefix
[REX_PREFIX
] != 0)
5640 *p
++ = i
.prefix
[REX_PREFIX
];
5642 *p
++ = i
.tm
.base_opcode
;
5643 if (i
.op
[1].imms
->X_op
== O_constant
)
5645 offsetT n
= i
.op
[1].imms
->X_add_number
;
5648 && !fits_in_unsigned_word (n
)
5649 && !fits_in_signed_word (n
))
5651 as_bad (_("16-bit jump out of range"));
5654 md_number_to_chars (p
, n
, size
);
5657 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5658 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5659 if (i
.op
[0].imms
->X_op
!= O_constant
)
5660 as_bad (_("can't handle non absolute segment in `%s'"),
5662 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5668 fragS
*insn_start_frag
;
5669 offsetT insn_start_off
;
5671 /* Tie dwarf2 debug info to the address at the start of the insn.
5672 We can't do this after the insn has been output as the current
5673 frag may have been closed off. eg. by frag_var. */
5674 dwarf2_emit_insn (0);
5676 insn_start_frag
= frag_now
;
5677 insn_start_off
= frag_now_fix ();
5680 if (i
.tm
.opcode_modifier
.jump
)
5682 else if (i
.tm
.opcode_modifier
.jumpbyte
5683 || i
.tm
.opcode_modifier
.jumpdword
)
5685 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5686 output_interseg_jump ();
5689 /* Output normal instructions here. */
5693 unsigned int prefix
;
5695 /* Since the VEX prefix contains the implicit prefix, we don't
5696 need the explicit prefix. */
5697 if (!i
.tm
.opcode_modifier
.vex
)
5699 switch (i
.tm
.opcode_length
)
5702 if (i
.tm
.base_opcode
& 0xff000000)
5704 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5709 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5711 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5712 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5715 if (prefix
!= REPE_PREFIX_OPCODE
5716 || (i
.prefix
[REP_PREFIX
]
5717 != REPE_PREFIX_OPCODE
))
5718 add_prefix (prefix
);
5721 add_prefix (prefix
);
5730 /* The prefix bytes. */
5731 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5733 FRAG_APPEND_1_CHAR (*q
);
5736 if (i
.tm
.opcode_modifier
.vex
)
5738 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5743 /* REX byte is encoded in VEX prefix. */
5747 FRAG_APPEND_1_CHAR (*q
);
5750 /* There should be no other prefixes for instructions
5755 /* Now the VEX prefix. */
5756 p
= frag_more (i
.vex
.length
);
5757 for (j
= 0; j
< i
.vex
.length
; j
++)
5758 p
[j
] = i
.vex
.bytes
[j
];
5761 /* Now the opcode; be careful about word order here! */
5762 if (i
.tm
.opcode_length
== 1)
5764 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5768 switch (i
.tm
.opcode_length
)
5772 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5782 /* Put out high byte first: can't use md_number_to_chars! */
5783 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5784 *p
= i
.tm
.base_opcode
& 0xff;
5787 /* Now the modrm byte and sib byte (if present). */
5788 if (i
.tm
.opcode_modifier
.modrm
)
5790 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5793 /* If i.rm.regmem == ESP (4)
5794 && i.rm.mode != (Register mode)
5796 ==> need second modrm byte. */
5797 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5799 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5800 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5802 | i
.sib
.scale
<< 6));
5805 if (i
.disp_operands
)
5806 output_disp (insn_start_frag
, insn_start_off
);
5809 output_imm (insn_start_frag
, insn_start_off
);
5815 pi ("" /*line*/, &i
);
5817 #endif /* DEBUG386 */
5820 /* Return the size of the displacement operand N. */
5823 disp_size (unsigned int n
)
5826 if (i
.types
[n
].bitfield
.disp64
)
5828 else if (i
.types
[n
].bitfield
.disp8
)
5830 else if (i
.types
[n
].bitfield
.disp16
)
5835 /* Return the size of the immediate operand N. */
5838 imm_size (unsigned int n
)
5841 if (i
.types
[n
].bitfield
.imm64
)
5843 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5845 else if (i
.types
[n
].bitfield
.imm16
)
5851 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5856 for (n
= 0; n
< i
.operands
; n
++)
5858 if (operand_type_check (i
.types
[n
], disp
))
5860 if (i
.op
[n
].disps
->X_op
== O_constant
)
5862 int size
= disp_size (n
);
5865 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5867 p
= frag_more (size
);
5868 md_number_to_chars (p
, val
, size
);
5872 enum bfd_reloc_code_real reloc_type
;
5873 int size
= disp_size (n
);
5874 int sign
= i
.types
[n
].bitfield
.disp32s
;
5875 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5877 /* We can't have 8 bit displacement here. */
5878 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5880 /* The PC relative address is computed relative
5881 to the instruction boundary, so in case immediate
5882 fields follows, we need to adjust the value. */
5883 if (pcrel
&& i
.imm_operands
)
5888 for (n1
= 0; n1
< i
.operands
; n1
++)
5889 if (operand_type_check (i
.types
[n1
], imm
))
5891 /* Only one immediate is allowed for PC
5892 relative address. */
5893 gas_assert (sz
== 0);
5895 i
.op
[n
].disps
->X_add_number
-= sz
;
5897 /* We should find the immediate. */
5898 gas_assert (sz
!= 0);
5901 p
= frag_more (size
);
5902 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5904 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5905 && (((reloc_type
== BFD_RELOC_32
5906 || reloc_type
== BFD_RELOC_X86_64_32S
5907 || (reloc_type
== BFD_RELOC_64
5909 && (i
.op
[n
].disps
->X_op
== O_symbol
5910 || (i
.op
[n
].disps
->X_op
== O_add
5911 && ((symbol_get_value_expression
5912 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5914 || reloc_type
== BFD_RELOC_32_PCREL
))
5918 if (insn_start_frag
== frag_now
)
5919 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5924 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5925 for (fr
= insn_start_frag
->fr_next
;
5926 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5928 add
+= p
- frag_now
->fr_literal
;
5933 reloc_type
= BFD_RELOC_386_GOTPC
;
5934 i
.op
[n
].imms
->X_add_number
+= add
;
5936 else if (reloc_type
== BFD_RELOC_64
)
5937 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5939 /* Don't do the adjustment for x86-64, as there
5940 the pcrel addressing is relative to the _next_
5941 insn, and that is taken care of in other code. */
5942 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5944 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5945 i
.op
[n
].disps
, pcrel
, reloc_type
);
5952 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5957 for (n
= 0; n
< i
.operands
; n
++)
5959 if (operand_type_check (i
.types
[n
], imm
))
5961 if (i
.op
[n
].imms
->X_op
== O_constant
)
5963 int size
= imm_size (n
);
5966 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5968 p
= frag_more (size
);
5969 md_number_to_chars (p
, val
, size
);
5973 /* Not absolute_section.
5974 Need a 32-bit fixup (don't support 8bit
5975 non-absolute imms). Try to support other
5977 enum bfd_reloc_code_real reloc_type
;
5978 int size
= imm_size (n
);
5981 if (i
.types
[n
].bitfield
.imm32s
5982 && (i
.suffix
== QWORD_MNEM_SUFFIX
5983 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5988 p
= frag_more (size
);
5989 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5991 /* This is tough to explain. We end up with this one if we
5992 * have operands that look like
5993 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5994 * obtain the absolute address of the GOT, and it is strongly
5995 * preferable from a performance point of view to avoid using
5996 * a runtime relocation for this. The actual sequence of
5997 * instructions often look something like:
6002 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6004 * The call and pop essentially return the absolute address
6005 * of the label .L66 and store it in %ebx. The linker itself
6006 * will ultimately change the first operand of the addl so
6007 * that %ebx points to the GOT, but to keep things simple, the
6008 * .o file must have this operand set so that it generates not
6009 * the absolute address of .L66, but the absolute address of
6010 * itself. This allows the linker itself simply treat a GOTPC
6011 * relocation as asking for a pcrel offset to the GOT to be
6012 * added in, and the addend of the relocation is stored in the
6013 * operand field for the instruction itself.
6015 * Our job here is to fix the operand so that it would add
6016 * the correct offset so that %ebx would point to itself. The
6017 * thing that is tricky is that .-.L66 will point to the
6018 * beginning of the instruction, so we need to further modify
6019 * the operand so that it will point to itself. There are
6020 * other cases where you have something like:
6022 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6024 * and here no correction would be required. Internally in
6025 * the assembler we treat operands of this form as not being
6026 * pcrel since the '.' is explicitly mentioned, and I wonder
6027 * whether it would simplify matters to do it this way. Who
6028 * knows. In earlier versions of the PIC patches, the
6029 * pcrel_adjust field was used to store the correction, but
6030 * since the expression is not pcrel, I felt it would be
6031 * confusing to do it this way. */
6033 if ((reloc_type
== BFD_RELOC_32
6034 || reloc_type
== BFD_RELOC_X86_64_32S
6035 || reloc_type
== BFD_RELOC_64
)
6037 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6038 && (i
.op
[n
].imms
->X_op
== O_symbol
6039 || (i
.op
[n
].imms
->X_op
== O_add
6040 && ((symbol_get_value_expression
6041 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6046 if (insn_start_frag
== frag_now
)
6047 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6052 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6053 for (fr
= insn_start_frag
->fr_next
;
6054 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6056 add
+= p
- frag_now
->fr_literal
;
6060 reloc_type
= BFD_RELOC_386_GOTPC
;
6062 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6064 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6065 i
.op
[n
].imms
->X_add_number
+= add
;
6067 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6068 i
.op
[n
].imms
, 0, reloc_type
);
6074 /* x86_cons_fix_new is called via the expression parsing code when a
6075 reloc is needed. We use this hook to get the correct .got reloc. */
6076 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6077 static int cons_sign
= -1;
6080 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6083 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6085 got_reloc
= NO_RELOC
;
6088 if (exp
->X_op
== O_secrel
)
6090 exp
->X_op
= O_symbol
;
6091 r
= BFD_RELOC_32_SECREL
;
6095 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6098 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6099 # define lex_got(reloc, adjust, types) NULL
6101 /* Parse operands of the form
6102 <symbol>@GOTOFF+<nnn>
6103 and similar .plt or .got references.
6105 If we find one, set up the correct relocation in RELOC and copy the
6106 input string, minus the `@GOTOFF' into a malloc'd buffer for
6107 parsing by the calling routine. Return this buffer, and if ADJUST
6108 is non-null set it to the length of the string we removed from the
6109 input line. Otherwise return NULL. */
6111 lex_got (enum bfd_reloc_code_real
*reloc
,
6113 i386_operand_type
*types
)
6115 /* Some of the relocations depend on the size of what field is to
6116 be relocated. But in our callers i386_immediate and i386_displacement
6117 we don't yet know the operand size (this will be set by insn
6118 matching). Hence we record the word32 relocation here,
6119 and adjust the reloc according to the real size in reloc(). */
6120 static const struct {
6122 const enum bfd_reloc_code_real rel
[2];
6123 const i386_operand_type types64
;
6125 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6126 BFD_RELOC_X86_64_PLTOFF64
},
6127 OPERAND_TYPE_IMM64
},
6128 { "PLT", { BFD_RELOC_386_PLT32
,
6129 BFD_RELOC_X86_64_PLT32
},
6130 OPERAND_TYPE_IMM32_32S_DISP32
},
6131 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6132 BFD_RELOC_X86_64_GOTPLT64
},
6133 OPERAND_TYPE_IMM64_DISP64
},
6134 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6135 BFD_RELOC_X86_64_GOTOFF64
},
6136 OPERAND_TYPE_IMM64_DISP64
},
6137 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6138 BFD_RELOC_X86_64_GOTPCREL
},
6139 OPERAND_TYPE_IMM32_32S_DISP32
},
6140 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6141 BFD_RELOC_X86_64_TLSGD
},
6142 OPERAND_TYPE_IMM32_32S_DISP32
},
6143 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6144 _dummy_first_bfd_reloc_code_real
},
6145 OPERAND_TYPE_NONE
},
6146 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6147 BFD_RELOC_X86_64_TLSLD
},
6148 OPERAND_TYPE_IMM32_32S_DISP32
},
6149 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6150 BFD_RELOC_X86_64_GOTTPOFF
},
6151 OPERAND_TYPE_IMM32_32S_DISP32
},
6152 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6153 BFD_RELOC_X86_64_TPOFF32
},
6154 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6155 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6156 _dummy_first_bfd_reloc_code_real
},
6157 OPERAND_TYPE_NONE
},
6158 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6159 BFD_RELOC_X86_64_DTPOFF32
},
6161 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6162 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6163 _dummy_first_bfd_reloc_code_real
},
6164 OPERAND_TYPE_NONE
},
6165 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6166 _dummy_first_bfd_reloc_code_real
},
6167 OPERAND_TYPE_NONE
},
6168 { "GOT", { BFD_RELOC_386_GOT32
,
6169 BFD_RELOC_X86_64_GOT32
},
6170 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6171 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6172 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6173 OPERAND_TYPE_IMM32_32S_DISP32
},
6174 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6175 BFD_RELOC_X86_64_TLSDESC_CALL
},
6176 OPERAND_TYPE_IMM32_32S_DISP32
},
6184 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6185 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6188 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6192 len
= strlen (gotrel
[j
].str
);
6193 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6195 if (gotrel
[j
].rel
[object_64bit
] != 0)
6198 char *tmpbuf
, *past_reloc
;
6200 *reloc
= gotrel
[j
].rel
[object_64bit
];
6206 if (flag_code
!= CODE_64BIT
)
6208 types
->bitfield
.imm32
= 1;
6209 types
->bitfield
.disp32
= 1;
6212 *types
= gotrel
[j
].types64
;
6215 if (GOT_symbol
== NULL
)
6216 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6218 /* The length of the first part of our input line. */
6219 first
= cp
- input_line_pointer
;
6221 /* The second part goes from after the reloc token until
6222 (and including) an end_of_line char or comma. */
6223 past_reloc
= cp
+ 1 + len
;
6225 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6227 second
= cp
+ 1 - past_reloc
;
6229 /* Allocate and copy string. The trailing NUL shouldn't
6230 be necessary, but be safe. */
6231 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6232 memcpy (tmpbuf
, input_line_pointer
, first
);
6233 if (second
!= 0 && *past_reloc
!= ' ')
6234 /* Replace the relocation token with ' ', so that
6235 errors like foo@GOTOFF1 will be detected. */
6236 tmpbuf
[first
++] = ' ';
6237 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6238 tmpbuf
[first
+ second
] = '\0';
6242 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6243 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6248 /* Might be a symbol version string. Don't as_bad here. */
6253 x86_cons (expressionS
*exp
, int size
)
6255 intel_syntax
= -intel_syntax
;
6257 if (size
== 4 || (object_64bit
&& size
== 8))
6259 /* Handle @GOTOFF and the like in an expression. */
6261 char *gotfree_input_line
;
6264 save
= input_line_pointer
;
6265 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6266 if (gotfree_input_line
)
6267 input_line_pointer
= gotfree_input_line
;
6271 if (gotfree_input_line
)
6273 /* expression () has merrily parsed up to the end of line,
6274 or a comma - in the wrong buffer. Transfer how far
6275 input_line_pointer has moved to the right buffer. */
6276 input_line_pointer
= (save
6277 + (input_line_pointer
- gotfree_input_line
)
6279 free (gotfree_input_line
);
6280 if (exp
->X_op
== O_constant
6281 || exp
->X_op
== O_absent
6282 || exp
->X_op
== O_illegal
6283 || exp
->X_op
== O_register
6284 || exp
->X_op
== O_big
)
6286 char c
= *input_line_pointer
;
6287 *input_line_pointer
= 0;
6288 as_bad (_("missing or invalid expression `%s'"), save
);
6289 *input_line_pointer
= c
;
6296 intel_syntax
= -intel_syntax
;
6299 i386_intel_simplify (exp
);
6304 signed_cons (int size
)
6306 if (flag_code
== CODE_64BIT
)
6314 pe_directive_secrel (dummy
)
6315 int dummy ATTRIBUTE_UNUSED
;
6322 if (exp
.X_op
== O_symbol
)
6323 exp
.X_op
= O_secrel
;
6325 emit_expr (&exp
, 4);
6327 while (*input_line_pointer
++ == ',');
6329 input_line_pointer
--;
6330 demand_empty_rest_of_line ();
6335 i386_immediate (char *imm_start
)
6337 char *save_input_line_pointer
;
6338 char *gotfree_input_line
;
6341 i386_operand_type types
;
6343 operand_type_set (&types
, ~0);
6345 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6347 as_bad (_("at most %d immediate operands are allowed"),
6348 MAX_IMMEDIATE_OPERANDS
);
6352 exp
= &im_expressions
[i
.imm_operands
++];
6353 i
.op
[this_operand
].imms
= exp
;
6355 if (is_space_char (*imm_start
))
6358 save_input_line_pointer
= input_line_pointer
;
6359 input_line_pointer
= imm_start
;
6361 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6362 if (gotfree_input_line
)
6363 input_line_pointer
= gotfree_input_line
;
6365 exp_seg
= expression (exp
);
6368 if (*input_line_pointer
)
6369 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6371 input_line_pointer
= save_input_line_pointer
;
6372 if (gotfree_input_line
)
6374 free (gotfree_input_line
);
6376 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6377 exp
->X_op
= O_illegal
;
6380 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6384 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6385 i386_operand_type types
, const char *imm_start
)
6387 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6390 as_bad (_("missing or invalid immediate expression `%s'"),
6394 else if (exp
->X_op
== O_constant
)
6396 /* Size it properly later. */
6397 i
.types
[this_operand
].bitfield
.imm64
= 1;
6398 /* If BFD64, sign extend val. */
6399 if (!use_rela_relocations
6400 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6402 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6404 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6405 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6406 && exp_seg
!= absolute_section
6407 && exp_seg
!= text_section
6408 && exp_seg
!= data_section
6409 && exp_seg
!= bss_section
6410 && exp_seg
!= undefined_section
6411 && !bfd_is_com_section (exp_seg
))
6413 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6417 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6420 as_bad (_("illegal immediate register operand %s"), imm_start
);
6425 /* This is an address. The size of the address will be
6426 determined later, depending on destination register,
6427 suffix, or the default for the section. */
6428 i
.types
[this_operand
].bitfield
.imm8
= 1;
6429 i
.types
[this_operand
].bitfield
.imm16
= 1;
6430 i
.types
[this_operand
].bitfield
.imm32
= 1;
6431 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6432 i
.types
[this_operand
].bitfield
.imm64
= 1;
6433 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6441 i386_scale (char *scale
)
6444 char *save
= input_line_pointer
;
6446 input_line_pointer
= scale
;
6447 val
= get_absolute_expression ();
6452 i
.log2_scale_factor
= 0;
6455 i
.log2_scale_factor
= 1;
6458 i
.log2_scale_factor
= 2;
6461 i
.log2_scale_factor
= 3;
6465 char sep
= *input_line_pointer
;
6467 *input_line_pointer
= '\0';
6468 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6470 *input_line_pointer
= sep
;
6471 input_line_pointer
= save
;
6475 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6477 as_warn (_("scale factor of %d without an index register"),
6478 1 << i
.log2_scale_factor
);
6479 i
.log2_scale_factor
= 0;
6481 scale
= input_line_pointer
;
6482 input_line_pointer
= save
;
6487 i386_displacement (char *disp_start
, char *disp_end
)
6491 char *save_input_line_pointer
;
6492 char *gotfree_input_line
;
6494 i386_operand_type bigdisp
, types
= anydisp
;
6497 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6499 as_bad (_("at most %d displacement operands are allowed"),
6500 MAX_MEMORY_OPERANDS
);
6504 operand_type_set (&bigdisp
, 0);
6505 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6506 || (!current_templates
->start
->opcode_modifier
.jump
6507 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6509 bigdisp
.bitfield
.disp32
= 1;
6510 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6511 if (flag_code
== CODE_64BIT
)
6515 bigdisp
.bitfield
.disp32s
= 1;
6516 bigdisp
.bitfield
.disp64
= 1;
6519 else if ((flag_code
== CODE_16BIT
) ^ override
)
6521 bigdisp
.bitfield
.disp32
= 0;
6522 bigdisp
.bitfield
.disp16
= 1;
6527 /* For PC-relative branches, the width of the displacement
6528 is dependent upon data size, not address size. */
6529 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6530 if (flag_code
== CODE_64BIT
)
6532 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6533 bigdisp
.bitfield
.disp16
= 1;
6536 bigdisp
.bitfield
.disp32
= 1;
6537 bigdisp
.bitfield
.disp32s
= 1;
6543 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6545 : LONG_MNEM_SUFFIX
));
6546 bigdisp
.bitfield
.disp32
= 1;
6547 if ((flag_code
== CODE_16BIT
) ^ override
)
6549 bigdisp
.bitfield
.disp32
= 0;
6550 bigdisp
.bitfield
.disp16
= 1;
6554 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6557 exp
= &disp_expressions
[i
.disp_operands
];
6558 i
.op
[this_operand
].disps
= exp
;
6560 save_input_line_pointer
= input_line_pointer
;
6561 input_line_pointer
= disp_start
;
6562 END_STRING_AND_SAVE (disp_end
);
6564 #ifndef GCC_ASM_O_HACK
6565 #define GCC_ASM_O_HACK 0
6568 END_STRING_AND_SAVE (disp_end
+ 1);
6569 if (i
.types
[this_operand
].bitfield
.baseIndex
6570 && displacement_string_end
[-1] == '+')
6572 /* This hack is to avoid a warning when using the "o"
6573 constraint within gcc asm statements.
6576 #define _set_tssldt_desc(n,addr,limit,type) \
6577 __asm__ __volatile__ ( \
6579 "movw %w1,2+%0\n\t" \
6581 "movb %b1,4+%0\n\t" \
6582 "movb %4,5+%0\n\t" \
6583 "movb $0,6+%0\n\t" \
6584 "movb %h1,7+%0\n\t" \
6586 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6588 This works great except that the output assembler ends
6589 up looking a bit weird if it turns out that there is
6590 no offset. You end up producing code that looks like:
6603 So here we provide the missing zero. */
6605 *displacement_string_end
= '0';
6608 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6609 if (gotfree_input_line
)
6610 input_line_pointer
= gotfree_input_line
;
6612 exp_seg
= expression (exp
);
6615 if (*input_line_pointer
)
6616 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6618 RESTORE_END_STRING (disp_end
+ 1);
6620 input_line_pointer
= save_input_line_pointer
;
6621 if (gotfree_input_line
)
6623 free (gotfree_input_line
);
6625 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6626 exp
->X_op
= O_illegal
;
6629 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6631 RESTORE_END_STRING (disp_end
);
6637 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6638 i386_operand_type types
, const char *disp_start
)
6640 i386_operand_type bigdisp
;
6643 /* We do this to make sure that the section symbol is in
6644 the symbol table. We will ultimately change the relocation
6645 to be relative to the beginning of the section. */
6646 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6647 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6648 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6650 if (exp
->X_op
!= O_symbol
)
6653 if (S_IS_LOCAL (exp
->X_add_symbol
)
6654 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6655 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6656 exp
->X_op
= O_subtract
;
6657 exp
->X_op_symbol
= GOT_symbol
;
6658 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6659 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6660 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6661 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6663 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6666 else if (exp
->X_op
== O_absent
6667 || exp
->X_op
== O_illegal
6668 || exp
->X_op
== O_big
)
6671 as_bad (_("missing or invalid displacement expression `%s'"),
6676 else if (flag_code
== CODE_64BIT
6677 && !i
.prefix
[ADDR_PREFIX
]
6678 && exp
->X_op
== O_constant
)
6680 /* Since displacement is signed extended to 64bit, don't allow
6681 disp32 and turn off disp32s if they are out of range. */
6682 i
.types
[this_operand
].bitfield
.disp32
= 0;
6683 if (!fits_in_signed_long (exp
->X_add_number
))
6685 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6686 if (i
.types
[this_operand
].bitfield
.baseindex
)
6688 as_bad (_("0x%lx out range of signed 32bit displacement"),
6689 (long) exp
->X_add_number
);
6695 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6696 else if (exp
->X_op
!= O_constant
6697 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6698 && exp_seg
!= absolute_section
6699 && exp_seg
!= text_section
6700 && exp_seg
!= data_section
6701 && exp_seg
!= bss_section
6702 && exp_seg
!= undefined_section
6703 && !bfd_is_com_section (exp_seg
))
6705 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6710 /* Check if this is a displacement only operand. */
6711 bigdisp
= i
.types
[this_operand
];
6712 bigdisp
.bitfield
.disp8
= 0;
6713 bigdisp
.bitfield
.disp16
= 0;
6714 bigdisp
.bitfield
.disp32
= 0;
6715 bigdisp
.bitfield
.disp32s
= 0;
6716 bigdisp
.bitfield
.disp64
= 0;
6717 if (operand_type_all_zero (&bigdisp
))
6718 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6724 /* Make sure the memory operand we've been dealt is valid.
6725 Return 1 on success, 0 on a failure. */
6728 i386_index_check (const char *operand_string
)
6731 const char *kind
= "base/index";
6732 #if INFER_ADDR_PREFIX
6738 if (current_templates
->start
->opcode_modifier
.isstring
6739 && !current_templates
->start
->opcode_modifier
.immext
6740 && (current_templates
->end
[-1].opcode_modifier
.isstring
6743 /* Memory operands of string insns are special in that they only allow
6744 a single register (rDI, rSI, or rBX) as their memory address. */
6745 unsigned int expected
;
6747 kind
= "string address";
6749 if (current_templates
->start
->opcode_modifier
.w
)
6751 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6753 if (!type
.bitfield
.baseindex
6754 || ((!i
.mem_operands
!= !intel_syntax
)
6755 && current_templates
->end
[-1].operand_types
[1]
6756 .bitfield
.baseindex
))
6757 type
= current_templates
->end
[-1].operand_types
[1];
6758 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6761 expected
= 3 /* rBX */;
6763 if (!i
.base_reg
|| i
.index_reg
6764 || operand_type_check (i
.types
[this_operand
], disp
))
6766 else if (!(flag_code
== CODE_64BIT
6767 ? i
.prefix
[ADDR_PREFIX
]
6768 ? i
.base_reg
->reg_type
.bitfield
.reg32
6769 : i
.base_reg
->reg_type
.bitfield
.reg64
6770 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6771 ? i
.base_reg
->reg_type
.bitfield
.reg32
6772 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6774 else if (i
.base_reg
->reg_num
!= expected
)
6781 for (j
= 0; j
< i386_regtab_size
; ++j
)
6782 if ((flag_code
== CODE_64BIT
6783 ? i
.prefix
[ADDR_PREFIX
]
6784 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6785 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6786 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6787 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6788 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6789 && i386_regtab
[j
].reg_num
== expected
)
6791 gas_assert (j
< i386_regtab_size
);
6792 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6794 intel_syntax
? '[' : '(',
6796 i386_regtab
[j
].reg_name
,
6797 intel_syntax
? ']' : ')');
6801 else if (flag_code
== CODE_64BIT
)
6804 && ((i
.prefix
[ADDR_PREFIX
] == 0
6805 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6806 || (i
.prefix
[ADDR_PREFIX
]
6807 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6809 || i
.base_reg
->reg_num
!=
6810 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6812 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6813 || (i
.prefix
[ADDR_PREFIX
] == 0
6814 && i
.index_reg
->reg_num
!= RegRiz
6815 && !i
.index_reg
->reg_type
.bitfield
.reg64
6817 || (i
.prefix
[ADDR_PREFIX
]
6818 && i
.index_reg
->reg_num
!= RegEiz
6819 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6824 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6828 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6829 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6831 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6832 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6834 && i
.base_reg
->reg_num
< 6
6835 && i
.index_reg
->reg_num
>= 6
6836 && i
.log2_scale_factor
== 0))))
6843 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6845 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6846 && i
.index_reg
->reg_num
!= RegEiz
)
6847 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6853 #if INFER_ADDR_PREFIX
6854 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6856 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6858 /* Change the size of any displacement too. At most one of
6859 Disp16 or Disp32 is set.
6860 FIXME. There doesn't seem to be any real need for separate
6861 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6862 Removing them would probably clean up the code quite a lot. */
6863 if (flag_code
!= CODE_64BIT
6864 && (i
.types
[this_operand
].bitfield
.disp16
6865 || i
.types
[this_operand
].bitfield
.disp32
))
6866 i
.types
[this_operand
]
6867 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6872 as_bad (_("`%s' is not a valid %s expression"),
6877 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6879 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6880 ? flag_code
== CODE_32BIT
6889 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6893 i386_att_operand (char *operand_string
)
6897 char *op_string
= operand_string
;
6899 if (is_space_char (*op_string
))
6902 /* We check for an absolute prefix (differentiating,
6903 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6904 if (*op_string
== ABSOLUTE_PREFIX
)
6907 if (is_space_char (*op_string
))
6909 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6912 /* Check if operand is a register. */
6913 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6915 i386_operand_type temp
;
6917 /* Check for a segment override by searching for ':' after a
6918 segment register. */
6920 if (is_space_char (*op_string
))
6922 if (*op_string
== ':'
6923 && (r
->reg_type
.bitfield
.sreg2
6924 || r
->reg_type
.bitfield
.sreg3
))
6929 i
.seg
[i
.mem_operands
] = &es
;
6932 i
.seg
[i
.mem_operands
] = &cs
;
6935 i
.seg
[i
.mem_operands
] = &ss
;
6938 i
.seg
[i
.mem_operands
] = &ds
;
6941 i
.seg
[i
.mem_operands
] = &fs
;
6944 i
.seg
[i
.mem_operands
] = &gs
;
6948 /* Skip the ':' and whitespace. */
6950 if (is_space_char (*op_string
))
6953 if (!is_digit_char (*op_string
)
6954 && !is_identifier_char (*op_string
)
6955 && *op_string
!= '('
6956 && *op_string
!= ABSOLUTE_PREFIX
)
6958 as_bad (_("bad memory operand `%s'"), op_string
);
6961 /* Handle case of %es:*foo. */
6962 if (*op_string
== ABSOLUTE_PREFIX
)
6965 if (is_space_char (*op_string
))
6967 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6969 goto do_memory_reference
;
6973 as_bad (_("junk `%s' after register"), op_string
);
6977 temp
.bitfield
.baseindex
= 0;
6978 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6980 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6981 i
.op
[this_operand
].regs
= r
;
6984 else if (*op_string
== REGISTER_PREFIX
)
6986 as_bad (_("bad register name `%s'"), op_string
);
6989 else if (*op_string
== IMMEDIATE_PREFIX
)
6992 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6994 as_bad (_("immediate operand illegal with absolute jump"));
6997 if (!i386_immediate (op_string
))
7000 else if (is_digit_char (*op_string
)
7001 || is_identifier_char (*op_string
)
7002 || *op_string
== '(')
7004 /* This is a memory reference of some sort. */
7007 /* Start and end of displacement string expression (if found). */
7008 char *displacement_string_start
;
7009 char *displacement_string_end
;
7011 do_memory_reference
:
7012 if ((i
.mem_operands
== 1
7013 && !current_templates
->start
->opcode_modifier
.isstring
)
7014 || i
.mem_operands
== 2)
7016 as_bad (_("too many memory references for `%s'"),
7017 current_templates
->start
->name
);
7021 /* Check for base index form. We detect the base index form by
7022 looking for an ')' at the end of the operand, searching
7023 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7025 base_string
= op_string
+ strlen (op_string
);
7028 if (is_space_char (*base_string
))
7031 /* If we only have a displacement, set-up for it to be parsed later. */
7032 displacement_string_start
= op_string
;
7033 displacement_string_end
= base_string
+ 1;
7035 if (*base_string
== ')')
7038 unsigned int parens_balanced
= 1;
7039 /* We've already checked that the number of left & right ()'s are
7040 equal, so this loop will not be infinite. */
7044 if (*base_string
== ')')
7046 if (*base_string
== '(')
7049 while (parens_balanced
);
7051 temp_string
= base_string
;
7053 /* Skip past '(' and whitespace. */
7055 if (is_space_char (*base_string
))
7058 if (*base_string
== ','
7059 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7062 displacement_string_end
= temp_string
;
7064 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7068 base_string
= end_op
;
7069 if (is_space_char (*base_string
))
7073 /* There may be an index reg or scale factor here. */
7074 if (*base_string
== ',')
7077 if (is_space_char (*base_string
))
7080 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7083 base_string
= end_op
;
7084 if (is_space_char (*base_string
))
7086 if (*base_string
== ',')
7089 if (is_space_char (*base_string
))
7092 else if (*base_string
!= ')')
7094 as_bad (_("expecting `,' or `)' "
7095 "after index register in `%s'"),
7100 else if (*base_string
== REGISTER_PREFIX
)
7102 as_bad (_("bad register name `%s'"), base_string
);
7106 /* Check for scale factor. */
7107 if (*base_string
!= ')')
7109 char *end_scale
= i386_scale (base_string
);
7114 base_string
= end_scale
;
7115 if (is_space_char (*base_string
))
7117 if (*base_string
!= ')')
7119 as_bad (_("expecting `)' "
7120 "after scale factor in `%s'"),
7125 else if (!i
.index_reg
)
7127 as_bad (_("expecting index register or scale factor "
7128 "after `,'; got '%c'"),
7133 else if (*base_string
!= ')')
7135 as_bad (_("expecting `,' or `)' "
7136 "after base register in `%s'"),
7141 else if (*base_string
== REGISTER_PREFIX
)
7143 as_bad (_("bad register name `%s'"), base_string
);
7148 /* If there's an expression beginning the operand, parse it,
7149 assuming displacement_string_start and
7150 displacement_string_end are meaningful. */
7151 if (displacement_string_start
!= displacement_string_end
)
7153 if (!i386_displacement (displacement_string_start
,
7154 displacement_string_end
))
7158 /* Special case for (%dx) while doing input/output op. */
7160 && operand_type_equal (&i
.base_reg
->reg_type
,
7161 ®16_inoutportreg
)
7163 && i
.log2_scale_factor
== 0
7164 && i
.seg
[i
.mem_operands
] == 0
7165 && !operand_type_check (i
.types
[this_operand
], disp
))
7167 i
.types
[this_operand
] = inoutportreg
;
7171 if (i386_index_check (operand_string
) == 0)
7173 i
.types
[this_operand
].bitfield
.mem
= 1;
7178 /* It's not a memory operand; argh! */
7179 as_bad (_("invalid char %s beginning operand %d `%s'"),
7180 output_invalid (*op_string
),
7185 return 1; /* Normal return. */
7188 /* md_estimate_size_before_relax()
7190 Called just before relax() for rs_machine_dependent frags. The x86
7191 assembler uses these frags to handle variable size jump
7194 Any symbol that is now undefined will not become defined.
7195 Return the correct fr_subtype in the frag.
7196 Return the initial "guess for variable size of frag" to caller.
7197 The guess is actually the growth beyond the fixed part. Whatever
7198 we do to grow the fixed or variable part contributes to our
7202 md_estimate_size_before_relax (fragP
, segment
)
7206 /* We've already got fragP->fr_subtype right; all we have to do is
7207 check for un-relaxable symbols. On an ELF system, we can't relax
7208 an externally visible symbol, because it may be overridden by a
7210 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7211 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7213 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7214 || S_IS_WEAK (fragP
->fr_symbol
)
7215 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7216 & BSF_GNU_INDIRECT_FUNCTION
))))
7218 #if defined (OBJ_COFF) && defined (TE_PE)
7219 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7220 && S_IS_WEAK (fragP
->fr_symbol
))
7224 /* Symbol is undefined in this segment, or we need to keep a
7225 reloc so that weak symbols can be overridden. */
7226 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7227 enum bfd_reloc_code_real reloc_type
;
7228 unsigned char *opcode
;
7231 if (fragP
->fr_var
!= NO_RELOC
)
7232 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7234 reloc_type
= BFD_RELOC_16_PCREL
;
7236 reloc_type
= BFD_RELOC_32_PCREL
;
7238 old_fr_fix
= fragP
->fr_fix
;
7239 opcode
= (unsigned char *) fragP
->fr_opcode
;
7241 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7244 /* Make jmp (0xeb) a (d)word displacement jump. */
7246 fragP
->fr_fix
+= size
;
7247 fix_new (fragP
, old_fr_fix
, size
,
7249 fragP
->fr_offset
, 1,
7255 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7257 /* Negate the condition, and branch past an
7258 unconditional jump. */
7261 /* Insert an unconditional jump. */
7263 /* We added two extra opcode bytes, and have a two byte
7265 fragP
->fr_fix
+= 2 + 2;
7266 fix_new (fragP
, old_fr_fix
+ 2, 2,
7268 fragP
->fr_offset
, 1,
7275 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7280 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7282 fragP
->fr_offset
, 1,
7284 fixP
->fx_signed
= 1;
7288 /* This changes the byte-displacement jump 0x7N
7289 to the (d)word-displacement jump 0x0f,0x8N. */
7290 opcode
[1] = opcode
[0] + 0x10;
7291 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7292 /* We've added an opcode byte. */
7293 fragP
->fr_fix
+= 1 + size
;
7294 fix_new (fragP
, old_fr_fix
+ 1, size
,
7296 fragP
->fr_offset
, 1,
7301 BAD_CASE (fragP
->fr_subtype
);
7305 return fragP
->fr_fix
- old_fr_fix
;
7308 /* Guess size depending on current relax state. Initially the relax
7309 state will correspond to a short jump and we return 1, because
7310 the variable part of the frag (the branch offset) is one byte
7311 long. However, we can relax a section more than once and in that
7312 case we must either set fr_subtype back to the unrelaxed state,
7313 or return the value for the appropriate branch. */
7314 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7317 /* Called after relax() is finished.
7319 In: Address of frag.
7320 fr_type == rs_machine_dependent.
7321 fr_subtype is what the address relaxed to.
7323 Out: Any fixSs and constants are set up.
7324 Caller will turn frag into a ".space 0". */
7327 md_convert_frag (abfd
, sec
, fragP
)
7328 bfd
*abfd ATTRIBUTE_UNUSED
;
7329 segT sec ATTRIBUTE_UNUSED
;
7332 unsigned char *opcode
;
7333 unsigned char *where_to_put_displacement
= NULL
;
7334 offsetT target_address
;
7335 offsetT opcode_address
;
7336 unsigned int extension
= 0;
7337 offsetT displacement_from_opcode_start
;
7339 opcode
= (unsigned char *) fragP
->fr_opcode
;
7341 /* Address we want to reach in file space. */
7342 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7344 /* Address opcode resides at in file space. */
7345 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7347 /* Displacement from opcode start to fill into instruction. */
7348 displacement_from_opcode_start
= target_address
- opcode_address
;
7350 if ((fragP
->fr_subtype
& BIG
) == 0)
7352 /* Don't have to change opcode. */
7353 extension
= 1; /* 1 opcode + 1 displacement */
7354 where_to_put_displacement
= &opcode
[1];
7358 if (no_cond_jump_promotion
7359 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7360 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7361 _("long jump required"));
7363 switch (fragP
->fr_subtype
)
7365 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7366 extension
= 4; /* 1 opcode + 4 displacement */
7368 where_to_put_displacement
= &opcode
[1];
7371 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7372 extension
= 2; /* 1 opcode + 2 displacement */
7374 where_to_put_displacement
= &opcode
[1];
7377 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7378 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7379 extension
= 5; /* 2 opcode + 4 displacement */
7380 opcode
[1] = opcode
[0] + 0x10;
7381 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7382 where_to_put_displacement
= &opcode
[2];
7385 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7386 extension
= 3; /* 2 opcode + 2 displacement */
7387 opcode
[1] = opcode
[0] + 0x10;
7388 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7389 where_to_put_displacement
= &opcode
[2];
7392 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7397 where_to_put_displacement
= &opcode
[3];
7401 BAD_CASE (fragP
->fr_subtype
);
7406 /* If size if less then four we are sure that the operand fits,
7407 but if it's 4, then it could be that the displacement is larger
7409 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7411 && ((addressT
) (displacement_from_opcode_start
- extension
7412 + ((addressT
) 1 << 31))
7413 > (((addressT
) 2 << 31) - 1)))
7415 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7416 _("jump target out of range"));
7417 /* Make us emit 0. */
7418 displacement_from_opcode_start
= extension
;
7420 /* Now put displacement after opcode. */
7421 md_number_to_chars ((char *) where_to_put_displacement
,
7422 (valueT
) (displacement_from_opcode_start
- extension
),
7423 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7424 fragP
->fr_fix
+= extension
;
7427 /* Apply a fixup (fixS) to segment data, once it has been determined
7428 by our caller that we have all the info we need to fix it up.
7430 On the 386, immediates, displacements, and data pointers are all in
7431 the same (little-endian) format, so we don't need to care about which
7435 md_apply_fix (fixP
, valP
, seg
)
7436 /* The fix we're to put in. */
7438 /* Pointer to the value of the bits. */
7440 /* Segment fix is from. */
7441 segT seg ATTRIBUTE_UNUSED
;
7443 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7444 valueT value
= *valP
;
7446 #if !defined (TE_Mach)
7449 switch (fixP
->fx_r_type
)
7455 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7458 case BFD_RELOC_X86_64_32S
:
7459 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7462 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7465 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7470 if (fixP
->fx_addsy
!= NULL
7471 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7472 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7473 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7474 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7475 && !use_rela_relocations
)
7477 /* This is a hack. There should be a better way to handle this.
7478 This covers for the fact that bfd_install_relocation will
7479 subtract the current location (for partial_inplace, PC relative
7480 relocations); see more below. */
7484 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7487 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7489 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7492 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7495 || (symbol_section_p (fixP
->fx_addsy
)
7496 && sym_seg
!= absolute_section
))
7497 && !generic_force_reloc (fixP
))
7499 /* Yes, we add the values in twice. This is because
7500 bfd_install_relocation subtracts them out again. I think
7501 bfd_install_relocation is broken, but I don't dare change
7503 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7507 #if defined (OBJ_COFF) && defined (TE_PE)
7508 /* For some reason, the PE format does not store a
7509 section address offset for a PC relative symbol. */
7510 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7511 || S_IS_WEAK (fixP
->fx_addsy
))
7512 value
+= md_pcrel_from (fixP
);
7515 #if defined (OBJ_COFF) && defined (TE_PE)
7516 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7518 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7522 /* Fix a few things - the dynamic linker expects certain values here,
7523 and we must not disappoint it. */
7524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7525 if (IS_ELF
&& fixP
->fx_addsy
)
7526 switch (fixP
->fx_r_type
)
7528 case BFD_RELOC_386_PLT32
:
7529 case BFD_RELOC_X86_64_PLT32
:
7530 /* Make the jump instruction point to the address of the operand. At
7531 runtime we merely add the offset to the actual PLT entry. */
7535 case BFD_RELOC_386_TLS_GD
:
7536 case BFD_RELOC_386_TLS_LDM
:
7537 case BFD_RELOC_386_TLS_IE_32
:
7538 case BFD_RELOC_386_TLS_IE
:
7539 case BFD_RELOC_386_TLS_GOTIE
:
7540 case BFD_RELOC_386_TLS_GOTDESC
:
7541 case BFD_RELOC_X86_64_TLSGD
:
7542 case BFD_RELOC_X86_64_TLSLD
:
7543 case BFD_RELOC_X86_64_GOTTPOFF
:
7544 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7545 value
= 0; /* Fully resolved at runtime. No addend. */
7547 case BFD_RELOC_386_TLS_LE
:
7548 case BFD_RELOC_386_TLS_LDO_32
:
7549 case BFD_RELOC_386_TLS_LE_32
:
7550 case BFD_RELOC_X86_64_DTPOFF32
:
7551 case BFD_RELOC_X86_64_DTPOFF64
:
7552 case BFD_RELOC_X86_64_TPOFF32
:
7553 case BFD_RELOC_X86_64_TPOFF64
:
7554 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7557 case BFD_RELOC_386_TLS_DESC_CALL
:
7558 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7559 value
= 0; /* Fully resolved at runtime. No addend. */
7560 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7564 case BFD_RELOC_386_GOT32
:
7565 case BFD_RELOC_X86_64_GOT32
:
7566 value
= 0; /* Fully resolved at runtime. No addend. */
7569 case BFD_RELOC_VTABLE_INHERIT
:
7570 case BFD_RELOC_VTABLE_ENTRY
:
7577 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7579 #endif /* !defined (TE_Mach) */
7581 /* Are we finished with this relocation now? */
7582 if (fixP
->fx_addsy
== NULL
)
7584 #if defined (OBJ_COFF) && defined (TE_PE)
7585 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7588 /* Remember value for tc_gen_reloc. */
7589 fixP
->fx_addnumber
= value
;
7590 /* Clear out the frag for now. */
7594 else if (use_rela_relocations
)
7596 fixP
->fx_no_overflow
= 1;
7597 /* Remember value for tc_gen_reloc. */
7598 fixP
->fx_addnumber
= value
;
7602 md_number_to_chars (p
, value
, fixP
->fx_size
);
7606 md_atof (int type
, char *litP
, int *sizeP
)
7608 /* This outputs the LITTLENUMs in REVERSE order;
7609 in accord with the bigendian 386. */
7610 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7613 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7616 output_invalid (int c
)
7619 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7622 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7623 "(0x%x)", (unsigned char) c
);
7624 return output_invalid_buf
;
7627 /* REG_STRING starts *before* REGISTER_PREFIX. */
7629 static const reg_entry
*
7630 parse_real_register (char *reg_string
, char **end_op
)
7632 char *s
= reg_string
;
7634 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7637 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7638 if (*s
== REGISTER_PREFIX
)
7641 if (is_space_char (*s
))
7645 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7647 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7648 return (const reg_entry
*) NULL
;
7652 /* For naked regs, make sure that we are not dealing with an identifier.
7653 This prevents confusing an identifier like `eax_var' with register
7655 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7656 return (const reg_entry
*) NULL
;
7660 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7662 /* Handle floating point regs, allowing spaces in the (i) part. */
7663 if (r
== i386_regtab
/* %st is first entry of table */)
7665 if (is_space_char (*s
))
7670 if (is_space_char (*s
))
7672 if (*s
>= '0' && *s
<= '7')
7676 if (is_space_char (*s
))
7681 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7686 /* We have "%st(" then garbage. */
7687 return (const reg_entry
*) NULL
;
7691 if (r
== NULL
|| allow_pseudo_reg
)
7694 if (operand_type_all_zero (&r
->reg_type
))
7695 return (const reg_entry
*) NULL
;
7697 if ((r
->reg_type
.bitfield
.reg32
7698 || r
->reg_type
.bitfield
.sreg3
7699 || r
->reg_type
.bitfield
.control
7700 || r
->reg_type
.bitfield
.debug
7701 || r
->reg_type
.bitfield
.test
)
7702 && !cpu_arch_flags
.bitfield
.cpui386
)
7703 return (const reg_entry
*) NULL
;
7705 if (r
->reg_type
.bitfield
.floatreg
7706 && !cpu_arch_flags
.bitfield
.cpu8087
7707 && !cpu_arch_flags
.bitfield
.cpu287
7708 && !cpu_arch_flags
.bitfield
.cpu387
)
7709 return (const reg_entry
*) NULL
;
7711 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7712 return (const reg_entry
*) NULL
;
7714 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7715 return (const reg_entry
*) NULL
;
7717 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7718 return (const reg_entry
*) NULL
;
7720 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7721 if (!allow_index_reg
7722 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7723 return (const reg_entry
*) NULL
;
7725 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7726 || r
->reg_type
.bitfield
.reg64
)
7727 && (!cpu_arch_flags
.bitfield
.cpulm
7728 || !operand_type_equal (&r
->reg_type
, &control
))
7729 && flag_code
!= CODE_64BIT
)
7730 return (const reg_entry
*) NULL
;
7732 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7733 return (const reg_entry
*) NULL
;
7738 /* REG_STRING starts *before* REGISTER_PREFIX. */
7740 static const reg_entry
*
7741 parse_register (char *reg_string
, char **end_op
)
7745 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7746 r
= parse_real_register (reg_string
, end_op
);
7751 char *save
= input_line_pointer
;
7755 input_line_pointer
= reg_string
;
7756 c
= get_symbol_end ();
7757 symbolP
= symbol_find (reg_string
);
7758 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7760 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7762 know (e
->X_op
== O_register
);
7763 know (e
->X_add_number
>= 0
7764 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7765 r
= i386_regtab
+ e
->X_add_number
;
7766 *end_op
= input_line_pointer
;
7768 *input_line_pointer
= c
;
7769 input_line_pointer
= save
;
7775 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7778 char *end
= input_line_pointer
;
7781 r
= parse_register (name
, &input_line_pointer
);
7782 if (r
&& end
<= input_line_pointer
)
7784 *nextcharP
= *input_line_pointer
;
7785 *input_line_pointer
= 0;
7786 e
->X_op
= O_register
;
7787 e
->X_add_number
= r
- i386_regtab
;
7790 input_line_pointer
= end
;
7792 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7796 md_operand (expressionS
*e
)
7801 switch (*input_line_pointer
)
7803 case REGISTER_PREFIX
:
7804 r
= parse_real_register (input_line_pointer
, &end
);
7807 e
->X_op
= O_register
;
7808 e
->X_add_number
= r
- i386_regtab
;
7809 input_line_pointer
= end
;
7814 gas_assert (intel_syntax
);
7815 end
= input_line_pointer
++;
7817 if (*input_line_pointer
== ']')
7819 ++input_line_pointer
;
7820 e
->X_op_symbol
= make_expr_symbol (e
);
7821 e
->X_add_symbol
= NULL
;
7822 e
->X_add_number
= 0;
7828 input_line_pointer
= end
;
7835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7836 const char *md_shortopts
= "kVQ:sqn";
7838 const char *md_shortopts
= "qn";
7841 #define OPTION_32 (OPTION_MD_BASE + 0)
7842 #define OPTION_64 (OPTION_MD_BASE + 1)
7843 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7844 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7845 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7846 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7847 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7848 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7849 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7850 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7851 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7852 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7854 struct option md_longopts
[] =
7856 {"32", no_argument
, NULL
, OPTION_32
},
7857 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7858 || defined (TE_PE) || defined (TE_PEP))
7859 {"64", no_argument
, NULL
, OPTION_64
},
7861 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7862 {"march", required_argument
, NULL
, OPTION_MARCH
},
7863 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7864 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7865 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7866 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7867 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7868 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7869 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7870 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7871 {NULL
, no_argument
, NULL
, 0}
7873 size_t md_longopts_size
= sizeof (md_longopts
);
7876 md_parse_option (int c
, char *arg
)
7884 optimize_align_code
= 0;
7891 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7892 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7893 should be emitted or not. FIXME: Not implemented. */
7897 /* -V: SVR4 argument to print version ID. */
7899 print_version_id ();
7902 /* -k: Ignore for FreeBSD compatibility. */
7907 /* -s: On i386 Solaris, this tells the native assembler to use
7908 .stab instead of .stab.excl. We always use .stab anyhow. */
7911 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7912 || defined (TE_PE) || defined (TE_PEP))
7915 const char **list
, **l
;
7917 list
= bfd_target_list ();
7918 for (l
= list
; *l
!= NULL
; l
++)
7919 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7920 || strcmp (*l
, "coff-x86-64") == 0
7921 || strcmp (*l
, "pe-x86-64") == 0
7922 || strcmp (*l
, "pei-x86-64") == 0)
7924 default_arch
= "x86_64";
7928 as_fatal (_("No compiled in support for x86_64"));
7935 default_arch
= "i386";
7939 #ifdef SVR4_COMMENT_CHARS
7944 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7946 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7950 i386_comment_chars
= n
;
7956 arch
= xstrdup (arg
);
7960 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7961 next
= strchr (arch
, '+');
7964 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7966 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7969 cpu_arch_name
= cpu_arch
[i
].name
;
7970 cpu_sub_arch_name
= NULL
;
7971 cpu_arch_flags
= cpu_arch
[i
].flags
;
7972 cpu_arch_isa
= cpu_arch
[i
].type
;
7973 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7974 if (!cpu_arch_tune_set
)
7976 cpu_arch_tune
= cpu_arch_isa
;
7977 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7981 else if (*cpu_arch
[i
].name
== '.'
7982 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7984 /* ISA entension. */
7985 i386_cpu_flags flags
;
7987 if (strncmp (arch
, "no", 2))
7988 flags
= cpu_flags_or (cpu_arch_flags
,
7991 flags
= cpu_flags_and_not (cpu_arch_flags
,
7993 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7995 if (cpu_sub_arch_name
)
7997 char *name
= cpu_sub_arch_name
;
7998 cpu_sub_arch_name
= concat (name
,
8000 (const char *) NULL
);
8004 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8005 cpu_arch_flags
= flags
;
8011 if (i
>= ARRAY_SIZE (cpu_arch
))
8012 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8016 while (next
!= NULL
);
8021 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8022 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8024 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8026 cpu_arch_tune_set
= 1;
8027 cpu_arch_tune
= cpu_arch
[i
].type
;
8028 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8032 if (i
>= ARRAY_SIZE (cpu_arch
))
8033 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8036 case OPTION_MMNEMONIC
:
8037 if (strcasecmp (arg
, "att") == 0)
8039 else if (strcasecmp (arg
, "intel") == 0)
8042 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8045 case OPTION_MSYNTAX
:
8046 if (strcasecmp (arg
, "att") == 0)
8048 else if (strcasecmp (arg
, "intel") == 0)
8051 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8054 case OPTION_MINDEX_REG
:
8055 allow_index_reg
= 1;
8058 case OPTION_MNAKED_REG
:
8059 allow_naked_reg
= 1;
8062 case OPTION_MOLD_GCC
:
8066 case OPTION_MSSE2AVX
:
8070 case OPTION_MSSE_CHECK
:
8071 if (strcasecmp (arg
, "error") == 0)
8072 sse_check
= sse_check_error
;
8073 else if (strcasecmp (arg
, "warning") == 0)
8074 sse_check
= sse_check_warning
;
8075 else if (strcasecmp (arg
, "none") == 0)
8076 sse_check
= sse_check_none
;
8078 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8088 md_show_usage (stream
)
8091 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8092 fprintf (stream
, _("\
8094 -V print assembler version number\n\
8097 fprintf (stream
, _("\
8098 -n Do not optimize code alignment\n\
8099 -q quieten some warnings\n"));
8100 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8101 fprintf (stream
, _("\
8104 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8105 || defined (TE_PE) || defined (TE_PEP))
8106 fprintf (stream
, _("\
8107 --32/--64 generate 32bit/64bit code\n"));
8109 #ifdef SVR4_COMMENT_CHARS
8110 fprintf (stream
, _("\
8111 --divide do not treat `/' as a comment character\n"));
8113 fprintf (stream
, _("\
8114 --divide ignored\n"));
8116 fprintf (stream
, _("\
8117 -march=CPU[,+EXTENSION...]\n\
8118 generate code for CPU and EXTENSION, CPU is one of:\n\
8119 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8120 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8121 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8122 amdfam10, generic32, generic64\n\
8123 EXTENSION is combination of:\n\
8124 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8125 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8126 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8127 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8128 svme, abm, padlock, fma4, xop, lwp\n"));
8129 fprintf (stream
, _("\
8130 -mtune=CPU optimize for CPU, CPU is one of:\n\
8131 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8132 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8133 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8134 amdfam10, generic32, generic64\n"));
8135 fprintf (stream
, _("\
8136 -msse2avx encode SSE instructions with VEX prefix\n"));
8137 fprintf (stream
, _("\
8138 -msse-check=[none|error|warning]\n\
8139 check SSE instructions\n"));
8140 fprintf (stream
, _("\
8141 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8142 fprintf (stream
, _("\
8143 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8144 fprintf (stream
, _("\
8145 -mindex-reg support pseudo index registers\n"));
8146 fprintf (stream
, _("\
8147 -mnaked-reg don't require `%%' prefix for registers\n"));
8148 fprintf (stream
, _("\
8149 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8152 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8153 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8154 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8156 /* Pick the target format to use. */
8159 i386_target_format (void)
8161 if (!strcmp (default_arch
, "x86_64"))
8163 set_code_flag (CODE_64BIT
);
8164 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8166 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8167 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8168 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8169 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8170 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8171 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8172 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8173 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8174 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8175 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8176 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8178 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8180 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8181 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8182 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8183 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8184 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8185 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8186 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8187 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8188 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8189 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8192 else if (!strcmp (default_arch
, "i386"))
8194 set_code_flag (CODE_32BIT
);
8195 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8197 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8198 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8199 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8201 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8203 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8204 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8205 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8209 as_fatal (_("Unknown architecture"));
8210 switch (OUTPUT_FLAVOR
)
8212 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8213 case bfd_target_aout_flavour
:
8214 return AOUT_TARGET_FORMAT
;
8216 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8217 # if defined (TE_PE) || defined (TE_PEP)
8218 case bfd_target_coff_flavour
:
8219 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8220 # elif defined (TE_GO32)
8221 case bfd_target_coff_flavour
:
8224 case bfd_target_coff_flavour
:
8228 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8229 case bfd_target_elf_flavour
:
8231 if (flag_code
== CODE_64BIT
)
8234 use_rela_relocations
= 1;
8236 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8238 if (flag_code
!= CODE_64BIT
)
8239 as_fatal (_("Intel L1OM is 64bit only"));
8240 return ELF_TARGET_L1OM_FORMAT
;
8243 return (flag_code
== CODE_64BIT
8244 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8247 #if defined (OBJ_MACH_O)
8248 case bfd_target_mach_o_flavour
:
8249 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8257 #endif /* OBJ_MAYBE_ more than one */
8259 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8261 i386_elf_emit_arch_note (void)
8263 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8266 asection
*seg
= now_seg
;
8267 subsegT subseg
= now_subseg
;
8268 Elf_Internal_Note i_note
;
8269 Elf_External_Note e_note
;
8270 asection
*note_secp
;
8273 /* Create the .note section. */
8274 note_secp
= subseg_new (".note", 0);
8275 bfd_set_section_flags (stdoutput
,
8277 SEC_HAS_CONTENTS
| SEC_READONLY
);
8279 /* Process the arch string. */
8280 len
= strlen (cpu_arch_name
);
8282 i_note
.namesz
= len
+ 1;
8284 i_note
.type
= NT_ARCH
;
8285 p
= frag_more (sizeof (e_note
.namesz
));
8286 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8287 p
= frag_more (sizeof (e_note
.descsz
));
8288 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8289 p
= frag_more (sizeof (e_note
.type
));
8290 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8291 p
= frag_more (len
+ 1);
8292 strcpy (p
, cpu_arch_name
);
8294 frag_align (2, 0, 0);
8296 subseg_set (seg
, subseg
);
8302 md_undefined_symbol (name
)
8305 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8306 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8307 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8308 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8312 if (symbol_find (name
))
8313 as_bad (_("GOT already in symbol table"));
8314 GOT_symbol
= symbol_new (name
, undefined_section
,
8315 (valueT
) 0, &zero_address_frag
);
8322 /* Round up a section size to the appropriate boundary. */
8325 md_section_align (segment
, size
)
8326 segT segment ATTRIBUTE_UNUSED
;
8329 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8330 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8332 /* For a.out, force the section size to be aligned. If we don't do
8333 this, BFD will align it for us, but it will not write out the
8334 final bytes of the section. This may be a bug in BFD, but it is
8335 easier to fix it here since that is how the other a.out targets
8339 align
= bfd_get_section_alignment (stdoutput
, segment
);
8340 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8347 /* On the i386, PC-relative offsets are relative to the start of the
8348 next instruction. That is, the address of the offset, plus its
8349 size, since the offset is always the last part of the insn. */
8352 md_pcrel_from (fixS
*fixP
)
8354 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8360 s_bss (int ignore ATTRIBUTE_UNUSED
)
8364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8366 obj_elf_section_change_hook ();
8368 temp
= get_absolute_expression ();
8369 subseg_set (bss_section
, (subsegT
) temp
);
8370 demand_empty_rest_of_line ();
8376 i386_validate_fix (fixS
*fixp
)
8378 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8380 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8384 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8389 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8391 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8398 tc_gen_reloc (section
, fixp
)
8399 asection
*section ATTRIBUTE_UNUSED
;
8403 bfd_reloc_code_real_type code
;
8405 switch (fixp
->fx_r_type
)
8407 case BFD_RELOC_X86_64_PLT32
:
8408 case BFD_RELOC_X86_64_GOT32
:
8409 case BFD_RELOC_X86_64_GOTPCREL
:
8410 case BFD_RELOC_386_PLT32
:
8411 case BFD_RELOC_386_GOT32
:
8412 case BFD_RELOC_386_GOTOFF
:
8413 case BFD_RELOC_386_GOTPC
:
8414 case BFD_RELOC_386_TLS_GD
:
8415 case BFD_RELOC_386_TLS_LDM
:
8416 case BFD_RELOC_386_TLS_LDO_32
:
8417 case BFD_RELOC_386_TLS_IE_32
:
8418 case BFD_RELOC_386_TLS_IE
:
8419 case BFD_RELOC_386_TLS_GOTIE
:
8420 case BFD_RELOC_386_TLS_LE_32
:
8421 case BFD_RELOC_386_TLS_LE
:
8422 case BFD_RELOC_386_TLS_GOTDESC
:
8423 case BFD_RELOC_386_TLS_DESC_CALL
:
8424 case BFD_RELOC_X86_64_TLSGD
:
8425 case BFD_RELOC_X86_64_TLSLD
:
8426 case BFD_RELOC_X86_64_DTPOFF32
:
8427 case BFD_RELOC_X86_64_DTPOFF64
:
8428 case BFD_RELOC_X86_64_GOTTPOFF
:
8429 case BFD_RELOC_X86_64_TPOFF32
:
8430 case BFD_RELOC_X86_64_TPOFF64
:
8431 case BFD_RELOC_X86_64_GOTOFF64
:
8432 case BFD_RELOC_X86_64_GOTPC32
:
8433 case BFD_RELOC_X86_64_GOT64
:
8434 case BFD_RELOC_X86_64_GOTPCREL64
:
8435 case BFD_RELOC_X86_64_GOTPC64
:
8436 case BFD_RELOC_X86_64_GOTPLT64
:
8437 case BFD_RELOC_X86_64_PLTOFF64
:
8438 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8439 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8441 case BFD_RELOC_VTABLE_ENTRY
:
8442 case BFD_RELOC_VTABLE_INHERIT
:
8444 case BFD_RELOC_32_SECREL
:
8446 code
= fixp
->fx_r_type
;
8448 case BFD_RELOC_X86_64_32S
:
8449 if (!fixp
->fx_pcrel
)
8451 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8452 code
= fixp
->fx_r_type
;
8458 switch (fixp
->fx_size
)
8461 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8462 _("can not do %d byte pc-relative relocation"),
8464 code
= BFD_RELOC_32_PCREL
;
8466 case 1: code
= BFD_RELOC_8_PCREL
; break;
8467 case 2: code
= BFD_RELOC_16_PCREL
; break;
8468 case 4: code
= BFD_RELOC_32_PCREL
; break;
8470 case 8: code
= BFD_RELOC_64_PCREL
; break;
8476 switch (fixp
->fx_size
)
8479 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8480 _("can not do %d byte relocation"),
8482 code
= BFD_RELOC_32
;
8484 case 1: code
= BFD_RELOC_8
; break;
8485 case 2: code
= BFD_RELOC_16
; break;
8486 case 4: code
= BFD_RELOC_32
; break;
8488 case 8: code
= BFD_RELOC_64
; break;
8495 if ((code
== BFD_RELOC_32
8496 || code
== BFD_RELOC_32_PCREL
8497 || code
== BFD_RELOC_X86_64_32S
)
8499 && fixp
->fx_addsy
== GOT_symbol
)
8502 code
= BFD_RELOC_386_GOTPC
;
8504 code
= BFD_RELOC_X86_64_GOTPC32
;
8506 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8508 && fixp
->fx_addsy
== GOT_symbol
)
8510 code
= BFD_RELOC_X86_64_GOTPC64
;
8513 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8514 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8515 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8517 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8519 if (!use_rela_relocations
)
8521 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8522 vtable entry to be used in the relocation's section offset. */
8523 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8524 rel
->address
= fixp
->fx_offset
;
8525 #if defined (OBJ_COFF) && defined (TE_PE)
8526 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8527 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8532 /* Use the rela in 64bit mode. */
8535 if (!fixp
->fx_pcrel
)
8536 rel
->addend
= fixp
->fx_offset
;
8540 case BFD_RELOC_X86_64_PLT32
:
8541 case BFD_RELOC_X86_64_GOT32
:
8542 case BFD_RELOC_X86_64_GOTPCREL
:
8543 case BFD_RELOC_X86_64_TLSGD
:
8544 case BFD_RELOC_X86_64_TLSLD
:
8545 case BFD_RELOC_X86_64_GOTTPOFF
:
8546 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8547 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8548 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8551 rel
->addend
= (section
->vma
8553 + fixp
->fx_addnumber
8554 + md_pcrel_from (fixp
));
8559 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8560 if (rel
->howto
== NULL
)
8562 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8563 _("cannot represent relocation type %s"),
8564 bfd_get_reloc_code_name (code
));
8565 /* Set howto to a garbage value so that we can keep going. */
8566 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8567 gas_assert (rel
->howto
!= NULL
);
8573 #include "tc-i386-intel.c"
8576 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8578 int saved_naked_reg
;
8579 char saved_register_dot
;
8581 saved_naked_reg
= allow_naked_reg
;
8582 allow_naked_reg
= 1;
8583 saved_register_dot
= register_chars
['.'];
8584 register_chars
['.'] = '.';
8585 allow_pseudo_reg
= 1;
8586 expression_and_evaluate (exp
);
8587 allow_pseudo_reg
= 0;
8588 register_chars
['.'] = saved_register_dot
;
8589 allow_naked_reg
= saved_naked_reg
;
8591 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8593 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8595 exp
->X_op
= O_constant
;
8596 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8597 .dw2_regnum
[flag_code
>> 1];
8600 exp
->X_op
= O_illegal
;
8605 tc_x86_frame_initial_instructions (void)
8607 static unsigned int sp_regno
[2];
8609 if (!sp_regno
[flag_code
>> 1])
8611 char *saved_input
= input_line_pointer
;
8612 char sp
[][4] = {"esp", "rsp"};
8615 input_line_pointer
= sp
[flag_code
>> 1];
8616 tc_x86_parse_to_dw2regnum (&exp
);
8617 gas_assert (exp
.X_op
== O_constant
);
8618 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8619 input_line_pointer
= saved_input
;
8622 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8623 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8627 i386_elf_section_type (const char *str
, size_t len
)
8629 if (flag_code
== CODE_64BIT
8630 && len
== sizeof ("unwind") - 1
8631 && strncmp (str
, "unwind", 6) == 0)
8632 return SHT_X86_64_UNWIND
;
8639 i386_solaris_fix_up_eh_frame (segT sec
)
8641 if (flag_code
== CODE_64BIT
)
8642 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8648 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8652 expr
.X_op
= O_secrel
;
8653 expr
.X_add_symbol
= symbol
;
8654 expr
.X_add_number
= 0;
8655 emit_expr (&expr
, size
);
8659 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8660 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8663 x86_64_section_letter (int letter
, char **ptr_msg
)
8665 if (flag_code
== CODE_64BIT
)
8668 return SHF_X86_64_LARGE
;
8670 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8673 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8678 x86_64_section_word (char *str
, size_t len
)
8680 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8681 return SHF_X86_64_LARGE
;
8687 handle_large_common (int small ATTRIBUTE_UNUSED
)
8689 if (flag_code
!= CODE_64BIT
)
8691 s_comm_internal (0, elf_common_parse
);
8692 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8696 static segT lbss_section
;
8697 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8698 asection
*saved_bss_section
= bss_section
;
8700 if (lbss_section
== NULL
)
8702 flagword applicable
;
8704 subsegT subseg
= now_subseg
;
8706 /* The .lbss section is for local .largecomm symbols. */
8707 lbss_section
= subseg_new (".lbss", 0);
8708 applicable
= bfd_applicable_section_flags (stdoutput
);
8709 bfd_set_section_flags (stdoutput
, lbss_section
,
8710 applicable
& SEC_ALLOC
);
8711 seg_info (lbss_section
)->bss
= 1;
8713 subseg_set (seg
, subseg
);
8716 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8717 bss_section
= lbss_section
;
8719 s_comm_internal (0, elf_common_parse
);
8721 elf_com_section_ptr
= saved_com_section_ptr
;
8722 bss_section
= saved_bss_section
;
8725 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */