1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
135 unsigned int negated
; /* turn off indicated flags. */
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_sse_check (int);
146 static void set_cpu_arch (int);
148 static void pe_directive_secrel (int);
150 static void signed_cons (int);
151 static char *output_invalid (int c
);
152 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
154 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS
*);
159 static int i386_intel_parse_name (const char *, expressionS
*);
160 static const reg_entry
*parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (int, int);
165 static void optimize_imm (void);
166 static void optimize_disp (void);
167 static const insn_template
*match_template (void);
168 static int check_string (void);
169 static int process_suffix (void);
170 static int check_byte_reg (void);
171 static int check_long_reg (void);
172 static int check_qword_reg (void);
173 static int check_word_reg (void);
174 static int finalize_imm (void);
175 static int process_operands (void);
176 static const seg_entry
*build_modrm_byte (void);
177 static void output_insn (void);
178 static void output_imm (fragS
*, offsetT
);
179 static void output_disp (fragS
*, offsetT
);
181 static void s_bss (int);
183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
187 static const char *default_arch
= DEFAULT_ARCH
;
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes
[3];
195 /* Destination or source register specifier. */
196 const reg_entry
*register_specifier
;
199 /* 'md_assemble ()' gathers together information and puts it into a
206 const reg_entry
*regs
;
211 operand_size_mismatch
,
212 operand_type_mismatch
,
213 register_type_mismatch
,
214 number_of_operands_mismatch
,
215 invalid_instruction_suffix
,
218 unsupported_with_intel_mnemonic
,
225 /* TM holds the template for the insn were currently assembling. */
228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
232 /* OPERANDS gives the number of given operands. */
233 unsigned int operands
;
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
238 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
240 /* TYPES [i] is the type (see above #defines) which tells us how to
241 use OP[i] for the corresponding operand. */
242 i386_operand_type types
[MAX_OPERANDS
];
244 /* Displacement expression, immediate expression, or register for each
246 union i386_op op
[MAX_OPERANDS
];
248 /* Flags for operands. */
249 unsigned int flags
[MAX_OPERANDS
];
250 #define Operand_PCrel 1
252 /* Relocation type for operand */
253 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry
*base_reg
;
258 const reg_entry
*index_reg
;
259 unsigned int log2_scale_factor
;
261 /* SEG gives the seg_entries of this insn. They are zero unless
262 explicit segment overrides are given. */
263 const seg_entry
*seg
[2];
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes
;
268 unsigned char prefix
[MAX_PREFIXES
];
270 /* RM and SIB are the modrm byte and the sib byte where the
271 addressing modes of this insn are encoded. */
277 /* Swap operand in encoding. */
278 unsigned int swap_operand
;
280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding
;
284 enum i386_error error
;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_DragonFly) \
307 && !defined (TE_NetBSD)))
308 /* This array holds the chars that always start a comment. If the
309 pre-processor is disabled, these aren't very useful. The option
310 --divide will remove '/' from this list. */
311 const char *i386_comment_chars
= "#/";
312 #define SVR4_COMMENT_CHARS 1
313 #define PREFIX_SEPARATOR '\\'
316 const char *i386_comment_chars
= "#";
317 #define PREFIX_SEPARATOR '/'
320 /* This array holds the chars that only start a comment at the beginning of
321 a line. If the line seems to have the form '# 123 filename'
322 .line and .file directives will appear in the pre-processed output.
323 Note that input_file.c hand checks for '#' at the beginning of the
324 first line of the input file. This is because the compiler outputs
325 #NO_APP at the beginning of its output.
326 Also note that comments started like this one will always work if
327 '/' isn't otherwise defined. */
328 const char line_comment_chars
[] = "#/";
330 const char line_separator_chars
[] = ";";
332 /* Chars that can be used to separate mant from exp in floating point
334 const char EXP_CHARS
[] = "eE";
336 /* Chars that mean this number is a floating point constant
339 const char FLT_CHARS
[] = "fFdDxX";
341 /* Tables for lexical analysis. */
342 static char mnemonic_chars
[256];
343 static char register_chars
[256];
344 static char operand_chars
[256];
345 static char identifier_chars
[256];
346 static char digit_chars
[256];
348 /* Lexical macros. */
349 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
350 #define is_operand_char(x) (operand_chars[(unsigned char) x])
351 #define is_register_char(x) (register_chars[(unsigned char) x])
352 #define is_space_char(x) ((x) == ' ')
353 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
354 #define is_digit_char(x) (digit_chars[(unsigned char) x])
356 /* All non-digit non-letter characters that may occur in an operand. */
357 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
359 /* md_assemble() always leaves the strings it's passed unaltered. To
360 effect this we maintain a stack of saved characters that we've smashed
361 with '\0's (indicating end of strings for various sub-fields of the
362 assembler instruction). */
363 static char save_stack
[32];
364 static char *save_stack_p
;
365 #define END_STRING_AND_SAVE(s) \
366 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
367 #define RESTORE_END_STRING(s) \
368 do { *(s) = *--save_stack_p; } while (0)
370 /* The instruction we're assembling. */
373 /* Possible templates for current insn. */
374 static const templates
*current_templates
;
376 /* Per instruction expressionS buffers: max displacements & immediates. */
377 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
378 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
380 /* Current operand we are working on. */
381 static int this_operand
= -1;
383 /* We support four different modes. FLAG_CODE variable is used to distinguish
391 static enum flag_code flag_code
;
392 static unsigned int object_64bit
;
393 static unsigned int disallow_64bit_reloc
;
394 static int use_rela_relocations
= 0;
396 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
397 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
398 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
400 /* The ELF ABI to use. */
408 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
411 /* The names used to print error messages. */
412 static const char *flag_code_names
[] =
419 /* 1 for intel syntax,
421 static int intel_syntax
= 0;
423 /* 1 for intel mnemonic,
424 0 if att mnemonic. */
425 static int intel_mnemonic
= !SYSV386_COMPAT
;
427 /* 1 if support old (<= 2.8.1) versions of gcc. */
428 static int old_gcc
= OLDGCC_COMPAT
;
430 /* 1 if pseudo registers are permitted. */
431 static int allow_pseudo_reg
= 0;
433 /* 1 if register prefix % not required. */
434 static int allow_naked_reg
= 0;
436 /* 1 if pseudo index register, eiz/riz, is allowed . */
437 static int allow_index_reg
= 0;
447 /* Register prefix used for error message. */
448 static const char *register_prefix
= "%";
450 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
451 leave, push, and pop instructions so that gcc has the same stack
452 frame as in 32 bit mode. */
453 static char stackop_size
= '\0';
455 /* Non-zero to optimize code alignment. */
456 int optimize_align_code
= 1;
458 /* Non-zero to quieten some warnings. */
459 static int quiet_warnings
= 0;
462 static const char *cpu_arch_name
= NULL
;
463 static char *cpu_sub_arch_name
= NULL
;
465 /* CPU feature flags. */
466 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
468 /* If we have selected a cpu we are generating instructions for. */
469 static int cpu_arch_tune_set
= 0;
471 /* Cpu we are generating instructions for. */
472 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
474 /* CPU feature flags of cpu we are generating instructions for. */
475 static i386_cpu_flags cpu_arch_tune_flags
;
477 /* CPU instruction set architecture used. */
478 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
480 /* CPU feature flags of instruction set architecture used. */
481 i386_cpu_flags cpu_arch_isa_flags
;
483 /* If set, conditional jumps are not automatically promoted to handle
484 larger than a byte offset. */
485 static unsigned int no_cond_jump_promotion
= 0;
487 /* Encode SSE instructions with VEX prefix. */
488 static unsigned int sse2avx
;
490 /* Encode scalar AVX instructions with specific vector length. */
497 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
498 static symbolS
*GOT_symbol
;
500 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
501 unsigned int x86_dwarf2_return_column
;
503 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
504 int x86_cie_data_alignment
;
506 /* Interface to relax_segment.
507 There are 3 major relax states for 386 jump insns because the
508 different types of jumps add different sizes to frags when we're
509 figuring out what sort of jump to choose to reach a given label. */
512 #define UNCOND_JUMP 0
514 #define COND_JUMP86 2
519 #define SMALL16 (SMALL | CODE16)
521 #define BIG16 (BIG | CODE16)
525 #define INLINE __inline__
531 #define ENCODE_RELAX_STATE(type, size) \
532 ((relax_substateT) (((type) << 2) | (size)))
533 #define TYPE_FROM_RELAX_STATE(s) \
535 #define DISP_SIZE_FROM_RELAX_STATE(s) \
536 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
538 /* This table is used by relax_frag to promote short jumps to long
539 ones where necessary. SMALL (short) jumps may be promoted to BIG
540 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
541 don't allow a short jump in a 32 bit code segment to be promoted to
542 a 16 bit offset jump because it's slower (requires data size
543 prefix), and doesn't work, unless the destination is in the bottom
544 64k of the code segment (The top 16 bits of eip are zeroed). */
546 const relax_typeS md_relax_table
[] =
549 1) most positive reach of this state,
550 2) most negative reach of this state,
551 3) how many bytes this mode will have in the variable part of the frag
552 4) which index into the table to try if we can't fit into this one. */
554 /* UNCOND_JUMP states. */
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
557 /* dword jmp adds 4 bytes to frag:
558 0 extra opcode bytes, 4 displacement bytes. */
560 /* word jmp adds 2 byte2 to frag:
561 0 extra opcode bytes, 2 displacement bytes. */
564 /* COND_JUMP states. */
565 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
566 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
567 /* dword conditionals adds 5 bytes to frag:
568 1 extra opcode byte, 4 displacement bytes. */
570 /* word conditionals add 3 bytes to frag:
571 1 extra opcode byte, 2 displacement bytes. */
574 /* COND_JUMP86 states. */
575 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
576 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
577 /* dword conditionals adds 5 bytes to frag:
578 1 extra opcode byte, 4 displacement bytes. */
580 /* word conditionals add 4 bytes to frag:
581 1 displacement byte and a 3 byte long branch insn. */
585 static const arch_entry cpu_arch
[] =
587 /* Do not replace the first two entries - i386_target_format()
588 relies on them being there in this order. */
589 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
590 CPU_GENERIC32_FLAGS
, 0, 0 },
591 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
592 CPU_GENERIC64_FLAGS
, 0, 0 },
593 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
594 CPU_NONE_FLAGS
, 0, 0 },
595 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
596 CPU_I186_FLAGS
, 0, 0 },
597 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
598 CPU_I286_FLAGS
, 0, 0 },
599 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
600 CPU_I386_FLAGS
, 0, 0 },
601 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
602 CPU_I486_FLAGS
, 0, 0 },
603 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
604 CPU_I586_FLAGS
, 0, 0 },
605 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
606 CPU_I686_FLAGS
, 0, 0 },
607 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
608 CPU_I586_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
610 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
612 CPU_P2_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
614 CPU_P3_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
616 CPU_P4_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
618 CPU_CORE_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
620 CPU_NOCONA_FLAGS
, 0, 0 },
621 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
622 CPU_CORE_FLAGS
, 1, 0 },
623 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
624 CPU_CORE_FLAGS
, 0, 0 },
625 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
626 CPU_CORE2_FLAGS
, 1, 0 },
627 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
628 CPU_CORE2_FLAGS
, 0, 0 },
629 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
630 CPU_COREI7_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
632 CPU_L1OM_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
634 CPU_K6_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
636 CPU_K6_2_FLAGS
, 0, 0 },
637 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
638 CPU_ATHLON_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
640 CPU_K8_FLAGS
, 1, 0 },
641 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
642 CPU_K8_FLAGS
, 0, 0 },
643 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
644 CPU_K8_FLAGS
, 0, 0 },
645 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
646 CPU_AMDFAM10_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
648 CPU_BDVER1_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
650 CPU_8087_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
652 CPU_287_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
654 CPU_387_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
656 CPU_ANY87_FLAGS
, 0, 1 },
657 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
658 CPU_MMX_FLAGS
, 0, 0 },
659 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
660 CPU_3DNOWA_FLAGS
, 0, 1 },
661 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
662 CPU_SSE_FLAGS
, 0, 0 },
663 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
664 CPU_SSE2_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
666 CPU_SSE3_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
668 CPU_SSSE3_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
670 CPU_SSE4_1_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
672 CPU_SSE4_2_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
674 CPU_SSE4_2_FLAGS
, 0, 0 },
675 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
676 CPU_ANY_SSE_FLAGS
, 0, 1 },
677 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
678 CPU_AVX_FLAGS
, 0, 0 },
679 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
680 CPU_ANY_AVX_FLAGS
, 0, 1 },
681 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
682 CPU_VMX_FLAGS
, 0, 0 },
683 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
684 CPU_SMX_FLAGS
, 0, 0 },
685 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
686 CPU_XSAVE_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
688 CPU_XSAVEOPT_FLAGS
, 0, 0 },
689 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
690 CPU_AES_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
692 CPU_PCLMUL_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
694 CPU_PCLMUL_FLAGS
, 1, 0 },
695 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
696 CPU_FSGSBASE_FLAGS
, 0, 0 },
697 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
698 CPU_RDRND_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
700 CPU_F16C_FLAGS
, 0, 0 },
701 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
702 CPU_FMA_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
704 CPU_FMA4_FLAGS
, 0, 0 },
705 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
706 CPU_XOP_FLAGS
, 0, 0 },
707 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
708 CPU_LWP_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
710 CPU_MOVBE_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
712 CPU_EPT_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
714 CPU_CLFLUSH_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
716 CPU_NOP_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
718 CPU_SYSCALL_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
720 CPU_RDTSCP_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
722 CPU_3DNOW_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
724 CPU_3DNOWA_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
726 CPU_PADLOCK_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
728 CPU_SVME_FLAGS
, 1, 0 },
729 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
730 CPU_SVME_FLAGS
, 0, 0 },
731 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
732 CPU_SSE4A_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
734 CPU_ABM_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
736 CPU_BMI_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
738 CPU_TBM_FLAGS
, 0, 0 },
742 /* Like s_lcomm_internal in gas/read.c but the alignment string
743 is allowed to be optional. */
746 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
753 && *input_line_pointer
== ',')
755 align
= parse_align (needs_align
- 1);
757 if (align
== (addressT
) -1)
772 bss_alloc (symbolP
, size
, align
);
777 pe_lcomm (int needs_align
)
779 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
783 const pseudo_typeS md_pseudo_table
[] =
785 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
786 {"align", s_align_bytes
, 0},
788 {"align", s_align_ptwo
, 0},
790 {"arch", set_cpu_arch
, 0},
794 {"lcomm", pe_lcomm
, 1},
796 {"ffloat", float_cons
, 'f'},
797 {"dfloat", float_cons
, 'd'},
798 {"tfloat", float_cons
, 'x'},
800 {"slong", signed_cons
, 4},
801 {"noopt", s_ignore
, 0},
802 {"optim", s_ignore
, 0},
803 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
804 {"code16", set_code_flag
, CODE_16BIT
},
805 {"code32", set_code_flag
, CODE_32BIT
},
806 {"code64", set_code_flag
, CODE_64BIT
},
807 {"intel_syntax", set_intel_syntax
, 1},
808 {"att_syntax", set_intel_syntax
, 0},
809 {"intel_mnemonic", set_intel_mnemonic
, 1},
810 {"att_mnemonic", set_intel_mnemonic
, 0},
811 {"allow_index_reg", set_allow_index_reg
, 1},
812 {"disallow_index_reg", set_allow_index_reg
, 0},
813 {"sse_check", set_sse_check
, 0},
814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
815 {"largecomm", handle_large_common
, 0},
817 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
818 {"loc", dwarf2_directive_loc
, 0},
819 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
822 {"secrel32", pe_directive_secrel
, 0},
827 /* For interface with expression (). */
828 extern char *input_line_pointer
;
830 /* Hash table for instruction mnemonic lookup. */
831 static struct hash_control
*op_hash
;
833 /* Hash table for register lookup. */
834 static struct hash_control
*reg_hash
;
837 i386_align_code (fragS
*fragP
, int count
)
839 /* Various efficient no-op patterns for aligning code labels.
840 Note: Don't try to assemble the instructions in the comments.
841 0L and 0w are not legal. */
842 static const char f32_1
[] =
844 static const char f32_2
[] =
845 {0x66,0x90}; /* xchg %ax,%ax */
846 static const char f32_3
[] =
847 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
848 static const char f32_4
[] =
849 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
850 static const char f32_5
[] =
852 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
853 static const char f32_6
[] =
854 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
855 static const char f32_7
[] =
856 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
857 static const char f32_8
[] =
859 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
860 static const char f32_9
[] =
861 {0x89,0xf6, /* movl %esi,%esi */
862 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
863 static const char f32_10
[] =
864 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
865 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
866 static const char f32_11
[] =
867 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
868 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
869 static const char f32_12
[] =
870 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
871 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
872 static const char f32_13
[] =
873 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
874 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
875 static const char f32_14
[] =
876 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
877 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
878 static const char f16_3
[] =
879 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
880 static const char f16_4
[] =
881 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
882 static const char f16_5
[] =
884 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
885 static const char f16_6
[] =
886 {0x89,0xf6, /* mov %si,%si */
887 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
888 static const char f16_7
[] =
889 {0x8d,0x74,0x00, /* lea 0(%si),%si */
890 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
891 static const char f16_8
[] =
892 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
893 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
894 static const char jump_31
[] =
895 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
896 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
897 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
898 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
899 static const char *const f32_patt
[] = {
900 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
901 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
903 static const char *const f16_patt
[] = {
904 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
907 static const char alt_3
[] =
909 /* nopl 0(%[re]ax) */
910 static const char alt_4
[] =
911 {0x0f,0x1f,0x40,0x00};
912 /* nopl 0(%[re]ax,%[re]ax,1) */
913 static const char alt_5
[] =
914 {0x0f,0x1f,0x44,0x00,0x00};
915 /* nopw 0(%[re]ax,%[re]ax,1) */
916 static const char alt_6
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopl 0L(%[re]ax) */
919 static const char alt_7
[] =
920 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 /* nopl 0L(%[re]ax,%[re]ax,1) */
922 static const char alt_8
[] =
923 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
924 /* nopw 0L(%[re]ax,%[re]ax,1) */
925 static const char alt_9
[] =
926 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
928 static const char alt_10
[] =
929 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_long_11
[] =
934 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
937 nopw %cs:0L(%[re]ax,%[re]ax,1) */
938 static const char alt_long_12
[] =
941 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
945 nopw %cs:0L(%[re]ax,%[re]ax,1) */
946 static const char alt_long_13
[] =
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
955 nopw %cs:0L(%[re]ax,%[re]ax,1) */
956 static const char alt_long_14
[] =
961 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
967 nopw %cs:0L(%[re]ax,%[re]ax,1) */
968 static const char alt_long_15
[] =
974 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
975 /* nopl 0(%[re]ax,%[re]ax,1)
976 nopw 0(%[re]ax,%[re]ax,1) */
977 static const char alt_short_11
[] =
978 {0x0f,0x1f,0x44,0x00,0x00,
979 0x66,0x0f,0x1f,0x44,0x00,0x00};
980 /* nopw 0(%[re]ax,%[re]ax,1)
981 nopw 0(%[re]ax,%[re]ax,1) */
982 static const char alt_short_12
[] =
983 {0x66,0x0f,0x1f,0x44,0x00,0x00,
984 0x66,0x0f,0x1f,0x44,0x00,0x00};
985 /* nopw 0(%[re]ax,%[re]ax,1)
987 static const char alt_short_13
[] =
988 {0x66,0x0f,0x1f,0x44,0x00,0x00,
989 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
992 static const char alt_short_14
[] =
993 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
994 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
996 nopl 0L(%[re]ax,%[re]ax,1) */
997 static const char alt_short_15
[] =
998 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
999 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1000 static const char *const alt_short_patt
[] = {
1001 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1002 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1003 alt_short_14
, alt_short_15
1005 static const char *const alt_long_patt
[] = {
1006 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1007 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1008 alt_long_14
, alt_long_15
1011 /* Only align for at least a positive non-zero boundary. */
1012 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1015 /* We need to decide which NOP sequence to use for 32bit and
1016 64bit. When -mtune= is used:
1018 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1019 PROCESSOR_GENERIC32, f32_patt will be used.
1020 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1021 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1022 PROCESSOR_GENERIC64, alt_long_patt will be used.
1023 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1024 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
1027 When -mtune= isn't used, alt_long_patt will be used if
1028 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1031 When -march= or .arch is used, we can't use anything beyond
1032 cpu_arch_isa_flags. */
1034 if (flag_code
== CODE_16BIT
)
1038 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1040 /* Adjust jump offset. */
1041 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1044 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1045 f16_patt
[count
- 1], count
);
1049 const char *const *patt
= NULL
;
1051 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1053 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1054 switch (cpu_arch_tune
)
1056 case PROCESSOR_UNKNOWN
:
1057 /* We use cpu_arch_isa_flags to check if we SHOULD
1058 optimize with nops. */
1059 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1060 patt
= alt_long_patt
;
1064 case PROCESSOR_PENTIUM4
:
1065 case PROCESSOR_NOCONA
:
1066 case PROCESSOR_CORE
:
1067 case PROCESSOR_CORE2
:
1068 case PROCESSOR_COREI7
:
1069 case PROCESSOR_L1OM
:
1070 case PROCESSOR_GENERIC64
:
1071 patt
= alt_long_patt
;
1074 case PROCESSOR_ATHLON
:
1076 case PROCESSOR_AMDFAM10
:
1077 case PROCESSOR_BDVER1
:
1078 patt
= alt_short_patt
;
1080 case PROCESSOR_I386
:
1081 case PROCESSOR_I486
:
1082 case PROCESSOR_PENTIUM
:
1083 case PROCESSOR_PENTIUMPRO
:
1084 case PROCESSOR_GENERIC32
:
1091 switch (fragP
->tc_frag_data
.tune
)
1093 case PROCESSOR_UNKNOWN
:
1094 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1095 PROCESSOR_UNKNOWN. */
1099 case PROCESSOR_I386
:
1100 case PROCESSOR_I486
:
1101 case PROCESSOR_PENTIUM
:
1103 case PROCESSOR_ATHLON
:
1105 case PROCESSOR_AMDFAM10
:
1106 case PROCESSOR_BDVER1
:
1107 case PROCESSOR_GENERIC32
:
1108 /* We use cpu_arch_isa_flags to check if we CAN optimize
1110 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1111 patt
= alt_short_patt
;
1115 case PROCESSOR_PENTIUMPRO
:
1116 case PROCESSOR_PENTIUM4
:
1117 case PROCESSOR_NOCONA
:
1118 case PROCESSOR_CORE
:
1119 case PROCESSOR_CORE2
:
1120 case PROCESSOR_COREI7
:
1121 case PROCESSOR_L1OM
:
1122 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1123 patt
= alt_long_patt
;
1127 case PROCESSOR_GENERIC64
:
1128 patt
= alt_long_patt
;
1133 if (patt
== f32_patt
)
1135 /* If the padding is less than 15 bytes, we use the normal
1136 ones. Otherwise, we use a jump instruction and adjust
1140 /* For 64bit, the limit is 3 bytes. */
1141 if (flag_code
== CODE_64BIT
1142 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1147 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1148 patt
[count
- 1], count
);
1151 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1153 /* Adjust jump offset. */
1154 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1159 /* Maximum length of an instruction is 15 byte. If the
1160 padding is greater than 15 bytes and we don't use jump,
1161 we have to break it into smaller pieces. */
1162 int padding
= count
;
1163 while (padding
> 15)
1166 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1171 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1172 patt
[padding
- 1], padding
);
1175 fragP
->fr_var
= count
;
1179 operand_type_all_zero (const union i386_operand_type
*x
)
1181 switch (ARRAY_SIZE(x
->array
))
1190 return !x
->array
[0];
1197 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1199 switch (ARRAY_SIZE(x
->array
))
1214 operand_type_equal (const union i386_operand_type
*x
,
1215 const union i386_operand_type
*y
)
1217 switch (ARRAY_SIZE(x
->array
))
1220 if (x
->array
[2] != y
->array
[2])
1223 if (x
->array
[1] != y
->array
[1])
1226 return x
->array
[0] == y
->array
[0];
1234 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1236 switch (ARRAY_SIZE(x
->array
))
1245 return !x
->array
[0];
1252 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1254 switch (ARRAY_SIZE(x
->array
))
1269 cpu_flags_equal (const union i386_cpu_flags
*x
,
1270 const union i386_cpu_flags
*y
)
1272 switch (ARRAY_SIZE(x
->array
))
1275 if (x
->array
[2] != y
->array
[2])
1278 if (x
->array
[1] != y
->array
[1])
1281 return x
->array
[0] == y
->array
[0];
1289 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1291 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1292 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1295 static INLINE i386_cpu_flags
1296 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1298 switch (ARRAY_SIZE (x
.array
))
1301 x
.array
[2] &= y
.array
[2];
1303 x
.array
[1] &= y
.array
[1];
1305 x
.array
[0] &= y
.array
[0];
1313 static INLINE i386_cpu_flags
1314 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1316 switch (ARRAY_SIZE (x
.array
))
1319 x
.array
[2] |= y
.array
[2];
1321 x
.array
[1] |= y
.array
[1];
1323 x
.array
[0] |= y
.array
[0];
1331 static INLINE i386_cpu_flags
1332 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1334 switch (ARRAY_SIZE (x
.array
))
1337 x
.array
[2] &= ~y
.array
[2];
1339 x
.array
[1] &= ~y
.array
[1];
1341 x
.array
[0] &= ~y
.array
[0];
1349 #define CPU_FLAGS_ARCH_MATCH 0x1
1350 #define CPU_FLAGS_64BIT_MATCH 0x2
1351 #define CPU_FLAGS_AES_MATCH 0x4
1352 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1353 #define CPU_FLAGS_AVX_MATCH 0x10
1355 #define CPU_FLAGS_32BIT_MATCH \
1356 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1357 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1358 #define CPU_FLAGS_PERFECT_MATCH \
1359 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1361 /* Return CPU flags match bits. */
1364 cpu_flags_match (const insn_template
*t
)
1366 i386_cpu_flags x
= t
->cpu_flags
;
1367 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1369 x
.bitfield
.cpu64
= 0;
1370 x
.bitfield
.cpuno64
= 0;
1372 if (cpu_flags_all_zero (&x
))
1374 /* This instruction is available on all archs. */
1375 match
|= CPU_FLAGS_32BIT_MATCH
;
1379 /* This instruction is available only on some archs. */
1380 i386_cpu_flags cpu
= cpu_arch_flags
;
1382 cpu
.bitfield
.cpu64
= 0;
1383 cpu
.bitfield
.cpuno64
= 0;
1384 cpu
= cpu_flags_and (x
, cpu
);
1385 if (!cpu_flags_all_zero (&cpu
))
1387 if (x
.bitfield
.cpuavx
)
1389 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1390 if (cpu
.bitfield
.cpuavx
)
1392 /* Check SSE2AVX. */
1393 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1395 match
|= (CPU_FLAGS_ARCH_MATCH
1396 | CPU_FLAGS_AVX_MATCH
);
1398 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1399 match
|= CPU_FLAGS_AES_MATCH
;
1401 if (!x
.bitfield
.cpupclmul
1402 || cpu
.bitfield
.cpupclmul
)
1403 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1407 match
|= CPU_FLAGS_ARCH_MATCH
;
1410 match
|= CPU_FLAGS_32BIT_MATCH
;
1416 static INLINE i386_operand_type
1417 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1419 switch (ARRAY_SIZE (x
.array
))
1422 x
.array
[2] &= y
.array
[2];
1424 x
.array
[1] &= y
.array
[1];
1426 x
.array
[0] &= y
.array
[0];
1434 static INLINE i386_operand_type
1435 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1437 switch (ARRAY_SIZE (x
.array
))
1440 x
.array
[2] |= y
.array
[2];
1442 x
.array
[1] |= y
.array
[1];
1444 x
.array
[0] |= y
.array
[0];
1452 static INLINE i386_operand_type
1453 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1455 switch (ARRAY_SIZE (x
.array
))
1458 x
.array
[2] ^= y
.array
[2];
1460 x
.array
[1] ^= y
.array
[1];
1462 x
.array
[0] ^= y
.array
[0];
1470 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1471 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1472 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1473 static const i386_operand_type inoutportreg
1474 = OPERAND_TYPE_INOUTPORTREG
;
1475 static const i386_operand_type reg16_inoutportreg
1476 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1477 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1478 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1479 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1480 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1481 static const i386_operand_type anydisp
1482 = OPERAND_TYPE_ANYDISP
;
1483 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1484 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1485 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1486 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1487 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1488 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1489 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1490 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1491 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1492 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1493 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1494 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1505 operand_type_check (i386_operand_type t
, enum operand_type c
)
1510 return (t
.bitfield
.reg8
1513 || t
.bitfield
.reg64
);
1516 return (t
.bitfield
.imm8
1520 || t
.bitfield
.imm32s
1521 || t
.bitfield
.imm64
);
1524 return (t
.bitfield
.disp8
1525 || t
.bitfield
.disp16
1526 || t
.bitfield
.disp32
1527 || t
.bitfield
.disp32s
1528 || t
.bitfield
.disp64
);
1531 return (t
.bitfield
.disp8
1532 || t
.bitfield
.disp16
1533 || t
.bitfield
.disp32
1534 || t
.bitfield
.disp32s
1535 || t
.bitfield
.disp64
1536 || t
.bitfield
.baseindex
);
1545 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1546 operand J for instruction template T. */
1549 match_reg_size (const insn_template
*t
, unsigned int j
)
1551 return !((i
.types
[j
].bitfield
.byte
1552 && !t
->operand_types
[j
].bitfield
.byte
)
1553 || (i
.types
[j
].bitfield
.word
1554 && !t
->operand_types
[j
].bitfield
.word
)
1555 || (i
.types
[j
].bitfield
.dword
1556 && !t
->operand_types
[j
].bitfield
.dword
)
1557 || (i
.types
[j
].bitfield
.qword
1558 && !t
->operand_types
[j
].bitfield
.qword
));
1561 /* Return 1 if there is no conflict in any size on operand J for
1562 instruction template T. */
1565 match_mem_size (const insn_template
*t
, unsigned int j
)
1567 return (match_reg_size (t
, j
)
1568 && !((i
.types
[j
].bitfield
.unspecified
1569 && !t
->operand_types
[j
].bitfield
.unspecified
)
1570 || (i
.types
[j
].bitfield
.fword
1571 && !t
->operand_types
[j
].bitfield
.fword
)
1572 || (i
.types
[j
].bitfield
.tbyte
1573 && !t
->operand_types
[j
].bitfield
.tbyte
)
1574 || (i
.types
[j
].bitfield
.xmmword
1575 && !t
->operand_types
[j
].bitfield
.xmmword
)
1576 || (i
.types
[j
].bitfield
.ymmword
1577 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1580 /* Return 1 if there is no size conflict on any operands for
1581 instruction template T. */
1584 operand_size_match (const insn_template
*t
)
1589 /* Don't check jump instructions. */
1590 if (t
->opcode_modifier
.jump
1591 || t
->opcode_modifier
.jumpbyte
1592 || t
->opcode_modifier
.jumpdword
1593 || t
->opcode_modifier
.jumpintersegment
)
1596 /* Check memory and accumulator operand size. */
1597 for (j
= 0; j
< i
.operands
; j
++)
1599 if (t
->operand_types
[j
].bitfield
.anysize
)
1602 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1608 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1617 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1620 i
.error
= operand_size_mismatch
;
1624 /* Check reverse. */
1625 gas_assert (i
.operands
== 2);
1628 for (j
= 0; j
< 2; j
++)
1630 if (t
->operand_types
[j
].bitfield
.acc
1631 && !match_reg_size (t
, j
? 0 : 1))
1634 if (i
.types
[j
].bitfield
.mem
1635 && !match_mem_size (t
, j
? 0 : 1))
1643 operand_type_match (i386_operand_type overlap
,
1644 i386_operand_type given
)
1646 i386_operand_type temp
= overlap
;
1648 temp
.bitfield
.jumpabsolute
= 0;
1649 temp
.bitfield
.unspecified
= 0;
1650 temp
.bitfield
.byte
= 0;
1651 temp
.bitfield
.word
= 0;
1652 temp
.bitfield
.dword
= 0;
1653 temp
.bitfield
.fword
= 0;
1654 temp
.bitfield
.qword
= 0;
1655 temp
.bitfield
.tbyte
= 0;
1656 temp
.bitfield
.xmmword
= 0;
1657 temp
.bitfield
.ymmword
= 0;
1658 if (operand_type_all_zero (&temp
))
1661 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1662 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1666 i
.error
= operand_type_mismatch
;
1670 /* If given types g0 and g1 are registers they must be of the same type
1671 unless the expected operand type register overlap is null.
1672 Note that Acc in a template matches every size of reg. */
1675 operand_type_register_match (i386_operand_type m0
,
1676 i386_operand_type g0
,
1677 i386_operand_type t0
,
1678 i386_operand_type m1
,
1679 i386_operand_type g1
,
1680 i386_operand_type t1
)
1682 if (!operand_type_check (g0
, reg
))
1685 if (!operand_type_check (g1
, reg
))
1688 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1689 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1690 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1691 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1694 if (m0
.bitfield
.acc
)
1696 t0
.bitfield
.reg8
= 1;
1697 t0
.bitfield
.reg16
= 1;
1698 t0
.bitfield
.reg32
= 1;
1699 t0
.bitfield
.reg64
= 1;
1702 if (m1
.bitfield
.acc
)
1704 t1
.bitfield
.reg8
= 1;
1705 t1
.bitfield
.reg16
= 1;
1706 t1
.bitfield
.reg32
= 1;
1707 t1
.bitfield
.reg64
= 1;
1710 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1711 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1712 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1713 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1716 i
.error
= register_type_mismatch
;
1721 static INLINE
unsigned int
1722 mode_from_disp_size (i386_operand_type t
)
1724 if (t
.bitfield
.disp8
)
1726 else if (t
.bitfield
.disp16
1727 || t
.bitfield
.disp32
1728 || t
.bitfield
.disp32s
)
1735 fits_in_signed_byte (offsetT num
)
1737 return (num
>= -128) && (num
<= 127);
1741 fits_in_unsigned_byte (offsetT num
)
1743 return (num
& 0xff) == num
;
1747 fits_in_unsigned_word (offsetT num
)
1749 return (num
& 0xffff) == num
;
1753 fits_in_signed_word (offsetT num
)
1755 return (-32768 <= num
) && (num
<= 32767);
1759 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1764 return (!(((offsetT
) -1 << 31) & num
)
1765 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1767 } /* fits_in_signed_long() */
1770 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1775 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1777 } /* fits_in_unsigned_long() */
1780 fits_in_imm4 (offsetT num
)
1782 return (num
& 0xf) == num
;
1785 static i386_operand_type
1786 smallest_imm_type (offsetT num
)
1788 i386_operand_type t
;
1790 operand_type_set (&t
, 0);
1791 t
.bitfield
.imm64
= 1;
1793 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1795 /* This code is disabled on the 486 because all the Imm1 forms
1796 in the opcode table are slower on the i486. They're the
1797 versions with the implicitly specified single-position
1798 displacement, which has another syntax if you really want to
1800 t
.bitfield
.imm1
= 1;
1801 t
.bitfield
.imm8
= 1;
1802 t
.bitfield
.imm8s
= 1;
1803 t
.bitfield
.imm16
= 1;
1804 t
.bitfield
.imm32
= 1;
1805 t
.bitfield
.imm32s
= 1;
1807 else if (fits_in_signed_byte (num
))
1809 t
.bitfield
.imm8
= 1;
1810 t
.bitfield
.imm8s
= 1;
1811 t
.bitfield
.imm16
= 1;
1812 t
.bitfield
.imm32
= 1;
1813 t
.bitfield
.imm32s
= 1;
1815 else if (fits_in_unsigned_byte (num
))
1817 t
.bitfield
.imm8
= 1;
1818 t
.bitfield
.imm16
= 1;
1819 t
.bitfield
.imm32
= 1;
1820 t
.bitfield
.imm32s
= 1;
1822 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1824 t
.bitfield
.imm16
= 1;
1825 t
.bitfield
.imm32
= 1;
1826 t
.bitfield
.imm32s
= 1;
1828 else if (fits_in_signed_long (num
))
1830 t
.bitfield
.imm32
= 1;
1831 t
.bitfield
.imm32s
= 1;
1833 else if (fits_in_unsigned_long (num
))
1834 t
.bitfield
.imm32
= 1;
1840 offset_in_range (offsetT val
, int size
)
1846 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1847 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1848 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1850 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1856 /* If BFD64, sign extend val for 32bit address mode. */
1857 if (flag_code
!= CODE_64BIT
1858 || i
.prefix
[ADDR_PREFIX
])
1859 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1860 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1863 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1865 char buf1
[40], buf2
[40];
1867 sprint_value (buf1
, val
);
1868 sprint_value (buf2
, val
& mask
);
1869 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1883 a. PREFIX_EXIST if attempting to add a prefix where one from the
1884 same class already exists.
1885 b. PREFIX_LOCK if lock prefix is added.
1886 c. PREFIX_REP if rep/repne prefix is added.
1887 d. PREFIX_OTHER if other prefix is added.
1890 static enum PREFIX_GROUP
1891 add_prefix (unsigned int prefix
)
1893 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1896 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1897 && flag_code
== CODE_64BIT
)
1899 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1900 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1901 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1912 case CS_PREFIX_OPCODE
:
1913 case DS_PREFIX_OPCODE
:
1914 case ES_PREFIX_OPCODE
:
1915 case FS_PREFIX_OPCODE
:
1916 case GS_PREFIX_OPCODE
:
1917 case SS_PREFIX_OPCODE
:
1921 case REPNE_PREFIX_OPCODE
:
1922 case REPE_PREFIX_OPCODE
:
1927 case LOCK_PREFIX_OPCODE
:
1936 case ADDR_PREFIX_OPCODE
:
1940 case DATA_PREFIX_OPCODE
:
1944 if (i
.prefix
[q
] != 0)
1952 i
.prefix
[q
] |= prefix
;
1955 as_bad (_("same type of prefix used twice"));
1961 update_code_flag (int value
, int check
)
1963 PRINTF_LIKE ((*as_error
));
1965 flag_code
= (enum flag_code
) value
;
1966 if (flag_code
== CODE_64BIT
)
1968 cpu_arch_flags
.bitfield
.cpu64
= 1;
1969 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1973 cpu_arch_flags
.bitfield
.cpu64
= 0;
1974 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1976 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1979 as_error
= as_fatal
;
1982 (*as_error
) (_("64bit mode not supported on `%s'."),
1983 cpu_arch_name
? cpu_arch_name
: default_arch
);
1985 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1988 as_error
= as_fatal
;
1991 (*as_error
) (_("32bit mode not supported on `%s'."),
1992 cpu_arch_name
? cpu_arch_name
: default_arch
);
1994 stackop_size
= '\0';
1998 set_code_flag (int value
)
2000 update_code_flag (value
, 0);
2004 set_16bit_gcc_code_flag (int new_code_flag
)
2006 flag_code
= (enum flag_code
) new_code_flag
;
2007 if (flag_code
!= CODE_16BIT
)
2009 cpu_arch_flags
.bitfield
.cpu64
= 0;
2010 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2011 stackop_size
= LONG_MNEM_SUFFIX
;
2015 set_intel_syntax (int syntax_flag
)
2017 /* Find out if register prefixing is specified. */
2018 int ask_naked_reg
= 0;
2021 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2023 char *string
= input_line_pointer
;
2024 int e
= get_symbol_end ();
2026 if (strcmp (string
, "prefix") == 0)
2028 else if (strcmp (string
, "noprefix") == 0)
2031 as_bad (_("bad argument to syntax directive."));
2032 *input_line_pointer
= e
;
2034 demand_empty_rest_of_line ();
2036 intel_syntax
= syntax_flag
;
2038 if (ask_naked_reg
== 0)
2039 allow_naked_reg
= (intel_syntax
2040 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2042 allow_naked_reg
= (ask_naked_reg
< 0);
2044 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2046 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2047 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2048 register_prefix
= allow_naked_reg
? "" : "%";
2052 set_intel_mnemonic (int mnemonic_flag
)
2054 intel_mnemonic
= mnemonic_flag
;
2058 set_allow_index_reg (int flag
)
2060 allow_index_reg
= flag
;
2064 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2068 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2070 char *string
= input_line_pointer
;
2071 int e
= get_symbol_end ();
2073 if (strcmp (string
, "none") == 0)
2074 sse_check
= sse_check_none
;
2075 else if (strcmp (string
, "warning") == 0)
2076 sse_check
= sse_check_warning
;
2077 else if (strcmp (string
, "error") == 0)
2078 sse_check
= sse_check_error
;
2080 as_bad (_("bad argument to sse_check directive."));
2081 *input_line_pointer
= e
;
2084 as_bad (_("missing argument for sse_check directive"));
2086 demand_empty_rest_of_line ();
2090 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2091 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2093 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2094 static const char *arch
;
2096 /* Intel LIOM is only supported on ELF. */
2102 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2103 use default_arch. */
2104 arch
= cpu_arch_name
;
2106 arch
= default_arch
;
2109 /* If we are targeting Intel L1OM, we must enable it. */
2110 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2111 || new_flag
.bitfield
.cpul1om
)
2114 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2119 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2123 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2125 char *string
= input_line_pointer
;
2126 int e
= get_symbol_end ();
2128 i386_cpu_flags flags
;
2130 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2132 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2134 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2138 cpu_arch_name
= cpu_arch
[j
].name
;
2139 cpu_sub_arch_name
= NULL
;
2140 cpu_arch_flags
= cpu_arch
[j
].flags
;
2141 if (flag_code
== CODE_64BIT
)
2143 cpu_arch_flags
.bitfield
.cpu64
= 1;
2144 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2148 cpu_arch_flags
.bitfield
.cpu64
= 0;
2149 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2151 cpu_arch_isa
= cpu_arch
[j
].type
;
2152 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2153 if (!cpu_arch_tune_set
)
2155 cpu_arch_tune
= cpu_arch_isa
;
2156 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2161 if (!cpu_arch
[j
].negated
)
2162 flags
= cpu_flags_or (cpu_arch_flags
,
2165 flags
= cpu_flags_and_not (cpu_arch_flags
,
2167 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2169 if (cpu_sub_arch_name
)
2171 char *name
= cpu_sub_arch_name
;
2172 cpu_sub_arch_name
= concat (name
,
2174 (const char *) NULL
);
2178 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2179 cpu_arch_flags
= flags
;
2180 cpu_arch_isa_flags
= flags
;
2182 *input_line_pointer
= e
;
2183 demand_empty_rest_of_line ();
2187 if (j
>= ARRAY_SIZE (cpu_arch
))
2188 as_bad (_("no such architecture: `%s'"), string
);
2190 *input_line_pointer
= e
;
2193 as_bad (_("missing cpu architecture"));
2195 no_cond_jump_promotion
= 0;
2196 if (*input_line_pointer
== ','
2197 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2199 char *string
= ++input_line_pointer
;
2200 int e
= get_symbol_end ();
2202 if (strcmp (string
, "nojumps") == 0)
2203 no_cond_jump_promotion
= 1;
2204 else if (strcmp (string
, "jumps") == 0)
2207 as_bad (_("no such architecture modifier: `%s'"), string
);
2209 *input_line_pointer
= e
;
2212 demand_empty_rest_of_line ();
2215 enum bfd_architecture
2218 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2220 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2221 || flag_code
!= CODE_64BIT
)
2222 as_fatal (_("Intel L1OM is 64bit ELF only"));
2223 return bfd_arch_l1om
;
2226 return bfd_arch_i386
;
2232 if (!strncmp (default_arch
, "x86_64", 6))
2234 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2236 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2237 || default_arch
[6] != '\0')
2238 as_fatal (_("Intel L1OM is 64bit ELF only"));
2239 return bfd_mach_l1om
;
2241 else if (default_arch
[6] == '\0')
2242 return bfd_mach_x86_64
;
2244 return bfd_mach_x64_32
;
2246 else if (!strcmp (default_arch
, "i386"))
2247 return bfd_mach_i386_i386
;
2249 as_fatal (_("Unknown architecture"));
2255 const char *hash_err
;
2257 /* Initialize op_hash hash table. */
2258 op_hash
= hash_new ();
2261 const insn_template
*optab
;
2262 templates
*core_optab
;
2264 /* Setup for loop. */
2266 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2267 core_optab
->start
= optab
;
2272 if (optab
->name
== NULL
2273 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2275 /* different name --> ship out current template list;
2276 add to hash table; & begin anew. */
2277 core_optab
->end
= optab
;
2278 hash_err
= hash_insert (op_hash
,
2280 (void *) core_optab
);
2283 as_fatal (_("Internal Error: Can't hash %s: %s"),
2287 if (optab
->name
== NULL
)
2289 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2290 core_optab
->start
= optab
;
2295 /* Initialize reg_hash hash table. */
2296 reg_hash
= hash_new ();
2298 const reg_entry
*regtab
;
2299 unsigned int regtab_size
= i386_regtab_size
;
2301 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2303 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2305 as_fatal (_("Internal Error: Can't hash %s: %s"),
2311 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2316 for (c
= 0; c
< 256; c
++)
2321 mnemonic_chars
[c
] = c
;
2322 register_chars
[c
] = c
;
2323 operand_chars
[c
] = c
;
2325 else if (ISLOWER (c
))
2327 mnemonic_chars
[c
] = c
;
2328 register_chars
[c
] = c
;
2329 operand_chars
[c
] = c
;
2331 else if (ISUPPER (c
))
2333 mnemonic_chars
[c
] = TOLOWER (c
);
2334 register_chars
[c
] = mnemonic_chars
[c
];
2335 operand_chars
[c
] = c
;
2338 if (ISALPHA (c
) || ISDIGIT (c
))
2339 identifier_chars
[c
] = c
;
2342 identifier_chars
[c
] = c
;
2343 operand_chars
[c
] = c
;
2348 identifier_chars
['@'] = '@';
2351 identifier_chars
['?'] = '?';
2352 operand_chars
['?'] = '?';
2354 digit_chars
['-'] = '-';
2355 mnemonic_chars
['_'] = '_';
2356 mnemonic_chars
['-'] = '-';
2357 mnemonic_chars
['.'] = '.';
2358 identifier_chars
['_'] = '_';
2359 identifier_chars
['.'] = '.';
2361 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2362 operand_chars
[(unsigned char) *p
] = *p
;
2365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2368 record_alignment (text_section
, 2);
2369 record_alignment (data_section
, 2);
2370 record_alignment (bss_section
, 2);
2374 if (flag_code
== CODE_64BIT
)
2376 #if defined (OBJ_COFF) && defined (TE_PE)
2377 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2380 x86_dwarf2_return_column
= 16;
2382 x86_cie_data_alignment
= -8;
2386 x86_dwarf2_return_column
= 8;
2387 x86_cie_data_alignment
= -4;
2392 i386_print_statistics (FILE *file
)
2394 hash_print_statistics (file
, "i386 opcode", op_hash
);
2395 hash_print_statistics (file
, "i386 register", reg_hash
);
2400 /* Debugging routines for md_assemble. */
2401 static void pte (insn_template
*);
2402 static void pt (i386_operand_type
);
2403 static void pe (expressionS
*);
2404 static void ps (symbolS
*);
2407 pi (char *line
, i386_insn
*x
)
2411 fprintf (stdout
, "%s: template ", line
);
2413 fprintf (stdout
, " address: base %s index %s scale %x\n",
2414 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2415 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2416 x
->log2_scale_factor
);
2417 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2418 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2419 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2420 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2421 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2422 (x
->rex
& REX_W
) != 0,
2423 (x
->rex
& REX_R
) != 0,
2424 (x
->rex
& REX_X
) != 0,
2425 (x
->rex
& REX_B
) != 0);
2426 for (j
= 0; j
< x
->operands
; j
++)
2428 fprintf (stdout
, " #%d: ", j
+ 1);
2430 fprintf (stdout
, "\n");
2431 if (x
->types
[j
].bitfield
.reg8
2432 || x
->types
[j
].bitfield
.reg16
2433 || x
->types
[j
].bitfield
.reg32
2434 || x
->types
[j
].bitfield
.reg64
2435 || x
->types
[j
].bitfield
.regmmx
2436 || x
->types
[j
].bitfield
.regxmm
2437 || x
->types
[j
].bitfield
.regymm
2438 || x
->types
[j
].bitfield
.sreg2
2439 || x
->types
[j
].bitfield
.sreg3
2440 || x
->types
[j
].bitfield
.control
2441 || x
->types
[j
].bitfield
.debug
2442 || x
->types
[j
].bitfield
.test
)
2443 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2444 if (operand_type_check (x
->types
[j
], imm
))
2446 if (operand_type_check (x
->types
[j
], disp
))
2447 pe (x
->op
[j
].disps
);
2452 pte (insn_template
*t
)
2455 fprintf (stdout
, " %d operands ", t
->operands
);
2456 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2457 if (t
->extension_opcode
!= None
)
2458 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2459 if (t
->opcode_modifier
.d
)
2460 fprintf (stdout
, "D");
2461 if (t
->opcode_modifier
.w
)
2462 fprintf (stdout
, "W");
2463 fprintf (stdout
, "\n");
2464 for (j
= 0; j
< t
->operands
; j
++)
2466 fprintf (stdout
, " #%d type ", j
+ 1);
2467 pt (t
->operand_types
[j
]);
2468 fprintf (stdout
, "\n");
2475 fprintf (stdout
, " operation %d\n", e
->X_op
);
2476 fprintf (stdout
, " add_number %ld (%lx)\n",
2477 (long) e
->X_add_number
, (long) e
->X_add_number
);
2478 if (e
->X_add_symbol
)
2480 fprintf (stdout
, " add_symbol ");
2481 ps (e
->X_add_symbol
);
2482 fprintf (stdout
, "\n");
2486 fprintf (stdout
, " op_symbol ");
2487 ps (e
->X_op_symbol
);
2488 fprintf (stdout
, "\n");
2495 fprintf (stdout
, "%s type %s%s",
2497 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2498 segment_name (S_GET_SEGMENT (s
)));
2501 static struct type_name
2503 i386_operand_type mask
;
2506 const type_names
[] =
2508 { OPERAND_TYPE_REG8
, "r8" },
2509 { OPERAND_TYPE_REG16
, "r16" },
2510 { OPERAND_TYPE_REG32
, "r32" },
2511 { OPERAND_TYPE_REG64
, "r64" },
2512 { OPERAND_TYPE_IMM8
, "i8" },
2513 { OPERAND_TYPE_IMM8
, "i8s" },
2514 { OPERAND_TYPE_IMM16
, "i16" },
2515 { OPERAND_TYPE_IMM32
, "i32" },
2516 { OPERAND_TYPE_IMM32S
, "i32s" },
2517 { OPERAND_TYPE_IMM64
, "i64" },
2518 { OPERAND_TYPE_IMM1
, "i1" },
2519 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2520 { OPERAND_TYPE_DISP8
, "d8" },
2521 { OPERAND_TYPE_DISP16
, "d16" },
2522 { OPERAND_TYPE_DISP32
, "d32" },
2523 { OPERAND_TYPE_DISP32S
, "d32s" },
2524 { OPERAND_TYPE_DISP64
, "d64" },
2525 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2526 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2527 { OPERAND_TYPE_CONTROL
, "control reg" },
2528 { OPERAND_TYPE_TEST
, "test reg" },
2529 { OPERAND_TYPE_DEBUG
, "debug reg" },
2530 { OPERAND_TYPE_FLOATREG
, "FReg" },
2531 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2532 { OPERAND_TYPE_SREG2
, "SReg2" },
2533 { OPERAND_TYPE_SREG3
, "SReg3" },
2534 { OPERAND_TYPE_ACC
, "Acc" },
2535 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2536 { OPERAND_TYPE_REGMMX
, "rMMX" },
2537 { OPERAND_TYPE_REGXMM
, "rXMM" },
2538 { OPERAND_TYPE_REGYMM
, "rYMM" },
2539 { OPERAND_TYPE_ESSEG
, "es" },
2543 pt (i386_operand_type t
)
2546 i386_operand_type a
;
2548 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2550 a
= operand_type_and (t
, type_names
[j
].mask
);
2551 if (!operand_type_all_zero (&a
))
2552 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2557 #endif /* DEBUG386 */
2559 static bfd_reloc_code_real_type
2560 reloc (unsigned int size
,
2563 bfd_reloc_code_real_type other
)
2565 if (other
!= NO_RELOC
)
2567 reloc_howto_type
*rel
;
2572 case BFD_RELOC_X86_64_GOT32
:
2573 return BFD_RELOC_X86_64_GOT64
;
2575 case BFD_RELOC_X86_64_PLTOFF64
:
2576 return BFD_RELOC_X86_64_PLTOFF64
;
2578 case BFD_RELOC_X86_64_GOTPC32
:
2579 other
= BFD_RELOC_X86_64_GOTPC64
;
2581 case BFD_RELOC_X86_64_GOTPCREL
:
2582 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2584 case BFD_RELOC_X86_64_TPOFF32
:
2585 other
= BFD_RELOC_X86_64_TPOFF64
;
2587 case BFD_RELOC_X86_64_DTPOFF32
:
2588 other
= BFD_RELOC_X86_64_DTPOFF64
;
2594 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2595 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2598 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2600 as_bad (_("unknown relocation (%u)"), other
);
2601 else if (size
!= bfd_get_reloc_size (rel
))
2602 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2603 bfd_get_reloc_size (rel
),
2605 else if (pcrel
&& !rel
->pc_relative
)
2606 as_bad (_("non-pc-relative relocation for pc-relative field"));
2607 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2609 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2611 as_bad (_("relocated field and relocation type differ in signedness"));
2620 as_bad (_("there are no unsigned pc-relative relocations"));
2623 case 1: return BFD_RELOC_8_PCREL
;
2624 case 2: return BFD_RELOC_16_PCREL
;
2625 case 4: return BFD_RELOC_32_PCREL
;
2626 case 8: return BFD_RELOC_64_PCREL
;
2628 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2635 case 4: return BFD_RELOC_X86_64_32S
;
2640 case 1: return BFD_RELOC_8
;
2641 case 2: return BFD_RELOC_16
;
2642 case 4: return BFD_RELOC_32
;
2643 case 8: return BFD_RELOC_64
;
2645 as_bad (_("cannot do %s %u byte relocation"),
2646 sign
> 0 ? "signed" : "unsigned", size
);
2652 /* Here we decide which fixups can be adjusted to make them relative to
2653 the beginning of the section instead of the symbol. Basically we need
2654 to make sure that the dynamic relocations are done correctly, so in
2655 some cases we force the original symbol to be used. */
2658 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2664 /* Don't adjust pc-relative references to merge sections in 64-bit
2666 if (use_rela_relocations
2667 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2671 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2672 and changed later by validate_fix. */
2673 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2674 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2677 /* adjust_reloc_syms doesn't know about the GOT. */
2678 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2679 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2680 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2681 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2682 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2683 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2684 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2685 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2686 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2687 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2688 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2689 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2690 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2691 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2692 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2693 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2694 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2695 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2696 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2697 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2698 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2699 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2700 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2701 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2702 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2703 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2704 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2705 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2712 intel_float_operand (const char *mnemonic
)
2714 /* Note that the value returned is meaningful only for opcodes with (memory)
2715 operands, hence the code here is free to improperly handle opcodes that
2716 have no operands (for better performance and smaller code). */
2718 if (mnemonic
[0] != 'f')
2719 return 0; /* non-math */
2721 switch (mnemonic
[1])
2723 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2724 the fs segment override prefix not currently handled because no
2725 call path can make opcodes without operands get here */
2727 return 2 /* integer op */;
2729 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2730 return 3; /* fldcw/fldenv */
2733 if (mnemonic
[2] != 'o' /* fnop */)
2734 return 3; /* non-waiting control op */
2737 if (mnemonic
[2] == 's')
2738 return 3; /* frstor/frstpm */
2741 if (mnemonic
[2] == 'a')
2742 return 3; /* fsave */
2743 if (mnemonic
[2] == 't')
2745 switch (mnemonic
[3])
2747 case 'c': /* fstcw */
2748 case 'd': /* fstdw */
2749 case 'e': /* fstenv */
2750 case 's': /* fsts[gw] */
2756 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2757 return 0; /* fxsave/fxrstor are not really math ops */
2764 /* Build the VEX prefix. */
2767 build_vex_prefix (const insn_template
*t
)
2769 unsigned int register_specifier
;
2770 unsigned int implied_prefix
;
2771 unsigned int vector_length
;
2773 /* Check register specifier. */
2774 if (i
.vex
.register_specifier
)
2776 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2777 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2778 register_specifier
+= 8;
2779 register_specifier
= ~register_specifier
& 0xf;
2782 register_specifier
= 0xf;
2784 /* Use 2-byte VEX prefix by swappping destination and source
2787 && i
.operands
== i
.reg_operands
2788 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2789 && i
.tm
.opcode_modifier
.s
2792 unsigned int xchg
= i
.operands
- 1;
2793 union i386_op temp_op
;
2794 i386_operand_type temp_type
;
2796 temp_type
= i
.types
[xchg
];
2797 i
.types
[xchg
] = i
.types
[0];
2798 i
.types
[0] = temp_type
;
2799 temp_op
= i
.op
[xchg
];
2800 i
.op
[xchg
] = i
.op
[0];
2803 gas_assert (i
.rm
.mode
== 3);
2807 i
.rm
.regmem
= i
.rm
.reg
;
2810 /* Use the next insn. */
2814 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2815 vector_length
= avxscalar
;
2817 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2819 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2824 case DATA_PREFIX_OPCODE
:
2827 case REPE_PREFIX_OPCODE
:
2830 case REPNE_PREFIX_OPCODE
:
2837 /* Use 2-byte VEX prefix if possible. */
2838 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2839 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2840 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2842 /* 2-byte VEX prefix. */
2846 i
.vex
.bytes
[0] = 0xc5;
2848 /* Check the REX.R bit. */
2849 r
= (i
.rex
& REX_R
) ? 0 : 1;
2850 i
.vex
.bytes
[1] = (r
<< 7
2851 | register_specifier
<< 3
2852 | vector_length
<< 2
2857 /* 3-byte VEX prefix. */
2862 switch (i
.tm
.opcode_modifier
.vexopcode
)
2866 i
.vex
.bytes
[0] = 0xc4;
2870 i
.vex
.bytes
[0] = 0xc4;
2874 i
.vex
.bytes
[0] = 0xc4;
2878 i
.vex
.bytes
[0] = 0x8f;
2882 i
.vex
.bytes
[0] = 0x8f;
2886 i
.vex
.bytes
[0] = 0x8f;
2892 /* The high 3 bits of the second VEX byte are 1's compliment
2893 of RXB bits from REX. */
2894 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2896 /* Check the REX.W bit. */
2897 w
= (i
.rex
& REX_W
) ? 1 : 0;
2898 if (i
.tm
.opcode_modifier
.vexw
)
2903 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2907 i
.vex
.bytes
[2] = (w
<< 7
2908 | register_specifier
<< 3
2909 | vector_length
<< 2
2915 process_immext (void)
2919 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2921 /* SSE3 Instructions have the fixed operands with an opcode
2922 suffix which is coded in the same place as an 8-bit immediate
2923 field would be. Here we check those operands and remove them
2927 for (x
= 0; x
< i
.operands
; x
++)
2928 if (i
.op
[x
].regs
->reg_num
!= x
)
2929 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2930 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2936 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2937 which is coded in the same place as an 8-bit immediate field
2938 would be. Here we fake an 8-bit immediate operand from the
2939 opcode suffix stored in tm.extension_opcode.
2941 AVX instructions also use this encoding, for some of
2942 3 argument instructions. */
2944 gas_assert (i
.imm_operands
== 0
2946 || (i
.tm
.opcode_modifier
.vex
2947 && i
.operands
<= 4)));
2949 exp
= &im_expressions
[i
.imm_operands
++];
2950 i
.op
[i
.operands
].imms
= exp
;
2951 i
.types
[i
.operands
] = imm8
;
2953 exp
->X_op
= O_constant
;
2954 exp
->X_add_number
= i
.tm
.extension_opcode
;
2955 i
.tm
.extension_opcode
= None
;
2958 /* This is the guts of the machine-dependent assembler. LINE points to a
2959 machine dependent instruction. This function is supposed to emit
2960 the frags/bytes it assembles to. */
2963 md_assemble (char *line
)
2966 char mnemonic
[MAX_MNEM_SIZE
];
2967 const insn_template
*t
;
2969 /* Initialize globals. */
2970 memset (&i
, '\0', sizeof (i
));
2971 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2972 i
.reloc
[j
] = NO_RELOC
;
2973 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2974 memset (im_expressions
, '\0', sizeof (im_expressions
));
2975 save_stack_p
= save_stack
;
2977 /* First parse an instruction mnemonic & call i386_operand for the operands.
2978 We assume that the scrubber has arranged it so that line[0] is the valid
2979 start of a (possibly prefixed) mnemonic. */
2981 line
= parse_insn (line
, mnemonic
);
2985 line
= parse_operands (line
, mnemonic
);
2990 /* Now we've parsed the mnemonic into a set of templates, and have the
2991 operands at hand. */
2993 /* All intel opcodes have reversed operands except for "bound" and
2994 "enter". We also don't reverse intersegment "jmp" and "call"
2995 instructions with 2 immediate operands so that the immediate segment
2996 precedes the offset, as it does when in AT&T mode. */
2999 && (strcmp (mnemonic
, "bound") != 0)
3000 && (strcmp (mnemonic
, "invlpga") != 0)
3001 && !(operand_type_check (i
.types
[0], imm
)
3002 && operand_type_check (i
.types
[1], imm
)))
3005 /* The order of the immediates should be reversed
3006 for 2 immediates extrq and insertq instructions */
3007 if (i
.imm_operands
== 2
3008 && (strcmp (mnemonic
, "extrq") == 0
3009 || strcmp (mnemonic
, "insertq") == 0))
3010 swap_2_operands (0, 1);
3015 /* Don't optimize displacement for movabs since it only takes 64bit
3018 && !i
.disp32_encoding
3019 && (flag_code
!= CODE_64BIT
3020 || strcmp (mnemonic
, "movabs") != 0))
3023 /* Next, we find a template that matches the given insn,
3024 making sure the overlap of the given operands types is consistent
3025 with the template operand types. */
3027 if (!(t
= match_template ()))
3030 if (sse_check
!= sse_check_none
3031 && !i
.tm
.opcode_modifier
.noavx
3032 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3033 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3034 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3035 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3036 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3037 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3039 (sse_check
== sse_check_warning
3041 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3044 /* Zap movzx and movsx suffix. The suffix has been set from
3045 "word ptr" or "byte ptr" on the source operand in Intel syntax
3046 or extracted from mnemonic in AT&T syntax. But we'll use
3047 the destination register to choose the suffix for encoding. */
3048 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3050 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3051 there is no suffix, the default will be byte extension. */
3052 if (i
.reg_operands
!= 2
3055 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3060 if (i
.tm
.opcode_modifier
.fwait
)
3061 if (!add_prefix (FWAIT_OPCODE
))
3064 /* Check for lock without a lockable instruction. Destination operand
3065 must be memory unless it is xchg (0x86). */
3066 if (i
.prefix
[LOCK_PREFIX
]
3067 && (!i
.tm
.opcode_modifier
.islockable
3068 || i
.mem_operands
== 0
3069 || (i
.tm
.base_opcode
!= 0x86
3070 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3072 as_bad (_("expecting lockable instruction after `lock'"));
3076 /* Check string instruction segment overrides. */
3077 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3079 if (!check_string ())
3081 i
.disp_operands
= 0;
3084 if (!process_suffix ())
3087 /* Update operand types. */
3088 for (j
= 0; j
< i
.operands
; j
++)
3089 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3091 /* Make still unresolved immediate matches conform to size of immediate
3092 given in i.suffix. */
3093 if (!finalize_imm ())
3096 if (i
.types
[0].bitfield
.imm1
)
3097 i
.imm_operands
= 0; /* kludge for shift insns. */
3099 /* We only need to check those implicit registers for instructions
3100 with 3 operands or less. */
3101 if (i
.operands
<= 3)
3102 for (j
= 0; j
< i
.operands
; j
++)
3103 if (i
.types
[j
].bitfield
.inoutportreg
3104 || i
.types
[j
].bitfield
.shiftcount
3105 || i
.types
[j
].bitfield
.acc
3106 || i
.types
[j
].bitfield
.floatacc
)
3109 /* ImmExt should be processed after SSE2AVX. */
3110 if (!i
.tm
.opcode_modifier
.sse2avx
3111 && i
.tm
.opcode_modifier
.immext
)
3114 /* For insns with operands there are more diddles to do to the opcode. */
3117 if (!process_operands ())
3120 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3122 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3123 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3126 if (i
.tm
.opcode_modifier
.vex
)
3127 build_vex_prefix (t
);
3129 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3130 instructions may define INT_OPCODE as well, so avoid this corner
3131 case for those instructions that use MODRM. */
3132 if (i
.tm
.base_opcode
== INT_OPCODE
3133 && !i
.tm
.opcode_modifier
.modrm
3134 && i
.op
[0].imms
->X_add_number
== 3)
3136 i
.tm
.base_opcode
= INT3_OPCODE
;
3140 if ((i
.tm
.opcode_modifier
.jump
3141 || i
.tm
.opcode_modifier
.jumpbyte
3142 || i
.tm
.opcode_modifier
.jumpdword
)
3143 && i
.op
[0].disps
->X_op
== O_constant
)
3145 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3146 the absolute address given by the constant. Since ix86 jumps and
3147 calls are pc relative, we need to generate a reloc. */
3148 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3149 i
.op
[0].disps
->X_op
= O_symbol
;
3152 if (i
.tm
.opcode_modifier
.rex64
)
3155 /* For 8 bit registers we need an empty rex prefix. Also if the
3156 instruction already has a prefix, we need to convert old
3157 registers to new ones. */
3159 if ((i
.types
[0].bitfield
.reg8
3160 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3161 || (i
.types
[1].bitfield
.reg8
3162 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3163 || ((i
.types
[0].bitfield
.reg8
3164 || i
.types
[1].bitfield
.reg8
)
3169 i
.rex
|= REX_OPCODE
;
3170 for (x
= 0; x
< 2; x
++)
3172 /* Look for 8 bit operand that uses old registers. */
3173 if (i
.types
[x
].bitfield
.reg8
3174 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3176 /* In case it is "hi" register, give up. */
3177 if (i
.op
[x
].regs
->reg_num
> 3)
3178 as_bad (_("can't encode register '%s%s' in an "
3179 "instruction requiring REX prefix."),
3180 register_prefix
, i
.op
[x
].regs
->reg_name
);
3182 /* Otherwise it is equivalent to the extended register.
3183 Since the encoding doesn't change this is merely
3184 cosmetic cleanup for debug output. */
3186 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3192 add_prefix (REX_OPCODE
| i
.rex
);
3194 /* We are ready to output the insn. */
3199 parse_insn (char *line
, char *mnemonic
)
3202 char *token_start
= l
;
3205 const insn_template
*t
;
3208 /* Non-zero if we found a prefix only acceptable with string insns. */
3209 const char *expecting_string_instruction
= NULL
;
3214 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3219 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3221 as_bad (_("no such instruction: `%s'"), token_start
);
3226 if (!is_space_char (*l
)
3227 && *l
!= END_OF_INSN
3229 || (*l
!= PREFIX_SEPARATOR
3232 as_bad (_("invalid character %s in mnemonic"),
3233 output_invalid (*l
));
3236 if (token_start
== l
)
3238 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3239 as_bad (_("expecting prefix; got nothing"));
3241 as_bad (_("expecting mnemonic; got nothing"));
3245 /* Look up instruction (or prefix) via hash table. */
3246 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3248 if (*l
!= END_OF_INSN
3249 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3250 && current_templates
3251 && current_templates
->start
->opcode_modifier
.isprefix
)
3253 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3255 as_bad ((flag_code
!= CODE_64BIT
3256 ? _("`%s' is only supported in 64-bit mode")
3257 : _("`%s' is not supported in 64-bit mode")),
3258 current_templates
->start
->name
);
3261 /* If we are in 16-bit mode, do not allow addr16 or data16.
3262 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3263 if ((current_templates
->start
->opcode_modifier
.size16
3264 || current_templates
->start
->opcode_modifier
.size32
)
3265 && flag_code
!= CODE_64BIT
3266 && (current_templates
->start
->opcode_modifier
.size32
3267 ^ (flag_code
== CODE_16BIT
)))
3269 as_bad (_("redundant %s prefix"),
3270 current_templates
->start
->name
);
3273 /* Add prefix, checking for repeated prefixes. */
3274 switch (add_prefix (current_templates
->start
->base_opcode
))
3279 expecting_string_instruction
= current_templates
->start
->name
;
3284 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3291 if (!current_templates
)
3293 /* Check if we should swap operand or force 32bit displacement in
3295 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3297 else if (mnem_p
- 4 == dot_p
3301 i
.disp32_encoding
= 1;
3306 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3309 if (!current_templates
)
3312 /* See if we can get a match by trimming off a suffix. */
3315 case WORD_MNEM_SUFFIX
:
3316 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3317 i
.suffix
= SHORT_MNEM_SUFFIX
;
3319 case BYTE_MNEM_SUFFIX
:
3320 case QWORD_MNEM_SUFFIX
:
3321 i
.suffix
= mnem_p
[-1];
3323 current_templates
= (const templates
*) hash_find (op_hash
,
3326 case SHORT_MNEM_SUFFIX
:
3327 case LONG_MNEM_SUFFIX
:
3330 i
.suffix
= mnem_p
[-1];
3332 current_templates
= (const templates
*) hash_find (op_hash
,
3341 if (intel_float_operand (mnemonic
) == 1)
3342 i
.suffix
= SHORT_MNEM_SUFFIX
;
3344 i
.suffix
= LONG_MNEM_SUFFIX
;
3346 current_templates
= (const templates
*) hash_find (op_hash
,
3351 if (!current_templates
)
3353 as_bad (_("no such instruction: `%s'"), token_start
);
3358 if (current_templates
->start
->opcode_modifier
.jump
3359 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3361 /* Check for a branch hint. We allow ",pt" and ",pn" for
3362 predict taken and predict not taken respectively.
3363 I'm not sure that branch hints actually do anything on loop
3364 and jcxz insns (JumpByte) for current Pentium4 chips. They
3365 may work in the future and it doesn't hurt to accept them
3367 if (l
[0] == ',' && l
[1] == 'p')
3371 if (!add_prefix (DS_PREFIX_OPCODE
))
3375 else if (l
[2] == 'n')
3377 if (!add_prefix (CS_PREFIX_OPCODE
))
3383 /* Any other comma loses. */
3386 as_bad (_("invalid character %s in mnemonic"),
3387 output_invalid (*l
));
3391 /* Check if instruction is supported on specified architecture. */
3393 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3395 supported
|= cpu_flags_match (t
);
3396 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3400 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3402 as_bad (flag_code
== CODE_64BIT
3403 ? _("`%s' is not supported in 64-bit mode")
3404 : _("`%s' is only supported in 64-bit mode"),
3405 current_templates
->start
->name
);
3408 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3410 as_bad (_("`%s' is not supported on `%s%s'"),
3411 current_templates
->start
->name
,
3412 cpu_arch_name
? cpu_arch_name
: default_arch
,
3413 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3418 if (!cpu_arch_flags
.bitfield
.cpui386
3419 && (flag_code
!= CODE_16BIT
))
3421 as_warn (_("use .code16 to ensure correct addressing mode"));
3424 /* Check for rep/repne without a string instruction. */
3425 if (expecting_string_instruction
)
3427 static templates override
;
3429 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3430 if (t
->opcode_modifier
.isstring
)
3432 if (t
>= current_templates
->end
)
3434 as_bad (_("expecting string instruction after `%s'"),
3435 expecting_string_instruction
);
3438 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3439 if (!t
->opcode_modifier
.isstring
)
3442 current_templates
= &override
;
3449 parse_operands (char *l
, const char *mnemonic
)
3453 /* 1 if operand is pending after ','. */
3454 unsigned int expecting_operand
= 0;
3456 /* Non-zero if operand parens not balanced. */
3457 unsigned int paren_not_balanced
;
3459 while (*l
!= END_OF_INSN
)
3461 /* Skip optional white space before operand. */
3462 if (is_space_char (*l
))
3464 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3466 as_bad (_("invalid character %s before operand %d"),
3467 output_invalid (*l
),
3471 token_start
= l
; /* after white space */
3472 paren_not_balanced
= 0;
3473 while (paren_not_balanced
|| *l
!= ',')
3475 if (*l
== END_OF_INSN
)
3477 if (paren_not_balanced
)
3480 as_bad (_("unbalanced parenthesis in operand %d."),
3483 as_bad (_("unbalanced brackets in operand %d."),
3488 break; /* we are done */
3490 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3492 as_bad (_("invalid character %s in operand %d"),
3493 output_invalid (*l
),
3500 ++paren_not_balanced
;
3502 --paren_not_balanced
;
3507 ++paren_not_balanced
;
3509 --paren_not_balanced
;
3513 if (l
!= token_start
)
3514 { /* Yes, we've read in another operand. */
3515 unsigned int operand_ok
;
3516 this_operand
= i
.operands
++;
3517 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3518 if (i
.operands
> MAX_OPERANDS
)
3520 as_bad (_("spurious operands; (%d operands/instruction max)"),
3524 /* Now parse operand adding info to 'i' as we go along. */
3525 END_STRING_AND_SAVE (l
);
3529 i386_intel_operand (token_start
,
3530 intel_float_operand (mnemonic
));
3532 operand_ok
= i386_att_operand (token_start
);
3534 RESTORE_END_STRING (l
);
3540 if (expecting_operand
)
3542 expecting_operand_after_comma
:
3543 as_bad (_("expecting operand after ','; got nothing"));
3548 as_bad (_("expecting operand before ','; got nothing"));
3553 /* Now *l must be either ',' or END_OF_INSN. */
3556 if (*++l
== END_OF_INSN
)
3558 /* Just skip it, if it's \n complain. */
3559 goto expecting_operand_after_comma
;
3561 expecting_operand
= 1;
3568 swap_2_operands (int xchg1
, int xchg2
)
3570 union i386_op temp_op
;
3571 i386_operand_type temp_type
;
3572 enum bfd_reloc_code_real temp_reloc
;
3574 temp_type
= i
.types
[xchg2
];
3575 i
.types
[xchg2
] = i
.types
[xchg1
];
3576 i
.types
[xchg1
] = temp_type
;
3577 temp_op
= i
.op
[xchg2
];
3578 i
.op
[xchg2
] = i
.op
[xchg1
];
3579 i
.op
[xchg1
] = temp_op
;
3580 temp_reloc
= i
.reloc
[xchg2
];
3581 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3582 i
.reloc
[xchg1
] = temp_reloc
;
3586 swap_operands (void)
3592 swap_2_operands (1, i
.operands
- 2);
3595 swap_2_operands (0, i
.operands
- 1);
3601 if (i
.mem_operands
== 2)
3603 const seg_entry
*temp_seg
;
3604 temp_seg
= i
.seg
[0];
3605 i
.seg
[0] = i
.seg
[1];
3606 i
.seg
[1] = temp_seg
;
3610 /* Try to ensure constant immediates are represented in the smallest
3615 char guess_suffix
= 0;
3619 guess_suffix
= i
.suffix
;
3620 else if (i
.reg_operands
)
3622 /* Figure out a suffix from the last register operand specified.
3623 We can't do this properly yet, ie. excluding InOutPortReg,
3624 but the following works for instructions with immediates.
3625 In any case, we can't set i.suffix yet. */
3626 for (op
= i
.operands
; --op
>= 0;)
3627 if (i
.types
[op
].bitfield
.reg8
)
3629 guess_suffix
= BYTE_MNEM_SUFFIX
;
3632 else if (i
.types
[op
].bitfield
.reg16
)
3634 guess_suffix
= WORD_MNEM_SUFFIX
;
3637 else if (i
.types
[op
].bitfield
.reg32
)
3639 guess_suffix
= LONG_MNEM_SUFFIX
;
3642 else if (i
.types
[op
].bitfield
.reg64
)
3644 guess_suffix
= QWORD_MNEM_SUFFIX
;
3648 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3649 guess_suffix
= WORD_MNEM_SUFFIX
;
3651 for (op
= i
.operands
; --op
>= 0;)
3652 if (operand_type_check (i
.types
[op
], imm
))
3654 switch (i
.op
[op
].imms
->X_op
)
3657 /* If a suffix is given, this operand may be shortened. */
3658 switch (guess_suffix
)
3660 case LONG_MNEM_SUFFIX
:
3661 i
.types
[op
].bitfield
.imm32
= 1;
3662 i
.types
[op
].bitfield
.imm64
= 1;
3664 case WORD_MNEM_SUFFIX
:
3665 i
.types
[op
].bitfield
.imm16
= 1;
3666 i
.types
[op
].bitfield
.imm32
= 1;
3667 i
.types
[op
].bitfield
.imm32s
= 1;
3668 i
.types
[op
].bitfield
.imm64
= 1;
3670 case BYTE_MNEM_SUFFIX
:
3671 i
.types
[op
].bitfield
.imm8
= 1;
3672 i
.types
[op
].bitfield
.imm8s
= 1;
3673 i
.types
[op
].bitfield
.imm16
= 1;
3674 i
.types
[op
].bitfield
.imm32
= 1;
3675 i
.types
[op
].bitfield
.imm32s
= 1;
3676 i
.types
[op
].bitfield
.imm64
= 1;
3680 /* If this operand is at most 16 bits, convert it
3681 to a signed 16 bit number before trying to see
3682 whether it will fit in an even smaller size.
3683 This allows a 16-bit operand such as $0xffe0 to
3684 be recognised as within Imm8S range. */
3685 if ((i
.types
[op
].bitfield
.imm16
)
3686 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3688 i
.op
[op
].imms
->X_add_number
=
3689 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3691 if ((i
.types
[op
].bitfield
.imm32
)
3692 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3695 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3696 ^ ((offsetT
) 1 << 31))
3697 - ((offsetT
) 1 << 31));
3700 = operand_type_or (i
.types
[op
],
3701 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3703 /* We must avoid matching of Imm32 templates when 64bit
3704 only immediate is available. */
3705 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3706 i
.types
[op
].bitfield
.imm32
= 0;
3713 /* Symbols and expressions. */
3715 /* Convert symbolic operand to proper sizes for matching, but don't
3716 prevent matching a set of insns that only supports sizes other
3717 than those matching the insn suffix. */
3719 i386_operand_type mask
, allowed
;
3720 const insn_template
*t
;
3722 operand_type_set (&mask
, 0);
3723 operand_type_set (&allowed
, 0);
3725 for (t
= current_templates
->start
;
3726 t
< current_templates
->end
;
3728 allowed
= operand_type_or (allowed
,
3729 t
->operand_types
[op
]);
3730 switch (guess_suffix
)
3732 case QWORD_MNEM_SUFFIX
:
3733 mask
.bitfield
.imm64
= 1;
3734 mask
.bitfield
.imm32s
= 1;
3736 case LONG_MNEM_SUFFIX
:
3737 mask
.bitfield
.imm32
= 1;
3739 case WORD_MNEM_SUFFIX
:
3740 mask
.bitfield
.imm16
= 1;
3742 case BYTE_MNEM_SUFFIX
:
3743 mask
.bitfield
.imm8
= 1;
3748 allowed
= operand_type_and (mask
, allowed
);
3749 if (!operand_type_all_zero (&allowed
))
3750 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3757 /* Try to use the smallest displacement type too. */
3759 optimize_disp (void)
3763 for (op
= i
.operands
; --op
>= 0;)
3764 if (operand_type_check (i
.types
[op
], disp
))
3766 if (i
.op
[op
].disps
->X_op
== O_constant
)
3768 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3770 if (i
.types
[op
].bitfield
.disp16
3771 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3773 /* If this operand is at most 16 bits, convert
3774 to a signed 16 bit number and don't use 64bit
3776 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3777 i
.types
[op
].bitfield
.disp64
= 0;
3779 if (i
.types
[op
].bitfield
.disp32
3780 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3782 /* If this operand is at most 32 bits, convert
3783 to a signed 32 bit number and don't use 64bit
3785 op_disp
&= (((offsetT
) 2 << 31) - 1);
3786 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3787 i
.types
[op
].bitfield
.disp64
= 0;
3789 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3791 i
.types
[op
].bitfield
.disp8
= 0;
3792 i
.types
[op
].bitfield
.disp16
= 0;
3793 i
.types
[op
].bitfield
.disp32
= 0;
3794 i
.types
[op
].bitfield
.disp32s
= 0;
3795 i
.types
[op
].bitfield
.disp64
= 0;
3799 else if (flag_code
== CODE_64BIT
)
3801 if (fits_in_signed_long (op_disp
))
3803 i
.types
[op
].bitfield
.disp64
= 0;
3804 i
.types
[op
].bitfield
.disp32s
= 1;
3806 if (i
.prefix
[ADDR_PREFIX
]
3807 && fits_in_unsigned_long (op_disp
))
3808 i
.types
[op
].bitfield
.disp32
= 1;
3810 if ((i
.types
[op
].bitfield
.disp32
3811 || i
.types
[op
].bitfield
.disp32s
3812 || i
.types
[op
].bitfield
.disp16
)
3813 && fits_in_signed_byte (op_disp
))
3814 i
.types
[op
].bitfield
.disp8
= 1;
3816 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3817 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3819 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3820 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3821 i
.types
[op
].bitfield
.disp8
= 0;
3822 i
.types
[op
].bitfield
.disp16
= 0;
3823 i
.types
[op
].bitfield
.disp32
= 0;
3824 i
.types
[op
].bitfield
.disp32s
= 0;
3825 i
.types
[op
].bitfield
.disp64
= 0;
3828 /* We only support 64bit displacement on constants. */
3829 i
.types
[op
].bitfield
.disp64
= 0;
3833 /* Check if operands are valid for the instruction. Update VEX
3837 VEX_check_operands (const insn_template
*t
)
3839 if (!t
->opcode_modifier
.vex
)
3842 /* Only check VEX_Imm4, which must be the first operand. */
3843 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3845 if (i
.op
[0].imms
->X_op
!= O_constant
3846 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3852 /* Turn off Imm8 so that update_imm won't complain. */
3853 i
.types
[0] = vec_imm4
;
3859 static const insn_template
*
3860 match_template (void)
3862 /* Points to template once we've found it. */
3863 const insn_template
*t
;
3864 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3865 i386_operand_type overlap4
;
3866 unsigned int found_reverse_match
;
3867 i386_opcode_modifier suffix_check
;
3868 i386_operand_type operand_types
[MAX_OPERANDS
];
3869 int addr_prefix_disp
;
3871 unsigned int found_cpu_match
;
3872 unsigned int check_register
;
3874 #if MAX_OPERANDS != 5
3875 # error "MAX_OPERANDS must be 5."
3878 found_reverse_match
= 0;
3879 addr_prefix_disp
= -1;
3881 memset (&suffix_check
, 0, sizeof (suffix_check
));
3882 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3883 suffix_check
.no_bsuf
= 1;
3884 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3885 suffix_check
.no_wsuf
= 1;
3886 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3887 suffix_check
.no_ssuf
= 1;
3888 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3889 suffix_check
.no_lsuf
= 1;
3890 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3891 suffix_check
.no_qsuf
= 1;
3892 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3893 suffix_check
.no_ldsuf
= 1;
3895 /* Must have right number of operands. */
3896 i
.error
= number_of_operands_mismatch
;
3898 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3900 addr_prefix_disp
= -1;
3902 if (i
.operands
!= t
->operands
)
3905 /* Check processor support. */
3906 i
.error
= unsupported
;
3907 found_cpu_match
= (cpu_flags_match (t
)
3908 == CPU_FLAGS_PERFECT_MATCH
);
3909 if (!found_cpu_match
)
3912 /* Check old gcc support. */
3913 i
.error
= old_gcc_only
;
3914 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3917 /* Check AT&T mnemonic. */
3918 i
.error
= unsupported_with_intel_mnemonic
;
3919 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3922 /* Check AT&T/Intel syntax. */
3923 i
.error
= unsupported_syntax
;
3924 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3925 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3928 /* Check the suffix, except for some instructions in intel mode. */
3929 i
.error
= invalid_instruction_suffix
;
3930 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3931 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3932 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3933 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3934 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3935 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3936 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3939 if (!operand_size_match (t
))
3942 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3943 operand_types
[j
] = t
->operand_types
[j
];
3945 /* In general, don't allow 64-bit operands in 32-bit mode. */
3946 if (i
.suffix
== QWORD_MNEM_SUFFIX
3947 && flag_code
!= CODE_64BIT
3949 ? (!t
->opcode_modifier
.ignoresize
3950 && !intel_float_operand (t
->name
))
3951 : intel_float_operand (t
->name
) != 2)
3952 && ((!operand_types
[0].bitfield
.regmmx
3953 && !operand_types
[0].bitfield
.regxmm
3954 && !operand_types
[0].bitfield
.regymm
)
3955 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3956 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3957 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3958 && (t
->base_opcode
!= 0x0fc7
3959 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3962 /* In general, don't allow 32-bit operands on pre-386. */
3963 else if (i
.suffix
== LONG_MNEM_SUFFIX
3964 && !cpu_arch_flags
.bitfield
.cpui386
3966 ? (!t
->opcode_modifier
.ignoresize
3967 && !intel_float_operand (t
->name
))
3968 : intel_float_operand (t
->name
) != 2)
3969 && ((!operand_types
[0].bitfield
.regmmx
3970 && !operand_types
[0].bitfield
.regxmm
)
3971 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3972 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3975 /* Do not verify operands when there are none. */
3979 /* We've found a match; break out of loop. */
3983 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3984 into Disp32/Disp16/Disp32 operand. */
3985 if (i
.prefix
[ADDR_PREFIX
] != 0)
3987 /* There should be only one Disp operand. */
3991 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3993 if (operand_types
[j
].bitfield
.disp16
)
3995 addr_prefix_disp
= j
;
3996 operand_types
[j
].bitfield
.disp32
= 1;
3997 operand_types
[j
].bitfield
.disp16
= 0;
4003 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4005 if (operand_types
[j
].bitfield
.disp32
)
4007 addr_prefix_disp
= j
;
4008 operand_types
[j
].bitfield
.disp32
= 0;
4009 operand_types
[j
].bitfield
.disp16
= 1;
4015 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4017 if (operand_types
[j
].bitfield
.disp64
)
4019 addr_prefix_disp
= j
;
4020 operand_types
[j
].bitfield
.disp64
= 0;
4021 operand_types
[j
].bitfield
.disp32
= 1;
4029 /* We check register size if needed. */
4030 check_register
= t
->opcode_modifier
.checkregsize
;
4031 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4032 switch (t
->operands
)
4035 if (!operand_type_match (overlap0
, i
.types
[0]))
4039 /* xchg %eax, %eax is a special case. It is an aliase for nop
4040 only in 32bit mode and we can use opcode 0x90. In 64bit
4041 mode, we can't use 0x90 for xchg %eax, %eax since it should
4042 zero-extend %eax to %rax. */
4043 if (flag_code
== CODE_64BIT
4044 && t
->base_opcode
== 0x90
4045 && operand_type_equal (&i
.types
[0], &acc32
)
4046 && operand_type_equal (&i
.types
[1], &acc32
))
4050 /* If we swap operand in encoding, we either match
4051 the next one or reverse direction of operands. */
4052 if (t
->opcode_modifier
.s
)
4054 else if (t
->opcode_modifier
.d
)
4059 /* If we swap operand in encoding, we match the next one. */
4060 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4064 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4065 if (!operand_type_match (overlap0
, i
.types
[0])
4066 || !operand_type_match (overlap1
, i
.types
[1])
4068 && !operand_type_register_match (overlap0
, i
.types
[0],
4070 overlap1
, i
.types
[1],
4073 /* Check if other direction is valid ... */
4074 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4078 /* Try reversing direction of operands. */
4079 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4080 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4081 if (!operand_type_match (overlap0
, i
.types
[0])
4082 || !operand_type_match (overlap1
, i
.types
[1])
4084 && !operand_type_register_match (overlap0
,
4091 /* Does not match either direction. */
4094 /* found_reverse_match holds which of D or FloatDR
4096 if (t
->opcode_modifier
.d
)
4097 found_reverse_match
= Opcode_D
;
4098 else if (t
->opcode_modifier
.floatd
)
4099 found_reverse_match
= Opcode_FloatD
;
4101 found_reverse_match
= 0;
4102 if (t
->opcode_modifier
.floatr
)
4103 found_reverse_match
|= Opcode_FloatR
;
4107 /* Found a forward 2 operand match here. */
4108 switch (t
->operands
)
4111 overlap4
= operand_type_and (i
.types
[4],
4114 overlap3
= operand_type_and (i
.types
[3],
4117 overlap2
= operand_type_and (i
.types
[2],
4122 switch (t
->operands
)
4125 if (!operand_type_match (overlap4
, i
.types
[4])
4126 || !operand_type_register_match (overlap3
,
4134 if (!operand_type_match (overlap3
, i
.types
[3])
4136 && !operand_type_register_match (overlap2
,
4144 /* Here we make use of the fact that there are no
4145 reverse match 3 operand instructions, and all 3
4146 operand instructions only need to be checked for
4147 register consistency between operands 2 and 3. */
4148 if (!operand_type_match (overlap2
, i
.types
[2])
4150 && !operand_type_register_match (overlap1
,
4160 /* Found either forward/reverse 2, 3 or 4 operand match here:
4161 slip through to break. */
4163 if (!found_cpu_match
)
4165 found_reverse_match
= 0;
4169 /* Check if VEX operands are valid. */
4170 if (VEX_check_operands (t
))
4173 /* We've found a match; break out of loop. */
4177 if (t
== current_templates
->end
)
4179 /* We found no match. */
4180 const char *err_msg
;
4185 case operand_size_mismatch
:
4186 err_msg
= _("operand size mismatch");
4188 case operand_type_mismatch
:
4189 err_msg
= _("operand type mismatch");
4191 case register_type_mismatch
:
4192 err_msg
= _("register type mismatch");
4194 case number_of_operands_mismatch
:
4195 err_msg
= _("number of operands mismatch");
4197 case invalid_instruction_suffix
:
4198 err_msg
= _("invalid instruction suffix");
4201 err_msg
= _("Imm4 isn't the first operand");
4204 err_msg
= _("only supported with old gcc");
4206 case unsupported_with_intel_mnemonic
:
4207 err_msg
= _("unsupported with Intel mnemonic");
4209 case unsupported_syntax
:
4210 err_msg
= _("unsupported syntax");
4213 err_msg
= _("unsupported");
4216 as_bad (_("%s for `%s'"), err_msg
,
4217 current_templates
->start
->name
);
4221 if (!quiet_warnings
)
4224 && (i
.types
[0].bitfield
.jumpabsolute
4225 != operand_types
[0].bitfield
.jumpabsolute
))
4227 as_warn (_("indirect %s without `*'"), t
->name
);
4230 if (t
->opcode_modifier
.isprefix
4231 && t
->opcode_modifier
.ignoresize
)
4233 /* Warn them that a data or address size prefix doesn't
4234 affect assembly of the next line of code. */
4235 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4239 /* Copy the template we found. */
4242 if (addr_prefix_disp
!= -1)
4243 i
.tm
.operand_types
[addr_prefix_disp
]
4244 = operand_types
[addr_prefix_disp
];
4246 if (found_reverse_match
)
4248 /* If we found a reverse match we must alter the opcode
4249 direction bit. found_reverse_match holds bits to change
4250 (different for int & float insns). */
4252 i
.tm
.base_opcode
^= found_reverse_match
;
4254 i
.tm
.operand_types
[0] = operand_types
[1];
4255 i
.tm
.operand_types
[1] = operand_types
[0];
4264 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4265 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4267 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4269 as_bad (_("`%s' operand %d must use `%ses' segment"),
4275 /* There's only ever one segment override allowed per instruction.
4276 This instruction possibly has a legal segment override on the
4277 second operand, so copy the segment to where non-string
4278 instructions store it, allowing common code. */
4279 i
.seg
[0] = i
.seg
[1];
4281 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4283 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4285 as_bad (_("`%s' operand %d must use `%ses' segment"),
4296 process_suffix (void)
4298 /* If matched instruction specifies an explicit instruction mnemonic
4300 if (i
.tm
.opcode_modifier
.size16
)
4301 i
.suffix
= WORD_MNEM_SUFFIX
;
4302 else if (i
.tm
.opcode_modifier
.size32
)
4303 i
.suffix
= LONG_MNEM_SUFFIX
;
4304 else if (i
.tm
.opcode_modifier
.size64
)
4305 i
.suffix
= QWORD_MNEM_SUFFIX
;
4306 else if (i
.reg_operands
)
4308 /* If there's no instruction mnemonic suffix we try to invent one
4309 based on register operands. */
4312 /* We take i.suffix from the last register operand specified,
4313 Destination register type is more significant than source
4314 register type. crc32 in SSE4.2 prefers source register
4316 if (i
.tm
.base_opcode
== 0xf20f38f1)
4318 if (i
.types
[0].bitfield
.reg16
)
4319 i
.suffix
= WORD_MNEM_SUFFIX
;
4320 else if (i
.types
[0].bitfield
.reg32
)
4321 i
.suffix
= LONG_MNEM_SUFFIX
;
4322 else if (i
.types
[0].bitfield
.reg64
)
4323 i
.suffix
= QWORD_MNEM_SUFFIX
;
4325 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4327 if (i
.types
[0].bitfield
.reg8
)
4328 i
.suffix
= BYTE_MNEM_SUFFIX
;
4335 if (i
.tm
.base_opcode
== 0xf20f38f1
4336 || i
.tm
.base_opcode
== 0xf20f38f0)
4338 /* We have to know the operand size for crc32. */
4339 as_bad (_("ambiguous memory operand size for `%s`"),
4344 for (op
= i
.operands
; --op
>= 0;)
4345 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4347 if (i
.types
[op
].bitfield
.reg8
)
4349 i
.suffix
= BYTE_MNEM_SUFFIX
;
4352 else if (i
.types
[op
].bitfield
.reg16
)
4354 i
.suffix
= WORD_MNEM_SUFFIX
;
4357 else if (i
.types
[op
].bitfield
.reg32
)
4359 i
.suffix
= LONG_MNEM_SUFFIX
;
4362 else if (i
.types
[op
].bitfield
.reg64
)
4364 i
.suffix
= QWORD_MNEM_SUFFIX
;
4370 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4373 && i
.tm
.opcode_modifier
.ignoresize
4374 && i
.tm
.opcode_modifier
.no_bsuf
)
4376 else if (!check_byte_reg ())
4379 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4382 && i
.tm
.opcode_modifier
.ignoresize
4383 && i
.tm
.opcode_modifier
.no_lsuf
)
4385 else if (!check_long_reg ())
4388 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4391 && i
.tm
.opcode_modifier
.ignoresize
4392 && i
.tm
.opcode_modifier
.no_qsuf
)
4394 else if (!check_qword_reg ())
4397 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4400 && i
.tm
.opcode_modifier
.ignoresize
4401 && i
.tm
.opcode_modifier
.no_wsuf
)
4403 else if (!check_word_reg ())
4406 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4407 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4409 /* Skip if the instruction has x/y suffix. match_template
4410 should check if it is a valid suffix. */
4412 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4413 /* Do nothing if the instruction is going to ignore the prefix. */
4418 else if (i
.tm
.opcode_modifier
.defaultsize
4420 /* exclude fldenv/frstor/fsave/fstenv */
4421 && i
.tm
.opcode_modifier
.no_ssuf
)
4423 i
.suffix
= stackop_size
;
4425 else if (intel_syntax
4427 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4428 || i
.tm
.opcode_modifier
.jumpbyte
4429 || i
.tm
.opcode_modifier
.jumpintersegment
4430 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4431 && i
.tm
.extension_opcode
<= 3)))
4436 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4438 i
.suffix
= QWORD_MNEM_SUFFIX
;
4442 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4443 i
.suffix
= LONG_MNEM_SUFFIX
;
4446 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4447 i
.suffix
= WORD_MNEM_SUFFIX
;
4456 if (i
.tm
.opcode_modifier
.w
)
4458 as_bad (_("no instruction mnemonic suffix given and "
4459 "no register operands; can't size instruction"));
4465 unsigned int suffixes
;
4467 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4468 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4470 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4472 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4474 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4476 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4479 /* There are more than suffix matches. */
4480 if (i
.tm
.opcode_modifier
.w
4481 || ((suffixes
& (suffixes
- 1))
4482 && !i
.tm
.opcode_modifier
.defaultsize
4483 && !i
.tm
.opcode_modifier
.ignoresize
))
4485 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4491 /* Change the opcode based on the operand size given by i.suffix;
4492 We don't need to change things for byte insns. */
4495 && i
.suffix
!= BYTE_MNEM_SUFFIX
4496 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4497 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4499 /* It's not a byte, select word/dword operation. */
4500 if (i
.tm
.opcode_modifier
.w
)
4502 if (i
.tm
.opcode_modifier
.shortform
)
4503 i
.tm
.base_opcode
|= 8;
4505 i
.tm
.base_opcode
|= 1;
4508 /* Now select between word & dword operations via the operand
4509 size prefix, except for instructions that will ignore this
4511 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4513 /* The address size override prefix changes the size of the
4515 if ((flag_code
== CODE_32BIT
4516 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4517 || (flag_code
!= CODE_32BIT
4518 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4519 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4522 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4523 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4524 && !i
.tm
.opcode_modifier
.ignoresize
4525 && !i
.tm
.opcode_modifier
.floatmf
4526 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4527 || (flag_code
== CODE_64BIT
4528 && i
.tm
.opcode_modifier
.jumpbyte
)))
4530 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4532 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4533 prefix
= ADDR_PREFIX_OPCODE
;
4535 if (!add_prefix (prefix
))
4539 /* Set mode64 for an operand. */
4540 if (i
.suffix
== QWORD_MNEM_SUFFIX
4541 && flag_code
== CODE_64BIT
4542 && !i
.tm
.opcode_modifier
.norex64
)
4544 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4545 need rex64. cmpxchg8b is also a special case. */
4546 if (! (i
.operands
== 2
4547 && i
.tm
.base_opcode
== 0x90
4548 && i
.tm
.extension_opcode
== None
4549 && operand_type_equal (&i
.types
[0], &acc64
)
4550 && operand_type_equal (&i
.types
[1], &acc64
))
4551 && ! (i
.operands
== 1
4552 && i
.tm
.base_opcode
== 0xfc7
4553 && i
.tm
.extension_opcode
== 1
4554 && !operand_type_check (i
.types
[0], reg
)
4555 && operand_type_check (i
.types
[0], anymem
)))
4559 /* Size floating point instruction. */
4560 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4561 if (i
.tm
.opcode_modifier
.floatmf
)
4562 i
.tm
.base_opcode
^= 4;
4569 check_byte_reg (void)
4573 for (op
= i
.operands
; --op
>= 0;)
4575 /* If this is an eight bit register, it's OK. If it's the 16 or
4576 32 bit version of an eight bit register, we will just use the
4577 low portion, and that's OK too. */
4578 if (i
.types
[op
].bitfield
.reg8
)
4581 /* crc32 doesn't generate this warning. */
4582 if (i
.tm
.base_opcode
== 0xf20f38f0)
4585 if ((i
.types
[op
].bitfield
.reg16
4586 || i
.types
[op
].bitfield
.reg32
4587 || i
.types
[op
].bitfield
.reg64
)
4588 && i
.op
[op
].regs
->reg_num
< 4)
4590 /* Prohibit these changes in the 64bit mode, since the
4591 lowering is more complicated. */
4592 if (flag_code
== CODE_64BIT
4593 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4595 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4596 register_prefix
, i
.op
[op
].regs
->reg_name
,
4600 #if REGISTER_WARNINGS
4602 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4603 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4605 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4606 ? REGNAM_AL
- REGNAM_AX
4607 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4609 i
.op
[op
].regs
->reg_name
,
4614 /* Any other register is bad. */
4615 if (i
.types
[op
].bitfield
.reg16
4616 || i
.types
[op
].bitfield
.reg32
4617 || i
.types
[op
].bitfield
.reg64
4618 || i
.types
[op
].bitfield
.regmmx
4619 || i
.types
[op
].bitfield
.regxmm
4620 || i
.types
[op
].bitfield
.regymm
4621 || i
.types
[op
].bitfield
.sreg2
4622 || i
.types
[op
].bitfield
.sreg3
4623 || i
.types
[op
].bitfield
.control
4624 || i
.types
[op
].bitfield
.debug
4625 || i
.types
[op
].bitfield
.test
4626 || i
.types
[op
].bitfield
.floatreg
4627 || i
.types
[op
].bitfield
.floatacc
)
4629 as_bad (_("`%s%s' not allowed with `%s%c'"),
4631 i
.op
[op
].regs
->reg_name
,
4641 check_long_reg (void)
4645 for (op
= i
.operands
; --op
>= 0;)
4646 /* Reject eight bit registers, except where the template requires
4647 them. (eg. movzb) */
4648 if (i
.types
[op
].bitfield
.reg8
4649 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4650 || i
.tm
.operand_types
[op
].bitfield
.reg32
4651 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4653 as_bad (_("`%s%s' not allowed with `%s%c'"),
4655 i
.op
[op
].regs
->reg_name
,
4660 /* Warn if the e prefix on a general reg is missing. */
4661 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4662 && i
.types
[op
].bitfield
.reg16
4663 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4664 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4666 /* Prohibit these changes in the 64bit mode, since the
4667 lowering is more complicated. */
4668 if (flag_code
== CODE_64BIT
)
4670 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4671 register_prefix
, i
.op
[op
].regs
->reg_name
,
4675 #if REGISTER_WARNINGS
4677 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4679 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4681 i
.op
[op
].regs
->reg_name
,
4685 /* Warn if the r prefix on a general reg is missing. */
4686 else if (i
.types
[op
].bitfield
.reg64
4687 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4688 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4691 && i
.tm
.opcode_modifier
.toqword
4692 && !i
.types
[0].bitfield
.regxmm
)
4694 /* Convert to QWORD. We want REX byte. */
4695 i
.suffix
= QWORD_MNEM_SUFFIX
;
4699 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4700 register_prefix
, i
.op
[op
].regs
->reg_name
,
4709 check_qword_reg (void)
4713 for (op
= i
.operands
; --op
>= 0; )
4714 /* Reject eight bit registers, except where the template requires
4715 them. (eg. movzb) */
4716 if (i
.types
[op
].bitfield
.reg8
4717 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4718 || i
.tm
.operand_types
[op
].bitfield
.reg32
4719 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4721 as_bad (_("`%s%s' not allowed with `%s%c'"),
4723 i
.op
[op
].regs
->reg_name
,
4728 /* Warn if the e prefix on a general reg is missing. */
4729 else if ((i
.types
[op
].bitfield
.reg16
4730 || i
.types
[op
].bitfield
.reg32
)
4731 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4732 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4734 /* Prohibit these changes in the 64bit mode, since the
4735 lowering is more complicated. */
4737 && i
.tm
.opcode_modifier
.todword
4738 && !i
.types
[0].bitfield
.regxmm
)
4740 /* Convert to DWORD. We don't want REX byte. */
4741 i
.suffix
= LONG_MNEM_SUFFIX
;
4745 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4746 register_prefix
, i
.op
[op
].regs
->reg_name
,
4755 check_word_reg (void)
4758 for (op
= i
.operands
; --op
>= 0;)
4759 /* Reject eight bit registers, except where the template requires
4760 them. (eg. movzb) */
4761 if (i
.types
[op
].bitfield
.reg8
4762 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4763 || i
.tm
.operand_types
[op
].bitfield
.reg32
4764 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4766 as_bad (_("`%s%s' not allowed with `%s%c'"),
4768 i
.op
[op
].regs
->reg_name
,
4773 /* Warn if the e prefix on a general reg is present. */
4774 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4775 && i
.types
[op
].bitfield
.reg32
4776 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4777 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4779 /* Prohibit these changes in the 64bit mode, since the
4780 lowering is more complicated. */
4781 if (flag_code
== CODE_64BIT
)
4783 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4784 register_prefix
, i
.op
[op
].regs
->reg_name
,
4789 #if REGISTER_WARNINGS
4790 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4792 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4794 i
.op
[op
].regs
->reg_name
,
4802 update_imm (unsigned int j
)
4804 i386_operand_type overlap
= i
.types
[j
];
4805 if ((overlap
.bitfield
.imm8
4806 || overlap
.bitfield
.imm8s
4807 || overlap
.bitfield
.imm16
4808 || overlap
.bitfield
.imm32
4809 || overlap
.bitfield
.imm32s
4810 || overlap
.bitfield
.imm64
)
4811 && !operand_type_equal (&overlap
, &imm8
)
4812 && !operand_type_equal (&overlap
, &imm8s
)
4813 && !operand_type_equal (&overlap
, &imm16
)
4814 && !operand_type_equal (&overlap
, &imm32
)
4815 && !operand_type_equal (&overlap
, &imm32s
)
4816 && !operand_type_equal (&overlap
, &imm64
))
4820 i386_operand_type temp
;
4822 operand_type_set (&temp
, 0);
4823 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4825 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4826 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4828 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4829 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4830 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4832 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4833 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4836 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4839 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4840 || operand_type_equal (&overlap
, &imm16_32
)
4841 || operand_type_equal (&overlap
, &imm16_32s
))
4843 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4848 if (!operand_type_equal (&overlap
, &imm8
)
4849 && !operand_type_equal (&overlap
, &imm8s
)
4850 && !operand_type_equal (&overlap
, &imm16
)
4851 && !operand_type_equal (&overlap
, &imm32
)
4852 && !operand_type_equal (&overlap
, &imm32s
)
4853 && !operand_type_equal (&overlap
, &imm64
))
4855 as_bad (_("no instruction mnemonic suffix given; "
4856 "can't determine immediate size"));
4860 i
.types
[j
] = overlap
;
4870 /* Update the first 2 immediate operands. */
4871 n
= i
.operands
> 2 ? 2 : i
.operands
;
4874 for (j
= 0; j
< n
; j
++)
4875 if (update_imm (j
) == 0)
4878 /* The 3rd operand can't be immediate operand. */
4879 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4886 bad_implicit_operand (int xmm
)
4888 const char *ireg
= xmm
? "xmm0" : "ymm0";
4891 as_bad (_("the last operand of `%s' must be `%s%s'"),
4892 i
.tm
.name
, register_prefix
, ireg
);
4894 as_bad (_("the first operand of `%s' must be `%s%s'"),
4895 i
.tm
.name
, register_prefix
, ireg
);
4900 process_operands (void)
4902 /* Default segment register this instruction will use for memory
4903 accesses. 0 means unknown. This is only for optimizing out
4904 unnecessary segment overrides. */
4905 const seg_entry
*default_seg
= 0;
4907 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4909 unsigned int dupl
= i
.operands
;
4910 unsigned int dest
= dupl
- 1;
4913 /* The destination must be an xmm register. */
4914 gas_assert (i
.reg_operands
4915 && MAX_OPERANDS
> dupl
4916 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4918 if (i
.tm
.opcode_modifier
.firstxmm0
)
4920 /* The first operand is implicit and must be xmm0. */
4921 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4922 if (i
.op
[0].regs
->reg_num
!= 0)
4923 return bad_implicit_operand (1);
4925 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4927 /* Keep xmm0 for instructions with VEX prefix and 3
4933 /* We remove the first xmm0 and keep the number of
4934 operands unchanged, which in fact duplicates the
4936 for (j
= 1; j
< i
.operands
; j
++)
4938 i
.op
[j
- 1] = i
.op
[j
];
4939 i
.types
[j
- 1] = i
.types
[j
];
4940 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4944 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4946 gas_assert ((MAX_OPERANDS
- 1) > dupl
4947 && (i
.tm
.opcode_modifier
.vexsources
4950 /* Add the implicit xmm0 for instructions with VEX prefix
4952 for (j
= i
.operands
; j
> 0; j
--)
4954 i
.op
[j
] = i
.op
[j
- 1];
4955 i
.types
[j
] = i
.types
[j
- 1];
4956 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4959 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4960 i
.types
[0] = regxmm
;
4961 i
.tm
.operand_types
[0] = regxmm
;
4964 i
.reg_operands
+= 2;
4969 i
.op
[dupl
] = i
.op
[dest
];
4970 i
.types
[dupl
] = i
.types
[dest
];
4971 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4980 i
.op
[dupl
] = i
.op
[dest
];
4981 i
.types
[dupl
] = i
.types
[dest
];
4982 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4985 if (i
.tm
.opcode_modifier
.immext
)
4988 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4992 /* The first operand is implicit and must be xmm0/ymm0. */
4993 gas_assert (i
.reg_operands
4994 && (operand_type_equal (&i
.types
[0], ®xmm
)
4995 || operand_type_equal (&i
.types
[0], ®ymm
)));
4996 if (i
.op
[0].regs
->reg_num
!= 0)
4997 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4999 for (j
= 1; j
< i
.operands
; j
++)
5001 i
.op
[j
- 1] = i
.op
[j
];
5002 i
.types
[j
- 1] = i
.types
[j
];
5004 /* We need to adjust fields in i.tm since they are used by
5005 build_modrm_byte. */
5006 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5013 else if (i
.tm
.opcode_modifier
.regkludge
)
5015 /* The imul $imm, %reg instruction is converted into
5016 imul $imm, %reg, %reg, and the clr %reg instruction
5017 is converted into xor %reg, %reg. */
5019 unsigned int first_reg_op
;
5021 if (operand_type_check (i
.types
[0], reg
))
5025 /* Pretend we saw the extra register operand. */
5026 gas_assert (i
.reg_operands
== 1
5027 && i
.op
[first_reg_op
+ 1].regs
== 0);
5028 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5029 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5034 if (i
.tm
.opcode_modifier
.shortform
)
5036 if (i
.types
[0].bitfield
.sreg2
5037 || i
.types
[0].bitfield
.sreg3
)
5039 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5040 && i
.op
[0].regs
->reg_num
== 1)
5042 as_bad (_("you can't `pop %scs'"), register_prefix
);
5045 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5046 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5051 /* The register or float register operand is in operand
5055 if (i
.types
[0].bitfield
.floatreg
5056 || operand_type_check (i
.types
[0], reg
))
5060 /* Register goes in low 3 bits of opcode. */
5061 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5062 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5064 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5066 /* Warn about some common errors, but press on regardless.
5067 The first case can be generated by gcc (<= 2.8.1). */
5068 if (i
.operands
== 2)
5070 /* Reversed arguments on faddp, fsubp, etc. */
5071 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5072 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5073 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5077 /* Extraneous `l' suffix on fp insn. */
5078 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5079 register_prefix
, i
.op
[0].regs
->reg_name
);
5084 else if (i
.tm
.opcode_modifier
.modrm
)
5086 /* The opcode is completed (modulo i.tm.extension_opcode which
5087 must be put into the modrm byte). Now, we make the modrm and
5088 index base bytes based on all the info we've collected. */
5090 default_seg
= build_modrm_byte ();
5092 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5096 else if (i
.tm
.opcode_modifier
.isstring
)
5098 /* For the string instructions that allow a segment override
5099 on one of their operands, the default segment is ds. */
5103 if (i
.tm
.base_opcode
== 0x8d /* lea */
5106 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5108 /* If a segment was explicitly specified, and the specified segment
5109 is not the default, use an opcode prefix to select it. If we
5110 never figured out what the default segment is, then default_seg
5111 will be zero at this point, and the specified segment prefix will
5113 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5115 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5121 static const seg_entry
*
5122 build_modrm_byte (void)
5124 const seg_entry
*default_seg
= 0;
5125 unsigned int source
, dest
;
5128 /* The first operand of instructions with VEX prefix and 3 sources
5129 must be VEX_Imm4. */
5130 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5133 unsigned int nds
, reg_slot
;
5136 if (i
.tm
.opcode_modifier
.veximmext
5137 && i
.tm
.opcode_modifier
.immext
)
5139 dest
= i
.operands
- 2;
5140 gas_assert (dest
== 3);
5143 dest
= i
.operands
- 1;
5146 /* There are 2 kinds of instructions:
5147 1. 5 operands: 4 register operands or 3 register operands
5148 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5149 VexW0 or VexW1. The destination must be either XMM or YMM
5151 2. 4 operands: 4 register operands or 3 register operands
5152 plus 1 memory operand, VexXDS, and VexImmExt */
5153 gas_assert ((i
.reg_operands
== 4
5154 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5155 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5156 && (i
.tm
.opcode_modifier
.veximmext
5157 || (i
.imm_operands
== 1
5158 && i
.types
[0].bitfield
.vec_imm4
5159 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5160 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5161 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5162 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5164 if (i
.imm_operands
== 0)
5166 /* When there is no immediate operand, generate an 8bit
5167 immediate operand to encode the first operand. */
5168 exp
= &im_expressions
[i
.imm_operands
++];
5169 i
.op
[i
.operands
].imms
= exp
;
5170 i
.types
[i
.operands
] = imm8
;
5172 /* If VexW1 is set, the first operand is the source and
5173 the second operand is encoded in the immediate operand. */
5174 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5185 /* FMA swaps REG and NDS. */
5186 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5194 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5196 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5198 exp
->X_op
= O_constant
;
5200 = ((i
.op
[reg_slot
].regs
->reg_num
5201 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5206 unsigned int imm_slot
;
5208 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5210 /* If VexW0 is set, the third operand is the source and
5211 the second operand is encoded in the immediate
5218 /* VexW1 is set, the second operand is the source and
5219 the third operand is encoded in the immediate
5225 if (i
.tm
.opcode_modifier
.immext
)
5227 /* When ImmExt is set, the immdiate byte is the last
5229 imm_slot
= i
.operands
- 1;
5237 /* Turn on Imm8 so that output_imm will generate it. */
5238 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5241 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5243 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5245 i
.op
[imm_slot
].imms
->X_add_number
5246 |= ((i
.op
[reg_slot
].regs
->reg_num
5247 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5251 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5252 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5254 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5259 /* i.reg_operands MUST be the number of real register operands;
5260 implicit registers do not count. If there are 3 register
5261 operands, it must be a instruction with VexNDS. For a
5262 instruction with VexNDD, the destination register is encoded
5263 in VEX prefix. If there are 4 register operands, it must be
5264 a instruction with VEX prefix and 3 sources. */
5265 if (i
.mem_operands
== 0
5266 && ((i
.reg_operands
== 2
5267 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5268 || (i
.reg_operands
== 3
5269 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5270 || (i
.reg_operands
== 4 && vex_3_sources
)))
5278 /* When there are 3 operands, one of them may be immediate,
5279 which may be the first or the last operand. Otherwise,
5280 the first operand must be shift count register (cl) or it
5281 is an instruction with VexNDS. */
5282 gas_assert (i
.imm_operands
== 1
5283 || (i
.imm_operands
== 0
5284 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5285 || i
.types
[0].bitfield
.shiftcount
)));
5286 if (operand_type_check (i
.types
[0], imm
)
5287 || i
.types
[0].bitfield
.shiftcount
)
5293 /* When there are 4 operands, the first two must be 8bit
5294 immediate operands. The source operand will be the 3rd
5297 For instructions with VexNDS, if the first operand
5298 an imm8, the source operand is the 2nd one. If the last
5299 operand is imm8, the source operand is the first one. */
5300 gas_assert ((i
.imm_operands
== 2
5301 && i
.types
[0].bitfield
.imm8
5302 && i
.types
[1].bitfield
.imm8
)
5303 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5304 && i
.imm_operands
== 1
5305 && (i
.types
[0].bitfield
.imm8
5306 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5307 if (i
.imm_operands
== 2)
5311 if (i
.types
[0].bitfield
.imm8
)
5327 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5329 /* For instructions with VexNDS, the register-only
5330 source operand must be 32/64bit integer, XMM or
5331 YMM register. It is encoded in VEX prefix. We
5332 need to clear RegMem bit before calling
5333 operand_type_equal. */
5335 i386_operand_type op
;
5338 /* Check register-only source operand when two source
5339 operands are swapped. */
5340 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5341 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5349 op
= i
.tm
.operand_types
[vvvv
];
5350 op
.bitfield
.regmem
= 0;
5351 if ((dest
+ 1) >= i
.operands
5352 || (op
.bitfield
.reg32
!= 1
5353 && !op
.bitfield
.reg64
!= 1
5354 && !operand_type_equal (&op
, ®xmm
)
5355 && !operand_type_equal (&op
, ®ymm
)))
5357 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5363 /* One of the register operands will be encoded in the i.tm.reg
5364 field, the other in the combined i.tm.mode and i.tm.regmem
5365 fields. If no form of this instruction supports a memory
5366 destination operand, then we assume the source operand may
5367 sometimes be a memory operand and so we need to store the
5368 destination in the i.rm.reg field. */
5369 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5370 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5372 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5373 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5374 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5376 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5381 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5382 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5383 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5385 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5388 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5390 if (!i
.types
[0].bitfield
.control
5391 && !i
.types
[1].bitfield
.control
)
5393 i
.rex
&= ~(REX_R
| REX_B
);
5394 add_prefix (LOCK_PREFIX_OPCODE
);
5398 { /* If it's not 2 reg operands... */
5403 unsigned int fake_zero_displacement
= 0;
5406 for (op
= 0; op
< i
.operands
; op
++)
5407 if (operand_type_check (i
.types
[op
], anymem
))
5409 gas_assert (op
< i
.operands
);
5413 if (i
.base_reg
== 0)
5416 if (!i
.disp_operands
)
5417 fake_zero_displacement
= 1;
5418 if (i
.index_reg
== 0)
5420 /* Operand is just <disp> */
5421 if (flag_code
== CODE_64BIT
)
5423 /* 64bit mode overwrites the 32bit absolute
5424 addressing by RIP relative addressing and
5425 absolute addressing is encoded by one of the
5426 redundant SIB forms. */
5427 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5428 i
.sib
.base
= NO_BASE_REGISTER
;
5429 i
.sib
.index
= NO_INDEX_REGISTER
;
5430 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5431 ? disp32s
: disp32
);
5433 else if ((flag_code
== CODE_16BIT
)
5434 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5436 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5437 i
.types
[op
] = disp16
;
5441 i
.rm
.regmem
= NO_BASE_REGISTER
;
5442 i
.types
[op
] = disp32
;
5445 else /* !i.base_reg && i.index_reg */
5447 if (i
.index_reg
->reg_num
== RegEiz
5448 || i
.index_reg
->reg_num
== RegRiz
)
5449 i
.sib
.index
= NO_INDEX_REGISTER
;
5451 i
.sib
.index
= i
.index_reg
->reg_num
;
5452 i
.sib
.base
= NO_BASE_REGISTER
;
5453 i
.sib
.scale
= i
.log2_scale_factor
;
5454 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5455 i
.types
[op
].bitfield
.disp8
= 0;
5456 i
.types
[op
].bitfield
.disp16
= 0;
5457 i
.types
[op
].bitfield
.disp64
= 0;
5458 if (flag_code
!= CODE_64BIT
)
5460 /* Must be 32 bit */
5461 i
.types
[op
].bitfield
.disp32
= 1;
5462 i
.types
[op
].bitfield
.disp32s
= 0;
5466 i
.types
[op
].bitfield
.disp32
= 0;
5467 i
.types
[op
].bitfield
.disp32s
= 1;
5469 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5473 /* RIP addressing for 64bit mode. */
5474 else if (i
.base_reg
->reg_num
== RegRip
||
5475 i
.base_reg
->reg_num
== RegEip
)
5477 i
.rm
.regmem
= NO_BASE_REGISTER
;
5478 i
.types
[op
].bitfield
.disp8
= 0;
5479 i
.types
[op
].bitfield
.disp16
= 0;
5480 i
.types
[op
].bitfield
.disp32
= 0;
5481 i
.types
[op
].bitfield
.disp32s
= 1;
5482 i
.types
[op
].bitfield
.disp64
= 0;
5483 i
.flags
[op
] |= Operand_PCrel
;
5484 if (! i
.disp_operands
)
5485 fake_zero_displacement
= 1;
5487 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5489 switch (i
.base_reg
->reg_num
)
5492 if (i
.index_reg
== 0)
5494 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5495 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5499 if (i
.index_reg
== 0)
5502 if (operand_type_check (i
.types
[op
], disp
) == 0)
5504 /* fake (%bp) into 0(%bp) */
5505 i
.types
[op
].bitfield
.disp8
= 1;
5506 fake_zero_displacement
= 1;
5509 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5510 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5512 default: /* (%si) -> 4 or (%di) -> 5 */
5513 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5515 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5517 else /* i.base_reg and 32/64 bit mode */
5519 if (flag_code
== CODE_64BIT
5520 && operand_type_check (i
.types
[op
], disp
))
5522 i386_operand_type temp
;
5523 operand_type_set (&temp
, 0);
5524 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5526 if (i
.prefix
[ADDR_PREFIX
] == 0)
5527 i
.types
[op
].bitfield
.disp32s
= 1;
5529 i
.types
[op
].bitfield
.disp32
= 1;
5532 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5533 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5535 i
.sib
.base
= i
.base_reg
->reg_num
;
5536 /* x86-64 ignores REX prefix bit here to avoid decoder
5538 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5541 if (i
.disp_operands
== 0)
5543 fake_zero_displacement
= 1;
5544 i
.types
[op
].bitfield
.disp8
= 1;
5547 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5551 i
.sib
.scale
= i
.log2_scale_factor
;
5552 if (i
.index_reg
== 0)
5554 /* <disp>(%esp) becomes two byte modrm with no index
5555 register. We've already stored the code for esp
5556 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5557 Any base register besides %esp will not use the
5558 extra modrm byte. */
5559 i
.sib
.index
= NO_INDEX_REGISTER
;
5563 if (i
.index_reg
->reg_num
== RegEiz
5564 || i
.index_reg
->reg_num
== RegRiz
)
5565 i
.sib
.index
= NO_INDEX_REGISTER
;
5567 i
.sib
.index
= i
.index_reg
->reg_num
;
5568 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5569 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5574 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5575 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5578 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5581 if (fake_zero_displacement
)
5583 /* Fakes a zero displacement assuming that i.types[op]
5584 holds the correct displacement size. */
5587 gas_assert (i
.op
[op
].disps
== 0);
5588 exp
= &disp_expressions
[i
.disp_operands
++];
5589 i
.op
[op
].disps
= exp
;
5590 exp
->X_op
= O_constant
;
5591 exp
->X_add_number
= 0;
5592 exp
->X_add_symbol
= (symbolS
*) 0;
5593 exp
->X_op_symbol
= (symbolS
*) 0;
5601 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5603 if (operand_type_check (i
.types
[0], imm
))
5604 i
.vex
.register_specifier
= NULL
;
5607 /* VEX.vvvv encodes one of the sources when the first
5608 operand is not an immediate. */
5609 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5610 i
.vex
.register_specifier
= i
.op
[0].regs
;
5612 i
.vex
.register_specifier
= i
.op
[1].regs
;
5615 /* Destination is a XMM register encoded in the ModRM.reg
5617 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5618 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5621 /* ModRM.rm and VEX.B encodes the other source. */
5622 if (!i
.mem_operands
)
5626 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5627 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5629 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5631 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5635 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5637 i
.vex
.register_specifier
= i
.op
[2].regs
;
5638 if (!i
.mem_operands
)
5641 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5642 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5646 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5647 (if any) based on i.tm.extension_opcode. Again, we must be
5648 careful to make sure that segment/control/debug/test/MMX
5649 registers are coded into the i.rm.reg field. */
5650 else if (i
.reg_operands
)
5653 unsigned int vex_reg
= ~0;
5655 for (op
= 0; op
< i
.operands
; op
++)
5656 if (i
.types
[op
].bitfield
.reg8
5657 || i
.types
[op
].bitfield
.reg16
5658 || i
.types
[op
].bitfield
.reg32
5659 || i
.types
[op
].bitfield
.reg64
5660 || i
.types
[op
].bitfield
.regmmx
5661 || i
.types
[op
].bitfield
.regxmm
5662 || i
.types
[op
].bitfield
.regymm
5663 || i
.types
[op
].bitfield
.sreg2
5664 || i
.types
[op
].bitfield
.sreg3
5665 || i
.types
[op
].bitfield
.control
5666 || i
.types
[op
].bitfield
.debug
5667 || i
.types
[op
].bitfield
.test
)
5672 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5674 /* For instructions with VexNDS, the register-only
5675 source operand is encoded in VEX prefix. */
5676 gas_assert (mem
!= (unsigned int) ~0);
5681 gas_assert (op
< i
.operands
);
5685 /* Check register-only source operand when two source
5686 operands are swapped. */
5687 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5688 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5692 gas_assert (mem
== (vex_reg
+ 1)
5693 && op
< i
.operands
);
5698 gas_assert (vex_reg
< i
.operands
);
5702 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5704 /* For instructions with VexNDD, the register destination
5705 is encoded in VEX prefix. */
5706 if (i
.mem_operands
== 0)
5708 /* There is no memory operand. */
5709 gas_assert ((op
+ 2) == i
.operands
);
5714 /* There are only 2 operands. */
5715 gas_assert (op
< 2 && i
.operands
== 2);
5720 gas_assert (op
< i
.operands
);
5722 if (vex_reg
!= (unsigned int) ~0)
5724 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5726 if (type
->bitfield
.reg32
!= 1
5727 && type
->bitfield
.reg64
!= 1
5728 && !operand_type_equal (type
, ®xmm
)
5729 && !operand_type_equal (type
, ®ymm
))
5732 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5735 /* Don't set OP operand twice. */
5738 /* If there is an extension opcode to put here, the
5739 register number must be put into the regmem field. */
5740 if (i
.tm
.extension_opcode
!= None
)
5742 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5743 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5748 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5749 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5754 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5755 must set it to 3 to indicate this is a register operand
5756 in the regmem field. */
5757 if (!i
.mem_operands
)
5761 /* Fill in i.rm.reg field with extension opcode (if any). */
5762 if (i
.tm
.extension_opcode
!= None
)
5763 i
.rm
.reg
= i
.tm
.extension_opcode
;
5769 output_branch (void)
5775 relax_substateT subtype
;
5779 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
5780 size
= i
.disp32_encoding
? BIG
: SMALL
;
5783 if (i
.prefix
[DATA_PREFIX
] != 0)
5789 /* Pentium4 branch hints. */
5790 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5791 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5796 if (i
.prefix
[REX_PREFIX
] != 0)
5802 if (i
.prefixes
!= 0 && !intel_syntax
)
5803 as_warn (_("skipping prefixes on this instruction"));
5805 /* It's always a symbol; End frag & setup for relax.
5806 Make sure there is enough room in this frag for the largest
5807 instruction we may generate in md_convert_frag. This is 2
5808 bytes for the opcode and room for the prefix and largest
5810 frag_grow (prefix
+ 2 + 4);
5811 /* Prefix and 1 opcode byte go in fr_fix. */
5812 p
= frag_more (prefix
+ 1);
5813 if (i
.prefix
[DATA_PREFIX
] != 0)
5814 *p
++ = DATA_PREFIX_OPCODE
;
5815 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5816 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5817 *p
++ = i
.prefix
[SEG_PREFIX
];
5818 if (i
.prefix
[REX_PREFIX
] != 0)
5819 *p
++ = i
.prefix
[REX_PREFIX
];
5820 *p
= i
.tm
.base_opcode
;
5822 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5823 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
5824 else if (cpu_arch_flags
.bitfield
.cpui386
)
5825 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
5827 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
5830 sym
= i
.op
[0].disps
->X_add_symbol
;
5831 off
= i
.op
[0].disps
->X_add_number
;
5833 if (i
.op
[0].disps
->X_op
!= O_constant
5834 && i
.op
[0].disps
->X_op
!= O_symbol
)
5836 /* Handle complex expressions. */
5837 sym
= make_expr_symbol (i
.op
[0].disps
);
5841 /* 1 possible extra opcode + 4 byte displacement go in var part.
5842 Pass reloc in fr_var. */
5843 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5853 if (i
.tm
.opcode_modifier
.jumpbyte
)
5855 /* This is a loop or jecxz type instruction. */
5857 if (i
.prefix
[ADDR_PREFIX
] != 0)
5859 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5862 /* Pentium4 branch hints. */
5863 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5864 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5866 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5875 if (flag_code
== CODE_16BIT
)
5878 if (i
.prefix
[DATA_PREFIX
] != 0)
5880 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5890 if (i
.prefix
[REX_PREFIX
] != 0)
5892 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5896 if (i
.prefixes
!= 0 && !intel_syntax
)
5897 as_warn (_("skipping prefixes on this instruction"));
5899 p
= frag_more (1 + size
);
5900 *p
++ = i
.tm
.base_opcode
;
5902 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5903 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5905 /* All jumps handled here are signed, but don't use a signed limit
5906 check for 32 and 16 bit jumps as we want to allow wrap around at
5907 4G and 64k respectively. */
5909 fixP
->fx_signed
= 1;
5913 output_interseg_jump (void)
5921 if (flag_code
== CODE_16BIT
)
5925 if (i
.prefix
[DATA_PREFIX
] != 0)
5931 if (i
.prefix
[REX_PREFIX
] != 0)
5941 if (i
.prefixes
!= 0 && !intel_syntax
)
5942 as_warn (_("skipping prefixes on this instruction"));
5944 /* 1 opcode; 2 segment; offset */
5945 p
= frag_more (prefix
+ 1 + 2 + size
);
5947 if (i
.prefix
[DATA_PREFIX
] != 0)
5948 *p
++ = DATA_PREFIX_OPCODE
;
5950 if (i
.prefix
[REX_PREFIX
] != 0)
5951 *p
++ = i
.prefix
[REX_PREFIX
];
5953 *p
++ = i
.tm
.base_opcode
;
5954 if (i
.op
[1].imms
->X_op
== O_constant
)
5956 offsetT n
= i
.op
[1].imms
->X_add_number
;
5959 && !fits_in_unsigned_word (n
)
5960 && !fits_in_signed_word (n
))
5962 as_bad (_("16-bit jump out of range"));
5965 md_number_to_chars (p
, n
, size
);
5968 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5969 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5970 if (i
.op
[0].imms
->X_op
!= O_constant
)
5971 as_bad (_("can't handle non absolute segment in `%s'"),
5973 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5979 fragS
*insn_start_frag
;
5980 offsetT insn_start_off
;
5982 /* Tie dwarf2 debug info to the address at the start of the insn.
5983 We can't do this after the insn has been output as the current
5984 frag may have been closed off. eg. by frag_var. */
5985 dwarf2_emit_insn (0);
5987 insn_start_frag
= frag_now
;
5988 insn_start_off
= frag_now_fix ();
5991 if (i
.tm
.opcode_modifier
.jump
)
5993 else if (i
.tm
.opcode_modifier
.jumpbyte
5994 || i
.tm
.opcode_modifier
.jumpdword
)
5996 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5997 output_interseg_jump ();
6000 /* Output normal instructions here. */
6004 unsigned int prefix
;
6006 /* Since the VEX prefix contains the implicit prefix, we don't
6007 need the explicit prefix. */
6008 if (!i
.tm
.opcode_modifier
.vex
)
6010 switch (i
.tm
.opcode_length
)
6013 if (i
.tm
.base_opcode
& 0xff000000)
6015 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6020 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6022 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6023 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6026 if (prefix
!= REPE_PREFIX_OPCODE
6027 || (i
.prefix
[REP_PREFIX
]
6028 != REPE_PREFIX_OPCODE
))
6029 add_prefix (prefix
);
6032 add_prefix (prefix
);
6041 /* The prefix bytes. */
6042 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6044 FRAG_APPEND_1_CHAR (*q
);
6047 if (i
.tm
.opcode_modifier
.vex
)
6049 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6054 /* REX byte is encoded in VEX prefix. */
6058 FRAG_APPEND_1_CHAR (*q
);
6061 /* There should be no other prefixes for instructions
6066 /* Now the VEX prefix. */
6067 p
= frag_more (i
.vex
.length
);
6068 for (j
= 0; j
< i
.vex
.length
; j
++)
6069 p
[j
] = i
.vex
.bytes
[j
];
6072 /* Now the opcode; be careful about word order here! */
6073 if (i
.tm
.opcode_length
== 1)
6075 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6079 switch (i
.tm
.opcode_length
)
6083 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6093 /* Put out high byte first: can't use md_number_to_chars! */
6094 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6095 *p
= i
.tm
.base_opcode
& 0xff;
6098 /* Now the modrm byte and sib byte (if present). */
6099 if (i
.tm
.opcode_modifier
.modrm
)
6101 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6104 /* If i.rm.regmem == ESP (4)
6105 && i.rm.mode != (Register mode)
6107 ==> need second modrm byte. */
6108 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6110 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6111 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6113 | i
.sib
.scale
<< 6));
6116 if (i
.disp_operands
)
6117 output_disp (insn_start_frag
, insn_start_off
);
6120 output_imm (insn_start_frag
, insn_start_off
);
6126 pi ("" /*line*/, &i
);
6128 #endif /* DEBUG386 */
6131 /* Return the size of the displacement operand N. */
6134 disp_size (unsigned int n
)
6137 if (i
.types
[n
].bitfield
.disp64
)
6139 else if (i
.types
[n
].bitfield
.disp8
)
6141 else if (i
.types
[n
].bitfield
.disp16
)
6146 /* Return the size of the immediate operand N. */
6149 imm_size (unsigned int n
)
6152 if (i
.types
[n
].bitfield
.imm64
)
6154 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6156 else if (i
.types
[n
].bitfield
.imm16
)
6162 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6167 for (n
= 0; n
< i
.operands
; n
++)
6169 if (operand_type_check (i
.types
[n
], disp
))
6171 if (i
.op
[n
].disps
->X_op
== O_constant
)
6173 int size
= disp_size (n
);
6176 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6178 p
= frag_more (size
);
6179 md_number_to_chars (p
, val
, size
);
6183 enum bfd_reloc_code_real reloc_type
;
6184 int size
= disp_size (n
);
6185 int sign
= i
.types
[n
].bitfield
.disp32s
;
6186 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6188 /* We can't have 8 bit displacement here. */
6189 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6191 /* The PC relative address is computed relative
6192 to the instruction boundary, so in case immediate
6193 fields follows, we need to adjust the value. */
6194 if (pcrel
&& i
.imm_operands
)
6199 for (n1
= 0; n1
< i
.operands
; n1
++)
6200 if (operand_type_check (i
.types
[n1
], imm
))
6202 /* Only one immediate is allowed for PC
6203 relative address. */
6204 gas_assert (sz
== 0);
6206 i
.op
[n
].disps
->X_add_number
-= sz
;
6208 /* We should find the immediate. */
6209 gas_assert (sz
!= 0);
6212 p
= frag_more (size
);
6213 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6215 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6216 && (((reloc_type
== BFD_RELOC_32
6217 || reloc_type
== BFD_RELOC_X86_64_32S
6218 || (reloc_type
== BFD_RELOC_64
6220 && (i
.op
[n
].disps
->X_op
== O_symbol
6221 || (i
.op
[n
].disps
->X_op
== O_add
6222 && ((symbol_get_value_expression
6223 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6225 || reloc_type
== BFD_RELOC_32_PCREL
))
6229 if (insn_start_frag
== frag_now
)
6230 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6235 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6236 for (fr
= insn_start_frag
->fr_next
;
6237 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6239 add
+= p
- frag_now
->fr_literal
;
6244 reloc_type
= BFD_RELOC_386_GOTPC
;
6245 i
.op
[n
].imms
->X_add_number
+= add
;
6247 else if (reloc_type
== BFD_RELOC_64
)
6248 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6250 /* Don't do the adjustment for x86-64, as there
6251 the pcrel addressing is relative to the _next_
6252 insn, and that is taken care of in other code. */
6253 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6255 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6256 i
.op
[n
].disps
, pcrel
, reloc_type
);
6263 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6268 for (n
= 0; n
< i
.operands
; n
++)
6270 if (operand_type_check (i
.types
[n
], imm
))
6272 if (i
.op
[n
].imms
->X_op
== O_constant
)
6274 int size
= imm_size (n
);
6277 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6279 p
= frag_more (size
);
6280 md_number_to_chars (p
, val
, size
);
6284 /* Not absolute_section.
6285 Need a 32-bit fixup (don't support 8bit
6286 non-absolute imms). Try to support other
6288 enum bfd_reloc_code_real reloc_type
;
6289 int size
= imm_size (n
);
6292 if (i
.types
[n
].bitfield
.imm32s
6293 && (i
.suffix
== QWORD_MNEM_SUFFIX
6294 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6299 p
= frag_more (size
);
6300 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6302 /* This is tough to explain. We end up with this one if we
6303 * have operands that look like
6304 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6305 * obtain the absolute address of the GOT, and it is strongly
6306 * preferable from a performance point of view to avoid using
6307 * a runtime relocation for this. The actual sequence of
6308 * instructions often look something like:
6313 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6315 * The call and pop essentially return the absolute address
6316 * of the label .L66 and store it in %ebx. The linker itself
6317 * will ultimately change the first operand of the addl so
6318 * that %ebx points to the GOT, but to keep things simple, the
6319 * .o file must have this operand set so that it generates not
6320 * the absolute address of .L66, but the absolute address of
6321 * itself. This allows the linker itself simply treat a GOTPC
6322 * relocation as asking for a pcrel offset to the GOT to be
6323 * added in, and the addend of the relocation is stored in the
6324 * operand field for the instruction itself.
6326 * Our job here is to fix the operand so that it would add
6327 * the correct offset so that %ebx would point to itself. The
6328 * thing that is tricky is that .-.L66 will point to the
6329 * beginning of the instruction, so we need to further modify
6330 * the operand so that it will point to itself. There are
6331 * other cases where you have something like:
6333 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6335 * and here no correction would be required. Internally in
6336 * the assembler we treat operands of this form as not being
6337 * pcrel since the '.' is explicitly mentioned, and I wonder
6338 * whether it would simplify matters to do it this way. Who
6339 * knows. In earlier versions of the PIC patches, the
6340 * pcrel_adjust field was used to store the correction, but
6341 * since the expression is not pcrel, I felt it would be
6342 * confusing to do it this way. */
6344 if ((reloc_type
== BFD_RELOC_32
6345 || reloc_type
== BFD_RELOC_X86_64_32S
6346 || reloc_type
== BFD_RELOC_64
)
6348 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6349 && (i
.op
[n
].imms
->X_op
== O_symbol
6350 || (i
.op
[n
].imms
->X_op
== O_add
6351 && ((symbol_get_value_expression
6352 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6357 if (insn_start_frag
== frag_now
)
6358 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6363 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6364 for (fr
= insn_start_frag
->fr_next
;
6365 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6367 add
+= p
- frag_now
->fr_literal
;
6371 reloc_type
= BFD_RELOC_386_GOTPC
;
6373 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6375 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6376 i
.op
[n
].imms
->X_add_number
+= add
;
6378 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6379 i
.op
[n
].imms
, 0, reloc_type
);
6385 /* x86_cons_fix_new is called via the expression parsing code when a
6386 reloc is needed. We use this hook to get the correct .got reloc. */
6387 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6388 static int cons_sign
= -1;
6391 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6394 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6396 got_reloc
= NO_RELOC
;
6399 if (exp
->X_op
== O_secrel
)
6401 exp
->X_op
= O_symbol
;
6402 r
= BFD_RELOC_32_SECREL
;
6406 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6409 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6410 # define lex_got(reloc, adjust, types) NULL
6412 /* Parse operands of the form
6413 <symbol>@GOTOFF+<nnn>
6414 and similar .plt or .got references.
6416 If we find one, set up the correct relocation in RELOC and copy the
6417 input string, minus the `@GOTOFF' into a malloc'd buffer for
6418 parsing by the calling routine. Return this buffer, and if ADJUST
6419 is non-null set it to the length of the string we removed from the
6420 input line. Otherwise return NULL. */
6422 lex_got (enum bfd_reloc_code_real
*rel
,
6424 i386_operand_type
*types
)
6426 /* Some of the relocations depend on the size of what field is to
6427 be relocated. But in our callers i386_immediate and i386_displacement
6428 we don't yet know the operand size (this will be set by insn
6429 matching). Hence we record the word32 relocation here,
6430 and adjust the reloc according to the real size in reloc(). */
6431 static const struct {
6434 const enum bfd_reloc_code_real rel
[2];
6435 const i386_operand_type types64
;
6437 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6438 BFD_RELOC_X86_64_PLTOFF64
},
6439 OPERAND_TYPE_IMM64
},
6440 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6441 BFD_RELOC_X86_64_PLT32
},
6442 OPERAND_TYPE_IMM32_32S_DISP32
},
6443 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6444 BFD_RELOC_X86_64_GOTPLT64
},
6445 OPERAND_TYPE_IMM64_DISP64
},
6446 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6447 BFD_RELOC_X86_64_GOTOFF64
},
6448 OPERAND_TYPE_IMM64_DISP64
},
6449 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6450 BFD_RELOC_X86_64_GOTPCREL
},
6451 OPERAND_TYPE_IMM32_32S_DISP32
},
6452 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6453 BFD_RELOC_X86_64_TLSGD
},
6454 OPERAND_TYPE_IMM32_32S_DISP32
},
6455 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6456 _dummy_first_bfd_reloc_code_real
},
6457 OPERAND_TYPE_NONE
},
6458 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6459 BFD_RELOC_X86_64_TLSLD
},
6460 OPERAND_TYPE_IMM32_32S_DISP32
},
6461 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6462 BFD_RELOC_X86_64_GOTTPOFF
},
6463 OPERAND_TYPE_IMM32_32S_DISP32
},
6464 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6465 BFD_RELOC_X86_64_TPOFF32
},
6466 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6467 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6468 _dummy_first_bfd_reloc_code_real
},
6469 OPERAND_TYPE_NONE
},
6470 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6471 BFD_RELOC_X86_64_DTPOFF32
},
6472 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6473 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6474 _dummy_first_bfd_reloc_code_real
},
6475 OPERAND_TYPE_NONE
},
6476 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6477 _dummy_first_bfd_reloc_code_real
},
6478 OPERAND_TYPE_NONE
},
6479 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6480 BFD_RELOC_X86_64_GOT32
},
6481 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6482 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6483 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6484 OPERAND_TYPE_IMM32_32S_DISP32
},
6485 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6486 BFD_RELOC_X86_64_TLSDESC_CALL
},
6487 OPERAND_TYPE_IMM32_32S_DISP32
},
6495 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6496 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6499 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6501 int len
= gotrel
[j
].len
;
6502 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6504 if (gotrel
[j
].rel
[object_64bit
] != 0)
6507 char *tmpbuf
, *past_reloc
;
6509 *rel
= gotrel
[j
].rel
[object_64bit
];
6515 if (flag_code
!= CODE_64BIT
)
6517 types
->bitfield
.imm32
= 1;
6518 types
->bitfield
.disp32
= 1;
6521 *types
= gotrel
[j
].types64
;
6524 if (GOT_symbol
== NULL
)
6525 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6527 /* The length of the first part of our input line. */
6528 first
= cp
- input_line_pointer
;
6530 /* The second part goes from after the reloc token until
6531 (and including) an end_of_line char or comma. */
6532 past_reloc
= cp
+ 1 + len
;
6534 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6536 second
= cp
+ 1 - past_reloc
;
6538 /* Allocate and copy string. The trailing NUL shouldn't
6539 be necessary, but be safe. */
6540 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6541 memcpy (tmpbuf
, input_line_pointer
, first
);
6542 if (second
!= 0 && *past_reloc
!= ' ')
6543 /* Replace the relocation token with ' ', so that
6544 errors like foo@GOTOFF1 will be detected. */
6545 tmpbuf
[first
++] = ' ';
6546 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6547 tmpbuf
[first
+ second
] = '\0';
6551 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6552 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6557 /* Might be a symbol version string. Don't as_bad here. */
6562 x86_cons (expressionS
*exp
, int size
)
6564 intel_syntax
= -intel_syntax
;
6567 if (size
== 4 || (object_64bit
&& size
== 8))
6569 /* Handle @GOTOFF and the like in an expression. */
6571 char *gotfree_input_line
;
6574 save
= input_line_pointer
;
6575 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6576 if (gotfree_input_line
)
6577 input_line_pointer
= gotfree_input_line
;
6581 if (gotfree_input_line
)
6583 /* expression () has merrily parsed up to the end of line,
6584 or a comma - in the wrong buffer. Transfer how far
6585 input_line_pointer has moved to the right buffer. */
6586 input_line_pointer
= (save
6587 + (input_line_pointer
- gotfree_input_line
)
6589 free (gotfree_input_line
);
6590 if (exp
->X_op
== O_constant
6591 || exp
->X_op
== O_absent
6592 || exp
->X_op
== O_illegal
6593 || exp
->X_op
== O_register
6594 || exp
->X_op
== O_big
)
6596 char c
= *input_line_pointer
;
6597 *input_line_pointer
= 0;
6598 as_bad (_("missing or invalid expression `%s'"), save
);
6599 *input_line_pointer
= c
;
6606 intel_syntax
= -intel_syntax
;
6609 i386_intel_simplify (exp
);
6614 signed_cons (int size
)
6616 if (flag_code
== CODE_64BIT
)
6624 pe_directive_secrel (dummy
)
6625 int dummy ATTRIBUTE_UNUSED
;
6632 if (exp
.X_op
== O_symbol
)
6633 exp
.X_op
= O_secrel
;
6635 emit_expr (&exp
, 4);
6637 while (*input_line_pointer
++ == ',');
6639 input_line_pointer
--;
6640 demand_empty_rest_of_line ();
6645 i386_immediate (char *imm_start
)
6647 char *save_input_line_pointer
;
6648 char *gotfree_input_line
;
6651 i386_operand_type types
;
6653 operand_type_set (&types
, ~0);
6655 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6657 as_bad (_("at most %d immediate operands are allowed"),
6658 MAX_IMMEDIATE_OPERANDS
);
6662 exp
= &im_expressions
[i
.imm_operands
++];
6663 i
.op
[this_operand
].imms
= exp
;
6665 if (is_space_char (*imm_start
))
6668 save_input_line_pointer
= input_line_pointer
;
6669 input_line_pointer
= imm_start
;
6671 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6672 if (gotfree_input_line
)
6673 input_line_pointer
= gotfree_input_line
;
6675 exp_seg
= expression (exp
);
6678 if (*input_line_pointer
)
6679 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6681 input_line_pointer
= save_input_line_pointer
;
6682 if (gotfree_input_line
)
6684 free (gotfree_input_line
);
6686 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6687 exp
->X_op
= O_illegal
;
6690 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6694 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6695 i386_operand_type types
, const char *imm_start
)
6697 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6700 as_bad (_("missing or invalid immediate expression `%s'"),
6704 else if (exp
->X_op
== O_constant
)
6706 /* Size it properly later. */
6707 i
.types
[this_operand
].bitfield
.imm64
= 1;
6708 /* If not 64bit, sign extend val. */
6709 if (flag_code
!= CODE_64BIT
6710 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6712 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6714 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6715 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6716 && exp_seg
!= absolute_section
6717 && exp_seg
!= text_section
6718 && exp_seg
!= data_section
6719 && exp_seg
!= bss_section
6720 && exp_seg
!= undefined_section
6721 && !bfd_is_com_section (exp_seg
))
6723 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6727 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6730 as_bad (_("illegal immediate register operand %s"), imm_start
);
6735 /* This is an address. The size of the address will be
6736 determined later, depending on destination register,
6737 suffix, or the default for the section. */
6738 i
.types
[this_operand
].bitfield
.imm8
= 1;
6739 i
.types
[this_operand
].bitfield
.imm16
= 1;
6740 i
.types
[this_operand
].bitfield
.imm32
= 1;
6741 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6742 i
.types
[this_operand
].bitfield
.imm64
= 1;
6743 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6751 i386_scale (char *scale
)
6754 char *save
= input_line_pointer
;
6756 input_line_pointer
= scale
;
6757 val
= get_absolute_expression ();
6762 i
.log2_scale_factor
= 0;
6765 i
.log2_scale_factor
= 1;
6768 i
.log2_scale_factor
= 2;
6771 i
.log2_scale_factor
= 3;
6775 char sep
= *input_line_pointer
;
6777 *input_line_pointer
= '\0';
6778 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6780 *input_line_pointer
= sep
;
6781 input_line_pointer
= save
;
6785 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6787 as_warn (_("scale factor of %d without an index register"),
6788 1 << i
.log2_scale_factor
);
6789 i
.log2_scale_factor
= 0;
6791 scale
= input_line_pointer
;
6792 input_line_pointer
= save
;
6797 i386_displacement (char *disp_start
, char *disp_end
)
6801 char *save_input_line_pointer
;
6802 char *gotfree_input_line
;
6804 i386_operand_type bigdisp
, types
= anydisp
;
6807 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6809 as_bad (_("at most %d displacement operands are allowed"),
6810 MAX_MEMORY_OPERANDS
);
6814 operand_type_set (&bigdisp
, 0);
6815 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6816 || (!current_templates
->start
->opcode_modifier
.jump
6817 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6819 bigdisp
.bitfield
.disp32
= 1;
6820 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6821 if (flag_code
== CODE_64BIT
)
6825 bigdisp
.bitfield
.disp32s
= 1;
6826 bigdisp
.bitfield
.disp64
= 1;
6829 else if ((flag_code
== CODE_16BIT
) ^ override
)
6831 bigdisp
.bitfield
.disp32
= 0;
6832 bigdisp
.bitfield
.disp16
= 1;
6837 /* For PC-relative branches, the width of the displacement
6838 is dependent upon data size, not address size. */
6839 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6840 if (flag_code
== CODE_64BIT
)
6842 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6843 bigdisp
.bitfield
.disp16
= 1;
6846 bigdisp
.bitfield
.disp32
= 1;
6847 bigdisp
.bitfield
.disp32s
= 1;
6853 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6855 : LONG_MNEM_SUFFIX
));
6856 bigdisp
.bitfield
.disp32
= 1;
6857 if ((flag_code
== CODE_16BIT
) ^ override
)
6859 bigdisp
.bitfield
.disp32
= 0;
6860 bigdisp
.bitfield
.disp16
= 1;
6864 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6867 exp
= &disp_expressions
[i
.disp_operands
];
6868 i
.op
[this_operand
].disps
= exp
;
6870 save_input_line_pointer
= input_line_pointer
;
6871 input_line_pointer
= disp_start
;
6872 END_STRING_AND_SAVE (disp_end
);
6874 #ifndef GCC_ASM_O_HACK
6875 #define GCC_ASM_O_HACK 0
6878 END_STRING_AND_SAVE (disp_end
+ 1);
6879 if (i
.types
[this_operand
].bitfield
.baseIndex
6880 && displacement_string_end
[-1] == '+')
6882 /* This hack is to avoid a warning when using the "o"
6883 constraint within gcc asm statements.
6886 #define _set_tssldt_desc(n,addr,limit,type) \
6887 __asm__ __volatile__ ( \
6889 "movw %w1,2+%0\n\t" \
6891 "movb %b1,4+%0\n\t" \
6892 "movb %4,5+%0\n\t" \
6893 "movb $0,6+%0\n\t" \
6894 "movb %h1,7+%0\n\t" \
6896 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6898 This works great except that the output assembler ends
6899 up looking a bit weird if it turns out that there is
6900 no offset. You end up producing code that looks like:
6913 So here we provide the missing zero. */
6915 *displacement_string_end
= '0';
6918 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6919 if (gotfree_input_line
)
6920 input_line_pointer
= gotfree_input_line
;
6922 exp_seg
= expression (exp
);
6925 if (*input_line_pointer
)
6926 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6928 RESTORE_END_STRING (disp_end
+ 1);
6930 input_line_pointer
= save_input_line_pointer
;
6931 if (gotfree_input_line
)
6933 free (gotfree_input_line
);
6935 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6936 exp
->X_op
= O_illegal
;
6939 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6941 RESTORE_END_STRING (disp_end
);
6947 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6948 i386_operand_type types
, const char *disp_start
)
6950 i386_operand_type bigdisp
;
6953 /* We do this to make sure that the section symbol is in
6954 the symbol table. We will ultimately change the relocation
6955 to be relative to the beginning of the section. */
6956 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6957 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6958 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6960 if (exp
->X_op
!= O_symbol
)
6963 if (S_IS_LOCAL (exp
->X_add_symbol
)
6964 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
6965 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
6966 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6967 exp
->X_op
= O_subtract
;
6968 exp
->X_op_symbol
= GOT_symbol
;
6969 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6970 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6971 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6972 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6974 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6977 else if (exp
->X_op
== O_absent
6978 || exp
->X_op
== O_illegal
6979 || exp
->X_op
== O_big
)
6982 as_bad (_("missing or invalid displacement expression `%s'"),
6987 else if (flag_code
== CODE_64BIT
6988 && !i
.prefix
[ADDR_PREFIX
]
6989 && exp
->X_op
== O_constant
)
6991 /* Since displacement is signed extended to 64bit, don't allow
6992 disp32 and turn off disp32s if they are out of range. */
6993 i
.types
[this_operand
].bitfield
.disp32
= 0;
6994 if (!fits_in_signed_long (exp
->X_add_number
))
6996 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6997 if (i
.types
[this_operand
].bitfield
.baseindex
)
6999 as_bad (_("0x%lx out range of signed 32bit displacement"),
7000 (long) exp
->X_add_number
);
7006 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7007 else if (exp
->X_op
!= O_constant
7008 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7009 && exp_seg
!= absolute_section
7010 && exp_seg
!= text_section
7011 && exp_seg
!= data_section
7012 && exp_seg
!= bss_section
7013 && exp_seg
!= undefined_section
7014 && !bfd_is_com_section (exp_seg
))
7016 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7021 /* Check if this is a displacement only operand. */
7022 bigdisp
= i
.types
[this_operand
];
7023 bigdisp
.bitfield
.disp8
= 0;
7024 bigdisp
.bitfield
.disp16
= 0;
7025 bigdisp
.bitfield
.disp32
= 0;
7026 bigdisp
.bitfield
.disp32s
= 0;
7027 bigdisp
.bitfield
.disp64
= 0;
7028 if (operand_type_all_zero (&bigdisp
))
7029 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7035 /* Make sure the memory operand we've been dealt is valid.
7036 Return 1 on success, 0 on a failure. */
7039 i386_index_check (const char *operand_string
)
7042 const char *kind
= "base/index";
7043 #if INFER_ADDR_PREFIX
7049 if (current_templates
->start
->opcode_modifier
.isstring
7050 && !current_templates
->start
->opcode_modifier
.immext
7051 && (current_templates
->end
[-1].opcode_modifier
.isstring
7054 /* Memory operands of string insns are special in that they only allow
7055 a single register (rDI, rSI, or rBX) as their memory address. */
7056 unsigned int expected
;
7058 kind
= "string address";
7060 if (current_templates
->start
->opcode_modifier
.w
)
7062 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7064 if (!type
.bitfield
.baseindex
7065 || ((!i
.mem_operands
!= !intel_syntax
)
7066 && current_templates
->end
[-1].operand_types
[1]
7067 .bitfield
.baseindex
))
7068 type
= current_templates
->end
[-1].operand_types
[1];
7069 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7072 expected
= 3 /* rBX */;
7074 if (!i
.base_reg
|| i
.index_reg
7075 || operand_type_check (i
.types
[this_operand
], disp
))
7077 else if (!(flag_code
== CODE_64BIT
7078 ? i
.prefix
[ADDR_PREFIX
]
7079 ? i
.base_reg
->reg_type
.bitfield
.reg32
7080 : i
.base_reg
->reg_type
.bitfield
.reg64
7081 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7082 ? i
.base_reg
->reg_type
.bitfield
.reg32
7083 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7085 else if (i
.base_reg
->reg_num
!= expected
)
7092 for (j
= 0; j
< i386_regtab_size
; ++j
)
7093 if ((flag_code
== CODE_64BIT
7094 ? i
.prefix
[ADDR_PREFIX
]
7095 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7096 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7097 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7098 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7099 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7100 && i386_regtab
[j
].reg_num
== expected
)
7102 gas_assert (j
< i386_regtab_size
);
7103 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7105 intel_syntax
? '[' : '(',
7107 i386_regtab
[j
].reg_name
,
7108 intel_syntax
? ']' : ')');
7112 else if (flag_code
== CODE_64BIT
)
7115 && ((i
.prefix
[ADDR_PREFIX
] == 0
7116 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7117 || (i
.prefix
[ADDR_PREFIX
]
7118 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7120 || i
.base_reg
->reg_num
!=
7121 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7123 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7124 || (i
.prefix
[ADDR_PREFIX
] == 0
7125 && i
.index_reg
->reg_num
!= RegRiz
7126 && !i
.index_reg
->reg_type
.bitfield
.reg64
7128 || (i
.prefix
[ADDR_PREFIX
]
7129 && i
.index_reg
->reg_num
!= RegEiz
7130 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7135 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7139 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7140 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7142 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7143 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7145 && i
.base_reg
->reg_num
< 6
7146 && i
.index_reg
->reg_num
>= 6
7147 && i
.log2_scale_factor
== 0))))
7154 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7156 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7157 && i
.index_reg
->reg_num
!= RegEiz
)
7158 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7164 #if INFER_ADDR_PREFIX
7165 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7167 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7169 /* Change the size of any displacement too. At most one of
7170 Disp16 or Disp32 is set.
7171 FIXME. There doesn't seem to be any real need for separate
7172 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7173 Removing them would probably clean up the code quite a lot. */
7174 if (flag_code
!= CODE_64BIT
7175 && (i
.types
[this_operand
].bitfield
.disp16
7176 || i
.types
[this_operand
].bitfield
.disp32
))
7177 i
.types
[this_operand
]
7178 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7183 as_bad (_("`%s' is not a valid %s expression"),
7188 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7190 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7191 ? flag_code
== CODE_32BIT
7200 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7204 i386_att_operand (char *operand_string
)
7208 char *op_string
= operand_string
;
7210 if (is_space_char (*op_string
))
7213 /* We check for an absolute prefix (differentiating,
7214 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7215 if (*op_string
== ABSOLUTE_PREFIX
)
7218 if (is_space_char (*op_string
))
7220 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7223 /* Check if operand is a register. */
7224 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7226 i386_operand_type temp
;
7228 /* Check for a segment override by searching for ':' after a
7229 segment register. */
7231 if (is_space_char (*op_string
))
7233 if (*op_string
== ':'
7234 && (r
->reg_type
.bitfield
.sreg2
7235 || r
->reg_type
.bitfield
.sreg3
))
7240 i
.seg
[i
.mem_operands
] = &es
;
7243 i
.seg
[i
.mem_operands
] = &cs
;
7246 i
.seg
[i
.mem_operands
] = &ss
;
7249 i
.seg
[i
.mem_operands
] = &ds
;
7252 i
.seg
[i
.mem_operands
] = &fs
;
7255 i
.seg
[i
.mem_operands
] = &gs
;
7259 /* Skip the ':' and whitespace. */
7261 if (is_space_char (*op_string
))
7264 if (!is_digit_char (*op_string
)
7265 && !is_identifier_char (*op_string
)
7266 && *op_string
!= '('
7267 && *op_string
!= ABSOLUTE_PREFIX
)
7269 as_bad (_("bad memory operand `%s'"), op_string
);
7272 /* Handle case of %es:*foo. */
7273 if (*op_string
== ABSOLUTE_PREFIX
)
7276 if (is_space_char (*op_string
))
7278 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7280 goto do_memory_reference
;
7284 as_bad (_("junk `%s' after register"), op_string
);
7288 temp
.bitfield
.baseindex
= 0;
7289 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7291 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7292 i
.op
[this_operand
].regs
= r
;
7295 else if (*op_string
== REGISTER_PREFIX
)
7297 as_bad (_("bad register name `%s'"), op_string
);
7300 else if (*op_string
== IMMEDIATE_PREFIX
)
7303 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7305 as_bad (_("immediate operand illegal with absolute jump"));
7308 if (!i386_immediate (op_string
))
7311 else if (is_digit_char (*op_string
)
7312 || is_identifier_char (*op_string
)
7313 || *op_string
== '(')
7315 /* This is a memory reference of some sort. */
7318 /* Start and end of displacement string expression (if found). */
7319 char *displacement_string_start
;
7320 char *displacement_string_end
;
7322 do_memory_reference
:
7323 if ((i
.mem_operands
== 1
7324 && !current_templates
->start
->opcode_modifier
.isstring
)
7325 || i
.mem_operands
== 2)
7327 as_bad (_("too many memory references for `%s'"),
7328 current_templates
->start
->name
);
7332 /* Check for base index form. We detect the base index form by
7333 looking for an ')' at the end of the operand, searching
7334 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7336 base_string
= op_string
+ strlen (op_string
);
7339 if (is_space_char (*base_string
))
7342 /* If we only have a displacement, set-up for it to be parsed later. */
7343 displacement_string_start
= op_string
;
7344 displacement_string_end
= base_string
+ 1;
7346 if (*base_string
== ')')
7349 unsigned int parens_balanced
= 1;
7350 /* We've already checked that the number of left & right ()'s are
7351 equal, so this loop will not be infinite. */
7355 if (*base_string
== ')')
7357 if (*base_string
== '(')
7360 while (parens_balanced
);
7362 temp_string
= base_string
;
7364 /* Skip past '(' and whitespace. */
7366 if (is_space_char (*base_string
))
7369 if (*base_string
== ','
7370 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7373 displacement_string_end
= temp_string
;
7375 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7379 base_string
= end_op
;
7380 if (is_space_char (*base_string
))
7384 /* There may be an index reg or scale factor here. */
7385 if (*base_string
== ',')
7388 if (is_space_char (*base_string
))
7391 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7394 base_string
= end_op
;
7395 if (is_space_char (*base_string
))
7397 if (*base_string
== ',')
7400 if (is_space_char (*base_string
))
7403 else if (*base_string
!= ')')
7405 as_bad (_("expecting `,' or `)' "
7406 "after index register in `%s'"),
7411 else if (*base_string
== REGISTER_PREFIX
)
7413 as_bad (_("bad register name `%s'"), base_string
);
7417 /* Check for scale factor. */
7418 if (*base_string
!= ')')
7420 char *end_scale
= i386_scale (base_string
);
7425 base_string
= end_scale
;
7426 if (is_space_char (*base_string
))
7428 if (*base_string
!= ')')
7430 as_bad (_("expecting `)' "
7431 "after scale factor in `%s'"),
7436 else if (!i
.index_reg
)
7438 as_bad (_("expecting index register or scale factor "
7439 "after `,'; got '%c'"),
7444 else if (*base_string
!= ')')
7446 as_bad (_("expecting `,' or `)' "
7447 "after base register in `%s'"),
7452 else if (*base_string
== REGISTER_PREFIX
)
7454 as_bad (_("bad register name `%s'"), base_string
);
7459 /* If there's an expression beginning the operand, parse it,
7460 assuming displacement_string_start and
7461 displacement_string_end are meaningful. */
7462 if (displacement_string_start
!= displacement_string_end
)
7464 if (!i386_displacement (displacement_string_start
,
7465 displacement_string_end
))
7469 /* Special case for (%dx) while doing input/output op. */
7471 && operand_type_equal (&i
.base_reg
->reg_type
,
7472 ®16_inoutportreg
)
7474 && i
.log2_scale_factor
== 0
7475 && i
.seg
[i
.mem_operands
] == 0
7476 && !operand_type_check (i
.types
[this_operand
], disp
))
7478 i
.types
[this_operand
] = inoutportreg
;
7482 if (i386_index_check (operand_string
) == 0)
7484 i
.types
[this_operand
].bitfield
.mem
= 1;
7489 /* It's not a memory operand; argh! */
7490 as_bad (_("invalid char %s beginning operand %d `%s'"),
7491 output_invalid (*op_string
),
7496 return 1; /* Normal return. */
7499 /* md_estimate_size_before_relax()
7501 Called just before relax() for rs_machine_dependent frags. The x86
7502 assembler uses these frags to handle variable size jump
7505 Any symbol that is now undefined will not become defined.
7506 Return the correct fr_subtype in the frag.
7507 Return the initial "guess for variable size of frag" to caller.
7508 The guess is actually the growth beyond the fixed part. Whatever
7509 we do to grow the fixed or variable part contributes to our
7513 md_estimate_size_before_relax (fragP
, segment
)
7517 /* We've already got fragP->fr_subtype right; all we have to do is
7518 check for un-relaxable symbols. On an ELF system, we can't relax
7519 an externally visible symbol, because it may be overridden by a
7521 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7522 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7524 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7525 || S_IS_WEAK (fragP
->fr_symbol
)
7526 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7527 & BSF_GNU_INDIRECT_FUNCTION
))))
7529 #if defined (OBJ_COFF) && defined (TE_PE)
7530 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7531 && S_IS_WEAK (fragP
->fr_symbol
))
7535 /* Symbol is undefined in this segment, or we need to keep a
7536 reloc so that weak symbols can be overridden. */
7537 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7538 enum bfd_reloc_code_real reloc_type
;
7539 unsigned char *opcode
;
7542 if (fragP
->fr_var
!= NO_RELOC
)
7543 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7545 reloc_type
= BFD_RELOC_16_PCREL
;
7547 reloc_type
= BFD_RELOC_32_PCREL
;
7549 old_fr_fix
= fragP
->fr_fix
;
7550 opcode
= (unsigned char *) fragP
->fr_opcode
;
7552 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7555 /* Make jmp (0xeb) a (d)word displacement jump. */
7557 fragP
->fr_fix
+= size
;
7558 fix_new (fragP
, old_fr_fix
, size
,
7560 fragP
->fr_offset
, 1,
7566 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7568 /* Negate the condition, and branch past an
7569 unconditional jump. */
7572 /* Insert an unconditional jump. */
7574 /* We added two extra opcode bytes, and have a two byte
7576 fragP
->fr_fix
+= 2 + 2;
7577 fix_new (fragP
, old_fr_fix
+ 2, 2,
7579 fragP
->fr_offset
, 1,
7586 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7591 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7593 fragP
->fr_offset
, 1,
7595 fixP
->fx_signed
= 1;
7599 /* This changes the byte-displacement jump 0x7N
7600 to the (d)word-displacement jump 0x0f,0x8N. */
7601 opcode
[1] = opcode
[0] + 0x10;
7602 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7603 /* We've added an opcode byte. */
7604 fragP
->fr_fix
+= 1 + size
;
7605 fix_new (fragP
, old_fr_fix
+ 1, size
,
7607 fragP
->fr_offset
, 1,
7612 BAD_CASE (fragP
->fr_subtype
);
7616 return fragP
->fr_fix
- old_fr_fix
;
7619 /* Guess size depending on current relax state. Initially the relax
7620 state will correspond to a short jump and we return 1, because
7621 the variable part of the frag (the branch offset) is one byte
7622 long. However, we can relax a section more than once and in that
7623 case we must either set fr_subtype back to the unrelaxed state,
7624 or return the value for the appropriate branch. */
7625 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7628 /* Called after relax() is finished.
7630 In: Address of frag.
7631 fr_type == rs_machine_dependent.
7632 fr_subtype is what the address relaxed to.
7634 Out: Any fixSs and constants are set up.
7635 Caller will turn frag into a ".space 0". */
7638 md_convert_frag (abfd
, sec
, fragP
)
7639 bfd
*abfd ATTRIBUTE_UNUSED
;
7640 segT sec ATTRIBUTE_UNUSED
;
7643 unsigned char *opcode
;
7644 unsigned char *where_to_put_displacement
= NULL
;
7645 offsetT target_address
;
7646 offsetT opcode_address
;
7647 unsigned int extension
= 0;
7648 offsetT displacement_from_opcode_start
;
7650 opcode
= (unsigned char *) fragP
->fr_opcode
;
7652 /* Address we want to reach in file space. */
7653 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7655 /* Address opcode resides at in file space. */
7656 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7658 /* Displacement from opcode start to fill into instruction. */
7659 displacement_from_opcode_start
= target_address
- opcode_address
;
7661 if ((fragP
->fr_subtype
& BIG
) == 0)
7663 /* Don't have to change opcode. */
7664 extension
= 1; /* 1 opcode + 1 displacement */
7665 where_to_put_displacement
= &opcode
[1];
7669 if (no_cond_jump_promotion
7670 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7671 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7672 _("long jump required"));
7674 switch (fragP
->fr_subtype
)
7676 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7677 extension
= 4; /* 1 opcode + 4 displacement */
7679 where_to_put_displacement
= &opcode
[1];
7682 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7683 extension
= 2; /* 1 opcode + 2 displacement */
7685 where_to_put_displacement
= &opcode
[1];
7688 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7689 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7690 extension
= 5; /* 2 opcode + 4 displacement */
7691 opcode
[1] = opcode
[0] + 0x10;
7692 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7693 where_to_put_displacement
= &opcode
[2];
7696 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7697 extension
= 3; /* 2 opcode + 2 displacement */
7698 opcode
[1] = opcode
[0] + 0x10;
7699 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7700 where_to_put_displacement
= &opcode
[2];
7703 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7708 where_to_put_displacement
= &opcode
[3];
7712 BAD_CASE (fragP
->fr_subtype
);
7717 /* If size if less then four we are sure that the operand fits,
7718 but if it's 4, then it could be that the displacement is larger
7720 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7722 && ((addressT
) (displacement_from_opcode_start
- extension
7723 + ((addressT
) 1 << 31))
7724 > (((addressT
) 2 << 31) - 1)))
7726 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7727 _("jump target out of range"));
7728 /* Make us emit 0. */
7729 displacement_from_opcode_start
= extension
;
7731 /* Now put displacement after opcode. */
7732 md_number_to_chars ((char *) where_to_put_displacement
,
7733 (valueT
) (displacement_from_opcode_start
- extension
),
7734 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7735 fragP
->fr_fix
+= extension
;
7738 /* Apply a fixup (fixS) to segment data, once it has been determined
7739 by our caller that we have all the info we need to fix it up.
7741 On the 386, immediates, displacements, and data pointers are all in
7742 the same (little-endian) format, so we don't need to care about which
7746 md_apply_fix (fixP
, valP
, seg
)
7747 /* The fix we're to put in. */
7749 /* Pointer to the value of the bits. */
7751 /* Segment fix is from. */
7752 segT seg ATTRIBUTE_UNUSED
;
7754 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7755 valueT value
= *valP
;
7757 #if !defined (TE_Mach)
7760 switch (fixP
->fx_r_type
)
7766 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7769 case BFD_RELOC_X86_64_32S
:
7770 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7773 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7776 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7781 if (fixP
->fx_addsy
!= NULL
7782 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7783 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7784 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7785 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7786 && !use_rela_relocations
)
7788 /* This is a hack. There should be a better way to handle this.
7789 This covers for the fact that bfd_install_relocation will
7790 subtract the current location (for partial_inplace, PC relative
7791 relocations); see more below. */
7795 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7798 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7800 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7803 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7806 || (symbol_section_p (fixP
->fx_addsy
)
7807 && sym_seg
!= absolute_section
))
7808 && !generic_force_reloc (fixP
))
7810 /* Yes, we add the values in twice. This is because
7811 bfd_install_relocation subtracts them out again. I think
7812 bfd_install_relocation is broken, but I don't dare change
7814 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7818 #if defined (OBJ_COFF) && defined (TE_PE)
7819 /* For some reason, the PE format does not store a
7820 section address offset for a PC relative symbol. */
7821 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7822 || S_IS_WEAK (fixP
->fx_addsy
))
7823 value
+= md_pcrel_from (fixP
);
7826 #if defined (OBJ_COFF) && defined (TE_PE)
7827 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7829 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7833 /* Fix a few things - the dynamic linker expects certain values here,
7834 and we must not disappoint it. */
7835 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7836 if (IS_ELF
&& fixP
->fx_addsy
)
7837 switch (fixP
->fx_r_type
)
7839 case BFD_RELOC_386_PLT32
:
7840 case BFD_RELOC_X86_64_PLT32
:
7841 /* Make the jump instruction point to the address of the operand. At
7842 runtime we merely add the offset to the actual PLT entry. */
7846 case BFD_RELOC_386_TLS_GD
:
7847 case BFD_RELOC_386_TLS_LDM
:
7848 case BFD_RELOC_386_TLS_IE_32
:
7849 case BFD_RELOC_386_TLS_IE
:
7850 case BFD_RELOC_386_TLS_GOTIE
:
7851 case BFD_RELOC_386_TLS_GOTDESC
:
7852 case BFD_RELOC_X86_64_TLSGD
:
7853 case BFD_RELOC_X86_64_TLSLD
:
7854 case BFD_RELOC_X86_64_GOTTPOFF
:
7855 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7856 value
= 0; /* Fully resolved at runtime. No addend. */
7858 case BFD_RELOC_386_TLS_LE
:
7859 case BFD_RELOC_386_TLS_LDO_32
:
7860 case BFD_RELOC_386_TLS_LE_32
:
7861 case BFD_RELOC_X86_64_DTPOFF32
:
7862 case BFD_RELOC_X86_64_DTPOFF64
:
7863 case BFD_RELOC_X86_64_TPOFF32
:
7864 case BFD_RELOC_X86_64_TPOFF64
:
7865 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7868 case BFD_RELOC_386_TLS_DESC_CALL
:
7869 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7870 value
= 0; /* Fully resolved at runtime. No addend. */
7871 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7875 case BFD_RELOC_386_GOT32
:
7876 case BFD_RELOC_X86_64_GOT32
:
7877 value
= 0; /* Fully resolved at runtime. No addend. */
7880 case BFD_RELOC_VTABLE_INHERIT
:
7881 case BFD_RELOC_VTABLE_ENTRY
:
7888 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7890 #endif /* !defined (TE_Mach) */
7892 /* Are we finished with this relocation now? */
7893 if (fixP
->fx_addsy
== NULL
)
7895 #if defined (OBJ_COFF) && defined (TE_PE)
7896 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7899 /* Remember value for tc_gen_reloc. */
7900 fixP
->fx_addnumber
= value
;
7901 /* Clear out the frag for now. */
7905 else if (use_rela_relocations
)
7907 fixP
->fx_no_overflow
= 1;
7908 /* Remember value for tc_gen_reloc. */
7909 fixP
->fx_addnumber
= value
;
7913 md_number_to_chars (p
, value
, fixP
->fx_size
);
7917 md_atof (int type
, char *litP
, int *sizeP
)
7919 /* This outputs the LITTLENUMs in REVERSE order;
7920 in accord with the bigendian 386. */
7921 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7924 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7927 output_invalid (int c
)
7930 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7933 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7934 "(0x%x)", (unsigned char) c
);
7935 return output_invalid_buf
;
7938 /* REG_STRING starts *before* REGISTER_PREFIX. */
7940 static const reg_entry
*
7941 parse_real_register (char *reg_string
, char **end_op
)
7943 char *s
= reg_string
;
7945 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7948 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7949 if (*s
== REGISTER_PREFIX
)
7952 if (is_space_char (*s
))
7956 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7958 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7959 return (const reg_entry
*) NULL
;
7963 /* For naked regs, make sure that we are not dealing with an identifier.
7964 This prevents confusing an identifier like `eax_var' with register
7966 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7967 return (const reg_entry
*) NULL
;
7971 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7973 /* Handle floating point regs, allowing spaces in the (i) part. */
7974 if (r
== i386_regtab
/* %st is first entry of table */)
7976 if (is_space_char (*s
))
7981 if (is_space_char (*s
))
7983 if (*s
>= '0' && *s
<= '7')
7987 if (is_space_char (*s
))
7992 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7997 /* We have "%st(" then garbage. */
7998 return (const reg_entry
*) NULL
;
8002 if (r
== NULL
|| allow_pseudo_reg
)
8005 if (operand_type_all_zero (&r
->reg_type
))
8006 return (const reg_entry
*) NULL
;
8008 if ((r
->reg_type
.bitfield
.reg32
8009 || r
->reg_type
.bitfield
.sreg3
8010 || r
->reg_type
.bitfield
.control
8011 || r
->reg_type
.bitfield
.debug
8012 || r
->reg_type
.bitfield
.test
)
8013 && !cpu_arch_flags
.bitfield
.cpui386
)
8014 return (const reg_entry
*) NULL
;
8016 if (r
->reg_type
.bitfield
.floatreg
8017 && !cpu_arch_flags
.bitfield
.cpu8087
8018 && !cpu_arch_flags
.bitfield
.cpu287
8019 && !cpu_arch_flags
.bitfield
.cpu387
)
8020 return (const reg_entry
*) NULL
;
8022 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8023 return (const reg_entry
*) NULL
;
8025 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8026 return (const reg_entry
*) NULL
;
8028 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8029 return (const reg_entry
*) NULL
;
8031 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8032 if (!allow_index_reg
8033 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8034 return (const reg_entry
*) NULL
;
8036 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8037 || r
->reg_type
.bitfield
.reg64
)
8038 && (!cpu_arch_flags
.bitfield
.cpulm
8039 || !operand_type_equal (&r
->reg_type
, &control
))
8040 && flag_code
!= CODE_64BIT
)
8041 return (const reg_entry
*) NULL
;
8043 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8044 return (const reg_entry
*) NULL
;
8049 /* REG_STRING starts *before* REGISTER_PREFIX. */
8051 static const reg_entry
*
8052 parse_register (char *reg_string
, char **end_op
)
8056 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8057 r
= parse_real_register (reg_string
, end_op
);
8062 char *save
= input_line_pointer
;
8066 input_line_pointer
= reg_string
;
8067 c
= get_symbol_end ();
8068 symbolP
= symbol_find (reg_string
);
8069 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8071 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8073 know (e
->X_op
== O_register
);
8074 know (e
->X_add_number
>= 0
8075 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8076 r
= i386_regtab
+ e
->X_add_number
;
8077 *end_op
= input_line_pointer
;
8079 *input_line_pointer
= c
;
8080 input_line_pointer
= save
;
8086 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8089 char *end
= input_line_pointer
;
8092 r
= parse_register (name
, &input_line_pointer
);
8093 if (r
&& end
<= input_line_pointer
)
8095 *nextcharP
= *input_line_pointer
;
8096 *input_line_pointer
= 0;
8097 e
->X_op
= O_register
;
8098 e
->X_add_number
= r
- i386_regtab
;
8101 input_line_pointer
= end
;
8103 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8107 md_operand (expressionS
*e
)
8112 switch (*input_line_pointer
)
8114 case REGISTER_PREFIX
:
8115 r
= parse_real_register (input_line_pointer
, &end
);
8118 e
->X_op
= O_register
;
8119 e
->X_add_number
= r
- i386_regtab
;
8120 input_line_pointer
= end
;
8125 gas_assert (intel_syntax
);
8126 end
= input_line_pointer
++;
8128 if (*input_line_pointer
== ']')
8130 ++input_line_pointer
;
8131 e
->X_op_symbol
= make_expr_symbol (e
);
8132 e
->X_add_symbol
= NULL
;
8133 e
->X_add_number
= 0;
8139 input_line_pointer
= end
;
8146 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8147 const char *md_shortopts
= "kVQ:sqn";
8149 const char *md_shortopts
= "qn";
8152 #define OPTION_32 (OPTION_MD_BASE + 0)
8153 #define OPTION_64 (OPTION_MD_BASE + 1)
8154 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8155 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8156 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8157 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8158 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8159 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8160 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8161 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8162 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8163 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8164 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8165 #define OPTION_X32 (OPTION_MD_BASE + 13)
8167 struct option md_longopts
[] =
8169 {"32", no_argument
, NULL
, OPTION_32
},
8170 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8171 || defined (TE_PE) || defined (TE_PEP))
8172 {"64", no_argument
, NULL
, OPTION_64
},
8174 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8175 {"x32", no_argument
, NULL
, OPTION_X32
},
8177 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8178 {"march", required_argument
, NULL
, OPTION_MARCH
},
8179 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8180 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8181 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8182 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8183 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8184 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8185 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8186 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8187 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8188 {NULL
, no_argument
, NULL
, 0}
8190 size_t md_longopts_size
= sizeof (md_longopts
);
8193 md_parse_option (int c
, char *arg
)
8201 optimize_align_code
= 0;
8208 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8209 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8210 should be emitted or not. FIXME: Not implemented. */
8214 /* -V: SVR4 argument to print version ID. */
8216 print_version_id ();
8219 /* -k: Ignore for FreeBSD compatibility. */
8224 /* -s: On i386 Solaris, this tells the native assembler to use
8225 .stab instead of .stab.excl. We always use .stab anyhow. */
8228 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8229 || defined (TE_PE) || defined (TE_PEP))
8232 const char **list
, **l
;
8234 list
= bfd_target_list ();
8235 for (l
= list
; *l
!= NULL
; l
++)
8236 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8237 || strcmp (*l
, "coff-x86-64") == 0
8238 || strcmp (*l
, "pe-x86-64") == 0
8239 || strcmp (*l
, "pei-x86-64") == 0)
8241 default_arch
= "x86_64";
8245 as_fatal (_("No compiled in support for x86_64"));
8251 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8255 const char **list
, **l
;
8257 list
= bfd_target_list ();
8258 for (l
= list
; *l
!= NULL
; l
++)
8259 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8261 default_arch
= "x86_64:32";
8265 as_fatal (_("No compiled in support for 32bit x86_64"));
8269 as_fatal (_("32bit x86_64 is only supported for ELF"));
8274 default_arch
= "i386";
8278 #ifdef SVR4_COMMENT_CHARS
8283 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8285 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8289 i386_comment_chars
= n
;
8295 arch
= xstrdup (arg
);
8299 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8300 next
= strchr (arch
, '+');
8303 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8305 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8308 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8311 cpu_arch_name
= cpu_arch
[j
].name
;
8312 cpu_sub_arch_name
= NULL
;
8313 cpu_arch_flags
= cpu_arch
[j
].flags
;
8314 cpu_arch_isa
= cpu_arch
[j
].type
;
8315 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8316 if (!cpu_arch_tune_set
)
8318 cpu_arch_tune
= cpu_arch_isa
;
8319 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8323 else if (*cpu_arch
[j
].name
== '.'
8324 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8326 /* ISA entension. */
8327 i386_cpu_flags flags
;
8329 if (!cpu_arch
[j
].negated
)
8330 flags
= cpu_flags_or (cpu_arch_flags
,
8333 flags
= cpu_flags_and_not (cpu_arch_flags
,
8335 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8337 if (cpu_sub_arch_name
)
8339 char *name
= cpu_sub_arch_name
;
8340 cpu_sub_arch_name
= concat (name
,
8342 (const char *) NULL
);
8346 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8347 cpu_arch_flags
= flags
;
8348 cpu_arch_isa_flags
= flags
;
8354 if (j
>= ARRAY_SIZE (cpu_arch
))
8355 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8359 while (next
!= NULL
);
8364 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8365 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8367 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8369 cpu_arch_tune_set
= 1;
8370 cpu_arch_tune
= cpu_arch
[j
].type
;
8371 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8375 if (j
>= ARRAY_SIZE (cpu_arch
))
8376 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8379 case OPTION_MMNEMONIC
:
8380 if (strcasecmp (arg
, "att") == 0)
8382 else if (strcasecmp (arg
, "intel") == 0)
8385 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8388 case OPTION_MSYNTAX
:
8389 if (strcasecmp (arg
, "att") == 0)
8391 else if (strcasecmp (arg
, "intel") == 0)
8394 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8397 case OPTION_MINDEX_REG
:
8398 allow_index_reg
= 1;
8401 case OPTION_MNAKED_REG
:
8402 allow_naked_reg
= 1;
8405 case OPTION_MOLD_GCC
:
8409 case OPTION_MSSE2AVX
:
8413 case OPTION_MSSE_CHECK
:
8414 if (strcasecmp (arg
, "error") == 0)
8415 sse_check
= sse_check_error
;
8416 else if (strcasecmp (arg
, "warning") == 0)
8417 sse_check
= sse_check_warning
;
8418 else if (strcasecmp (arg
, "none") == 0)
8419 sse_check
= sse_check_none
;
8421 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8424 case OPTION_MAVXSCALAR
:
8425 if (strcasecmp (arg
, "128") == 0)
8427 else if (strcasecmp (arg
, "256") == 0)
8430 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8439 #define MESSAGE_TEMPLATE \
8443 show_arch (FILE *stream
, int ext
, int check
)
8445 static char message
[] = MESSAGE_TEMPLATE
;
8446 char *start
= message
+ 27;
8448 int size
= sizeof (MESSAGE_TEMPLATE
);
8455 left
= size
- (start
- message
);
8456 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8458 /* Should it be skipped? */
8459 if (cpu_arch
[j
].skip
)
8462 name
= cpu_arch
[j
].name
;
8463 len
= cpu_arch
[j
].len
;
8466 /* It is an extension. Skip if we aren't asked to show it. */
8477 /* It is an processor. Skip if we show only extension. */
8480 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8482 /* It is an impossible processor - skip. */
8486 /* Reserve 2 spaces for ", " or ",\0" */
8489 /* Check if there is any room. */
8497 p
= mempcpy (p
, name
, len
);
8501 /* Output the current message now and start a new one. */
8504 fprintf (stream
, "%s\n", message
);
8506 left
= size
- (start
- message
) - len
- 2;
8508 gas_assert (left
>= 0);
8510 p
= mempcpy (p
, name
, len
);
8515 fprintf (stream
, "%s\n", message
);
8519 md_show_usage (FILE *stream
)
8521 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8522 fprintf (stream
, _("\
8524 -V print assembler version number\n\
8527 fprintf (stream
, _("\
8528 -n Do not optimize code alignment\n\
8529 -q quieten some warnings\n"));
8530 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8531 fprintf (stream
, _("\
8534 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8535 || defined (TE_PE) || defined (TE_PEP))
8536 fprintf (stream
, _("\
8537 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8539 #ifdef SVR4_COMMENT_CHARS
8540 fprintf (stream
, _("\
8541 --divide do not treat `/' as a comment character\n"));
8543 fprintf (stream
, _("\
8544 --divide ignored\n"));
8546 fprintf (stream
, _("\
8547 -march=CPU[,+EXTENSION...]\n\
8548 generate code for CPU and EXTENSION, CPU is one of:\n"));
8549 show_arch (stream
, 0, 1);
8550 fprintf (stream
, _("\
8551 EXTENSION is combination of:\n"));
8552 show_arch (stream
, 1, 0);
8553 fprintf (stream
, _("\
8554 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8555 show_arch (stream
, 0, 0);
8556 fprintf (stream
, _("\
8557 -msse2avx encode SSE instructions with VEX prefix\n"));
8558 fprintf (stream
, _("\
8559 -msse-check=[none|error|warning]\n\
8560 check SSE instructions\n"));
8561 fprintf (stream
, _("\
8562 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8564 fprintf (stream
, _("\
8565 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8566 fprintf (stream
, _("\
8567 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8568 fprintf (stream
, _("\
8569 -mindex-reg support pseudo index registers\n"));
8570 fprintf (stream
, _("\
8571 -mnaked-reg don't require `%%' prefix for registers\n"));
8572 fprintf (stream
, _("\
8573 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8576 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8577 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8578 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8580 /* Pick the target format to use. */
8583 i386_target_format (void)
8585 if (!strncmp (default_arch
, "x86_64", 6))
8587 update_code_flag (CODE_64BIT
, 1);
8588 if (default_arch
[6] == '\0')
8589 x86_elf_abi
= X86_64_ABI
;
8591 x86_elf_abi
= X86_64_X32_ABI
;
8593 else if (!strcmp (default_arch
, "i386"))
8594 update_code_flag (CODE_32BIT
, 1);
8596 as_fatal (_("Unknown architecture"));
8598 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8599 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8600 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8601 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8603 switch (OUTPUT_FLAVOR
)
8605 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8606 case bfd_target_aout_flavour
:
8607 return AOUT_TARGET_FORMAT
;
8609 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8610 # if defined (TE_PE) || defined (TE_PEP)
8611 case bfd_target_coff_flavour
:
8612 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8613 # elif defined (TE_GO32)
8614 case bfd_target_coff_flavour
:
8617 case bfd_target_coff_flavour
:
8621 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8622 case bfd_target_elf_flavour
:
8626 switch (x86_elf_abi
)
8629 format
= ELF_TARGET_FORMAT
;
8632 use_rela_relocations
= 1;
8634 format
= ELF_TARGET_FORMAT64
;
8636 case X86_64_X32_ABI
:
8637 use_rela_relocations
= 1;
8639 disallow_64bit_reloc
= 1;
8640 format
= ELF_TARGET_FORMAT32
;
8643 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8645 if (x86_elf_abi
!= X86_64_ABI
)
8646 as_fatal (_("Intel L1OM is 64bit only"));
8647 return ELF_TARGET_L1OM_FORMAT
;
8653 #if defined (OBJ_MACH_O)
8654 case bfd_target_mach_o_flavour
:
8655 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8663 #endif /* OBJ_MAYBE_ more than one */
8665 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8667 i386_elf_emit_arch_note (void)
8669 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8672 asection
*seg
= now_seg
;
8673 subsegT subseg
= now_subseg
;
8674 Elf_Internal_Note i_note
;
8675 Elf_External_Note e_note
;
8676 asection
*note_secp
;
8679 /* Create the .note section. */
8680 note_secp
= subseg_new (".note", 0);
8681 bfd_set_section_flags (stdoutput
,
8683 SEC_HAS_CONTENTS
| SEC_READONLY
);
8685 /* Process the arch string. */
8686 len
= strlen (cpu_arch_name
);
8688 i_note
.namesz
= len
+ 1;
8690 i_note
.type
= NT_ARCH
;
8691 p
= frag_more (sizeof (e_note
.namesz
));
8692 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8693 p
= frag_more (sizeof (e_note
.descsz
));
8694 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8695 p
= frag_more (sizeof (e_note
.type
));
8696 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8697 p
= frag_more (len
+ 1);
8698 strcpy (p
, cpu_arch_name
);
8700 frag_align (2, 0, 0);
8702 subseg_set (seg
, subseg
);
8708 md_undefined_symbol (name
)
8711 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8712 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8713 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8714 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8718 if (symbol_find (name
))
8719 as_bad (_("GOT already in symbol table"));
8720 GOT_symbol
= symbol_new (name
, undefined_section
,
8721 (valueT
) 0, &zero_address_frag
);
8728 /* Round up a section size to the appropriate boundary. */
8731 md_section_align (segment
, size
)
8732 segT segment ATTRIBUTE_UNUSED
;
8735 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8736 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8738 /* For a.out, force the section size to be aligned. If we don't do
8739 this, BFD will align it for us, but it will not write out the
8740 final bytes of the section. This may be a bug in BFD, but it is
8741 easier to fix it here since that is how the other a.out targets
8745 align
= bfd_get_section_alignment (stdoutput
, segment
);
8746 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8753 /* On the i386, PC-relative offsets are relative to the start of the
8754 next instruction. That is, the address of the offset, plus its
8755 size, since the offset is always the last part of the insn. */
8758 md_pcrel_from (fixS
*fixP
)
8760 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8766 s_bss (int ignore ATTRIBUTE_UNUSED
)
8770 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8772 obj_elf_section_change_hook ();
8774 temp
= get_absolute_expression ();
8775 subseg_set (bss_section
, (subsegT
) temp
);
8776 demand_empty_rest_of_line ();
8782 i386_validate_fix (fixS
*fixp
)
8784 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8786 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8790 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8795 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8797 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8804 tc_gen_reloc (section
, fixp
)
8805 asection
*section ATTRIBUTE_UNUSED
;
8809 bfd_reloc_code_real_type code
;
8811 switch (fixp
->fx_r_type
)
8813 case BFD_RELOC_X86_64_PLT32
:
8814 case BFD_RELOC_X86_64_GOT32
:
8815 case BFD_RELOC_X86_64_GOTPCREL
:
8816 case BFD_RELOC_386_PLT32
:
8817 case BFD_RELOC_386_GOT32
:
8818 case BFD_RELOC_386_GOTOFF
:
8819 case BFD_RELOC_386_GOTPC
:
8820 case BFD_RELOC_386_TLS_GD
:
8821 case BFD_RELOC_386_TLS_LDM
:
8822 case BFD_RELOC_386_TLS_LDO_32
:
8823 case BFD_RELOC_386_TLS_IE_32
:
8824 case BFD_RELOC_386_TLS_IE
:
8825 case BFD_RELOC_386_TLS_GOTIE
:
8826 case BFD_RELOC_386_TLS_LE_32
:
8827 case BFD_RELOC_386_TLS_LE
:
8828 case BFD_RELOC_386_TLS_GOTDESC
:
8829 case BFD_RELOC_386_TLS_DESC_CALL
:
8830 case BFD_RELOC_X86_64_TLSGD
:
8831 case BFD_RELOC_X86_64_TLSLD
:
8832 case BFD_RELOC_X86_64_DTPOFF32
:
8833 case BFD_RELOC_X86_64_DTPOFF64
:
8834 case BFD_RELOC_X86_64_GOTTPOFF
:
8835 case BFD_RELOC_X86_64_TPOFF32
:
8836 case BFD_RELOC_X86_64_TPOFF64
:
8837 case BFD_RELOC_X86_64_GOTOFF64
:
8838 case BFD_RELOC_X86_64_GOTPC32
:
8839 case BFD_RELOC_X86_64_GOT64
:
8840 case BFD_RELOC_X86_64_GOTPCREL64
:
8841 case BFD_RELOC_X86_64_GOTPC64
:
8842 case BFD_RELOC_X86_64_GOTPLT64
:
8843 case BFD_RELOC_X86_64_PLTOFF64
:
8844 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8845 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8847 case BFD_RELOC_VTABLE_ENTRY
:
8848 case BFD_RELOC_VTABLE_INHERIT
:
8850 case BFD_RELOC_32_SECREL
:
8852 code
= fixp
->fx_r_type
;
8854 case BFD_RELOC_X86_64_32S
:
8855 if (!fixp
->fx_pcrel
)
8857 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8858 code
= fixp
->fx_r_type
;
8864 switch (fixp
->fx_size
)
8867 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8868 _("can not do %d byte pc-relative relocation"),
8870 code
= BFD_RELOC_32_PCREL
;
8872 case 1: code
= BFD_RELOC_8_PCREL
; break;
8873 case 2: code
= BFD_RELOC_16_PCREL
; break;
8874 case 4: code
= BFD_RELOC_32_PCREL
; break;
8876 case 8: code
= BFD_RELOC_64_PCREL
; break;
8882 switch (fixp
->fx_size
)
8885 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8886 _("can not do %d byte relocation"),
8888 code
= BFD_RELOC_32
;
8890 case 1: code
= BFD_RELOC_8
; break;
8891 case 2: code
= BFD_RELOC_16
; break;
8892 case 4: code
= BFD_RELOC_32
; break;
8894 case 8: code
= BFD_RELOC_64
; break;
8901 if ((code
== BFD_RELOC_32
8902 || code
== BFD_RELOC_32_PCREL
8903 || code
== BFD_RELOC_X86_64_32S
)
8905 && fixp
->fx_addsy
== GOT_symbol
)
8908 code
= BFD_RELOC_386_GOTPC
;
8910 code
= BFD_RELOC_X86_64_GOTPC32
;
8912 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8914 && fixp
->fx_addsy
== GOT_symbol
)
8916 code
= BFD_RELOC_X86_64_GOTPC64
;
8919 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8920 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8921 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8923 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8925 if (!use_rela_relocations
)
8927 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8928 vtable entry to be used in the relocation's section offset. */
8929 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8930 rel
->address
= fixp
->fx_offset
;
8931 #if defined (OBJ_COFF) && defined (TE_PE)
8932 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8933 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8938 /* Use the rela in 64bit mode. */
8941 if (disallow_64bit_reloc
)
8945 case BFD_RELOC_X86_64_DTPOFF64
:
8946 case BFD_RELOC_X86_64_TPOFF64
:
8947 case BFD_RELOC_64_PCREL
:
8948 case BFD_RELOC_X86_64_GOTOFF64
:
8949 case BFD_RELOC_X86_64_GOT64
:
8950 case BFD_RELOC_X86_64_GOTPCREL64
:
8951 case BFD_RELOC_X86_64_GOTPC64
:
8952 case BFD_RELOC_X86_64_GOTPLT64
:
8953 case BFD_RELOC_X86_64_PLTOFF64
:
8954 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8955 _("cannot represent relocation type %s in x32 mode"),
8956 bfd_get_reloc_code_name (code
));
8962 if (!fixp
->fx_pcrel
)
8963 rel
->addend
= fixp
->fx_offset
;
8967 case BFD_RELOC_X86_64_PLT32
:
8968 case BFD_RELOC_X86_64_GOT32
:
8969 case BFD_RELOC_X86_64_GOTPCREL
:
8970 case BFD_RELOC_X86_64_TLSGD
:
8971 case BFD_RELOC_X86_64_TLSLD
:
8972 case BFD_RELOC_X86_64_GOTTPOFF
:
8973 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8974 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8975 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8978 rel
->addend
= (section
->vma
8980 + fixp
->fx_addnumber
8981 + md_pcrel_from (fixp
));
8986 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8987 if (rel
->howto
== NULL
)
8989 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8990 _("cannot represent relocation type %s"),
8991 bfd_get_reloc_code_name (code
));
8992 /* Set howto to a garbage value so that we can keep going. */
8993 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8994 gas_assert (rel
->howto
!= NULL
);
9000 #include "tc-i386-intel.c"
9003 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9005 int saved_naked_reg
;
9006 char saved_register_dot
;
9008 saved_naked_reg
= allow_naked_reg
;
9009 allow_naked_reg
= 1;
9010 saved_register_dot
= register_chars
['.'];
9011 register_chars
['.'] = '.';
9012 allow_pseudo_reg
= 1;
9013 expression_and_evaluate (exp
);
9014 allow_pseudo_reg
= 0;
9015 register_chars
['.'] = saved_register_dot
;
9016 allow_naked_reg
= saved_naked_reg
;
9018 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9020 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9022 exp
->X_op
= O_constant
;
9023 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9024 .dw2_regnum
[flag_code
>> 1];
9027 exp
->X_op
= O_illegal
;
9032 tc_x86_frame_initial_instructions (void)
9034 static unsigned int sp_regno
[2];
9036 if (!sp_regno
[flag_code
>> 1])
9038 char *saved_input
= input_line_pointer
;
9039 char sp
[][4] = {"esp", "rsp"};
9042 input_line_pointer
= sp
[flag_code
>> 1];
9043 tc_x86_parse_to_dw2regnum (&exp
);
9044 gas_assert (exp
.X_op
== O_constant
);
9045 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9046 input_line_pointer
= saved_input
;
9049 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9050 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9054 i386_elf_section_type (const char *str
, size_t len
)
9056 if (flag_code
== CODE_64BIT
9057 && len
== sizeof ("unwind") - 1
9058 && strncmp (str
, "unwind", 6) == 0)
9059 return SHT_X86_64_UNWIND
;
9066 i386_solaris_fix_up_eh_frame (segT sec
)
9068 if (flag_code
== CODE_64BIT
)
9069 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9075 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9079 exp
.X_op
= O_secrel
;
9080 exp
.X_add_symbol
= symbol
;
9081 exp
.X_add_number
= 0;
9082 emit_expr (&exp
, size
);
9086 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9087 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9090 x86_64_section_letter (int letter
, char **ptr_msg
)
9092 if (flag_code
== CODE_64BIT
)
9095 return SHF_X86_64_LARGE
;
9097 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9100 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9105 x86_64_section_word (char *str
, size_t len
)
9107 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9108 return SHF_X86_64_LARGE
;
9114 handle_large_common (int small ATTRIBUTE_UNUSED
)
9116 if (flag_code
!= CODE_64BIT
)
9118 s_comm_internal (0, elf_common_parse
);
9119 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9123 static segT lbss_section
;
9124 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9125 asection
*saved_bss_section
= bss_section
;
9127 if (lbss_section
== NULL
)
9129 flagword applicable
;
9131 subsegT subseg
= now_subseg
;
9133 /* The .lbss section is for local .largecomm symbols. */
9134 lbss_section
= subseg_new (".lbss", 0);
9135 applicable
= bfd_applicable_section_flags (stdoutput
);
9136 bfd_set_section_flags (stdoutput
, lbss_section
,
9137 applicable
& SEC_ALLOC
);
9138 seg_info (lbss_section
)->bss
= 1;
9140 subseg_set (seg
, subseg
);
9143 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9144 bss_section
= lbss_section
;
9146 s_comm_internal (0, elf_common_parse
);
9148 elf_com_section_ptr
= saved_com_section_ptr
;
9149 bss_section
= saved_bss_section
;
9152 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */