Add support for DragonFlyBSD target.

[binutils.git] / gas / config / tc-i386.c

/* tc-i386.c -- Assemble code for the Intel 80386
   Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
   2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
   Free Software Foundation, Inc.

   This file is part of GAS, the GNU Assembler.

   GAS is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS; see the file COPYING.  If not, write to the Free
   Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
   02110-1301, USA.  */

/* Intel 80386 machine specific gas.
   Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
   x86_64 support by Jan Hubicka (jh@suse.cz)
   VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
   Bugs & suggestions are completely welcome.  This is free software.
   Please help us make it better.  */

#include "as.h"
#include "safe-ctype.h"
#include "subsegs.h"
#include "dwarf2dbg.h"
#include "dw2gencfi.h"
#include "elf/x86-64.h"
#include "opcodes/i386-init.h"

#ifndef REGISTER_WARNINGS
#define REGISTER_WARNINGS 1
#endif

#ifndef INFER_ADDR_PREFIX
#define INFER_ADDR_PREFIX 1
#endif

#ifndef DEFAULT_ARCH
#define DEFAULT_ARCH "i386"
#endif

#ifndef INLINE
#if __GNUC__ >= 2
#define INLINE __inline__
#else
#define INLINE
#endif
#endif

/* Prefixes will be emitted in the order defined below.
   WAIT_PREFIX must be the first prefix since FWAIT is really is an
   instruction, and so must come before any prefixes.
   The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
   REP_PREFIX, LOCK_PREFIX.  */
#define WAIT_PREFIX     0
#define SEG_PREFIX      1
#define ADDR_PREFIX     2
#define DATA_PREFIX     3
#define REP_PREFIX      4
#define LOCK_PREFIX     5
#define REX_PREFIX      6       /* must come last.  */
#define MAX_PREFIXES    7       /* max prefixes per opcode */

/* we define the syntax here (modulo base,index,scale syntax) */
#define REGISTER_PREFIX '%'
#define IMMEDIATE_PREFIX '$'
#define ABSOLUTE_PREFIX '*'

/* these are the instruction mnemonic suffixes in AT&T syntax or
   memory operand size in Intel syntax.  */
#define WORD_MNEM_SUFFIX  'w'
#define BYTE_MNEM_SUFFIX  'b'
#define SHORT_MNEM_SUFFIX 's'
#define LONG_MNEM_SUFFIX  'l'
#define QWORD_MNEM_SUFFIX  'q'
#define XMMWORD_MNEM_SUFFIX  'x'
#define YMMWORD_MNEM_SUFFIX 'y'
/* Intel Syntax.  Use a non-ascii letter since since it never appears
   in instructions.  */
#define LONG_DOUBLE_MNEM_SUFFIX '\1'

#define END_OF_INSN '\0'

/*
  'templates' is for grouping together 'template' structures for opcodes
  of the same name.  This is only used for storing the insns in the grand
  ole hash table of insns.
  The templates themselves start at START and range up to (but not including)
  END.
  */
typedef struct
{
  const insn_template *start;
  const insn_template *end;
}
templates;

/* 386 operand encoding bytes:  see 386 book for details of this.  */
typedef struct
{
  unsigned int regmem;  /* codes register or memory operand */
  unsigned int reg;     /* codes register operand (or extended opcode) */
  unsigned int mode;    /* how to interpret regmem & reg */
}
modrm_byte;

/* x86-64 extension prefix.  */
typedef int rex_byte;

/* 386 opcode byte to code indirect addressing.  */
typedef struct
{
  unsigned base;
  unsigned index;
  unsigned scale;
}
sib_byte;

/* x86 arch names, types and features */
typedef struct
{
  const char *name;             /* arch name */
  unsigned int len;             /* arch string length */
  enum processor_type type;     /* arch type */
  i386_cpu_flags flags;         /* cpu feature flags */
  unsigned int skip;            /* show_arch should skip this. */
  unsigned int negated;         /* turn off indicated flags.  */
}
arch_entry;

static void update_code_flag (int, int);
static void set_code_flag (int);
static void set_16bit_gcc_code_flag (int);
static void set_intel_syntax (int);
static void set_intel_mnemonic (int);
static void set_allow_index_reg (int);
static void set_sse_check (int);
static void set_cpu_arch (int);
#ifdef TE_PE
static void pe_directive_secrel (int);
#endif
static void signed_cons (int);
static char *output_invalid (int c);
static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
                                    const char *);
static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
                                       const char *);
static int i386_att_operand (char *);
static int i386_intel_operand (char *, int);
static int i386_intel_simplify (expressionS *);
static int i386_intel_parse_name (const char *, expressionS *);
static const reg_entry *parse_register (char *, char **);
static char *parse_insn (char *, char *);
static char *parse_operands (char *, const char *);
static void swap_operands (void);
static void swap_2_operands (int, int);
static void optimize_imm (void);
static void optimize_disp (void);
static const insn_template *match_template (void);
static int check_string (void);
static int process_suffix (void);
static int check_byte_reg (void);
static int check_long_reg (void);
static int check_qword_reg (void);
static int check_word_reg (void);
static int finalize_imm (void);
static int process_operands (void);
static const seg_entry *build_modrm_byte (void);
static void output_insn (void);
static void output_imm (fragS *, offsetT);
static void output_disp (fragS *, offsetT);
#ifndef I386COFF
static void s_bss (int);
#endif
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
static void handle_large_common (int small ATTRIBUTE_UNUSED);
#endif

static const char *default_arch = DEFAULT_ARCH;

/* VEX prefix.  */
typedef struct
{
  /* VEX prefix is either 2 byte or 3 byte.  */
  unsigned char bytes[3];
  unsigned int length;
  /* Destination or source register specifier.  */
  const reg_entry *register_specifier;
} vex_prefix;

/* 'md_assemble ()' gathers together information and puts it into a
   i386_insn.  */

union i386_op
  {
    expressionS *disps;
    expressionS *imms;
    const reg_entry *regs;
  };

enum i386_error
  {
    operand_size_mismatch,
    operand_type_mismatch,
    register_type_mismatch,
    number_of_operands_mismatch,
    invalid_instruction_suffix,
    bad_imm4,
    old_gcc_only,
    unsupported_with_intel_mnemonic,
    unsupported_syntax,
    unsupported
  };

struct _i386_insn
  {
    /* TM holds the template for the insn were currently assembling.  */
    insn_template tm;

    /* SUFFIX holds the instruction size suffix for byte, word, dword
       or qword, if given.  */
    char suffix;

    /* OPERANDS gives the number of given operands.  */
    unsigned int operands;

    /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
       of given register, displacement, memory operands and immediate
       operands.  */
    unsigned int reg_operands, disp_operands, mem_operands, imm_operands;

    /* TYPES [i] is the type (see above #defines) which tells us how to
       use OP[i] for the corresponding operand.  */
    i386_operand_type types[MAX_OPERANDS];

    /* Displacement expression, immediate expression, or register for each
       operand.  */
    union i386_op op[MAX_OPERANDS];

    /* Flags for operands.  */
    unsigned int flags[MAX_OPERANDS];
#define Operand_PCrel 1

    /* Relocation type for operand */
    enum bfd_reloc_code_real reloc[MAX_OPERANDS];

    /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
       the base index byte below.  */
    const reg_entry *base_reg;
    const reg_entry *index_reg;
    unsigned int log2_scale_factor;

    /* SEG gives the seg_entries of this insn.  They are zero unless
       explicit segment overrides are given.  */
    const seg_entry *seg[2];

    /* PREFIX holds all the given prefix opcodes (usually null).
       PREFIXES is the number of prefix opcodes.  */
    unsigned int prefixes;
    unsigned char prefix[MAX_PREFIXES];

    /* RM and SIB are the modrm byte and the sib byte where the
       addressing modes of this insn are encoded.  */
    modrm_byte rm;
    rex_byte rex;
    sib_byte sib;
    vex_prefix vex;

    /* Swap operand in encoding.  */
    unsigned int swap_operand;

    /* Force 32bit displacement in encoding.  */
    unsigned int disp32_encoding;

    /* Error message.  */
    enum i386_error error;
  };

typedef struct _i386_insn i386_insn;

/* List of chars besides those in app.c:symbol_chars that can start an
   operand.  Used to prevent the scrubber eating vital white-space.  */
const char extra_symbol_chars[] = "*%-(["
#ifdef LEX_AT
        "@"
#endif
#ifdef LEX_QM
        "?"
#endif
        ;

#if (defined (TE_I386AIX)                               \
     || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
         && !defined (TE_GNU)                           \
         && !defined (TE_LINUX)                         \
         && !defined (TE_NETWARE)                       \
         && !defined (TE_FreeBSD)                       \
         && !defined (TE_DragonFly)                     \
         && !defined (TE_NetBSD)))
/* This array holds the chars that always start a comment.  If the
   pre-processor is disabled, these aren't very useful.  The option
   --divide will remove '/' from this list.  */
const char *i386_comment_chars = "#/";
#define SVR4_COMMENT_CHARS 1
#define PREFIX_SEPARATOR '\\'

#else
const char *i386_comment_chars = "#";
#define PREFIX_SEPARATOR '/'
#endif

/* This array holds the chars that only start a comment at the beginning of
   a line.  If the line seems to have the form '# 123 filename'
   .line and .file directives will appear in the pre-processed output.
   Note that input_file.c hand checks for '#' at the beginning of the
   first line of the input file.  This is because the compiler outputs
   #NO_APP at the beginning of its output.
   Also note that comments started like this one will always work if
   '/' isn't otherwise defined.  */
const char line_comment_chars[] = "#/";

const char line_separator_chars[] = ";";

/* Chars that can be used to separate mant from exp in floating point
   nums.  */
const char EXP_CHARS[] = "eE";

/* Chars that mean this number is a floating point constant
   As in 0f12.456
   or    0d1.2345e12.  */
const char FLT_CHARS[] = "fFdDxX";

/* Tables for lexical analysis.  */
static char mnemonic_chars[256];
static char register_chars[256];
static char operand_chars[256];
static char identifier_chars[256];
static char digit_chars[256];

/* Lexical macros.  */
#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
#define is_operand_char(x) (operand_chars[(unsigned char) x])
#define is_register_char(x) (register_chars[(unsigned char) x])
#define is_space_char(x) ((x) == ' ')
#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
#define is_digit_char(x) (digit_chars[(unsigned char) x])

/* All non-digit non-letter characters that may occur in an operand.  */
static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";

/* md_assemble() always leaves the strings it's passed unaltered.  To
   effect this we maintain a stack of saved characters that we've smashed
   with '\0's (indicating end of strings for various sub-fields of the
   assembler instruction).  */
static char save_stack[32];
static char *save_stack_p;
#define END_STRING_AND_SAVE(s) \
        do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
#define RESTORE_END_STRING(s) \
        do { *(s) = *--save_stack_p; } while (0)

/* The instruction we're assembling.  */
static i386_insn i;

/* Possible templates for current insn.  */
static const templates *current_templates;

/* Per instruction expressionS buffers: max displacements & immediates.  */
static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];

/* Current operand we are working on.  */
static int this_operand = -1;

/* We support four different modes.  FLAG_CODE variable is used to distinguish
   these.  */

enum flag_code {
        CODE_32BIT,
        CODE_16BIT,
        CODE_64BIT };

static enum flag_code flag_code;
static unsigned int object_64bit;
static unsigned int disallow_64bit_reloc;
static int use_rela_relocations = 0;

#if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
     || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
     || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))

/* The ELF ABI to use.  */
enum x86_elf_abi
{
  I386_ABI,
  X86_64_ABI,
  X86_64_X32_ABI
};

static enum x86_elf_abi x86_elf_abi = I386_ABI;
#endif

/* The names used to print error messages.  */
static const char *flag_code_names[] =
  {
    "32",
    "16",
    "64"
  };

/* 1 for intel syntax,
   0 if att syntax.  */
static int intel_syntax = 0;

/* 1 for intel mnemonic,
   0 if att mnemonic.  */
static int intel_mnemonic = !SYSV386_COMPAT;

/* 1 if support old (<= 2.8.1) versions of gcc.  */
static int old_gcc = OLDGCC_COMPAT;

/* 1 if pseudo registers are permitted.  */
static int allow_pseudo_reg = 0;

/* 1 if register prefix % not required.  */
static int allow_naked_reg = 0;

/* 1 if pseudo index register, eiz/riz, is allowed .  */
static int allow_index_reg = 0;

static enum
  {
    sse_check_none = 0,
    sse_check_warning,
    sse_check_error
  }
sse_check;

/* Register prefix used for error message.  */
static const char *register_prefix = "%";

/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
   leave, push, and pop instructions so that gcc has the same stack
   frame as in 32 bit mode.  */
static char stackop_size = '\0';

/* Non-zero to optimize code alignment.  */
int optimize_align_code = 1;

/* Non-zero to quieten some warnings.  */
static int quiet_warnings = 0;

/* CPU name.  */
static const char *cpu_arch_name = NULL;
static char *cpu_sub_arch_name = NULL;

/* CPU feature flags.  */
static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;

/* If we have selected a cpu we are generating instructions for.  */
static int cpu_arch_tune_set = 0;

/* Cpu we are generating instructions for.  */
enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;

/* CPU feature flags of cpu we are generating instructions for.  */
static i386_cpu_flags cpu_arch_tune_flags;

/* CPU instruction set architecture used.  */
enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;

/* CPU feature flags of instruction set architecture used.  */
i386_cpu_flags cpu_arch_isa_flags;

/* If set, conditional jumps are not automatically promoted to handle
   larger than a byte offset.  */
static unsigned int no_cond_jump_promotion = 0;

/* Encode SSE instructions with VEX prefix.  */
static unsigned int sse2avx;

/* Encode scalar AVX instructions with specific vector length.  */
static enum
  {
    vex128 = 0,
    vex256
  } avxscalar;

/* Pre-defined "_GLOBAL_OFFSET_TABLE_".  */
static symbolS *GOT_symbol;

/* The dwarf2 return column, adjusted for 32 or 64 bit.  */
unsigned int x86_dwarf2_return_column;

/* The dwarf2 data alignment, adjusted for 32 or 64 bit.  */
int x86_cie_data_alignment;

/* Interface to relax_segment.
   There are 3 major relax states for 386 jump insns because the
   different types of jumps add different sizes to frags when we're
   figuring out what sort of jump to choose to reach a given label.  */

/* Types.  */
#define UNCOND_JUMP 0
#define COND_JUMP 1
#define COND_JUMP86 2

/* Sizes.  */
#define CODE16  1
#define SMALL   0
#define SMALL16 (SMALL | CODE16)
#define BIG     2
#define BIG16   (BIG | CODE16)

#ifndef INLINE
#ifdef __GNUC__
#define INLINE __inline__
#else
#define INLINE
#endif
#endif

#define ENCODE_RELAX_STATE(type, size) \
  ((relax_substateT) (((type) << 2) | (size)))
#define TYPE_FROM_RELAX_STATE(s) \
  ((s) >> 2)
#define DISP_SIZE_FROM_RELAX_STATE(s) \
    ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))

/* This table is used by relax_frag to promote short jumps to long
   ones where necessary.  SMALL (short) jumps may be promoted to BIG
   (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long).  We
   don't allow a short jump in a 32 bit code segment to be promoted to
   a 16 bit offset jump because it's slower (requires data size
   prefix), and doesn't work, unless the destination is in the bottom
   64k of the code segment (The top 16 bits of eip are zeroed).  */

const relax_typeS md_relax_table[] =
{
  /* The fields are:
     1) most positive reach of this state,
     2) most negative reach of this state,
     3) how many bytes this mode will have in the variable part of the frag
     4) which index into the table to try if we can't fit into this one.  */

  /* UNCOND_JUMP states.  */
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
  /* dword jmp adds 4 bytes to frag:
     0 extra opcode bytes, 4 displacement bytes.  */
  {0, 0, 4, 0},
  /* word jmp adds 2 byte2 to frag:
     0 extra opcode bytes, 2 displacement bytes.  */
  {0, 0, 2, 0},

  /* COND_JUMP states.  */
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
  /* dword conditionals adds 5 bytes to frag:
     1 extra opcode byte, 4 displacement bytes.  */
  {0, 0, 5, 0},
  /* word conditionals add 3 bytes to frag:
     1 extra opcode byte, 2 displacement bytes.  */
  {0, 0, 3, 0},

  /* COND_JUMP86 states.  */
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
  {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
  /* dword conditionals adds 5 bytes to frag:
     1 extra opcode byte, 4 displacement bytes.  */
  {0, 0, 5, 0},
  /* word conditionals add 4 bytes to frag:
     1 displacement byte and a 3 byte long branch insn.  */
  {0, 0, 4, 0}
};

static const arch_entry cpu_arch[] =
{
  /* Do not replace the first two entries - i386_target_format()
     relies on them being there in this order.  */
  { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
    CPU_GENERIC32_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
    CPU_GENERIC64_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
    CPU_NONE_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
    CPU_I186_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
    CPU_I286_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
    CPU_I386_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
    CPU_I486_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
    CPU_I586_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
    CPU_I686_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
    CPU_I586_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
    CPU_PENTIUMPRO_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
    CPU_P2_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
    CPU_P3_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
    CPU_P4_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
    CPU_CORE_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
    CPU_NOCONA_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
    CPU_CORE_FLAGS, 1, 0 },
  { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
    CPU_CORE_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
    CPU_CORE2_FLAGS, 1, 0 },
  { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
    CPU_CORE2_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
    CPU_COREI7_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
    CPU_L1OM_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
    CPU_K6_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
    CPU_K6_2_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
    CPU_ATHLON_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
    CPU_K8_FLAGS, 1, 0 },
  { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
    CPU_K8_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
    CPU_K8_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
    CPU_AMDFAM10_FLAGS, 0, 0 },
  { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
    CPU_BDVER1_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
    CPU_8087_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
    CPU_287_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
    CPU_387_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
    CPU_ANY87_FLAGS, 0, 1 },
  { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
    CPU_MMX_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
    CPU_3DNOWA_FLAGS, 0, 1 },
  { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
    CPU_SSE_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
    CPU_SSE2_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
    CPU_SSE3_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
    CPU_SSSE3_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
    CPU_SSE4_1_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
    CPU_SSE4_2_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
    CPU_SSE4_2_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
    CPU_ANY_SSE_FLAGS, 0, 1 },
  { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
    CPU_AVX_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
    CPU_ANY_AVX_FLAGS, 0, 1 },
  { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
    CPU_VMX_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
    CPU_SMX_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
    CPU_XSAVE_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
    CPU_XSAVEOPT_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
    CPU_AES_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
    CPU_PCLMUL_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
    CPU_PCLMUL_FLAGS, 1, 0 },
  { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
    CPU_FSGSBASE_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
    CPU_RDRND_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
    CPU_F16C_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
    CPU_FMA_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
    CPU_FMA4_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
    CPU_XOP_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
    CPU_LWP_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
    CPU_MOVBE_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
    CPU_EPT_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
    CPU_CLFLUSH_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
    CPU_NOP_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
    CPU_SYSCALL_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
    CPU_RDTSCP_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
    CPU_3DNOW_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
    CPU_3DNOWA_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
    CPU_PADLOCK_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
    CPU_SVME_FLAGS, 1, 0 },
  { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
    CPU_SVME_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
    CPU_SSE4A_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
    CPU_ABM_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
    CPU_BMI_FLAGS, 0, 0 },
  { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
    CPU_TBM_FLAGS, 0, 0 },
};

#ifdef I386COFF
/* Like s_lcomm_internal in gas/read.c but the alignment string
   is allowed to be optional.  */

static symbolS *
pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
{
  addressT align = 0;

  SKIP_WHITESPACE ();

  if (needs_align
      && *input_line_pointer == ',')
    {
      align = parse_align (needs_align - 1);

      if (align == (addressT) -1)
        return NULL;
    }
  else
    {
      if (size >= 8)
        align = 3;
      else if (size >= 4)
        align = 2;
      else if (size >= 2)
        align = 1;
      else
        align = 0;
    }

  bss_alloc (symbolP, size, align);
  return symbolP;
}

static void
pe_lcomm (int needs_align)
{
  s_comm_internal (needs_align * 2, pe_lcomm_internal);
}
#endif

const pseudo_typeS md_pseudo_table[] =
{
#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
  {"align", s_align_bytes, 0},
#else
  {"align", s_align_ptwo, 0},
#endif
  {"arch", set_cpu_arch, 0},
#ifndef I386COFF
  {"bss", s_bss, 0},
#else
  {"lcomm", pe_lcomm, 1},
#endif
  {"ffloat", float_cons, 'f'},
  {"dfloat", float_cons, 'd'},
  {"tfloat", float_cons, 'x'},
  {"value", cons, 2},
  {"slong", signed_cons, 4},
  {"noopt", s_ignore, 0},
  {"optim", s_ignore, 0},
  {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
  {"code16", set_code_flag, CODE_16BIT},
  {"code32", set_code_flag, CODE_32BIT},
  {"code64", set_code_flag, CODE_64BIT},
  {"intel_syntax", set_intel_syntax, 1},
  {"att_syntax", set_intel_syntax, 0},
  {"intel_mnemonic", set_intel_mnemonic, 1},
  {"att_mnemonic", set_intel_mnemonic, 0},
  {"allow_index_reg", set_allow_index_reg, 1},
  {"disallow_index_reg", set_allow_index_reg, 0},
  {"sse_check", set_sse_check, 0},
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
  {"largecomm", handle_large_common, 0},
#else
  {"file", (void (*) (int)) dwarf2_directive_file, 0},
  {"loc", dwarf2_directive_loc, 0},
  {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
#endif
#ifdef TE_PE
  {"secrel32", pe_directive_secrel, 0},
#endif
  {0, 0, 0}
};

/* For interface with expression ().  */
extern char *input_line_pointer;

/* Hash table for instruction mnemonic lookup.  */
static struct hash_control *op_hash;

/* Hash table for register lookup.  */
static struct hash_control *reg_hash;
\f
void
i386_align_code (fragS *fragP, int count)
{
  /* Various efficient no-op patterns for aligning code labels.
     Note: Don't try to assemble the instructions in the comments.
     0L and 0w are not legal.  */
  static const char f32_1[] =
    {0x90};                                     /* nop                  */
  static const char f32_2[] =
    {0x66,0x90};                                /* xchg %ax,%ax */
  static const char f32_3[] =
    {0x8d,0x76,0x00};                           /* leal 0(%esi),%esi    */
  static const char f32_4[] =
    {0x8d,0x74,0x26,0x00};                      /* leal 0(%esi,1),%esi  */
  static const char f32_5[] =
    {0x90,                                      /* nop                  */
     0x8d,0x74,0x26,0x00};                      /* leal 0(%esi,1),%esi  */
  static const char f32_6[] =
    {0x8d,0xb6,0x00,0x00,0x00,0x00};            /* leal 0L(%esi),%esi   */
  static const char f32_7[] =
    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
  static const char f32_8[] =
    {0x90,                                      /* nop                  */
     0x8d,0xb4,0x26,0x00,0x00,0x00,0x00};       /* leal 0L(%esi,1),%esi */
  static const char f32_9[] =
    {0x89,0xf6,                                 /* movl %esi,%esi       */
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
  static const char f32_10[] =
    {0x8d,0x76,0x00,                            /* leal 0(%esi),%esi    */
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
  static const char f32_11[] =
    {0x8d,0x74,0x26,0x00,                       /* leal 0(%esi,1),%esi  */
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
  static const char f32_12[] =
    {0x8d,0xb6,0x00,0x00,0x00,0x00,             /* leal 0L(%esi),%esi   */
     0x8d,0xbf,0x00,0x00,0x00,0x00};            /* leal 0L(%edi),%edi   */
  static const char f32_13[] =
    {0x8d,0xb6,0x00,0x00,0x00,0x00,             /* leal 0L(%esi),%esi   */
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
  static const char f32_14[] =
    {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00,        /* leal 0L(%esi,1),%esi */
     0x8d,0xbc,0x27,0x00,0x00,0x00,0x00};       /* leal 0L(%edi,1),%edi */
  static const char f16_3[] =
    {0x8d,0x74,0x00};                           /* lea 0(%esi),%esi     */
  static const char f16_4[] =
    {0x8d,0xb4,0x00,0x00};                      /* lea 0w(%si),%si      */
  static const char f16_5[] =
    {0x90,                                      /* nop                  */
     0x8d,0xb4,0x00,0x00};                      /* lea 0w(%si),%si      */
  static const char f16_6[] =
    {0x89,0xf6,                                 /* mov %si,%si          */
     0x8d,0xbd,0x00,0x00};                      /* lea 0w(%di),%di      */
  static const char f16_7[] =
    {0x8d,0x74,0x00,                            /* lea 0(%si),%si       */
     0x8d,0xbd,0x00,0x00};                      /* lea 0w(%di),%di      */
  static const char f16_8[] =
    {0x8d,0xb4,0x00,0x00,                       /* lea 0w(%si),%si      */
     0x8d,0xbd,0x00,0x00};                      /* lea 0w(%di),%di      */
  static const char jump_31[] =
    {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90,        /* jmp .+31; lotsa nops */
     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
     0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
  static const char *const f32_patt[] = {
    f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
    f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
  };
  static const char *const f16_patt[] = {
    f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
  };
  /* nopl (%[re]ax) */
  static const char alt_3[] =
    {0x0f,0x1f,0x00};
  /* nopl 0(%[re]ax) */
  static const char alt_4[] =
    {0x0f,0x1f,0x40,0x00};
  /* nopl 0(%[re]ax,%[re]ax,1) */
  static const char alt_5[] =
    {0x0f,0x1f,0x44,0x00,0x00};
  /* nopw 0(%[re]ax,%[re]ax,1) */
  static const char alt_6[] =
    {0x66,0x0f,0x1f,0x44,0x00,0x00};
  /* nopl 0L(%[re]ax) */
  static const char alt_7[] =
    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
  /* nopl 0L(%[re]ax,%[re]ax,1) */
  static const char alt_8[] =
    {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* nopw 0L(%[re]ax,%[re]ax,1) */
  static const char alt_9[] =
    {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
  static const char alt_10[] =
    {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* data16
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
  static const char alt_long_11[] =
    {0x66,
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* data16
     data16
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
  static const char alt_long_12[] =
    {0x66,
     0x66,
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* data16
     data16
     data16
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
  static const char alt_long_13[] =
    {0x66,
     0x66,
     0x66,
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* data16
     data16
     data16
     data16
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
  static const char alt_long_14[] =
    {0x66,
     0x66,
     0x66,
     0x66,
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* data16
     data16
     data16
     data16
     data16
     nopw %cs:0L(%[re]ax,%[re]ax,1) */
  static const char alt_long_15[] =
    {0x66,
     0x66,
     0x66,
     0x66,
     0x66,
     0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  /* nopl 0(%[re]ax,%[re]ax,1)
     nopw 0(%[re]ax,%[re]ax,1) */
  static const char alt_short_11[] =
    {0x0f,0x1f,0x44,0x00,0x00,
     0x66,0x0f,0x1f,0x44,0x00,0x00};
  /* nopw 0(%[re]ax,%[re]ax,1)
     nopw 0(%[re]ax,%[re]ax,1) */
  static const char alt_short_12[] =
    {0x66,0x0f,0x1f,0x44,0x00,0x00,
     0x66,0x0f,0x1f,0x44,0x00,0x00};
  /* nopw 0(%[re]ax,%[re]ax,1)
     nopl 0L(%[re]ax) */
  static const char alt_short_13[] =
    {0x66,0x0f,0x1f,0x44,0x00,0x00,
     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
  /* nopl 0L(%[re]ax)
     nopl 0L(%[re]ax) */
  static const char alt_short_14[] =
    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
     0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
  /* nopl 0L(%[re]ax)
     nopl 0L(%[re]ax,%[re]ax,1) */
  static const char alt_short_15[] =
    {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
     0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
  static const char *const alt_short_patt[] = {
    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
    alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
    alt_short_14, alt_short_15
  };
  static const char *const alt_long_patt[] = {
    f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
    alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
    alt_long_14, alt_long_15
  };

  /* Only align for at least a positive non-zero boundary. */
  if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
    return;

  /* We need to decide which NOP sequence to use for 32bit and
     64bit. When -mtune= is used:

     1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
     PROCESSOR_GENERIC32, f32_patt will be used.
     2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
     PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
     PROCESSOR_GENERIC64, alt_long_patt will be used.
     3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
     PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
     will be used.

     When -mtune= isn't used, alt_long_patt will be used if
     cpu_arch_isa_flags has CpuNop.  Otherwise, f32_patt will
     be used.

     When -march= or .arch is used, we can't use anything beyond
     cpu_arch_isa_flags.   */

  if (flag_code == CODE_16BIT)
    {
      if (count > 8)
        {
          memcpy (fragP->fr_literal + fragP->fr_fix,
                  jump_31, count);
          /* Adjust jump offset.  */
          fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
        }
      else
        memcpy (fragP->fr_literal + fragP->fr_fix,
                f16_patt[count - 1], count);
    }
  else
    {
      const char *const *patt = NULL;

      if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
        {
          /* PROCESSOR_UNKNOWN means that all ISAs may be used.  */
          switch (cpu_arch_tune)
            {
            case PROCESSOR_UNKNOWN:
              /* We use cpu_arch_isa_flags to check if we SHOULD
                 optimize with nops.  */
              if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
                patt = alt_long_patt;
              else
                patt = f32_patt;
              break;
            case PROCESSOR_PENTIUM4:
            case PROCESSOR_NOCONA:
            case PROCESSOR_CORE:
            case PROCESSOR_CORE2:
            case PROCESSOR_COREI7:
            case PROCESSOR_L1OM:
            case PROCESSOR_GENERIC64:
              patt = alt_long_patt;
              break;
            case PROCESSOR_K6:
            case PROCESSOR_ATHLON:
            case PROCESSOR_K8:
            case PROCESSOR_AMDFAM10:
            case PROCESSOR_BDVER1:
              patt = alt_short_patt;
              break;
            case PROCESSOR_I386:
            case PROCESSOR_I486:
            case PROCESSOR_PENTIUM:
            case PROCESSOR_PENTIUMPRO:
            case PROCESSOR_GENERIC32:
              patt = f32_patt;
              break;
            }
        }
      else
        {
          switch (fragP->tc_frag_data.tune)
            {
            case PROCESSOR_UNKNOWN:
              /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
                 PROCESSOR_UNKNOWN.  */
              abort ();
              break;

            case PROCESSOR_I386:
            case PROCESSOR_I486:
            case PROCESSOR_PENTIUM:
            case PROCESSOR_K6:
            case PROCESSOR_ATHLON:
            case PROCESSOR_K8:
            case PROCESSOR_AMDFAM10:
            case PROCESSOR_BDVER1:
            case PROCESSOR_GENERIC32:
              /* We use cpu_arch_isa_flags to check if we CAN optimize
                 with nops.  */
              if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
                patt = alt_short_patt;
              else
                patt = f32_patt;
              break;
            case PROCESSOR_PENTIUMPRO:
            case PROCESSOR_PENTIUM4:
            case PROCESSOR_NOCONA:
            case PROCESSOR_CORE:
            case PROCESSOR_CORE2:
            case PROCESSOR_COREI7:
            case PROCESSOR_L1OM:
              if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
                patt = alt_long_patt;
              else
                patt = f32_patt;
              break;
            case PROCESSOR_GENERIC64:
              patt = alt_long_patt;
              break;
            }
        }

      if (patt == f32_patt)
        {
          /* If the padding is less than 15 bytes, we use the normal
             ones.  Otherwise, we use a jump instruction and adjust
             its offset.   */
          int limit;

          /* For 64bit, the limit is 3 bytes.  */
          if (flag_code == CODE_64BIT
              && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
            limit = 3;
          else
            limit = 15;
          if (count < limit)
            memcpy (fragP->fr_literal + fragP->fr_fix,
                    patt[count - 1], count);
          else
            {
              memcpy (fragP->fr_literal + fragP->fr_fix,
                      jump_31, count);
              /* Adjust jump offset.  */
              fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
            }
        }
      else
        {
          /* Maximum length of an instruction is 15 byte.  If the
             padding is greater than 15 bytes and we don't use jump,
             we have to break it into smaller pieces.  */
          int padding = count;
          while (padding > 15)
            {
              padding -= 15;
              memcpy (fragP->fr_literal + fragP->fr_fix + padding,
                      patt [14], 15);
            }

          if (padding)
            memcpy (fragP->fr_literal + fragP->fr_fix,
                    patt [padding - 1], padding);
        }
    }
  fragP->fr_var = count;
}

static INLINE int
operand_type_all_zero (const union i386_operand_type *x)
{
  switch (ARRAY_SIZE(x->array))
    {
    case 3:
      if (x->array[2])
        return 0;
    case 2:
      if (x->array[1])
        return 0;
    case 1:
      return !x->array[0];
    default:
      abort ();
    }
}

static INLINE void
operand_type_set (union i386_operand_type *x, unsigned int v)
{
  switch (ARRAY_SIZE(x->array))
    {
    case 3:
      x->array[2] = v;
    case 2:
      x->array[1] = v;
    case 1:
      x->array[0] = v;
      break;
    default:
      abort ();
    }
}

static INLINE int
operand_type_equal (const union i386_operand_type *x,
                    const union i386_operand_type *y)
{
  switch (ARRAY_SIZE(x->array))
    {
    case 3:
      if (x->array[2] != y->array[2])
        return 0;
    case 2:
      if (x->array[1] != y->array[1])
        return 0;
    case 1:
      return x->array[0] == y->array[0];
      break;
    default:
      abort ();
    }
}

static INLINE int
cpu_flags_all_zero (const union i386_cpu_flags *x)
{
  switch (ARRAY_SIZE(x->array))
    {
    case 3:
      if (x->array[2])
        return 0;
    case 2:
      if (x->array[1])
        return 0;
    case 1:
      return !x->array[0];
    default:
      abort ();
    }
}

static INLINE void
cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
{
  switch (ARRAY_SIZE(x->array))
    {
    case 3:
      x->array[2] = v;
    case 2:
      x->array[1] = v;
    case 1:
      x->array[0] = v;
      break;
    default:
      abort ();
    }
}

static INLINE int
cpu_flags_equal (const union i386_cpu_flags *x,
                 const union i386_cpu_flags *y)
{
  switch (ARRAY_SIZE(x->array))
    {
    case 3:
      if (x->array[2] != y->array[2])
        return 0;
    case 2:
      if (x->array[1] != y->array[1])
        return 0;
    case 1:
      return x->array[0] == y->array[0];
      break;
    default:
      abort ();
    }
}

static INLINE int
cpu_flags_check_cpu64 (i386_cpu_flags f)
{
  return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
           || (flag_code != CODE_64BIT && f.bitfield.cpu64));
}

static INLINE i386_cpu_flags
cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
{
  switch (ARRAY_SIZE (x.array))
    {
    case 3:
      x.array [2] &= y.array [2];
    case 2:
      x.array [1] &= y.array [1];
    case 1:
      x.array [0] &= y.array [0];
      break;
    default:
      abort ();
    }
  return x;
}

static INLINE i386_cpu_flags
cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
{
  switch (ARRAY_SIZE (x.array))
    {
    case 3:
      x.array [2] |= y.array [2];
    case 2:
      x.array [1] |= y.array [1];
    case 1:
      x.array [0] |= y.array [0];
      break;
    default:
      abort ();
    }
  return x;
}

static INLINE i386_cpu_flags
cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
{
  switch (ARRAY_SIZE (x.array))
    {
    case 3:
      x.array [2] &= ~y.array [2];
    case 2:
      x.array [1] &= ~y.array [1];
    case 1:
      x.array [0] &= ~y.array [0];
      break;
    default:
      abort ();
    }
  return x;
}

#define CPU_FLAGS_ARCH_MATCH            0x1
#define CPU_FLAGS_64BIT_MATCH           0x2
#define CPU_FLAGS_AES_MATCH             0x4
#define CPU_FLAGS_PCLMUL_MATCH          0x8
#define CPU_FLAGS_AVX_MATCH            0x10

#define CPU_FLAGS_32BIT_MATCH \
  (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
   | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
#define CPU_FLAGS_PERFECT_MATCH \
  (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)

/* Return CPU flags match bits. */

static int
cpu_flags_match (const insn_template *t)
{
  i386_cpu_flags x = t->cpu_flags;
  int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;

  x.bitfield.cpu64 = 0;
  x.bitfield.cpuno64 = 0;

  if (cpu_flags_all_zero (&x))
    {
      /* This instruction is available on all archs.  */
      match |= CPU_FLAGS_32BIT_MATCH;
    }
  else
    {
      /* This instruction is available only on some archs.  */
      i386_cpu_flags cpu = cpu_arch_flags;

      cpu.bitfield.cpu64 = 0;
      cpu.bitfield.cpuno64 = 0;
      cpu = cpu_flags_and (x, cpu);
      if (!cpu_flags_all_zero (&cpu))
        {
          if (x.bitfield.cpuavx)
            {
              /* We only need to check AES/PCLMUL/SSE2AVX with AVX.  */
              if (cpu.bitfield.cpuavx)
                {
                  /* Check SSE2AVX.  */
                  if (!t->opcode_modifier.sse2avx|| sse2avx)
                    {
                      match |= (CPU_FLAGS_ARCH_MATCH
                                | CPU_FLAGS_AVX_MATCH);
                      /* Check AES.  */
                      if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
                        match |= CPU_FLAGS_AES_MATCH;
                      /* Check PCLMUL.  */
                      if (!x.bitfield.cpupclmul
                          || cpu.bitfield.cpupclmul)
                        match |= CPU_FLAGS_PCLMUL_MATCH;
                    }
                }
              else
                match |= CPU_FLAGS_ARCH_MATCH;
            }
          else
            match |= CPU_FLAGS_32BIT_MATCH;
        }
    }
  return match;
}

static INLINE i386_operand_type
operand_type_and (i386_operand_type x, i386_operand_type y)
{
  switch (ARRAY_SIZE (x.array))
    {
    case 3:
      x.array [2] &= y.array [2];
    case 2:
      x.array [1] &= y.array [1];
    case 1:
      x.array [0] &= y.array [0];
      break;
    default:
      abort ();
    }
  return x;
}

static INLINE i386_operand_type
operand_type_or (i386_operand_type x, i386_operand_type y)
{
  switch (ARRAY_SIZE (x.array))
    {
    case 3:
      x.array [2] |= y.array [2];
    case 2:
      x.array [1] |= y.array [1];
    case 1:
      x.array [0] |= y.array [0];
      break;
    default:
      abort ();
    }
  return x;
}

static INLINE i386_operand_type
operand_type_xor (i386_operand_type x, i386_operand_type y)
{
  switch (ARRAY_SIZE (x.array))
    {
    case 3:
      x.array [2] ^= y.array [2];
    case 2:
      x.array [1] ^= y.array [1];
    case 1:
      x.array [0] ^= y.array [0];
      break;
    default:
      abort ();
    }
  return x;
}

static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
static const i386_operand_type control = OPERAND_TYPE_CONTROL;
static const i386_operand_type inoutportreg
  = OPERAND_TYPE_INOUTPORTREG;
static const i386_operand_type reg16_inoutportreg
  = OPERAND_TYPE_REG16_INOUTPORTREG;
static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
static const i386_operand_type anydisp
  = OPERAND_TYPE_ANYDISP;
static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;

enum operand_type
{
  reg,
  imm,
  disp,
  anymem
};

static INLINE int
operand_type_check (i386_operand_type t, enum operand_type c)
{
  switch (c)
    {
    case reg:
      return (t.bitfield.reg8
              || t.bitfield.reg16
              || t.bitfield.reg32
              || t.bitfield.reg64);

    case imm:
      return (t.bitfield.imm8
              || t.bitfield.imm8s
              || t.bitfield.imm16
              || t.bitfield.imm32
              || t.bitfield.imm32s
              || t.bitfield.imm64);

    case disp:
      return (t.bitfield.disp8
              || t.bitfield.disp16
              || t.bitfield.disp32
              || t.bitfield.disp32s
              || t.bitfield.disp64);

    case anymem:
      return (t.bitfield.disp8
              || t.bitfield.disp16
              || t.bitfield.disp32
              || t.bitfield.disp32s
              || t.bitfield.disp64
              || t.bitfield.baseindex);

    default:
      abort ();
    }

  return 0;
}

/* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
   operand J for instruction template T.  */

static INLINE int
match_reg_size (const insn_template *t, unsigned int j)
{
  return !((i.types[j].bitfield.byte
            && !t->operand_types[j].bitfield.byte)
           || (i.types[j].bitfield.word
               && !t->operand_types[j].bitfield.word)
           || (i.types[j].bitfield.dword
               && !t->operand_types[j].bitfield.dword)
           || (i.types[j].bitfield.qword
               && !t->operand_types[j].bitfield.qword));
}

/* Return 1 if there is no conflict in any size on operand J for
   instruction template T.  */

static INLINE int
match_mem_size (const insn_template *t, unsigned int j)
{
  return (match_reg_size (t, j)
          && !((i.types[j].bitfield.unspecified
                && !t->operand_types[j].bitfield.unspecified)
               || (i.types[j].bitfield.fword
                   && !t->operand_types[j].bitfield.fword)
               || (i.types[j].bitfield.tbyte
                   && !t->operand_types[j].bitfield.tbyte)
               || (i.types[j].bitfield.xmmword
                   && !t->operand_types[j].bitfield.xmmword)
               || (i.types[j].bitfield.ymmword
                   && !t->operand_types[j].bitfield.ymmword)));
}

/* Return 1 if there is no size conflict on any operands for
   instruction template T.  */

static INLINE int
operand_size_match (const insn_template *t)
{
  unsigned int j;
  int match = 1;

  /* Don't check jump instructions.  */
  if (t->opcode_modifier.jump
      || t->opcode_modifier.jumpbyte
      || t->opcode_modifier.jumpdword
      || t->opcode_modifier.jumpintersegment)
    return match;

  /* Check memory and accumulator operand size.  */
  for (j = 0; j < i.operands; j++)
    {
      if (t->operand_types[j].bitfield.anysize)
        continue;

      if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
        {
          match = 0;
          break;
        }

      if (i.types[j].bitfield.mem && !match_mem_size (t, j))
        {
          match = 0;
          break;
        }
    }

  if (match)
    return match;
  else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
    {
mismatch:
      i.error = operand_size_mismatch;
      return 0;
    }

  /* Check reverse.  */
  gas_assert (i.operands == 2);

  match = 1;
  for (j = 0; j < 2; j++)
    {
      if (t->operand_types[j].bitfield.acc
          && !match_reg_size (t, j ? 0 : 1))
        goto mismatch;

      if (i.types[j].bitfield.mem
          && !match_mem_size (t, j ? 0 : 1))
        goto mismatch;
    }

  return match;
}

static INLINE int
operand_type_match (i386_operand_type overlap,
                    i386_operand_type given)
{
  i386_operand_type temp = overlap;

  temp.bitfield.jumpabsolute = 0;
  temp.bitfield.unspecified = 0;
  temp.bitfield.byte = 0;
  temp.bitfield.word = 0;
  temp.bitfield.dword = 0;
  temp.bitfield.fword = 0;
  temp.bitfield.qword = 0;
  temp.bitfield.tbyte = 0;
  temp.bitfield.xmmword = 0;
  temp.bitfield.ymmword = 0;
  if (operand_type_all_zero (&temp))
    goto mismatch;

  if (given.bitfield.baseindex == overlap.bitfield.baseindex
      && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
    return 1;

mismatch:
  i.error = operand_type_mismatch;
  return 0;
}

/* If given types g0 and g1 are registers they must be of the same type
   unless the expected operand type register overlap is null.
   Note that Acc in a template matches every size of reg.  */

static INLINE int
operand_type_register_match (i386_operand_type m0,
                             i386_operand_type g0,
                             i386_operand_type t0,
                             i386_operand_type m1,
                             i386_operand_type g1,
                             i386_operand_type t1)
{
  if (!operand_type_check (g0, reg))
    return 1;

  if (!operand_type_check (g1, reg))
    return 1;

  if (g0.bitfield.reg8 == g1.bitfield.reg8
      && g0.bitfield.reg16 == g1.bitfield.reg16
      && g0.bitfield.reg32 == g1.bitfield.reg32
      && g0.bitfield.reg64 == g1.bitfield.reg64)
    return 1;

  if (m0.bitfield.acc)
    {
      t0.bitfield.reg8 = 1;
      t0.bitfield.reg16 = 1;
      t0.bitfield.reg32 = 1;
      t0.bitfield.reg64 = 1;
    }

  if (m1.bitfield.acc)
    {
      t1.bitfield.reg8 = 1;
      t1.bitfield.reg16 = 1;
      t1.bitfield.reg32 = 1;
      t1.bitfield.reg64 = 1;
    }

  if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
      && !(t0.bitfield.reg16 & t1.bitfield.reg16)
      && !(t0.bitfield.reg32 & t1.bitfield.reg32)
      && !(t0.bitfield.reg64 & t1.bitfield.reg64))
    return 1;

  i.error = register_type_mismatch;

  return 0;
}

static INLINE unsigned int
mode_from_disp_size (i386_operand_type t)
{
  if (t.bitfield.disp8)
    return 1;
  else if (t.bitfield.disp16
           || t.bitfield.disp32
           || t.bitfield.disp32s)
    return 2;
  else
    return 0;
}

static INLINE int
fits_in_signed_byte (offsetT num)
{
  return (num >= -128) && (num <= 127);
}

static INLINE int
fits_in_unsigned_byte (offsetT num)
{
  return (num & 0xff) == num;
}

static INLINE int
fits_in_unsigned_word (offsetT num)
{
  return (num & 0xffff) == num;
}

static INLINE int
fits_in_signed_word (offsetT num)
{
  return (-32768 <= num) && (num <= 32767);
}

static INLINE int
fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
{
#ifndef BFD64
  return 1;
#else
  return (!(((offsetT) -1 << 31) & num)
          || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
#endif
}                               /* fits_in_signed_long() */

static INLINE int
fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
{
#ifndef BFD64
  return 1;
#else
  return (num & (((offsetT) 2 << 31) - 1)) == num;
#endif
}                               /* fits_in_unsigned_long() */

static INLINE int
fits_in_imm4 (offsetT num)
{
  return (num & 0xf) == num;
}

static i386_operand_type
smallest_imm_type (offsetT num)
{
  i386_operand_type t;

  operand_type_set (&t, 0);
  t.bitfield.imm64 = 1;

  if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
    {
      /* This code is disabled on the 486 because all the Imm1 forms
         in the opcode table are slower on the i486.  They're the
         versions with the implicitly specified single-position
         displacement, which has another syntax if you really want to
         use that form.  */
      t.bitfield.imm1 = 1;
      t.bitfield.imm8 = 1;
      t.bitfield.imm8s = 1;
      t.bitfield.imm16 = 1;
      t.bitfield.imm32 = 1;
      t.bitfield.imm32s = 1;
    }
  else if (fits_in_signed_byte (num))
    {
      t.bitfield.imm8 = 1;
      t.bitfield.imm8s = 1;
      t.bitfield.imm16 = 1;
      t.bitfield.imm32 = 1;
      t.bitfield.imm32s = 1;
    }
  else if (fits_in_unsigned_byte (num))
    {
      t.bitfield.imm8 = 1;
      t.bitfield.imm16 = 1;
      t.bitfield.imm32 = 1;
      t.bitfield.imm32s = 1;
    }
  else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
    {
      t.bitfield.imm16 = 1;
      t.bitfield.imm32 = 1;
      t.bitfield.imm32s = 1;
    }
  else if (fits_in_signed_long (num))
    {
      t.bitfield.imm32 = 1;
      t.bitfield.imm32s = 1;
    }
  else if (fits_in_unsigned_long (num))
    t.bitfield.imm32 = 1;

  return t;
}

static offsetT
offset_in_range (offsetT val, int size)
{
  addressT mask;

  switch (size)
    {
    case 1: mask = ((addressT) 1 <<  8) - 1; break;
    case 2: mask = ((addressT) 1 << 16) - 1; break;
    case 4: mask = ((addressT) 2 << 31) - 1; break;
#ifdef BFD64
    case 8: mask = ((addressT) 2 << 63) - 1; break;
#endif
    default: abort ();
    }

#ifdef BFD64
  /* If BFD64, sign extend val for 32bit address mode.  */
  if (flag_code != CODE_64BIT
      || i.prefix[ADDR_PREFIX])
    if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
      val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
#endif

  if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
    {
      char buf1[40], buf2[40];

      sprint_value (buf1, val);
      sprint_value (buf2, val & mask);
      as_warn (_("%s shortened to %s"), buf1, buf2);
    }
  return val & mask;
}

enum PREFIX_GROUP
{
  PREFIX_EXIST = 0,
  PREFIX_LOCK,
  PREFIX_REP,
  PREFIX_OTHER
};

/* Returns
   a. PREFIX_EXIST if attempting to add a prefix where one from the
   same class already exists.
   b. PREFIX_LOCK if lock prefix is added.
   c. PREFIX_REP if rep/repne prefix is added.
   d. PREFIX_OTHER if other prefix is added.
 */

static enum PREFIX_GROUP
add_prefix (unsigned int prefix)
{
  enum PREFIX_GROUP ret = PREFIX_OTHER;
  unsigned int q;

  if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
      && flag_code == CODE_64BIT)
    {
      if ((i.prefix[REX_PREFIX] & prefix & REX_W)
          || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
              && (prefix & (REX_R | REX_X | REX_B))))
        ret = PREFIX_EXIST;
      q = REX_PREFIX;
    }
  else
    {
      switch (prefix)
        {
        default:
          abort ();

        case CS_PREFIX_OPCODE:
        case DS_PREFIX_OPCODE:
        case ES_PREFIX_OPCODE:
        case FS_PREFIX_OPCODE:
        case GS_PREFIX_OPCODE:
        case SS_PREFIX_OPCODE:
          q = SEG_PREFIX;
          break;

        case REPNE_PREFIX_OPCODE:
        case REPE_PREFIX_OPCODE:
          q = REP_PREFIX;
          ret = PREFIX_REP;
          break;

        case LOCK_PREFIX_OPCODE:
          q = LOCK_PREFIX;
          ret = PREFIX_LOCK;
          break;

        case FWAIT_OPCODE:
          q = WAIT_PREFIX;
          break;

        case ADDR_PREFIX_OPCODE:
          q = ADDR_PREFIX;
          break;

        case DATA_PREFIX_OPCODE:
          q = DATA_PREFIX;
          break;
        }
      if (i.prefix[q] != 0)
        ret = PREFIX_EXIST;
    }

  if (ret)
    {
      if (!i.prefix[q])
        ++i.prefixes;
      i.prefix[q] |= prefix;
    }
  else
    as_bad (_("same type of prefix used twice"));

  return ret;
}

static void
update_code_flag (int value, int check)
{
  PRINTF_LIKE ((*as_error));

  flag_code = (enum flag_code) value;
  if (flag_code == CODE_64BIT)
    {
      cpu_arch_flags.bitfield.cpu64 = 1;
      cpu_arch_flags.bitfield.cpuno64 = 0;
    }
  else
    {
      cpu_arch_flags.bitfield.cpu64 = 0;
      cpu_arch_flags.bitfield.cpuno64 = 1;
    }
  if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
    {
      if (check)
        as_error = as_fatal;
      else
        as_error = as_bad;
      (*as_error) (_("64bit mode not supported on `%s'."),
                   cpu_arch_name ? cpu_arch_name : default_arch);
    }
  if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
    {
      if (check)
        as_error = as_fatal;
      else
        as_error = as_bad;
      (*as_error) (_("32bit mode not supported on `%s'."),
                   cpu_arch_name ? cpu_arch_name : default_arch);
    }
  stackop_size = '\0';
}

static void
set_code_flag (int value)
{
  update_code_flag (value, 0);
}

static void
set_16bit_gcc_code_flag (int new_code_flag)
{
  flag_code = (enum flag_code) new_code_flag;
  if (flag_code != CODE_16BIT)
    abort ();
  cpu_arch_flags.bitfield.cpu64 = 0;
  cpu_arch_flags.bitfield.cpuno64 = 1;
  stackop_size = LONG_MNEM_SUFFIX;
}

static void
set_intel_syntax (int syntax_flag)
{
  /* Find out if register prefixing is specified.  */
  int ask_naked_reg = 0;

  SKIP_WHITESPACE ();
  if (!is_end_of_line[(unsigned char) *input_line_pointer])
    {
      char *string = input_line_pointer;
      int e = get_symbol_end ();

      if (strcmp (string, "prefix") == 0)
        ask_naked_reg = 1;
      else if (strcmp (string, "noprefix") == 0)
        ask_naked_reg = -1;
      else
        as_bad (_("bad argument to syntax directive."));
      *input_line_pointer = e;
    }
  demand_empty_rest_of_line ();

  intel_syntax = syntax_flag;

  if (ask_naked_reg == 0)
    allow_naked_reg = (intel_syntax
                       && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
  else
    allow_naked_reg = (ask_naked_reg < 0);

  expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);

  identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
  identifier_chars['$'] = intel_syntax ? '$' : 0;
  register_prefix = allow_naked_reg ? "" : "%";
}

static void
set_intel_mnemonic (int mnemonic_flag)
{
  intel_mnemonic = mnemonic_flag;
}

static void
set_allow_index_reg (int flag)
{
  allow_index_reg = flag;
}

static void
set_sse_check (int dummy ATTRIBUTE_UNUSED)
{
  SKIP_WHITESPACE ();

  if (!is_end_of_line[(unsigned char) *input_line_pointer])
    {
      char *string = input_line_pointer;
      int e = get_symbol_end ();

      if (strcmp (string, "none") == 0)
        sse_check = sse_check_none;
      else if (strcmp (string, "warning") == 0)
        sse_check = sse_check_warning;
      else if (strcmp (string, "error") == 0)
        sse_check = sse_check_error;
      else
        as_bad (_("bad argument to sse_check directive."));
      *input_line_pointer = e;
    }
  else
    as_bad (_("missing argument for sse_check directive"));

  demand_empty_rest_of_line ();
}

static void
check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
                           i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
{
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
  static const char *arch;

  /* Intel LIOM is only supported on ELF.  */
  if (!IS_ELF)
    return;

  if (!arch)
    {
      /* Use cpu_arch_name if it is set in md_parse_option.  Otherwise
         use default_arch.  */
      arch = cpu_arch_name;
      if (!arch)
        arch = default_arch;
    }

  /* If we are targeting Intel L1OM, we must enable it.  */
  if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
      || new_flag.bitfield.cpul1om)
    return;

  as_bad (_("`%s' is not supported on `%s'"), name, arch);
#endif
}

static void
set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
{
  SKIP_WHITESPACE ();

  if (!is_end_of_line[(unsigned char) *input_line_pointer])
    {
      char *string = input_line_pointer;
      int e = get_symbol_end ();
      unsigned int j;
      i386_cpu_flags flags;

      for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
        {
          if (strcmp (string, cpu_arch[j].name) == 0)
            {
              check_cpu_arch_compatible (string, cpu_arch[j].flags);

              if (*string != '.')
                {
                  cpu_arch_name = cpu_arch[j].name;
                  cpu_sub_arch_name = NULL;
                  cpu_arch_flags = cpu_arch[j].flags;
                  if (flag_code == CODE_64BIT)
                    {
                      cpu_arch_flags.bitfield.cpu64 = 1;
                      cpu_arch_flags.bitfield.cpuno64 = 0;
                    }
                  else
                    {
                      cpu_arch_flags.bitfield.cpu64 = 0;
                      cpu_arch_flags.bitfield.cpuno64 = 1;
                    }
                  cpu_arch_isa = cpu_arch[j].type;
                  cpu_arch_isa_flags = cpu_arch[j].flags;
                  if (!cpu_arch_tune_set)
                    {
                      cpu_arch_tune = cpu_arch_isa;
                      cpu_arch_tune_flags = cpu_arch_isa_flags;
                    }
                  break;
                }

              if (!cpu_arch[j].negated)
                flags = cpu_flags_or (cpu_arch_flags,
                                      cpu_arch[j].flags);
              else
                flags = cpu_flags_and_not (cpu_arch_flags,
                                           cpu_arch[j].flags);
              if (!cpu_flags_equal (&flags, &cpu_arch_flags))
                {
                  if (cpu_sub_arch_name)
                    {
                      char *name = cpu_sub_arch_name;
                      cpu_sub_arch_name = concat (name,
                                                  cpu_arch[j].name,
                                                  (const char *) NULL);
                      free (name);
                    }
                  else
                    cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
                  cpu_arch_flags = flags;
                  cpu_arch_isa_flags = flags;
                }
              *input_line_pointer = e;
              demand_empty_rest_of_line ();
              return;
            }
        }
      if (j >= ARRAY_SIZE (cpu_arch))
        as_bad (_("no such architecture: `%s'"), string);

      *input_line_pointer = e;
    }
  else
    as_bad (_("missing cpu architecture"));

  no_cond_jump_promotion = 0;
  if (*input_line_pointer == ','
      && !is_end_of_line[(unsigned char) input_line_pointer[1]])
    {
      char *string = ++input_line_pointer;
      int e = get_symbol_end ();

      if (strcmp (string, "nojumps") == 0)
        no_cond_jump_promotion = 1;
      else if (strcmp (string, "jumps") == 0)
        ;
      else
        as_bad (_("no such architecture modifier: `%s'"), string);

      *input_line_pointer = e;
    }

  demand_empty_rest_of_line ();
}

enum bfd_architecture
i386_arch (void)
{
  if (cpu_arch_isa == PROCESSOR_L1OM)
    {
      if (OUTPUT_FLAVOR != bfd_target_elf_flavour
          || flag_code != CODE_64BIT)
        as_fatal (_("Intel L1OM is 64bit ELF only"));
      return bfd_arch_l1om;
    }
  else
    return bfd_arch_i386;
}

unsigned long
i386_mach ()
{
  if (!strncmp (default_arch, "x86_64", 6))
    {
      if (cpu_arch_isa == PROCESSOR_L1OM)
        {
          if (OUTPUT_FLAVOR != bfd_target_elf_flavour
              || default_arch[6] != '\0')
            as_fatal (_("Intel L1OM is 64bit ELF only"));
          return bfd_mach_l1om;
        }
      else if (default_arch[6] == '\0')
        return bfd_mach_x86_64;
      else
        return bfd_mach_x64_32;
    }
  else if (!strcmp (default_arch, "i386"))
    return bfd_mach_i386_i386;
  else
    as_fatal (_("Unknown architecture"));
}
\f
void
md_begin ()
{
  const char *hash_err;

  /* Initialize op_hash hash table.  */
  op_hash = hash_new ();

  {
    const insn_template *optab;
    templates *core_optab;

    /* Setup for loop.  */
    optab = i386_optab;
    core_optab = (templates *) xmalloc (sizeof (templates));
    core_optab->start = optab;

    while (1)
      {
        ++optab;
        if (optab->name == NULL
            || strcmp (optab->name, (optab - 1)->name) != 0)
          {
            /* different name --> ship out current template list;
               add to hash table; & begin anew.  */
            core_optab->end = optab;
            hash_err = hash_insert (op_hash,
                                    (optab - 1)->name,
                                    (void *) core_optab);
            if (hash_err)
              {
                as_fatal (_("Internal Error:  Can't hash %s: %s"),
                          (optab - 1)->name,
                          hash_err);
              }
            if (optab->name == NULL)
              break;
            core_optab = (templates *) xmalloc (sizeof (templates));
            core_optab->start = optab;
          }
      }
  }

  /* Initialize reg_hash hash table.  */
  reg_hash = hash_new ();
  {
    const reg_entry *regtab;
    unsigned int regtab_size = i386_regtab_size;

    for (regtab = i386_regtab; regtab_size--; regtab++)
      {
        hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
        if (hash_err)
          as_fatal (_("Internal Error:  Can't hash %s: %s"),
                    regtab->reg_name,
                    hash_err);
      }
  }

  /* Fill in lexical tables:  mnemonic_chars, operand_chars.  */
  {
    int c;
    char *p;

    for (c = 0; c < 256; c++)
      {
        if (ISDIGIT (c))
          {
            digit_chars[c] = c;
            mnemonic_chars[c] = c;
            register_chars[c] = c;
            operand_chars[c] = c;
          }
        else if (ISLOWER (c))
          {
            mnemonic_chars[c] = c;
            register_chars[c] = c;
            operand_chars[c] = c;
          }
        else if (ISUPPER (c))
          {
            mnemonic_chars[c] = TOLOWER (c);
            register_chars[c] = mnemonic_chars[c];
            operand_chars[c] = c;
          }

        if (ISALPHA (c) || ISDIGIT (c))
          identifier_chars[c] = c;
        else if (c >= 128)
          {
            identifier_chars[c] = c;
            operand_chars[c] = c;
          }
      }

#ifdef LEX_AT
    identifier_chars['@'] = '@';
#endif
#ifdef LEX_QM
    identifier_chars['?'] = '?';
    operand_chars['?'] = '?';
#endif
    digit_chars['-'] = '-';
    mnemonic_chars['_'] = '_';
    mnemonic_chars['-'] = '-';
    mnemonic_chars['.'] = '.';
    identifier_chars['_'] = '_';
    identifier_chars['.'] = '.';

    for (p = operand_special_chars; *p != '\0'; p++)
      operand_chars[(unsigned char) *p] = *p;
  }

#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
  if (IS_ELF)
    {
      record_alignment (text_section, 2);
      record_alignment (data_section, 2);
      record_alignment (bss_section, 2);
    }
#endif

  if (flag_code == CODE_64BIT)
    {
#if defined (OBJ_COFF) && defined (TE_PE)
      x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
                                  ? 32 : 16);
#else
      x86_dwarf2_return_column = 16;
#endif
      x86_cie_data_alignment = -8;
    }
  else
    {
      x86_dwarf2_return_column = 8;
      x86_cie_data_alignment = -4;
    }
}

void
i386_print_statistics (FILE *file)
{
  hash_print_statistics (file, "i386 opcode", op_hash);
  hash_print_statistics (file, "i386 register", reg_hash);
}
\f
#ifdef DEBUG386

/* Debugging routines for md_assemble.  */
static void pte (insn_template *);
static void pt (i386_operand_type);
static void pe (expressionS *);
static void ps (symbolS *);

static void
pi (char *line, i386_insn *x)
{
  unsigned int j;

  fprintf (stdout, "%s: template ", line);
  pte (&x->tm);
  fprintf (stdout, "  address: base %s  index %s  scale %x\n",
           x->base_reg ? x->base_reg->reg_name : "none",
           x->index_reg ? x->index_reg->reg_name : "none",
           x->log2_scale_factor);
  fprintf (stdout, "  modrm:  mode %x  reg %x  reg/mem %x\n",
           x->rm.mode, x->rm.reg, x->rm.regmem);
  fprintf (stdout, "  sib:  base %x  index %x  scale %x\n",
           x->sib.base, x->sib.index, x->sib.scale);
  fprintf (stdout, "  rex: 64bit %x  extX %x  extY %x  extZ %x\n",
           (x->rex & REX_W) != 0,
           (x->rex & REX_R) != 0,
           (x->rex & REX_X) != 0,
           (x->rex & REX_B) != 0);
  for (j = 0; j < x->operands; j++)
    {
      fprintf (stdout, "    #%d:  ", j + 1);
      pt (x->types[j]);
      fprintf (stdout, "\n");
      if (x->types[j].bitfield.reg8
          || x->types[j].bitfield.reg16
          || x->types[j].bitfield.reg32
          || x->types[j].bitfield.reg64
          || x->types[j].bitfield.regmmx
          || x->types[j].bitfield.regxmm
          || x->types[j].bitfield.regymm
          || x->types[j].bitfield.sreg2
          || x->types[j].bitfield.sreg3
          || x->types[j].bitfield.control
          || x->types[j].bitfield.debug
          || x->types[j].bitfield.test)
        fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
      if (operand_type_check (x->types[j], imm))
        pe (x->op[j].imms);
      if (operand_type_check (x->types[j], disp))
        pe (x->op[j].disps);
    }
}

static void
pte (insn_template *t)
{
  unsigned int j;
  fprintf (stdout, " %d operands ", t->operands);
  fprintf (stdout, "opcode %x ", t->base_opcode);
  if (t->extension_opcode != None)
    fprintf (stdout, "ext %x ", t->extension_opcode);
  if (t->opcode_modifier.d)
    fprintf (stdout, "D");
  if (t->opcode_modifier.w)
    fprintf (stdout, "W");
  fprintf (stdout, "\n");
  for (j = 0; j < t->operands; j++)
    {
      fprintf (stdout, "    #%d type ", j + 1);
      pt (t->operand_types[j]);
      fprintf (stdout, "\n");
    }
}

static void
pe (expressionS *e)
{
  fprintf (stdout, "    operation     %d\n", e->X_op);
  fprintf (stdout, "    add_number    %ld (%lx)\n",
           (long) e->X_add_number, (long) e->X_add_number);
  if (e->X_add_symbol)
    {
      fprintf (stdout, "    add_symbol    ");
      ps (e->X_add_symbol);
      fprintf (stdout, "\n");
    }
  if (e->X_op_symbol)
    {
      fprintf (stdout, "    op_symbol    ");
      ps (e->X_op_symbol);
      fprintf (stdout, "\n");
    }
}

static void
ps (symbolS *s)
{
  fprintf (stdout, "%s type %s%s",
           S_GET_NAME (s),
           S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
           segment_name (S_GET_SEGMENT (s)));
}

static struct type_name
  {
    i386_operand_type mask;
    const char *name;
  }
const type_names[] =
{
  { OPERAND_TYPE_REG8, "r8" },
  { OPERAND_TYPE_REG16, "r16" },
  { OPERAND_TYPE_REG32, "r32" },
  { OPERAND_TYPE_REG64, "r64" },
  { OPERAND_TYPE_IMM8, "i8" },
  { OPERAND_TYPE_IMM8, "i8s" },
  { OPERAND_TYPE_IMM16, "i16" },
  { OPERAND_TYPE_IMM32, "i32" },
  { OPERAND_TYPE_IMM32S, "i32s" },
  { OPERAND_TYPE_IMM64, "i64" },
  { OPERAND_TYPE_IMM1, "i1" },
  { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
  { OPERAND_TYPE_DISP8, "d8" },
  { OPERAND_TYPE_DISP16, "d16" },
  { OPERAND_TYPE_DISP32, "d32" },
  { OPERAND_TYPE_DISP32S, "d32s" },
  { OPERAND_TYPE_DISP64, "d64" },
  { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
  { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
  { OPERAND_TYPE_CONTROL, "control reg" },
  { OPERAND_TYPE_TEST, "test reg" },
  { OPERAND_TYPE_DEBUG, "debug reg" },
  { OPERAND_TYPE_FLOATREG, "FReg" },
  { OPERAND_TYPE_FLOATACC, "FAcc" },
  { OPERAND_TYPE_SREG2, "SReg2" },
  { OPERAND_TYPE_SREG3, "SReg3" },
  { OPERAND_TYPE_ACC, "Acc" },
  { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
  { OPERAND_TYPE_REGMMX, "rMMX" },
  { OPERAND_TYPE_REGXMM, "rXMM" },
  { OPERAND_TYPE_REGYMM, "rYMM" },
  { OPERAND_TYPE_ESSEG, "es" },
};

static void
pt (i386_operand_type t)
{
  unsigned int j;
  i386_operand_type a;

  for (j = 0; j < ARRAY_SIZE (type_names); j++)
    {
      a = operand_type_and (t, type_names[j].mask);
      if (!operand_type_all_zero (&a))
        fprintf (stdout, "%s, ",  type_names[j].name);
    }
  fflush (stdout);
}

#endif /* DEBUG386 */
\f
static bfd_reloc_code_real_type
reloc (unsigned int size,
       int pcrel,
       int sign,
       bfd_reloc_code_real_type other)
{
  if (other != NO_RELOC)
    {
      reloc_howto_type *rel;

      if (size == 8)
        switch (other)
          {
          case BFD_RELOC_X86_64_GOT32:
            return BFD_RELOC_X86_64_GOT64;
            break;
          case BFD_RELOC_X86_64_PLTOFF64:
            return BFD_RELOC_X86_64_PLTOFF64;
            break;
          case BFD_RELOC_X86_64_GOTPC32:
            other = BFD_RELOC_X86_64_GOTPC64;
            break;
          case BFD_RELOC_X86_64_GOTPCREL:
            other = BFD_RELOC_X86_64_GOTPCREL64;
            break;
          case BFD_RELOC_X86_64_TPOFF32:
            other = BFD_RELOC_X86_64_TPOFF64;
            break;
          case BFD_RELOC_X86_64_DTPOFF32:
            other = BFD_RELOC_X86_64_DTPOFF64;
            break;
          default:
            break;
          }

      /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless.  */
      if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
        sign = -1;

      rel = bfd_reloc_type_lookup (stdoutput, other);
      if (!rel)
        as_bad (_("unknown relocation (%u)"), other);
      else if (size != bfd_get_reloc_size (rel))
        as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
                bfd_get_reloc_size (rel),
                size);
      else if (pcrel && !rel->pc_relative)
        as_bad (_("non-pc-relative relocation for pc-relative field"));
      else if ((rel->complain_on_overflow == complain_overflow_signed
                && !sign)
               || (rel->complain_on_overflow == complain_overflow_unsigned
                   && sign > 0))
        as_bad (_("relocated field and relocation type differ in signedness"));
      else
        return other;
      return NO_RELOC;
    }

  if (pcrel)
    {
      if (!sign)
        as_bad (_("there are no unsigned pc-relative relocations"));
      switch (size)
        {
        case 1: return BFD_RELOC_8_PCREL;
        case 2: return BFD_RELOC_16_PCREL;
        case 4: return BFD_RELOC_32_PCREL;
        case 8: return BFD_RELOC_64_PCREL;
        }
      as_bad (_("cannot do %u byte pc-relative relocation"), size);
    }
  else
    {
      if (sign > 0)
        switch (size)
          {
          case 4: return BFD_RELOC_X86_64_32S;
          }
      else
        switch (size)
          {
          case 1: return BFD_RELOC_8;
          case 2: return BFD_RELOC_16;
          case 4: return BFD_RELOC_32;
          case 8: return BFD_RELOC_64;
          }
      as_bad (_("cannot do %s %u byte relocation"),
              sign > 0 ? "signed" : "unsigned", size);
    }

  return NO_RELOC;
}

/* Here we decide which fixups can be adjusted to make them relative to
   the beginning of the section instead of the symbol.  Basically we need
   to make sure that the dynamic relocations are done correctly, so in
   some cases we force the original symbol to be used.  */

int
tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
{
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
  if (!IS_ELF)
    return 1;

  /* Don't adjust pc-relative references to merge sections in 64-bit
     mode.  */
  if (use_rela_relocations
      && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
      && fixP->fx_pcrel)
    return 0;

  /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
     and changed later by validate_fix.  */
  if (GOT_symbol && fixP->fx_subsy == GOT_symbol
      && fixP->fx_r_type == BFD_RELOC_32_PCREL)
    return 0;

  /* adjust_reloc_syms doesn't know about the GOT.  */
  if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
      || fixP->fx_r_type == BFD_RELOC_386_PLT32
      || fixP->fx_r_type == BFD_RELOC_386_GOT32
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
      || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
      || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
      || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
      || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
      || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
      || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
      || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
      || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
      || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
      || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
      || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
    return 0;
#endif
  return 1;
}

static int
intel_float_operand (const char *mnemonic)
{
  /* Note that the value returned is meaningful only for opcodes with (memory)
     operands, hence the code here is free to improperly handle opcodes that
     have no operands (for better performance and smaller code). */

  if (mnemonic[0] != 'f')
    return 0; /* non-math */

  switch (mnemonic[1])
    {
    /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
       the fs segment override prefix not currently handled because no
       call path can make opcodes without operands get here */
    case 'i':
      return 2 /* integer op */;
    case 'l':
      if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
        return 3; /* fldcw/fldenv */
      break;
    case 'n':
      if (mnemonic[2] != 'o' /* fnop */)
        return 3; /* non-waiting control op */
      break;
    case 'r':
      if (mnemonic[2] == 's')
        return 3; /* frstor/frstpm */
      break;
    case 's':
      if (mnemonic[2] == 'a')
        return 3; /* fsave */
      if (mnemonic[2] == 't')
        {
          switch (mnemonic[3])
            {
            case 'c': /* fstcw */
            case 'd': /* fstdw */
            case 'e': /* fstenv */
            case 's': /* fsts[gw] */
              return 3;
            }
        }
      break;
    case 'x':
      if (mnemonic[2] == 'r' || mnemonic[2] == 's')
        return 0; /* fxsave/fxrstor are not really math ops */
      break;
    }

  return 1;
}

/* Build the VEX prefix.  */

static void
build_vex_prefix (const insn_template *t)
{
  unsigned int register_specifier;
  unsigned int implied_prefix;
  unsigned int vector_length;

  /* Check register specifier.  */
  if (i.vex.register_specifier)
    {
      register_specifier = i.vex.register_specifier->reg_num;
      if ((i.vex.register_specifier->reg_flags & RegRex))
        register_specifier += 8;
      register_specifier = ~register_specifier & 0xf;
    }
  else
    register_specifier = 0xf;

  /* Use 2-byte VEX prefix by swappping destination and source
     operand.  */
  if (!i.swap_operand
      && i.operands == i.reg_operands
      && i.tm.opcode_modifier.vexopcode == VEX0F
      && i.tm.opcode_modifier.s
      && i.rex == REX_B)
    {
      unsigned int xchg = i.operands - 1;
      union i386_op temp_op;
      i386_operand_type temp_type;

      temp_type = i.types[xchg];
      i.types[xchg] = i.types[0];
      i.types[0] = temp_type;
      temp_op = i.op[xchg];
      i.op[xchg] = i.op[0];
      i.op[0] = temp_op;

      gas_assert (i.rm.mode == 3);

      i.rex = REX_R;
      xchg = i.rm.regmem;
      i.rm.regmem = i.rm.reg;
      i.rm.reg = xchg;

      /* Use the next insn.  */
      i.tm = t[1];
    }

  if (i.tm.opcode_modifier.vex == VEXScalar)
    vector_length = avxscalar;
  else
    vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;

  switch ((i.tm.base_opcode >> 8) & 0xff)
    {
    case 0:
      implied_prefix = 0;
      break;
    case DATA_PREFIX_OPCODE:
      implied_prefix = 1;
      break;
    case REPE_PREFIX_OPCODE:
      implied_prefix = 2;
      break;
    case REPNE_PREFIX_OPCODE:
      implied_prefix = 3;
      break;
    default:
      abort ();
    }

  /* Use 2-byte VEX prefix if possible.  */
  if (i.tm.opcode_modifier.vexopcode == VEX0F
      && i.tm.opcode_modifier.vexw != VEXW1
      && (i.rex & (REX_W | REX_X | REX_B)) == 0)
    {
      /* 2-byte VEX prefix.  */
      unsigned int r;

      i.vex.length = 2;
      i.vex.bytes[0] = 0xc5;

      /* Check the REX.R bit.  */
      r = (i.rex & REX_R) ? 0 : 1;
      i.vex.bytes[1] = (r << 7
                        | register_specifier << 3
                        | vector_length << 2
                        | implied_prefix);
    }
  else
    {
      /* 3-byte VEX prefix.  */
      unsigned int m, w;

      i.vex.length = 3;

      switch (i.tm.opcode_modifier.vexopcode)
        {
        case VEX0F:
          m = 0x1;
          i.vex.bytes[0] = 0xc4;
          break;
        case VEX0F38:
          m = 0x2;
          i.vex.bytes[0] = 0xc4;
          break;
        case VEX0F3A:
          m = 0x3;
          i.vex.bytes[0] = 0xc4;
          break;
        case XOP08:
          m = 0x8;
          i.vex.bytes[0] = 0x8f;
          break;
        case XOP09:
          m = 0x9;
          i.vex.bytes[0] = 0x8f;
          break;
        case XOP0A:
          m = 0xa;
          i.vex.bytes[0] = 0x8f;
          break;
        default:
          abort ();
        }

      /* The high 3 bits of the second VEX byte are 1's compliment
         of RXB bits from REX.  */
      i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;

      /* Check the REX.W bit.  */
      w = (i.rex & REX_W) ? 1 : 0;
      if (i.tm.opcode_modifier.vexw)
        {
          if (w)
            abort ();

          if (i.tm.opcode_modifier.vexw == VEXW1)
            w = 1;
        }

      i.vex.bytes[2] = (w << 7
                        | register_specifier << 3
                        | vector_length << 2
                        | implied_prefix);
    }
}

static void
process_immext (void)
{
  expressionS *exp;

  if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
    {
      /* SSE3 Instructions have the fixed operands with an opcode
         suffix which is coded in the same place as an 8-bit immediate
         field would be.  Here we check those operands and remove them
         afterwards.  */
      unsigned int x;

      for (x = 0; x < i.operands; x++)
        if (i.op[x].regs->reg_num != x)
          as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
                  register_prefix, i.op[x].regs->reg_name, x + 1,
                  i.tm.name);

      i.operands = 0;
    }

  /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
     which is coded in the same place as an 8-bit immediate field
     would be.  Here we fake an 8-bit immediate operand from the
     opcode suffix stored in tm.extension_opcode.

     AVX instructions also use this encoding, for some of
     3 argument instructions.  */

  gas_assert (i.imm_operands == 0
              && (i.operands <= 2
                  || (i.tm.opcode_modifier.vex
                      && i.operands <= 4)));

  exp = &im_expressions[i.imm_operands++];
  i.op[i.operands].imms = exp;
  i.types[i.operands] = imm8;
  i.operands++;
  exp->X_op = O_constant;
  exp->X_add_number = i.tm.extension_opcode;
  i.tm.extension_opcode = None;
}

/* This is the guts of the machine-dependent assembler.  LINE points to a
   machine dependent instruction.  This function is supposed to emit
   the frags/bytes it assembles to.  */

void
md_assemble (char *line)
{
  unsigned int j;
  char mnemonic[MAX_MNEM_SIZE];
  const insn_template *t;

  /* Initialize globals.  */
  memset (&i, '\0', sizeof (i));
  for (j = 0; j < MAX_OPERANDS; j++)
    i.reloc[j] = NO_RELOC;
  memset (disp_expressions, '\0', sizeof (disp_expressions));
  memset (im_expressions, '\0', sizeof (im_expressions));
  save_stack_p = save_stack;

  /* First parse an instruction mnemonic & call i386_operand for the operands.
     We assume that the scrubber has arranged it so that line[0] is the valid
     start of a (possibly prefixed) mnemonic.  */

  line = parse_insn (line, mnemonic);
  if (line == NULL)
    return;

  line = parse_operands (line, mnemonic);
  this_operand = -1;
  if (line == NULL)
    return;

  /* Now we've parsed the mnemonic into a set of templates, and have the
     operands at hand.  */

  /* All intel opcodes have reversed operands except for "bound" and
     "enter".  We also don't reverse intersegment "jmp" and "call"
     instructions with 2 immediate operands so that the immediate segment
     precedes the offset, as it does when in AT&T mode. */
  if (intel_syntax
      && i.operands > 1
      && (strcmp (mnemonic, "bound") != 0)
      && (strcmp (mnemonic, "invlpga") != 0)
      && !(operand_type_check (i.types[0], imm)
           && operand_type_check (i.types[1], imm)))
    swap_operands ();

  /* The order of the immediates should be reversed
     for 2 immediates extrq and insertq instructions */
  if (i.imm_operands == 2
      && (strcmp (mnemonic, "extrq") == 0
          || strcmp (mnemonic, "insertq") == 0))
      swap_2_operands (0, 1);

  if (i.imm_operands)
    optimize_imm ();

  /* Don't optimize displacement for movabs since it only takes 64bit
     displacement.  */
  if (i.disp_operands
      && !i.disp32_encoding
      && (flag_code != CODE_64BIT
          || strcmp (mnemonic, "movabs") != 0))
    optimize_disp ();

  /* Next, we find a template that matches the given insn,
     making sure the overlap of the given operands types is consistent
     with the template operand types.  */

  if (!(t = match_template ()))
    return;

  if (sse_check != sse_check_none
      && !i.tm.opcode_modifier.noavx
      && (i.tm.cpu_flags.bitfield.cpusse
          || i.tm.cpu_flags.bitfield.cpusse2
          || i.tm.cpu_flags.bitfield.cpusse3
          || i.tm.cpu_flags.bitfield.cpussse3
          || i.tm.cpu_flags.bitfield.cpusse4_1
          || i.tm.cpu_flags.bitfield.cpusse4_2))
    {
      (sse_check == sse_check_warning
       ? as_warn
       : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
    }

  /* Zap movzx and movsx suffix.  The suffix has been set from
     "word ptr" or "byte ptr" on the source operand in Intel syntax
     or extracted from mnemonic in AT&T syntax.  But we'll use
     the destination register to choose the suffix for encoding.  */
  if ((i.tm.base_opcode & ~9) == 0x0fb6)
    {
      /* In Intel syntax, there must be a suffix.  In AT&T syntax, if
         there is no suffix, the default will be byte extension.  */
      if (i.reg_operands != 2
          && !i.suffix
          && intel_syntax)
        as_bad (_("ambiguous operand size for `%s'"), i.tm.name);

      i.suffix = 0;
    }

  if (i.tm.opcode_modifier.fwait)
    if (!add_prefix (FWAIT_OPCODE))
      return;

  /* Check for lock without a lockable instruction.  Destination operand
     must be memory unless it is xchg (0x86).  */
  if (i.prefix[LOCK_PREFIX]
      && (!i.tm.opcode_modifier.islockable
          || i.mem_operands == 0
          || (i.tm.base_opcode != 0x86
              && !operand_type_check (i.types[i.operands - 1], anymem))))
    {
      as_bad (_("expecting lockable instruction after `lock'"));
      return;
    }

  /* Check string instruction segment overrides.  */
  if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
    {
      if (!check_string ())
        return;
      i.disp_operands = 0;
    }

  if (!process_suffix ())
    return;

  /* Update operand types.  */
  for (j = 0; j < i.operands; j++)
    i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);

  /* Make still unresolved immediate matches conform to size of immediate
     given in i.suffix.  */
  if (!finalize_imm ())
    return;

  if (i.types[0].bitfield.imm1)
    i.imm_operands = 0; /* kludge for shift insns.  */

  /* We only need to check those implicit registers for instructions
     with 3 operands or less.  */
  if (i.operands <= 3)
    for (j = 0; j < i.operands; j++)
      if (i.types[j].bitfield.inoutportreg
          || i.types[j].bitfield.shiftcount
          || i.types[j].bitfield.acc
          || i.types[j].bitfield.floatacc)
        i.reg_operands--;

  /* ImmExt should be processed after SSE2AVX.  */
  if (!i.tm.opcode_modifier.sse2avx
      && i.tm.opcode_modifier.immext)
    process_immext ();

  /* For insns with operands there are more diddles to do to the opcode.  */
  if (i.operands)
    {
      if (!process_operands ())
        return;
    }
  else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
    {
      /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc.  */
      as_warn (_("translating to `%sp'"), i.tm.name);
    }

  if (i.tm.opcode_modifier.vex)
    build_vex_prefix (t);

  /* Handle conversion of 'int $3' --> special int3 insn.  XOP or FMA4
     instructions may define INT_OPCODE as well, so avoid this corner
     case for those instructions that use MODRM.  */
  if (i.tm.base_opcode == INT_OPCODE
      && !i.tm.opcode_modifier.modrm
      && i.op[0].imms->X_add_number == 3)
    {
      i.tm.base_opcode = INT3_OPCODE;
      i.imm_operands = 0;
    }

  if ((i.tm.opcode_modifier.jump
       || i.tm.opcode_modifier.jumpbyte
       || i.tm.opcode_modifier.jumpdword)
      && i.op[0].disps->X_op == O_constant)
    {
      /* Convert "jmp constant" (and "call constant") to a jump (call) to
         the absolute address given by the constant.  Since ix86 jumps and
         calls are pc relative, we need to generate a reloc.  */
      i.op[0].disps->X_add_symbol = &abs_symbol;
      i.op[0].disps->X_op = O_symbol;
    }

  if (i.tm.opcode_modifier.rex64)
    i.rex |= REX_W;

  /* For 8 bit registers we need an empty rex prefix.  Also if the
     instruction already has a prefix, we need to convert old
     registers to new ones.  */

  if ((i.types[0].bitfield.reg8
       && (i.op[0].regs->reg_flags & RegRex64) != 0)
      || (i.types[1].bitfield.reg8
          && (i.op[1].regs->reg_flags & RegRex64) != 0)
      || ((i.types[0].bitfield.reg8
           || i.types[1].bitfield.reg8)
          && i.rex != 0))
    {
      int x;

      i.rex |= REX_OPCODE;
      for (x = 0; x < 2; x++)
        {
          /* Look for 8 bit operand that uses old registers.  */
          if (i.types[x].bitfield.reg8
              && (i.op[x].regs->reg_flags & RegRex64) == 0)
            {
              /* In case it is "hi" register, give up.  */
              if (i.op[x].regs->reg_num > 3)
                as_bad (_("can't encode register '%s%s' in an "
                          "instruction requiring REX prefix."),
                        register_prefix, i.op[x].regs->reg_name);

              /* Otherwise it is equivalent to the extended register.
                 Since the encoding doesn't change this is merely
                 cosmetic cleanup for debug output.  */

              i.op[x].regs = i.op[x].regs + 8;
            }
        }
    }

  if (i.rex != 0)
    add_prefix (REX_OPCODE | i.rex);

  /* We are ready to output the insn.  */
  output_insn ();
}

static char *
parse_insn (char *line, char *mnemonic)
{
  char *l = line;
  char *token_start = l;
  char *mnem_p;
  int supported;
  const insn_template *t;
  char *dot_p = NULL;

  /* Non-zero if we found a prefix only acceptable with string insns.  */
  const char *expecting_string_instruction = NULL;

  while (1)
    {
      mnem_p = mnemonic;
      while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
        {
          if (*mnem_p == '.')
            dot_p = mnem_p;
          mnem_p++;
          if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
            {
              as_bad (_("no such instruction: `%s'"), token_start);
              return NULL;
            }
          l++;
        }
      if (!is_space_char (*l)
          && *l != END_OF_INSN
          && (intel_syntax
              || (*l != PREFIX_SEPARATOR
                  && *l != ',')))
        {
          as_bad (_("invalid character %s in mnemonic"),
                  output_invalid (*l));
          return NULL;
        }
      if (token_start == l)
        {
          if (!intel_syntax && *l == PREFIX_SEPARATOR)
            as_bad (_("expecting prefix; got nothing"));
          else
            as_bad (_("expecting mnemonic; got nothing"));
          return NULL;
        }

      /* Look up instruction (or prefix) via hash table.  */
      current_templates = (const templates *) hash_find (op_hash, mnemonic);

      if (*l != END_OF_INSN
          && (!is_space_char (*l) || l[1] != END_OF_INSN)
          && current_templates
          && current_templates->start->opcode_modifier.isprefix)
        {
          if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
            {
              as_bad ((flag_code != CODE_64BIT
                       ? _("`%s' is only supported in 64-bit mode")
                       : _("`%s' is not supported in 64-bit mode")),
                      current_templates->start->name);
              return NULL;
            }
          /* If we are in 16-bit mode, do not allow addr16 or data16.
             Similarly, in 32-bit mode, do not allow addr32 or data32.  */
          if ((current_templates->start->opcode_modifier.size16
               || current_templates->start->opcode_modifier.size32)
              && flag_code != CODE_64BIT
              && (current_templates->start->opcode_modifier.size32
                  ^ (flag_code == CODE_16BIT)))
            {
              as_bad (_("redundant %s prefix"),
                      current_templates->start->name);
              return NULL;
            }
          /* Add prefix, checking for repeated prefixes.  */
          switch (add_prefix (current_templates->start->base_opcode))
            {
            case PREFIX_EXIST:
              return NULL;
            case PREFIX_REP:
              expecting_string_instruction = current_templates->start->name;
              break;
            default:
              break;
            }
          /* Skip past PREFIX_SEPARATOR and reset token_start.  */
          token_start = ++l;
        }
      else
        break;
    }

  if (!current_templates)
    {
      /* Check if we should swap operand or force 32bit displacement in
         encoding.  */
      if (mnem_p - 2 == dot_p && dot_p[1] == 's')
        i.swap_operand = 1;
      else if (mnem_p - 4 == dot_p 
               && dot_p[1] == 'd'
               && dot_p[2] == '3'
               && dot_p[3] == '2')
        i.disp32_encoding = 1;
      else
        goto check_suffix;
      mnem_p = dot_p;
      *dot_p = '\0';
      current_templates = (const templates *) hash_find (op_hash, mnemonic);
    }

  if (!current_templates)
    {
check_suffix:
      /* See if we can get a match by trimming off a suffix.  */
      switch (mnem_p[-1])
        {
        case WORD_MNEM_SUFFIX:
          if (intel_syntax && (intel_float_operand (mnemonic) & 2))
            i.suffix = SHORT_MNEM_SUFFIX;
          else
        case BYTE_MNEM_SUFFIX:
        case QWORD_MNEM_SUFFIX:
          i.suffix = mnem_p[-1];
          mnem_p[-1] = '\0';
          current_templates = (const templates *) hash_find (op_hash,
                                                             mnemonic);
          break;
        case SHORT_MNEM_SUFFIX:
        case LONG_MNEM_SUFFIX:
          if (!intel_syntax)
            {
              i.suffix = mnem_p[-1];
              mnem_p[-1] = '\0';
              current_templates = (const templates *) hash_find (op_hash,
                                                                 mnemonic);
            }
          break;

          /* Intel Syntax.  */
        case 'd':
          if (intel_syntax)
            {
              if (intel_float_operand (mnemonic) == 1)
                i.suffix = SHORT_MNEM_SUFFIX;
              else
                i.suffix = LONG_MNEM_SUFFIX;
              mnem_p[-1] = '\0';
              current_templates = (const templates *) hash_find (op_hash,
                                                                 mnemonic);
            }
          break;
        }
      if (!current_templates)
        {
          as_bad (_("no such instruction: `%s'"), token_start);
          return NULL;
        }
    }

  if (current_templates->start->opcode_modifier.jump
      || current_templates->start->opcode_modifier.jumpbyte)
    {
      /* Check for a branch hint.  We allow ",pt" and ",pn" for
         predict taken and predict not taken respectively.
         I'm not sure that branch hints actually do anything on loop
         and jcxz insns (JumpByte) for current Pentium4 chips.  They
         may work in the future and it doesn't hurt to accept them
         now.  */
      if (l[0] == ',' && l[1] == 'p')
        {
          if (l[2] == 't')
            {
              if (!add_prefix (DS_PREFIX_OPCODE))
                return NULL;
              l += 3;
            }
          else if (l[2] == 'n')
            {
              if (!add_prefix (CS_PREFIX_OPCODE))
                return NULL;
              l += 3;
            }
        }
    }
  /* Any other comma loses.  */
  if (*l == ',')
    {
      as_bad (_("invalid character %s in mnemonic"),
              output_invalid (*l));
      return NULL;
    }

  /* Check if instruction is supported on specified architecture.  */
  supported = 0;
  for (t = current_templates->start; t < current_templates->end; ++t)
    {
      supported |= cpu_flags_match (t);
      if (supported == CPU_FLAGS_PERFECT_MATCH)
        goto skip;
    }

  if (!(supported & CPU_FLAGS_64BIT_MATCH))
    {
      as_bad (flag_code == CODE_64BIT
              ? _("`%s' is not supported in 64-bit mode")
              : _("`%s' is only supported in 64-bit mode"),
              current_templates->start->name);
      return NULL;
    }
  if (supported != CPU_FLAGS_PERFECT_MATCH)
    {
      as_bad (_("`%s' is not supported on `%s%s'"),
              current_templates->start->name,
              cpu_arch_name ? cpu_arch_name : default_arch,
              cpu_sub_arch_name ? cpu_sub_arch_name : "");
      return NULL;
    }

skip:
  if (!cpu_arch_flags.bitfield.cpui386
           && (flag_code != CODE_16BIT))
    {
      as_warn (_("use .code16 to ensure correct addressing mode"));
    }

  /* Check for rep/repne without a string instruction.  */
  if (expecting_string_instruction)
    {
      static templates override;

      for (t = current_templates->start; t < current_templates->end; ++t)
        if (t->opcode_modifier.isstring)
          break;
      if (t >= current_templates->end)
        {
          as_bad (_("expecting string instruction after `%s'"),
                  expecting_string_instruction);
          return NULL;
        }
      for (override.start = t; t < current_templates->end; ++t)
        if (!t->opcode_modifier.isstring)
          break;
      override.end = t;
      current_templates = &override;
    }

  return l;
}

static char *
parse_operands (char *l, const char *mnemonic)
{
  char *token_start;

  /* 1 if operand is pending after ','.  */
  unsigned int expecting_operand = 0;

  /* Non-zero if operand parens not balanced.  */
  unsigned int paren_not_balanced;

  while (*l != END_OF_INSN)
    {
      /* Skip optional white space before operand.  */
      if (is_space_char (*l))
        ++l;
      if (!is_operand_char (*l) && *l != END_OF_INSN)
        {
          as_bad (_("invalid character %s before operand %d"),
                  output_invalid (*l),
                  i.operands + 1);
          return NULL;
        }
      token_start = l;  /* after white space */
      paren_not_balanced = 0;
      while (paren_not_balanced || *l != ',')
        {
          if (*l == END_OF_INSN)
            {
              if (paren_not_balanced)
                {
                  if (!intel_syntax)
                    as_bad (_("unbalanced parenthesis in operand %d."),
                            i.operands + 1);
                  else
                    as_bad (_("unbalanced brackets in operand %d."),
                            i.operands + 1);
                  return NULL;
                }
              else
                break;  /* we are done */
            }
          else if (!is_operand_char (*l) && !is_space_char (*l))
            {
              as_bad (_("invalid character %s in operand %d"),
                      output_invalid (*l),
                      i.operands + 1);
              return NULL;
            }
          if (!intel_syntax)
            {
              if (*l == '(')
                ++paren_not_balanced;
              if (*l == ')')
                --paren_not_balanced;
            }
          else
            {
              if (*l == '[')
                ++paren_not_balanced;
              if (*l == ']')
                --paren_not_balanced;
            }
          l++;
        }
      if (l != token_start)
        {                       /* Yes, we've read in another operand.  */
          unsigned int operand_ok;
          this_operand = i.operands++;
          i.types[this_operand].bitfield.unspecified = 1;
          if (i.operands > MAX_OPERANDS)
            {
              as_bad (_("spurious operands; (%d operands/instruction max)"),
                      MAX_OPERANDS);
              return NULL;
            }
          /* Now parse operand adding info to 'i' as we go along.  */
          END_STRING_AND_SAVE (l);

          if (intel_syntax)
            operand_ok =
              i386_intel_operand (token_start,
                                  intel_float_operand (mnemonic));
          else
            operand_ok = i386_att_operand (token_start);

          RESTORE_END_STRING (l);
          if (!operand_ok)
            return NULL;
        }
      else
        {
          if (expecting_operand)
            {
            expecting_operand_after_comma:
              as_bad (_("expecting operand after ','; got nothing"));
              return NULL;
            }
          if (*l == ',')
            {
              as_bad (_("expecting operand before ','; got nothing"));
              return NULL;
            }
        }

      /* Now *l must be either ',' or END_OF_INSN.  */
      if (*l == ',')
        {
          if (*++l == END_OF_INSN)
            {
              /* Just skip it, if it's \n complain.  */
              goto expecting_operand_after_comma;
            }
          expecting_operand = 1;
        }
    }
  return l;
}

static void
swap_2_operands (int xchg1, int xchg2)
{
  union i386_op temp_op;
  i386_operand_type temp_type;
  enum bfd_reloc_code_real temp_reloc;

  temp_type = i.types[xchg2];
  i.types[xchg2] = i.types[xchg1];
  i.types[xchg1] = temp_type;
  temp_op = i.op[xchg2];
  i.op[xchg2] = i.op[xchg1];
  i.op[xchg1] = temp_op;
  temp_reloc = i.reloc[xchg2];
  i.reloc[xchg2] = i.reloc[xchg1];
  i.reloc[xchg1] = temp_reloc;
}

static void
swap_operands (void)
{
  switch (i.operands)
    {
    case 5:
    case 4:
      swap_2_operands (1, i.operands - 2);
    case 3:
    case 2:
      swap_2_operands (0, i.operands - 1);
      break;
    default:
      abort ();
    }

  if (i.mem_operands == 2)
    {
      const seg_entry *temp_seg;
      temp_seg = i.seg[0];
      i.seg[0] = i.seg[1];
      i.seg[1] = temp_seg;
    }
}

/* Try to ensure constant immediates are represented in the smallest
   opcode possible.  */
static void
optimize_imm (void)
{
  char guess_suffix = 0;
  int op;

  if (i.suffix)
    guess_suffix = i.suffix;
  else if (i.reg_operands)
    {
      /* Figure out a suffix from the last register operand specified.
         We can't do this properly yet, ie. excluding InOutPortReg,
         but the following works for instructions with immediates.
         In any case, we can't set i.suffix yet.  */
      for (op = i.operands; --op >= 0;)
        if (i.types[op].bitfield.reg8)
          {
            guess_suffix = BYTE_MNEM_SUFFIX;
            break;
          }
        else if (i.types[op].bitfield.reg16)
          {
            guess_suffix = WORD_MNEM_SUFFIX;
            break;
          }
        else if (i.types[op].bitfield.reg32)
          {
            guess_suffix = LONG_MNEM_SUFFIX;
            break;
          }
        else if (i.types[op].bitfield.reg64)
          {
            guess_suffix = QWORD_MNEM_SUFFIX;
            break;
          }
    }
  else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
    guess_suffix = WORD_MNEM_SUFFIX;

  for (op = i.operands; --op >= 0;)
    if (operand_type_check (i.types[op], imm))
      {
        switch (i.op[op].imms->X_op)
          {
          case O_constant:
            /* If a suffix is given, this operand may be shortened.  */
            switch (guess_suffix)
              {
              case LONG_MNEM_SUFFIX:
                i.types[op].bitfield.imm32 = 1;
                i.types[op].bitfield.imm64 = 1;
                break;
              case WORD_MNEM_SUFFIX:
                i.types[op].bitfield.imm16 = 1;
                i.types[op].bitfield.imm32 = 1;
                i.types[op].bitfield.imm32s = 1;
                i.types[op].bitfield.imm64 = 1;
                break;
              case BYTE_MNEM_SUFFIX:
                i.types[op].bitfield.imm8 = 1;
                i.types[op].bitfield.imm8s = 1;
                i.types[op].bitfield.imm16 = 1;
                i.types[op].bitfield.imm32 = 1;
                i.types[op].bitfield.imm32s = 1;
                i.types[op].bitfield.imm64 = 1;
                break;
              }

            /* If this operand is at most 16 bits, convert it
               to a signed 16 bit number before trying to see
               whether it will fit in an even smaller size.
               This allows a 16-bit operand such as $0xffe0 to
               be recognised as within Imm8S range.  */
            if ((i.types[op].bitfield.imm16)
                && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
              {
                i.op[op].imms->X_add_number =
                  (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
              }
            if ((i.types[op].bitfield.imm32)
                && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
                    == 0))
              {
                i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
                                                ^ ((offsetT) 1 << 31))
                                               - ((offsetT) 1 << 31));
              }
            i.types[op]
              = operand_type_or (i.types[op],
                                 smallest_imm_type (i.op[op].imms->X_add_number));

            /* We must avoid matching of Imm32 templates when 64bit
               only immediate is available.  */
            if (guess_suffix == QWORD_MNEM_SUFFIX)
              i.types[op].bitfield.imm32 = 0;
            break;

          case O_absent:
          case O_register:
            abort ();

            /* Symbols and expressions.  */
          default:
            /* Convert symbolic operand to proper sizes for matching, but don't
               prevent matching a set of insns that only supports sizes other
               than those matching the insn suffix.  */
            {
              i386_operand_type mask, allowed;
              const insn_template *t;

              operand_type_set (&mask, 0);
              operand_type_set (&allowed, 0);

              for (t = current_templates->start;
                   t < current_templates->end;
                   ++t)
                allowed = operand_type_or (allowed,
                                           t->operand_types[op]);
              switch (guess_suffix)
                {
                case QWORD_MNEM_SUFFIX:
                  mask.bitfield.imm64 = 1;
                  mask.bitfield.imm32s = 1;
                  break;
                case LONG_MNEM_SUFFIX:
                  mask.bitfield.imm32 = 1;
                  break;
                case WORD_MNEM_SUFFIX:
                  mask.bitfield.imm16 = 1;
                  break;
                case BYTE_MNEM_SUFFIX:
                  mask.bitfield.imm8 = 1;
                  break;
                default:
                  break;
                }
              allowed = operand_type_and (mask, allowed);
              if (!operand_type_all_zero (&allowed))
                i.types[op] = operand_type_and (i.types[op], mask);
            }
            break;
          }
      }
}

/* Try to use the smallest displacement type too.  */
static void
optimize_disp (void)
{
  int op;

  for (op = i.operands; --op >= 0;)
    if (operand_type_check (i.types[op], disp))
      {
        if (i.op[op].disps->X_op == O_constant)
          {
            offsetT op_disp = i.op[op].disps->X_add_number;

            if (i.types[op].bitfield.disp16
                && (op_disp & ~(offsetT) 0xffff) == 0)
              {
                /* If this operand is at most 16 bits, convert
                   to a signed 16 bit number and don't use 64bit
                   displacement.  */
                op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
                i.types[op].bitfield.disp64 = 0;
              }
            if (i.types[op].bitfield.disp32
                && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
              {
                /* If this operand is at most 32 bits, convert
                   to a signed 32 bit number and don't use 64bit
                   displacement.  */
                op_disp &= (((offsetT) 2 << 31) - 1);
                op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
                i.types[op].bitfield.disp64 = 0;
              }
            if (!op_disp && i.types[op].bitfield.baseindex)
              {
                i.types[op].bitfield.disp8 = 0;
                i.types[op].bitfield.disp16 = 0;
                i.types[op].bitfield.disp32 = 0;
                i.types[op].bitfield.disp32s = 0;
                i.types[op].bitfield.disp64 = 0;
                i.op[op].disps = 0;
                i.disp_operands--;
              }
            else if (flag_code == CODE_64BIT)
              {
                if (fits_in_signed_long (op_disp))
                  {
                    i.types[op].bitfield.disp64 = 0;
                    i.types[op].bitfield.disp32s = 1;
                  }
                if (i.prefix[ADDR_PREFIX]
                    && fits_in_unsigned_long (op_disp))
                  i.types[op].bitfield.disp32 = 1;
              }
            if ((i.types[op].bitfield.disp32
                 || i.types[op].bitfield.disp32s
                 || i.types[op].bitfield.disp16)
                && fits_in_signed_byte (op_disp))
              i.types[op].bitfield.disp8 = 1;
          }
        else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
                 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
          {
            fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
                         i.op[op].disps, 0, i.reloc[op]);
            i.types[op].bitfield.disp8 = 0;
            i.types[op].bitfield.disp16 = 0;
            i.types[op].bitfield.disp32 = 0;
            i.types[op].bitfield.disp32s = 0;
            i.types[op].bitfield.disp64 = 0;
          }
        else
          /* We only support 64bit displacement on constants.  */
          i.types[op].bitfield.disp64 = 0;
      }
}

/* Check if operands are valid for the instruction.  Update VEX
   operand types.  */

static int
VEX_check_operands (const insn_template *t)
{
  if (!t->opcode_modifier.vex)
    return 0;

  /* Only check VEX_Imm4, which must be the first operand.  */
  if (t->operand_types[0].bitfield.vec_imm4)
    {
      if (i.op[0].imms->X_op != O_constant
          || !fits_in_imm4 (i.op[0].imms->X_add_number))
        {
          i.error = bad_imm4;
          return 1;
        }

      /* Turn off Imm8 so that update_imm won't complain.  */
      i.types[0] = vec_imm4;
    }

  return 0;
}

static const insn_template *
match_template (void)
{
  /* Points to template once we've found it.  */
  const insn_template *t;
  i386_operand_type overlap0, overlap1, overlap2, overlap3;
  i386_operand_type overlap4;
  unsigned int found_reverse_match;
  i386_opcode_modifier suffix_check;
  i386_operand_type operand_types [MAX_OPERANDS];
  int addr_prefix_disp;
  unsigned int j;
  unsigned int found_cpu_match;
  unsigned int check_register;

#if MAX_OPERANDS != 5
# error "MAX_OPERANDS must be 5."
#endif

  found_reverse_match = 0;
  addr_prefix_disp = -1;

  memset (&suffix_check, 0, sizeof (suffix_check));
  if (i.suffix == BYTE_MNEM_SUFFIX)
    suffix_check.no_bsuf = 1;
  else if (i.suffix == WORD_MNEM_SUFFIX)
    suffix_check.no_wsuf = 1;
  else if (i.suffix == SHORT_MNEM_SUFFIX)
    suffix_check.no_ssuf = 1;
  else if (i.suffix == LONG_MNEM_SUFFIX)
    suffix_check.no_lsuf = 1;
  else if (i.suffix == QWORD_MNEM_SUFFIX)
    suffix_check.no_qsuf = 1;
  else if (i.suffix == LONG_DOUBLE_MNEM_SUFFIX)
    suffix_check.no_ldsuf = 1;

  /* Must have right number of operands.  */
  i.error = number_of_operands_mismatch;

  for (t = current_templates->start; t < current_templates->end; t++)
    {
      addr_prefix_disp = -1;

      if (i.operands != t->operands)
        continue;

      /* Check processor support.  */
      i.error = unsupported;
      found_cpu_match = (cpu_flags_match (t)
                         == CPU_FLAGS_PERFECT_MATCH);
      if (!found_cpu_match)
        continue;

      /* Check old gcc support. */
      i.error = old_gcc_only;
      if (!old_gcc && t->opcode_modifier.oldgcc)
        continue;

      /* Check AT&T mnemonic.   */
      i.error = unsupported_with_intel_mnemonic;
      if (intel_mnemonic && t->opcode_modifier.attmnemonic)
        continue;

      /* Check AT&T/Intel syntax.   */
      i.error = unsupported_syntax;
      if ((intel_syntax && t->opcode_modifier.attsyntax)
          || (!intel_syntax && t->opcode_modifier.intelsyntax))
        continue;

      /* Check the suffix, except for some instructions in intel mode.  */
      i.error = invalid_instruction_suffix;
      if ((!intel_syntax || !t->opcode_modifier.ignoresize)
          && ((t->opcode_modifier.no_bsuf && suffix_check.no_bsuf)
              || (t->opcode_modifier.no_wsuf && suffix_check.no_wsuf)
              || (t->opcode_modifier.no_lsuf && suffix_check.no_lsuf)
              || (t->opcode_modifier.no_ssuf && suffix_check.no_ssuf)
              || (t->opcode_modifier.no_qsuf && suffix_check.no_qsuf)
              || (t->opcode_modifier.no_ldsuf && suffix_check.no_ldsuf)))
        continue;

      if (!operand_size_match (t))
        continue;

      for (j = 0; j < MAX_OPERANDS; j++)
        operand_types[j] = t->operand_types[j];

      /* In general, don't allow 64-bit operands in 32-bit mode.  */
      if (i.suffix == QWORD_MNEM_SUFFIX
          && flag_code != CODE_64BIT
          && (intel_syntax
              ? (!t->opcode_modifier.ignoresize
                 && !intel_float_operand (t->name))
              : intel_float_operand (t->name) != 2)
          && ((!operand_types[0].bitfield.regmmx
               && !operand_types[0].bitfield.regxmm
               && !operand_types[0].bitfield.regymm)
              || (!operand_types[t->operands > 1].bitfield.regmmx
                  && !!operand_types[t->operands > 1].bitfield.regxmm
                  && !!operand_types[t->operands > 1].bitfield.regymm))
          && (t->base_opcode != 0x0fc7
              || t->extension_opcode != 1 /* cmpxchg8b */))
        continue;

      /* In general, don't allow 32-bit operands on pre-386.  */
      else if (i.suffix == LONG_MNEM_SUFFIX
               && !cpu_arch_flags.bitfield.cpui386
               && (intel_syntax
                   ? (!t->opcode_modifier.ignoresize
                      && !intel_float_operand (t->name))
                   : intel_float_operand (t->name) != 2)
               && ((!operand_types[0].bitfield.regmmx
                    && !operand_types[0].bitfield.regxmm)
                   || (!operand_types[t->operands > 1].bitfield.regmmx
                       && !!operand_types[t->operands > 1].bitfield.regxmm)))
        continue;

      /* Do not verify operands when there are none.  */
      else
        {
          if (!t->operands)
            /* We've found a match; break out of loop.  */
            break;
        }

      /* Address size prefix will turn Disp64/Disp32/Disp16 operand
         into Disp32/Disp16/Disp32 operand.  */
      if (i.prefix[ADDR_PREFIX] != 0)
          {
            /* There should be only one Disp operand.  */
            switch (flag_code)
            {
            case CODE_16BIT:
              for (j = 0; j < MAX_OPERANDS; j++)
                {
                  if (operand_types[j].bitfield.disp16)
                    {
                      addr_prefix_disp = j;
                      operand_types[j].bitfield.disp32 = 1;
                      operand_types[j].bitfield.disp16 = 0;
                      break;
                    }
                }
              break;
            case CODE_32BIT:
              for (j = 0; j < MAX_OPERANDS; j++)
                {
                  if (operand_types[j].bitfield.disp32)
                    {
                      addr_prefix_disp = j;
                      operand_types[j].bitfield.disp32 = 0;
                      operand_types[j].bitfield.disp16 = 1;
                      break;
                    }
                }
              break;
            case CODE_64BIT:
              for (j = 0; j < MAX_OPERANDS; j++)
                {
                  if (operand_types[j].bitfield.disp64)
                    {
                      addr_prefix_disp = j;
                      operand_types[j].bitfield.disp64 = 0;
                      operand_types[j].bitfield.disp32 = 1;
                      break;
                    }
                }
              break;
            }
          }

      /* We check register size if needed.  */
      check_register = t->opcode_modifier.checkregsize;
      overlap0 = operand_type_and (i.types[0], operand_types[0]);
      switch (t->operands)
        {
        case 1:
          if (!operand_type_match (overlap0, i.types[0]))
            continue;
          break;
        case 2:
          /* xchg %eax, %eax is a special case. It is an aliase for nop
             only in 32bit mode and we can use opcode 0x90.  In 64bit
             mode, we can't use 0x90 for xchg %eax, %eax since it should
             zero-extend %eax to %rax.  */
          if (flag_code == CODE_64BIT
              && t->base_opcode == 0x90
              && operand_type_equal (&i.types [0], &acc32)
              && operand_type_equal (&i.types [1], &acc32))
            continue;
          if (i.swap_operand)
            {
              /* If we swap operand in encoding, we either match
                 the next one or reverse direction of operands.  */
              if (t->opcode_modifier.s)
                continue;
              else if (t->opcode_modifier.d)
                goto check_reverse;
            }

        case 3:
          /* If we swap operand in encoding, we match the next one.  */
          if (i.swap_operand && t->opcode_modifier.s)
            continue;
        case 4:
        case 5:
          overlap1 = operand_type_and (i.types[1], operand_types[1]);
          if (!operand_type_match (overlap0, i.types[0])
              || !operand_type_match (overlap1, i.types[1])
              || (check_register
                  && !operand_type_register_match (overlap0, i.types[0],
                                                   operand_types[0],
                                                   overlap1, i.types[1],
                                                   operand_types[1])))
            {
              /* Check if other direction is valid ...  */
              if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
                continue;

check_reverse:
              /* Try reversing direction of operands.  */
              overlap0 = operand_type_and (i.types[0], operand_types[1]);
              overlap1 = operand_type_and (i.types[1], operand_types[0]);
              if (!operand_type_match (overlap0, i.types[0])
                  || !operand_type_match (overlap1, i.types[1])
                  || (check_register
                      && !operand_type_register_match (overlap0,
                                                       i.types[0],
                                                       operand_types[1],
                                                       overlap1,
                                                       i.types[1],
                                                       operand_types[0])))
                {
                  /* Does not match either direction.  */
                  continue;
                }
              /* found_reverse_match holds which of D or FloatDR
                 we've found.  */
              if (t->opcode_modifier.d)
                found_reverse_match = Opcode_D;
              else if (t->opcode_modifier.floatd)
                found_reverse_match = Opcode_FloatD;
              else
                found_reverse_match = 0;
              if (t->opcode_modifier.floatr)
                found_reverse_match |= Opcode_FloatR;
            }
          else
            {
              /* Found a forward 2 operand match here.  */
              switch (t->operands)
                {
                case 5:
                  overlap4 = operand_type_and (i.types[4],
                                               operand_types[4]);
                case 4:
                  overlap3 = operand_type_and (i.types[3],
                                               operand_types[3]);
                case 3:
                  overlap2 = operand_type_and (i.types[2],
                                               operand_types[2]);
                  break;
                }

              switch (t->operands)
                {
                case 5:
                  if (!operand_type_match (overlap4, i.types[4])
                      || !operand_type_register_match (overlap3,
                                                       i.types[3],
                                                       operand_types[3],
                                                       overlap4,
                                                       i.types[4],
                                                       operand_types[4]))
                    continue;
                case 4:
                  if (!operand_type_match (overlap3, i.types[3])
                      || (check_register
                          && !operand_type_register_match (overlap2,
                                                           i.types[2],
                                                           operand_types[2],
                                                           overlap3,
                                                           i.types[3],
                                                           operand_types[3])))
                    continue;
                case 3:
                  /* Here we make use of the fact that there are no
                     reverse match 3 operand instructions, and all 3
                     operand instructions only need to be checked for
                     register consistency between operands 2 and 3.  */
                  if (!operand_type_match (overlap2, i.types[2])
                      || (check_register
                          && !operand_type_register_match (overlap1,
                                                           i.types[1],
                                                           operand_types[1],
                                                           overlap2,
                                                           i.types[2],
                                                           operand_types[2])))
                    continue;
                  break;
                }
            }
          /* Found either forward/reverse 2, 3 or 4 operand match here:
             slip through to break.  */
        }
      if (!found_cpu_match)
        {
          found_reverse_match = 0;
          continue;
        }

      /* Check if VEX operands are valid.  */
      if (VEX_check_operands (t))
        continue;

      /* We've found a match; break out of loop.  */
      break;
    }

  if (t == current_templates->end)
    {
      /* We found no match.  */
      const char *err_msg;
      switch (i.error)
        {
        default:
          abort ();
        case operand_size_mismatch:
          err_msg = _("operand size mismatch");
          break;