Add support for DragonFlyBSD target.
[binutils.git] / gas / config / tc-i386.c
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
5
6 This file is part of GAS, the GNU Assembler.
7
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
11 any later version.
12
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
21 02110-1301, USA. */
22
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
29
30 #include "as.h"
31 #include "safe-ctype.h"
32 #include "subsegs.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
37
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
40 #endif
41
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
44 #endif
45
46 #ifndef DEFAULT_ARCH
47 #define DEFAULT_ARCH "i386"
48 #endif
49
50 #ifndef INLINE
51 #if __GNUC__ >= 2
52 #define INLINE __inline__
53 #else
54 #define INLINE
55 #endif
56 #endif
57
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
63 #define WAIT_PREFIX 0
64 #define SEG_PREFIX 1
65 #define ADDR_PREFIX 2
66 #define DATA_PREFIX 3
67 #define REP_PREFIX 4
68 #define LOCK_PREFIX 5
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
71
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
76
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 in instructions. */
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89
90 #define END_OF_INSN '\0'
91
92 /*
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
97 END.
98 */
99 typedef struct
100 {
101 const insn_template *start;
102 const insn_template *end;
103 }
104 templates;
105
106 /* 386 operand encoding bytes: see 386 book for details of this. */
107 typedef struct
108 {
109 unsigned int regmem; /* codes register or memory operand */
110 unsigned int reg; /* codes register operand (or extended opcode) */
111 unsigned int mode; /* how to interpret regmem & reg */
112 }
113 modrm_byte;
114
115 /* x86-64 extension prefix. */
116 typedef int rex_byte;
117
118 /* 386 opcode byte to code indirect addressing. */
119 typedef struct
120 {
121 unsigned base;
122 unsigned index;
123 unsigned scale;
124 }
125 sib_byte;
126
127 /* x86 arch names, types and features */
128 typedef struct
129 {
130 const char *name; /* arch name */
131 unsigned int len; /* arch string length */
132 enum processor_type type; /* arch type */
133 i386_cpu_flags flags; /* cpu feature flags */
134 unsigned int skip; /* show_arch should skip this. */
135 unsigned int negated; /* turn off indicated flags. */
136 }
137 arch_entry;
138
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_sse_check (int);
146 static void set_cpu_arch (int);
147 #ifdef TE_PE
148 static void pe_directive_secrel (int);
149 #endif
150 static void signed_cons (int);
151 static char *output_invalid (int c);
152 static int i386_finalize_immediate (segT, expressionS *, i386_operand_type,
153 const char *);
154 static int i386_finalize_displacement (segT, expressionS *, i386_operand_type,
155 const char *);
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS *);
159 static int i386_intel_parse_name (const char *, expressionS *);
160 static const reg_entry *parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (int, int);
165 static void optimize_imm (void);
166 static void optimize_disp (void);
167 static const insn_template *match_template (void);
168 static int check_string (void);
169 static int process_suffix (void);
170 static int check_byte_reg (void);
171 static int check_long_reg (void);
172 static int check_qword_reg (void);
173 static int check_word_reg (void);
174 static int finalize_imm (void);
175 static int process_operands (void);
176 static const seg_entry *build_modrm_byte (void);
177 static void output_insn (void);
178 static void output_imm (fragS *, offsetT);
179 static void output_disp (fragS *, offsetT);
180 #ifndef I386COFF
181 static void s_bss (int);
182 #endif
183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184 static void handle_large_common (int small ATTRIBUTE_UNUSED);
185 #endif
186
187 static const char *default_arch = DEFAULT_ARCH;
188
189 /* VEX prefix. */
190 typedef struct
191 {
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes[3];
194 unsigned int length;
195 /* Destination or source register specifier. */
196 const reg_entry *register_specifier;
197 } vex_prefix;
198
199 /* 'md_assemble ()' gathers together information and puts it into a
200 i386_insn. */
201
202 union i386_op
203 {
204 expressionS *disps;
205 expressionS *imms;
206 const reg_entry *regs;
207 };
208
209 enum i386_error
210 {
211 operand_size_mismatch,
212 operand_type_mismatch,
213 register_type_mismatch,
214 number_of_operands_mismatch,
215 invalid_instruction_suffix,
216 bad_imm4,
217 old_gcc_only,
218 unsupported_with_intel_mnemonic,
219 unsupported_syntax,
220 unsupported
221 };
222
223 struct _i386_insn
224 {
225 /* TM holds the template for the insn were currently assembling. */
226 insn_template tm;
227
228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
230 char suffix;
231
232 /* OPERANDS gives the number of given operands. */
233 unsigned int operands;
234
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
237 operands. */
238 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
239
240 /* TYPES [i] is the type (see above #defines) which tells us how to
241 use OP[i] for the corresponding operand. */
242 i386_operand_type types[MAX_OPERANDS];
243
244 /* Displacement expression, immediate expression, or register for each
245 operand. */
246 union i386_op op[MAX_OPERANDS];
247
248 /* Flags for operands. */
249 unsigned int flags[MAX_OPERANDS];
250 #define Operand_PCrel 1
251
252 /* Relocation type for operand */
253 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
254
255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry *base_reg;
258 const reg_entry *index_reg;
259 unsigned int log2_scale_factor;
260
261 /* SEG gives the seg_entries of this insn. They are zero unless
262 explicit segment overrides are given. */
263 const seg_entry *seg[2];
264
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes;
268 unsigned char prefix[MAX_PREFIXES];
269
270 /* RM and SIB are the modrm byte and the sib byte where the
271 addressing modes of this insn are encoded. */
272 modrm_byte rm;
273 rex_byte rex;
274 sib_byte sib;
275 vex_prefix vex;
276
277 /* Swap operand in encoding. */
278 unsigned int swap_operand;
279
280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding;
282
283 /* Error message. */
284 enum i386_error error;
285 };
286
287 typedef struct _i386_insn i386_insn;
288
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars[] = "*%-(["
292 #ifdef LEX_AT
293 "@"
294 #endif
295 #ifdef LEX_QM
296 "?"
297 #endif
298 ;
299
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_DragonFly) \
307 && !defined (TE_NetBSD)))
308 /* This array holds the chars that always start a comment. If the
309 pre-processor is disabled, these aren't very useful. The option
310 --divide will remove '/' from this list. */
311 const char *i386_comment_chars = "#/";
312 #define SVR4_COMMENT_CHARS 1
313 #define PREFIX_SEPARATOR '\\'
314
315 #else
316 const char *i386_comment_chars = "#";
317 #define PREFIX_SEPARATOR '/'
318 #endif
319
320 /* This array holds the chars that only start a comment at the beginning of
321 a line. If the line seems to have the form '# 123 filename'
322 .line and .file directives will appear in the pre-processed output.
323 Note that input_file.c hand checks for '#' at the beginning of the
324 first line of the input file. This is because the compiler outputs
325 #NO_APP at the beginning of its output.
326 Also note that comments started like this one will always work if
327 '/' isn't otherwise defined. */
328 const char line_comment_chars[] = "#/";
329
330 const char line_separator_chars[] = ";";
331
332 /* Chars that can be used to separate mant from exp in floating point
333 nums. */
334 const char EXP_CHARS[] = "eE";
335
336 /* Chars that mean this number is a floating point constant
337 As in 0f12.456
338 or 0d1.2345e12. */
339 const char FLT_CHARS[] = "fFdDxX";
340
341 /* Tables for lexical analysis. */
342 static char mnemonic_chars[256];
343 static char register_chars[256];
344 static char operand_chars[256];
345 static char identifier_chars[256];
346 static char digit_chars[256];
347
348 /* Lexical macros. */
349 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
350 #define is_operand_char(x) (operand_chars[(unsigned char) x])
351 #define is_register_char(x) (register_chars[(unsigned char) x])
352 #define is_space_char(x) ((x) == ' ')
353 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
354 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355
356 /* All non-digit non-letter characters that may occur in an operand. */
357 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
358
359 /* md_assemble() always leaves the strings it's passed unaltered. To
360 effect this we maintain a stack of saved characters that we've smashed
361 with '\0's (indicating end of strings for various sub-fields of the
362 assembler instruction). */
363 static char save_stack[32];
364 static char *save_stack_p;
365 #define END_STRING_AND_SAVE(s) \
366 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
367 #define RESTORE_END_STRING(s) \
368 do { *(s) = *--save_stack_p; } while (0)
369
370 /* The instruction we're assembling. */
371 static i386_insn i;
372
373 /* Possible templates for current insn. */
374 static const templates *current_templates;
375
376 /* Per instruction expressionS buffers: max displacements & immediates. */
377 static expressionS disp_expressions[MAX_MEMORY_OPERANDS];
378 static expressionS im_expressions[MAX_IMMEDIATE_OPERANDS];
379
380 /* Current operand we are working on. */
381 static int this_operand = -1;
382
383 /* We support four different modes. FLAG_CODE variable is used to distinguish
384 these. */
385
386 enum flag_code {
387 CODE_32BIT,
388 CODE_16BIT,
389 CODE_64BIT };
390
391 static enum flag_code flag_code;
392 static unsigned int object_64bit;
393 static unsigned int disallow_64bit_reloc;
394 static int use_rela_relocations = 0;
395
396 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
397 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
398 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
399
400 /* The ELF ABI to use. */
401 enum x86_elf_abi
402 {
403 I386_ABI,
404 X86_64_ABI,
405 X86_64_X32_ABI
406 };
407
408 static enum x86_elf_abi x86_elf_abi = I386_ABI;
409 #endif
410
411 /* The names used to print error messages. */
412 static const char *flag_code_names[] =
413 {
414 "32",
415 "16",
416 "64"
417 };
418
419 /* 1 for intel syntax,
420 0 if att syntax. */
421 static int intel_syntax = 0;
422
423 /* 1 for intel mnemonic,
424 0 if att mnemonic. */
425 static int intel_mnemonic = !SYSV386_COMPAT;
426
427 /* 1 if support old (<= 2.8.1) versions of gcc. */
428 static int old_gcc = OLDGCC_COMPAT;
429
430 /* 1 if pseudo registers are permitted. */
431 static int allow_pseudo_reg = 0;
432
433 /* 1 if register prefix % not required. */
434 static int allow_naked_reg = 0;
435
436 /* 1 if pseudo index register, eiz/riz, is allowed . */
437 static int allow_index_reg = 0;
438
439 static enum
440 {
441 sse_check_none = 0,
442 sse_check_warning,
443 sse_check_error
444 }
445 sse_check;
446
447 /* Register prefix used for error message. */
448 static const char *register_prefix = "%";
449
450 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
451 leave, push, and pop instructions so that gcc has the same stack
452 frame as in 32 bit mode. */
453 static char stackop_size = '\0';
454
455 /* Non-zero to optimize code alignment. */
456 int optimize_align_code = 1;
457
458 /* Non-zero to quieten some warnings. */
459 static int quiet_warnings = 0;
460
461 /* CPU name. */
462 static const char *cpu_arch_name = NULL;
463 static char *cpu_sub_arch_name = NULL;
464
465 /* CPU feature flags. */
466 static i386_cpu_flags cpu_arch_flags = CPU_UNKNOWN_FLAGS;
467
468 /* If we have selected a cpu we are generating instructions for. */
469 static int cpu_arch_tune_set = 0;
470
471 /* Cpu we are generating instructions for. */
472 enum processor_type cpu_arch_tune = PROCESSOR_UNKNOWN;
473
474 /* CPU feature flags of cpu we are generating instructions for. */
475 static i386_cpu_flags cpu_arch_tune_flags;
476
477 /* CPU instruction set architecture used. */
478 enum processor_type cpu_arch_isa = PROCESSOR_UNKNOWN;
479
480 /* CPU feature flags of instruction set architecture used. */
481 i386_cpu_flags cpu_arch_isa_flags;
482
483 /* If set, conditional jumps are not automatically promoted to handle
484 larger than a byte offset. */
485 static unsigned int no_cond_jump_promotion = 0;
486
487 /* Encode SSE instructions with VEX prefix. */
488 static unsigned int sse2avx;
489
490 /* Encode scalar AVX instructions with specific vector length. */
491 static enum
492 {
493 vex128 = 0,
494 vex256
495 } avxscalar;
496
497 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
498 static symbolS *GOT_symbol;
499
500 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
501 unsigned int x86_dwarf2_return_column;
502
503 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
504 int x86_cie_data_alignment;
505
506 /* Interface to relax_segment.
507 There are 3 major relax states for 386 jump insns because the
508 different types of jumps add different sizes to frags when we're
509 figuring out what sort of jump to choose to reach a given label. */
510
511 /* Types. */
512 #define UNCOND_JUMP 0
513 #define COND_JUMP 1
514 #define COND_JUMP86 2
515
516 /* Sizes. */
517 #define CODE16 1
518 #define SMALL 0
519 #define SMALL16 (SMALL | CODE16)
520 #define BIG 2
521 #define BIG16 (BIG | CODE16)
522
523 #ifndef INLINE
524 #ifdef __GNUC__
525 #define INLINE __inline__
526 #else
527 #define INLINE
528 #endif
529 #endif
530
531 #define ENCODE_RELAX_STATE(type, size) \
532 ((relax_substateT) (((type) << 2) | (size)))
533 #define TYPE_FROM_RELAX_STATE(s) \
534 ((s) >> 2)
535 #define DISP_SIZE_FROM_RELAX_STATE(s) \
536 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
537
538 /* This table is used by relax_frag to promote short jumps to long
539 ones where necessary. SMALL (short) jumps may be promoted to BIG
540 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
541 don't allow a short jump in a 32 bit code segment to be promoted to
542 a 16 bit offset jump because it's slower (requires data size
543 prefix), and doesn't work, unless the destination is in the bottom
544 64k of the code segment (The top 16 bits of eip are zeroed). */
545
546 const relax_typeS md_relax_table[] =
547 {
548 /* The fields are:
549 1) most positive reach of this state,
550 2) most negative reach of this state,
551 3) how many bytes this mode will have in the variable part of the frag
552 4) which index into the table to try if we can't fit into this one. */
553
554 /* UNCOND_JUMP states. */
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
556 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
557 /* dword jmp adds 4 bytes to frag:
558 0 extra opcode bytes, 4 displacement bytes. */
559 {0, 0, 4, 0},
560 /* word jmp adds 2 byte2 to frag:
561 0 extra opcode bytes, 2 displacement bytes. */
562 {0, 0, 2, 0},
563
564 /* COND_JUMP states. */
565 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
566 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
567 /* dword conditionals adds 5 bytes to frag:
568 1 extra opcode byte, 4 displacement bytes. */
569 {0, 0, 5, 0},
570 /* word conditionals add 3 bytes to frag:
571 1 extra opcode byte, 2 displacement bytes. */
572 {0, 0, 3, 0},
573
574 /* COND_JUMP86 states. */
575 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
576 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
577 /* dword conditionals adds 5 bytes to frag:
578 1 extra opcode byte, 4 displacement bytes. */
579 {0, 0, 5, 0},
580 /* word conditionals add 4 bytes to frag:
581 1 displacement byte and a 3 byte long branch insn. */
582 {0, 0, 4, 0}
583 };
584
585 static const arch_entry cpu_arch[] =
586 {
587 /* Do not replace the first two entries - i386_target_format()
588 relies on them being there in this order. */
589 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32,
590 CPU_GENERIC32_FLAGS, 0, 0 },
591 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64,
592 CPU_GENERIC64_FLAGS, 0, 0 },
593 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN,
594 CPU_NONE_FLAGS, 0, 0 },
595 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN,
596 CPU_I186_FLAGS, 0, 0 },
597 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN,
598 CPU_I286_FLAGS, 0, 0 },
599 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386,
600 CPU_I386_FLAGS, 0, 0 },
601 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486,
602 CPU_I486_FLAGS, 0, 0 },
603 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM,
604 CPU_I586_FLAGS, 0, 0 },
605 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO,
606 CPU_I686_FLAGS, 0, 0 },
607 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM,
608 CPU_I586_FLAGS, 0, 0 },
609 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO,
610 CPU_PENTIUMPRO_FLAGS, 0, 0 },
611 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO,
612 CPU_P2_FLAGS, 0, 0 },
613 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO,
614 CPU_P3_FLAGS, 0, 0 },
615 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4,
616 CPU_P4_FLAGS, 0, 0 },
617 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA,
618 CPU_CORE_FLAGS, 0, 0 },
619 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA,
620 CPU_NOCONA_FLAGS, 0, 0 },
621 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE,
622 CPU_CORE_FLAGS, 1, 0 },
623 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE,
624 CPU_CORE_FLAGS, 0, 0 },
625 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2,
626 CPU_CORE2_FLAGS, 1, 0 },
627 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2,
628 CPU_CORE2_FLAGS, 0, 0 },
629 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7,
630 CPU_COREI7_FLAGS, 0, 0 },
631 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM,
632 CPU_L1OM_FLAGS, 0, 0 },
633 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6,
634 CPU_K6_FLAGS, 0, 0 },
635 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6,
636 CPU_K6_2_FLAGS, 0, 0 },
637 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON,
638 CPU_ATHLON_FLAGS, 0, 0 },
639 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8,
640 CPU_K8_FLAGS, 1, 0 },
641 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8,
642 CPU_K8_FLAGS, 0, 0 },
643 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8,
644 CPU_K8_FLAGS, 0, 0 },
645 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10,
646 CPU_AMDFAM10_FLAGS, 0, 0 },
647 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1,
648 CPU_BDVER1_FLAGS, 0, 0 },
649 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN,
650 CPU_8087_FLAGS, 0, 0 },
651 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN,
652 CPU_287_FLAGS, 0, 0 },
653 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN,
654 CPU_387_FLAGS, 0, 0 },
655 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN,
656 CPU_ANY87_FLAGS, 0, 1 },
657 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN,
658 CPU_MMX_FLAGS, 0, 0 },
659 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN,
660 CPU_3DNOWA_FLAGS, 0, 1 },
661 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN,
662 CPU_SSE_FLAGS, 0, 0 },
663 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN,
664 CPU_SSE2_FLAGS, 0, 0 },
665 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN,
666 CPU_SSE3_FLAGS, 0, 0 },
667 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN,
668 CPU_SSSE3_FLAGS, 0, 0 },
669 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN,
670 CPU_SSE4_1_FLAGS, 0, 0 },
671 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN,
672 CPU_SSE4_2_FLAGS, 0, 0 },
673 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN,
674 CPU_SSE4_2_FLAGS, 0, 0 },
675 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN,
676 CPU_ANY_SSE_FLAGS, 0, 1 },
677 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN,
678 CPU_AVX_FLAGS, 0, 0 },
679 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN,
680 CPU_ANY_AVX_FLAGS, 0, 1 },
681 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN,
682 CPU_VMX_FLAGS, 0, 0 },
683 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN,
684 CPU_SMX_FLAGS, 0, 0 },
685 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN,
686 CPU_XSAVE_FLAGS, 0, 0 },
687 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN,
688 CPU_XSAVEOPT_FLAGS, 0, 0 },
689 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN,
690 CPU_AES_FLAGS, 0, 0 },
691 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN,
692 CPU_PCLMUL_FLAGS, 0, 0 },
693 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN,
694 CPU_PCLMUL_FLAGS, 1, 0 },
695 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN,
696 CPU_FSGSBASE_FLAGS, 0, 0 },
697 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN,
698 CPU_RDRND_FLAGS, 0, 0 },
699 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN,
700 CPU_F16C_FLAGS, 0, 0 },
701 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN,
702 CPU_FMA_FLAGS, 0, 0 },
703 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN,
704 CPU_FMA4_FLAGS, 0, 0 },
705 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN,
706 CPU_XOP_FLAGS, 0, 0 },
707 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN,
708 CPU_LWP_FLAGS, 0, 0 },
709 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN,
710 CPU_MOVBE_FLAGS, 0, 0 },
711 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN,
712 CPU_EPT_FLAGS, 0, 0 },
713 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN,
714 CPU_CLFLUSH_FLAGS, 0, 0 },
715 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN,
716 CPU_NOP_FLAGS, 0, 0 },
717 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN,
718 CPU_SYSCALL_FLAGS, 0, 0 },
719 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN,
720 CPU_RDTSCP_FLAGS, 0, 0 },
721 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN,
722 CPU_3DNOW_FLAGS, 0, 0 },
723 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN,
724 CPU_3DNOWA_FLAGS, 0, 0 },
725 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN,
726 CPU_PADLOCK_FLAGS, 0, 0 },
727 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN,
728 CPU_SVME_FLAGS, 1, 0 },
729 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN,
730 CPU_SVME_FLAGS, 0, 0 },
731 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN,
732 CPU_SSE4A_FLAGS, 0, 0 },
733 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN,
734 CPU_ABM_FLAGS, 0, 0 },
735 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN,
736 CPU_BMI_FLAGS, 0, 0 },
737 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN,
738 CPU_TBM_FLAGS, 0, 0 },
739 };
740
741 #ifdef I386COFF
742 /* Like s_lcomm_internal in gas/read.c but the alignment string
743 is allowed to be optional. */
744
745 static symbolS *
746 pe_lcomm_internal (int needs_align, symbolS *symbolP, addressT size)
747 {
748 addressT align = 0;
749
750 SKIP_WHITESPACE ();
751
752 if (needs_align
753 && *input_line_pointer == ',')
754 {
755 align = parse_align (needs_align - 1);
756
757 if (align == (addressT) -1)
758 return NULL;
759 }
760 else
761 {
762 if (size >= 8)
763 align = 3;
764 else if (size >= 4)
765 align = 2;
766 else if (size >= 2)
767 align = 1;
768 else
769 align = 0;
770 }
771
772 bss_alloc (symbolP, size, align);
773 return symbolP;
774 }
775
776 static void
777 pe_lcomm (int needs_align)
778 {
779 s_comm_internal (needs_align * 2, pe_lcomm_internal);
780 }
781 #endif
782
783 const pseudo_typeS md_pseudo_table[] =
784 {
785 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
786 {"align", s_align_bytes, 0},
787 #else
788 {"align", s_align_ptwo, 0},
789 #endif
790 {"arch", set_cpu_arch, 0},
791 #ifndef I386COFF
792 {"bss", s_bss, 0},
793 #else
794 {"lcomm", pe_lcomm, 1},
795 #endif
796 {"ffloat", float_cons, 'f'},
797 {"dfloat", float_cons, 'd'},
798 {"tfloat", float_cons, 'x'},
799 {"value", cons, 2},
800 {"slong", signed_cons, 4},
801 {"noopt", s_ignore, 0},
802 {"optim", s_ignore, 0},
803 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
804 {"code16", set_code_flag, CODE_16BIT},
805 {"code32", set_code_flag, CODE_32BIT},
806 {"code64", set_code_flag, CODE_64BIT},
807 {"intel_syntax", set_intel_syntax, 1},
808 {"att_syntax", set_intel_syntax, 0},
809 {"intel_mnemonic", set_intel_mnemonic, 1},
810 {"att_mnemonic", set_intel_mnemonic, 0},
811 {"allow_index_reg", set_allow_index_reg, 1},
812 {"disallow_index_reg", set_allow_index_reg, 0},
813 {"sse_check", set_sse_check, 0},
814 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
815 {"largecomm", handle_large_common, 0},
816 #else
817 {"file", (void (*) (int)) dwarf2_directive_file, 0},
818 {"loc", dwarf2_directive_loc, 0},
819 {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0},
820 #endif
821 #ifdef TE_PE
822 {"secrel32", pe_directive_secrel, 0},
823 #endif
824 {0, 0, 0}
825 };
826
827 /* For interface with expression (). */
828 extern char *input_line_pointer;
829
830 /* Hash table for instruction mnemonic lookup. */
831 static struct hash_control *op_hash;
832
833 /* Hash table for register lookup. */
834 static struct hash_control *reg_hash;
835 \f
836 void
837 i386_align_code (fragS *fragP, int count)
838 {
839 /* Various efficient no-op patterns for aligning code labels.
840 Note: Don't try to assemble the instructions in the comments.
841 0L and 0w are not legal. */
842 static const char f32_1[] =
843 {0x90}; /* nop */
844 static const char f32_2[] =
845 {0x66,0x90}; /* xchg %ax,%ax */
846 static const char f32_3[] =
847 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
848 static const char f32_4[] =
849 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
850 static const char f32_5[] =
851 {0x90, /* nop */
852 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
853 static const char f32_6[] =
854 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
855 static const char f32_7[] =
856 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
857 static const char f32_8[] =
858 {0x90, /* nop */
859 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
860 static const char f32_9[] =
861 {0x89,0xf6, /* movl %esi,%esi */
862 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
863 static const char f32_10[] =
864 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
865 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
866 static const char f32_11[] =
867 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
868 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
869 static const char f32_12[] =
870 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
871 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
872 static const char f32_13[] =
873 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
874 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
875 static const char f32_14[] =
876 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
877 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
878 static const char f16_3[] =
879 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
880 static const char f16_4[] =
881 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
882 static const char f16_5[] =
883 {0x90, /* nop */
884 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
885 static const char f16_6[] =
886 {0x89,0xf6, /* mov %si,%si */
887 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
888 static const char f16_7[] =
889 {0x8d,0x74,0x00, /* lea 0(%si),%si */
890 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
891 static const char f16_8[] =
892 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
893 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
894 static const char jump_31[] =
895 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
896 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
897 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
898 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
899 static const char *const f32_patt[] = {
900 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
901 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14
902 };
903 static const char *const f16_patt[] = {
904 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8
905 };
906 /* nopl (%[re]ax) */
907 static const char alt_3[] =
908 {0x0f,0x1f,0x00};
909 /* nopl 0(%[re]ax) */
910 static const char alt_4[] =
911 {0x0f,0x1f,0x40,0x00};
912 /* nopl 0(%[re]ax,%[re]ax,1) */
913 static const char alt_5[] =
914 {0x0f,0x1f,0x44,0x00,0x00};
915 /* nopw 0(%[re]ax,%[re]ax,1) */
916 static const char alt_6[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopl 0L(%[re]ax) */
919 static const char alt_7[] =
920 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 /* nopl 0L(%[re]ax,%[re]ax,1) */
922 static const char alt_8[] =
923 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
924 /* nopw 0L(%[re]ax,%[re]ax,1) */
925 static const char alt_9[] =
926 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
928 static const char alt_10[] =
929 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
930 /* data16
931 nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_long_11[] =
933 {0x66,
934 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
935 /* data16
936 data16
937 nopw %cs:0L(%[re]ax,%[re]ax,1) */
938 static const char alt_long_12[] =
939 {0x66,
940 0x66,
941 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
942 /* data16
943 data16
944 data16
945 nopw %cs:0L(%[re]ax,%[re]ax,1) */
946 static const char alt_long_13[] =
947 {0x66,
948 0x66,
949 0x66,
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
951 /* data16
952 data16
953 data16
954 data16
955 nopw %cs:0L(%[re]ax,%[re]ax,1) */
956 static const char alt_long_14[] =
957 {0x66,
958 0x66,
959 0x66,
960 0x66,
961 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
962 /* data16
963 data16
964 data16
965 data16
966 data16
967 nopw %cs:0L(%[re]ax,%[re]ax,1) */
968 static const char alt_long_15[] =
969 {0x66,
970 0x66,
971 0x66,
972 0x66,
973 0x66,
974 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
975 /* nopl 0(%[re]ax,%[re]ax,1)
976 nopw 0(%[re]ax,%[re]ax,1) */
977 static const char alt_short_11[] =
978 {0x0f,0x1f,0x44,0x00,0x00,
979 0x66,0x0f,0x1f,0x44,0x00,0x00};
980 /* nopw 0(%[re]ax,%[re]ax,1)
981 nopw 0(%[re]ax,%[re]ax,1) */
982 static const char alt_short_12[] =
983 {0x66,0x0f,0x1f,0x44,0x00,0x00,
984 0x66,0x0f,0x1f,0x44,0x00,0x00};
985 /* nopw 0(%[re]ax,%[re]ax,1)
986 nopl 0L(%[re]ax) */
987 static const char alt_short_13[] =
988 {0x66,0x0f,0x1f,0x44,0x00,0x00,
989 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
990 /* nopl 0L(%[re]ax)
991 nopl 0L(%[re]ax) */
992 static const char alt_short_14[] =
993 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
994 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
995 /* nopl 0L(%[re]ax)
996 nopl 0L(%[re]ax,%[re]ax,1) */
997 static const char alt_short_15[] =
998 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
999 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1000 static const char *const alt_short_patt[] = {
1001 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1002 alt_9, alt_10, alt_short_11, alt_short_12, alt_short_13,
1003 alt_short_14, alt_short_15
1004 };
1005 static const char *const alt_long_patt[] = {
1006 f32_1, f32_2, alt_3, alt_4, alt_5, alt_6, alt_7, alt_8,
1007 alt_9, alt_10, alt_long_11, alt_long_12, alt_long_13,
1008 alt_long_14, alt_long_15
1009 };
1010
1011 /* Only align for at least a positive non-zero boundary. */
1012 if (count <= 0 || count > MAX_MEM_FOR_RS_ALIGN_CODE)
1013 return;
1014
1015 /* We need to decide which NOP sequence to use for 32bit and
1016 64bit. When -mtune= is used:
1017
1018 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1019 PROCESSOR_GENERIC32, f32_patt will be used.
1020 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1021 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1022 PROCESSOR_GENERIC64, alt_long_patt will be used.
1023 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1024 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
1025 will be used.
1026
1027 When -mtune= isn't used, alt_long_patt will be used if
1028 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1029 be used.
1030
1031 When -march= or .arch is used, we can't use anything beyond
1032 cpu_arch_isa_flags. */
1033
1034 if (flag_code == CODE_16BIT)
1035 {
1036 if (count > 8)
1037 {
1038 memcpy (fragP->fr_literal + fragP->fr_fix,
1039 jump_31, count);
1040 /* Adjust jump offset. */
1041 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1042 }
1043 else
1044 memcpy (fragP->fr_literal + fragP->fr_fix,
1045 f16_patt[count - 1], count);
1046 }
1047 else
1048 {
1049 const char *const *patt = NULL;
1050
1051 if (fragP->tc_frag_data.isa == PROCESSOR_UNKNOWN)
1052 {
1053 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1054 switch (cpu_arch_tune)
1055 {
1056 case PROCESSOR_UNKNOWN:
1057 /* We use cpu_arch_isa_flags to check if we SHOULD
1058 optimize with nops. */
1059 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1060 patt = alt_long_patt;
1061 else
1062 patt = f32_patt;
1063 break;
1064 case PROCESSOR_PENTIUM4:
1065 case PROCESSOR_NOCONA:
1066 case PROCESSOR_CORE:
1067 case PROCESSOR_CORE2:
1068 case PROCESSOR_COREI7:
1069 case PROCESSOR_L1OM:
1070 case PROCESSOR_GENERIC64:
1071 patt = alt_long_patt;
1072 break;
1073 case PROCESSOR_K6:
1074 case PROCESSOR_ATHLON:
1075 case PROCESSOR_K8:
1076 case PROCESSOR_AMDFAM10:
1077 case PROCESSOR_BDVER1:
1078 patt = alt_short_patt;
1079 break;
1080 case PROCESSOR_I386:
1081 case PROCESSOR_I486:
1082 case PROCESSOR_PENTIUM:
1083 case PROCESSOR_PENTIUMPRO:
1084 case PROCESSOR_GENERIC32:
1085 patt = f32_patt;
1086 break;
1087 }
1088 }
1089 else
1090 {
1091 switch (fragP->tc_frag_data.tune)
1092 {
1093 case PROCESSOR_UNKNOWN:
1094 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1095 PROCESSOR_UNKNOWN. */
1096 abort ();
1097 break;
1098
1099 case PROCESSOR_I386:
1100 case PROCESSOR_I486:
1101 case PROCESSOR_PENTIUM:
1102 case PROCESSOR_K6:
1103 case PROCESSOR_ATHLON:
1104 case PROCESSOR_K8:
1105 case PROCESSOR_AMDFAM10:
1106 case PROCESSOR_BDVER1:
1107 case PROCESSOR_GENERIC32:
1108 /* We use cpu_arch_isa_flags to check if we CAN optimize
1109 with nops. */
1110 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1111 patt = alt_short_patt;
1112 else
1113 patt = f32_patt;
1114 break;
1115 case PROCESSOR_PENTIUMPRO:
1116 case PROCESSOR_PENTIUM4:
1117 case PROCESSOR_NOCONA:
1118 case PROCESSOR_CORE:
1119 case PROCESSOR_CORE2:
1120 case PROCESSOR_COREI7:
1121 case PROCESSOR_L1OM:
1122 if (fragP->tc_frag_data.isa_flags.bitfield.cpunop)
1123 patt = alt_long_patt;
1124 else
1125 patt = f32_patt;
1126 break;
1127 case PROCESSOR_GENERIC64:
1128 patt = alt_long_patt;
1129 break;
1130 }
1131 }
1132
1133 if (patt == f32_patt)
1134 {
1135 /* If the padding is less than 15 bytes, we use the normal
1136 ones. Otherwise, we use a jump instruction and adjust
1137 its offset. */
1138 int limit;
1139
1140 /* For 64bit, the limit is 3 bytes. */
1141 if (flag_code == CODE_64BIT
1142 && fragP->tc_frag_data.isa_flags.bitfield.cpulm)
1143 limit = 3;
1144 else
1145 limit = 15;
1146 if (count < limit)
1147 memcpy (fragP->fr_literal + fragP->fr_fix,
1148 patt[count - 1], count);
1149 else
1150 {
1151 memcpy (fragP->fr_literal + fragP->fr_fix,
1152 jump_31, count);
1153 /* Adjust jump offset. */
1154 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
1155 }
1156 }
1157 else
1158 {
1159 /* Maximum length of an instruction is 15 byte. If the
1160 padding is greater than 15 bytes and we don't use jump,
1161 we have to break it into smaller pieces. */
1162 int padding = count;
1163 while (padding > 15)
1164 {
1165 padding -= 15;
1166 memcpy (fragP->fr_literal + fragP->fr_fix + padding,
1167 patt [14], 15);
1168 }
1169
1170 if (padding)
1171 memcpy (fragP->fr_literal + fragP->fr_fix,
1172 patt [padding - 1], padding);
1173 }
1174 }
1175 fragP->fr_var = count;
1176 }
1177
1178 static INLINE int
1179 operand_type_all_zero (const union i386_operand_type *x)
1180 {
1181 switch (ARRAY_SIZE(x->array))
1182 {
1183 case 3:
1184 if (x->array[2])
1185 return 0;
1186 case 2:
1187 if (x->array[1])
1188 return 0;
1189 case 1:
1190 return !x->array[0];
1191 default:
1192 abort ();
1193 }
1194 }
1195
1196 static INLINE void
1197 operand_type_set (union i386_operand_type *x, unsigned int v)
1198 {
1199 switch (ARRAY_SIZE(x->array))
1200 {
1201 case 3:
1202 x->array[2] = v;
1203 case 2:
1204 x->array[1] = v;
1205 case 1:
1206 x->array[0] = v;
1207 break;
1208 default:
1209 abort ();
1210 }
1211 }
1212
1213 static INLINE int
1214 operand_type_equal (const union i386_operand_type *x,
1215 const union i386_operand_type *y)
1216 {
1217 switch (ARRAY_SIZE(x->array))
1218 {
1219 case 3:
1220 if (x->array[2] != y->array[2])
1221 return 0;
1222 case 2:
1223 if (x->array[1] != y->array[1])
1224 return 0;
1225 case 1:
1226 return x->array[0] == y->array[0];
1227 break;
1228 default:
1229 abort ();
1230 }
1231 }
1232
1233 static INLINE int
1234 cpu_flags_all_zero (const union i386_cpu_flags *x)
1235 {
1236 switch (ARRAY_SIZE(x->array))
1237 {
1238 case 3:
1239 if (x->array[2])
1240 return 0;
1241 case 2:
1242 if (x->array[1])
1243 return 0;
1244 case 1:
1245 return !x->array[0];
1246 default:
1247 abort ();
1248 }
1249 }
1250
1251 static INLINE void
1252 cpu_flags_set (union i386_cpu_flags *x, unsigned int v)
1253 {
1254 switch (ARRAY_SIZE(x->array))
1255 {
1256 case 3:
1257 x->array[2] = v;
1258 case 2:
1259 x->array[1] = v;
1260 case 1:
1261 x->array[0] = v;
1262 break;
1263 default:
1264 abort ();
1265 }
1266 }
1267
1268 static INLINE int
1269 cpu_flags_equal (const union i386_cpu_flags *x,
1270 const union i386_cpu_flags *y)
1271 {
1272 switch (ARRAY_SIZE(x->array))
1273 {
1274 case 3:
1275 if (x->array[2] != y->array[2])
1276 return 0;
1277 case 2:
1278 if (x->array[1] != y->array[1])
1279 return 0;
1280 case 1:
1281 return x->array[0] == y->array[0];
1282 break;
1283 default:
1284 abort ();
1285 }
1286 }
1287
1288 static INLINE int
1289 cpu_flags_check_cpu64 (i386_cpu_flags f)
1290 {
1291 return !((flag_code == CODE_64BIT && f.bitfield.cpuno64)
1292 || (flag_code != CODE_64BIT && f.bitfield.cpu64));
1293 }
1294
1295 static INLINE i386_cpu_flags
1296 cpu_flags_and (i386_cpu_flags x, i386_cpu_flags y)
1297 {
1298 switch (ARRAY_SIZE (x.array))
1299 {
1300 case 3:
1301 x.array [2] &= y.array [2];
1302 case 2:
1303 x.array [1] &= y.array [1];
1304 case 1:
1305 x.array [0] &= y.array [0];
1306 break;
1307 default:
1308 abort ();
1309 }
1310 return x;
1311 }
1312
1313 static INLINE i386_cpu_flags
1314 cpu_flags_or (i386_cpu_flags x, i386_cpu_flags y)
1315 {
1316 switch (ARRAY_SIZE (x.array))
1317 {
1318 case 3:
1319 x.array [2] |= y.array [2];
1320 case 2:
1321 x.array [1] |= y.array [1];
1322 case 1:
1323 x.array [0] |= y.array [0];
1324 break;
1325 default:
1326 abort ();
1327 }
1328 return x;
1329 }
1330
1331 static INLINE i386_cpu_flags
1332 cpu_flags_and_not (i386_cpu_flags x, i386_cpu_flags y)
1333 {
1334 switch (ARRAY_SIZE (x.array))
1335 {
1336 case 3:
1337 x.array [2] &= ~y.array [2];
1338 case 2:
1339 x.array [1] &= ~y.array [1];
1340 case 1:
1341 x.array [0] &= ~y.array [0];
1342 break;
1343 default:
1344 abort ();
1345 }
1346 return x;
1347 }
1348
1349 #define CPU_FLAGS_ARCH_MATCH 0x1
1350 #define CPU_FLAGS_64BIT_MATCH 0x2
1351 #define CPU_FLAGS_AES_MATCH 0x4
1352 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1353 #define CPU_FLAGS_AVX_MATCH 0x10
1354
1355 #define CPU_FLAGS_32BIT_MATCH \
1356 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1357 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1358 #define CPU_FLAGS_PERFECT_MATCH \
1359 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1360
1361 /* Return CPU flags match bits. */
1362
1363 static int
1364 cpu_flags_match (const insn_template *t)
1365 {
1366 i386_cpu_flags x = t->cpu_flags;
1367 int match = cpu_flags_check_cpu64 (x) ? CPU_FLAGS_64BIT_MATCH : 0;
1368
1369 x.bitfield.cpu64 = 0;
1370 x.bitfield.cpuno64 = 0;
1371
1372 if (cpu_flags_all_zero (&x))
1373 {
1374 /* This instruction is available on all archs. */
1375 match |= CPU_FLAGS_32BIT_MATCH;
1376 }
1377 else
1378 {
1379 /* This instruction is available only on some archs. */
1380 i386_cpu_flags cpu = cpu_arch_flags;
1381
1382 cpu.bitfield.cpu64 = 0;
1383 cpu.bitfield.cpuno64 = 0;
1384 cpu = cpu_flags_and (x, cpu);
1385 if (!cpu_flags_all_zero (&cpu))
1386 {
1387 if (x.bitfield.cpuavx)
1388 {
1389 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1390 if (cpu.bitfield.cpuavx)
1391 {
1392 /* Check SSE2AVX. */
1393 if (!t->opcode_modifier.sse2avx|| sse2avx)
1394 {
1395 match |= (CPU_FLAGS_ARCH_MATCH
1396 | CPU_FLAGS_AVX_MATCH);
1397 /* Check AES. */
1398 if (!x.bitfield.cpuaes || cpu.bitfield.cpuaes)
1399 match |= CPU_FLAGS_AES_MATCH;
1400 /* Check PCLMUL. */
1401 if (!x.bitfield.cpupclmul
1402 || cpu.bitfield.cpupclmul)
1403 match |= CPU_FLAGS_PCLMUL_MATCH;
1404 }
1405 }
1406 else
1407 match |= CPU_FLAGS_ARCH_MATCH;
1408 }
1409 else
1410 match |= CPU_FLAGS_32BIT_MATCH;
1411 }
1412 }
1413 return match;
1414 }
1415
1416 static INLINE i386_operand_type
1417 operand_type_and (i386_operand_type x, i386_operand_type y)
1418 {
1419 switch (ARRAY_SIZE (x.array))
1420 {
1421 case 3:
1422 x.array [2] &= y.array [2];
1423 case 2:
1424 x.array [1] &= y.array [1];
1425 case 1:
1426 x.array [0] &= y.array [0];
1427 break;
1428 default:
1429 abort ();
1430 }
1431 return x;
1432 }
1433
1434 static INLINE i386_operand_type
1435 operand_type_or (i386_operand_type x, i386_operand_type y)
1436 {
1437 switch (ARRAY_SIZE (x.array))
1438 {
1439 case 3:
1440 x.array [2] |= y.array [2];
1441 case 2:
1442 x.array [1] |= y.array [1];
1443 case 1:
1444 x.array [0] |= y.array [0];
1445 break;
1446 default:
1447 abort ();
1448 }
1449 return x;
1450 }
1451
1452 static INLINE i386_operand_type
1453 operand_type_xor (i386_operand_type x, i386_operand_type y)
1454 {
1455 switch (ARRAY_SIZE (x.array))
1456 {
1457 case 3:
1458 x.array [2] ^= y.array [2];
1459 case 2:
1460 x.array [1] ^= y.array [1];
1461 case 1:
1462 x.array [0] ^= y.array [0];
1463 break;
1464 default:
1465 abort ();
1466 }
1467 return x;
1468 }
1469
1470 static const i386_operand_type acc32 = OPERAND_TYPE_ACC32;
1471 static const i386_operand_type acc64 = OPERAND_TYPE_ACC64;
1472 static const i386_operand_type control = OPERAND_TYPE_CONTROL;
1473 static const i386_operand_type inoutportreg
1474 = OPERAND_TYPE_INOUTPORTREG;
1475 static const i386_operand_type reg16_inoutportreg
1476 = OPERAND_TYPE_REG16_INOUTPORTREG;
1477 static const i386_operand_type disp16 = OPERAND_TYPE_DISP16;
1478 static const i386_operand_type disp32 = OPERAND_TYPE_DISP32;
1479 static const i386_operand_type disp32s = OPERAND_TYPE_DISP32S;
1480 static const i386_operand_type disp16_32 = OPERAND_TYPE_DISP16_32;
1481 static const i386_operand_type anydisp
1482 = OPERAND_TYPE_ANYDISP;
1483 static const i386_operand_type regxmm = OPERAND_TYPE_REGXMM;
1484 static const i386_operand_type regymm = OPERAND_TYPE_REGYMM;
1485 static const i386_operand_type imm8 = OPERAND_TYPE_IMM8;
1486 static const i386_operand_type imm8s = OPERAND_TYPE_IMM8S;
1487 static const i386_operand_type imm16 = OPERAND_TYPE_IMM16;
1488 static const i386_operand_type imm32 = OPERAND_TYPE_IMM32;
1489 static const i386_operand_type imm32s = OPERAND_TYPE_IMM32S;
1490 static const i386_operand_type imm64 = OPERAND_TYPE_IMM64;
1491 static const i386_operand_type imm16_32 = OPERAND_TYPE_IMM16_32;
1492 static const i386_operand_type imm16_32s = OPERAND_TYPE_IMM16_32S;
1493 static const i386_operand_type imm16_32_32s = OPERAND_TYPE_IMM16_32_32S;
1494 static const i386_operand_type vec_imm4 = OPERAND_TYPE_VEC_IMM4;
1495
1496 enum operand_type
1497 {
1498 reg,
1499 imm,
1500 disp,
1501 anymem
1502 };
1503
1504 static INLINE int
1505 operand_type_check (i386_operand_type t, enum operand_type c)
1506 {
1507 switch (c)
1508 {
1509 case reg:
1510 return (t.bitfield.reg8
1511 || t.bitfield.reg16
1512 || t.bitfield.reg32
1513 || t.bitfield.reg64);
1514
1515 case imm:
1516 return (t.bitfield.imm8
1517 || t.bitfield.imm8s
1518 || t.bitfield.imm16
1519 || t.bitfield.imm32
1520 || t.bitfield.imm32s
1521 || t.bitfield.imm64);
1522
1523 case disp:
1524 return (t.bitfield.disp8
1525 || t.bitfield.disp16
1526 || t.bitfield.disp32
1527 || t.bitfield.disp32s
1528 || t.bitfield.disp64);
1529
1530 case anymem:
1531 return (t.bitfield.disp8
1532 || t.bitfield.disp16
1533 || t.bitfield.disp32
1534 || t.bitfield.disp32s
1535 || t.bitfield.disp64
1536 || t.bitfield.baseindex);
1537
1538 default:
1539 abort ();
1540 }
1541
1542 return 0;
1543 }
1544
1545 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1546 operand J for instruction template T. */
1547
1548 static INLINE int
1549 match_reg_size (const insn_template *t, unsigned int j)
1550 {
1551 return !((i.types[j].bitfield.byte
1552 && !t->operand_types[j].bitfield.byte)
1553 || (i.types[j].bitfield.word
1554 && !t->operand_types[j].bitfield.word)
1555 || (i.types[j].bitfield.dword
1556 && !t->operand_types[j].bitfield.dword)
1557 || (i.types[j].bitfield.qword
1558 && !t->operand_types[j].bitfield.qword));
1559 }
1560
1561 /* Return 1 if there is no conflict in any size on operand J for
1562 instruction template T. */
1563
1564 static INLINE int
1565 match_mem_size (const insn_template *t, unsigned int j)
1566 {
1567 return (match_reg_size (t, j)
1568 && !((i.types[j].bitfield.unspecified
1569 && !t->operand_types[j].bitfield.unspecified)
1570 || (i.types[j].bitfield.fword
1571 && !t->operand_types[j].bitfield.fword)
1572 || (i.types[j].bitfield.tbyte
1573 && !t->operand_types[j].bitfield.tbyte)
1574 || (i.types[j].bitfield.xmmword
1575 && !t->operand_types[j].bitfield.xmmword)
1576 || (i.types[j].bitfield.ymmword
1577 && !t->operand_types[j].bitfield.ymmword)));
1578 }
1579
1580 /* Return 1 if there is no size conflict on any operands for
1581 instruction template T. */
1582
1583 static INLINE int
1584 operand_size_match (const insn_template *t)
1585 {
1586 unsigned int j;
1587 int match = 1;
1588
1589 /* Don't check jump instructions. */
1590 if (t->opcode_modifier.jump
1591 || t->opcode_modifier.jumpbyte
1592 || t->opcode_modifier.jumpdword
1593 || t->opcode_modifier.jumpintersegment)
1594 return match;
1595
1596 /* Check memory and accumulator operand size. */
1597 for (j = 0; j < i.operands; j++)
1598 {
1599 if (t->operand_types[j].bitfield.anysize)
1600 continue;
1601
1602 if (t->operand_types[j].bitfield.acc && !match_reg_size (t, j))
1603 {
1604 match = 0;
1605 break;
1606 }
1607
1608 if (i.types[j].bitfield.mem && !match_mem_size (t, j))
1609 {
1610 match = 0;
1611 break;
1612 }
1613 }
1614
1615 if (match)
1616 return match;
1617 else if (!t->opcode_modifier.d && !t->opcode_modifier.floatd)
1618 {
1619 mismatch:
1620 i.error = operand_size_mismatch;
1621 return 0;
1622 }
1623
1624 /* Check reverse. */
1625 gas_assert (i.operands == 2);
1626
1627 match = 1;
1628 for (j = 0; j < 2; j++)
1629 {
1630 if (t->operand_types[j].bitfield.acc
1631 && !match_reg_size (t, j ? 0 : 1))
1632 goto mismatch;
1633
1634 if (i.types[j].bitfield.mem
1635 && !match_mem_size (t, j ? 0 : 1))
1636 goto mismatch;
1637 }
1638
1639 return match;
1640 }
1641
1642 static INLINE int
1643 operand_type_match (i386_operand_type overlap,
1644 i386_operand_type given)
1645 {
1646 i386_operand_type temp = overlap;
1647
1648 temp.bitfield.jumpabsolute = 0;
1649 temp.bitfield.unspecified = 0;
1650 temp.bitfield.byte = 0;
1651 temp.bitfield.word = 0;
1652 temp.bitfield.dword = 0;
1653 temp.bitfield.fword = 0;
1654 temp.bitfield.qword = 0;
1655 temp.bitfield.tbyte = 0;
1656 temp.bitfield.xmmword = 0;
1657 temp.bitfield.ymmword = 0;
1658 if (operand_type_all_zero (&temp))
1659 goto mismatch;
1660
1661 if (given.bitfield.baseindex == overlap.bitfield.baseindex
1662 && given.bitfield.jumpabsolute == overlap.bitfield.jumpabsolute)
1663 return 1;
1664
1665 mismatch:
1666 i.error = operand_type_mismatch;
1667 return 0;
1668 }
1669
1670 /* If given types g0 and g1 are registers they must be of the same type
1671 unless the expected operand type register overlap is null.
1672 Note that Acc in a template matches every size of reg. */
1673
1674 static INLINE int
1675 operand_type_register_match (i386_operand_type m0,
1676 i386_operand_type g0,
1677 i386_operand_type t0,
1678 i386_operand_type m1,
1679 i386_operand_type g1,
1680 i386_operand_type t1)
1681 {
1682 if (!operand_type_check (g0, reg))
1683 return 1;
1684
1685 if (!operand_type_check (g1, reg))
1686 return 1;
1687
1688 if (g0.bitfield.reg8 == g1.bitfield.reg8
1689 && g0.bitfield.reg16 == g1.bitfield.reg16
1690 && g0.bitfield.reg32 == g1.bitfield.reg32
1691 && g0.bitfield.reg64 == g1.bitfield.reg64)
1692 return 1;
1693
1694 if (m0.bitfield.acc)
1695 {
1696 t0.bitfield.reg8 = 1;
1697 t0.bitfield.reg16 = 1;
1698 t0.bitfield.reg32 = 1;
1699 t0.bitfield.reg64 = 1;
1700 }
1701
1702 if (m1.bitfield.acc)
1703 {
1704 t1.bitfield.reg8 = 1;
1705 t1.bitfield.reg16 = 1;
1706 t1.bitfield.reg32 = 1;
1707 t1.bitfield.reg64 = 1;
1708 }
1709
1710 if (!(t0.bitfield.reg8 & t1.bitfield.reg8)
1711 && !(t0.bitfield.reg16 & t1.bitfield.reg16)
1712 && !(t0.bitfield.reg32 & t1.bitfield.reg32)
1713 && !(t0.bitfield.reg64 & t1.bitfield.reg64))
1714 return 1;
1715
1716 i.error = register_type_mismatch;
1717
1718 return 0;
1719 }
1720
1721 static INLINE unsigned int
1722 mode_from_disp_size (i386_operand_type t)
1723 {
1724 if (t.bitfield.disp8)
1725 return 1;
1726 else if (t.bitfield.disp16
1727 || t.bitfield.disp32
1728 || t.bitfield.disp32s)
1729 return 2;
1730 else
1731 return 0;
1732 }
1733
1734 static INLINE int
1735 fits_in_signed_byte (offsetT num)
1736 {
1737 return (num >= -128) && (num <= 127);
1738 }
1739
1740 static INLINE int
1741 fits_in_unsigned_byte (offsetT num)
1742 {
1743 return (num & 0xff) == num;
1744 }
1745
1746 static INLINE int
1747 fits_in_unsigned_word (offsetT num)
1748 {
1749 return (num & 0xffff) == num;
1750 }
1751
1752 static INLINE int
1753 fits_in_signed_word (offsetT num)
1754 {
1755 return (-32768 <= num) && (num <= 32767);
1756 }
1757
1758 static INLINE int
1759 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED)
1760 {
1761 #ifndef BFD64
1762 return 1;
1763 #else
1764 return (!(((offsetT) -1 << 31) & num)
1765 || (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
1766 #endif
1767 } /* fits_in_signed_long() */
1768
1769 static INLINE int
1770 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED)
1771 {
1772 #ifndef BFD64
1773 return 1;
1774 #else
1775 return (num & (((offsetT) 2 << 31) - 1)) == num;
1776 #endif
1777 } /* fits_in_unsigned_long() */
1778
1779 static INLINE int
1780 fits_in_imm4 (offsetT num)
1781 {
1782 return (num & 0xf) == num;
1783 }
1784
1785 static i386_operand_type
1786 smallest_imm_type (offsetT num)
1787 {
1788 i386_operand_type t;
1789
1790 operand_type_set (&t, 0);
1791 t.bitfield.imm64 = 1;
1792
1793 if (cpu_arch_tune != PROCESSOR_I486 && num == 1)
1794 {
1795 /* This code is disabled on the 486 because all the Imm1 forms
1796 in the opcode table are slower on the i486. They're the
1797 versions with the implicitly specified single-position
1798 displacement, which has another syntax if you really want to
1799 use that form. */
1800 t.bitfield.imm1 = 1;
1801 t.bitfield.imm8 = 1;
1802 t.bitfield.imm8s = 1;
1803 t.bitfield.imm16 = 1;
1804 t.bitfield.imm32 = 1;
1805 t.bitfield.imm32s = 1;
1806 }
1807 else if (fits_in_signed_byte (num))
1808 {
1809 t.bitfield.imm8 = 1;
1810 t.bitfield.imm8s = 1;
1811 t.bitfield.imm16 = 1;
1812 t.bitfield.imm32 = 1;
1813 t.bitfield.imm32s = 1;
1814 }
1815 else if (fits_in_unsigned_byte (num))
1816 {
1817 t.bitfield.imm8 = 1;
1818 t.bitfield.imm16 = 1;
1819 t.bitfield.imm32 = 1;
1820 t.bitfield.imm32s = 1;
1821 }
1822 else if (fits_in_signed_word (num) || fits_in_unsigned_word (num))
1823 {
1824 t.bitfield.imm16 = 1;
1825 t.bitfield.imm32 = 1;
1826 t.bitfield.imm32s = 1;
1827 }
1828 else if (fits_in_signed_long (num))
1829 {
1830 t.bitfield.imm32 = 1;
1831 t.bitfield.imm32s = 1;
1832 }
1833 else if (fits_in_unsigned_long (num))
1834 t.bitfield.imm32 = 1;
1835
1836 return t;
1837 }
1838
1839 static offsetT
1840 offset_in_range (offsetT val, int size)
1841 {
1842 addressT mask;
1843
1844 switch (size)
1845 {
1846 case 1: mask = ((addressT) 1 << 8) - 1; break;
1847 case 2: mask = ((addressT) 1 << 16) - 1; break;
1848 case 4: mask = ((addressT) 2 << 31) - 1; break;
1849 #ifdef BFD64
1850 case 8: mask = ((addressT) 2 << 63) - 1; break;
1851 #endif
1852 default: abort ();
1853 }
1854
1855 #ifdef BFD64
1856 /* If BFD64, sign extend val for 32bit address mode. */
1857 if (flag_code != CODE_64BIT
1858 || i.prefix[ADDR_PREFIX])
1859 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
1860 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
1861 #endif
1862
1863 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
1864 {
1865 char buf1[40], buf2[40];
1866
1867 sprint_value (buf1, val);
1868 sprint_value (buf2, val & mask);
1869 as_warn (_("%s shortened to %s"), buf1, buf2);
1870 }
1871 return val & mask;
1872 }
1873
1874 enum PREFIX_GROUP
1875 {
1876 PREFIX_EXIST = 0,
1877 PREFIX_LOCK,
1878 PREFIX_REP,
1879 PREFIX_OTHER
1880 };
1881
1882 /* Returns
1883 a. PREFIX_EXIST if attempting to add a prefix where one from the
1884 same class already exists.
1885 b. PREFIX_LOCK if lock prefix is added.
1886 c. PREFIX_REP if rep/repne prefix is added.
1887 d. PREFIX_OTHER if other prefix is added.
1888 */
1889
1890 static enum PREFIX_GROUP
1891 add_prefix (unsigned int prefix)
1892 {
1893 enum PREFIX_GROUP ret = PREFIX_OTHER;
1894 unsigned int q;
1895
1896 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
1897 && flag_code == CODE_64BIT)
1898 {
1899 if ((i.prefix[REX_PREFIX] & prefix & REX_W)
1900 || ((i.prefix[REX_PREFIX] & (REX_R | REX_X | REX_B))
1901 && (prefix & (REX_R | REX_X | REX_B))))
1902 ret = PREFIX_EXIST;
1903 q = REX_PREFIX;
1904 }
1905 else
1906 {
1907 switch (prefix)
1908 {
1909 default:
1910 abort ();
1911
1912 case CS_PREFIX_OPCODE:
1913 case DS_PREFIX_OPCODE:
1914 case ES_PREFIX_OPCODE:
1915 case FS_PREFIX_OPCODE:
1916 case GS_PREFIX_OPCODE:
1917 case SS_PREFIX_OPCODE:
1918 q = SEG_PREFIX;
1919 break;
1920
1921 case REPNE_PREFIX_OPCODE:
1922 case REPE_PREFIX_OPCODE:
1923 q = REP_PREFIX;
1924 ret = PREFIX_REP;
1925 break;
1926
1927 case LOCK_PREFIX_OPCODE:
1928 q = LOCK_PREFIX;
1929 ret = PREFIX_LOCK;
1930 break;
1931
1932 case FWAIT_OPCODE:
1933 q = WAIT_PREFIX;
1934 break;
1935
1936 case ADDR_PREFIX_OPCODE:
1937 q = ADDR_PREFIX;
1938 break;
1939
1940 case DATA_PREFIX_OPCODE:
1941 q = DATA_PREFIX;
1942 break;
1943 }
1944 if (i.prefix[q] != 0)
1945 ret = PREFIX_EXIST;
1946 }
1947
1948 if (ret)
1949 {
1950 if (!i.prefix[q])
1951 ++i.prefixes;
1952 i.prefix[q] |= prefix;
1953 }
1954 else
1955 as_bad (_("same type of prefix used twice"));
1956
1957 return ret;
1958 }
1959
1960 static void
1961 update_code_flag (int value, int check)
1962 {
1963 PRINTF_LIKE ((*as_error));
1964
1965 flag_code = (enum flag_code) value;
1966 if (flag_code == CODE_64BIT)
1967 {
1968 cpu_arch_flags.bitfield.cpu64 = 1;
1969 cpu_arch_flags.bitfield.cpuno64 = 0;
1970 }
1971 else
1972 {
1973 cpu_arch_flags.bitfield.cpu64 = 0;
1974 cpu_arch_flags.bitfield.cpuno64 = 1;
1975 }
1976 if (value == CODE_64BIT && !cpu_arch_flags.bitfield.cpulm )
1977 {
1978 if (check)
1979 as_error = as_fatal;
1980 else
1981 as_error = as_bad;
1982 (*as_error) (_("64bit mode not supported on `%s'."),
1983 cpu_arch_name ? cpu_arch_name : default_arch);
1984 }
1985 if (value == CODE_32BIT && !cpu_arch_flags.bitfield.cpui386)
1986 {
1987 if (check)
1988 as_error = as_fatal;
1989 else
1990 as_error = as_bad;
1991 (*as_error) (_("32bit mode not supported on `%s'."),
1992 cpu_arch_name ? cpu_arch_name : default_arch);
1993 }
1994 stackop_size = '\0';
1995 }
1996
1997 static void
1998 set_code_flag (int value)
1999 {
2000 update_code_flag (value, 0);
2001 }
2002
2003 static void
2004 set_16bit_gcc_code_flag (int new_code_flag)
2005 {
2006 flag_code = (enum flag_code) new_code_flag;
2007 if (flag_code != CODE_16BIT)
2008 abort ();
2009 cpu_arch_flags.bitfield.cpu64 = 0;
2010 cpu_arch_flags.bitfield.cpuno64 = 1;
2011 stackop_size = LONG_MNEM_SUFFIX;
2012 }
2013
2014 static void
2015 set_intel_syntax (int syntax_flag)
2016 {
2017 /* Find out if register prefixing is specified. */
2018 int ask_naked_reg = 0;
2019
2020 SKIP_WHITESPACE ();
2021 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2022 {
2023 char *string = input_line_pointer;
2024 int e = get_symbol_end ();
2025
2026 if (strcmp (string, "prefix") == 0)
2027 ask_naked_reg = 1;
2028 else if (strcmp (string, "noprefix") == 0)
2029 ask_naked_reg = -1;
2030 else
2031 as_bad (_("bad argument to syntax directive."));
2032 *input_line_pointer = e;
2033 }
2034 demand_empty_rest_of_line ();
2035
2036 intel_syntax = syntax_flag;
2037
2038 if (ask_naked_reg == 0)
2039 allow_naked_reg = (intel_syntax
2040 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
2041 else
2042 allow_naked_reg = (ask_naked_reg < 0);
2043
2044 expr_set_rank (O_full_ptr, syntax_flag ? 10 : 0);
2045
2046 identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0;
2047 identifier_chars['$'] = intel_syntax ? '$' : 0;
2048 register_prefix = allow_naked_reg ? "" : "%";
2049 }
2050
2051 static void
2052 set_intel_mnemonic (int mnemonic_flag)
2053 {
2054 intel_mnemonic = mnemonic_flag;
2055 }
2056
2057 static void
2058 set_allow_index_reg (int flag)
2059 {
2060 allow_index_reg = flag;
2061 }
2062
2063 static void
2064 set_sse_check (int dummy ATTRIBUTE_UNUSED)
2065 {
2066 SKIP_WHITESPACE ();
2067
2068 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2069 {
2070 char *string = input_line_pointer;
2071 int e = get_symbol_end ();
2072
2073 if (strcmp (string, "none") == 0)
2074 sse_check = sse_check_none;
2075 else if (strcmp (string, "warning") == 0)
2076 sse_check = sse_check_warning;
2077 else if (strcmp (string, "error") == 0)
2078 sse_check = sse_check_error;
2079 else
2080 as_bad (_("bad argument to sse_check directive."));
2081 *input_line_pointer = e;
2082 }
2083 else
2084 as_bad (_("missing argument for sse_check directive"));
2085
2086 demand_empty_rest_of_line ();
2087 }
2088
2089 static void
2090 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED,
2091 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
2092 {
2093 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2094 static const char *arch;
2095
2096 /* Intel LIOM is only supported on ELF. */
2097 if (!IS_ELF)
2098 return;
2099
2100 if (!arch)
2101 {
2102 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2103 use default_arch. */
2104 arch = cpu_arch_name;
2105 if (!arch)
2106 arch = default_arch;
2107 }
2108
2109 /* If we are targeting Intel L1OM, we must enable it. */
2110 if (get_elf_backend_data (stdoutput)->elf_machine_code != EM_L1OM
2111 || new_flag.bitfield.cpul1om)
2112 return;
2113
2114 as_bad (_("`%s' is not supported on `%s'"), name, arch);
2115 #endif
2116 }
2117
2118 static void
2119 set_cpu_arch (int dummy ATTRIBUTE_UNUSED)
2120 {
2121 SKIP_WHITESPACE ();
2122
2123 if (!is_end_of_line[(unsigned char) *input_line_pointer])
2124 {
2125 char *string = input_line_pointer;
2126 int e = get_symbol_end ();
2127 unsigned int j;
2128 i386_cpu_flags flags;
2129
2130 for (j = 0; j < ARRAY_SIZE (cpu_arch); j++)
2131 {
2132 if (strcmp (string, cpu_arch[j].name) == 0)
2133 {
2134 check_cpu_arch_compatible (string, cpu_arch[j].flags);
2135
2136 if (*string != '.')
2137 {
2138 cpu_arch_name = cpu_arch[j].name;
2139 cpu_sub_arch_name = NULL;
2140 cpu_arch_flags = cpu_arch[j].flags;
2141 if (flag_code == CODE_64BIT)
2142 {
2143 cpu_arch_flags.bitfield.cpu64 = 1;
2144 cpu_arch_flags.bitfield.cpuno64 = 0;
2145 }
2146 else
2147 {
2148 cpu_arch_flags.bitfield.cpu64 = 0;
2149 cpu_arch_flags.bitfield.cpuno64 = 1;
2150 }
2151 cpu_arch_isa = cpu_arch[j].type;
2152 cpu_arch_isa_flags = cpu_arch[j].flags;
2153 if (!cpu_arch_tune_set)
2154 {
2155 cpu_arch_tune = cpu_arch_isa;
2156 cpu_arch_tune_flags = cpu_arch_isa_flags;
2157 }
2158 break;
2159 }
2160
2161 if (!cpu_arch[j].negated)
2162 flags = cpu_flags_or (cpu_arch_flags,
2163 cpu_arch[j].flags);
2164 else
2165 flags = cpu_flags_and_not (cpu_arch_flags,
2166 cpu_arch[j].flags);
2167 if (!cpu_flags_equal (&flags, &cpu_arch_flags))
2168 {
2169 if (cpu_sub_arch_name)
2170 {
2171 char *name = cpu_sub_arch_name;
2172 cpu_sub_arch_name = concat (name,
2173 cpu_arch[j].name,
2174 (const char *) NULL);
2175 free (name);
2176 }
2177 else
2178 cpu_sub_arch_name = xstrdup (cpu_arch[j].name);
2179 cpu_arch_flags = flags;
2180 cpu_arch_isa_flags = flags;
2181 }
2182 *input_line_pointer = e;
2183 demand_empty_rest_of_line ();
2184 return;
2185 }
2186 }
2187 if (j >= ARRAY_SIZE (cpu_arch))
2188 as_bad (_("no such architecture: `%s'"), string);
2189
2190 *input_line_pointer = e;
2191 }
2192 else
2193 as_bad (_("missing cpu architecture"));
2194
2195 no_cond_jump_promotion = 0;
2196 if (*input_line_pointer == ','
2197 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
2198 {
2199 char *string = ++input_line_pointer;
2200 int e = get_symbol_end ();
2201
2202 if (strcmp (string, "nojumps") == 0)
2203 no_cond_jump_promotion = 1;
2204 else if (strcmp (string, "jumps") == 0)
2205 ;
2206 else
2207 as_bad (_("no such architecture modifier: `%s'"), string);
2208
2209 *input_line_pointer = e;
2210 }
2211
2212 demand_empty_rest_of_line ();
2213 }
2214
2215 enum bfd_architecture
2216 i386_arch (void)
2217 {
2218 if (cpu_arch_isa == PROCESSOR_L1OM)
2219 {
2220 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2221 || flag_code != CODE_64BIT)
2222 as_fatal (_("Intel L1OM is 64bit ELF only"));
2223 return bfd_arch_l1om;
2224 }
2225 else
2226 return bfd_arch_i386;
2227 }
2228
2229 unsigned long
2230 i386_mach ()
2231 {
2232 if (!strncmp (default_arch, "x86_64", 6))
2233 {
2234 if (cpu_arch_isa == PROCESSOR_L1OM)
2235 {
2236 if (OUTPUT_FLAVOR != bfd_target_elf_flavour
2237 || default_arch[6] != '\0')
2238 as_fatal (_("Intel L1OM is 64bit ELF only"));
2239 return bfd_mach_l1om;
2240 }
2241 else if (default_arch[6] == '\0')
2242 return bfd_mach_x86_64;
2243 else
2244 return bfd_mach_x64_32;
2245 }
2246 else if (!strcmp (default_arch, "i386"))
2247 return bfd_mach_i386_i386;
2248 else
2249 as_fatal (_("Unknown architecture"));
2250 }
2251 \f
2252 void
2253 md_begin ()
2254 {
2255 const char *hash_err;
2256
2257 /* Initialize op_hash hash table. */
2258 op_hash = hash_new ();
2259
2260 {
2261 const insn_template *optab;
2262 templates *core_optab;
2263
2264 /* Setup for loop. */
2265 optab = i386_optab;
2266 core_optab = (templates *) xmalloc (sizeof (templates));
2267 core_optab->start = optab;
2268
2269 while (1)
2270 {
2271 ++optab;
2272 if (optab->name == NULL
2273 || strcmp (optab->name, (optab - 1)->name) != 0)
2274 {
2275 /* different name --> ship out current template list;
2276 add to hash table; & begin anew. */
2277 core_optab->end = optab;
2278 hash_err = hash_insert (op_hash,
2279 (optab - 1)->name,
2280 (void *) core_optab);
2281 if (hash_err)
2282 {
2283 as_fatal (_("Internal Error: Can't hash %s: %s"),
2284 (optab - 1)->name,
2285 hash_err);
2286 }
2287 if (optab->name == NULL)
2288 break;
2289 core_optab = (templates *) xmalloc (sizeof (templates));
2290 core_optab->start = optab;
2291 }
2292 }
2293 }
2294
2295 /* Initialize reg_hash hash table. */
2296 reg_hash = hash_new ();
2297 {
2298 const reg_entry *regtab;
2299 unsigned int regtab_size = i386_regtab_size;
2300
2301 for (regtab = i386_regtab; regtab_size--; regtab++)
2302 {
2303 hash_err = hash_insert (reg_hash, regtab->reg_name, (void *) regtab);
2304 if (hash_err)
2305 as_fatal (_("Internal Error: Can't hash %s: %s"),
2306 regtab->reg_name,
2307 hash_err);
2308 }
2309 }
2310
2311 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2312 {
2313 int c;
2314 char *p;
2315
2316 for (c = 0; c < 256; c++)
2317 {
2318 if (ISDIGIT (c))
2319 {
2320 digit_chars[c] = c;
2321 mnemonic_chars[c] = c;
2322 register_chars[c] = c;
2323 operand_chars[c] = c;
2324 }
2325 else if (ISLOWER (c))
2326 {
2327 mnemonic_chars[c] = c;
2328 register_chars[c] = c;
2329 operand_chars[c] = c;
2330 }
2331 else if (ISUPPER (c))
2332 {
2333 mnemonic_chars[c] = TOLOWER (c);
2334 register_chars[c] = mnemonic_chars[c];
2335 operand_chars[c] = c;
2336 }
2337
2338 if (ISALPHA (c) || ISDIGIT (c))
2339 identifier_chars[c] = c;
2340 else if (c >= 128)
2341 {
2342 identifier_chars[c] = c;
2343 operand_chars[c] = c;
2344 }
2345 }
2346
2347 #ifdef LEX_AT
2348 identifier_chars['@'] = '@';
2349 #endif
2350 #ifdef LEX_QM
2351 identifier_chars['?'] = '?';
2352 operand_chars['?'] = '?';
2353 #endif
2354 digit_chars['-'] = '-';
2355 mnemonic_chars['_'] = '_';
2356 mnemonic_chars['-'] = '-';
2357 mnemonic_chars['.'] = '.';
2358 identifier_chars['_'] = '_';
2359 identifier_chars['.'] = '.';
2360
2361 for (p = operand_special_chars; *p != '\0'; p++)
2362 operand_chars[(unsigned char) *p] = *p;
2363 }
2364
2365 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2366 if (IS_ELF)
2367 {
2368 record_alignment (text_section, 2);
2369 record_alignment (data_section, 2);
2370 record_alignment (bss_section, 2);
2371 }
2372 #endif
2373
2374 if (flag_code == CODE_64BIT)
2375 {
2376 #if defined (OBJ_COFF) && defined (TE_PE)
2377 x86_dwarf2_return_column = (OUTPUT_FLAVOR == bfd_target_coff_flavour
2378 ? 32 : 16);
2379 #else
2380 x86_dwarf2_return_column = 16;
2381 #endif
2382 x86_cie_data_alignment = -8;
2383 }
2384 else
2385 {
2386 x86_dwarf2_return_column = 8;
2387 x86_cie_data_alignment = -4;
2388 }
2389 }
2390
2391 void
2392 i386_print_statistics (FILE *file)
2393 {
2394 hash_print_statistics (file, "i386 opcode", op_hash);
2395 hash_print_statistics (file, "i386 register", reg_hash);
2396 }
2397 \f
2398 #ifdef DEBUG386
2399
2400 /* Debugging routines for md_assemble. */
2401 static void pte (insn_template *);
2402 static void pt (i386_operand_type);
2403 static void pe (expressionS *);
2404 static void ps (symbolS *);
2405
2406 static void
2407 pi (char *line, i386_insn *x)
2408 {
2409 unsigned int j;
2410
2411 fprintf (stdout, "%s: template ", line);
2412 pte (&x->tm);
2413 fprintf (stdout, " address: base %s index %s scale %x\n",
2414 x->base_reg ? x->base_reg->reg_name : "none",
2415 x->index_reg ? x->index_reg->reg_name : "none",
2416 x->log2_scale_factor);
2417 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
2418 x->rm.mode, x->rm.reg, x->rm.regmem);
2419 fprintf (stdout, " sib: base %x index %x scale %x\n",
2420 x->sib.base, x->sib.index, x->sib.scale);
2421 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
2422 (x->rex & REX_W) != 0,
2423 (x->rex & REX_R) != 0,
2424 (x->rex & REX_X) != 0,
2425 (x->rex & REX_B) != 0);
2426 for (j = 0; j < x->operands; j++)
2427 {
2428 fprintf (stdout, " #%d: ", j + 1);
2429 pt (x->types[j]);
2430 fprintf (stdout, "\n");
2431 if (x->types[j].bitfield.reg8
2432 || x->types[j].bitfield.reg16
2433 || x->types[j].bitfield.reg32
2434 || x->types[j].bitfield.reg64
2435 || x->types[j].bitfield.regmmx
2436 || x->types[j].bitfield.regxmm
2437 || x->types[j].bitfield.regymm
2438 || x->types[j].bitfield.sreg2
2439 || x->types[j].bitfield.sreg3
2440 || x->types[j].bitfield.control
2441 || x->types[j].bitfield.debug
2442 || x->types[j].bitfield.test)
2443 fprintf (stdout, "%s\n", x->op[j].regs->reg_name);
2444 if (operand_type_check (x->types[j], imm))
2445 pe (x->op[j].imms);
2446 if (operand_type_check (x->types[j], disp))
2447 pe (x->op[j].disps);
2448 }
2449 }
2450
2451 static void
2452 pte (insn_template *t)
2453 {
2454 unsigned int j;
2455 fprintf (stdout, " %d operands ", t->operands);
2456 fprintf (stdout, "opcode %x ", t->base_opcode);
2457 if (t->extension_opcode != None)
2458 fprintf (stdout, "ext %x ", t->extension_opcode);
2459 if (t->opcode_modifier.d)
2460 fprintf (stdout, "D");
2461 if (t->opcode_modifier.w)
2462 fprintf (stdout, "W");
2463 fprintf (stdout, "\n");
2464 for (j = 0; j < t->operands; j++)
2465 {
2466 fprintf (stdout, " #%d type ", j + 1);
2467 pt (t->operand_types[j]);
2468 fprintf (stdout, "\n");
2469 }
2470 }
2471
2472 static void
2473 pe (expressionS *e)
2474 {
2475 fprintf (stdout, " operation %d\n", e->X_op);
2476 fprintf (stdout, " add_number %ld (%lx)\n",
2477 (long) e->X_add_number, (long) e->X_add_number);
2478 if (e->X_add_symbol)
2479 {
2480 fprintf (stdout, " add_symbol ");
2481 ps (e->X_add_symbol);
2482 fprintf (stdout, "\n");
2483 }
2484 if (e->X_op_symbol)
2485 {
2486 fprintf (stdout, " op_symbol ");
2487 ps (e->X_op_symbol);
2488 fprintf (stdout, "\n");
2489 }
2490 }
2491
2492 static void
2493 ps (symbolS *s)
2494 {
2495 fprintf (stdout, "%s type %s%s",
2496 S_GET_NAME (s),
2497 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
2498 segment_name (S_GET_SEGMENT (s)));
2499 }
2500
2501 static struct type_name
2502 {
2503 i386_operand_type mask;
2504 const char *name;
2505 }
2506 const type_names[] =
2507 {
2508 { OPERAND_TYPE_REG8, "r8" },
2509 { OPERAND_TYPE_REG16, "r16" },
2510 { OPERAND_TYPE_REG32, "r32" },
2511 { OPERAND_TYPE_REG64, "r64" },
2512 { OPERAND_TYPE_IMM8, "i8" },
2513 { OPERAND_TYPE_IMM8, "i8s" },
2514 { OPERAND_TYPE_IMM16, "i16" },
2515 { OPERAND_TYPE_IMM32, "i32" },
2516 { OPERAND_TYPE_IMM32S, "i32s" },
2517 { OPERAND_TYPE_IMM64, "i64" },
2518 { OPERAND_TYPE_IMM1, "i1" },
2519 { OPERAND_TYPE_BASEINDEX, "BaseIndex" },
2520 { OPERAND_TYPE_DISP8, "d8" },
2521 { OPERAND_TYPE_DISP16, "d16" },
2522 { OPERAND_TYPE_DISP32, "d32" },
2523 { OPERAND_TYPE_DISP32S, "d32s" },
2524 { OPERAND_TYPE_DISP64, "d64" },
2525 { OPERAND_TYPE_INOUTPORTREG, "InOutPortReg" },
2526 { OPERAND_TYPE_SHIFTCOUNT, "ShiftCount" },
2527 { OPERAND_TYPE_CONTROL, "control reg" },
2528 { OPERAND_TYPE_TEST, "test reg" },
2529 { OPERAND_TYPE_DEBUG, "debug reg" },
2530 { OPERAND_TYPE_FLOATREG, "FReg" },
2531 { OPERAND_TYPE_FLOATACC, "FAcc" },
2532 { OPERAND_TYPE_SREG2, "SReg2" },
2533 { OPERAND_TYPE_SREG3, "SReg3" },
2534 { OPERAND_TYPE_ACC, "Acc" },
2535 { OPERAND_TYPE_JUMPABSOLUTE, "Jump Absolute" },
2536 { OPERAND_TYPE_REGMMX, "rMMX" },
2537 { OPERAND_TYPE_REGXMM, "rXMM" },
2538 { OPERAND_TYPE_REGYMM, "rYMM" },
2539 { OPERAND_TYPE_ESSEG, "es" },
2540 };
2541
2542 static void
2543 pt (i386_operand_type t)
2544 {
2545 unsigned int j;
2546 i386_operand_type a;
2547
2548 for (j = 0; j < ARRAY_SIZE (type_names); j++)
2549 {
2550 a = operand_type_and (t, type_names[j].mask);
2551 if (!operand_type_all_zero (&a))
2552 fprintf (stdout, "%s, ", type_names[j].name);
2553 }
2554 fflush (stdout);
2555 }
2556
2557 #endif /* DEBUG386 */
2558 \f
2559 static bfd_reloc_code_real_type
2560 reloc (unsigned int size,
2561 int pcrel,
2562 int sign,
2563 bfd_reloc_code_real_type other)
2564 {
2565 if (other != NO_RELOC)
2566 {
2567 reloc_howto_type *rel;
2568
2569 if (size == 8)
2570 switch (other)
2571 {
2572 case BFD_RELOC_X86_64_GOT32:
2573 return BFD_RELOC_X86_64_GOT64;
2574 break;
2575 case BFD_RELOC_X86_64_PLTOFF64:
2576 return BFD_RELOC_X86_64_PLTOFF64;
2577 break;
2578 case BFD_RELOC_X86_64_GOTPC32:
2579 other = BFD_RELOC_X86_64_GOTPC64;
2580 break;
2581 case BFD_RELOC_X86_64_GOTPCREL:
2582 other = BFD_RELOC_X86_64_GOTPCREL64;
2583 break;
2584 case BFD_RELOC_X86_64_TPOFF32:
2585 other = BFD_RELOC_X86_64_TPOFF64;
2586 break;
2587 case BFD_RELOC_X86_64_DTPOFF32:
2588 other = BFD_RELOC_X86_64_DTPOFF64;
2589 break;
2590 default:
2591 break;
2592 }
2593
2594 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2595 if (size == 4 && (flag_code != CODE_64BIT || disallow_64bit_reloc))
2596 sign = -1;
2597
2598 rel = bfd_reloc_type_lookup (stdoutput, other);
2599 if (!rel)
2600 as_bad (_("unknown relocation (%u)"), other);
2601 else if (size != bfd_get_reloc_size (rel))
2602 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2603 bfd_get_reloc_size (rel),
2604 size);
2605 else if (pcrel && !rel->pc_relative)
2606 as_bad (_("non-pc-relative relocation for pc-relative field"));
2607 else if ((rel->complain_on_overflow == complain_overflow_signed
2608 && !sign)
2609 || (rel->complain_on_overflow == complain_overflow_unsigned
2610 && sign > 0))
2611 as_bad (_("relocated field and relocation type differ in signedness"));
2612 else
2613 return other;
2614 return NO_RELOC;
2615 }
2616
2617 if (pcrel)
2618 {
2619 if (!sign)
2620 as_bad (_("there are no unsigned pc-relative relocations"));
2621 switch (size)
2622 {
2623 case 1: return BFD_RELOC_8_PCREL;
2624 case 2: return BFD_RELOC_16_PCREL;
2625 case 4: return BFD_RELOC_32_PCREL;
2626 case 8: return BFD_RELOC_64_PCREL;
2627 }
2628 as_bad (_("cannot do %u byte pc-relative relocation"), size);
2629 }
2630 else
2631 {
2632 if (sign > 0)
2633 switch (size)
2634 {
2635 case 4: return BFD_RELOC_X86_64_32S;
2636 }
2637 else
2638 switch (size)
2639 {
2640 case 1: return BFD_RELOC_8;
2641 case 2: return BFD_RELOC_16;
2642 case 4: return BFD_RELOC_32;
2643 case 8: return BFD_RELOC_64;
2644 }
2645 as_bad (_("cannot do %s %u byte relocation"),
2646 sign > 0 ? "signed" : "unsigned", size);
2647 }
2648
2649 return NO_RELOC;
2650 }
2651
2652 /* Here we decide which fixups can be adjusted to make them relative to
2653 the beginning of the section instead of the symbol. Basically we need
2654 to make sure that the dynamic relocations are done correctly, so in
2655 some cases we force the original symbol to be used. */
2656
2657 int
2658 tc_i386_fix_adjustable (fixS *fixP ATTRIBUTE_UNUSED)
2659 {
2660 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2661 if (!IS_ELF)
2662 return 1;
2663
2664 /* Don't adjust pc-relative references to merge sections in 64-bit
2665 mode. */
2666 if (use_rela_relocations
2667 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
2668 && fixP->fx_pcrel)
2669 return 0;
2670
2671 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2672 and changed later by validate_fix. */
2673 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
2674 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
2675 return 0;
2676
2677 /* adjust_reloc_syms doesn't know about the GOT. */
2678 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
2679 || fixP->fx_r_type == BFD_RELOC_386_PLT32
2680 || fixP->fx_r_type == BFD_RELOC_386_GOT32
2681 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
2682 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
2683 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
2684 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
2685 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
2686 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
2687 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
2688 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
2689 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC
2690 || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL
2691 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
2692 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
2693 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
2694 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
2695 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
2696 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
2697 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64
2698 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
2699 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
2700 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64
2701 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64
2702 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC
2703 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL
2704 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
2705 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
2706 return 0;
2707 #endif
2708 return 1;
2709 }
2710
2711 static int
2712 intel_float_operand (const char *mnemonic)
2713 {
2714 /* Note that the value returned is meaningful only for opcodes with (memory)
2715 operands, hence the code here is free to improperly handle opcodes that
2716 have no operands (for better performance and smaller code). */
2717
2718 if (mnemonic[0] != 'f')
2719 return 0; /* non-math */
2720
2721 switch (mnemonic[1])
2722 {
2723 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2724 the fs segment override prefix not currently handled because no
2725 call path can make opcodes without operands get here */
2726 case 'i':
2727 return 2 /* integer op */;
2728 case 'l':
2729 if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e'))
2730 return 3; /* fldcw/fldenv */
2731 break;
2732 case 'n':
2733 if (mnemonic[2] != 'o' /* fnop */)
2734 return 3; /* non-waiting control op */
2735 break;
2736 case 'r':
2737 if (mnemonic[2] == 's')
2738 return 3; /* frstor/frstpm */
2739 break;
2740 case 's':
2741 if (mnemonic[2] == 'a')
2742 return 3; /* fsave */
2743 if (mnemonic[2] == 't')
2744 {
2745 switch (mnemonic[3])
2746 {
2747 case 'c': /* fstcw */
2748 case 'd': /* fstdw */
2749 case 'e': /* fstenv */
2750 case 's': /* fsts[gw] */
2751 return 3;
2752 }
2753 }
2754 break;
2755 case 'x':
2756 if (mnemonic[2] == 'r' || mnemonic[2] == 's')
2757 return 0; /* fxsave/fxrstor are not really math ops */
2758 break;
2759 }
2760
2761 return 1;
2762 }
2763
2764 /* Build the VEX prefix. */
2765
2766 static void
2767 build_vex_prefix (const insn_template *t)
2768 {
2769 unsigned int register_specifier;
2770 unsigned int implied_prefix;
2771 unsigned int vector_length;
2772
2773 /* Check register specifier. */
2774 if (i.vex.register_specifier)
2775 {
2776 register_specifier = i.vex.register_specifier->reg_num;
2777 if ((i.vex.register_specifier->reg_flags & RegRex))
2778 register_specifier += 8;
2779 register_specifier = ~register_specifier & 0xf;
2780 }
2781 else
2782 register_specifier = 0xf;
2783
2784 /* Use 2-byte VEX prefix by swappping destination and source
2785 operand. */
2786 if (!i.swap_operand
2787 && i.operands == i.reg_operands
2788 && i.tm.opcode_modifier.vexopcode == VEX0F
2789 && i.tm.opcode_modifier.s
2790 && i.rex == REX_B)
2791 {
2792 unsigned int xchg = i.operands - 1;
2793 union i386_op temp_op;
2794 i386_operand_type temp_type;
2795
2796 temp_type = i.types[xchg];
2797 i.types[xchg] = i.types[0];
2798 i.types[0] = temp_type;
2799 temp_op = i.op[xchg];
2800 i.op[xchg] = i.op[0];
2801 i.op[0] = temp_op;
2802
2803 gas_assert (i.rm.mode == 3);
2804
2805 i.rex = REX_R;
2806 xchg = i.rm.regmem;
2807 i.rm.regmem = i.rm.reg;
2808 i.rm.reg = xchg;
2809
2810 /* Use the next insn. */
2811 i.tm = t[1];
2812 }
2813
2814 if (i.tm.opcode_modifier.vex == VEXScalar)
2815 vector_length = avxscalar;
2816 else
2817 vector_length = i.tm.opcode_modifier.vex == VEX256 ? 1 : 0;
2818
2819 switch ((i.tm.base_opcode >> 8) & 0xff)
2820 {
2821 case 0:
2822 implied_prefix = 0;
2823 break;
2824 case DATA_PREFIX_OPCODE:
2825 implied_prefix = 1;
2826 break;
2827 case REPE_PREFIX_OPCODE:
2828 implied_prefix = 2;
2829 break;
2830 case REPNE_PREFIX_OPCODE:
2831 implied_prefix = 3;
2832 break;
2833 default:
2834 abort ();
2835 }
2836
2837 /* Use 2-byte VEX prefix if possible. */
2838 if (i.tm.opcode_modifier.vexopcode == VEX0F
2839 && i.tm.opcode_modifier.vexw != VEXW1
2840 && (i.rex & (REX_W | REX_X | REX_B)) == 0)
2841 {
2842 /* 2-byte VEX prefix. */
2843 unsigned int r;
2844
2845 i.vex.length = 2;
2846 i.vex.bytes[0] = 0xc5;
2847
2848 /* Check the REX.R bit. */
2849 r = (i.rex & REX_R) ? 0 : 1;
2850 i.vex.bytes[1] = (r << 7
2851 | register_specifier << 3
2852 | vector_length << 2
2853 | implied_prefix);
2854 }
2855 else
2856 {
2857 /* 3-byte VEX prefix. */
2858 unsigned int m, w;
2859
2860 i.vex.length = 3;
2861
2862 switch (i.tm.opcode_modifier.vexopcode)
2863 {
2864 case VEX0F:
2865 m = 0x1;
2866 i.vex.bytes[0] = 0xc4;
2867 break;
2868 case VEX0F38:
2869 m = 0x2;
2870 i.vex.bytes[0] = 0xc4;
2871 break;
2872 case VEX0F3A:
2873 m = 0x3;
2874 i.vex.bytes[0] = 0xc4;
2875 break;
2876 case XOP08:
2877 m = 0x8;
2878 i.vex.bytes[0] = 0x8f;
2879 break;
2880 case XOP09:
2881 m = 0x9;
2882 i.vex.bytes[0] = 0x8f;
2883 break;
2884 case XOP0A:
2885 m = 0xa;
2886 i.vex.bytes[0] = 0x8f;
2887 break;
2888 default:
2889 abort ();
2890 }
2891
2892 /* The high 3 bits of the second VEX byte are 1's compliment
2893 of RXB bits from REX. */
2894 i.vex.bytes[1] = (~i.rex & 0x7) << 5 | m;
2895
2896 /* Check the REX.W bit. */
2897 w = (i.rex & REX_W) ? 1 : 0;
2898 if (i.tm.opcode_modifier.vexw)
2899 {
2900 if (w)
2901 abort ();
2902
2903 if (i.tm.opcode_modifier.vexw == VEXW1)
2904 w = 1;
2905 }
2906
2907 i.vex.bytes[2] = (w << 7
2908 | register_specifier << 3
2909 | vector_length << 2
2910 | implied_prefix);
2911 }
2912 }
2913
2914 static void
2915 process_immext (void)
2916 {
2917 expressionS *exp;
2918
2919 if (i.tm.cpu_flags.bitfield.cpusse3 && i.operands > 0)
2920 {
2921 /* SSE3 Instructions have the fixed operands with an opcode
2922 suffix which is coded in the same place as an 8-bit immediate
2923 field would be. Here we check those operands and remove them
2924 afterwards. */
2925 unsigned int x;
2926
2927 for (x = 0; x < i.operands; x++)
2928 if (i.op[x].regs->reg_num != x)
2929 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2930 register_prefix, i.op[x].regs->reg_name, x + 1,
2931 i.tm.name);
2932
2933 i.operands = 0;
2934 }
2935
2936 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2937 which is coded in the same place as an 8-bit immediate field
2938 would be. Here we fake an 8-bit immediate operand from the
2939 opcode suffix stored in tm.extension_opcode.
2940
2941 AVX instructions also use this encoding, for some of
2942 3 argument instructions. */
2943
2944 gas_assert (i.imm_operands == 0
2945 && (i.operands <= 2
2946 || (i.tm.opcode_modifier.vex
2947 && i.operands <= 4)));
2948
2949 exp = &im_expressions[i.imm_operands++];
2950 i.op[i.operands].imms = exp;
2951 i.types[i.operands] = imm8;
2952 i.operands++;
2953 exp->X_op = O_constant;
2954 exp->X_add_number = i.tm.extension_opcode;
2955 i.tm.extension_opcode = None;
2956 }
2957
2958 /* This is the guts of the machine-dependent assembler. LINE points to a
2959 machine dependent instruction. This function is supposed to emit
2960 the frags/bytes it assembles to. */
2961
2962 void
2963 md_assemble (char *line)
2964 {
2965 unsigned int j;
2966 char mnemonic[MAX_MNEM_SIZE];
2967 const insn_template *t;
2968
2969 /* Initialize globals. */
2970 memset (&i, '\0', sizeof (i));
2971 for (j = 0; j < MAX_OPERANDS; j++)
2972 i.reloc[j] = NO_RELOC;
2973 memset (disp_expressions, '\0', sizeof (disp_expressions));
2974 memset (im_expressions, '\0', sizeof (im_expressions));
2975 save_stack_p = save_stack;
2976
2977 /* First parse an instruction mnemonic & call i386_operand for the operands.
2978 We assume that the scrubber has arranged it so that line[0] is the valid
2979 start of a (possibly prefixed) mnemonic. */
2980
2981 line = parse_insn (line, mnemonic);
2982 if (line == NULL)
2983 return;
2984
2985 line = parse_operands (line, mnemonic);
2986 this_operand = -1;
2987 if (line == NULL)
2988 return;
2989
2990 /* Now we've parsed the mnemonic into a set of templates, and have the
2991 operands at hand. */
2992
2993 /* All intel opcodes have reversed operands except for "bound" and
2994 "enter". We also don't reverse intersegment "jmp" and "call"
2995 instructions with 2 immediate operands so that the immediate segment
2996 precedes the offset, as it does when in AT&T mode. */
2997 if (intel_syntax
2998 && i.operands > 1
2999 && (strcmp (mnemonic, "bound") != 0)
3000 && (strcmp (mnemonic, "invlpga") != 0)
3001 && !(operand_type_check (i.types[0], imm)
3002 && operand_type_check (i.types[1], imm)))
3003 swap_operands ();
3004
3005 /* The order of the immediates should be reversed
3006 for 2 immediates extrq and insertq instructions */
3007 if (i.imm_operands == 2
3008 && (strcmp (mnemonic, "extrq") == 0
3009 || strcmp (mnemonic, "insertq") == 0))
3010 swap_2_operands (0, 1);
3011
3012 if (i.imm_operands)
3013 optimize_imm ();
3014
3015 /* Don't optimize displacement for movabs since it only takes 64bit
3016 displacement. */
3017 if (i.disp_operands
3018 && !i.disp32_encoding
3019 && (flag_code != CODE_64BIT
3020 || strcmp (mnemonic, "movabs") != 0))
3021 optimize_disp ();
3022
3023 /* Next, we find a template that matches the given insn,
3024 making sure the overlap of the given operands types is consistent
3025 with the template operand types. */
3026
3027 if (!(t = match_template ()))
3028 return;
3029
3030 if (sse_check != sse_check_none
3031 && !i.tm.opcode_modifier.noavx
3032 && (i.tm.cpu_flags.bitfield.cpusse
3033 || i.tm.cpu_flags.bitfield.cpusse2
3034 || i.tm.cpu_flags.bitfield.cpusse3
3035 || i.tm.cpu_flags.bitfield.cpussse3
3036 || i.tm.cpu_flags.bitfield.cpusse4_1
3037 || i.tm.cpu_flags.bitfield.cpusse4_2))
3038 {
3039 (sse_check == sse_check_warning
3040 ? as_warn
3041 : as_bad) (_("SSE instruction `%s' is used"), i.tm.name);
3042 }
3043
3044 /* Zap movzx and movsx suffix. The suffix has been set from
3045 "word ptr" or "byte ptr" on the source operand in Intel syntax
3046 or extracted from mnemonic in AT&T syntax. But we'll use
3047 the destination register to choose the suffix for encoding. */
3048 if ((i.tm.base_opcode & ~9) == 0x0fb6)
3049 {
3050 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3051 there is no suffix, the default will be byte extension. */
3052 if (i.reg_operands != 2
3053 && !i.suffix
3054 && intel_syntax)
3055 as_bad (_("ambiguous operand size for `%s'"), i.tm.name);
3056
3057 i.suffix = 0;
3058 }
3059
3060 if (i.tm.opcode_modifier.fwait)
3061 if (!add_prefix (FWAIT_OPCODE))
3062 return;
3063
3064 /* Check for lock without a lockable instruction. Destination operand
3065 must be memory unless it is xchg (0x86). */
3066 if (i.prefix[LOCK_PREFIX]
3067 && (!i.tm.opcode_modifier.islockable
3068 || i.mem_operands == 0
3069 || (i.tm.base_opcode != 0x86
3070 && !operand_type_check (i.types[i.operands - 1], anymem))))
3071 {
3072 as_bad (_("expecting lockable instruction after `lock'"));
3073 return;
3074 }
3075
3076 /* Check string instruction segment overrides. */
3077 if (i.tm.opcode_modifier.isstring && i.mem_operands != 0)
3078 {
3079 if (!check_string ())
3080 return;
3081 i.disp_operands = 0;
3082 }
3083
3084 if (!process_suffix ())
3085 return;
3086
3087 /* Update operand types. */
3088 for (j = 0; j < i.operands; j++)
3089 i.types[j] = operand_type_and (i.types[j], i.tm.operand_types[j]);
3090
3091 /* Make still unresolved immediate matches conform to size of immediate
3092 given in i.suffix. */
3093 if (!finalize_imm ())
3094 return;
3095
3096 if (i.types[0].bitfield.imm1)
3097 i.imm_operands = 0; /* kludge for shift insns. */
3098
3099 /* We only need to check those implicit registers for instructions
3100 with 3 operands or less. */
3101 if (i.operands <= 3)
3102 for (j = 0; j < i.operands; j++)
3103 if (i.types[j].bitfield.inoutportreg
3104 || i.types[j].bitfield.shiftcount
3105 || i.types[j].bitfield.acc
3106 || i.types[j].bitfield.floatacc)
3107 i.reg_operands--;
3108
3109 /* ImmExt should be processed after SSE2AVX. */
3110 if (!i.tm.opcode_modifier.sse2avx
3111 && i.tm.opcode_modifier.immext)
3112 process_immext ();
3113
3114 /* For insns with operands there are more diddles to do to the opcode. */
3115 if (i.operands)
3116 {
3117 if (!process_operands ())
3118 return;
3119 }
3120 else if (!quiet_warnings && i.tm.opcode_modifier.ugh)
3121 {
3122 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3123 as_warn (_("translating to `%sp'"), i.tm.name);
3124 }
3125
3126 if (i.tm.opcode_modifier.vex)
3127 build_vex_prefix (t);
3128
3129 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3130 instructions may define INT_OPCODE as well, so avoid this corner
3131 case for those instructions that use MODRM. */
3132 if (i.tm.base_opcode == INT_OPCODE
3133 && !i.tm.opcode_modifier.modrm
3134 && i.op[0].imms->X_add_number == 3)
3135 {
3136 i.tm.base_opcode = INT3_OPCODE;
3137 i.imm_operands = 0;
3138 }
3139
3140 if ((i.tm.opcode_modifier.jump
3141 || i.tm.opcode_modifier.jumpbyte
3142 || i.tm.opcode_modifier.jumpdword)
3143 && i.op[0].disps->X_op == O_constant)
3144 {
3145 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3146 the absolute address given by the constant. Since ix86 jumps and
3147 calls are pc relative, we need to generate a reloc. */
3148 i.op[0].disps->X_add_symbol = &abs_symbol;
3149 i.op[0].disps->X_op = O_symbol;
3150 }
3151
3152 if (i.tm.opcode_modifier.rex64)
3153 i.rex |= REX_W;
3154
3155 /* For 8 bit registers we need an empty rex prefix. Also if the
3156 instruction already has a prefix, we need to convert old
3157 registers to new ones. */
3158
3159 if ((i.types[0].bitfield.reg8
3160 && (i.op[0].regs->reg_flags & RegRex64) != 0)
3161 || (i.types[1].bitfield.reg8
3162 && (i.op[1].regs->reg_flags & RegRex64) != 0)
3163 || ((i.types[0].bitfield.reg8
3164 || i.types[1].bitfield.reg8)
3165 && i.rex != 0))
3166 {
3167 int x;
3168
3169 i.rex |= REX_OPCODE;
3170 for (x = 0; x < 2; x++)
3171 {
3172 /* Look for 8 bit operand that uses old registers. */
3173 if (i.types[x].bitfield.reg8
3174 && (i.op[x].regs->reg_flags & RegRex64) == 0)
3175 {
3176 /* In case it is "hi" register, give up. */
3177 if (i.op[x].regs->reg_num > 3)
3178 as_bad (_("can't encode register '%s%s' in an "
3179 "instruction requiring REX prefix."),
3180 register_prefix, i.op[x].regs->reg_name);
3181
3182 /* Otherwise it is equivalent to the extended register.
3183 Since the encoding doesn't change this is merely
3184 cosmetic cleanup for debug output. */
3185
3186 i.op[x].regs = i.op[x].regs + 8;
3187 }
3188 }
3189 }
3190
3191 if (i.rex != 0)
3192 add_prefix (REX_OPCODE | i.rex);
3193
3194 /* We are ready to output the insn. */
3195 output_insn ();
3196 }
3197
3198 static char *
3199 parse_insn (char *line, char *mnemonic)
3200 {
3201 char *l = line;
3202 char *token_start = l;
3203 char *mnem_p;
3204 int supported;
3205 const insn_template *t;
3206 char *dot_p = NULL;
3207
3208 /* Non-zero if we found a prefix only acceptable with string insns. */
3209 const char *expecting_string_instruction = NULL;
3210
3211 while (1)
3212 {
3213 mnem_p = mnemonic;
3214 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
3215 {
3216 if (*mnem_p == '.')
3217 dot_p = mnem_p;
3218 mnem_p++;
3219 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
3220 {
3221 as_bad (_("no such instruction: `%s'"), token_start);
3222 return NULL;
3223 }
3224 l++;
3225 }
3226 if (!is_space_char (*l)
3227 && *l != END_OF_INSN
3228 && (intel_syntax
3229 || (*l != PREFIX_SEPARATOR
3230 && *l != ',')))
3231 {
3232 as_bad (_("invalid character %s in mnemonic"),
3233 output_invalid (*l));
3234 return NULL;
3235 }
3236 if (token_start == l)
3237 {
3238 if (!intel_syntax && *l == PREFIX_SEPARATOR)
3239 as_bad (_("expecting prefix; got nothing"));
3240 else
3241 as_bad (_("expecting mnemonic; got nothing"));
3242 return NULL;
3243 }
3244
3245 /* Look up instruction (or prefix) via hash table. */
3246 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3247
3248 if (*l != END_OF_INSN
3249 && (!is_space_char (*l) || l[1] != END_OF_INSN)
3250 && current_templates
3251 && current_templates->start->opcode_modifier.isprefix)
3252 {
3253 if (!cpu_flags_check_cpu64 (current_templates->start->cpu_flags))
3254 {
3255 as_bad ((flag_code != CODE_64BIT
3256 ? _("`%s' is only supported in 64-bit mode")
3257 : _("`%s' is not supported in 64-bit mode")),
3258 current_templates->start->name);
3259 return NULL;
3260 }
3261 /* If we are in 16-bit mode, do not allow addr16 or data16.
3262 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3263 if ((current_templates->start->opcode_modifier.size16
3264 || current_templates->start->opcode_modifier.size32)
3265 && flag_code != CODE_64BIT
3266 && (current_templates->start->opcode_modifier.size32
3267 ^ (flag_code == CODE_16BIT)))
3268 {
3269 as_bad (_("redundant %s prefix"),
3270 current_templates->start->name);
3271 return NULL;
3272 }
3273 /* Add prefix, checking for repeated prefixes. */
3274 switch (add_prefix (current_templates->start->base_opcode))
3275 {
3276 case PREFIX_EXIST:
3277 return NULL;
3278 case PREFIX_REP:
3279 expecting_string_instruction = current_templates->start->name;
3280 break;
3281 default:
3282 break;
3283 }
3284 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3285 token_start = ++l;
3286 }
3287 else
3288 break;
3289 }
3290
3291 if (!current_templates)
3292 {
3293 /* Check if we should swap operand or force 32bit displacement in
3294 encoding. */
3295 if (mnem_p - 2 == dot_p && dot_p[1] == 's')
3296 i.swap_operand = 1;
3297 else if (mnem_p - 4 == dot_p
3298 && dot_p[1] == 'd'
3299 && dot_p[2] == '3'
3300 && dot_p[3] == '2')
3301 i.disp32_encoding = 1;
3302 else
3303 goto check_suffix;
3304 mnem_p = dot_p;
3305 *dot_p = '\0';
3306 current_templates = (const templates *) hash_find (op_hash, mnemonic);
3307 }
3308
3309 if (!current_templates)
3310 {
3311 check_suffix:
3312 /* See if we can get a match by trimming off a suffix. */
3313 switch (mnem_p[-1])
3314 {
3315 case WORD_MNEM_SUFFIX:
3316 if (intel_syntax && (intel_float_operand (mnemonic) & 2))
3317 i.suffix = SHORT_MNEM_SUFFIX;
3318 else
3319 case BYTE_MNEM_SUFFIX:
3320 case QWORD_MNEM_SUFFIX:
3321 i.suffix = mnem_p[-1];
3322 mnem_p[-1] = '\0';
3323 current_templates = (const templates *) hash_find (op_hash,
3324 mnemonic);
3325 break;
3326 case SHORT_MNEM_SUFFIX:
3327 case LONG_MNEM_SUFFIX:
3328 if (!intel_syntax)
3329 {
3330 i.suffix = mnem_p[-1];
3331 mnem_p[-1] = '\0';
3332 current_templates = (const templates *) hash_find (op_hash,
3333 mnemonic);
3334 }
3335 break;
3336
3337 /* Intel Syntax. */
3338 case 'd':
3339 if (intel_syntax)
3340 {
3341 if (intel_float_operand (mnemonic) == 1)
3342 i.suffix = SHORT_MNEM_SUFFIX;
3343 else
3344 i.suffix = LONG_MNEM_SUFFIX;
3345 mnem_p[-1] = '\0';
3346 current_templates = (const templates *) hash_find (op_hash,
3347 mnemonic);
3348 }
3349 break;
3350 }
3351 if (!current_templates)
3352 {
3353 as_bad (_("no such instruction: `%s'"), token_start);
3354 return NULL;
3355 }
3356 }
3357
3358 if (current_templates->start->opcode_modifier.jump
3359 || current_templates->start->opcode_modifier.jumpbyte)
3360 {
3361 /* Check for a branch hint. We allow ",pt" and ",pn" for
3362 predict taken and predict not taken respectively.
3363 I'm not sure that branch hints actually do anything on loop
3364 and jcxz insns (JumpByte) for current Pentium4 chips. They
3365 may work in the future and it doesn't hurt to accept them
3366 now. */
3367 if (l[0] == ',' && l[1] == 'p')
3368 {
3369 if (l[2] == 't')
3370 {
3371 if (!add_prefix (DS_PREFIX_OPCODE))
3372 return NULL;
3373 l += 3;
3374 }
3375 else if (l[2] == 'n')
3376 {
3377 if (!add_prefix (CS_PREFIX_OPCODE))
3378 return NULL;
3379 l += 3;
3380 }
3381 }
3382 }
3383 /* Any other comma loses. */
3384 if (*l == ',')
3385 {
3386 as_bad (_("invalid character %s in mnemonic"),
3387 output_invalid (*l));
3388 return NULL;
3389 }
3390
3391 /* Check if instruction is supported on specified architecture. */
3392 supported = 0;
3393 for (t = current_templates->start; t < current_templates->end; ++t)
3394 {
3395 supported |= cpu_flags_match (t);
3396 if (supported == CPU_FLAGS_PERFECT_MATCH)
3397 goto skip;
3398 }
3399
3400 if (!(supported & CPU_FLAGS_64BIT_MATCH))
3401 {
3402 as_bad (flag_code == CODE_64BIT
3403 ? _("`%s' is not supported in 64-bit mode")
3404 : _("`%s' is only supported in 64-bit mode"),
3405 current_templates->start->name);
3406 return NULL;
3407 }
3408 if (supported != CPU_FLAGS_PERFECT_MATCH)
3409 {
3410 as_bad (_("`%s' is not supported on `%s%s'"),
3411 current_templates->start->name,
3412 cpu_arch_name ? cpu_arch_name : default_arch,
3413 cpu_sub_arch_name ? cpu_sub_arch_name : "");
3414 return NULL;
3415 }
3416
3417 skip:
3418 if (!cpu_arch_flags.bitfield.cpui386
3419 && (flag_code != CODE_16BIT))
3420 {
3421 as_warn (_("use .code16 to ensure correct addressing mode"));
3422 }
3423
3424 /* Check for rep/repne without a string instruction. */
3425 if (expecting_string_instruction)
3426 {
3427 static templates override;
3428
3429 for (t = current_templates->start; t < current_templates->end; ++t)
3430 if (t->opcode_modifier.isstring)
3431 break;
3432 if (t >= current_templates->end)
3433 {
3434 as_bad (_("expecting string instruction after `%s'"),
3435 expecting_string_instruction);
3436 return NULL;
3437 }
3438 for (override.start = t; t < current_templates->end; ++t)
3439 if (!t->opcode_modifier.isstring)
3440 break;
3441 override.end = t;
3442 current_templates = &override;
3443 }
3444
3445 return l;
3446 }
3447
3448 static char *
3449 parse_operands (char *l, const char *mnemonic)
3450 {
3451 char *token_start;
3452
3453 /* 1 if operand is pending after ','. */
3454 unsigned int expecting_operand = 0;
3455
3456 /* Non-zero if operand parens not balanced. */
3457 unsigned int paren_not_balanced;
3458
3459 while (*l != END_OF_INSN)
3460 {
3461 /* Skip optional white space before operand. */
3462 if (is_space_char (*l))
3463 ++l;
3464 if (!is_operand_char (*l) && *l != END_OF_INSN)
3465 {
3466 as_bad (_("invalid character %s before operand %d"),
3467 output_invalid (*l),
3468 i.operands + 1);
3469 return NULL;
3470 }
3471 token_start = l; /* after white space */
3472 paren_not_balanced = 0;
3473 while (paren_not_balanced || *l != ',')
3474 {
3475 if (*l == END_OF_INSN)
3476 {
3477 if (paren_not_balanced)
3478 {
3479 if (!intel_syntax)
3480 as_bad (_("unbalanced parenthesis in operand %d."),
3481 i.operands + 1);
3482 else
3483 as_bad (_("unbalanced brackets in operand %d."),
3484 i.operands + 1);
3485 return NULL;
3486 }
3487 else
3488 break; /* we are done */
3489 }
3490 else if (!is_operand_char (*l) && !is_space_char (*l))
3491 {
3492 as_bad (_("invalid character %s in operand %d"),
3493 output_invalid (*l),
3494 i.operands + 1);
3495 return NULL;
3496 }
3497 if (!intel_syntax)
3498 {
3499 if (*l == '(')
3500 ++paren_not_balanced;
3501 if (*l == ')')
3502 --paren_not_balanced;
3503 }
3504 else
3505 {
3506 if (*l == '[')
3507 ++paren_not_balanced;
3508 if (*l == ']')
3509 --paren_not_balanced;
3510 }
3511 l++;
3512 }
3513 if (l != token_start)
3514 { /* Yes, we've read in another operand. */
3515 unsigned int operand_ok;
3516 this_operand = i.operands++;
3517 i.types[this_operand].bitfield.unspecified = 1;
3518 if (i.operands > MAX_OPERANDS)
3519 {
3520 as_bad (_("spurious operands; (%d operands/instruction max)"),
3521 MAX_OPERANDS);
3522 return NULL;
3523 }
3524 /* Now parse operand adding info to 'i' as we go along. */
3525 END_STRING_AND_SAVE (l);
3526
3527 if (intel_syntax)
3528 operand_ok =
3529 i386_intel_operand (token_start,
3530 intel_float_operand (mnemonic));
3531 else
3532 operand_ok = i386_att_operand (token_start);
3533
3534 RESTORE_END_STRING (l);
3535 if (!operand_ok)
3536 return NULL;
3537 }
3538 else
3539 {
3540 if (expecting_operand)
3541 {
3542 expecting_operand_after_comma:
3543 as_bad (_("expecting operand after ','; got nothing"));
3544 return NULL;
3545 }
3546 if (*l == ',')
3547 {
3548 as_bad (_("expecting operand before ','; got nothing"));
3549 return NULL;
3550 }
3551 }
3552
3553 /* Now *l must be either ',' or END_OF_INSN. */
3554 if (*l == ',')
3555 {
3556 if (*++l == END_OF_INSN)
3557 {
3558 /* Just skip it, if it's \n complain. */
3559 goto expecting_operand_after_comma;
3560 }
3561 expecting_operand = 1;
3562 }
3563 }
3564 return l;
3565 }
3566
3567 static void
3568 swap_2_operands (int xchg1, int xchg2)
3569 {
3570 union i386_op temp_op;
3571 i386_operand_type temp_type;
3572 enum bfd_reloc_code_real temp_reloc;
3573
3574 temp_type = i.types[xchg2];
3575 i.types[xchg2] = i.types[xchg1];
3576 i.types[xchg1] = temp_type;
3577 temp_op = i.op[xchg2];
3578 i.op[xchg2] = i.op[xchg1];
3579 i.op[xchg1] = temp_op;
3580 temp_reloc = i.reloc[xchg2];
3581 i.reloc[xchg2] = i.reloc[xchg1];
3582 i.reloc[xchg1] = temp_reloc;
3583 }
3584
3585 static void
3586 swap_operands (void)
3587 {
3588 switch (i.operands)
3589 {
3590 case 5:
3591 case 4:
3592 swap_2_operands (1, i.operands - 2);
3593 case 3:
3594 case 2:
3595 swap_2_operands (0, i.operands - 1);
3596 break;
3597 default:
3598 abort ();
3599 }
3600
3601 if (i.mem_operands == 2)
3602 {
3603 const seg_entry *temp_seg;
3604 temp_seg = i.seg[0];
3605 i.seg[0] = i.seg[1];
3606 i.seg[1] = temp_seg;
3607 }
3608 }
3609
3610 /* Try to ensure constant immediates are represented in the smallest
3611 opcode possible. */
3612 static void
3613 optimize_imm (void)
3614 {
3615 char guess_suffix = 0;
3616 int op;
3617
3618 if (i.suffix)
3619 guess_suffix = i.suffix;
3620 else if (i.reg_operands)
3621 {
3622 /* Figure out a suffix from the last register operand specified.
3623 We can't do this properly yet, ie. excluding InOutPortReg,
3624 but the following works for instructions with immediates.
3625 In any case, we can't set i.suffix yet. */
3626 for (op = i.operands; --op >= 0;)
3627 if (i.types[op].bitfield.reg8)
3628 {
3629 guess_suffix = BYTE_MNEM_SUFFIX;
3630 break;
3631 }
3632 else if (i.types[op].bitfield.reg16)
3633 {
3634 guess_suffix = WORD_MNEM_SUFFIX;
3635 break;
3636 }
3637 else if (i.types[op].bitfield.reg32)
3638 {
3639 guess_suffix = LONG_MNEM_SUFFIX;
3640 break;
3641 }
3642 else if (i.types[op].bitfield.reg64)
3643 {
3644 guess_suffix = QWORD_MNEM_SUFFIX;
3645 break;
3646 }
3647 }
3648 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
3649 guess_suffix = WORD_MNEM_SUFFIX;
3650
3651 for (op = i.operands; --op >= 0;)
3652 if (operand_type_check (i.types[op], imm))
3653 {
3654 switch (i.op[op].imms->X_op)
3655 {
3656 case O_constant:
3657 /* If a suffix is given, this operand may be shortened. */
3658 switch (guess_suffix)
3659 {
3660 case LONG_MNEM_SUFFIX:
3661 i.types[op].bitfield.imm32 = 1;
3662 i.types[op].bitfield.imm64 = 1;
3663 break;
3664 case WORD_MNEM_SUFFIX:
3665 i.types[op].bitfield.imm16 = 1;
3666 i.types[op].bitfield.imm32 = 1;
3667 i.types[op].bitfield.imm32s = 1;
3668 i.types[op].bitfield.imm64 = 1;
3669 break;
3670 case BYTE_MNEM_SUFFIX:
3671 i.types[op].bitfield.imm8 = 1;
3672 i.types[op].bitfield.imm8s = 1;
3673 i.types[op].bitfield.imm16 = 1;
3674 i.types[op].bitfield.imm32 = 1;
3675 i.types[op].bitfield.imm32s = 1;
3676 i.types[op].bitfield.imm64 = 1;
3677 break;
3678 }
3679
3680 /* If this operand is at most 16 bits, convert it
3681 to a signed 16 bit number before trying to see
3682 whether it will fit in an even smaller size.
3683 This allows a 16-bit operand such as $0xffe0 to
3684 be recognised as within Imm8S range. */
3685 if ((i.types[op].bitfield.imm16)
3686 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
3687 {
3688 i.op[op].imms->X_add_number =
3689 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
3690 }
3691 if ((i.types[op].bitfield.imm32)
3692 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
3693 == 0))
3694 {
3695 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
3696 ^ ((offsetT) 1 << 31))
3697 - ((offsetT) 1 << 31));
3698 }
3699 i.types[op]
3700 = operand_type_or (i.types[op],
3701 smallest_imm_type (i.op[op].imms->X_add_number));
3702
3703 /* We must avoid matching of Imm32 templates when 64bit
3704 only immediate is available. */
3705 if (guess_suffix == QWORD_MNEM_SUFFIX)
3706 i.types[op].bitfield.imm32 = 0;
3707 break;
3708
3709 case O_absent:
3710 case O_register:
3711 abort ();
3712
3713 /* Symbols and expressions. */
3714 default:
3715 /* Convert symbolic operand to proper sizes for matching, but don't
3716 prevent matching a set of insns that only supports sizes other
3717 than those matching the insn suffix. */
3718 {
3719 i386_operand_type mask, allowed;
3720 const insn_template *t;
3721
3722 operand_type_set (&mask, 0);
3723 operand_type_set (&allowed, 0);
3724
3725 for (t = current_templates->start;
3726 t < current_templates->end;
3727 ++t)
3728 allowed = operand_type_or (allowed,
3729 t->operand_types[op]);
3730 switch (guess_suffix)
3731 {
3732 case QWORD_MNEM_SUFFIX:
3733 mask.bitfield.imm64 = 1;
3734 mask.bitfield.imm32s = 1;
3735 break;
3736 case LONG_MNEM_SUFFIX:
3737 mask.bitfield.imm32 = 1;
3738 break;
3739 case WORD_MNEM_SUFFIX:
3740 mask.bitfield.imm16 = 1;
3741 break;
3742 case BYTE_MNEM_SUFFIX:
3743 mask.bitfield.imm8 = 1;
3744 break;
3745 default:
3746 break;
3747 }
3748 allowed = operand_type_and (mask, allowed);
3749 if (!operand_type_all_zero (&allowed))
3750 i.types[op] = operand_type_and (i.types[op], mask);
3751 }
3752 break;
3753 }
3754 }
3755 }
3756
3757 /* Try to use the smallest displacement type too. */
3758 static void
3759 optimize_disp (void)
3760 {
3761 int op;
3762
3763 for (op = i.operands; --op >= 0;)
3764 if (operand_type_check (i.types[op], disp))
3765 {
3766 if (i.op[op].disps->X_op == O_constant)
3767 {
3768 offsetT op_disp = i.op[op].disps->X_add_number;
3769
3770 if (i.types[op].bitfield.disp16
3771 && (op_disp & ~(offsetT) 0xffff) == 0)
3772 {
3773 /* If this operand is at most 16 bits, convert
3774 to a signed 16 bit number and don't use 64bit
3775 displacement. */
3776 op_disp = (((op_disp & 0xffff) ^ 0x8000) - 0x8000);
3777 i.types[op].bitfield.disp64 = 0;
3778 }
3779 if (i.types[op].bitfield.disp32
3780 && (op_disp & ~(((offsetT) 2 << 31) - 1)) == 0)
3781 {
3782 /* If this operand is at most 32 bits, convert
3783 to a signed 32 bit number and don't use 64bit
3784 displacement. */
3785 op_disp &= (((offsetT) 2 << 31) - 1);
3786 op_disp = (op_disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
3787 i.types[op].bitfield.disp64 = 0;
3788 }
3789 if (!op_disp && i.types[op].bitfield.baseindex)
3790 {
3791 i.types[op].bitfield.disp8 = 0;
3792 i.types[op].bitfield.disp16 = 0;
3793 i.types[op].bitfield.disp32 = 0;
3794 i.types[op].bitfield.disp32s = 0;
3795 i.types[op].bitfield.disp64 = 0;
3796 i.op[op].disps = 0;
3797 i.disp_operands--;
3798 }
3799 else if (flag_code == CODE_64BIT)
3800 {
3801 if (fits_in_signed_long (op_disp))
3802 {
3803 i.types[op].bitfield.disp64 = 0;
3804 i.types[op].bitfield.disp32s = 1;
3805 }
3806 if (i.prefix[ADDR_PREFIX]
3807 && fits_in_unsigned_long (op_disp))
3808 i.types[op].bitfield.disp32 = 1;
3809 }
3810 if ((i.types[op].bitfield.disp32
3811 || i.types[op].bitfield.disp32s
3812 || i.types[op].bitfield.disp16)
3813 && fits_in_signed_byte (op_disp))
3814 i.types[op].bitfield.disp8 = 1;
3815 }
3816 else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL
3817 || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)
3818 {
3819 fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0,
3820 i.op[op].disps, 0, i.reloc[op]);
3821 i.types[op].bitfield.disp8 = 0;
3822 i.types[op].bitfield.disp16 = 0;
3823 i.types[op].bitfield.disp32 = 0;
3824 i.types[op].bitfield.disp32s = 0;
3825 i.types[op].bitfield.disp64 = 0;
3826 }
3827 else
3828 /* We only support 64bit displacement on constants. */
3829 i.types[op].bitfield.disp64 = 0;
3830 }
3831 }
3832
3833 /* Check if operands are valid for the instruction. Update VEX
3834 operand types. */
3835
3836 static int
3837 VEX_check_operands (const insn_template *t)
3838 {
3839 if (!t->opcode_modifier.vex)
3840 return 0;
3841
3842 /* Only check VEX_Imm4, which must be the first operand. */
3843 if (t->operand_types[0].bitfield.vec_imm4)
3844 {
3845 if (i.op[0].imms->X_op != O_constant
3846 || !fits_in_imm4 (i.op[0].imms->X_add_number))
3847 {
3848 i.error = bad_imm4;
3849 return 1;
3850 }
3851
3852 /* Turn off Imm8 so that update_imm won't complain. */
3853 i.types[0] = vec_imm4;
3854 }
3855
3856 return 0;
3857 }
3858
3859 static const insn_template *
3860 match_template (void)