1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void update_code_flag (int, int);
139 static void set_code_flag (int);
140 static void set_16bit_gcc_code_flag (int);
141 static void set_intel_syntax (int);
142 static void set_intel_mnemonic (int);
143 static void set_allow_index_reg (int);
144 static void set_sse_check (int);
145 static void set_cpu_arch (int);
147 static void pe_directive_secrel (int);
149 static void signed_cons (int);
150 static char *output_invalid (int c
);
151 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
153 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
155 static int i386_att_operand (char *);
156 static int i386_intel_operand (char *, int);
157 static int i386_intel_simplify (expressionS
*);
158 static int i386_intel_parse_name (const char *, expressionS
*);
159 static const reg_entry
*parse_register (char *, char **);
160 static char *parse_insn (char *, char *);
161 static char *parse_operands (char *, const char *);
162 static void swap_operands (void);
163 static void swap_2_operands (int, int);
164 static void optimize_imm (void);
165 static void optimize_disp (void);
166 static const insn_template
*match_template (void);
167 static int check_string (void);
168 static int process_suffix (void);
169 static int check_byte_reg (void);
170 static int check_long_reg (void);
171 static int check_qword_reg (void);
172 static int check_word_reg (void);
173 static int finalize_imm (void);
174 static int process_operands (void);
175 static const seg_entry
*build_modrm_byte (void);
176 static void output_insn (void);
177 static void output_imm (fragS
*, offsetT
);
178 static void output_disp (fragS
*, offsetT
);
180 static void s_bss (int);
182 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
183 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
186 static const char *default_arch
= DEFAULT_ARCH
;
191 /* VEX prefix is either 2 byte or 3 byte. */
192 unsigned char bytes
[3];
194 /* Destination or source register specifier. */
195 const reg_entry
*register_specifier
;
198 /* 'md_assemble ()' gathers together information and puts it into a
205 const reg_entry
*regs
;
210 operand_size_mismatch
,
211 operand_type_mismatch
,
212 register_type_mismatch
,
213 number_of_operands_mismatch
,
214 invalid_instruction_suffix
,
217 unsupported_with_intel_mnemonic
,
224 /* TM holds the template for the insn were currently assembling. */
227 /* SUFFIX holds the instruction size suffix for byte, word, dword
228 or qword, if given. */
231 /* OPERANDS gives the number of given operands. */
232 unsigned int operands
;
234 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
235 of given register, displacement, memory operands and immediate
237 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
239 /* TYPES [i] is the type (see above #defines) which tells us how to
240 use OP[i] for the corresponding operand. */
241 i386_operand_type types
[MAX_OPERANDS
];
243 /* Displacement expression, immediate expression, or register for each
245 union i386_op op
[MAX_OPERANDS
];
247 /* Flags for operands. */
248 unsigned int flags
[MAX_OPERANDS
];
249 #define Operand_PCrel 1
251 /* Relocation type for operand */
252 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
254 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
255 the base index byte below. */
256 const reg_entry
*base_reg
;
257 const reg_entry
*index_reg
;
258 unsigned int log2_scale_factor
;
260 /* SEG gives the seg_entries of this insn. They are zero unless
261 explicit segment overrides are given. */
262 const seg_entry
*seg
[2];
264 /* PREFIX holds all the given prefix opcodes (usually null).
265 PREFIXES is the number of prefix opcodes. */
266 unsigned int prefixes
;
267 unsigned char prefix
[MAX_PREFIXES
];
269 /* RM and SIB are the modrm byte and the sib byte where the
270 addressing modes of this insn are encoded. */
276 /* Swap operand in encoding. */
277 unsigned int swap_operand
;
280 enum i386_error error
;
283 typedef struct _i386_insn i386_insn
;
285 /* List of chars besides those in app.c:symbol_chars that can start an
286 operand. Used to prevent the scrubber eating vital white-space. */
287 const char extra_symbol_chars
[] = "*%-(["
296 #if (defined (TE_I386AIX) \
297 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
298 && !defined (TE_GNU) \
299 && !defined (TE_LINUX) \
300 && !defined (TE_NETWARE) \
301 && !defined (TE_FreeBSD) \
302 && !defined (TE_NetBSD)))
303 /* This array holds the chars that always start a comment. If the
304 pre-processor is disabled, these aren't very useful. The option
305 --divide will remove '/' from this list. */
306 const char *i386_comment_chars
= "#/";
307 #define SVR4_COMMENT_CHARS 1
308 #define PREFIX_SEPARATOR '\\'
311 const char *i386_comment_chars
= "#";
312 #define PREFIX_SEPARATOR '/'
315 /* This array holds the chars that only start a comment at the beginning of
316 a line. If the line seems to have the form '# 123 filename'
317 .line and .file directives will appear in the pre-processed output.
318 Note that input_file.c hand checks for '#' at the beginning of the
319 first line of the input file. This is because the compiler outputs
320 #NO_APP at the beginning of its output.
321 Also note that comments started like this one will always work if
322 '/' isn't otherwise defined. */
323 const char line_comment_chars
[] = "#/";
325 const char line_separator_chars
[] = ";";
327 /* Chars that can be used to separate mant from exp in floating point
329 const char EXP_CHARS
[] = "eE";
331 /* Chars that mean this number is a floating point constant
334 const char FLT_CHARS
[] = "fFdDxX";
336 /* Tables for lexical analysis. */
337 static char mnemonic_chars
[256];
338 static char register_chars
[256];
339 static char operand_chars
[256];
340 static char identifier_chars
[256];
341 static char digit_chars
[256];
343 /* Lexical macros. */
344 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
345 #define is_operand_char(x) (operand_chars[(unsigned char) x])
346 #define is_register_char(x) (register_chars[(unsigned char) x])
347 #define is_space_char(x) ((x) == ' ')
348 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
349 #define is_digit_char(x) (digit_chars[(unsigned char) x])
351 /* All non-digit non-letter characters that may occur in an operand. */
352 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
354 /* md_assemble() always leaves the strings it's passed unaltered. To
355 effect this we maintain a stack of saved characters that we've smashed
356 with '\0's (indicating end of strings for various sub-fields of the
357 assembler instruction). */
358 static char save_stack
[32];
359 static char *save_stack_p
;
360 #define END_STRING_AND_SAVE(s) \
361 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
362 #define RESTORE_END_STRING(s) \
363 do { *(s) = *--save_stack_p; } while (0)
365 /* The instruction we're assembling. */
368 /* Possible templates for current insn. */
369 static const templates
*current_templates
;
371 /* Per instruction expressionS buffers: max displacements & immediates. */
372 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
373 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
375 /* Current operand we are working on. */
376 static int this_operand
= -1;
378 /* We support four different modes. FLAG_CODE variable is used to distinguish
386 static enum flag_code flag_code
;
387 static unsigned int object_64bit
;
388 static int use_rela_relocations
= 0;
390 /* The names used to print error messages. */
391 static const char *flag_code_names
[] =
398 /* 1 for intel syntax,
400 static int intel_syntax
= 0;
402 /* 1 for intel mnemonic,
403 0 if att mnemonic. */
404 static int intel_mnemonic
= !SYSV386_COMPAT
;
406 /* 1 if support old (<= 2.8.1) versions of gcc. */
407 static int old_gcc
= OLDGCC_COMPAT
;
409 /* 1 if pseudo registers are permitted. */
410 static int allow_pseudo_reg
= 0;
412 /* 1 if register prefix % not required. */
413 static int allow_naked_reg
= 0;
415 /* 1 if pseudo index register, eiz/riz, is allowed . */
416 static int allow_index_reg
= 0;
426 /* Register prefix used for error message. */
427 static const char *register_prefix
= "%";
429 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
430 leave, push, and pop instructions so that gcc has the same stack
431 frame as in 32 bit mode. */
432 static char stackop_size
= '\0';
434 /* Non-zero to optimize code alignment. */
435 int optimize_align_code
= 1;
437 /* Non-zero to quieten some warnings. */
438 static int quiet_warnings
= 0;
441 static const char *cpu_arch_name
= NULL
;
442 static char *cpu_sub_arch_name
= NULL
;
444 /* CPU feature flags. */
445 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
447 /* If we have selected a cpu we are generating instructions for. */
448 static int cpu_arch_tune_set
= 0;
450 /* Cpu we are generating instructions for. */
451 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
453 /* CPU feature flags of cpu we are generating instructions for. */
454 static i386_cpu_flags cpu_arch_tune_flags
;
456 /* CPU instruction set architecture used. */
457 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
459 /* CPU feature flags of instruction set architecture used. */
460 i386_cpu_flags cpu_arch_isa_flags
;
462 /* If set, conditional jumps are not automatically promoted to handle
463 larger than a byte offset. */
464 static unsigned int no_cond_jump_promotion
= 0;
466 /* Encode SSE instructions with VEX prefix. */
467 static unsigned int sse2avx
;
469 /* Encode scalar AVX instructions with specific vector length. */
476 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
477 static symbolS
*GOT_symbol
;
479 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
480 unsigned int x86_dwarf2_return_column
;
482 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
483 int x86_cie_data_alignment
;
485 /* Interface to relax_segment.
486 There are 3 major relax states for 386 jump insns because the
487 different types of jumps add different sizes to frags when we're
488 figuring out what sort of jump to choose to reach a given label. */
491 #define UNCOND_JUMP 0
493 #define COND_JUMP86 2
498 #define SMALL16 (SMALL | CODE16)
500 #define BIG16 (BIG | CODE16)
504 #define INLINE __inline__
510 #define ENCODE_RELAX_STATE(type, size) \
511 ((relax_substateT) (((type) << 2) | (size)))
512 #define TYPE_FROM_RELAX_STATE(s) \
514 #define DISP_SIZE_FROM_RELAX_STATE(s) \
515 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
517 /* This table is used by relax_frag to promote short jumps to long
518 ones where necessary. SMALL (short) jumps may be promoted to BIG
519 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
520 don't allow a short jump in a 32 bit code segment to be promoted to
521 a 16 bit offset jump because it's slower (requires data size
522 prefix), and doesn't work, unless the destination is in the bottom
523 64k of the code segment (The top 16 bits of eip are zeroed). */
525 const relax_typeS md_relax_table
[] =
528 1) most positive reach of this state,
529 2) most negative reach of this state,
530 3) how many bytes this mode will have in the variable part of the frag
531 4) which index into the table to try if we can't fit into this one. */
533 /* UNCOND_JUMP states. */
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
535 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
536 /* dword jmp adds 4 bytes to frag:
537 0 extra opcode bytes, 4 displacement bytes. */
539 /* word jmp adds 2 byte2 to frag:
540 0 extra opcode bytes, 2 displacement bytes. */
543 /* COND_JUMP states. */
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
545 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
546 /* dword conditionals adds 5 bytes to frag:
547 1 extra opcode byte, 4 displacement bytes. */
549 /* word conditionals add 3 bytes to frag:
550 1 extra opcode byte, 2 displacement bytes. */
553 /* COND_JUMP86 states. */
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
555 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
556 /* dword conditionals adds 5 bytes to frag:
557 1 extra opcode byte, 4 displacement bytes. */
559 /* word conditionals add 4 bytes to frag:
560 1 displacement byte and a 3 byte long branch insn. */
564 static const arch_entry cpu_arch
[] =
566 /* Do not replace the first two entries - i386_target_format()
567 relies on them being there in this order. */
568 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
569 CPU_GENERIC32_FLAGS
, 0 },
570 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
571 CPU_GENERIC64_FLAGS
, 0 },
572 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
574 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
576 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
578 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
580 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
582 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
584 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
586 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
588 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
590 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
592 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
594 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
596 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
598 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
599 CPU_NOCONA_FLAGS
, 0 },
600 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
602 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
604 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
605 CPU_CORE2_FLAGS
, 1 },
606 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
607 CPU_CORE2_FLAGS
, 0 },
608 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
609 CPU_COREI7_FLAGS
, 0 },
610 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
612 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
614 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
616 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
617 CPU_ATHLON_FLAGS
, 0 },
618 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
620 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
622 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
624 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
625 CPU_AMDFAM10_FLAGS
, 0 },
626 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
627 CPU_BDVER1_FLAGS
, 0 },
628 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
630 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
632 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
634 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
635 CPU_ANY87_FLAGS
, 0 },
636 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
638 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
639 CPU_3DNOWA_FLAGS
, 0 },
640 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
642 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
644 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
646 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
647 CPU_SSSE3_FLAGS
, 0 },
648 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
649 CPU_SSE4_1_FLAGS
, 0 },
650 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
651 CPU_SSE4_2_FLAGS
, 0 },
652 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
653 CPU_SSE4_2_FLAGS
, 0 },
654 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
655 CPU_ANY_SSE_FLAGS
, 0 },
656 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
658 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
659 CPU_ANY_AVX_FLAGS
, 0 },
660 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
662 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
664 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
665 CPU_XSAVE_FLAGS
, 0 },
666 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
667 CPU_XSAVEOPT_FLAGS
, 0 },
668 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
670 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
671 CPU_PCLMUL_FLAGS
, 0 },
672 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
673 CPU_PCLMUL_FLAGS
, 1 },
674 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
675 CPU_FSGSBASE_FLAGS
, 0 },
676 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
677 CPU_RDRND_FLAGS
, 0 },
678 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
680 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
682 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
684 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
686 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
688 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
689 CPU_MOVBE_FLAGS
, 0 },
690 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
692 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
693 CPU_CLFLUSH_FLAGS
, 0 },
694 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
695 CPU_SYSCALL_FLAGS
, 0 },
696 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
697 CPU_RDTSCP_FLAGS
, 0 },
698 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
699 CPU_3DNOW_FLAGS
, 0 },
700 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
701 CPU_3DNOWA_FLAGS
, 0 },
702 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
703 CPU_PADLOCK_FLAGS
, 0 },
704 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
706 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
708 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
709 CPU_SSE4A_FLAGS
, 0 },
710 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
715 /* Like s_lcomm_internal in gas/read.c but the alignment string
716 is allowed to be optional. */
719 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
726 && *input_line_pointer
== ',')
728 align
= parse_align (needs_align
- 1);
730 if (align
== (addressT
) -1)
745 bss_alloc (symbolP
, size
, align
);
750 pe_lcomm (int needs_align
)
752 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
756 const pseudo_typeS md_pseudo_table
[] =
758 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
759 {"align", s_align_bytes
, 0},
761 {"align", s_align_ptwo
, 0},
763 {"arch", set_cpu_arch
, 0},
767 {"lcomm", pe_lcomm
, 1},
769 {"ffloat", float_cons
, 'f'},
770 {"dfloat", float_cons
, 'd'},
771 {"tfloat", float_cons
, 'x'},
773 {"slong", signed_cons
, 4},
774 {"noopt", s_ignore
, 0},
775 {"optim", s_ignore
, 0},
776 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
777 {"code16", set_code_flag
, CODE_16BIT
},
778 {"code32", set_code_flag
, CODE_32BIT
},
779 {"code64", set_code_flag
, CODE_64BIT
},
780 {"intel_syntax", set_intel_syntax
, 1},
781 {"att_syntax", set_intel_syntax
, 0},
782 {"intel_mnemonic", set_intel_mnemonic
, 1},
783 {"att_mnemonic", set_intel_mnemonic
, 0},
784 {"allow_index_reg", set_allow_index_reg
, 1},
785 {"disallow_index_reg", set_allow_index_reg
, 0},
786 {"sse_check", set_sse_check
, 0},
787 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
788 {"largecomm", handle_large_common
, 0},
790 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
791 {"loc", dwarf2_directive_loc
, 0},
792 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
795 {"secrel32", pe_directive_secrel
, 0},
800 /* For interface with expression (). */
801 extern char *input_line_pointer
;
803 /* Hash table for instruction mnemonic lookup. */
804 static struct hash_control
*op_hash
;
806 /* Hash table for register lookup. */
807 static struct hash_control
*reg_hash
;
810 i386_align_code (fragS
*fragP
, int count
)
812 /* Various efficient no-op patterns for aligning code labels.
813 Note: Don't try to assemble the instructions in the comments.
814 0L and 0w are not legal. */
815 static const char f32_1
[] =
817 static const char f32_2
[] =
818 {0x66,0x90}; /* xchg %ax,%ax */
819 static const char f32_3
[] =
820 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
821 static const char f32_4
[] =
822 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
823 static const char f32_5
[] =
825 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
826 static const char f32_6
[] =
827 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
828 static const char f32_7
[] =
829 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
830 static const char f32_8
[] =
832 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
833 static const char f32_9
[] =
834 {0x89,0xf6, /* movl %esi,%esi */
835 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
836 static const char f32_10
[] =
837 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
838 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
839 static const char f32_11
[] =
840 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
841 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
842 static const char f32_12
[] =
843 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
844 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
845 static const char f32_13
[] =
846 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
847 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
848 static const char f32_14
[] =
849 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
850 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
851 static const char f16_3
[] =
852 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
853 static const char f16_4
[] =
854 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
855 static const char f16_5
[] =
857 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
858 static const char f16_6
[] =
859 {0x89,0xf6, /* mov %si,%si */
860 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
861 static const char f16_7
[] =
862 {0x8d,0x74,0x00, /* lea 0(%si),%si */
863 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
864 static const char f16_8
[] =
865 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
866 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
867 static const char jump_31
[] =
868 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
869 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
870 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
871 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
872 static const char *const f32_patt
[] = {
873 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
874 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
876 static const char *const f16_patt
[] = {
877 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
880 static const char alt_3
[] =
882 /* nopl 0(%[re]ax) */
883 static const char alt_4
[] =
884 {0x0f,0x1f,0x40,0x00};
885 /* nopl 0(%[re]ax,%[re]ax,1) */
886 static const char alt_5
[] =
887 {0x0f,0x1f,0x44,0x00,0x00};
888 /* nopw 0(%[re]ax,%[re]ax,1) */
889 static const char alt_6
[] =
890 {0x66,0x0f,0x1f,0x44,0x00,0x00};
891 /* nopl 0L(%[re]ax) */
892 static const char alt_7
[] =
893 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
894 /* nopl 0L(%[re]ax,%[re]ax,1) */
895 static const char alt_8
[] =
896 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
897 /* nopw 0L(%[re]ax,%[re]ax,1) */
898 static const char alt_9
[] =
899 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
900 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
901 static const char alt_10
[] =
902 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 nopw %cs:0L(%[re]ax,%[re]ax,1) */
905 static const char alt_long_11
[] =
907 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
910 nopw %cs:0L(%[re]ax,%[re]ax,1) */
911 static const char alt_long_12
[] =
914 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
918 nopw %cs:0L(%[re]ax,%[re]ax,1) */
919 static const char alt_long_13
[] =
923 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
928 nopw %cs:0L(%[re]ax,%[re]ax,1) */
929 static const char alt_long_14
[] =
934 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
940 nopw %cs:0L(%[re]ax,%[re]ax,1) */
941 static const char alt_long_15
[] =
947 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
948 /* nopl 0(%[re]ax,%[re]ax,1)
949 nopw 0(%[re]ax,%[re]ax,1) */
950 static const char alt_short_11
[] =
951 {0x0f,0x1f,0x44,0x00,0x00,
952 0x66,0x0f,0x1f,0x44,0x00,0x00};
953 /* nopw 0(%[re]ax,%[re]ax,1)
954 nopw 0(%[re]ax,%[re]ax,1) */
955 static const char alt_short_12
[] =
956 {0x66,0x0f,0x1f,0x44,0x00,0x00,
957 0x66,0x0f,0x1f,0x44,0x00,0x00};
958 /* nopw 0(%[re]ax,%[re]ax,1)
960 static const char alt_short_13
[] =
961 {0x66,0x0f,0x1f,0x44,0x00,0x00,
962 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
965 static const char alt_short_14
[] =
966 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
967 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
969 nopl 0L(%[re]ax,%[re]ax,1) */
970 static const char alt_short_15
[] =
971 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
972 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
973 static const char *const alt_short_patt
[] = {
974 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
975 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
976 alt_short_14
, alt_short_15
978 static const char *const alt_long_patt
[] = {
979 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
980 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
981 alt_long_14
, alt_long_15
984 /* Only align for at least a positive non-zero boundary. */
985 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
988 /* We need to decide which NOP sequence to use for 32bit and
989 64bit. When -mtune= is used:
991 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
992 PROCESSOR_GENERIC32, f32_patt will be used.
993 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
994 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
995 PROCESSOR_GENERIC64, alt_long_patt will be used.
996 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
997 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
1000 When -mtune= isn't used, alt_long_patt will be used if
1001 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
1004 When -march= or .arch is used, we can't use anything beyond
1005 cpu_arch_isa_flags. */
1007 if (flag_code
== CODE_16BIT
)
1011 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1013 /* Adjust jump offset. */
1014 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1017 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1018 f16_patt
[count
- 1], count
);
1022 const char *const *patt
= NULL
;
1024 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1026 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1027 switch (cpu_arch_tune
)
1029 case PROCESSOR_UNKNOWN
:
1030 /* We use cpu_arch_isa_flags to check if we SHOULD
1031 optimize for Cpu686. */
1032 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1033 patt
= alt_long_patt
;
1037 case PROCESSOR_PENTIUMPRO
:
1038 case PROCESSOR_PENTIUM4
:
1039 case PROCESSOR_NOCONA
:
1040 case PROCESSOR_CORE
:
1041 case PROCESSOR_CORE2
:
1042 case PROCESSOR_COREI7
:
1043 case PROCESSOR_L1OM
:
1044 case PROCESSOR_GENERIC64
:
1045 patt
= alt_long_patt
;
1048 case PROCESSOR_ATHLON
:
1050 case PROCESSOR_AMDFAM10
:
1051 case PROCESSOR_BDVER1
:
1052 patt
= alt_short_patt
;
1054 case PROCESSOR_I386
:
1055 case PROCESSOR_I486
:
1056 case PROCESSOR_PENTIUM
:
1057 case PROCESSOR_GENERIC32
:
1064 switch (fragP
->tc_frag_data
.tune
)
1066 case PROCESSOR_UNKNOWN
:
1067 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1068 PROCESSOR_UNKNOWN. */
1072 case PROCESSOR_I386
:
1073 case PROCESSOR_I486
:
1074 case PROCESSOR_PENTIUM
:
1076 case PROCESSOR_ATHLON
:
1078 case PROCESSOR_AMDFAM10
:
1079 case PROCESSOR_BDVER1
:
1080 case PROCESSOR_GENERIC32
:
1081 /* We use cpu_arch_isa_flags to check if we CAN optimize
1083 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1084 patt
= alt_short_patt
;
1088 case PROCESSOR_PENTIUMPRO
:
1089 case PROCESSOR_PENTIUM4
:
1090 case PROCESSOR_NOCONA
:
1091 case PROCESSOR_CORE
:
1092 case PROCESSOR_CORE2
:
1093 case PROCESSOR_COREI7
:
1094 case PROCESSOR_L1OM
:
1095 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1096 patt
= alt_long_patt
;
1100 case PROCESSOR_GENERIC64
:
1101 patt
= alt_long_patt
;
1106 if (patt
== f32_patt
)
1108 /* If the padding is less than 15 bytes, we use the normal
1109 ones. Otherwise, we use a jump instruction and adjust
1113 /* For 64bit, the limit is 3 bytes. */
1114 if (flag_code
== CODE_64BIT
1115 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1120 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1121 patt
[count
- 1], count
);
1124 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1126 /* Adjust jump offset. */
1127 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1132 /* Maximum length of an instruction is 15 byte. If the
1133 padding is greater than 15 bytes and we don't use jump,
1134 we have to break it into smaller pieces. */
1135 int padding
= count
;
1136 while (padding
> 15)
1139 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1144 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1145 patt
[padding
- 1], padding
);
1148 fragP
->fr_var
= count
;
1152 operand_type_all_zero (const union i386_operand_type
*x
)
1154 switch (ARRAY_SIZE(x
->array
))
1163 return !x
->array
[0];
1170 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1172 switch (ARRAY_SIZE(x
->array
))
1187 operand_type_equal (const union i386_operand_type
*x
,
1188 const union i386_operand_type
*y
)
1190 switch (ARRAY_SIZE(x
->array
))
1193 if (x
->array
[2] != y
->array
[2])
1196 if (x
->array
[1] != y
->array
[1])
1199 return x
->array
[0] == y
->array
[0];
1207 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1209 switch (ARRAY_SIZE(x
->array
))
1218 return !x
->array
[0];
1225 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1227 switch (ARRAY_SIZE(x
->array
))
1242 cpu_flags_equal (const union i386_cpu_flags
*x
,
1243 const union i386_cpu_flags
*y
)
1245 switch (ARRAY_SIZE(x
->array
))
1248 if (x
->array
[2] != y
->array
[2])
1251 if (x
->array
[1] != y
->array
[1])
1254 return x
->array
[0] == y
->array
[0];
1262 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1264 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1265 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1268 static INLINE i386_cpu_flags
1269 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1271 switch (ARRAY_SIZE (x
.array
))
1274 x
.array
[2] &= y
.array
[2];
1276 x
.array
[1] &= y
.array
[1];
1278 x
.array
[0] &= y
.array
[0];
1286 static INLINE i386_cpu_flags
1287 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1289 switch (ARRAY_SIZE (x
.array
))
1292 x
.array
[2] |= y
.array
[2];
1294 x
.array
[1] |= y
.array
[1];
1296 x
.array
[0] |= y
.array
[0];
1304 static INLINE i386_cpu_flags
1305 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1307 switch (ARRAY_SIZE (x
.array
))
1310 x
.array
[2] &= ~y
.array
[2];
1312 x
.array
[1] &= ~y
.array
[1];
1314 x
.array
[0] &= ~y
.array
[0];
1322 #define CPU_FLAGS_ARCH_MATCH 0x1
1323 #define CPU_FLAGS_64BIT_MATCH 0x2
1324 #define CPU_FLAGS_AES_MATCH 0x4
1325 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1326 #define CPU_FLAGS_AVX_MATCH 0x10
1328 #define CPU_FLAGS_32BIT_MATCH \
1329 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1330 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1331 #define CPU_FLAGS_PERFECT_MATCH \
1332 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1334 /* Return CPU flags match bits. */
1337 cpu_flags_match (const insn_template
*t
)
1339 i386_cpu_flags x
= t
->cpu_flags
;
1340 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1342 x
.bitfield
.cpu64
= 0;
1343 x
.bitfield
.cpuno64
= 0;
1345 if (cpu_flags_all_zero (&x
))
1347 /* This instruction is available on all archs. */
1348 match
|= CPU_FLAGS_32BIT_MATCH
;
1352 /* This instruction is available only on some archs. */
1353 i386_cpu_flags cpu
= cpu_arch_flags
;
1355 cpu
.bitfield
.cpu64
= 0;
1356 cpu
.bitfield
.cpuno64
= 0;
1357 cpu
= cpu_flags_and (x
, cpu
);
1358 if (!cpu_flags_all_zero (&cpu
))
1360 if (x
.bitfield
.cpuavx
)
1362 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1363 if (cpu
.bitfield
.cpuavx
)
1365 /* Check SSE2AVX. */
1366 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1368 match
|= (CPU_FLAGS_ARCH_MATCH
1369 | CPU_FLAGS_AVX_MATCH
);
1371 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1372 match
|= CPU_FLAGS_AES_MATCH
;
1374 if (!x
.bitfield
.cpupclmul
1375 || cpu
.bitfield
.cpupclmul
)
1376 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1380 match
|= CPU_FLAGS_ARCH_MATCH
;
1383 match
|= CPU_FLAGS_32BIT_MATCH
;
1389 static INLINE i386_operand_type
1390 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1392 switch (ARRAY_SIZE (x
.array
))
1395 x
.array
[2] &= y
.array
[2];
1397 x
.array
[1] &= y
.array
[1];
1399 x
.array
[0] &= y
.array
[0];
1407 static INLINE i386_operand_type
1408 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1410 switch (ARRAY_SIZE (x
.array
))
1413 x
.array
[2] |= y
.array
[2];
1415 x
.array
[1] |= y
.array
[1];
1417 x
.array
[0] |= y
.array
[0];
1425 static INLINE i386_operand_type
1426 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1428 switch (ARRAY_SIZE (x
.array
))
1431 x
.array
[2] ^= y
.array
[2];
1433 x
.array
[1] ^= y
.array
[1];
1435 x
.array
[0] ^= y
.array
[0];
1443 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1444 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1445 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1446 static const i386_operand_type inoutportreg
1447 = OPERAND_TYPE_INOUTPORTREG
;
1448 static const i386_operand_type reg16_inoutportreg
1449 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1450 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1451 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1452 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1453 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1454 static const i386_operand_type anydisp
1455 = OPERAND_TYPE_ANYDISP
;
1456 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1457 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1458 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1459 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1460 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1461 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1462 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1463 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1464 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1465 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1466 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1467 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1478 operand_type_check (i386_operand_type t
, enum operand_type c
)
1483 return (t
.bitfield
.reg8
1486 || t
.bitfield
.reg64
);
1489 return (t
.bitfield
.imm8
1493 || t
.bitfield
.imm32s
1494 || t
.bitfield
.imm64
);
1497 return (t
.bitfield
.disp8
1498 || t
.bitfield
.disp16
1499 || t
.bitfield
.disp32
1500 || t
.bitfield
.disp32s
1501 || t
.bitfield
.disp64
);
1504 return (t
.bitfield
.disp8
1505 || t
.bitfield
.disp16
1506 || t
.bitfield
.disp32
1507 || t
.bitfield
.disp32s
1508 || t
.bitfield
.disp64
1509 || t
.bitfield
.baseindex
);
1518 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1519 operand J for instruction template T. */
1522 match_reg_size (const insn_template
*t
, unsigned int j
)
1524 return !((i
.types
[j
].bitfield
.byte
1525 && !t
->operand_types
[j
].bitfield
.byte
)
1526 || (i
.types
[j
].bitfield
.word
1527 && !t
->operand_types
[j
].bitfield
.word
)
1528 || (i
.types
[j
].bitfield
.dword
1529 && !t
->operand_types
[j
].bitfield
.dword
)
1530 || (i
.types
[j
].bitfield
.qword
1531 && !t
->operand_types
[j
].bitfield
.qword
));
1534 /* Return 1 if there is no conflict in any size on operand J for
1535 instruction template T. */
1538 match_mem_size (const insn_template
*t
, unsigned int j
)
1540 return (match_reg_size (t
, j
)
1541 && !((i
.types
[j
].bitfield
.unspecified
1542 && !t
->operand_types
[j
].bitfield
.unspecified
)
1543 || (i
.types
[j
].bitfield
.fword
1544 && !t
->operand_types
[j
].bitfield
.fword
)
1545 || (i
.types
[j
].bitfield
.tbyte
1546 && !t
->operand_types
[j
].bitfield
.tbyte
)
1547 || (i
.types
[j
].bitfield
.xmmword
1548 && !t
->operand_types
[j
].bitfield
.xmmword
)
1549 || (i
.types
[j
].bitfield
.ymmword
1550 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1553 /* Return 1 if there is no size conflict on any operands for
1554 instruction template T. */
1557 operand_size_match (const insn_template
*t
)
1562 /* Don't check jump instructions. */
1563 if (t
->opcode_modifier
.jump
1564 || t
->opcode_modifier
.jumpbyte
1565 || t
->opcode_modifier
.jumpdword
1566 || t
->opcode_modifier
.jumpintersegment
)
1569 /* Check memory and accumulator operand size. */
1570 for (j
= 0; j
< i
.operands
; j
++)
1572 if (t
->operand_types
[j
].bitfield
.anysize
)
1575 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1581 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1590 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1593 i
.error
= operand_size_mismatch
;
1597 /* Check reverse. */
1598 gas_assert (i
.operands
== 2);
1601 for (j
= 0; j
< 2; j
++)
1603 if (t
->operand_types
[j
].bitfield
.acc
1604 && !match_reg_size (t
, j
? 0 : 1))
1607 if (i
.types
[j
].bitfield
.mem
1608 && !match_mem_size (t
, j
? 0 : 1))
1616 operand_type_match (i386_operand_type overlap
,
1617 i386_operand_type given
)
1619 i386_operand_type temp
= overlap
;
1621 temp
.bitfield
.jumpabsolute
= 0;
1622 temp
.bitfield
.unspecified
= 0;
1623 temp
.bitfield
.byte
= 0;
1624 temp
.bitfield
.word
= 0;
1625 temp
.bitfield
.dword
= 0;
1626 temp
.bitfield
.fword
= 0;
1627 temp
.bitfield
.qword
= 0;
1628 temp
.bitfield
.tbyte
= 0;
1629 temp
.bitfield
.xmmword
= 0;
1630 temp
.bitfield
.ymmword
= 0;
1631 if (operand_type_all_zero (&temp
))
1634 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1635 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1639 i
.error
= operand_type_mismatch
;
1643 /* If given types g0 and g1 are registers they must be of the same type
1644 unless the expected operand type register overlap is null.
1645 Note that Acc in a template matches every size of reg. */
1648 operand_type_register_match (i386_operand_type m0
,
1649 i386_operand_type g0
,
1650 i386_operand_type t0
,
1651 i386_operand_type m1
,
1652 i386_operand_type g1
,
1653 i386_operand_type t1
)
1655 if (!operand_type_check (g0
, reg
))
1658 if (!operand_type_check (g1
, reg
))
1661 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1662 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1663 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1664 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1667 if (m0
.bitfield
.acc
)
1669 t0
.bitfield
.reg8
= 1;
1670 t0
.bitfield
.reg16
= 1;
1671 t0
.bitfield
.reg32
= 1;
1672 t0
.bitfield
.reg64
= 1;
1675 if (m1
.bitfield
.acc
)
1677 t1
.bitfield
.reg8
= 1;
1678 t1
.bitfield
.reg16
= 1;
1679 t1
.bitfield
.reg32
= 1;
1680 t1
.bitfield
.reg64
= 1;
1683 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1684 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1685 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1686 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1689 i
.error
= register_type_mismatch
;
1694 static INLINE
unsigned int
1695 mode_from_disp_size (i386_operand_type t
)
1697 if (t
.bitfield
.disp8
)
1699 else if (t
.bitfield
.disp16
1700 || t
.bitfield
.disp32
1701 || t
.bitfield
.disp32s
)
1708 fits_in_signed_byte (offsetT num
)
1710 return (num
>= -128) && (num
<= 127);
1714 fits_in_unsigned_byte (offsetT num
)
1716 return (num
& 0xff) == num
;
1720 fits_in_unsigned_word (offsetT num
)
1722 return (num
& 0xffff) == num
;
1726 fits_in_signed_word (offsetT num
)
1728 return (-32768 <= num
) && (num
<= 32767);
1732 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1737 return (!(((offsetT
) -1 << 31) & num
)
1738 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1740 } /* fits_in_signed_long() */
1743 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1748 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1750 } /* fits_in_unsigned_long() */
1753 fits_in_imm4 (offsetT num
)
1755 return (num
& 0xf) == num
;
1758 static i386_operand_type
1759 smallest_imm_type (offsetT num
)
1761 i386_operand_type t
;
1763 operand_type_set (&t
, 0);
1764 t
.bitfield
.imm64
= 1;
1766 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1768 /* This code is disabled on the 486 because all the Imm1 forms
1769 in the opcode table are slower on the i486. They're the
1770 versions with the implicitly specified single-position
1771 displacement, which has another syntax if you really want to
1773 t
.bitfield
.imm1
= 1;
1774 t
.bitfield
.imm8
= 1;
1775 t
.bitfield
.imm8s
= 1;
1776 t
.bitfield
.imm16
= 1;
1777 t
.bitfield
.imm32
= 1;
1778 t
.bitfield
.imm32s
= 1;
1780 else if (fits_in_signed_byte (num
))
1782 t
.bitfield
.imm8
= 1;
1783 t
.bitfield
.imm8s
= 1;
1784 t
.bitfield
.imm16
= 1;
1785 t
.bitfield
.imm32
= 1;
1786 t
.bitfield
.imm32s
= 1;
1788 else if (fits_in_unsigned_byte (num
))
1790 t
.bitfield
.imm8
= 1;
1791 t
.bitfield
.imm16
= 1;
1792 t
.bitfield
.imm32
= 1;
1793 t
.bitfield
.imm32s
= 1;
1795 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1797 t
.bitfield
.imm16
= 1;
1798 t
.bitfield
.imm32
= 1;
1799 t
.bitfield
.imm32s
= 1;
1801 else if (fits_in_signed_long (num
))
1803 t
.bitfield
.imm32
= 1;
1804 t
.bitfield
.imm32s
= 1;
1806 else if (fits_in_unsigned_long (num
))
1807 t
.bitfield
.imm32
= 1;
1813 offset_in_range (offsetT val
, int size
)
1819 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1820 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1821 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1823 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1829 /* If BFD64, sign extend val for 32bit address mode. */
1830 if (flag_code
!= CODE_64BIT
1831 || i
.prefix
[ADDR_PREFIX
])
1832 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1833 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1836 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1838 char buf1
[40], buf2
[40];
1840 sprint_value (buf1
, val
);
1841 sprint_value (buf2
, val
& mask
);
1842 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1856 a. PREFIX_EXIST if attempting to add a prefix where one from the
1857 same class already exists.
1858 b. PREFIX_LOCK if lock prefix is added.
1859 c. PREFIX_REP if rep/repne prefix is added.
1860 d. PREFIX_OTHER if other prefix is added.
1863 static enum PREFIX_GROUP
1864 add_prefix (unsigned int prefix
)
1866 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1869 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1870 && flag_code
== CODE_64BIT
)
1872 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1873 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1874 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1885 case CS_PREFIX_OPCODE
:
1886 case DS_PREFIX_OPCODE
:
1887 case ES_PREFIX_OPCODE
:
1888 case FS_PREFIX_OPCODE
:
1889 case GS_PREFIX_OPCODE
:
1890 case SS_PREFIX_OPCODE
:
1894 case REPNE_PREFIX_OPCODE
:
1895 case REPE_PREFIX_OPCODE
:
1900 case LOCK_PREFIX_OPCODE
:
1909 case ADDR_PREFIX_OPCODE
:
1913 case DATA_PREFIX_OPCODE
:
1917 if (i
.prefix
[q
] != 0)
1925 i
.prefix
[q
] |= prefix
;
1928 as_bad (_("same type of prefix used twice"));
1934 update_code_flag (int value
, int check
)
1936 PRINTF_LIKE ((*as_error
));
1938 flag_code
= (enum flag_code
) value
;
1939 if (flag_code
== CODE_64BIT
)
1941 cpu_arch_flags
.bitfield
.cpu64
= 1;
1942 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1946 cpu_arch_flags
.bitfield
.cpu64
= 0;
1947 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1949 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1952 as_error
= as_fatal
;
1955 (*as_error
) (_("64bit mode not supported on `%s'."),
1956 cpu_arch_name
? cpu_arch_name
: default_arch
);
1958 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1961 as_error
= as_fatal
;
1964 (*as_error
) (_("32bit mode not supported on `%s'."),
1965 cpu_arch_name
? cpu_arch_name
: default_arch
);
1967 stackop_size
= '\0';
1971 set_code_flag (int value
)
1973 update_code_flag (value
, 0);
1977 set_16bit_gcc_code_flag (int new_code_flag
)
1979 flag_code
= (enum flag_code
) new_code_flag
;
1980 if (flag_code
!= CODE_16BIT
)
1982 cpu_arch_flags
.bitfield
.cpu64
= 0;
1983 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1984 stackop_size
= LONG_MNEM_SUFFIX
;
1988 set_intel_syntax (int syntax_flag
)
1990 /* Find out if register prefixing is specified. */
1991 int ask_naked_reg
= 0;
1994 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1996 char *string
= input_line_pointer
;
1997 int e
= get_symbol_end ();
1999 if (strcmp (string
, "prefix") == 0)
2001 else if (strcmp (string
, "noprefix") == 0)
2004 as_bad (_("bad argument to syntax directive."));
2005 *input_line_pointer
= e
;
2007 demand_empty_rest_of_line ();
2009 intel_syntax
= syntax_flag
;
2011 if (ask_naked_reg
== 0)
2012 allow_naked_reg
= (intel_syntax
2013 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2015 allow_naked_reg
= (ask_naked_reg
< 0);
2017 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2019 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2020 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2021 register_prefix
= allow_naked_reg
? "" : "%";
2025 set_intel_mnemonic (int mnemonic_flag
)
2027 intel_mnemonic
= mnemonic_flag
;
2031 set_allow_index_reg (int flag
)
2033 allow_index_reg
= flag
;
2037 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2041 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2043 char *string
= input_line_pointer
;
2044 int e
= get_symbol_end ();
2046 if (strcmp (string
, "none") == 0)
2047 sse_check
= sse_check_none
;
2048 else if (strcmp (string
, "warning") == 0)
2049 sse_check
= sse_check_warning
;
2050 else if (strcmp (string
, "error") == 0)
2051 sse_check
= sse_check_error
;
2053 as_bad (_("bad argument to sse_check directive."));
2054 *input_line_pointer
= e
;
2057 as_bad (_("missing argument for sse_check directive"));
2059 demand_empty_rest_of_line ();
2063 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2064 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2066 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2067 static const char *arch
;
2069 /* Intel LIOM is only supported on ELF. */
2075 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2076 use default_arch. */
2077 arch
= cpu_arch_name
;
2079 arch
= default_arch
;
2082 /* If we are targeting Intel L1OM, we must enable it. */
2083 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2084 || new_flag
.bitfield
.cpul1om
)
2087 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2092 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2096 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2098 char *string
= input_line_pointer
;
2099 int e
= get_symbol_end ();
2101 i386_cpu_flags flags
;
2103 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2105 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2107 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2111 cpu_arch_name
= cpu_arch
[j
].name
;
2112 cpu_sub_arch_name
= NULL
;
2113 cpu_arch_flags
= cpu_arch
[j
].flags
;
2114 if (flag_code
== CODE_64BIT
)
2116 cpu_arch_flags
.bitfield
.cpu64
= 1;
2117 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2121 cpu_arch_flags
.bitfield
.cpu64
= 0;
2122 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2124 cpu_arch_isa
= cpu_arch
[j
].type
;
2125 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2126 if (!cpu_arch_tune_set
)
2128 cpu_arch_tune
= cpu_arch_isa
;
2129 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2134 if (strncmp (string
+ 1, "no", 2))
2135 flags
= cpu_flags_or (cpu_arch_flags
,
2138 flags
= cpu_flags_and_not (cpu_arch_flags
,
2140 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2142 if (cpu_sub_arch_name
)
2144 char *name
= cpu_sub_arch_name
;
2145 cpu_sub_arch_name
= concat (name
,
2147 (const char *) NULL
);
2151 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2152 cpu_arch_flags
= flags
;
2154 *input_line_pointer
= e
;
2155 demand_empty_rest_of_line ();
2159 if (j
>= ARRAY_SIZE (cpu_arch
))
2160 as_bad (_("no such architecture: `%s'"), string
);
2162 *input_line_pointer
= e
;
2165 as_bad (_("missing cpu architecture"));
2167 no_cond_jump_promotion
= 0;
2168 if (*input_line_pointer
== ','
2169 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2171 char *string
= ++input_line_pointer
;
2172 int e
= get_symbol_end ();
2174 if (strcmp (string
, "nojumps") == 0)
2175 no_cond_jump_promotion
= 1;
2176 else if (strcmp (string
, "jumps") == 0)
2179 as_bad (_("no such architecture modifier: `%s'"), string
);
2181 *input_line_pointer
= e
;
2184 demand_empty_rest_of_line ();
2187 enum bfd_architecture
2190 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2192 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2193 || flag_code
!= CODE_64BIT
)
2194 as_fatal (_("Intel L1OM is 64bit ELF only"));
2195 return bfd_arch_l1om
;
2198 return bfd_arch_i386
;
2204 if (!strcmp (default_arch
, "x86_64"))
2206 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2208 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2209 as_fatal (_("Intel L1OM is 64bit ELF only"));
2210 return bfd_mach_l1om
;
2213 return bfd_mach_x86_64
;
2215 else if (!strcmp (default_arch
, "i386"))
2216 return bfd_mach_i386_i386
;
2218 as_fatal (_("Unknown architecture"));
2224 const char *hash_err
;
2226 /* Initialize op_hash hash table. */
2227 op_hash
= hash_new ();
2230 const insn_template
*optab
;
2231 templates
*core_optab
;
2233 /* Setup for loop. */
2235 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2236 core_optab
->start
= optab
;
2241 if (optab
->name
== NULL
2242 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2244 /* different name --> ship out current template list;
2245 add to hash table; & begin anew. */
2246 core_optab
->end
= optab
;
2247 hash_err
= hash_insert (op_hash
,
2249 (void *) core_optab
);
2252 as_fatal (_("Internal Error: Can't hash %s: %s"),
2256 if (optab
->name
== NULL
)
2258 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2259 core_optab
->start
= optab
;
2264 /* Initialize reg_hash hash table. */
2265 reg_hash
= hash_new ();
2267 const reg_entry
*regtab
;
2268 unsigned int regtab_size
= i386_regtab_size
;
2270 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2272 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2274 as_fatal (_("Internal Error: Can't hash %s: %s"),
2280 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2285 for (c
= 0; c
< 256; c
++)
2290 mnemonic_chars
[c
] = c
;
2291 register_chars
[c
] = c
;
2292 operand_chars
[c
] = c
;
2294 else if (ISLOWER (c
))
2296 mnemonic_chars
[c
] = c
;
2297 register_chars
[c
] = c
;
2298 operand_chars
[c
] = c
;
2300 else if (ISUPPER (c
))
2302 mnemonic_chars
[c
] = TOLOWER (c
);
2303 register_chars
[c
] = mnemonic_chars
[c
];
2304 operand_chars
[c
] = c
;
2307 if (ISALPHA (c
) || ISDIGIT (c
))
2308 identifier_chars
[c
] = c
;
2311 identifier_chars
[c
] = c
;
2312 operand_chars
[c
] = c
;
2317 identifier_chars
['@'] = '@';
2320 identifier_chars
['?'] = '?';
2321 operand_chars
['?'] = '?';
2323 digit_chars
['-'] = '-';
2324 mnemonic_chars
['_'] = '_';
2325 mnemonic_chars
['-'] = '-';
2326 mnemonic_chars
['.'] = '.';
2327 identifier_chars
['_'] = '_';
2328 identifier_chars
['.'] = '.';
2330 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2331 operand_chars
[(unsigned char) *p
] = *p
;
2334 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2337 record_alignment (text_section
, 2);
2338 record_alignment (data_section
, 2);
2339 record_alignment (bss_section
, 2);
2343 if (flag_code
== CODE_64BIT
)
2345 x86_dwarf2_return_column
= 16;
2346 x86_cie_data_alignment
= -8;
2350 x86_dwarf2_return_column
= 8;
2351 x86_cie_data_alignment
= -4;
2356 i386_print_statistics (FILE *file
)
2358 hash_print_statistics (file
, "i386 opcode", op_hash
);
2359 hash_print_statistics (file
, "i386 register", reg_hash
);
2364 /* Debugging routines for md_assemble. */
2365 static void pte (insn_template
*);
2366 static void pt (i386_operand_type
);
2367 static void pe (expressionS
*);
2368 static void ps (symbolS
*);
2371 pi (char *line
, i386_insn
*x
)
2375 fprintf (stdout
, "%s: template ", line
);
2377 fprintf (stdout
, " address: base %s index %s scale %x\n",
2378 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2379 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2380 x
->log2_scale_factor
);
2381 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2382 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2383 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2384 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2385 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2386 (x
->rex
& REX_W
) != 0,
2387 (x
->rex
& REX_R
) != 0,
2388 (x
->rex
& REX_X
) != 0,
2389 (x
->rex
& REX_B
) != 0);
2390 for (j
= 0; j
< x
->operands
; j
++)
2392 fprintf (stdout
, " #%d: ", j
+ 1);
2394 fprintf (stdout
, "\n");
2395 if (x
->types
[j
].bitfield
.reg8
2396 || x
->types
[j
].bitfield
.reg16
2397 || x
->types
[j
].bitfield
.reg32
2398 || x
->types
[j
].bitfield
.reg64
2399 || x
->types
[j
].bitfield
.regmmx
2400 || x
->types
[j
].bitfield
.regxmm
2401 || x
->types
[j
].bitfield
.regymm
2402 || x
->types
[j
].bitfield
.sreg2
2403 || x
->types
[j
].bitfield
.sreg3
2404 || x
->types
[j
].bitfield
.control
2405 || x
->types
[j
].bitfield
.debug
2406 || x
->types
[j
].bitfield
.test
)
2407 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2408 if (operand_type_check (x
->types
[j
], imm
))
2410 if (operand_type_check (x
->types
[j
], disp
))
2411 pe (x
->op
[j
].disps
);
2416 pte (insn_template
*t
)
2419 fprintf (stdout
, " %d operands ", t
->operands
);
2420 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2421 if (t
->extension_opcode
!= None
)
2422 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2423 if (t
->opcode_modifier
.d
)
2424 fprintf (stdout
, "D");
2425 if (t
->opcode_modifier
.w
)
2426 fprintf (stdout
, "W");
2427 fprintf (stdout
, "\n");
2428 for (j
= 0; j
< t
->operands
; j
++)
2430 fprintf (stdout
, " #%d type ", j
+ 1);
2431 pt (t
->operand_types
[j
]);
2432 fprintf (stdout
, "\n");
2439 fprintf (stdout
, " operation %d\n", e
->X_op
);
2440 fprintf (stdout
, " add_number %ld (%lx)\n",
2441 (long) e
->X_add_number
, (long) e
->X_add_number
);
2442 if (e
->X_add_symbol
)
2444 fprintf (stdout
, " add_symbol ");
2445 ps (e
->X_add_symbol
);
2446 fprintf (stdout
, "\n");
2450 fprintf (stdout
, " op_symbol ");
2451 ps (e
->X_op_symbol
);
2452 fprintf (stdout
, "\n");
2459 fprintf (stdout
, "%s type %s%s",
2461 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2462 segment_name (S_GET_SEGMENT (s
)));
2465 static struct type_name
2467 i386_operand_type mask
;
2470 const type_names
[] =
2472 { OPERAND_TYPE_REG8
, "r8" },
2473 { OPERAND_TYPE_REG16
, "r16" },
2474 { OPERAND_TYPE_REG32
, "r32" },
2475 { OPERAND_TYPE_REG64
, "r64" },
2476 { OPERAND_TYPE_IMM8
, "i8" },
2477 { OPERAND_TYPE_IMM8
, "i8s" },
2478 { OPERAND_TYPE_IMM16
, "i16" },
2479 { OPERAND_TYPE_IMM32
, "i32" },
2480 { OPERAND_TYPE_IMM32S
, "i32s" },
2481 { OPERAND_TYPE_IMM64
, "i64" },
2482 { OPERAND_TYPE_IMM1
, "i1" },
2483 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2484 { OPERAND_TYPE_DISP8
, "d8" },
2485 { OPERAND_TYPE_DISP16
, "d16" },
2486 { OPERAND_TYPE_DISP32
, "d32" },
2487 { OPERAND_TYPE_DISP32S
, "d32s" },
2488 { OPERAND_TYPE_DISP64
, "d64" },
2489 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2490 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2491 { OPERAND_TYPE_CONTROL
, "control reg" },
2492 { OPERAND_TYPE_TEST
, "test reg" },
2493 { OPERAND_TYPE_DEBUG
, "debug reg" },
2494 { OPERAND_TYPE_FLOATREG
, "FReg" },
2495 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2496 { OPERAND_TYPE_SREG2
, "SReg2" },
2497 { OPERAND_TYPE_SREG3
, "SReg3" },
2498 { OPERAND_TYPE_ACC
, "Acc" },
2499 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2500 { OPERAND_TYPE_REGMMX
, "rMMX" },
2501 { OPERAND_TYPE_REGXMM
, "rXMM" },
2502 { OPERAND_TYPE_REGYMM
, "rYMM" },
2503 { OPERAND_TYPE_ESSEG
, "es" },
2507 pt (i386_operand_type t
)
2510 i386_operand_type a
;
2512 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2514 a
= operand_type_and (t
, type_names
[j
].mask
);
2515 if (!operand_type_all_zero (&a
))
2516 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2521 #endif /* DEBUG386 */
2523 static bfd_reloc_code_real_type
2524 reloc (unsigned int size
,
2527 bfd_reloc_code_real_type other
)
2529 if (other
!= NO_RELOC
)
2531 reloc_howto_type
*rel
;
2536 case BFD_RELOC_X86_64_GOT32
:
2537 return BFD_RELOC_X86_64_GOT64
;
2539 case BFD_RELOC_X86_64_PLTOFF64
:
2540 return BFD_RELOC_X86_64_PLTOFF64
;
2542 case BFD_RELOC_X86_64_GOTPC32
:
2543 other
= BFD_RELOC_X86_64_GOTPC64
;
2545 case BFD_RELOC_X86_64_GOTPCREL
:
2546 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2548 case BFD_RELOC_X86_64_TPOFF32
:
2549 other
= BFD_RELOC_X86_64_TPOFF64
;
2551 case BFD_RELOC_X86_64_DTPOFF32
:
2552 other
= BFD_RELOC_X86_64_DTPOFF64
;
2558 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2559 if (size
== 4 && flag_code
!= CODE_64BIT
)
2562 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2564 as_bad (_("unknown relocation (%u)"), other
);
2565 else if (size
!= bfd_get_reloc_size (rel
))
2566 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2567 bfd_get_reloc_size (rel
),
2569 else if (pcrel
&& !rel
->pc_relative
)
2570 as_bad (_("non-pc-relative relocation for pc-relative field"));
2571 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2573 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2575 as_bad (_("relocated field and relocation type differ in signedness"));
2584 as_bad (_("there are no unsigned pc-relative relocations"));
2587 case 1: return BFD_RELOC_8_PCREL
;
2588 case 2: return BFD_RELOC_16_PCREL
;
2589 case 4: return BFD_RELOC_32_PCREL
;
2590 case 8: return BFD_RELOC_64_PCREL
;
2592 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2599 case 4: return BFD_RELOC_X86_64_32S
;
2604 case 1: return BFD_RELOC_8
;
2605 case 2: return BFD_RELOC_16
;
2606 case 4: return BFD_RELOC_32
;
2607 case 8: return BFD_RELOC_64
;
2609 as_bad (_("cannot do %s %u byte relocation"),
2610 sign
> 0 ? "signed" : "unsigned", size
);
2616 /* Here we decide which fixups can be adjusted to make them relative to
2617 the beginning of the section instead of the symbol. Basically we need
2618 to make sure that the dynamic relocations are done correctly, so in
2619 some cases we force the original symbol to be used. */
2622 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2624 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2628 /* Don't adjust pc-relative references to merge sections in 64-bit
2630 if (use_rela_relocations
2631 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2635 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2636 and changed later by validate_fix. */
2637 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2638 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2641 /* adjust_reloc_syms doesn't know about the GOT. */
2642 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2643 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2644 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2645 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2646 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2647 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2648 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2649 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2650 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2651 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2652 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2653 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2654 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2655 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2656 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2657 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2658 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2659 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2660 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2661 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2662 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2663 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2664 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2665 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2666 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2667 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2668 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2669 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2676 intel_float_operand (const char *mnemonic
)
2678 /* Note that the value returned is meaningful only for opcodes with (memory)
2679 operands, hence the code here is free to improperly handle opcodes that
2680 have no operands (for better performance and smaller code). */
2682 if (mnemonic
[0] != 'f')
2683 return 0; /* non-math */
2685 switch (mnemonic
[1])
2687 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2688 the fs segment override prefix not currently handled because no
2689 call path can make opcodes without operands get here */
2691 return 2 /* integer op */;
2693 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2694 return 3; /* fldcw/fldenv */
2697 if (mnemonic
[2] != 'o' /* fnop */)
2698 return 3; /* non-waiting control op */
2701 if (mnemonic
[2] == 's')
2702 return 3; /* frstor/frstpm */
2705 if (mnemonic
[2] == 'a')
2706 return 3; /* fsave */
2707 if (mnemonic
[2] == 't')
2709 switch (mnemonic
[3])
2711 case 'c': /* fstcw */
2712 case 'd': /* fstdw */
2713 case 'e': /* fstenv */
2714 case 's': /* fsts[gw] */
2720 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2721 return 0; /* fxsave/fxrstor are not really math ops */
2728 /* Build the VEX prefix. */
2731 build_vex_prefix (const insn_template
*t
)
2733 unsigned int register_specifier
;
2734 unsigned int implied_prefix
;
2735 unsigned int vector_length
;
2737 /* Check register specifier. */
2738 if (i
.vex
.register_specifier
)
2740 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2741 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2742 register_specifier
+= 8;
2743 register_specifier
= ~register_specifier
& 0xf;
2746 register_specifier
= 0xf;
2748 /* Use 2-byte VEX prefix by swappping destination and source
2751 && i
.operands
== i
.reg_operands
2752 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2753 && i
.tm
.opcode_modifier
.s
2756 unsigned int xchg
= i
.operands
- 1;
2757 union i386_op temp_op
;
2758 i386_operand_type temp_type
;
2760 temp_type
= i
.types
[xchg
];
2761 i
.types
[xchg
] = i
.types
[0];
2762 i
.types
[0] = temp_type
;
2763 temp_op
= i
.op
[xchg
];
2764 i
.op
[xchg
] = i
.op
[0];
2767 gas_assert (i
.rm
.mode
== 3);
2771 i
.rm
.regmem
= i
.rm
.reg
;
2774 /* Use the next insn. */
2778 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2779 vector_length
= avxscalar
;
2781 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2783 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2788 case DATA_PREFIX_OPCODE
:
2791 case REPE_PREFIX_OPCODE
:
2794 case REPNE_PREFIX_OPCODE
:
2801 /* Use 2-byte VEX prefix if possible. */
2802 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2803 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2805 /* 2-byte VEX prefix. */
2809 i
.vex
.bytes
[0] = 0xc5;
2811 /* Check the REX.R bit. */
2812 r
= (i
.rex
& REX_R
) ? 0 : 1;
2813 i
.vex
.bytes
[1] = (r
<< 7
2814 | register_specifier
<< 3
2815 | vector_length
<< 2
2820 /* 3-byte VEX prefix. */
2825 switch (i
.tm
.opcode_modifier
.vexopcode
)
2829 i
.vex
.bytes
[0] = 0xc4;
2833 i
.vex
.bytes
[0] = 0xc4;
2837 i
.vex
.bytes
[0] = 0xc4;
2841 i
.vex
.bytes
[0] = 0x8f;
2845 i
.vex
.bytes
[0] = 0x8f;
2849 i
.vex
.bytes
[0] = 0x8f;
2855 /* The high 3 bits of the second VEX byte are 1's compliment
2856 of RXB bits from REX. */
2857 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2859 /* Check the REX.W bit. */
2860 w
= (i
.rex
& REX_W
) ? 1 : 0;
2861 if (i
.tm
.opcode_modifier
.vexw
)
2866 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2870 i
.vex
.bytes
[2] = (w
<< 7
2871 | register_specifier
<< 3
2872 | vector_length
<< 2
2878 process_immext (void)
2882 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2884 /* SSE3 Instructions have the fixed operands with an opcode
2885 suffix which is coded in the same place as an 8-bit immediate
2886 field would be. Here we check those operands and remove them
2890 for (x
= 0; x
< i
.operands
; x
++)
2891 if (i
.op
[x
].regs
->reg_num
!= x
)
2892 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2893 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2899 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2900 which is coded in the same place as an 8-bit immediate field
2901 would be. Here we fake an 8-bit immediate operand from the
2902 opcode suffix stored in tm.extension_opcode.
2904 AVX instructions also use this encoding, for some of
2905 3 argument instructions. */
2907 gas_assert (i
.imm_operands
== 0
2909 || (i
.tm
.opcode_modifier
.vex
2910 && i
.operands
<= 4)));
2912 exp
= &im_expressions
[i
.imm_operands
++];
2913 i
.op
[i
.operands
].imms
= exp
;
2914 i
.types
[i
.operands
] = imm8
;
2916 exp
->X_op
= O_constant
;
2917 exp
->X_add_number
= i
.tm
.extension_opcode
;
2918 i
.tm
.extension_opcode
= None
;
2921 /* This is the guts of the machine-dependent assembler. LINE points to a
2922 machine dependent instruction. This function is supposed to emit
2923 the frags/bytes it assembles to. */
2926 md_assemble (char *line
)
2929 char mnemonic
[MAX_MNEM_SIZE
];
2930 const insn_template
*t
;
2932 /* Initialize globals. */
2933 memset (&i
, '\0', sizeof (i
));
2934 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2935 i
.reloc
[j
] = NO_RELOC
;
2936 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2937 memset (im_expressions
, '\0', sizeof (im_expressions
));
2938 save_stack_p
= save_stack
;
2940 /* First parse an instruction mnemonic & call i386_operand for the operands.
2941 We assume that the scrubber has arranged it so that line[0] is the valid
2942 start of a (possibly prefixed) mnemonic. */
2944 line
= parse_insn (line
, mnemonic
);
2948 line
= parse_operands (line
, mnemonic
);
2953 /* Now we've parsed the mnemonic into a set of templates, and have the
2954 operands at hand. */
2956 /* All intel opcodes have reversed operands except for "bound" and
2957 "enter". We also don't reverse intersegment "jmp" and "call"
2958 instructions with 2 immediate operands so that the immediate segment
2959 precedes the offset, as it does when in AT&T mode. */
2962 && (strcmp (mnemonic
, "bound") != 0)
2963 && (strcmp (mnemonic
, "invlpga") != 0)
2964 && !(operand_type_check (i
.types
[0], imm
)
2965 && operand_type_check (i
.types
[1], imm
)))
2968 /* The order of the immediates should be reversed
2969 for 2 immediates extrq and insertq instructions */
2970 if (i
.imm_operands
== 2
2971 && (strcmp (mnemonic
, "extrq") == 0
2972 || strcmp (mnemonic
, "insertq") == 0))
2973 swap_2_operands (0, 1);
2978 /* Don't optimize displacement for movabs since it only takes 64bit
2981 && (flag_code
!= CODE_64BIT
2982 || strcmp (mnemonic
, "movabs") != 0))
2985 /* Next, we find a template that matches the given insn,
2986 making sure the overlap of the given operands types is consistent
2987 with the template operand types. */
2989 if (!(t
= match_template ()))
2992 if (sse_check
!= sse_check_none
2993 && !i
.tm
.opcode_modifier
.noavx
2994 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2995 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2996 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2997 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2998 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2999 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3001 (sse_check
== sse_check_warning
3003 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3006 /* Zap movzx and movsx suffix. The suffix has been set from
3007 "word ptr" or "byte ptr" on the source operand in Intel syntax
3008 or extracted from mnemonic in AT&T syntax. But we'll use
3009 the destination register to choose the suffix for encoding. */
3010 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3012 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3013 there is no suffix, the default will be byte extension. */
3014 if (i
.reg_operands
!= 2
3017 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3022 if (i
.tm
.opcode_modifier
.fwait
)
3023 if (!add_prefix (FWAIT_OPCODE
))
3026 /* Check for lock without a lockable instruction. Destination operand
3027 must be memory unless it is xchg (0x86). */
3028 if (i
.prefix
[LOCK_PREFIX
]
3029 && (!i
.tm
.opcode_modifier
.islockable
3030 || i
.mem_operands
== 0
3031 || (i
.tm
.base_opcode
!= 0x86
3032 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3034 as_bad (_("expecting lockable instruction after `lock'"));
3038 /* Check string instruction segment overrides. */
3039 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3041 if (!check_string ())
3043 i
.disp_operands
= 0;
3046 if (!process_suffix ())
3049 /* Update operand types. */
3050 for (j
= 0; j
< i
.operands
; j
++)
3051 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3053 /* Make still unresolved immediate matches conform to size of immediate
3054 given in i.suffix. */
3055 if (!finalize_imm ())
3058 if (i
.types
[0].bitfield
.imm1
)
3059 i
.imm_operands
= 0; /* kludge for shift insns. */
3061 /* We only need to check those implicit registers for instructions
3062 with 3 operands or less. */
3063 if (i
.operands
<= 3)
3064 for (j
= 0; j
< i
.operands
; j
++)
3065 if (i
.types
[j
].bitfield
.inoutportreg
3066 || i
.types
[j
].bitfield
.shiftcount
3067 || i
.types
[j
].bitfield
.acc
3068 || i
.types
[j
].bitfield
.floatacc
)
3071 /* ImmExt should be processed after SSE2AVX. */
3072 if (!i
.tm
.opcode_modifier
.sse2avx
3073 && i
.tm
.opcode_modifier
.immext
)
3076 /* For insns with operands there are more diddles to do to the opcode. */
3079 if (!process_operands ())
3082 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3084 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3085 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3088 if (i
.tm
.opcode_modifier
.vex
)
3089 build_vex_prefix (t
);
3091 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3092 instructions may define INT_OPCODE as well, so avoid this corner
3093 case for those instructions that use MODRM. */
3094 if (i
.tm
.base_opcode
== INT_OPCODE
3095 && !i
.tm
.opcode_modifier
.modrm
3096 && i
.op
[0].imms
->X_add_number
== 3)
3098 i
.tm
.base_opcode
= INT3_OPCODE
;
3102 if ((i
.tm
.opcode_modifier
.jump
3103 || i
.tm
.opcode_modifier
.jumpbyte
3104 || i
.tm
.opcode_modifier
.jumpdword
)
3105 && i
.op
[0].disps
->X_op
== O_constant
)
3107 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3108 the absolute address given by the constant. Since ix86 jumps and
3109 calls are pc relative, we need to generate a reloc. */
3110 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3111 i
.op
[0].disps
->X_op
= O_symbol
;
3114 if (i
.tm
.opcode_modifier
.rex64
)
3117 /* For 8 bit registers we need an empty rex prefix. Also if the
3118 instruction already has a prefix, we need to convert old
3119 registers to new ones. */
3121 if ((i
.types
[0].bitfield
.reg8
3122 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3123 || (i
.types
[1].bitfield
.reg8
3124 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3125 || ((i
.types
[0].bitfield
.reg8
3126 || i
.types
[1].bitfield
.reg8
)
3131 i
.rex
|= REX_OPCODE
;
3132 for (x
= 0; x
< 2; x
++)
3134 /* Look for 8 bit operand that uses old registers. */
3135 if (i
.types
[x
].bitfield
.reg8
3136 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3138 /* In case it is "hi" register, give up. */
3139 if (i
.op
[x
].regs
->reg_num
> 3)
3140 as_bad (_("can't encode register '%s%s' in an "
3141 "instruction requiring REX prefix."),
3142 register_prefix
, i
.op
[x
].regs
->reg_name
);
3144 /* Otherwise it is equivalent to the extended register.
3145 Since the encoding doesn't change this is merely
3146 cosmetic cleanup for debug output. */
3148 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3154 add_prefix (REX_OPCODE
| i
.rex
);
3156 /* We are ready to output the insn. */
3161 parse_insn (char *line
, char *mnemonic
)
3164 char *token_start
= l
;
3167 const insn_template
*t
;
3170 /* Non-zero if we found a prefix only acceptable with string insns. */
3171 const char *expecting_string_instruction
= NULL
;
3176 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3181 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3183 as_bad (_("no such instruction: `%s'"), token_start
);
3188 if (!is_space_char (*l
)
3189 && *l
!= END_OF_INSN
3191 || (*l
!= PREFIX_SEPARATOR
3194 as_bad (_("invalid character %s in mnemonic"),
3195 output_invalid (*l
));
3198 if (token_start
== l
)
3200 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3201 as_bad (_("expecting prefix; got nothing"));
3203 as_bad (_("expecting mnemonic; got nothing"));
3207 /* Look up instruction (or prefix) via hash table. */
3208 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3210 if (*l
!= END_OF_INSN
3211 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3212 && current_templates
3213 && current_templates
->start
->opcode_modifier
.isprefix
)
3215 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3217 as_bad ((flag_code
!= CODE_64BIT
3218 ? _("`%s' is only supported in 64-bit mode")
3219 : _("`%s' is not supported in 64-bit mode")),
3220 current_templates
->start
->name
);
3223 /* If we are in 16-bit mode, do not allow addr16 or data16.
3224 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3225 if ((current_templates
->start
->opcode_modifier
.size16
3226 || current_templates
->start
->opcode_modifier
.size32
)
3227 && flag_code
!= CODE_64BIT
3228 && (current_templates
->start
->opcode_modifier
.size32
3229 ^ (flag_code
== CODE_16BIT
)))
3231 as_bad (_("redundant %s prefix"),
3232 current_templates
->start
->name
);
3235 /* Add prefix, checking for repeated prefixes. */
3236 switch (add_prefix (current_templates
->start
->base_opcode
))
3241 expecting_string_instruction
= current_templates
->start
->name
;
3246 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3253 if (!current_templates
)
3255 /* Check if we should swap operand in encoding. */
3256 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3262 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3265 if (!current_templates
)
3268 /* See if we can get a match by trimming off a suffix. */
3271 case WORD_MNEM_SUFFIX
:
3272 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3273 i
.suffix
= SHORT_MNEM_SUFFIX
;
3275 case BYTE_MNEM_SUFFIX
:
3276 case QWORD_MNEM_SUFFIX
:
3277 i
.suffix
= mnem_p
[-1];
3279 current_templates
= (const templates
*) hash_find (op_hash
,
3282 case SHORT_MNEM_SUFFIX
:
3283 case LONG_MNEM_SUFFIX
:
3286 i
.suffix
= mnem_p
[-1];
3288 current_templates
= (const templates
*) hash_find (op_hash
,
3297 if (intel_float_operand (mnemonic
) == 1)
3298 i
.suffix
= SHORT_MNEM_SUFFIX
;
3300 i
.suffix
= LONG_MNEM_SUFFIX
;
3302 current_templates
= (const templates
*) hash_find (op_hash
,
3307 if (!current_templates
)
3309 as_bad (_("no such instruction: `%s'"), token_start
);
3314 if (current_templates
->start
->opcode_modifier
.jump
3315 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3317 /* Check for a branch hint. We allow ",pt" and ",pn" for
3318 predict taken and predict not taken respectively.
3319 I'm not sure that branch hints actually do anything on loop
3320 and jcxz insns (JumpByte) for current Pentium4 chips. They
3321 may work in the future and it doesn't hurt to accept them
3323 if (l
[0] == ',' && l
[1] == 'p')
3327 if (!add_prefix (DS_PREFIX_OPCODE
))
3331 else if (l
[2] == 'n')
3333 if (!add_prefix (CS_PREFIX_OPCODE
))
3339 /* Any other comma loses. */
3342 as_bad (_("invalid character %s in mnemonic"),
3343 output_invalid (*l
));
3347 /* Check if instruction is supported on specified architecture. */
3349 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3351 supported
|= cpu_flags_match (t
);
3352 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3356 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3358 as_bad (flag_code
== CODE_64BIT
3359 ? _("`%s' is not supported in 64-bit mode")
3360 : _("`%s' is only supported in 64-bit mode"),
3361 current_templates
->start
->name
);
3364 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3366 as_bad (_("`%s' is not supported on `%s%s'"),
3367 current_templates
->start
->name
,
3368 cpu_arch_name
? cpu_arch_name
: default_arch
,
3369 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3374 if (!cpu_arch_flags
.bitfield
.cpui386
3375 && (flag_code
!= CODE_16BIT
))
3377 as_warn (_("use .code16 to ensure correct addressing mode"));
3380 /* Check for rep/repne without a string instruction. */
3381 if (expecting_string_instruction
)
3383 static templates override
;
3385 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3386 if (t
->opcode_modifier
.isstring
)
3388 if (t
>= current_templates
->end
)
3390 as_bad (_("expecting string instruction after `%s'"),
3391 expecting_string_instruction
);
3394 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3395 if (!t
->opcode_modifier
.isstring
)
3398 current_templates
= &override
;
3405 parse_operands (char *l
, const char *mnemonic
)
3409 /* 1 if operand is pending after ','. */
3410 unsigned int expecting_operand
= 0;
3412 /* Non-zero if operand parens not balanced. */
3413 unsigned int paren_not_balanced
;
3415 while (*l
!= END_OF_INSN
)
3417 /* Skip optional white space before operand. */
3418 if (is_space_char (*l
))
3420 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3422 as_bad (_("invalid character %s before operand %d"),
3423 output_invalid (*l
),
3427 token_start
= l
; /* after white space */
3428 paren_not_balanced
= 0;
3429 while (paren_not_balanced
|| *l
!= ',')
3431 if (*l
== END_OF_INSN
)
3433 if (paren_not_balanced
)
3436 as_bad (_("unbalanced parenthesis in operand %d."),
3439 as_bad (_("unbalanced brackets in operand %d."),
3444 break; /* we are done */
3446 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3448 as_bad (_("invalid character %s in operand %d"),
3449 output_invalid (*l
),
3456 ++paren_not_balanced
;
3458 --paren_not_balanced
;
3463 ++paren_not_balanced
;
3465 --paren_not_balanced
;
3469 if (l
!= token_start
)
3470 { /* Yes, we've read in another operand. */
3471 unsigned int operand_ok
;
3472 this_operand
= i
.operands
++;
3473 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3474 if (i
.operands
> MAX_OPERANDS
)
3476 as_bad (_("spurious operands; (%d operands/instruction max)"),
3480 /* Now parse operand adding info to 'i' as we go along. */
3481 END_STRING_AND_SAVE (l
);
3485 i386_intel_operand (token_start
,
3486 intel_float_operand (mnemonic
));
3488 operand_ok
= i386_att_operand (token_start
);
3490 RESTORE_END_STRING (l
);
3496 if (expecting_operand
)
3498 expecting_operand_after_comma
:
3499 as_bad (_("expecting operand after ','; got nothing"));
3504 as_bad (_("expecting operand before ','; got nothing"));
3509 /* Now *l must be either ',' or END_OF_INSN. */
3512 if (*++l
== END_OF_INSN
)
3514 /* Just skip it, if it's \n complain. */
3515 goto expecting_operand_after_comma
;
3517 expecting_operand
= 1;
3524 swap_2_operands (int xchg1
, int xchg2
)
3526 union i386_op temp_op
;
3527 i386_operand_type temp_type
;
3528 enum bfd_reloc_code_real temp_reloc
;
3530 temp_type
= i
.types
[xchg2
];
3531 i
.types
[xchg2
] = i
.types
[xchg1
];
3532 i
.types
[xchg1
] = temp_type
;
3533 temp_op
= i
.op
[xchg2
];
3534 i
.op
[xchg2
] = i
.op
[xchg1
];
3535 i
.op
[xchg1
] = temp_op
;
3536 temp_reloc
= i
.reloc
[xchg2
];
3537 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3538 i
.reloc
[xchg1
] = temp_reloc
;
3542 swap_operands (void)
3548 swap_2_operands (1, i
.operands
- 2);
3551 swap_2_operands (0, i
.operands
- 1);
3557 if (i
.mem_operands
== 2)
3559 const seg_entry
*temp_seg
;
3560 temp_seg
= i
.seg
[0];
3561 i
.seg
[0] = i
.seg
[1];
3562 i
.seg
[1] = temp_seg
;
3566 /* Try to ensure constant immediates are represented in the smallest
3571 char guess_suffix
= 0;
3575 guess_suffix
= i
.suffix
;
3576 else if (i
.reg_operands
)
3578 /* Figure out a suffix from the last register operand specified.
3579 We can't do this properly yet, ie. excluding InOutPortReg,
3580 but the following works for instructions with immediates.
3581 In any case, we can't set i.suffix yet. */
3582 for (op
= i
.operands
; --op
>= 0;)
3583 if (i
.types
[op
].bitfield
.reg8
)
3585 guess_suffix
= BYTE_MNEM_SUFFIX
;
3588 else if (i
.types
[op
].bitfield
.reg16
)
3590 guess_suffix
= WORD_MNEM_SUFFIX
;
3593 else if (i
.types
[op
].bitfield
.reg32
)
3595 guess_suffix
= LONG_MNEM_SUFFIX
;
3598 else if (i
.types
[op
].bitfield
.reg64
)
3600 guess_suffix
= QWORD_MNEM_SUFFIX
;
3604 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3605 guess_suffix
= WORD_MNEM_SUFFIX
;
3607 for (op
= i
.operands
; --op
>= 0;)
3608 if (operand_type_check (i
.types
[op
], imm
))
3610 switch (i
.op
[op
].imms
->X_op
)
3613 /* If a suffix is given, this operand may be shortened. */
3614 switch (guess_suffix
)
3616 case LONG_MNEM_SUFFIX
:
3617 i
.types
[op
].bitfield
.imm32
= 1;
3618 i
.types
[op
].bitfield
.imm64
= 1;
3620 case WORD_MNEM_SUFFIX
:
3621 i
.types
[op
].bitfield
.imm16
= 1;
3622 i
.types
[op
].bitfield
.imm32
= 1;
3623 i
.types
[op
].bitfield
.imm32s
= 1;
3624 i
.types
[op
].bitfield
.imm64
= 1;
3626 case BYTE_MNEM_SUFFIX
:
3627 i
.types
[op
].bitfield
.imm8
= 1;
3628 i
.types
[op
].bitfield
.imm8s
= 1;
3629 i
.types
[op
].bitfield
.imm16
= 1;
3630 i
.types
[op
].bitfield
.imm32
= 1;
3631 i
.types
[op
].bitfield
.imm32s
= 1;
3632 i
.types
[op
].bitfield
.imm64
= 1;
3636 /* If this operand is at most 16 bits, convert it
3637 to a signed 16 bit number before trying to see
3638 whether it will fit in an even smaller size.
3639 This allows a 16-bit operand such as $0xffe0 to
3640 be recognised as within Imm8S range. */
3641 if ((i
.types
[op
].bitfield
.imm16
)
3642 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3644 i
.op
[op
].imms
->X_add_number
=
3645 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3647 if ((i
.types
[op
].bitfield
.imm32
)
3648 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3651 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3652 ^ ((offsetT
) 1 << 31))
3653 - ((offsetT
) 1 << 31));
3656 = operand_type_or (i
.types
[op
],
3657 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3659 /* We must avoid matching of Imm32 templates when 64bit
3660 only immediate is available. */
3661 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3662 i
.types
[op
].bitfield
.imm32
= 0;
3669 /* Symbols and expressions. */
3671 /* Convert symbolic operand to proper sizes for matching, but don't
3672 prevent matching a set of insns that only supports sizes other
3673 than those matching the insn suffix. */
3675 i386_operand_type mask
, allowed
;
3676 const insn_template
*t
;
3678 operand_type_set (&mask
, 0);
3679 operand_type_set (&allowed
, 0);
3681 for (t
= current_templates
->start
;
3682 t
< current_templates
->end
;
3684 allowed
= operand_type_or (allowed
,
3685 t
->operand_types
[op
]);
3686 switch (guess_suffix
)
3688 case QWORD_MNEM_SUFFIX
:
3689 mask
.bitfield
.imm64
= 1;
3690 mask
.bitfield
.imm32s
= 1;
3692 case LONG_MNEM_SUFFIX
:
3693 mask
.bitfield
.imm32
= 1;
3695 case WORD_MNEM_SUFFIX
:
3696 mask
.bitfield
.imm16
= 1;
3698 case BYTE_MNEM_SUFFIX
:
3699 mask
.bitfield
.imm8
= 1;
3704 allowed
= operand_type_and (mask
, allowed
);
3705 if (!operand_type_all_zero (&allowed
))
3706 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3713 /* Try to use the smallest displacement type too. */
3715 optimize_disp (void)
3719 for (op
= i
.operands
; --op
>= 0;)
3720 if (operand_type_check (i
.types
[op
], disp
))
3722 if (i
.op
[op
].disps
->X_op
== O_constant
)
3724 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3726 if (i
.types
[op
].bitfield
.disp16
3727 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3729 /* If this operand is at most 16 bits, convert
3730 to a signed 16 bit number and don't use 64bit
3732 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3733 i
.types
[op
].bitfield
.disp64
= 0;
3735 if (i
.types
[op
].bitfield
.disp32
3736 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3738 /* If this operand is at most 32 bits, convert
3739 to a signed 32 bit number and don't use 64bit
3741 op_disp
&= (((offsetT
) 2 << 31) - 1);
3742 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3743 i
.types
[op
].bitfield
.disp64
= 0;
3745 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3747 i
.types
[op
].bitfield
.disp8
= 0;
3748 i
.types
[op
].bitfield
.disp16
= 0;
3749 i
.types
[op
].bitfield
.disp32
= 0;
3750 i
.types
[op
].bitfield
.disp32s
= 0;
3751 i
.types
[op
].bitfield
.disp64
= 0;
3755 else if (flag_code
== CODE_64BIT
)
3757 if (fits_in_signed_long (op_disp
))
3759 i
.types
[op
].bitfield
.disp64
= 0;
3760 i
.types
[op
].bitfield
.disp32s
= 1;
3762 if (i
.prefix
[ADDR_PREFIX
]
3763 && fits_in_unsigned_long (op_disp
))
3764 i
.types
[op
].bitfield
.disp32
= 1;
3766 if ((i
.types
[op
].bitfield
.disp32
3767 || i
.types
[op
].bitfield
.disp32s
3768 || i
.types
[op
].bitfield
.disp16
)
3769 && fits_in_signed_byte (op_disp
))
3770 i
.types
[op
].bitfield
.disp8
= 1;
3772 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3773 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3775 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3776 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3777 i
.types
[op
].bitfield
.disp8
= 0;
3778 i
.types
[op
].bitfield
.disp16
= 0;
3779 i
.types
[op
].bitfield
.disp32
= 0;
3780 i
.types
[op
].bitfield
.disp32s
= 0;
3781 i
.types
[op
].bitfield
.disp64
= 0;
3784 /* We only support 64bit displacement on constants. */
3785 i
.types
[op
].bitfield
.disp64
= 0;
3789 /* Check if operands are valid for the instrucrtion. Update VEX
3793 VEX_check_operands (const insn_template
*t
)
3795 if (!t
->opcode_modifier
.vex
)
3798 /* Only check VEX_Imm4, which must be the first operand. */
3799 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3801 if (i
.op
[0].imms
->X_op
!= O_constant
3802 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3808 /* Turn off Imm8 so that update_imm won't complain. */
3809 i
.types
[0] = vec_imm4
;
3815 static const insn_template
*
3816 match_template (void)
3818 /* Points to template once we've found it. */
3819 const insn_template
*t
;
3820 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3821 i386_operand_type overlap4
;
3822 unsigned int found_reverse_match
;
3823 i386_opcode_modifier suffix_check
;
3824 i386_operand_type operand_types
[MAX_OPERANDS
];
3825 int addr_prefix_disp
;
3827 unsigned int found_cpu_match
;
3828 unsigned int check_register
;
3830 #if MAX_OPERANDS != 5
3831 # error "MAX_OPERANDS must be 5."
3834 found_reverse_match
= 0;
3835 addr_prefix_disp
= -1;
3837 memset (&suffix_check
, 0, sizeof (suffix_check
));
3838 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3839 suffix_check
.no_bsuf
= 1;
3840 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3841 suffix_check
.no_wsuf
= 1;
3842 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3843 suffix_check
.no_ssuf
= 1;
3844 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3845 suffix_check
.no_lsuf
= 1;
3846 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3847 suffix_check
.no_qsuf
= 1;
3848 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3849 suffix_check
.no_ldsuf
= 1;
3851 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3853 addr_prefix_disp
= -1;
3855 /* Must have right number of operands. */
3856 i
.error
= number_of_operands_mismatch
;
3857 if (i
.operands
!= t
->operands
)
3860 /* Check processor support. */
3861 i
.error
= unsupported
;
3862 found_cpu_match
= (cpu_flags_match (t
)
3863 == CPU_FLAGS_PERFECT_MATCH
);
3864 if (!found_cpu_match
)
3867 /* Check old gcc support. */
3868 i
.error
= old_gcc_only
;
3869 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3872 /* Check AT&T mnemonic. */
3873 i
.error
= unsupported_with_intel_mnemonic
;
3874 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3877 /* Check AT&T/Intel syntax. */
3878 i
.error
= unsupported_syntax
;
3879 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3880 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3883 /* Check the suffix, except for some instructions in intel mode. */
3884 i
.error
= invalid_instruction_suffix
;
3885 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3886 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3887 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3888 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3889 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3890 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3891 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3894 if (!operand_size_match (t
))
3897 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3898 operand_types
[j
] = t
->operand_types
[j
];
3900 /* In general, don't allow 64-bit operands in 32-bit mode. */
3901 if (i
.suffix
== QWORD_MNEM_SUFFIX
3902 && flag_code
!= CODE_64BIT
3904 ? (!t
->opcode_modifier
.ignoresize
3905 && !intel_float_operand (t
->name
))
3906 : intel_float_operand (t
->name
) != 2)
3907 && ((!operand_types
[0].bitfield
.regmmx
3908 && !operand_types
[0].bitfield
.regxmm
3909 && !operand_types
[0].bitfield
.regymm
)
3910 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3911 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3912 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3913 && (t
->base_opcode
!= 0x0fc7
3914 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3917 /* In general, don't allow 32-bit operands on pre-386. */
3918 else if (i
.suffix
== LONG_MNEM_SUFFIX
3919 && !cpu_arch_flags
.bitfield
.cpui386
3921 ? (!t
->opcode_modifier
.ignoresize
3922 && !intel_float_operand (t
->name
))
3923 : intel_float_operand (t
->name
) != 2)
3924 && ((!operand_types
[0].bitfield
.regmmx
3925 && !operand_types
[0].bitfield
.regxmm
)
3926 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3927 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3930 /* Do not verify operands when there are none. */
3934 /* We've found a match; break out of loop. */
3938 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3939 into Disp32/Disp16/Disp32 operand. */
3940 if (i
.prefix
[ADDR_PREFIX
] != 0)
3942 /* There should be only one Disp operand. */
3946 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3948 if (operand_types
[j
].bitfield
.disp16
)
3950 addr_prefix_disp
= j
;
3951 operand_types
[j
].bitfield
.disp32
= 1;
3952 operand_types
[j
].bitfield
.disp16
= 0;
3958 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3960 if (operand_types
[j
].bitfield
.disp32
)
3962 addr_prefix_disp
= j
;
3963 operand_types
[j
].bitfield
.disp32
= 0;
3964 operand_types
[j
].bitfield
.disp16
= 1;
3970 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3972 if (operand_types
[j
].bitfield
.disp64
)
3974 addr_prefix_disp
= j
;
3975 operand_types
[j
].bitfield
.disp64
= 0;
3976 operand_types
[j
].bitfield
.disp32
= 1;
3984 /* We check register size only if size of operands can be
3985 encoded the canonical way. */
3986 check_register
= t
->opcode_modifier
.w
;
3987 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3988 switch (t
->operands
)
3991 if (!operand_type_match (overlap0
, i
.types
[0]))
3995 /* xchg %eax, %eax is a special case. It is an aliase for nop
3996 only in 32bit mode and we can use opcode 0x90. In 64bit
3997 mode, we can't use 0x90 for xchg %eax, %eax since it should
3998 zero-extend %eax to %rax. */
3999 if (flag_code
== CODE_64BIT
4000 && t
->base_opcode
== 0x90
4001 && operand_type_equal (&i
.types
[0], &acc32
)
4002 && operand_type_equal (&i
.types
[1], &acc32
))
4006 /* If we swap operand in encoding, we either match
4007 the next one or reverse direction of operands. */
4008 if (t
->opcode_modifier
.s
)
4010 else if (t
->opcode_modifier
.d
)
4015 /* If we swap operand in encoding, we match the next one. */
4016 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4020 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4021 if (!operand_type_match (overlap0
, i
.types
[0])
4022 || !operand_type_match (overlap1
, i
.types
[1])
4024 && !operand_type_register_match (overlap0
, i
.types
[0],
4026 overlap1
, i
.types
[1],
4029 /* Check if other direction is valid ... */
4030 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4034 /* Try reversing direction of operands. */
4035 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4036 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4037 if (!operand_type_match (overlap0
, i
.types
[0])
4038 || !operand_type_match (overlap1
, i
.types
[1])
4040 && !operand_type_register_match (overlap0
,
4047 /* Does not match either direction. */
4050 /* found_reverse_match holds which of D or FloatDR
4052 if (t
->opcode_modifier
.d
)
4053 found_reverse_match
= Opcode_D
;
4054 else if (t
->opcode_modifier
.floatd
)
4055 found_reverse_match
= Opcode_FloatD
;
4057 found_reverse_match
= 0;
4058 if (t
->opcode_modifier
.floatr
)
4059 found_reverse_match
|= Opcode_FloatR
;
4063 /* Found a forward 2 operand match here. */
4064 switch (t
->operands
)
4067 overlap4
= operand_type_and (i
.types
[4],
4070 overlap3
= operand_type_and (i
.types
[3],
4073 overlap2
= operand_type_and (i
.types
[2],
4078 switch (t
->operands
)
4081 if (!operand_type_match (overlap4
, i
.types
[4])
4082 || !operand_type_register_match (overlap3
,
4090 if (!operand_type_match (overlap3
, i
.types
[3])
4092 && !operand_type_register_match (overlap2
,
4100 /* Here we make use of the fact that there are no
4101 reverse match 3 operand instructions, and all 3
4102 operand instructions only need to be checked for
4103 register consistency between operands 2 and 3. */
4104 if (!operand_type_match (overlap2
, i
.types
[2])
4106 && !operand_type_register_match (overlap1
,
4116 /* Found either forward/reverse 2, 3 or 4 operand match here:
4117 slip through to break. */
4119 if (!found_cpu_match
)
4121 found_reverse_match
= 0;
4125 /* Check if VEX operands are valid. */
4126 if (VEX_check_operands (t
))
4129 /* We've found a match; break out of loop. */
4133 if (t
== current_templates
->end
)
4135 /* We found no match. */
4136 const char *err_msg
;
4141 case operand_size_mismatch
:
4142 err_msg
= _("operand size mismatch");
4144 case operand_type_mismatch
:
4145 err_msg
= _("operand type mismatch");
4147 case register_type_mismatch
:
4148 err_msg
= _("register type mismatch");
4150 case number_of_operands_mismatch
:
4151 err_msg
= _("number of operands mismatch");
4153 case invalid_instruction_suffix
:
4154 err_msg
= _("invalid instruction suffix");
4157 err_msg
= _("Imm4 isn't the first operand");
4160 err_msg
= _("only supported with old gcc");
4162 case unsupported_with_intel_mnemonic
:
4163 err_msg
= _("unsupported with Intel mnemonic");
4165 case unsupported_syntax
:
4166 err_msg
= _("unsupported syntax");
4169 err_msg
= _("unsupported");
4172 as_bad (_("%s for `%s'"), err_msg
,
4173 current_templates
->start
->name
);
4177 if (!quiet_warnings
)
4180 && (i
.types
[0].bitfield
.jumpabsolute
4181 != operand_types
[0].bitfield
.jumpabsolute
))
4183 as_warn (_("indirect %s without `*'"), t
->name
);
4186 if (t
->opcode_modifier
.isprefix
4187 && t
->opcode_modifier
.ignoresize
)
4189 /* Warn them that a data or address size prefix doesn't
4190 affect assembly of the next line of code. */
4191 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4195 /* Copy the template we found. */
4198 if (addr_prefix_disp
!= -1)
4199 i
.tm
.operand_types
[addr_prefix_disp
]
4200 = operand_types
[addr_prefix_disp
];
4202 if (found_reverse_match
)
4204 /* If we found a reverse match we must alter the opcode
4205 direction bit. found_reverse_match holds bits to change
4206 (different for int & float insns). */
4208 i
.tm
.base_opcode
^= found_reverse_match
;
4210 i
.tm
.operand_types
[0] = operand_types
[1];
4211 i
.tm
.operand_types
[1] = operand_types
[0];
4220 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4221 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4223 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4225 as_bad (_("`%s' operand %d must use `%ses' segment"),
4231 /* There's only ever one segment override allowed per instruction.
4232 This instruction possibly has a legal segment override on the
4233 second operand, so copy the segment to where non-string
4234 instructions store it, allowing common code. */
4235 i
.seg
[0] = i
.seg
[1];
4237 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4239 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4241 as_bad (_("`%s' operand %d must use `%ses' segment"),
4252 process_suffix (void)
4254 /* If matched instruction specifies an explicit instruction mnemonic
4256 if (i
.tm
.opcode_modifier
.size16
)
4257 i
.suffix
= WORD_MNEM_SUFFIX
;
4258 else if (i
.tm
.opcode_modifier
.size32
)
4259 i
.suffix
= LONG_MNEM_SUFFIX
;
4260 else if (i
.tm
.opcode_modifier
.size64
)
4261 i
.suffix
= QWORD_MNEM_SUFFIX
;
4262 else if (i
.reg_operands
)
4264 /* If there's no instruction mnemonic suffix we try to invent one
4265 based on register operands. */
4268 /* We take i.suffix from the last register operand specified,
4269 Destination register type is more significant than source
4270 register type. crc32 in SSE4.2 prefers source register
4272 if (i
.tm
.base_opcode
== 0xf20f38f1)
4274 if (i
.types
[0].bitfield
.reg16
)
4275 i
.suffix
= WORD_MNEM_SUFFIX
;
4276 else if (i
.types
[0].bitfield
.reg32
)
4277 i
.suffix
= LONG_MNEM_SUFFIX
;
4278 else if (i
.types
[0].bitfield
.reg64
)
4279 i
.suffix
= QWORD_MNEM_SUFFIX
;
4281 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4283 if (i
.types
[0].bitfield
.reg8
)
4284 i
.suffix
= BYTE_MNEM_SUFFIX
;
4291 if (i
.tm
.base_opcode
== 0xf20f38f1
4292 || i
.tm
.base_opcode
== 0xf20f38f0)
4294 /* We have to know the operand size for crc32. */
4295 as_bad (_("ambiguous memory operand size for `%s`"),
4300 for (op
= i
.operands
; --op
>= 0;)
4301 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4303 if (i
.types
[op
].bitfield
.reg8
)
4305 i
.suffix
= BYTE_MNEM_SUFFIX
;
4308 else if (i
.types
[op
].bitfield
.reg16
)
4310 i
.suffix
= WORD_MNEM_SUFFIX
;
4313 else if (i
.types
[op
].bitfield
.reg32
)
4315 i
.suffix
= LONG_MNEM_SUFFIX
;
4318 else if (i
.types
[op
].bitfield
.reg64
)
4320 i
.suffix
= QWORD_MNEM_SUFFIX
;
4326 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4329 && i
.tm
.opcode_modifier
.ignoresize
4330 && i
.tm
.opcode_modifier
.no_bsuf
)
4332 else if (!check_byte_reg ())
4335 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4338 && i
.tm
.opcode_modifier
.ignoresize
4339 && i
.tm
.opcode_modifier
.no_lsuf
)
4341 else if (!check_long_reg ())
4344 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4347 && i
.tm
.opcode_modifier
.ignoresize
4348 && i
.tm
.opcode_modifier
.no_qsuf
)
4350 else if (!check_qword_reg ())
4353 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4356 && i
.tm
.opcode_modifier
.ignoresize
4357 && i
.tm
.opcode_modifier
.no_wsuf
)
4359 else if (!check_word_reg ())
4362 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4363 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4365 /* Skip if the instruction has x/y suffix. match_template
4366 should check if it is a valid suffix. */
4368 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4369 /* Do nothing if the instruction is going to ignore the prefix. */
4374 else if (i
.tm
.opcode_modifier
.defaultsize
4376 /* exclude fldenv/frstor/fsave/fstenv */
4377 && i
.tm
.opcode_modifier
.no_ssuf
)
4379 i
.suffix
= stackop_size
;
4381 else if (intel_syntax
4383 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4384 || i
.tm
.opcode_modifier
.jumpbyte
4385 || i
.tm
.opcode_modifier
.jumpintersegment
4386 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4387 && i
.tm
.extension_opcode
<= 3)))
4392 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4394 i
.suffix
= QWORD_MNEM_SUFFIX
;
4398 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4399 i
.suffix
= LONG_MNEM_SUFFIX
;
4402 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4403 i
.suffix
= WORD_MNEM_SUFFIX
;
4412 if (i
.tm
.opcode_modifier
.w
)
4414 as_bad (_("no instruction mnemonic suffix given and "
4415 "no register operands; can't size instruction"));
4421 unsigned int suffixes
;
4423 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4424 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4426 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4428 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4430 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4432 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4435 /* There are more than suffix matches. */
4436 if (i
.tm
.opcode_modifier
.w
4437 || ((suffixes
& (suffixes
- 1))
4438 && !i
.tm
.opcode_modifier
.defaultsize
4439 && !i
.tm
.opcode_modifier
.ignoresize
))
4441 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4447 /* Change the opcode based on the operand size given by i.suffix;
4448 We don't need to change things for byte insns. */
4451 && i
.suffix
!= BYTE_MNEM_SUFFIX
4452 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4453 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4455 /* It's not a byte, select word/dword operation. */
4456 if (i
.tm
.opcode_modifier
.w
)
4458 if (i
.tm
.opcode_modifier
.shortform
)
4459 i
.tm
.base_opcode
|= 8;
4461 i
.tm
.base_opcode
|= 1;
4464 /* Now select between word & dword operations via the operand
4465 size prefix, except for instructions that will ignore this
4467 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4469 /* The address size override prefix changes the size of the
4471 if ((flag_code
== CODE_32BIT
4472 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4473 || (flag_code
!= CODE_32BIT
4474 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4475 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4478 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4479 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4480 && !i
.tm
.opcode_modifier
.ignoresize
4481 && !i
.tm
.opcode_modifier
.floatmf
4482 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4483 || (flag_code
== CODE_64BIT
4484 && i
.tm
.opcode_modifier
.jumpbyte
)))
4486 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4488 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4489 prefix
= ADDR_PREFIX_OPCODE
;
4491 if (!add_prefix (prefix
))
4495 /* Set mode64 for an operand. */
4496 if (i
.suffix
== QWORD_MNEM_SUFFIX
4497 && flag_code
== CODE_64BIT
4498 && !i
.tm
.opcode_modifier
.norex64
)
4500 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4501 need rex64. cmpxchg8b is also a special case. */
4502 if (! (i
.operands
== 2
4503 && i
.tm
.base_opcode
== 0x90
4504 && i
.tm
.extension_opcode
== None
4505 && operand_type_equal (&i
.types
[0], &acc64
)
4506 && operand_type_equal (&i
.types
[1], &acc64
))
4507 && ! (i
.operands
== 1
4508 && i
.tm
.base_opcode
== 0xfc7
4509 && i
.tm
.extension_opcode
== 1
4510 && !operand_type_check (i
.types
[0], reg
)
4511 && operand_type_check (i
.types
[0], anymem
)))
4515 /* Size floating point instruction. */
4516 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4517 if (i
.tm
.opcode_modifier
.floatmf
)
4518 i
.tm
.base_opcode
^= 4;
4525 check_byte_reg (void)
4529 for (op
= i
.operands
; --op
>= 0;)
4531 /* If this is an eight bit register, it's OK. If it's the 16 or
4532 32 bit version of an eight bit register, we will just use the
4533 low portion, and that's OK too. */
4534 if (i
.types
[op
].bitfield
.reg8
)
4537 /* crc32 doesn't generate this warning. */
4538 if (i
.tm
.base_opcode
== 0xf20f38f0)
4541 if ((i
.types
[op
].bitfield
.reg16
4542 || i
.types
[op
].bitfield
.reg32
4543 || i
.types
[op
].bitfield
.reg64
)
4544 && i
.op
[op
].regs
->reg_num
< 4)
4546 /* Prohibit these changes in the 64bit mode, since the
4547 lowering is more complicated. */
4548 if (flag_code
== CODE_64BIT
4549 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4551 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4552 register_prefix
, i
.op
[op
].regs
->reg_name
,
4556 #if REGISTER_WARNINGS
4558 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4559 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4561 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4562 ? REGNAM_AL
- REGNAM_AX
4563 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4565 i
.op
[op
].regs
->reg_name
,
4570 /* Any other register is bad. */
4571 if (i
.types
[op
].bitfield
.reg16
4572 || i
.types
[op
].bitfield
.reg32
4573 || i
.types
[op
].bitfield
.reg64
4574 || i
.types
[op
].bitfield
.regmmx
4575 || i
.types
[op
].bitfield
.regxmm
4576 || i
.types
[op
].bitfield
.regymm
4577 || i
.types
[op
].bitfield
.sreg2
4578 || i
.types
[op
].bitfield
.sreg3
4579 || i
.types
[op
].bitfield
.control
4580 || i
.types
[op
].bitfield
.debug
4581 || i
.types
[op
].bitfield
.test
4582 || i
.types
[op
].bitfield
.floatreg
4583 || i
.types
[op
].bitfield
.floatacc
)
4585 as_bad (_("`%s%s' not allowed with `%s%c'"),
4587 i
.op
[op
].regs
->reg_name
,
4597 check_long_reg (void)
4601 for (op
= i
.operands
; --op
>= 0;)
4602 /* Reject eight bit registers, except where the template requires
4603 them. (eg. movzb) */
4604 if (i
.types
[op
].bitfield
.reg8
4605 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4606 || i
.tm
.operand_types
[op
].bitfield
.reg32
4607 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4609 as_bad (_("`%s%s' not allowed with `%s%c'"),
4611 i
.op
[op
].regs
->reg_name
,
4616 /* Warn if the e prefix on a general reg is missing. */
4617 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4618 && i
.types
[op
].bitfield
.reg16
4619 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4620 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4622 /* Prohibit these changes in the 64bit mode, since the
4623 lowering is more complicated. */
4624 if (flag_code
== CODE_64BIT
)
4626 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4627 register_prefix
, i
.op
[op
].regs
->reg_name
,
4631 #if REGISTER_WARNINGS
4633 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4635 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4637 i
.op
[op
].regs
->reg_name
,
4641 /* Warn if the r prefix on a general reg is missing. */
4642 else if (i
.types
[op
].bitfield
.reg64
4643 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4644 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4647 && i
.tm
.opcode_modifier
.toqword
4648 && !i
.types
[0].bitfield
.regxmm
)
4650 /* Convert to QWORD. We want REX byte. */
4651 i
.suffix
= QWORD_MNEM_SUFFIX
;
4655 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4656 register_prefix
, i
.op
[op
].regs
->reg_name
,
4665 check_qword_reg (void)
4669 for (op
= i
.operands
; --op
>= 0; )
4670 /* Reject eight bit registers, except where the template requires
4671 them. (eg. movzb) */
4672 if (i
.types
[op
].bitfield
.reg8
4673 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4674 || i
.tm
.operand_types
[op
].bitfield
.reg32
4675 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4677 as_bad (_("`%s%s' not allowed with `%s%c'"),
4679 i
.op
[op
].regs
->reg_name
,
4684 /* Warn if the e prefix on a general reg is missing. */
4685 else if ((i
.types
[op
].bitfield
.reg16
4686 || i
.types
[op
].bitfield
.reg32
)
4687 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4688 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4690 /* Prohibit these changes in the 64bit mode, since the
4691 lowering is more complicated. */
4693 && i
.tm
.opcode_modifier
.todword
4694 && !i
.types
[0].bitfield
.regxmm
)
4696 /* Convert to DWORD. We don't want REX byte. */
4697 i
.suffix
= LONG_MNEM_SUFFIX
;
4701 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4702 register_prefix
, i
.op
[op
].regs
->reg_name
,
4711 check_word_reg (void)
4714 for (op
= i
.operands
; --op
>= 0;)
4715 /* Reject eight bit registers, except where the template requires
4716 them. (eg. movzb) */
4717 if (i
.types
[op
].bitfield
.reg8
4718 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4719 || i
.tm
.operand_types
[op
].bitfield
.reg32
4720 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4722 as_bad (_("`%s%s' not allowed with `%s%c'"),
4724 i
.op
[op
].regs
->reg_name
,
4729 /* Warn if the e prefix on a general reg is present. */
4730 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4731 && i
.types
[op
].bitfield
.reg32
4732 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4733 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4735 /* Prohibit these changes in the 64bit mode, since the
4736 lowering is more complicated. */
4737 if (flag_code
== CODE_64BIT
)
4739 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4740 register_prefix
, i
.op
[op
].regs
->reg_name
,
4745 #if REGISTER_WARNINGS
4746 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4748 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4750 i
.op
[op
].regs
->reg_name
,
4758 update_imm (unsigned int j
)
4760 i386_operand_type overlap
= i
.types
[j
];
4761 if ((overlap
.bitfield
.imm8
4762 || overlap
.bitfield
.imm8s
4763 || overlap
.bitfield
.imm16
4764 || overlap
.bitfield
.imm32
4765 || overlap
.bitfield
.imm32s
4766 || overlap
.bitfield
.imm64
)
4767 && !operand_type_equal (&overlap
, &imm8
)
4768 && !operand_type_equal (&overlap
, &imm8s
)
4769 && !operand_type_equal (&overlap
, &imm16
)
4770 && !operand_type_equal (&overlap
, &imm32
)
4771 && !operand_type_equal (&overlap
, &imm32s
)
4772 && !operand_type_equal (&overlap
, &imm64
))
4776 i386_operand_type temp
;
4778 operand_type_set (&temp
, 0);
4779 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4781 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4782 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4784 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4785 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4786 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4788 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4789 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4792 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4795 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4796 || operand_type_equal (&overlap
, &imm16_32
)
4797 || operand_type_equal (&overlap
, &imm16_32s
))
4799 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4804 if (!operand_type_equal (&overlap
, &imm8
)
4805 && !operand_type_equal (&overlap
, &imm8s
)
4806 && !operand_type_equal (&overlap
, &imm16
)
4807 && !operand_type_equal (&overlap
, &imm32
)
4808 && !operand_type_equal (&overlap
, &imm32s
)
4809 && !operand_type_equal (&overlap
, &imm64
))
4811 as_bad (_("no instruction mnemonic suffix given; "
4812 "can't determine immediate size"));
4816 i
.types
[j
] = overlap
;
4826 /* Update the first 2 immediate operands. */
4827 n
= i
.operands
> 2 ? 2 : i
.operands
;
4830 for (j
= 0; j
< n
; j
++)
4831 if (update_imm (j
) == 0)
4834 /* The 3rd operand can't be immediate operand. */
4835 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4842 bad_implicit_operand (int xmm
)
4844 const char *ireg
= xmm
? "xmm0" : "ymm0";
4847 as_bad (_("the last operand of `%s' must be `%s%s'"),
4848 i
.tm
.name
, register_prefix
, ireg
);
4850 as_bad (_("the first operand of `%s' must be `%s%s'"),
4851 i
.tm
.name
, register_prefix
, ireg
);
4856 process_operands (void)
4858 /* Default segment register this instruction will use for memory
4859 accesses. 0 means unknown. This is only for optimizing out
4860 unnecessary segment overrides. */
4861 const seg_entry
*default_seg
= 0;
4863 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4865 unsigned int dupl
= i
.operands
;
4866 unsigned int dest
= dupl
- 1;
4869 /* The destination must be an xmm register. */
4870 gas_assert (i
.reg_operands
4871 && MAX_OPERANDS
> dupl
4872 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4874 if (i
.tm
.opcode_modifier
.firstxmm0
)
4876 /* The first operand is implicit and must be xmm0. */
4877 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4878 if (i
.op
[0].regs
->reg_num
!= 0)
4879 return bad_implicit_operand (1);
4881 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4883 /* Keep xmm0 for instructions with VEX prefix and 3
4889 /* We remove the first xmm0 and keep the number of
4890 operands unchanged, which in fact duplicates the
4892 for (j
= 1; j
< i
.operands
; j
++)
4894 i
.op
[j
- 1] = i
.op
[j
];
4895 i
.types
[j
- 1] = i
.types
[j
];
4896 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4900 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4902 gas_assert ((MAX_OPERANDS
- 1) > dupl
4903 && (i
.tm
.opcode_modifier
.vexsources
4906 /* Add the implicit xmm0 for instructions with VEX prefix
4908 for (j
= i
.operands
; j
> 0; j
--)
4910 i
.op
[j
] = i
.op
[j
- 1];
4911 i
.types
[j
] = i
.types
[j
- 1];
4912 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4915 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4916 i
.types
[0] = regxmm
;
4917 i
.tm
.operand_types
[0] = regxmm
;
4920 i
.reg_operands
+= 2;
4925 i
.op
[dupl
] = i
.op
[dest
];
4926 i
.types
[dupl
] = i
.types
[dest
];
4927 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4936 i
.op
[dupl
] = i
.op
[dest
];
4937 i
.types
[dupl
] = i
.types
[dest
];
4938 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4941 if (i
.tm
.opcode_modifier
.immext
)
4944 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4948 /* The first operand is implicit and must be xmm0/ymm0. */
4949 gas_assert (i
.reg_operands
4950 && (operand_type_equal (&i
.types
[0], ®xmm
)
4951 || operand_type_equal (&i
.types
[0], ®ymm
)));
4952 if (i
.op
[0].regs
->reg_num
!= 0)
4953 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4955 for (j
= 1; j
< i
.operands
; j
++)
4957 i
.op
[j
- 1] = i
.op
[j
];
4958 i
.types
[j
- 1] = i
.types
[j
];
4960 /* We need to adjust fields in i.tm since they are used by
4961 build_modrm_byte. */
4962 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4969 else if (i
.tm
.opcode_modifier
.regkludge
)
4971 /* The imul $imm, %reg instruction is converted into
4972 imul $imm, %reg, %reg, and the clr %reg instruction
4973 is converted into xor %reg, %reg. */
4975 unsigned int first_reg_op
;
4977 if (operand_type_check (i
.types
[0], reg
))
4981 /* Pretend we saw the extra register operand. */
4982 gas_assert (i
.reg_operands
== 1
4983 && i
.op
[first_reg_op
+ 1].regs
== 0);
4984 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4985 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4990 if (i
.tm
.opcode_modifier
.shortform
)
4992 if (i
.types
[0].bitfield
.sreg2
4993 || i
.types
[0].bitfield
.sreg3
)
4995 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4996 && i
.op
[0].regs
->reg_num
== 1)
4998 as_bad (_("you can't `pop %scs'"), register_prefix
);
5001 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5002 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5007 /* The register or float register operand is in operand
5011 if (i
.types
[0].bitfield
.floatreg
5012 || operand_type_check (i
.types
[0], reg
))
5016 /* Register goes in low 3 bits of opcode. */
5017 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5018 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5020 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5022 /* Warn about some common errors, but press on regardless.
5023 The first case can be generated by gcc (<= 2.8.1). */
5024 if (i
.operands
== 2)
5026 /* Reversed arguments on faddp, fsubp, etc. */
5027 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5028 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5029 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5033 /* Extraneous `l' suffix on fp insn. */
5034 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5035 register_prefix
, i
.op
[0].regs
->reg_name
);
5040 else if (i
.tm
.opcode_modifier
.modrm
)
5042 /* The opcode is completed (modulo i.tm.extension_opcode which
5043 must be put into the modrm byte). Now, we make the modrm and
5044 index base bytes based on all the info we've collected. */
5046 default_seg
= build_modrm_byte ();
5048 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5052 else if (i
.tm
.opcode_modifier
.isstring
)
5054 /* For the string instructions that allow a segment override
5055 on one of their operands, the default segment is ds. */
5059 if (i
.tm
.base_opcode
== 0x8d /* lea */
5062 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5064 /* If a segment was explicitly specified, and the specified segment
5065 is not the default, use an opcode prefix to select it. If we
5066 never figured out what the default segment is, then default_seg
5067 will be zero at this point, and the specified segment prefix will
5069 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5071 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5077 static const seg_entry
*
5078 build_modrm_byte (void)
5080 const seg_entry
*default_seg
= 0;
5081 unsigned int source
, dest
;
5084 /* The first operand of instructions with VEX prefix and 3 sources
5085 must be VEX_Imm4. */
5086 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5089 unsigned int nds
, reg_slot
;
5092 if (i
.tm
.opcode_modifier
.veximmext
5093 && i
.tm
.opcode_modifier
.immext
)
5095 dest
= i
.operands
- 2;
5096 gas_assert (dest
== 3);
5099 dest
= i
.operands
- 1;
5102 /* There are 2 kinds of instructions:
5103 1. 5 operands: 4 register operands or 3 register operands
5104 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5105 VexW0 or VexW1. The destination must be either XMM or YMM
5107 2. 4 operands: 4 register operands or 3 register operands
5108 plus 1 memory operand, VexXDS, and VexImmExt */
5109 gas_assert ((i
.reg_operands
== 4
5110 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5111 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5112 && (i
.tm
.opcode_modifier
.veximmext
5113 || (i
.imm_operands
== 1
5114 && i
.types
[0].bitfield
.vec_imm4
5115 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5116 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5117 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5118 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5120 if (i
.imm_operands
== 0)
5122 /* When there is no immediate operand, generate an 8bit
5123 immediate operand to encode the first operand. */
5124 exp
= &im_expressions
[i
.imm_operands
++];
5125 i
.op
[i
.operands
].imms
= exp
;
5126 i
.types
[i
.operands
] = imm8
;
5128 /* If VexW1 is set, the first operand is the source and
5129 the second operand is encoded in the immediate operand. */
5130 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5141 /* FMA swaps REG and NDS. */
5142 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5150 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5152 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5154 exp
->X_op
= O_constant
;
5156 = ((i
.op
[reg_slot
].regs
->reg_num
5157 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5162 unsigned int imm_slot
;
5164 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5166 /* If VexW0 is set, the third operand is the source and
5167 the second operand is encoded in the immediate
5174 /* VexW1 is set, the second operand is the source and
5175 the third operand is encoded in the immediate
5181 if (i
.tm
.opcode_modifier
.immext
)
5183 /* When ImmExt is set, the immdiate byte is the last
5185 imm_slot
= i
.operands
- 1;
5193 /* Turn on Imm8 so that output_imm will generate it. */
5194 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5197 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5199 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5201 i
.op
[imm_slot
].imms
->X_add_number
5202 |= ((i
.op
[reg_slot
].regs
->reg_num
5203 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5207 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5208 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5210 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5215 /* i.reg_operands MUST be the number of real register operands;
5216 implicit registers do not count. If there are 3 register
5217 operands, it must be a instruction with VexNDS. For a
5218 instruction with VexNDD, the destination register is encoded
5219 in VEX prefix. If there are 4 register operands, it must be
5220 a instruction with VEX prefix and 3 sources. */
5221 if (i
.mem_operands
== 0
5222 && ((i
.reg_operands
== 2
5223 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5224 || (i
.reg_operands
== 3
5225 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5226 || (i
.reg_operands
== 4 && vex_3_sources
)))
5234 /* When there are 3 operands, one of them may be immediate,
5235 which may be the first or the last operand. Otherwise,
5236 the first operand must be shift count register (cl) or it
5237 is an instruction with VexNDS. */
5238 gas_assert (i
.imm_operands
== 1
5239 || (i
.imm_operands
== 0
5240 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5241 || i
.types
[0].bitfield
.shiftcount
)));
5242 if (operand_type_check (i
.types
[0], imm
)
5243 || i
.types
[0].bitfield
.shiftcount
)
5249 /* When there are 4 operands, the first two must be 8bit
5250 immediate operands. The source operand will be the 3rd
5253 For instructions with VexNDS, if the first operand
5254 an imm8, the source operand is the 2nd one. If the last
5255 operand is imm8, the source operand is the first one. */
5256 gas_assert ((i
.imm_operands
== 2
5257 && i
.types
[0].bitfield
.imm8
5258 && i
.types
[1].bitfield
.imm8
)
5259 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5260 && i
.imm_operands
== 1
5261 && (i
.types
[0].bitfield
.imm8
5262 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5263 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5265 if (i
.types
[0].bitfield
.imm8
)
5283 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5285 /* For instructions with VexNDS, the register-only
5286 source operand must be XMM or YMM register. It is
5287 encoded in VEX prefix. We need to clear RegMem bit
5288 before calling operand_type_equal. */
5289 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5290 op
.bitfield
.regmem
= 0;
5291 if ((dest
+ 1) >= i
.operands
5292 || (!operand_type_equal (&op
, ®xmm
)
5293 && !operand_type_equal (&op
, ®ymm
)))
5295 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5301 /* One of the register operands will be encoded in the i.tm.reg
5302 field, the other in the combined i.tm.mode and i.tm.regmem
5303 fields. If no form of this instruction supports a memory
5304 destination operand, then we assume the source operand may
5305 sometimes be a memory operand and so we need to store the
5306 destination in the i.rm.reg field. */
5307 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5308 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5310 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5311 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5312 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5314 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5319 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5320 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5321 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5323 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5326 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5328 if (!i
.types
[0].bitfield
.control
5329 && !i
.types
[1].bitfield
.control
)
5331 i
.rex
&= ~(REX_R
| REX_B
);
5332 add_prefix (LOCK_PREFIX_OPCODE
);
5336 { /* If it's not 2 reg operands... */
5341 unsigned int fake_zero_displacement
= 0;
5344 for (op
= 0; op
< i
.operands
; op
++)
5345 if (operand_type_check (i
.types
[op
], anymem
))
5347 gas_assert (op
< i
.operands
);
5351 if (i
.base_reg
== 0)
5354 if (!i
.disp_operands
)
5355 fake_zero_displacement
= 1;
5356 if (i
.index_reg
== 0)
5358 /* Operand is just <disp> */
5359 if (flag_code
== CODE_64BIT
)
5361 /* 64bit mode overwrites the 32bit absolute
5362 addressing by RIP relative addressing and
5363 absolute addressing is encoded by one of the
5364 redundant SIB forms. */
5365 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5366 i
.sib
.base
= NO_BASE_REGISTER
;
5367 i
.sib
.index
= NO_INDEX_REGISTER
;
5368 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5369 ? disp32s
: disp32
);
5371 else if ((flag_code
== CODE_16BIT
)
5372 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5374 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5375 i
.types
[op
] = disp16
;
5379 i
.rm
.regmem
= NO_BASE_REGISTER
;
5380 i
.types
[op
] = disp32
;
5383 else /* !i.base_reg && i.index_reg */
5385 if (i
.index_reg
->reg_num
== RegEiz
5386 || i
.index_reg
->reg_num
== RegRiz
)
5387 i
.sib
.index
= NO_INDEX_REGISTER
;
5389 i
.sib
.index
= i
.index_reg
->reg_num
;
5390 i
.sib
.base
= NO_BASE_REGISTER
;
5391 i
.sib
.scale
= i
.log2_scale_factor
;
5392 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5393 i
.types
[op
].bitfield
.disp8
= 0;
5394 i
.types
[op
].bitfield
.disp16
= 0;
5395 i
.types
[op
].bitfield
.disp64
= 0;
5396 if (flag_code
!= CODE_64BIT
)
5398 /* Must be 32 bit */
5399 i
.types
[op
].bitfield
.disp32
= 1;
5400 i
.types
[op
].bitfield
.disp32s
= 0;
5404 i
.types
[op
].bitfield
.disp32
= 0;
5405 i
.types
[op
].bitfield
.disp32s
= 1;
5407 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5411 /* RIP addressing for 64bit mode. */
5412 else if (i
.base_reg
->reg_num
== RegRip
||
5413 i
.base_reg
->reg_num
== RegEip
)
5415 i
.rm
.regmem
= NO_BASE_REGISTER
;
5416 i
.types
[op
].bitfield
.disp8
= 0;
5417 i
.types
[op
].bitfield
.disp16
= 0;
5418 i
.types
[op
].bitfield
.disp32
= 0;
5419 i
.types
[op
].bitfield
.disp32s
= 1;
5420 i
.types
[op
].bitfield
.disp64
= 0;
5421 i
.flags
[op
] |= Operand_PCrel
;
5422 if (! i
.disp_operands
)
5423 fake_zero_displacement
= 1;
5425 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5427 switch (i
.base_reg
->reg_num
)
5430 if (i
.index_reg
== 0)
5432 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5433 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5437 if (i
.index_reg
== 0)
5440 if (operand_type_check (i
.types
[op
], disp
) == 0)
5442 /* fake (%bp) into 0(%bp) */
5443 i
.types
[op
].bitfield
.disp8
= 1;
5444 fake_zero_displacement
= 1;
5447 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5448 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5450 default: /* (%si) -> 4 or (%di) -> 5 */
5451 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5453 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5455 else /* i.base_reg and 32/64 bit mode */
5457 if (flag_code
== CODE_64BIT
5458 && operand_type_check (i
.types
[op
], disp
))
5460 i386_operand_type temp
;
5461 operand_type_set (&temp
, 0);
5462 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5464 if (i
.prefix
[ADDR_PREFIX
] == 0)
5465 i
.types
[op
].bitfield
.disp32s
= 1;
5467 i
.types
[op
].bitfield
.disp32
= 1;
5470 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5471 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5473 i
.sib
.base
= i
.base_reg
->reg_num
;
5474 /* x86-64 ignores REX prefix bit here to avoid decoder
5476 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5479 if (i
.disp_operands
== 0)
5481 fake_zero_displacement
= 1;
5482 i
.types
[op
].bitfield
.disp8
= 1;
5485 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5489 i
.sib
.scale
= i
.log2_scale_factor
;
5490 if (i
.index_reg
== 0)
5492 /* <disp>(%esp) becomes two byte modrm with no index
5493 register. We've already stored the code for esp
5494 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5495 Any base register besides %esp will not use the
5496 extra modrm byte. */
5497 i
.sib
.index
= NO_INDEX_REGISTER
;
5501 if (i
.index_reg
->reg_num
== RegEiz
5502 || i
.index_reg
->reg_num
== RegRiz
)
5503 i
.sib
.index
= NO_INDEX_REGISTER
;
5505 i
.sib
.index
= i
.index_reg
->reg_num
;
5506 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5507 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5512 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5513 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5516 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5519 if (fake_zero_displacement
)
5521 /* Fakes a zero displacement assuming that i.types[op]
5522 holds the correct displacement size. */
5525 gas_assert (i
.op
[op
].disps
== 0);
5526 exp
= &disp_expressions
[i
.disp_operands
++];
5527 i
.op
[op
].disps
= exp
;
5528 exp
->X_op
= O_constant
;
5529 exp
->X_add_number
= 0;
5530 exp
->X_add_symbol
= (symbolS
*) 0;
5531 exp
->X_op_symbol
= (symbolS
*) 0;
5539 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5541 if (operand_type_check (i
.types
[0], imm
))
5542 i
.vex
.register_specifier
= NULL
;
5545 /* VEX.vvvv encodes one of the sources when the first
5546 operand is not an immediate. */
5547 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5548 i
.vex
.register_specifier
= i
.op
[0].regs
;
5550 i
.vex
.register_specifier
= i
.op
[1].regs
;
5553 /* Destination is a XMM register encoded in the ModRM.reg
5555 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5556 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5559 /* ModRM.rm and VEX.B encodes the other source. */
5560 if (!i
.mem_operands
)
5564 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5565 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5567 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5569 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5573 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5575 i
.vex
.register_specifier
= i
.op
[2].regs
;
5576 if (!i
.mem_operands
)
5579 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5580 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5584 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5585 (if any) based on i.tm.extension_opcode. Again, we must be
5586 careful to make sure that segment/control/debug/test/MMX
5587 registers are coded into the i.rm.reg field. */
5588 else if (i
.reg_operands
)
5591 unsigned int vex_reg
= ~0;
5593 for (op
= 0; op
< i
.operands
; op
++)
5594 if (i
.types
[op
].bitfield
.reg8
5595 || i
.types
[op
].bitfield
.reg16
5596 || i
.types
[op
].bitfield
.reg32
5597 || i
.types
[op
].bitfield
.reg64
5598 || i
.types
[op
].bitfield
.regmmx
5599 || i
.types
[op
].bitfield
.regxmm
5600 || i
.types
[op
].bitfield
.regymm
5601 || i
.types
[op
].bitfield
.sreg2
5602 || i
.types
[op
].bitfield
.sreg3
5603 || i
.types
[op
].bitfield
.control
5604 || i
.types
[op
].bitfield
.debug
5605 || i
.types
[op
].bitfield
.test
)
5610 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5612 /* For instructions with VexNDS, the register-only
5613 source operand is encoded in VEX prefix. */
5614 gas_assert (mem
!= (unsigned int) ~0);
5619 gas_assert (op
< i
.operands
);
5624 gas_assert (vex_reg
< i
.operands
);
5627 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5629 /* For instructions with VexNDD, there should be
5630 no memory operand and the register destination
5631 is encoded in VEX prefix. */
5632 gas_assert (i
.mem_operands
== 0
5633 && (op
+ 2) == i
.operands
);
5637 gas_assert (op
< i
.operands
);
5639 if (vex_reg
!= (unsigned int) ~0)
5641 gas_assert (i
.reg_operands
== 2);
5643 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5645 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5649 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5652 /* Don't set OP operand twice. */
5655 /* If there is an extension opcode to put here, the
5656 register number must be put into the regmem field. */
5657 if (i
.tm
.extension_opcode
!= None
)
5659 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5660 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5665 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5666 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5671 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5672 must set it to 3 to indicate this is a register operand
5673 in the regmem field. */
5674 if (!i
.mem_operands
)
5678 /* Fill in i.rm.reg field with extension opcode (if any). */
5679 if (i
.tm
.extension_opcode
!= None
)
5680 i
.rm
.reg
= i
.tm
.extension_opcode
;
5686 output_branch (void)
5691 relax_substateT subtype
;
5696 if (flag_code
== CODE_16BIT
)
5700 if (i
.prefix
[DATA_PREFIX
] != 0)
5706 /* Pentium4 branch hints. */
5707 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5708 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5713 if (i
.prefix
[REX_PREFIX
] != 0)
5719 if (i
.prefixes
!= 0 && !intel_syntax
)
5720 as_warn (_("skipping prefixes on this instruction"));
5722 /* It's always a symbol; End frag & setup for relax.
5723 Make sure there is enough room in this frag for the largest
5724 instruction we may generate in md_convert_frag. This is 2
5725 bytes for the opcode and room for the prefix and largest
5727 frag_grow (prefix
+ 2 + 4);
5728 /* Prefix and 1 opcode byte go in fr_fix. */
5729 p
= frag_more (prefix
+ 1);
5730 if (i
.prefix
[DATA_PREFIX
] != 0)
5731 *p
++ = DATA_PREFIX_OPCODE
;
5732 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5733 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5734 *p
++ = i
.prefix
[SEG_PREFIX
];
5735 if (i
.prefix
[REX_PREFIX
] != 0)
5736 *p
++ = i
.prefix
[REX_PREFIX
];
5737 *p
= i
.tm
.base_opcode
;
5739 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5740 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5741 else if (cpu_arch_flags
.bitfield
.cpui386
)
5742 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5744 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5747 sym
= i
.op
[0].disps
->X_add_symbol
;
5748 off
= i
.op
[0].disps
->X_add_number
;
5750 if (i
.op
[0].disps
->X_op
!= O_constant
5751 && i
.op
[0].disps
->X_op
!= O_symbol
)
5753 /* Handle complex expressions. */
5754 sym
= make_expr_symbol (i
.op
[0].disps
);
5758 /* 1 possible extra opcode + 4 byte displacement go in var part.
5759 Pass reloc in fr_var. */
5760 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5770 if (i
.tm
.opcode_modifier
.jumpbyte
)
5772 /* This is a loop or jecxz type instruction. */
5774 if (i
.prefix
[ADDR_PREFIX
] != 0)
5776 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5779 /* Pentium4 branch hints. */
5780 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5781 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5783 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5792 if (flag_code
== CODE_16BIT
)
5795 if (i
.prefix
[DATA_PREFIX
] != 0)
5797 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5807 if (i
.prefix
[REX_PREFIX
] != 0)
5809 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5813 if (i
.prefixes
!= 0 && !intel_syntax
)
5814 as_warn (_("skipping prefixes on this instruction"));
5816 p
= frag_more (1 + size
);
5817 *p
++ = i
.tm
.base_opcode
;
5819 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5820 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5822 /* All jumps handled here are signed, but don't use a signed limit
5823 check for 32 and 16 bit jumps as we want to allow wrap around at
5824 4G and 64k respectively. */
5826 fixP
->fx_signed
= 1;
5830 output_interseg_jump (void)
5838 if (flag_code
== CODE_16BIT
)
5842 if (i
.prefix
[DATA_PREFIX
] != 0)
5848 if (i
.prefix
[REX_PREFIX
] != 0)
5858 if (i
.prefixes
!= 0 && !intel_syntax
)
5859 as_warn (_("skipping prefixes on this instruction"));
5861 /* 1 opcode; 2 segment; offset */
5862 p
= frag_more (prefix
+ 1 + 2 + size
);
5864 if (i
.prefix
[DATA_PREFIX
] != 0)
5865 *p
++ = DATA_PREFIX_OPCODE
;
5867 if (i
.prefix
[REX_PREFIX
] != 0)
5868 *p
++ = i
.prefix
[REX_PREFIX
];
5870 *p
++ = i
.tm
.base_opcode
;
5871 if (i
.op
[1].imms
->X_op
== O_constant
)
5873 offsetT n
= i
.op
[1].imms
->X_add_number
;
5876 && !fits_in_unsigned_word (n
)
5877 && !fits_in_signed_word (n
))
5879 as_bad (_("16-bit jump out of range"));
5882 md_number_to_chars (p
, n
, size
);
5885 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5886 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5887 if (i
.op
[0].imms
->X_op
!= O_constant
)
5888 as_bad (_("can't handle non absolute segment in `%s'"),
5890 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5896 fragS
*insn_start_frag
;
5897 offsetT insn_start_off
;
5899 /* Tie dwarf2 debug info to the address at the start of the insn.
5900 We can't do this after the insn has been output as the current
5901 frag may have been closed off. eg. by frag_var. */
5902 dwarf2_emit_insn (0);
5904 insn_start_frag
= frag_now
;
5905 insn_start_off
= frag_now_fix ();
5908 if (i
.tm
.opcode_modifier
.jump
)
5910 else if (i
.tm
.opcode_modifier
.jumpbyte
5911 || i
.tm
.opcode_modifier
.jumpdword
)
5913 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5914 output_interseg_jump ();
5917 /* Output normal instructions here. */
5921 unsigned int prefix
;
5923 /* Since the VEX prefix contains the implicit prefix, we don't
5924 need the explicit prefix. */
5925 if (!i
.tm
.opcode_modifier
.vex
)
5927 switch (i
.tm
.opcode_length
)
5930 if (i
.tm
.base_opcode
& 0xff000000)
5932 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5937 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5939 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5940 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5943 if (prefix
!= REPE_PREFIX_OPCODE
5944 || (i
.prefix
[REP_PREFIX
]
5945 != REPE_PREFIX_OPCODE
))
5946 add_prefix (prefix
);
5949 add_prefix (prefix
);
5958 /* The prefix bytes. */
5959 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5961 FRAG_APPEND_1_CHAR (*q
);
5964 if (i
.tm
.opcode_modifier
.vex
)
5966 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5971 /* REX byte is encoded in VEX prefix. */
5975 FRAG_APPEND_1_CHAR (*q
);
5978 /* There should be no other prefixes for instructions
5983 /* Now the VEX prefix. */
5984 p
= frag_more (i
.vex
.length
);
5985 for (j
= 0; j
< i
.vex
.length
; j
++)
5986 p
[j
] = i
.vex
.bytes
[j
];
5989 /* Now the opcode; be careful about word order here! */
5990 if (i
.tm
.opcode_length
== 1)
5992 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5996 switch (i
.tm
.opcode_length
)
6000 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6010 /* Put out high byte first: can't use md_number_to_chars! */
6011 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6012 *p
= i
.tm
.base_opcode
& 0xff;
6015 /* Now the modrm byte and sib byte (if present). */
6016 if (i
.tm
.opcode_modifier
.modrm
)
6018 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6021 /* If i.rm.regmem == ESP (4)
6022 && i.rm.mode != (Register mode)
6024 ==> need second modrm byte. */
6025 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6027 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6028 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6030 | i
.sib
.scale
<< 6));
6033 if (i
.disp_operands
)
6034 output_disp (insn_start_frag
, insn_start_off
);
6037 output_imm (insn_start_frag
, insn_start_off
);
6043 pi ("" /*line*/, &i
);
6045 #endif /* DEBUG386 */
6048 /* Return the size of the displacement operand N. */
6051 disp_size (unsigned int n
)
6054 if (i
.types
[n
].bitfield
.disp64
)
6056 else if (i
.types
[n
].bitfield
.disp8
)
6058 else if (i
.types
[n
].bitfield
.disp16
)
6063 /* Return the size of the immediate operand N. */
6066 imm_size (unsigned int n
)
6069 if (i
.types
[n
].bitfield
.imm64
)
6071 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6073 else if (i
.types
[n
].bitfield
.imm16
)
6079 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6084 for (n
= 0; n
< i
.operands
; n
++)
6086 if (operand_type_check (i
.types
[n
], disp
))
6088 if (i
.op
[n
].disps
->X_op
== O_constant
)
6090 int size
= disp_size (n
);
6093 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6095 p
= frag_more (size
);
6096 md_number_to_chars (p
, val
, size
);
6100 enum bfd_reloc_code_real reloc_type
;
6101 int size
= disp_size (n
);
6102 int sign
= i
.types
[n
].bitfield
.disp32s
;
6103 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6105 /* We can't have 8 bit displacement here. */
6106 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6108 /* The PC relative address is computed relative
6109 to the instruction boundary, so in case immediate
6110 fields follows, we need to adjust the value. */
6111 if (pcrel
&& i
.imm_operands
)
6116 for (n1
= 0; n1
< i
.operands
; n1
++)
6117 if (operand_type_check (i
.types
[n1
], imm
))
6119 /* Only one immediate is allowed for PC
6120 relative address. */
6121 gas_assert (sz
== 0);
6123 i
.op
[n
].disps
->X_add_number
-= sz
;
6125 /* We should find the immediate. */
6126 gas_assert (sz
!= 0);
6129 p
= frag_more (size
);
6130 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6132 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6133 && (((reloc_type
== BFD_RELOC_32
6134 || reloc_type
== BFD_RELOC_X86_64_32S
6135 || (reloc_type
== BFD_RELOC_64
6137 && (i
.op
[n
].disps
->X_op
== O_symbol
6138 || (i
.op
[n
].disps
->X_op
== O_add
6139 && ((symbol_get_value_expression
6140 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6142 || reloc_type
== BFD_RELOC_32_PCREL
))
6146 if (insn_start_frag
== frag_now
)
6147 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6152 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6153 for (fr
= insn_start_frag
->fr_next
;
6154 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6156 add
+= p
- frag_now
->fr_literal
;
6161 reloc_type
= BFD_RELOC_386_GOTPC
;
6162 i
.op
[n
].imms
->X_add_number
+= add
;
6164 else if (reloc_type
== BFD_RELOC_64
)
6165 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6167 /* Don't do the adjustment for x86-64, as there
6168 the pcrel addressing is relative to the _next_
6169 insn, and that is taken care of in other code. */
6170 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6172 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6173 i
.op
[n
].disps
, pcrel
, reloc_type
);
6180 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6185 for (n
= 0; n
< i
.operands
; n
++)
6187 if (operand_type_check (i
.types
[n
], imm
))
6189 if (i
.op
[n
].imms
->X_op
== O_constant
)
6191 int size
= imm_size (n
);
6194 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6196 p
= frag_more (size
);
6197 md_number_to_chars (p
, val
, size
);
6201 /* Not absolute_section.
6202 Need a 32-bit fixup (don't support 8bit
6203 non-absolute imms). Try to support other
6205 enum bfd_reloc_code_real reloc_type
;
6206 int size
= imm_size (n
);
6209 if (i
.types
[n
].bitfield
.imm32s
6210 && (i
.suffix
== QWORD_MNEM_SUFFIX
6211 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6216 p
= frag_more (size
);
6217 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6219 /* This is tough to explain. We end up with this one if we
6220 * have operands that look like
6221 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6222 * obtain the absolute address of the GOT, and it is strongly
6223 * preferable from a performance point of view to avoid using
6224 * a runtime relocation for this. The actual sequence of
6225 * instructions often look something like:
6230 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6232 * The call and pop essentially return the absolute address
6233 * of the label .L66 and store it in %ebx. The linker itself
6234 * will ultimately change the first operand of the addl so
6235 * that %ebx points to the GOT, but to keep things simple, the
6236 * .o file must have this operand set so that it generates not
6237 * the absolute address of .L66, but the absolute address of
6238 * itself. This allows the linker itself simply treat a GOTPC
6239 * relocation as asking for a pcrel offset to the GOT to be
6240 * added in, and the addend of the relocation is stored in the
6241 * operand field for the instruction itself.
6243 * Our job here is to fix the operand so that it would add
6244 * the correct offset so that %ebx would point to itself. The
6245 * thing that is tricky is that .-.L66 will point to the
6246 * beginning of the instruction, so we need to further modify
6247 * the operand so that it will point to itself. There are
6248 * other cases where you have something like:
6250 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6252 * and here no correction would be required. Internally in
6253 * the assembler we treat operands of this form as not being
6254 * pcrel since the '.' is explicitly mentioned, and I wonder
6255 * whether it would simplify matters to do it this way. Who
6256 * knows. In earlier versions of the PIC patches, the
6257 * pcrel_adjust field was used to store the correction, but
6258 * since the expression is not pcrel, I felt it would be
6259 * confusing to do it this way. */
6261 if ((reloc_type
== BFD_RELOC_32
6262 || reloc_type
== BFD_RELOC_X86_64_32S
6263 || reloc_type
== BFD_RELOC_64
)
6265 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6266 && (i
.op
[n
].imms
->X_op
== O_symbol
6267 || (i
.op
[n
].imms
->X_op
== O_add
6268 && ((symbol_get_value_expression
6269 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6274 if (insn_start_frag
== frag_now
)
6275 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6280 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6281 for (fr
= insn_start_frag
->fr_next
;
6282 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6284 add
+= p
- frag_now
->fr_literal
;
6288 reloc_type
= BFD_RELOC_386_GOTPC
;
6290 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6292 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6293 i
.op
[n
].imms
->X_add_number
+= add
;
6295 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6296 i
.op
[n
].imms
, 0, reloc_type
);
6302 /* x86_cons_fix_new is called via the expression parsing code when a
6303 reloc is needed. We use this hook to get the correct .got reloc. */
6304 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6305 static int cons_sign
= -1;
6308 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6311 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6313 got_reloc
= NO_RELOC
;
6316 if (exp
->X_op
== O_secrel
)
6318 exp
->X_op
= O_symbol
;
6319 r
= BFD_RELOC_32_SECREL
;
6323 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6326 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6327 # define lex_got(reloc, adjust, types) NULL
6329 /* Parse operands of the form
6330 <symbol>@GOTOFF+<nnn>
6331 and similar .plt or .got references.
6333 If we find one, set up the correct relocation in RELOC and copy the
6334 input string, minus the `@GOTOFF' into a malloc'd buffer for
6335 parsing by the calling routine. Return this buffer, and if ADJUST
6336 is non-null set it to the length of the string we removed from the
6337 input line. Otherwise return NULL. */
6339 lex_got (enum bfd_reloc_code_real
*rel
,
6341 i386_operand_type
*types
)
6343 /* Some of the relocations depend on the size of what field is to
6344 be relocated. But in our callers i386_immediate and i386_displacement
6345 we don't yet know the operand size (this will be set by insn
6346 matching). Hence we record the word32 relocation here,
6347 and adjust the reloc according to the real size in reloc(). */
6348 static const struct {
6351 const enum bfd_reloc_code_real rel
[2];
6352 const i386_operand_type types64
;
6354 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6355 BFD_RELOC_X86_64_PLTOFF64
},
6356 OPERAND_TYPE_IMM64
},
6357 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6358 BFD_RELOC_X86_64_PLT32
},
6359 OPERAND_TYPE_IMM32_32S_DISP32
},
6360 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6361 BFD_RELOC_X86_64_GOTPLT64
},
6362 OPERAND_TYPE_IMM64_DISP64
},
6363 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6364 BFD_RELOC_X86_64_GOTOFF64
},
6365 OPERAND_TYPE_IMM64_DISP64
},
6366 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6367 BFD_RELOC_X86_64_GOTPCREL
},
6368 OPERAND_TYPE_IMM32_32S_DISP32
},
6369 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6370 BFD_RELOC_X86_64_TLSGD
},
6371 OPERAND_TYPE_IMM32_32S_DISP32
},
6372 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6373 _dummy_first_bfd_reloc_code_real
},
6374 OPERAND_TYPE_NONE
},
6375 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6376 BFD_RELOC_X86_64_TLSLD
},
6377 OPERAND_TYPE_IMM32_32S_DISP32
},
6378 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6379 BFD_RELOC_X86_64_GOTTPOFF
},
6380 OPERAND_TYPE_IMM32_32S_DISP32
},
6381 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6382 BFD_RELOC_X86_64_TPOFF32
},
6383 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6384 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6385 _dummy_first_bfd_reloc_code_real
},
6386 OPERAND_TYPE_NONE
},
6387 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6388 BFD_RELOC_X86_64_DTPOFF32
},
6389 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6390 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6391 _dummy_first_bfd_reloc_code_real
},
6392 OPERAND_TYPE_NONE
},
6393 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6394 _dummy_first_bfd_reloc_code_real
},
6395 OPERAND_TYPE_NONE
},
6396 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6397 BFD_RELOC_X86_64_GOT32
},
6398 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6399 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6400 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6401 OPERAND_TYPE_IMM32_32S_DISP32
},
6402 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6403 BFD_RELOC_X86_64_TLSDESC_CALL
},
6404 OPERAND_TYPE_IMM32_32S_DISP32
},
6412 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6413 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6416 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6418 int len
= gotrel
[j
].len
;
6419 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6421 if (gotrel
[j
].rel
[object_64bit
] != 0)
6424 char *tmpbuf
, *past_reloc
;
6426 *rel
= gotrel
[j
].rel
[object_64bit
];
6432 if (flag_code
!= CODE_64BIT
)
6434 types
->bitfield
.imm32
= 1;
6435 types
->bitfield
.disp32
= 1;
6438 *types
= gotrel
[j
].types64
;
6441 if (GOT_symbol
== NULL
)
6442 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6444 /* The length of the first part of our input line. */
6445 first
= cp
- input_line_pointer
;
6447 /* The second part goes from after the reloc token until
6448 (and including) an end_of_line char or comma. */
6449 past_reloc
= cp
+ 1 + len
;
6451 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6453 second
= cp
+ 1 - past_reloc
;
6455 /* Allocate and copy string. The trailing NUL shouldn't
6456 be necessary, but be safe. */
6457 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6458 memcpy (tmpbuf
, input_line_pointer
, first
);
6459 if (second
!= 0 && *past_reloc
!= ' ')
6460 /* Replace the relocation token with ' ', so that
6461 errors like foo@GOTOFF1 will be detected. */
6462 tmpbuf
[first
++] = ' ';
6463 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6464 tmpbuf
[first
+ second
] = '\0';
6468 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6469 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6474 /* Might be a symbol version string. Don't as_bad here. */
6479 x86_cons (expressionS
*exp
, int size
)
6481 intel_syntax
= -intel_syntax
;
6484 if (size
== 4 || (object_64bit
&& size
== 8))
6486 /* Handle @GOTOFF and the like in an expression. */
6488 char *gotfree_input_line
;
6491 save
= input_line_pointer
;
6492 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6493 if (gotfree_input_line
)
6494 input_line_pointer
= gotfree_input_line
;
6498 if (gotfree_input_line
)
6500 /* expression () has merrily parsed up to the end of line,
6501 or a comma - in the wrong buffer. Transfer how far
6502 input_line_pointer has moved to the right buffer. */
6503 input_line_pointer
= (save
6504 + (input_line_pointer
- gotfree_input_line
)
6506 free (gotfree_input_line
);
6507 if (exp
->X_op
== O_constant
6508 || exp
->X_op
== O_absent
6509 || exp
->X_op
== O_illegal
6510 || exp
->X_op
== O_register
6511 || exp
->X_op
== O_big
)
6513 char c
= *input_line_pointer
;
6514 *input_line_pointer
= 0;
6515 as_bad (_("missing or invalid expression `%s'"), save
);
6516 *input_line_pointer
= c
;
6523 intel_syntax
= -intel_syntax
;
6526 i386_intel_simplify (exp
);
6531 signed_cons (int size
)
6533 if (flag_code
== CODE_64BIT
)
6541 pe_directive_secrel (dummy
)
6542 int dummy ATTRIBUTE_UNUSED
;
6549 if (exp
.X_op
== O_symbol
)
6550 exp
.X_op
= O_secrel
;
6552 emit_expr (&exp
, 4);
6554 while (*input_line_pointer
++ == ',');
6556 input_line_pointer
--;
6557 demand_empty_rest_of_line ();
6562 i386_immediate (char *imm_start
)
6564 char *save_input_line_pointer
;
6565 char *gotfree_input_line
;
6568 i386_operand_type types
;
6570 operand_type_set (&types
, ~0);
6572 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6574 as_bad (_("at most %d immediate operands are allowed"),
6575 MAX_IMMEDIATE_OPERANDS
);
6579 exp
= &im_expressions
[i
.imm_operands
++];
6580 i
.op
[this_operand
].imms
= exp
;
6582 if (is_space_char (*imm_start
))
6585 save_input_line_pointer
= input_line_pointer
;
6586 input_line_pointer
= imm_start
;
6588 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6589 if (gotfree_input_line
)
6590 input_line_pointer
= gotfree_input_line
;
6592 exp_seg
= expression (exp
);
6595 if (*input_line_pointer
)
6596 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6598 input_line_pointer
= save_input_line_pointer
;
6599 if (gotfree_input_line
)
6601 free (gotfree_input_line
);
6603 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6604 exp
->X_op
= O_illegal
;
6607 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6611 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6612 i386_operand_type types
, const char *imm_start
)
6614 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6617 as_bad (_("missing or invalid immediate expression `%s'"),
6621 else if (exp
->X_op
== O_constant
)
6623 /* Size it properly later. */
6624 i
.types
[this_operand
].bitfield
.imm64
= 1;
6625 /* If BFD64, sign extend val. */
6626 if (!use_rela_relocations
6627 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6629 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6631 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6632 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6633 && exp_seg
!= absolute_section
6634 && exp_seg
!= text_section
6635 && exp_seg
!= data_section
6636 && exp_seg
!= bss_section
6637 && exp_seg
!= undefined_section
6638 && !bfd_is_com_section (exp_seg
))
6640 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6644 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6647 as_bad (_("illegal immediate register operand %s"), imm_start
);
6652 /* This is an address. The size of the address will be
6653 determined later, depending on destination register,
6654 suffix, or the default for the section. */
6655 i
.types
[this_operand
].bitfield
.imm8
= 1;
6656 i
.types
[this_operand
].bitfield
.imm16
= 1;
6657 i
.types
[this_operand
].bitfield
.imm32
= 1;
6658 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6659 i
.types
[this_operand
].bitfield
.imm64
= 1;
6660 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6668 i386_scale (char *scale
)
6671 char *save
= input_line_pointer
;
6673 input_line_pointer
= scale
;
6674 val
= get_absolute_expression ();
6679 i
.log2_scale_factor
= 0;
6682 i
.log2_scale_factor
= 1;
6685 i
.log2_scale_factor
= 2;
6688 i
.log2_scale_factor
= 3;
6692 char sep
= *input_line_pointer
;
6694 *input_line_pointer
= '\0';
6695 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6697 *input_line_pointer
= sep
;
6698 input_line_pointer
= save
;
6702 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6704 as_warn (_("scale factor of %d without an index register"),
6705 1 << i
.log2_scale_factor
);
6706 i
.log2_scale_factor
= 0;
6708 scale
= input_line_pointer
;
6709 input_line_pointer
= save
;
6714 i386_displacement (char *disp_start
, char *disp_end
)
6718 char *save_input_line_pointer
;
6719 char *gotfree_input_line
;
6721 i386_operand_type bigdisp
, types
= anydisp
;
6724 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6726 as_bad (_("at most %d displacement operands are allowed"),
6727 MAX_MEMORY_OPERANDS
);
6731 operand_type_set (&bigdisp
, 0);
6732 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6733 || (!current_templates
->start
->opcode_modifier
.jump
6734 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6736 bigdisp
.bitfield
.disp32
= 1;
6737 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6738 if (flag_code
== CODE_64BIT
)
6742 bigdisp
.bitfield
.disp32s
= 1;
6743 bigdisp
.bitfield
.disp64
= 1;
6746 else if ((flag_code
== CODE_16BIT
) ^ override
)
6748 bigdisp
.bitfield
.disp32
= 0;
6749 bigdisp
.bitfield
.disp16
= 1;
6754 /* For PC-relative branches, the width of the displacement
6755 is dependent upon data size, not address size. */
6756 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6757 if (flag_code
== CODE_64BIT
)
6759 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6760 bigdisp
.bitfield
.disp16
= 1;
6763 bigdisp
.bitfield
.disp32
= 1;
6764 bigdisp
.bitfield
.disp32s
= 1;
6770 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6772 : LONG_MNEM_SUFFIX
));
6773 bigdisp
.bitfield
.disp32
= 1;
6774 if ((flag_code
== CODE_16BIT
) ^ override
)
6776 bigdisp
.bitfield
.disp32
= 0;
6777 bigdisp
.bitfield
.disp16
= 1;
6781 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6784 exp
= &disp_expressions
[i
.disp_operands
];
6785 i
.op
[this_operand
].disps
= exp
;
6787 save_input_line_pointer
= input_line_pointer
;
6788 input_line_pointer
= disp_start
;
6789 END_STRING_AND_SAVE (disp_end
);
6791 #ifndef GCC_ASM_O_HACK
6792 #define GCC_ASM_O_HACK 0
6795 END_STRING_AND_SAVE (disp_end
+ 1);
6796 if (i
.types
[this_operand
].bitfield
.baseIndex
6797 && displacement_string_end
[-1] == '+')
6799 /* This hack is to avoid a warning when using the "o"
6800 constraint within gcc asm statements.
6803 #define _set_tssldt_desc(n,addr,limit,type) \
6804 __asm__ __volatile__ ( \
6806 "movw %w1,2+%0\n\t" \
6808 "movb %b1,4+%0\n\t" \
6809 "movb %4,5+%0\n\t" \
6810 "movb $0,6+%0\n\t" \
6811 "movb %h1,7+%0\n\t" \
6813 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6815 This works great except that the output assembler ends
6816 up looking a bit weird if it turns out that there is
6817 no offset. You end up producing code that looks like:
6830 So here we provide the missing zero. */
6832 *displacement_string_end
= '0';
6835 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6836 if (gotfree_input_line
)
6837 input_line_pointer
= gotfree_input_line
;
6839 exp_seg
= expression (exp
);
6842 if (*input_line_pointer
)
6843 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6845 RESTORE_END_STRING (disp_end
+ 1);
6847 input_line_pointer
= save_input_line_pointer
;
6848 if (gotfree_input_line
)
6850 free (gotfree_input_line
);
6852 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6853 exp
->X_op
= O_illegal
;
6856 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6858 RESTORE_END_STRING (disp_end
);
6864 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6865 i386_operand_type types
, const char *disp_start
)
6867 i386_operand_type bigdisp
;
6870 /* We do this to make sure that the section symbol is in
6871 the symbol table. We will ultimately change the relocation
6872 to be relative to the beginning of the section. */
6873 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6874 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6875 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6877 if (exp
->X_op
!= O_symbol
)
6880 if (S_IS_LOCAL (exp
->X_add_symbol
)
6881 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6882 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6883 exp
->X_op
= O_subtract
;
6884 exp
->X_op_symbol
= GOT_symbol
;
6885 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6886 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6887 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6888 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6890 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6893 else if (exp
->X_op
== O_absent
6894 || exp
->X_op
== O_illegal
6895 || exp
->X_op
== O_big
)
6898 as_bad (_("missing or invalid displacement expression `%s'"),
6903 else if (flag_code
== CODE_64BIT
6904 && !i
.prefix
[ADDR_PREFIX
]
6905 && exp
->X_op
== O_constant
)
6907 /* Since displacement is signed extended to 64bit, don't allow
6908 disp32 and turn off disp32s if they are out of range. */
6909 i
.types
[this_operand
].bitfield
.disp32
= 0;
6910 if (!fits_in_signed_long (exp
->X_add_number
))
6912 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6913 if (i
.types
[this_operand
].bitfield
.baseindex
)
6915 as_bad (_("0x%lx out range of signed 32bit displacement"),
6916 (long) exp
->X_add_number
);
6922 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6923 else if (exp
->X_op
!= O_constant
6924 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6925 && exp_seg
!= absolute_section
6926 && exp_seg
!= text_section
6927 && exp_seg
!= data_section
6928 && exp_seg
!= bss_section
6929 && exp_seg
!= undefined_section
6930 && !bfd_is_com_section (exp_seg
))
6932 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6937 /* Check if this is a displacement only operand. */
6938 bigdisp
= i
.types
[this_operand
];
6939 bigdisp
.bitfield
.disp8
= 0;
6940 bigdisp
.bitfield
.disp16
= 0;
6941 bigdisp
.bitfield
.disp32
= 0;
6942 bigdisp
.bitfield
.disp32s
= 0;
6943 bigdisp
.bitfield
.disp64
= 0;
6944 if (operand_type_all_zero (&bigdisp
))
6945 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6951 /* Make sure the memory operand we've been dealt is valid.
6952 Return 1 on success, 0 on a failure. */
6955 i386_index_check (const char *operand_string
)
6958 const char *kind
= "base/index";
6959 #if INFER_ADDR_PREFIX
6965 if (current_templates
->start
->opcode_modifier
.isstring
6966 && !current_templates
->start
->opcode_modifier
.immext
6967 && (current_templates
->end
[-1].opcode_modifier
.isstring
6970 /* Memory operands of string insns are special in that they only allow
6971 a single register (rDI, rSI, or rBX) as their memory address. */
6972 unsigned int expected
;
6974 kind
= "string address";
6976 if (current_templates
->start
->opcode_modifier
.w
)
6978 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6980 if (!type
.bitfield
.baseindex
6981 || ((!i
.mem_operands
!= !intel_syntax
)
6982 && current_templates
->end
[-1].operand_types
[1]
6983 .bitfield
.baseindex
))
6984 type
= current_templates
->end
[-1].operand_types
[1];
6985 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6988 expected
= 3 /* rBX */;
6990 if (!i
.base_reg
|| i
.index_reg
6991 || operand_type_check (i
.types
[this_operand
], disp
))
6993 else if (!(flag_code
== CODE_64BIT
6994 ? i
.prefix
[ADDR_PREFIX
]
6995 ? i
.base_reg
->reg_type
.bitfield
.reg32
6996 : i
.base_reg
->reg_type
.bitfield
.reg64
6997 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6998 ? i
.base_reg
->reg_type
.bitfield
.reg32
6999 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7001 else if (i
.base_reg
->reg_num
!= expected
)
7008 for (j
= 0; j
< i386_regtab_size
; ++j
)
7009 if ((flag_code
== CODE_64BIT
7010 ? i
.prefix
[ADDR_PREFIX
]
7011 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7012 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7013 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7014 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7015 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7016 && i386_regtab
[j
].reg_num
== expected
)
7018 gas_assert (j
< i386_regtab_size
);
7019 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7021 intel_syntax
? '[' : '(',
7023 i386_regtab
[j
].reg_name
,
7024 intel_syntax
? ']' : ')');
7028 else if (flag_code
== CODE_64BIT
)
7031 && ((i
.prefix
[ADDR_PREFIX
] == 0
7032 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7033 || (i
.prefix
[ADDR_PREFIX
]
7034 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7036 || i
.base_reg
->reg_num
!=
7037 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7039 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7040 || (i
.prefix
[ADDR_PREFIX
] == 0
7041 && i
.index_reg
->reg_num
!= RegRiz
7042 && !i
.index_reg
->reg_type
.bitfield
.reg64
7044 || (i
.prefix
[ADDR_PREFIX
]
7045 && i
.index_reg
->reg_num
!= RegEiz
7046 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7051 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7055 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7056 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7058 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7059 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7061 && i
.base_reg
->reg_num
< 6
7062 && i
.index_reg
->reg_num
>= 6
7063 && i
.log2_scale_factor
== 0))))
7070 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7072 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7073 && i
.index_reg
->reg_num
!= RegEiz
)
7074 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7080 #if INFER_ADDR_PREFIX
7081 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7083 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7085 /* Change the size of any displacement too. At most one of
7086 Disp16 or Disp32 is set.
7087 FIXME. There doesn't seem to be any real need for separate
7088 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7089 Removing them would probably clean up the code quite a lot. */
7090 if (flag_code
!= CODE_64BIT
7091 && (i
.types
[this_operand
].bitfield
.disp16
7092 || i
.types
[this_operand
].bitfield
.disp32
))
7093 i
.types
[this_operand
]
7094 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7099 as_bad (_("`%s' is not a valid %s expression"),
7104 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7106 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7107 ? flag_code
== CODE_32BIT
7116 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7120 i386_att_operand (char *operand_string
)
7124 char *op_string
= operand_string
;
7126 if (is_space_char (*op_string
))
7129 /* We check for an absolute prefix (differentiating,
7130 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7131 if (*op_string
== ABSOLUTE_PREFIX
)
7134 if (is_space_char (*op_string
))
7136 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7139 /* Check if operand is a register. */
7140 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7142 i386_operand_type temp
;
7144 /* Check for a segment override by searching for ':' after a
7145 segment register. */
7147 if (is_space_char (*op_string
))
7149 if (*op_string
== ':'
7150 && (r
->reg_type
.bitfield
.sreg2
7151 || r
->reg_type
.bitfield
.sreg3
))
7156 i
.seg
[i
.mem_operands
] = &es
;
7159 i
.seg
[i
.mem_operands
] = &cs
;
7162 i
.seg
[i
.mem_operands
] = &ss
;
7165 i
.seg
[i
.mem_operands
] = &ds
;
7168 i
.seg
[i
.mem_operands
] = &fs
;
7171 i
.seg
[i
.mem_operands
] = &gs
;
7175 /* Skip the ':' and whitespace. */
7177 if (is_space_char (*op_string
))
7180 if (!is_digit_char (*op_string
)
7181 && !is_identifier_char (*op_string
)
7182 && *op_string
!= '('
7183 && *op_string
!= ABSOLUTE_PREFIX
)
7185 as_bad (_("bad memory operand `%s'"), op_string
);
7188 /* Handle case of %es:*foo. */
7189 if (*op_string
== ABSOLUTE_PREFIX
)
7192 if (is_space_char (*op_string
))
7194 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7196 goto do_memory_reference
;
7200 as_bad (_("junk `%s' after register"), op_string
);
7204 temp
.bitfield
.baseindex
= 0;
7205 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7207 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7208 i
.op
[this_operand
].regs
= r
;
7211 else if (*op_string
== REGISTER_PREFIX
)
7213 as_bad (_("bad register name `%s'"), op_string
);
7216 else if (*op_string
== IMMEDIATE_PREFIX
)
7219 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7221 as_bad (_("immediate operand illegal with absolute jump"));
7224 if (!i386_immediate (op_string
))
7227 else if (is_digit_char (*op_string
)
7228 || is_identifier_char (*op_string
)
7229 || *op_string
== '(')
7231 /* This is a memory reference of some sort. */
7234 /* Start and end of displacement string expression (if found). */
7235 char *displacement_string_start
;
7236 char *displacement_string_end
;
7238 do_memory_reference
:
7239 if ((i
.mem_operands
== 1
7240 && !current_templates
->start
->opcode_modifier
.isstring
)
7241 || i
.mem_operands
== 2)
7243 as_bad (_("too many memory references for `%s'"),
7244 current_templates
->start
->name
);
7248 /* Check for base index form. We detect the base index form by
7249 looking for an ')' at the end of the operand, searching
7250 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7252 base_string
= op_string
+ strlen (op_string
);
7255 if (is_space_char (*base_string
))
7258 /* If we only have a displacement, set-up for it to be parsed later. */
7259 displacement_string_start
= op_string
;
7260 displacement_string_end
= base_string
+ 1;
7262 if (*base_string
== ')')
7265 unsigned int parens_balanced
= 1;
7266 /* We've already checked that the number of left & right ()'s are
7267 equal, so this loop will not be infinite. */
7271 if (*base_string
== ')')
7273 if (*base_string
== '(')
7276 while (parens_balanced
);
7278 temp_string
= base_string
;
7280 /* Skip past '(' and whitespace. */
7282 if (is_space_char (*base_string
))
7285 if (*base_string
== ','
7286 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7289 displacement_string_end
= temp_string
;
7291 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7295 base_string
= end_op
;
7296 if (is_space_char (*base_string
))
7300 /* There may be an index reg or scale factor here. */
7301 if (*base_string
== ',')
7304 if (is_space_char (*base_string
))
7307 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7310 base_string
= end_op
;
7311 if (is_space_char (*base_string
))
7313 if (*base_string
== ',')
7316 if (is_space_char (*base_string
))
7319 else if (*base_string
!= ')')
7321 as_bad (_("expecting `,' or `)' "
7322 "after index register in `%s'"),
7327 else if (*base_string
== REGISTER_PREFIX
)
7329 as_bad (_("bad register name `%s'"), base_string
);
7333 /* Check for scale factor. */
7334 if (*base_string
!= ')')
7336 char *end_scale
= i386_scale (base_string
);
7341 base_string
= end_scale
;
7342 if (is_space_char (*base_string
))
7344 if (*base_string
!= ')')
7346 as_bad (_("expecting `)' "
7347 "after scale factor in `%s'"),
7352 else if (!i
.index_reg
)
7354 as_bad (_("expecting index register or scale factor "
7355 "after `,'; got '%c'"),
7360 else if (*base_string
!= ')')
7362 as_bad (_("expecting `,' or `)' "
7363 "after base register in `%s'"),
7368 else if (*base_string
== REGISTER_PREFIX
)
7370 as_bad (_("bad register name `%s'"), base_string
);
7375 /* If there's an expression beginning the operand, parse it,
7376 assuming displacement_string_start and
7377 displacement_string_end are meaningful. */
7378 if (displacement_string_start
!= displacement_string_end
)
7380 if (!i386_displacement (displacement_string_start
,
7381 displacement_string_end
))
7385 /* Special case for (%dx) while doing input/output op. */
7387 && operand_type_equal (&i
.base_reg
->reg_type
,
7388 ®16_inoutportreg
)
7390 && i
.log2_scale_factor
== 0
7391 && i
.seg
[i
.mem_operands
] == 0
7392 && !operand_type_check (i
.types
[this_operand
], disp
))
7394 i
.types
[this_operand
] = inoutportreg
;
7398 if (i386_index_check (operand_string
) == 0)
7400 i
.types
[this_operand
].bitfield
.mem
= 1;
7405 /* It's not a memory operand; argh! */
7406 as_bad (_("invalid char %s beginning operand %d `%s'"),
7407 output_invalid (*op_string
),
7412 return 1; /* Normal return. */
7415 /* md_estimate_size_before_relax()
7417 Called just before relax() for rs_machine_dependent frags. The x86
7418 assembler uses these frags to handle variable size jump
7421 Any symbol that is now undefined will not become defined.
7422 Return the correct fr_subtype in the frag.
7423 Return the initial "guess for variable size of frag" to caller.
7424 The guess is actually the growth beyond the fixed part. Whatever
7425 we do to grow the fixed or variable part contributes to our
7429 md_estimate_size_before_relax (fragP
, segment
)
7433 /* We've already got fragP->fr_subtype right; all we have to do is
7434 check for un-relaxable symbols. On an ELF system, we can't relax
7435 an externally visible symbol, because it may be overridden by a
7437 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7438 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7440 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7441 || S_IS_WEAK (fragP
->fr_symbol
)
7442 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7443 & BSF_GNU_INDIRECT_FUNCTION
))))
7445 #if defined (OBJ_COFF) && defined (TE_PE)
7446 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7447 && S_IS_WEAK (fragP
->fr_symbol
))
7451 /* Symbol is undefined in this segment, or we need to keep a
7452 reloc so that weak symbols can be overridden. */
7453 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7454 enum bfd_reloc_code_real reloc_type
;
7455 unsigned char *opcode
;
7458 if (fragP
->fr_var
!= NO_RELOC
)
7459 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7461 reloc_type
= BFD_RELOC_16_PCREL
;
7463 reloc_type
= BFD_RELOC_32_PCREL
;
7465 old_fr_fix
= fragP
->fr_fix
;
7466 opcode
= (unsigned char *) fragP
->fr_opcode
;
7468 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7471 /* Make jmp (0xeb) a (d)word displacement jump. */
7473 fragP
->fr_fix
+= size
;
7474 fix_new (fragP
, old_fr_fix
, size
,
7476 fragP
->fr_offset
, 1,
7482 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7484 /* Negate the condition, and branch past an
7485 unconditional jump. */
7488 /* Insert an unconditional jump. */
7490 /* We added two extra opcode bytes, and have a two byte
7492 fragP
->fr_fix
+= 2 + 2;
7493 fix_new (fragP
, old_fr_fix
+ 2, 2,
7495 fragP
->fr_offset
, 1,
7502 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7507 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7509 fragP
->fr_offset
, 1,
7511 fixP
->fx_signed
= 1;
7515 /* This changes the byte-displacement jump 0x7N
7516 to the (d)word-displacement jump 0x0f,0x8N. */
7517 opcode
[1] = opcode
[0] + 0x10;
7518 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7519 /* We've added an opcode byte. */
7520 fragP
->fr_fix
+= 1 + size
;
7521 fix_new (fragP
, old_fr_fix
+ 1, size
,
7523 fragP
->fr_offset
, 1,
7528 BAD_CASE (fragP
->fr_subtype
);
7532 return fragP
->fr_fix
- old_fr_fix
;
7535 /* Guess size depending on current relax state. Initially the relax
7536 state will correspond to a short jump and we return 1, because
7537 the variable part of the frag (the branch offset) is one byte
7538 long. However, we can relax a section more than once and in that
7539 case we must either set fr_subtype back to the unrelaxed state,
7540 or return the value for the appropriate branch. */
7541 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7544 /* Called after relax() is finished.
7546 In: Address of frag.
7547 fr_type == rs_machine_dependent.
7548 fr_subtype is what the address relaxed to.
7550 Out: Any fixSs and constants are set up.
7551 Caller will turn frag into a ".space 0". */
7554 md_convert_frag (abfd
, sec
, fragP
)
7555 bfd
*abfd ATTRIBUTE_UNUSED
;
7556 segT sec ATTRIBUTE_UNUSED
;
7559 unsigned char *opcode
;
7560 unsigned char *where_to_put_displacement
= NULL
;
7561 offsetT target_address
;
7562 offsetT opcode_address
;
7563 unsigned int extension
= 0;
7564 offsetT displacement_from_opcode_start
;
7566 opcode
= (unsigned char *) fragP
->fr_opcode
;
7568 /* Address we want to reach in file space. */
7569 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7571 /* Address opcode resides at in file space. */
7572 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7574 /* Displacement from opcode start to fill into instruction. */
7575 displacement_from_opcode_start
= target_address
- opcode_address
;
7577 if ((fragP
->fr_subtype
& BIG
) == 0)
7579 /* Don't have to change opcode. */
7580 extension
= 1; /* 1 opcode + 1 displacement */
7581 where_to_put_displacement
= &opcode
[1];
7585 if (no_cond_jump_promotion
7586 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7587 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7588 _("long jump required"));
7590 switch (fragP
->fr_subtype
)
7592 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7593 extension
= 4; /* 1 opcode + 4 displacement */
7595 where_to_put_displacement
= &opcode
[1];
7598 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7599 extension
= 2; /* 1 opcode + 2 displacement */
7601 where_to_put_displacement
= &opcode
[1];
7604 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7605 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7606 extension
= 5; /* 2 opcode + 4 displacement */
7607 opcode
[1] = opcode
[0] + 0x10;
7608 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7609 where_to_put_displacement
= &opcode
[2];
7612 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7613 extension
= 3; /* 2 opcode + 2 displacement */
7614 opcode
[1] = opcode
[0] + 0x10;
7615 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7616 where_to_put_displacement
= &opcode
[2];
7619 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7624 where_to_put_displacement
= &opcode
[3];
7628 BAD_CASE (fragP
->fr_subtype
);
7633 /* If size if less then four we are sure that the operand fits,
7634 but if it's 4, then it could be that the displacement is larger
7636 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7638 && ((addressT
) (displacement_from_opcode_start
- extension
7639 + ((addressT
) 1 << 31))
7640 > (((addressT
) 2 << 31) - 1)))
7642 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7643 _("jump target out of range"));
7644 /* Make us emit 0. */
7645 displacement_from_opcode_start
= extension
;
7647 /* Now put displacement after opcode. */
7648 md_number_to_chars ((char *) where_to_put_displacement
,
7649 (valueT
) (displacement_from_opcode_start
- extension
),
7650 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7651 fragP
->fr_fix
+= extension
;
7654 /* Apply a fixup (fixS) to segment data, once it has been determined
7655 by our caller that we have all the info we need to fix it up.
7657 On the 386, immediates, displacements, and data pointers are all in
7658 the same (little-endian) format, so we don't need to care about which
7662 md_apply_fix (fixP
, valP
, seg
)
7663 /* The fix we're to put in. */
7665 /* Pointer to the value of the bits. */
7667 /* Segment fix is from. */
7668 segT seg ATTRIBUTE_UNUSED
;
7670 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7671 valueT value
= *valP
;
7673 #if !defined (TE_Mach)
7676 switch (fixP
->fx_r_type
)
7682 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7685 case BFD_RELOC_X86_64_32S
:
7686 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7689 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7692 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7697 if (fixP
->fx_addsy
!= NULL
7698 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7699 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7700 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7701 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7702 && !use_rela_relocations
)
7704 /* This is a hack. There should be a better way to handle this.
7705 This covers for the fact that bfd_install_relocation will
7706 subtract the current location (for partial_inplace, PC relative
7707 relocations); see more below. */
7711 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7714 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7716 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7719 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7722 || (symbol_section_p (fixP
->fx_addsy
)
7723 && sym_seg
!= absolute_section
))
7724 && !generic_force_reloc (fixP
))
7726 /* Yes, we add the values in twice. This is because
7727 bfd_install_relocation subtracts them out again. I think
7728 bfd_install_relocation is broken, but I don't dare change
7730 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7734 #if defined (OBJ_COFF) && defined (TE_PE)
7735 /* For some reason, the PE format does not store a
7736 section address offset for a PC relative symbol. */
7737 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7738 || S_IS_WEAK (fixP
->fx_addsy
))
7739 value
+= md_pcrel_from (fixP
);
7742 #if defined (OBJ_COFF) && defined (TE_PE)
7743 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7745 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7749 /* Fix a few things - the dynamic linker expects certain values here,
7750 and we must not disappoint it. */
7751 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7752 if (IS_ELF
&& fixP
->fx_addsy
)
7753 switch (fixP
->fx_r_type
)
7755 case BFD_RELOC_386_PLT32
:
7756 case BFD_RELOC_X86_64_PLT32
:
7757 /* Make the jump instruction point to the address of the operand. At
7758 runtime we merely add the offset to the actual PLT entry. */
7762 case BFD_RELOC_386_TLS_GD
:
7763 case BFD_RELOC_386_TLS_LDM
:
7764 case BFD_RELOC_386_TLS_IE_32
:
7765 case BFD_RELOC_386_TLS_IE
:
7766 case BFD_RELOC_386_TLS_GOTIE
:
7767 case BFD_RELOC_386_TLS_GOTDESC
:
7768 case BFD_RELOC_X86_64_TLSGD
:
7769 case BFD_RELOC_X86_64_TLSLD
:
7770 case BFD_RELOC_X86_64_GOTTPOFF
:
7771 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7772 value
= 0; /* Fully resolved at runtime. No addend. */
7774 case BFD_RELOC_386_TLS_LE
:
7775 case BFD_RELOC_386_TLS_LDO_32
:
7776 case BFD_RELOC_386_TLS_LE_32
:
7777 case BFD_RELOC_X86_64_DTPOFF32
:
7778 case BFD_RELOC_X86_64_DTPOFF64
:
7779 case BFD_RELOC_X86_64_TPOFF32
:
7780 case BFD_RELOC_X86_64_TPOFF64
:
7781 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7784 case BFD_RELOC_386_TLS_DESC_CALL
:
7785 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7786 value
= 0; /* Fully resolved at runtime. No addend. */
7787 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7791 case BFD_RELOC_386_GOT32
:
7792 case BFD_RELOC_X86_64_GOT32
:
7793 value
= 0; /* Fully resolved at runtime. No addend. */
7796 case BFD_RELOC_VTABLE_INHERIT
:
7797 case BFD_RELOC_VTABLE_ENTRY
:
7804 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7806 #endif /* !defined (TE_Mach) */
7808 /* Are we finished with this relocation now? */
7809 if (fixP
->fx_addsy
== NULL
)
7811 #if defined (OBJ_COFF) && defined (TE_PE)
7812 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7815 /* Remember value for tc_gen_reloc. */
7816 fixP
->fx_addnumber
= value
;
7817 /* Clear out the frag for now. */
7821 else if (use_rela_relocations
)
7823 fixP
->fx_no_overflow
= 1;
7824 /* Remember value for tc_gen_reloc. */
7825 fixP
->fx_addnumber
= value
;
7829 md_number_to_chars (p
, value
, fixP
->fx_size
);
7833 md_atof (int type
, char *litP
, int *sizeP
)
7835 /* This outputs the LITTLENUMs in REVERSE order;
7836 in accord with the bigendian 386. */
7837 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7840 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7843 output_invalid (int c
)
7846 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7849 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7850 "(0x%x)", (unsigned char) c
);
7851 return output_invalid_buf
;
7854 /* REG_STRING starts *before* REGISTER_PREFIX. */
7856 static const reg_entry
*
7857 parse_real_register (char *reg_string
, char **end_op
)
7859 char *s
= reg_string
;
7861 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7864 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7865 if (*s
== REGISTER_PREFIX
)
7868 if (is_space_char (*s
))
7872 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7874 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7875 return (const reg_entry
*) NULL
;
7879 /* For naked regs, make sure that we are not dealing with an identifier.
7880 This prevents confusing an identifier like `eax_var' with register
7882 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7883 return (const reg_entry
*) NULL
;
7887 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7889 /* Handle floating point regs, allowing spaces in the (i) part. */
7890 if (r
== i386_regtab
/* %st is first entry of table */)
7892 if (is_space_char (*s
))
7897 if (is_space_char (*s
))
7899 if (*s
>= '0' && *s
<= '7')
7903 if (is_space_char (*s
))
7908 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7913 /* We have "%st(" then garbage. */
7914 return (const reg_entry
*) NULL
;
7918 if (r
== NULL
|| allow_pseudo_reg
)
7921 if (operand_type_all_zero (&r
->reg_type
))
7922 return (const reg_entry
*) NULL
;
7924 if ((r
->reg_type
.bitfield
.reg32
7925 || r
->reg_type
.bitfield
.sreg3
7926 || r
->reg_type
.bitfield
.control
7927 || r
->reg_type
.bitfield
.debug
7928 || r
->reg_type
.bitfield
.test
)
7929 && !cpu_arch_flags
.bitfield
.cpui386
)
7930 return (const reg_entry
*) NULL
;
7932 if (r
->reg_type
.bitfield
.floatreg
7933 && !cpu_arch_flags
.bitfield
.cpu8087
7934 && !cpu_arch_flags
.bitfield
.cpu287
7935 && !cpu_arch_flags
.bitfield
.cpu387
)
7936 return (const reg_entry
*) NULL
;
7938 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7939 return (const reg_entry
*) NULL
;
7941 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7942 return (const reg_entry
*) NULL
;
7944 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7945 return (const reg_entry
*) NULL
;
7947 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7948 if (!allow_index_reg
7949 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7950 return (const reg_entry
*) NULL
;
7952 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7953 || r
->reg_type
.bitfield
.reg64
)
7954 && (!cpu_arch_flags
.bitfield
.cpulm
7955 || !operand_type_equal (&r
->reg_type
, &control
))
7956 && flag_code
!= CODE_64BIT
)
7957 return (const reg_entry
*) NULL
;
7959 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7960 return (const reg_entry
*) NULL
;
7965 /* REG_STRING starts *before* REGISTER_PREFIX. */
7967 static const reg_entry
*
7968 parse_register (char *reg_string
, char **end_op
)
7972 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7973 r
= parse_real_register (reg_string
, end_op
);
7978 char *save
= input_line_pointer
;
7982 input_line_pointer
= reg_string
;
7983 c
= get_symbol_end ();
7984 symbolP
= symbol_find (reg_string
);
7985 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7987 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7989 know (e
->X_op
== O_register
);
7990 know (e
->X_add_number
>= 0
7991 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7992 r
= i386_regtab
+ e
->X_add_number
;
7993 *end_op
= input_line_pointer
;
7995 *input_line_pointer
= c
;
7996 input_line_pointer
= save
;
8002 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8005 char *end
= input_line_pointer
;
8008 r
= parse_register (name
, &input_line_pointer
);
8009 if (r
&& end
<= input_line_pointer
)
8011 *nextcharP
= *input_line_pointer
;
8012 *input_line_pointer
= 0;
8013 e
->X_op
= O_register
;
8014 e
->X_add_number
= r
- i386_regtab
;
8017 input_line_pointer
= end
;
8019 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8023 md_operand (expressionS
*e
)
8028 switch (*input_line_pointer
)
8030 case REGISTER_PREFIX
:
8031 r
= parse_real_register (input_line_pointer
, &end
);
8034 e
->X_op
= O_register
;
8035 e
->X_add_number
= r
- i386_regtab
;
8036 input_line_pointer
= end
;
8041 gas_assert (intel_syntax
);
8042 end
= input_line_pointer
++;
8044 if (*input_line_pointer
== ']')
8046 ++input_line_pointer
;
8047 e
->X_op_symbol
= make_expr_symbol (e
);
8048 e
->X_add_symbol
= NULL
;
8049 e
->X_add_number
= 0;
8055 input_line_pointer
= end
;
8062 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8063 const char *md_shortopts
= "kVQ:sqn";
8065 const char *md_shortopts
= "qn";
8068 #define OPTION_32 (OPTION_MD_BASE + 0)
8069 #define OPTION_64 (OPTION_MD_BASE + 1)
8070 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8071 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8072 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8073 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8074 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8075 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8076 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8077 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8078 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8079 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8080 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8082 struct option md_longopts
[] =
8084 {"32", no_argument
, NULL
, OPTION_32
},
8085 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8086 || defined (TE_PE) || defined (TE_PEP))
8087 {"64", no_argument
, NULL
, OPTION_64
},
8089 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8090 {"march", required_argument
, NULL
, OPTION_MARCH
},
8091 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8092 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8093 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8094 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8095 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8096 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8097 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8098 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8099 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8100 {NULL
, no_argument
, NULL
, 0}
8102 size_t md_longopts_size
= sizeof (md_longopts
);
8105 md_parse_option (int c
, char *arg
)
8113 optimize_align_code
= 0;
8120 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8121 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8122 should be emitted or not. FIXME: Not implemented. */
8126 /* -V: SVR4 argument to print version ID. */
8128 print_version_id ();
8131 /* -k: Ignore for FreeBSD compatibility. */
8136 /* -s: On i386 Solaris, this tells the native assembler to use
8137 .stab instead of .stab.excl. We always use .stab anyhow. */
8140 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8141 || defined (TE_PE) || defined (TE_PEP))
8144 const char **list
, **l
;
8146 list
= bfd_target_list ();
8147 for (l
= list
; *l
!= NULL
; l
++)
8148 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8149 || strcmp (*l
, "coff-x86-64") == 0
8150 || strcmp (*l
, "pe-x86-64") == 0
8151 || strcmp (*l
, "pei-x86-64") == 0)
8153 default_arch
= "x86_64";
8157 as_fatal (_("No compiled in support for x86_64"));
8164 default_arch
= "i386";
8168 #ifdef SVR4_COMMENT_CHARS
8173 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8175 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8179 i386_comment_chars
= n
;
8185 arch
= xstrdup (arg
);
8189 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8190 next
= strchr (arch
, '+');
8193 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8195 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8198 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8201 cpu_arch_name
= cpu_arch
[j
].name
;
8202 cpu_sub_arch_name
= NULL
;
8203 cpu_arch_flags
= cpu_arch
[j
].flags
;
8204 cpu_arch_isa
= cpu_arch
[j
].type
;
8205 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8206 if (!cpu_arch_tune_set
)
8208 cpu_arch_tune
= cpu_arch_isa
;
8209 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8213 else if (*cpu_arch
[j
].name
== '.'
8214 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8216 /* ISA entension. */
8217 i386_cpu_flags flags
;
8219 if (strncmp (arch
, "no", 2))
8220 flags
= cpu_flags_or (cpu_arch_flags
,
8223 flags
= cpu_flags_and_not (cpu_arch_flags
,
8225 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8227 if (cpu_sub_arch_name
)
8229 char *name
= cpu_sub_arch_name
;
8230 cpu_sub_arch_name
= concat (name
,
8232 (const char *) NULL
);
8236 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8237 cpu_arch_flags
= flags
;
8243 if (j
>= ARRAY_SIZE (cpu_arch
))
8244 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8248 while (next
!= NULL
);
8253 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8254 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8256 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8258 cpu_arch_tune_set
= 1;
8259 cpu_arch_tune
= cpu_arch
[j
].type
;
8260 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8264 if (j
>= ARRAY_SIZE (cpu_arch
))
8265 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8268 case OPTION_MMNEMONIC
:
8269 if (strcasecmp (arg
, "att") == 0)
8271 else if (strcasecmp (arg
, "intel") == 0)
8274 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8277 case OPTION_MSYNTAX
:
8278 if (strcasecmp (arg
, "att") == 0)
8280 else if (strcasecmp (arg
, "intel") == 0)
8283 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8286 case OPTION_MINDEX_REG
:
8287 allow_index_reg
= 1;
8290 case OPTION_MNAKED_REG
:
8291 allow_naked_reg
= 1;
8294 case OPTION_MOLD_GCC
:
8298 case OPTION_MSSE2AVX
:
8302 case OPTION_MSSE_CHECK
:
8303 if (strcasecmp (arg
, "error") == 0)
8304 sse_check
= sse_check_error
;
8305 else if (strcasecmp (arg
, "warning") == 0)
8306 sse_check
= sse_check_warning
;
8307 else if (strcasecmp (arg
, "none") == 0)
8308 sse_check
= sse_check_none
;
8310 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8313 case OPTION_MAVXSCALAR
:
8314 if (strcasecmp (arg
, "128") == 0)
8316 else if (strcasecmp (arg
, "256") == 0)
8319 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8328 #define MESSAGE_TEMPLATE \
8332 show_arch (FILE *stream
, int ext
, int check
)
8334 static char message
[] = MESSAGE_TEMPLATE
;
8335 char *start
= message
+ 27;
8337 int size
= sizeof (MESSAGE_TEMPLATE
);
8344 left
= size
- (start
- message
);
8345 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8347 /* Should it be skipped? */
8348 if (cpu_arch
[j
].skip
)
8351 name
= cpu_arch
[j
].name
;
8352 len
= cpu_arch
[j
].len
;
8355 /* It is an extension. Skip if we aren't asked to show it. */
8366 /* It is an processor. Skip if we show only extension. */
8369 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8371 /* It is an impossible processor - skip. */
8375 /* Reserve 2 spaces for ", " or ",\0" */
8378 /* Check if there is any room. */
8386 p
= mempcpy (p
, name
, len
);
8390 /* Output the current message now and start a new one. */
8393 fprintf (stream
, "%s\n", message
);
8395 left
= size
- (start
- message
) - len
- 2;
8397 gas_assert (left
>= 0);
8399 p
= mempcpy (p
, name
, len
);
8404 fprintf (stream
, "%s\n", message
);
8408 md_show_usage (FILE *stream
)
8410 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8411 fprintf (stream
, _("\
8413 -V print assembler version number\n\
8416 fprintf (stream
, _("\
8417 -n Do not optimize code alignment\n\
8418 -q quieten some warnings\n"));
8419 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8420 fprintf (stream
, _("\
8423 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8424 || defined (TE_PE) || defined (TE_PEP))
8425 fprintf (stream
, _("\
8426 --32/--64 generate 32bit/64bit code\n"));
8428 #ifdef SVR4_COMMENT_CHARS
8429 fprintf (stream
, _("\
8430 --divide do not treat `/' as a comment character\n"));
8432 fprintf (stream
, _("\
8433 --divide ignored\n"));
8435 fprintf (stream
, _("\
8436 -march=CPU[,+EXTENSION...]\n\
8437 generate code for CPU and EXTENSION, CPU is one of:\n"));
8438 show_arch (stream
, 0, 1);
8439 fprintf (stream
, _("\
8440 EXTENSION is combination of:\n"));
8441 show_arch (stream
, 1, 0);
8442 fprintf (stream
, _("\
8443 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8444 show_arch (stream
, 0, 0);
8445 fprintf (stream
, _("\
8446 -msse2avx encode SSE instructions with VEX prefix\n"));
8447 fprintf (stream
, _("\
8448 -msse-check=[none|error|warning]\n\
8449 check SSE instructions\n"));
8450 fprintf (stream
, _("\
8451 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8453 fprintf (stream
, _("\
8454 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8455 fprintf (stream
, _("\
8456 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8457 fprintf (stream
, _("\
8458 -mindex-reg support pseudo index registers\n"));
8459 fprintf (stream
, _("\
8460 -mnaked-reg don't require `%%' prefix for registers\n"));
8461 fprintf (stream
, _("\
8462 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8465 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8466 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8467 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8469 /* Pick the target format to use. */
8472 i386_target_format (void)
8474 if (!strcmp (default_arch
, "x86_64"))
8475 update_code_flag (CODE_64BIT
, 1);
8476 else if (!strcmp (default_arch
, "i386"))
8477 update_code_flag (CODE_32BIT
, 1);
8479 as_fatal (_("Unknown architecture"));
8481 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8482 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8483 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8484 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8486 switch (OUTPUT_FLAVOR
)
8488 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8489 case bfd_target_aout_flavour
:
8490 return AOUT_TARGET_FORMAT
;
8492 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8493 # if defined (TE_PE) || defined (TE_PEP)
8494 case bfd_target_coff_flavour
:
8495 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8496 # elif defined (TE_GO32)
8497 case bfd_target_coff_flavour
:
8500 case bfd_target_coff_flavour
:
8504 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8505 case bfd_target_elf_flavour
:
8507 if (flag_code
== CODE_64BIT
)
8510 use_rela_relocations
= 1;
8512 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8514 if (flag_code
!= CODE_64BIT
)
8515 as_fatal (_("Intel L1OM is 64bit only"));
8516 return ELF_TARGET_L1OM_FORMAT
;
8519 return (flag_code
== CODE_64BIT
8520 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8523 #if defined (OBJ_MACH_O)
8524 case bfd_target_mach_o_flavour
:
8525 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8533 #endif /* OBJ_MAYBE_ more than one */
8535 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8537 i386_elf_emit_arch_note (void)
8539 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8542 asection
*seg
= now_seg
;
8543 subsegT subseg
= now_subseg
;
8544 Elf_Internal_Note i_note
;
8545 Elf_External_Note e_note
;
8546 asection
*note_secp
;
8549 /* Create the .note section. */
8550 note_secp
= subseg_new (".note", 0);
8551 bfd_set_section_flags (stdoutput
,
8553 SEC_HAS_CONTENTS
| SEC_READONLY
);
8555 /* Process the arch string. */
8556 len
= strlen (cpu_arch_name
);
8558 i_note
.namesz
= len
+ 1;
8560 i_note
.type
= NT_ARCH
;
8561 p
= frag_more (sizeof (e_note
.namesz
));
8562 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8563 p
= frag_more (sizeof (e_note
.descsz
));
8564 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8565 p
= frag_more (sizeof (e_note
.type
));
8566 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8567 p
= frag_more (len
+ 1);
8568 strcpy (p
, cpu_arch_name
);
8570 frag_align (2, 0, 0);
8572 subseg_set (seg
, subseg
);
8578 md_undefined_symbol (name
)
8581 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8582 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8583 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8584 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8588 if (symbol_find (name
))
8589 as_bad (_("GOT already in symbol table"));
8590 GOT_symbol
= symbol_new (name
, undefined_section
,
8591 (valueT
) 0, &zero_address_frag
);
8598 /* Round up a section size to the appropriate boundary. */
8601 md_section_align (segment
, size
)
8602 segT segment ATTRIBUTE_UNUSED
;
8605 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8606 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8608 /* For a.out, force the section size to be aligned. If we don't do
8609 this, BFD will align it for us, but it will not write out the
8610 final bytes of the section. This may be a bug in BFD, but it is
8611 easier to fix it here since that is how the other a.out targets
8615 align
= bfd_get_section_alignment (stdoutput
, segment
);
8616 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8623 /* On the i386, PC-relative offsets are relative to the start of the
8624 next instruction. That is, the address of the offset, plus its
8625 size, since the offset is always the last part of the insn. */
8628 md_pcrel_from (fixS
*fixP
)
8630 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8636 s_bss (int ignore ATTRIBUTE_UNUSED
)
8640 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8642 obj_elf_section_change_hook ();
8644 temp
= get_absolute_expression ();
8645 subseg_set (bss_section
, (subsegT
) temp
);
8646 demand_empty_rest_of_line ();
8652 i386_validate_fix (fixS
*fixp
)
8654 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8656 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8660 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8665 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8667 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8674 tc_gen_reloc (section
, fixp
)
8675 asection
*section ATTRIBUTE_UNUSED
;
8679 bfd_reloc_code_real_type code
;
8681 switch (fixp
->fx_r_type
)
8683 case BFD_RELOC_X86_64_PLT32
:
8684 case BFD_RELOC_X86_64_GOT32
:
8685 case BFD_RELOC_X86_64_GOTPCREL
:
8686 case BFD_RELOC_386_PLT32
:
8687 case BFD_RELOC_386_GOT32
:
8688 case BFD_RELOC_386_GOTOFF
:
8689 case BFD_RELOC_386_GOTPC
:
8690 case BFD_RELOC_386_TLS_GD
:
8691 case BFD_RELOC_386_TLS_LDM
:
8692 case BFD_RELOC_386_TLS_LDO_32
:
8693 case BFD_RELOC_386_TLS_IE_32
:
8694 case BFD_RELOC_386_TLS_IE
:
8695 case BFD_RELOC_386_TLS_GOTIE
:
8696 case BFD_RELOC_386_TLS_LE_32
:
8697 case BFD_RELOC_386_TLS_LE
:
8698 case BFD_RELOC_386_TLS_GOTDESC
:
8699 case BFD_RELOC_386_TLS_DESC_CALL
:
8700 case BFD_RELOC_X86_64_TLSGD
:
8701 case BFD_RELOC_X86_64_TLSLD
:
8702 case BFD_RELOC_X86_64_DTPOFF32
:
8703 case BFD_RELOC_X86_64_DTPOFF64
:
8704 case BFD_RELOC_X86_64_GOTTPOFF
:
8705 case BFD_RELOC_X86_64_TPOFF32
:
8706 case BFD_RELOC_X86_64_TPOFF64
:
8707 case BFD_RELOC_X86_64_GOTOFF64
:
8708 case BFD_RELOC_X86_64_GOTPC32
:
8709 case BFD_RELOC_X86_64_GOT64
:
8710 case BFD_RELOC_X86_64_GOTPCREL64
:
8711 case BFD_RELOC_X86_64_GOTPC64
:
8712 case BFD_RELOC_X86_64_GOTPLT64
:
8713 case BFD_RELOC_X86_64_PLTOFF64
:
8714 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8715 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8717 case BFD_RELOC_VTABLE_ENTRY
:
8718 case BFD_RELOC_VTABLE_INHERIT
:
8720 case BFD_RELOC_32_SECREL
:
8722 code
= fixp
->fx_r_type
;
8724 case BFD_RELOC_X86_64_32S
:
8725 if (!fixp
->fx_pcrel
)
8727 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8728 code
= fixp
->fx_r_type
;
8734 switch (fixp
->fx_size
)
8737 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8738 _("can not do %d byte pc-relative relocation"),
8740 code
= BFD_RELOC_32_PCREL
;
8742 case 1: code
= BFD_RELOC_8_PCREL
; break;
8743 case 2: code
= BFD_RELOC_16_PCREL
; break;
8744 case 4: code
= BFD_RELOC_32_PCREL
; break;
8746 case 8: code
= BFD_RELOC_64_PCREL
; break;
8752 switch (fixp
->fx_size
)
8755 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8756 _("can not do %d byte relocation"),
8758 code
= BFD_RELOC_32
;
8760 case 1: code
= BFD_RELOC_8
; break;
8761 case 2: code
= BFD_RELOC_16
; break;
8762 case 4: code
= BFD_RELOC_32
; break;
8764 case 8: code
= BFD_RELOC_64
; break;
8771 if ((code
== BFD_RELOC_32
8772 || code
== BFD_RELOC_32_PCREL
8773 || code
== BFD_RELOC_X86_64_32S
)
8775 && fixp
->fx_addsy
== GOT_symbol
)
8778 code
= BFD_RELOC_386_GOTPC
;
8780 code
= BFD_RELOC_X86_64_GOTPC32
;
8782 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8784 && fixp
->fx_addsy
== GOT_symbol
)
8786 code
= BFD_RELOC_X86_64_GOTPC64
;
8789 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8790 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8791 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8793 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8795 if (!use_rela_relocations
)
8797 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8798 vtable entry to be used in the relocation's section offset. */
8799 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8800 rel
->address
= fixp
->fx_offset
;
8801 #if defined (OBJ_COFF) && defined (TE_PE)
8802 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8803 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8808 /* Use the rela in 64bit mode. */
8811 if (!fixp
->fx_pcrel
)
8812 rel
->addend
= fixp
->fx_offset
;
8816 case BFD_RELOC_X86_64_PLT32
:
8817 case BFD_RELOC_X86_64_GOT32
:
8818 case BFD_RELOC_X86_64_GOTPCREL
:
8819 case BFD_RELOC_X86_64_TLSGD
:
8820 case BFD_RELOC_X86_64_TLSLD
:
8821 case BFD_RELOC_X86_64_GOTTPOFF
:
8822 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8823 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8824 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8827 rel
->addend
= (section
->vma
8829 + fixp
->fx_addnumber
8830 + md_pcrel_from (fixp
));
8835 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8836 if (rel
->howto
== NULL
)
8838 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8839 _("cannot represent relocation type %s"),
8840 bfd_get_reloc_code_name (code
));
8841 /* Set howto to a garbage value so that we can keep going. */
8842 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8843 gas_assert (rel
->howto
!= NULL
);
8849 #include "tc-i386-intel.c"
8852 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8854 int saved_naked_reg
;
8855 char saved_register_dot
;
8857 saved_naked_reg
= allow_naked_reg
;
8858 allow_naked_reg
= 1;
8859 saved_register_dot
= register_chars
['.'];
8860 register_chars
['.'] = '.';
8861 allow_pseudo_reg
= 1;
8862 expression_and_evaluate (exp
);
8863 allow_pseudo_reg
= 0;
8864 register_chars
['.'] = saved_register_dot
;
8865 allow_naked_reg
= saved_naked_reg
;
8867 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8869 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8871 exp
->X_op
= O_constant
;
8872 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8873 .dw2_regnum
[flag_code
>> 1];
8876 exp
->X_op
= O_illegal
;
8881 tc_x86_frame_initial_instructions (void)
8883 static unsigned int sp_regno
[2];
8885 if (!sp_regno
[flag_code
>> 1])
8887 char *saved_input
= input_line_pointer
;
8888 char sp
[][4] = {"esp", "rsp"};
8891 input_line_pointer
= sp
[flag_code
>> 1];
8892 tc_x86_parse_to_dw2regnum (&exp
);
8893 gas_assert (exp
.X_op
== O_constant
);
8894 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8895 input_line_pointer
= saved_input
;
8898 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8899 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8903 i386_elf_section_type (const char *str
, size_t len
)
8905 if (flag_code
== CODE_64BIT
8906 && len
== sizeof ("unwind") - 1
8907 && strncmp (str
, "unwind", 6) == 0)
8908 return SHT_X86_64_UNWIND
;
8915 i386_solaris_fix_up_eh_frame (segT sec
)
8917 if (flag_code
== CODE_64BIT
)
8918 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8924 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8928 exp
.X_op
= O_secrel
;
8929 exp
.X_add_symbol
= symbol
;
8930 exp
.X_add_number
= 0;
8931 emit_expr (&exp
, size
);
8935 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8936 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8939 x86_64_section_letter (int letter
, char **ptr_msg
)
8941 if (flag_code
== CODE_64BIT
)
8944 return SHF_X86_64_LARGE
;
8946 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8949 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8954 x86_64_section_word (char *str
, size_t len
)
8956 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8957 return SHF_X86_64_LARGE
;
8963 handle_large_common (int small ATTRIBUTE_UNUSED
)
8965 if (flag_code
!= CODE_64BIT
)
8967 s_comm_internal (0, elf_common_parse
);
8968 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8972 static segT lbss_section
;
8973 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8974 asection
*saved_bss_section
= bss_section
;
8976 if (lbss_section
== NULL
)
8978 flagword applicable
;
8980 subsegT subseg
= now_subseg
;
8982 /* The .lbss section is for local .largecomm symbols. */
8983 lbss_section
= subseg_new (".lbss", 0);
8984 applicable
= bfd_applicable_section_flags (stdoutput
);
8985 bfd_set_section_flags (stdoutput
, lbss_section
,
8986 applicable
& SEC_ALLOC
);
8987 seg_info (lbss_section
)->bss
= 1;
8989 subseg_set (seg
, subseg
);
8992 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8993 bss_section
= lbss_section
;
8995 s_comm_internal (0, elf_common_parse
);
8997 elf_com_section_ptr
= saved_com_section_ptr
;
8998 bss_section
= saved_bss_section
;
9001 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */