1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "l1om", PROCESSOR_L1OM
,
582 { "k6", PROCESSOR_K6
,
584 { "k6_2", PROCESSOR_K6
,
586 { "athlon", PROCESSOR_ATHLON
,
588 { "sledgehammer", PROCESSOR_K8
,
590 { "opteron", PROCESSOR_K8
,
592 { "k8", PROCESSOR_K8
,
594 { "amdfam10", PROCESSOR_AMDFAM10
,
595 CPU_AMDFAM10_FLAGS
},
596 { ".8087", PROCESSOR_UNKNOWN
,
598 { ".287", PROCESSOR_UNKNOWN
,
600 { ".387", PROCESSOR_UNKNOWN
,
602 { ".no87", PROCESSOR_UNKNOWN
,
604 { ".mmx", PROCESSOR_UNKNOWN
,
606 { ".nommx", PROCESSOR_UNKNOWN
,
608 { ".sse", PROCESSOR_UNKNOWN
,
610 { ".sse2", PROCESSOR_UNKNOWN
,
612 { ".sse3", PROCESSOR_UNKNOWN
,
614 { ".ssse3", PROCESSOR_UNKNOWN
,
616 { ".sse4.1", PROCESSOR_UNKNOWN
,
618 { ".sse4.2", PROCESSOR_UNKNOWN
,
620 { ".sse4", PROCESSOR_UNKNOWN
,
622 { ".nosse", PROCESSOR_UNKNOWN
,
624 { ".avx", PROCESSOR_UNKNOWN
,
626 { ".noavx", PROCESSOR_UNKNOWN
,
628 { ".vmx", PROCESSOR_UNKNOWN
,
630 { ".smx", PROCESSOR_UNKNOWN
,
632 { ".xsave", PROCESSOR_UNKNOWN
,
634 { ".aes", PROCESSOR_UNKNOWN
,
636 { ".pclmul", PROCESSOR_UNKNOWN
,
638 { ".clmul", PROCESSOR_UNKNOWN
,
640 { ".fma", PROCESSOR_UNKNOWN
,
642 { ".fma4", PROCESSOR_UNKNOWN
,
644 { ".movbe", PROCESSOR_UNKNOWN
,
646 { ".ept", PROCESSOR_UNKNOWN
,
648 { ".clflush", PROCESSOR_UNKNOWN
,
650 { ".syscall", PROCESSOR_UNKNOWN
,
652 { ".rdtscp", PROCESSOR_UNKNOWN
,
654 { ".3dnow", PROCESSOR_UNKNOWN
,
656 { ".3dnowa", PROCESSOR_UNKNOWN
,
658 { ".padlock", PROCESSOR_UNKNOWN
,
660 { ".pacifica", PROCESSOR_UNKNOWN
,
662 { ".svme", PROCESSOR_UNKNOWN
,
664 { ".sse4a", PROCESSOR_UNKNOWN
,
666 { ".abm", PROCESSOR_UNKNOWN
,
671 /* Like s_lcomm_internal in gas/read.c but the alignment string
672 is allowed to be optional. */
675 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
682 && *input_line_pointer
== ',')
684 align
= parse_align (needs_align
- 1);
686 if (align
== (addressT
) -1)
701 bss_alloc (symbolP
, size
, align
);
706 pe_lcomm (int needs_align
)
708 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
712 const pseudo_typeS md_pseudo_table
[] =
714 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
715 {"align", s_align_bytes
, 0},
717 {"align", s_align_ptwo
, 0},
719 {"arch", set_cpu_arch
, 0},
723 {"lcomm", pe_lcomm
, 1},
725 {"ffloat", float_cons
, 'f'},
726 {"dfloat", float_cons
, 'd'},
727 {"tfloat", float_cons
, 'x'},
729 {"slong", signed_cons
, 4},
730 {"noopt", s_ignore
, 0},
731 {"optim", s_ignore
, 0},
732 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
733 {"code16", set_code_flag
, CODE_16BIT
},
734 {"code32", set_code_flag
, CODE_32BIT
},
735 {"code64", set_code_flag
, CODE_64BIT
},
736 {"intel_syntax", set_intel_syntax
, 1},
737 {"att_syntax", set_intel_syntax
, 0},
738 {"intel_mnemonic", set_intel_mnemonic
, 1},
739 {"att_mnemonic", set_intel_mnemonic
, 0},
740 {"allow_index_reg", set_allow_index_reg
, 1},
741 {"disallow_index_reg", set_allow_index_reg
, 0},
742 {"sse_check", set_sse_check
, 0},
743 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
744 {"largecomm", handle_large_common
, 0},
746 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
747 {"loc", dwarf2_directive_loc
, 0},
748 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
751 {"secrel32", pe_directive_secrel
, 0},
756 /* For interface with expression (). */
757 extern char *input_line_pointer
;
759 /* Hash table for instruction mnemonic lookup. */
760 static struct hash_control
*op_hash
;
762 /* Hash table for register lookup. */
763 static struct hash_control
*reg_hash
;
766 i386_align_code (fragS
*fragP
, int count
)
768 /* Various efficient no-op patterns for aligning code labels.
769 Note: Don't try to assemble the instructions in the comments.
770 0L and 0w are not legal. */
771 static const char f32_1
[] =
773 static const char f32_2
[] =
774 {0x66,0x90}; /* xchg %ax,%ax */
775 static const char f32_3
[] =
776 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
777 static const char f32_4
[] =
778 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
779 static const char f32_5
[] =
781 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
782 static const char f32_6
[] =
783 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
784 static const char f32_7
[] =
785 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
786 static const char f32_8
[] =
788 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
789 static const char f32_9
[] =
790 {0x89,0xf6, /* movl %esi,%esi */
791 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
792 static const char f32_10
[] =
793 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
794 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
795 static const char f32_11
[] =
796 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
797 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
798 static const char f32_12
[] =
799 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
800 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
801 static const char f32_13
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_14
[] =
805 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f16_3
[] =
808 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
809 static const char f16_4
[] =
810 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
811 static const char f16_5
[] =
813 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
814 static const char f16_6
[] =
815 {0x89,0xf6, /* mov %si,%si */
816 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
817 static const char f16_7
[] =
818 {0x8d,0x74,0x00, /* lea 0(%si),%si */
819 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
820 static const char f16_8
[] =
821 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
822 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
823 static const char jump_31
[] =
824 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
826 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
828 static const char *const f32_patt
[] = {
829 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
830 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
832 static const char *const f16_patt
[] = {
833 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
836 static const char alt_3
[] =
838 /* nopl 0(%[re]ax) */
839 static const char alt_4
[] =
840 {0x0f,0x1f,0x40,0x00};
841 /* nopl 0(%[re]ax,%[re]ax,1) */
842 static const char alt_5
[] =
843 {0x0f,0x1f,0x44,0x00,0x00};
844 /* nopw 0(%[re]ax,%[re]ax,1) */
845 static const char alt_6
[] =
846 {0x66,0x0f,0x1f,0x44,0x00,0x00};
847 /* nopl 0L(%[re]ax) */
848 static const char alt_7
[] =
849 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
850 /* nopl 0L(%[re]ax,%[re]ax,1) */
851 static const char alt_8
[] =
852 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
853 /* nopw 0L(%[re]ax,%[re]ax,1) */
854 static const char alt_9
[] =
855 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_10
[] =
858 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 nopw %cs:0L(%[re]ax,%[re]ax,1) */
861 static const char alt_long_11
[] =
863 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_12
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
874 nopw %cs:0L(%[re]ax,%[re]ax,1) */
875 static const char alt_long_13
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
884 nopw %cs:0L(%[re]ax,%[re]ax,1) */
885 static const char alt_long_14
[] =
890 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
896 nopw %cs:0L(%[re]ax,%[re]ax,1) */
897 static const char alt_long_15
[] =
903 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
904 /* nopl 0(%[re]ax,%[re]ax,1)
905 nopw 0(%[re]ax,%[re]ax,1) */
906 static const char alt_short_11
[] =
907 {0x0f,0x1f,0x44,0x00,0x00,
908 0x66,0x0f,0x1f,0x44,0x00,0x00};
909 /* nopw 0(%[re]ax,%[re]ax,1)
910 nopw 0(%[re]ax,%[re]ax,1) */
911 static const char alt_short_12
[] =
912 {0x66,0x0f,0x1f,0x44,0x00,0x00,
913 0x66,0x0f,0x1f,0x44,0x00,0x00};
914 /* nopw 0(%[re]ax,%[re]ax,1)
916 static const char alt_short_13
[] =
917 {0x66,0x0f,0x1f,0x44,0x00,0x00,
918 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
921 static const char alt_short_14
[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
923 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
925 nopl 0L(%[re]ax,%[re]ax,1) */
926 static const char alt_short_15
[] =
927 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
928 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 static const char *const alt_short_patt
[] = {
930 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
931 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
932 alt_short_14
, alt_short_15
934 static const char *const alt_long_patt
[] = {
935 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
936 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
937 alt_long_14
, alt_long_15
940 /* Only align for at least a positive non-zero boundary. */
941 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
944 /* We need to decide which NOP sequence to use for 32bit and
945 64bit. When -mtune= is used:
947 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
948 PROCESSOR_GENERIC32, f32_patt will be used.
949 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
950 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
951 PROCESSOR_GENERIC64, alt_long_patt will be used.
952 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
953 PROCESSOR_AMDFAM10, alt_short_patt will be used.
955 When -mtune= isn't used, alt_long_patt will be used if
956 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
959 When -march= or .arch is used, we can't use anything beyond
960 cpu_arch_isa_flags. */
962 if (flag_code
== CODE_16BIT
)
966 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
968 /* Adjust jump offset. */
969 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
972 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
973 f16_patt
[count
- 1], count
);
977 const char *const *patt
= NULL
;
979 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
981 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
982 switch (cpu_arch_tune
)
984 case PROCESSOR_UNKNOWN
:
985 /* We use cpu_arch_isa_flags to check if we SHOULD
986 optimize for Cpu686. */
987 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
988 patt
= alt_long_patt
;
992 case PROCESSOR_PENTIUMPRO
:
993 case PROCESSOR_PENTIUM4
:
994 case PROCESSOR_NOCONA
:
996 case PROCESSOR_CORE2
:
997 case PROCESSOR_COREI7
:
999 case PROCESSOR_GENERIC64
:
1000 patt
= alt_long_patt
;
1003 case PROCESSOR_ATHLON
:
1005 case PROCESSOR_AMDFAM10
:
1006 patt
= alt_short_patt
;
1008 case PROCESSOR_I386
:
1009 case PROCESSOR_I486
:
1010 case PROCESSOR_PENTIUM
:
1011 case PROCESSOR_GENERIC32
:
1018 switch (fragP
->tc_frag_data
.tune
)
1020 case PROCESSOR_UNKNOWN
:
1021 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1022 PROCESSOR_UNKNOWN. */
1026 case PROCESSOR_I386
:
1027 case PROCESSOR_I486
:
1028 case PROCESSOR_PENTIUM
:
1030 case PROCESSOR_ATHLON
:
1032 case PROCESSOR_AMDFAM10
:
1033 case PROCESSOR_GENERIC32
:
1034 /* We use cpu_arch_isa_flags to check if we CAN optimize
1036 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1037 patt
= alt_short_patt
;
1041 case PROCESSOR_PENTIUMPRO
:
1042 case PROCESSOR_PENTIUM4
:
1043 case PROCESSOR_NOCONA
:
1044 case PROCESSOR_CORE
:
1045 case PROCESSOR_CORE2
:
1046 case PROCESSOR_COREI7
:
1047 case PROCESSOR_L1OM
:
1048 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1049 patt
= alt_long_patt
;
1053 case PROCESSOR_GENERIC64
:
1054 patt
= alt_long_patt
;
1059 if (patt
== f32_patt
)
1061 /* If the padding is less than 15 bytes, we use the normal
1062 ones. Otherwise, we use a jump instruction and adjust
1066 /* For 64bit, the limit is 3 bytes. */
1067 if (flag_code
== CODE_64BIT
1068 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1073 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1074 patt
[count
- 1], count
);
1077 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1079 /* Adjust jump offset. */
1080 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1085 /* Maximum length of an instruction is 15 byte. If the
1086 padding is greater than 15 bytes and we don't use jump,
1087 we have to break it into smaller pieces. */
1088 int padding
= count
;
1089 while (padding
> 15)
1092 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1097 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1098 patt
[padding
- 1], padding
);
1101 fragP
->fr_var
= count
;
1105 operand_type_all_zero (const union i386_operand_type
*x
)
1107 switch (ARRAY_SIZE(x
->array
))
1116 return !x
->array
[0];
1123 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1125 switch (ARRAY_SIZE(x
->array
))
1140 operand_type_equal (const union i386_operand_type
*x
,
1141 const union i386_operand_type
*y
)
1143 switch (ARRAY_SIZE(x
->array
))
1146 if (x
->array
[2] != y
->array
[2])
1149 if (x
->array
[1] != y
->array
[1])
1152 return x
->array
[0] == y
->array
[0];
1160 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1162 switch (ARRAY_SIZE(x
->array
))
1171 return !x
->array
[0];
1178 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1180 switch (ARRAY_SIZE(x
->array
))
1195 cpu_flags_equal (const union i386_cpu_flags
*x
,
1196 const union i386_cpu_flags
*y
)
1198 switch (ARRAY_SIZE(x
->array
))
1201 if (x
->array
[2] != y
->array
[2])
1204 if (x
->array
[1] != y
->array
[1])
1207 return x
->array
[0] == y
->array
[0];
1215 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1217 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1218 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1221 static INLINE i386_cpu_flags
1222 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1224 switch (ARRAY_SIZE (x
.array
))
1227 x
.array
[2] &= y
.array
[2];
1229 x
.array
[1] &= y
.array
[1];
1231 x
.array
[0] &= y
.array
[0];
1239 static INLINE i386_cpu_flags
1240 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1242 switch (ARRAY_SIZE (x
.array
))
1245 x
.array
[2] |= y
.array
[2];
1247 x
.array
[1] |= y
.array
[1];
1249 x
.array
[0] |= y
.array
[0];
1257 static INLINE i386_cpu_flags
1258 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1260 switch (ARRAY_SIZE (x
.array
))
1263 x
.array
[2] &= ~y
.array
[2];
1265 x
.array
[1] &= ~y
.array
[1];
1267 x
.array
[0] &= ~y
.array
[0];
1275 #define CPU_FLAGS_ARCH_MATCH 0x1
1276 #define CPU_FLAGS_64BIT_MATCH 0x2
1277 #define CPU_FLAGS_AES_MATCH 0x4
1278 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1279 #define CPU_FLAGS_AVX_MATCH 0x10
1281 #define CPU_FLAGS_32BIT_MATCH \
1282 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1283 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1284 #define CPU_FLAGS_PERFECT_MATCH \
1285 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1287 /* Return CPU flags match bits. */
1290 cpu_flags_match (const template *t
)
1292 i386_cpu_flags x
= t
->cpu_flags
;
1293 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1295 x
.bitfield
.cpu64
= 0;
1296 x
.bitfield
.cpuno64
= 0;
1298 if (cpu_flags_all_zero (&x
))
1300 /* This instruction is available on all archs. */
1301 match
|= CPU_FLAGS_32BIT_MATCH
;
1305 /* This instruction is available only on some archs. */
1306 i386_cpu_flags cpu
= cpu_arch_flags
;
1308 cpu
.bitfield
.cpu64
= 0;
1309 cpu
.bitfield
.cpuno64
= 0;
1310 cpu
= cpu_flags_and (x
, cpu
);
1311 if (!cpu_flags_all_zero (&cpu
))
1313 if (x
.bitfield
.cpuavx
)
1315 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1316 if (cpu
.bitfield
.cpuavx
)
1318 /* Check SSE2AVX. */
1319 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1321 match
|= (CPU_FLAGS_ARCH_MATCH
1322 | CPU_FLAGS_AVX_MATCH
);
1324 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1325 match
|= CPU_FLAGS_AES_MATCH
;
1327 if (!x
.bitfield
.cpupclmul
1328 || cpu
.bitfield
.cpupclmul
)
1329 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1333 match
|= CPU_FLAGS_ARCH_MATCH
;
1336 match
|= CPU_FLAGS_32BIT_MATCH
;
1342 static INLINE i386_operand_type
1343 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1345 switch (ARRAY_SIZE (x
.array
))
1348 x
.array
[2] &= y
.array
[2];
1350 x
.array
[1] &= y
.array
[1];
1352 x
.array
[0] &= y
.array
[0];
1360 static INLINE i386_operand_type
1361 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1363 switch (ARRAY_SIZE (x
.array
))
1366 x
.array
[2] |= y
.array
[2];
1368 x
.array
[1] |= y
.array
[1];
1370 x
.array
[0] |= y
.array
[0];
1378 static INLINE i386_operand_type
1379 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1381 switch (ARRAY_SIZE (x
.array
))
1384 x
.array
[2] ^= y
.array
[2];
1386 x
.array
[1] ^= y
.array
[1];
1388 x
.array
[0] ^= y
.array
[0];
1396 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1397 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1398 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1399 static const i386_operand_type inoutportreg
1400 = OPERAND_TYPE_INOUTPORTREG
;
1401 static const i386_operand_type reg16_inoutportreg
1402 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1403 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1404 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1405 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1406 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1407 static const i386_operand_type anydisp
1408 = OPERAND_TYPE_ANYDISP
;
1409 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1410 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1411 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1412 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1413 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1414 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1415 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1416 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1417 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1418 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1419 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1430 operand_type_check (i386_operand_type t
, enum operand_type c
)
1435 return (t
.bitfield
.reg8
1438 || t
.bitfield
.reg64
);
1441 return (t
.bitfield
.imm8
1445 || t
.bitfield
.imm32s
1446 || t
.bitfield
.imm64
);
1449 return (t
.bitfield
.disp8
1450 || t
.bitfield
.disp16
1451 || t
.bitfield
.disp32
1452 || t
.bitfield
.disp32s
1453 || t
.bitfield
.disp64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
1461 || t
.bitfield
.baseindex
);
1470 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1471 operand J for instruction template T. */
1474 match_reg_size (const template *t
, unsigned int j
)
1476 return !((i
.types
[j
].bitfield
.byte
1477 && !t
->operand_types
[j
].bitfield
.byte
)
1478 || (i
.types
[j
].bitfield
.word
1479 && !t
->operand_types
[j
].bitfield
.word
)
1480 || (i
.types
[j
].bitfield
.dword
1481 && !t
->operand_types
[j
].bitfield
.dword
)
1482 || (i
.types
[j
].bitfield
.qword
1483 && !t
->operand_types
[j
].bitfield
.qword
));
1486 /* Return 1 if there is no conflict in any size on operand J for
1487 instruction template T. */
1490 match_mem_size (const template *t
, unsigned int j
)
1492 return (match_reg_size (t
, j
)
1493 && !((i
.types
[j
].bitfield
.unspecified
1494 && !t
->operand_types
[j
].bitfield
.unspecified
)
1495 || (i
.types
[j
].bitfield
.fword
1496 && !t
->operand_types
[j
].bitfield
.fword
)
1497 || (i
.types
[j
].bitfield
.tbyte
1498 && !t
->operand_types
[j
].bitfield
.tbyte
)
1499 || (i
.types
[j
].bitfield
.xmmword
1500 && !t
->operand_types
[j
].bitfield
.xmmword
)
1501 || (i
.types
[j
].bitfield
.ymmword
1502 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1505 /* Return 1 if there is no size conflict on any operands for
1506 instruction template T. */
1509 operand_size_match (const template *t
)
1514 /* Don't check jump instructions. */
1515 if (t
->opcode_modifier
.jump
1516 || t
->opcode_modifier
.jumpbyte
1517 || t
->opcode_modifier
.jumpdword
1518 || t
->opcode_modifier
.jumpintersegment
)
1521 /* Check memory and accumulator operand size. */
1522 for (j
= 0; j
< i
.operands
; j
++)
1524 if (t
->operand_types
[j
].bitfield
.anysize
)
1527 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1533 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1541 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1544 /* Check reverse. */
1545 gas_assert (i
.operands
== 2);
1548 for (j
= 0; j
< 2; j
++)
1550 if (t
->operand_types
[j
].bitfield
.acc
1551 && !match_reg_size (t
, j
? 0 : 1))
1557 if (i
.types
[j
].bitfield
.mem
1558 && !match_mem_size (t
, j
? 0 : 1))
1569 operand_type_match (i386_operand_type overlap
,
1570 i386_operand_type given
)
1572 i386_operand_type temp
= overlap
;
1574 temp
.bitfield
.jumpabsolute
= 0;
1575 temp
.bitfield
.unspecified
= 0;
1576 temp
.bitfield
.byte
= 0;
1577 temp
.bitfield
.word
= 0;
1578 temp
.bitfield
.dword
= 0;
1579 temp
.bitfield
.fword
= 0;
1580 temp
.bitfield
.qword
= 0;
1581 temp
.bitfield
.tbyte
= 0;
1582 temp
.bitfield
.xmmword
= 0;
1583 temp
.bitfield
.ymmword
= 0;
1584 if (operand_type_all_zero (&temp
))
1587 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1588 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1591 /* If given types g0 and g1 are registers they must be of the same type
1592 unless the expected operand type register overlap is null.
1593 Note that Acc in a template matches every size of reg. */
1596 operand_type_register_match (i386_operand_type m0
,
1597 i386_operand_type g0
,
1598 i386_operand_type t0
,
1599 i386_operand_type m1
,
1600 i386_operand_type g1
,
1601 i386_operand_type t1
)
1603 if (!operand_type_check (g0
, reg
))
1606 if (!operand_type_check (g1
, reg
))
1609 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1610 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1611 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1612 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1615 if (m0
.bitfield
.acc
)
1617 t0
.bitfield
.reg8
= 1;
1618 t0
.bitfield
.reg16
= 1;
1619 t0
.bitfield
.reg32
= 1;
1620 t0
.bitfield
.reg64
= 1;
1623 if (m1
.bitfield
.acc
)
1625 t1
.bitfield
.reg8
= 1;
1626 t1
.bitfield
.reg16
= 1;
1627 t1
.bitfield
.reg32
= 1;
1628 t1
.bitfield
.reg64
= 1;
1631 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1632 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1633 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1634 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1637 static INLINE
unsigned int
1638 mode_from_disp_size (i386_operand_type t
)
1640 if (t
.bitfield
.disp8
)
1642 else if (t
.bitfield
.disp16
1643 || t
.bitfield
.disp32
1644 || t
.bitfield
.disp32s
)
1651 fits_in_signed_byte (offsetT num
)
1653 return (num
>= -128) && (num
<= 127);
1657 fits_in_unsigned_byte (offsetT num
)
1659 return (num
& 0xff) == num
;
1663 fits_in_unsigned_word (offsetT num
)
1665 return (num
& 0xffff) == num
;
1669 fits_in_signed_word (offsetT num
)
1671 return (-32768 <= num
) && (num
<= 32767);
1675 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1680 return (!(((offsetT
) -1 << 31) & num
)
1681 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1683 } /* fits_in_signed_long() */
1686 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1691 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1693 } /* fits_in_unsigned_long() */
1695 static i386_operand_type
1696 smallest_imm_type (offsetT num
)
1698 i386_operand_type t
;
1700 operand_type_set (&t
, 0);
1701 t
.bitfield
.imm64
= 1;
1703 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1705 /* This code is disabled on the 486 because all the Imm1 forms
1706 in the opcode table are slower on the i486. They're the
1707 versions with the implicitly specified single-position
1708 displacement, which has another syntax if you really want to
1710 t
.bitfield
.imm1
= 1;
1711 t
.bitfield
.imm8
= 1;
1712 t
.bitfield
.imm8s
= 1;
1713 t
.bitfield
.imm16
= 1;
1714 t
.bitfield
.imm32
= 1;
1715 t
.bitfield
.imm32s
= 1;
1717 else if (fits_in_signed_byte (num
))
1719 t
.bitfield
.imm8
= 1;
1720 t
.bitfield
.imm8s
= 1;
1721 t
.bitfield
.imm16
= 1;
1722 t
.bitfield
.imm32
= 1;
1723 t
.bitfield
.imm32s
= 1;
1725 else if (fits_in_unsigned_byte (num
))
1727 t
.bitfield
.imm8
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1734 t
.bitfield
.imm16
= 1;
1735 t
.bitfield
.imm32
= 1;
1736 t
.bitfield
.imm32s
= 1;
1738 else if (fits_in_signed_long (num
))
1740 t
.bitfield
.imm32
= 1;
1741 t
.bitfield
.imm32s
= 1;
1743 else if (fits_in_unsigned_long (num
))
1744 t
.bitfield
.imm32
= 1;
1750 offset_in_range (offsetT val
, int size
)
1756 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1757 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1758 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1760 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1765 /* If BFD64, sign extend val. */
1766 if (!use_rela_relocations
)
1767 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1768 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1770 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1772 char buf1
[40], buf2
[40];
1774 sprint_value (buf1
, val
);
1775 sprint_value (buf2
, val
& mask
);
1776 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1781 /* Returns 0 if attempting to add a prefix where one from the same
1782 class already exists, 1 if non rep/repne added, 2 if rep/repne
1785 add_prefix (unsigned int prefix
)
1790 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1791 && flag_code
== CODE_64BIT
)
1793 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1794 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1795 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1806 case CS_PREFIX_OPCODE
:
1807 case DS_PREFIX_OPCODE
:
1808 case ES_PREFIX_OPCODE
:
1809 case FS_PREFIX_OPCODE
:
1810 case GS_PREFIX_OPCODE
:
1811 case SS_PREFIX_OPCODE
:
1815 case REPNE_PREFIX_OPCODE
:
1816 case REPE_PREFIX_OPCODE
:
1819 case LOCK_PREFIX_OPCODE
:
1827 case ADDR_PREFIX_OPCODE
:
1831 case DATA_PREFIX_OPCODE
:
1835 if (i
.prefix
[q
] != 0)
1843 i
.prefix
[q
] |= prefix
;
1846 as_bad (_("same type of prefix used twice"));
1852 set_code_flag (int value
)
1855 if (flag_code
== CODE_64BIT
)
1857 cpu_arch_flags
.bitfield
.cpu64
= 1;
1858 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1862 cpu_arch_flags
.bitfield
.cpu64
= 0;
1863 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1865 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1867 as_bad (_("64bit mode not supported on this CPU."));
1869 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1871 as_bad (_("32bit mode not supported on this CPU."));
1873 stackop_size
= '\0';
1877 set_16bit_gcc_code_flag (int new_code_flag
)
1879 flag_code
= new_code_flag
;
1880 if (flag_code
!= CODE_16BIT
)
1882 cpu_arch_flags
.bitfield
.cpu64
= 0;
1883 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1884 stackop_size
= LONG_MNEM_SUFFIX
;
1888 set_intel_syntax (int syntax_flag
)
1890 /* Find out if register prefixing is specified. */
1891 int ask_naked_reg
= 0;
1894 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1896 char *string
= input_line_pointer
;
1897 int e
= get_symbol_end ();
1899 if (strcmp (string
, "prefix") == 0)
1901 else if (strcmp (string
, "noprefix") == 0)
1904 as_bad (_("bad argument to syntax directive."));
1905 *input_line_pointer
= e
;
1907 demand_empty_rest_of_line ();
1909 intel_syntax
= syntax_flag
;
1911 if (ask_naked_reg
== 0)
1912 allow_naked_reg
= (intel_syntax
1913 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1915 allow_naked_reg
= (ask_naked_reg
< 0);
1917 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1919 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1920 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1921 register_prefix
= allow_naked_reg
? "" : "%";
1925 set_intel_mnemonic (int mnemonic_flag
)
1927 intel_mnemonic
= mnemonic_flag
;
1931 set_allow_index_reg (int flag
)
1933 allow_index_reg
= flag
;
1937 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1941 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1943 char *string
= input_line_pointer
;
1944 int e
= get_symbol_end ();
1946 if (strcmp (string
, "none") == 0)
1947 sse_check
= sse_check_none
;
1948 else if (strcmp (string
, "warning") == 0)
1949 sse_check
= sse_check_warning
;
1950 else if (strcmp (string
, "error") == 0)
1951 sse_check
= sse_check_error
;
1953 as_bad (_("bad argument to sse_check directive."));
1954 *input_line_pointer
= e
;
1957 as_bad (_("missing argument for sse_check directive"));
1959 demand_empty_rest_of_line ();
1963 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1964 i386_cpu_flags
new ATTRIBUTE_UNUSED
)
1966 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1967 static const char *arch
;
1969 /* Intel LIOM is only supported on ELF. */
1975 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1976 use default_arch. */
1977 arch
= cpu_arch_name
;
1979 arch
= default_arch
;
1982 /* If we are targeting Intel L1OM, we must enable it. */
1983 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
1984 || new.bitfield
.cpul1om
)
1987 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
1992 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1996 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1998 char *string
= input_line_pointer
;
1999 int e
= get_symbol_end ();
2001 i386_cpu_flags flags
;
2003 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2005 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2007 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2011 cpu_arch_name
= cpu_arch
[i
].name
;
2012 cpu_sub_arch_name
= NULL
;
2013 cpu_arch_flags
= cpu_arch
[i
].flags
;
2014 if (flag_code
== CODE_64BIT
)
2016 cpu_arch_flags
.bitfield
.cpu64
= 1;
2017 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2021 cpu_arch_flags
.bitfield
.cpu64
= 0;
2022 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2024 cpu_arch_isa
= cpu_arch
[i
].type
;
2025 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2026 if (!cpu_arch_tune_set
)
2028 cpu_arch_tune
= cpu_arch_isa
;
2029 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2034 if (strncmp (string
+ 1, "no", 2))
2035 flags
= cpu_flags_or (cpu_arch_flags
,
2038 flags
= cpu_flags_and_not (cpu_arch_flags
,
2040 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2042 if (cpu_sub_arch_name
)
2044 char *name
= cpu_sub_arch_name
;
2045 cpu_sub_arch_name
= concat (name
,
2047 (const char *) NULL
);
2051 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2052 cpu_arch_flags
= flags
;
2054 *input_line_pointer
= e
;
2055 demand_empty_rest_of_line ();
2059 if (i
>= ARRAY_SIZE (cpu_arch
))
2060 as_bad (_("no such architecture: `%s'"), string
);
2062 *input_line_pointer
= e
;
2065 as_bad (_("missing cpu architecture"));
2067 no_cond_jump_promotion
= 0;
2068 if (*input_line_pointer
== ','
2069 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2071 char *string
= ++input_line_pointer
;
2072 int e
= get_symbol_end ();
2074 if (strcmp (string
, "nojumps") == 0)
2075 no_cond_jump_promotion
= 1;
2076 else if (strcmp (string
, "jumps") == 0)
2079 as_bad (_("no such architecture modifier: `%s'"), string
);
2081 *input_line_pointer
= e
;
2084 demand_empty_rest_of_line ();
2087 enum bfd_architecture
2090 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2092 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2093 || flag_code
!= CODE_64BIT
)
2094 as_fatal (_("Intel L1OM is 64bit ELF only"));
2095 return bfd_arch_l1om
;
2098 return bfd_arch_i386
;
2104 if (!strcmp (default_arch
, "x86_64"))
2106 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2108 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2109 as_fatal (_("Intel L1OM is 64bit ELF only"));
2110 return bfd_mach_l1om
;
2113 return bfd_mach_x86_64
;
2115 else if (!strcmp (default_arch
, "i386"))
2116 return bfd_mach_i386_i386
;
2118 as_fatal (_("Unknown architecture"));
2124 const char *hash_err
;
2126 /* Initialize op_hash hash table. */
2127 op_hash
= hash_new ();
2130 const template *optab
;
2131 templates
*core_optab
;
2133 /* Setup for loop. */
2135 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2136 core_optab
->start
= optab
;
2141 if (optab
->name
== NULL
2142 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2144 /* different name --> ship out current template list;
2145 add to hash table; & begin anew. */
2146 core_optab
->end
= optab
;
2147 hash_err
= hash_insert (op_hash
,
2149 (void *) core_optab
);
2152 as_fatal (_("Internal Error: Can't hash %s: %s"),
2156 if (optab
->name
== NULL
)
2158 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2159 core_optab
->start
= optab
;
2164 /* Initialize reg_hash hash table. */
2165 reg_hash
= hash_new ();
2167 const reg_entry
*regtab
;
2168 unsigned int regtab_size
= i386_regtab_size
;
2170 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2172 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2174 as_fatal (_("Internal Error: Can't hash %s: %s"),
2180 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2185 for (c
= 0; c
< 256; c
++)
2190 mnemonic_chars
[c
] = c
;
2191 register_chars
[c
] = c
;
2192 operand_chars
[c
] = c
;
2194 else if (ISLOWER (c
))
2196 mnemonic_chars
[c
] = c
;
2197 register_chars
[c
] = c
;
2198 operand_chars
[c
] = c
;
2200 else if (ISUPPER (c
))
2202 mnemonic_chars
[c
] = TOLOWER (c
);
2203 register_chars
[c
] = mnemonic_chars
[c
];
2204 operand_chars
[c
] = c
;
2207 if (ISALPHA (c
) || ISDIGIT (c
))
2208 identifier_chars
[c
] = c
;
2211 identifier_chars
[c
] = c
;
2212 operand_chars
[c
] = c
;
2217 identifier_chars
['@'] = '@';
2220 identifier_chars
['?'] = '?';
2221 operand_chars
['?'] = '?';
2223 digit_chars
['-'] = '-';
2224 mnemonic_chars
['_'] = '_';
2225 mnemonic_chars
['-'] = '-';
2226 mnemonic_chars
['.'] = '.';
2227 identifier_chars
['_'] = '_';
2228 identifier_chars
['.'] = '.';
2230 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2231 operand_chars
[(unsigned char) *p
] = *p
;
2234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2237 record_alignment (text_section
, 2);
2238 record_alignment (data_section
, 2);
2239 record_alignment (bss_section
, 2);
2243 if (flag_code
== CODE_64BIT
)
2245 x86_dwarf2_return_column
= 16;
2246 x86_cie_data_alignment
= -8;
2250 x86_dwarf2_return_column
= 8;
2251 x86_cie_data_alignment
= -4;
2256 i386_print_statistics (FILE *file
)
2258 hash_print_statistics (file
, "i386 opcode", op_hash
);
2259 hash_print_statistics (file
, "i386 register", reg_hash
);
2264 /* Debugging routines for md_assemble. */
2265 static void pte (template *);
2266 static void pt (i386_operand_type
);
2267 static void pe (expressionS
*);
2268 static void ps (symbolS
*);
2271 pi (char *line
, i386_insn
*x
)
2275 fprintf (stdout
, "%s: template ", line
);
2277 fprintf (stdout
, " address: base %s index %s scale %x\n",
2278 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2279 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2280 x
->log2_scale_factor
);
2281 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2282 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2283 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2284 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2285 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2286 (x
->rex
& REX_W
) != 0,
2287 (x
->rex
& REX_R
) != 0,
2288 (x
->rex
& REX_X
) != 0,
2289 (x
->rex
& REX_B
) != 0);
2290 for (i
= 0; i
< x
->operands
; i
++)
2292 fprintf (stdout
, " #%d: ", i
+ 1);
2294 fprintf (stdout
, "\n");
2295 if (x
->types
[i
].bitfield
.reg8
2296 || x
->types
[i
].bitfield
.reg16
2297 || x
->types
[i
].bitfield
.reg32
2298 || x
->types
[i
].bitfield
.reg64
2299 || x
->types
[i
].bitfield
.regmmx
2300 || x
->types
[i
].bitfield
.regxmm
2301 || x
->types
[i
].bitfield
.regymm
2302 || x
->types
[i
].bitfield
.sreg2
2303 || x
->types
[i
].bitfield
.sreg3
2304 || x
->types
[i
].bitfield
.control
2305 || x
->types
[i
].bitfield
.debug
2306 || x
->types
[i
].bitfield
.test
)
2307 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2308 if (operand_type_check (x
->types
[i
], imm
))
2310 if (operand_type_check (x
->types
[i
], disp
))
2311 pe (x
->op
[i
].disps
);
2319 fprintf (stdout
, " %d operands ", t
->operands
);
2320 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2321 if (t
->extension_opcode
!= None
)
2322 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2323 if (t
->opcode_modifier
.d
)
2324 fprintf (stdout
, "D");
2325 if (t
->opcode_modifier
.w
)
2326 fprintf (stdout
, "W");
2327 fprintf (stdout
, "\n");
2328 for (i
= 0; i
< t
->operands
; i
++)
2330 fprintf (stdout
, " #%d type ", i
+ 1);
2331 pt (t
->operand_types
[i
]);
2332 fprintf (stdout
, "\n");
2339 fprintf (stdout
, " operation %d\n", e
->X_op
);
2340 fprintf (stdout
, " add_number %ld (%lx)\n",
2341 (long) e
->X_add_number
, (long) e
->X_add_number
);
2342 if (e
->X_add_symbol
)
2344 fprintf (stdout
, " add_symbol ");
2345 ps (e
->X_add_symbol
);
2346 fprintf (stdout
, "\n");
2350 fprintf (stdout
, " op_symbol ");
2351 ps (e
->X_op_symbol
);
2352 fprintf (stdout
, "\n");
2359 fprintf (stdout
, "%s type %s%s",
2361 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2362 segment_name (S_GET_SEGMENT (s
)));
2365 static struct type_name
2367 i386_operand_type mask
;
2370 const type_names
[] =
2372 { OPERAND_TYPE_REG8
, "r8" },
2373 { OPERAND_TYPE_REG16
, "r16" },
2374 { OPERAND_TYPE_REG32
, "r32" },
2375 { OPERAND_TYPE_REG64
, "r64" },
2376 { OPERAND_TYPE_IMM8
, "i8" },
2377 { OPERAND_TYPE_IMM8
, "i8s" },
2378 { OPERAND_TYPE_IMM16
, "i16" },
2379 { OPERAND_TYPE_IMM32
, "i32" },
2380 { OPERAND_TYPE_IMM32S
, "i32s" },
2381 { OPERAND_TYPE_IMM64
, "i64" },
2382 { OPERAND_TYPE_IMM1
, "i1" },
2383 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2384 { OPERAND_TYPE_DISP8
, "d8" },
2385 { OPERAND_TYPE_DISP16
, "d16" },
2386 { OPERAND_TYPE_DISP32
, "d32" },
2387 { OPERAND_TYPE_DISP32S
, "d32s" },
2388 { OPERAND_TYPE_DISP64
, "d64" },
2389 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2390 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2391 { OPERAND_TYPE_CONTROL
, "control reg" },
2392 { OPERAND_TYPE_TEST
, "test reg" },
2393 { OPERAND_TYPE_DEBUG
, "debug reg" },
2394 { OPERAND_TYPE_FLOATREG
, "FReg" },
2395 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2396 { OPERAND_TYPE_SREG2
, "SReg2" },
2397 { OPERAND_TYPE_SREG3
, "SReg3" },
2398 { OPERAND_TYPE_ACC
, "Acc" },
2399 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2400 { OPERAND_TYPE_REGMMX
, "rMMX" },
2401 { OPERAND_TYPE_REGXMM
, "rXMM" },
2402 { OPERAND_TYPE_REGYMM
, "rYMM" },
2403 { OPERAND_TYPE_ESSEG
, "es" },
2407 pt (i386_operand_type t
)
2410 i386_operand_type a
;
2412 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2414 a
= operand_type_and (t
, type_names
[j
].mask
);
2415 if (!operand_type_all_zero (&a
))
2416 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2421 #endif /* DEBUG386 */
2423 static bfd_reloc_code_real_type
2424 reloc (unsigned int size
,
2427 bfd_reloc_code_real_type other
)
2429 if (other
!= NO_RELOC
)
2431 reloc_howto_type
*reloc
;
2436 case BFD_RELOC_X86_64_GOT32
:
2437 return BFD_RELOC_X86_64_GOT64
;
2439 case BFD_RELOC_X86_64_PLTOFF64
:
2440 return BFD_RELOC_X86_64_PLTOFF64
;
2442 case BFD_RELOC_X86_64_GOTPC32
:
2443 other
= BFD_RELOC_X86_64_GOTPC64
;
2445 case BFD_RELOC_X86_64_GOTPCREL
:
2446 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2448 case BFD_RELOC_X86_64_TPOFF32
:
2449 other
= BFD_RELOC_X86_64_TPOFF64
;
2451 case BFD_RELOC_X86_64_DTPOFF32
:
2452 other
= BFD_RELOC_X86_64_DTPOFF64
;
2458 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2459 if (size
== 4 && flag_code
!= CODE_64BIT
)
2462 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2464 as_bad (_("unknown relocation (%u)"), other
);
2465 else if (size
!= bfd_get_reloc_size (reloc
))
2466 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2467 bfd_get_reloc_size (reloc
),
2469 else if (pcrel
&& !reloc
->pc_relative
)
2470 as_bad (_("non-pc-relative relocation for pc-relative field"));
2471 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2473 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2475 as_bad (_("relocated field and relocation type differ in signedness"));
2484 as_bad (_("there are no unsigned pc-relative relocations"));
2487 case 1: return BFD_RELOC_8_PCREL
;
2488 case 2: return BFD_RELOC_16_PCREL
;
2489 case 4: return BFD_RELOC_32_PCREL
;
2490 case 8: return BFD_RELOC_64_PCREL
;
2492 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2499 case 4: return BFD_RELOC_X86_64_32S
;
2504 case 1: return BFD_RELOC_8
;
2505 case 2: return BFD_RELOC_16
;
2506 case 4: return BFD_RELOC_32
;
2507 case 8: return BFD_RELOC_64
;
2509 as_bad (_("cannot do %s %u byte relocation"),
2510 sign
> 0 ? "signed" : "unsigned", size
);
2516 /* Here we decide which fixups can be adjusted to make them relative to
2517 the beginning of the section instead of the symbol. Basically we need
2518 to make sure that the dynamic relocations are done correctly, so in
2519 some cases we force the original symbol to be used. */
2522 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2524 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2528 /* Don't adjust pc-relative references to merge sections in 64-bit
2530 if (use_rela_relocations
2531 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2535 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2536 and changed later by validate_fix. */
2537 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2538 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2541 /* adjust_reloc_syms doesn't know about the GOT. */
2542 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2543 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2544 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2545 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2546 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2547 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2548 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2549 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2553 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2554 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2555 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2556 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2557 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2558 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2559 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2566 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2567 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2568 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2569 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2576 intel_float_operand (const char *mnemonic
)
2578 /* Note that the value returned is meaningful only for opcodes with (memory)
2579 operands, hence the code here is free to improperly handle opcodes that
2580 have no operands (for better performance and smaller code). */
2582 if (mnemonic
[0] != 'f')
2583 return 0; /* non-math */
2585 switch (mnemonic
[1])
2587 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2588 the fs segment override prefix not currently handled because no
2589 call path can make opcodes without operands get here */
2591 return 2 /* integer op */;
2593 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2594 return 3; /* fldcw/fldenv */
2597 if (mnemonic
[2] != 'o' /* fnop */)
2598 return 3; /* non-waiting control op */
2601 if (mnemonic
[2] == 's')
2602 return 3; /* frstor/frstpm */
2605 if (mnemonic
[2] == 'a')
2606 return 3; /* fsave */
2607 if (mnemonic
[2] == 't')
2609 switch (mnemonic
[3])
2611 case 'c': /* fstcw */
2612 case 'd': /* fstdw */
2613 case 'e': /* fstenv */
2614 case 's': /* fsts[gw] */
2620 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2621 return 0; /* fxsave/fxrstor are not really math ops */
2628 /* Build the VEX prefix. */
2631 build_vex_prefix (const template *t
)
2633 unsigned int register_specifier
;
2634 unsigned int implied_prefix
;
2635 unsigned int vector_length
;
2637 /* Check register specifier. */
2638 if (i
.vex
.register_specifier
)
2640 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2641 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2642 register_specifier
+= 8;
2643 register_specifier
= ~register_specifier
& 0xf;
2646 register_specifier
= 0xf;
2648 /* Use 2-byte VEX prefix by swappping destination and source
2651 && i
.operands
== i
.reg_operands
2652 && i
.tm
.opcode_modifier
.vex0f
2653 && i
.tm
.opcode_modifier
.s
2656 unsigned int xchg
= i
.operands
- 1;
2657 union i386_op temp_op
;
2658 i386_operand_type temp_type
;
2660 temp_type
= i
.types
[xchg
];
2661 i
.types
[xchg
] = i
.types
[0];
2662 i
.types
[0] = temp_type
;
2663 temp_op
= i
.op
[xchg
];
2664 i
.op
[xchg
] = i
.op
[0];
2667 gas_assert (i
.rm
.mode
== 3);
2671 i
.rm
.regmem
= i
.rm
.reg
;
2674 /* Use the next insn. */
2678 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2680 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2685 case DATA_PREFIX_OPCODE
:
2688 case REPE_PREFIX_OPCODE
:
2691 case REPNE_PREFIX_OPCODE
:
2698 /* Use 2-byte VEX prefix if possible. */
2699 if (i
.tm
.opcode_modifier
.vex0f
2700 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2702 /* 2-byte VEX prefix. */
2706 i
.vex
.bytes
[0] = 0xc5;
2708 /* Check the REX.R bit. */
2709 r
= (i
.rex
& REX_R
) ? 0 : 1;
2710 i
.vex
.bytes
[1] = (r
<< 7
2711 | register_specifier
<< 3
2712 | vector_length
<< 2
2717 /* 3-byte VEX prefix. */
2720 if (i
.tm
.opcode_modifier
.vex0f
)
2722 else if (i
.tm
.opcode_modifier
.vex0f38
)
2724 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2730 i
.vex
.bytes
[0] = 0xc4;
2732 /* The high 3 bits of the second VEX byte are 1's compliment
2733 of RXB bits from REX. */
2734 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2736 /* Check the REX.W bit. */
2737 w
= (i
.rex
& REX_W
) ? 1 : 0;
2738 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2743 if (i
.tm
.opcode_modifier
.vexw1
)
2747 i
.vex
.bytes
[2] = (w
<< 7
2748 | register_specifier
<< 3
2749 | vector_length
<< 2
2755 process_immext (void)
2759 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2761 /* SSE3 Instructions have the fixed operands with an opcode
2762 suffix which is coded in the same place as an 8-bit immediate
2763 field would be. Here we check those operands and remove them
2767 for (x
= 0; x
< i
.operands
; x
++)
2768 if (i
.op
[x
].regs
->reg_num
!= x
)
2769 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2770 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2776 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2777 which is coded in the same place as an 8-bit immediate field
2778 would be. Here we fake an 8-bit immediate operand from the
2779 opcode suffix stored in tm.extension_opcode.
2781 AVX instructions also use this encoding, for some of
2782 3 argument instructions. */
2784 gas_assert (i
.imm_operands
== 0
2786 || (i
.tm
.opcode_modifier
.vex
2787 && i
.operands
<= 4)));
2789 exp
= &im_expressions
[i
.imm_operands
++];
2790 i
.op
[i
.operands
].imms
= exp
;
2791 i
.types
[i
.operands
] = imm8
;
2793 exp
->X_op
= O_constant
;
2794 exp
->X_add_number
= i
.tm
.extension_opcode
;
2795 i
.tm
.extension_opcode
= None
;
2798 /* This is the guts of the machine-dependent assembler. LINE points to a
2799 machine dependent instruction. This function is supposed to emit
2800 the frags/bytes it assembles to. */
2803 md_assemble (char *line
)
2806 char mnemonic
[MAX_MNEM_SIZE
];
2809 /* Initialize globals. */
2810 memset (&i
, '\0', sizeof (i
));
2811 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2812 i
.reloc
[j
] = NO_RELOC
;
2813 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2814 memset (im_expressions
, '\0', sizeof (im_expressions
));
2815 save_stack_p
= save_stack
;
2817 /* First parse an instruction mnemonic & call i386_operand for the operands.
2818 We assume that the scrubber has arranged it so that line[0] is the valid
2819 start of a (possibly prefixed) mnemonic. */
2821 line
= parse_insn (line
, mnemonic
);
2825 line
= parse_operands (line
, mnemonic
);
2830 /* Now we've parsed the mnemonic into a set of templates, and have the
2831 operands at hand. */
2833 /* All intel opcodes have reversed operands except for "bound" and
2834 "enter". We also don't reverse intersegment "jmp" and "call"
2835 instructions with 2 immediate operands so that the immediate segment
2836 precedes the offset, as it does when in AT&T mode. */
2839 && (strcmp (mnemonic
, "bound") != 0)
2840 && (strcmp (mnemonic
, "invlpga") != 0)
2841 && !(operand_type_check (i
.types
[0], imm
)
2842 && operand_type_check (i
.types
[1], imm
)))
2845 /* The order of the immediates should be reversed
2846 for 2 immediates extrq and insertq instructions */
2847 if (i
.imm_operands
== 2
2848 && (strcmp (mnemonic
, "extrq") == 0
2849 || strcmp (mnemonic
, "insertq") == 0))
2850 swap_2_operands (0, 1);
2855 /* Don't optimize displacement for movabs since it only takes 64bit
2858 && (flag_code
!= CODE_64BIT
2859 || strcmp (mnemonic
, "movabs") != 0))
2862 /* Next, we find a template that matches the given insn,
2863 making sure the overlap of the given operands types is consistent
2864 with the template operand types. */
2866 if (!(t
= match_template ()))
2869 if (sse_check
!= sse_check_none
2870 && !i
.tm
.opcode_modifier
.noavx
2871 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2872 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2873 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2874 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2875 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2876 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2878 (sse_check
== sse_check_warning
2880 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2883 /* Zap movzx and movsx suffix. The suffix has been set from
2884 "word ptr" or "byte ptr" on the source operand in Intel syntax
2885 or extracted from mnemonic in AT&T syntax. But we'll use
2886 the destination register to choose the suffix for encoding. */
2887 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2889 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2890 there is no suffix, the default will be byte extension. */
2891 if (i
.reg_operands
!= 2
2894 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2899 if (i
.tm
.opcode_modifier
.fwait
)
2900 if (!add_prefix (FWAIT_OPCODE
))
2903 /* Check string instruction segment overrides. */
2904 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2906 if (!check_string ())
2908 i
.disp_operands
= 0;
2911 if (!process_suffix ())
2914 /* Update operand types. */
2915 for (j
= 0; j
< i
.operands
; j
++)
2916 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2918 /* Make still unresolved immediate matches conform to size of immediate
2919 given in i.suffix. */
2920 if (!finalize_imm ())
2923 if (i
.types
[0].bitfield
.imm1
)
2924 i
.imm_operands
= 0; /* kludge for shift insns. */
2926 /* We only need to check those implicit registers for instructions
2927 with 3 operands or less. */
2928 if (i
.operands
<= 3)
2929 for (j
= 0; j
< i
.operands
; j
++)
2930 if (i
.types
[j
].bitfield
.inoutportreg
2931 || i
.types
[j
].bitfield
.shiftcount
2932 || i
.types
[j
].bitfield
.acc
2933 || i
.types
[j
].bitfield
.floatacc
)
2936 /* ImmExt should be processed after SSE2AVX. */
2937 if (!i
.tm
.opcode_modifier
.sse2avx
2938 && i
.tm
.opcode_modifier
.immext
)
2941 /* For insns with operands there are more diddles to do to the opcode. */
2944 if (!process_operands ())
2947 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2949 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2950 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2953 if (i
.tm
.opcode_modifier
.vex
)
2954 build_vex_prefix (t
);
2956 /* Handle conversion of 'int $3' --> special int3 insn. */
2957 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2959 i
.tm
.base_opcode
= INT3_OPCODE
;
2963 if ((i
.tm
.opcode_modifier
.jump
2964 || i
.tm
.opcode_modifier
.jumpbyte
2965 || i
.tm
.opcode_modifier
.jumpdword
)
2966 && i
.op
[0].disps
->X_op
== O_constant
)
2968 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2969 the absolute address given by the constant. Since ix86 jumps and
2970 calls are pc relative, we need to generate a reloc. */
2971 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2972 i
.op
[0].disps
->X_op
= O_symbol
;
2975 if (i
.tm
.opcode_modifier
.rex64
)
2978 /* For 8 bit registers we need an empty rex prefix. Also if the
2979 instruction already has a prefix, we need to convert old
2980 registers to new ones. */
2982 if ((i
.types
[0].bitfield
.reg8
2983 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2984 || (i
.types
[1].bitfield
.reg8
2985 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2986 || ((i
.types
[0].bitfield
.reg8
2987 || i
.types
[1].bitfield
.reg8
)
2992 i
.rex
|= REX_OPCODE
;
2993 for (x
= 0; x
< 2; x
++)
2995 /* Look for 8 bit operand that uses old registers. */
2996 if (i
.types
[x
].bitfield
.reg8
2997 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2999 /* In case it is "hi" register, give up. */
3000 if (i
.op
[x
].regs
->reg_num
> 3)
3001 as_bad (_("can't encode register '%s%s' in an "
3002 "instruction requiring REX prefix."),
3003 register_prefix
, i
.op
[x
].regs
->reg_name
);
3005 /* Otherwise it is equivalent to the extended register.
3006 Since the encoding doesn't change this is merely
3007 cosmetic cleanup for debug output. */
3009 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3015 add_prefix (REX_OPCODE
| i
.rex
);
3017 /* We are ready to output the insn. */
3022 parse_insn (char *line
, char *mnemonic
)
3025 char *token_start
= l
;
3031 /* Non-zero if we found a prefix only acceptable with string insns. */
3032 const char *expecting_string_instruction
= NULL
;
3037 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3042 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3044 as_bad (_("no such instruction: `%s'"), token_start
);
3049 if (!is_space_char (*l
)
3050 && *l
!= END_OF_INSN
3052 || (*l
!= PREFIX_SEPARATOR
3055 as_bad (_("invalid character %s in mnemonic"),
3056 output_invalid (*l
));
3059 if (token_start
== l
)
3061 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3062 as_bad (_("expecting prefix; got nothing"));
3064 as_bad (_("expecting mnemonic; got nothing"));
3068 /* Look up instruction (or prefix) via hash table. */
3069 current_templates
= hash_find (op_hash
, mnemonic
);
3071 if (*l
!= END_OF_INSN
3072 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3073 && current_templates
3074 && current_templates
->start
->opcode_modifier
.isprefix
)
3076 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3078 as_bad ((flag_code
!= CODE_64BIT
3079 ? _("`%s' is only supported in 64-bit mode")
3080 : _("`%s' is not supported in 64-bit mode")),
3081 current_templates
->start
->name
);
3084 /* If we are in 16-bit mode, do not allow addr16 or data16.
3085 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3086 if ((current_templates
->start
->opcode_modifier
.size16
3087 || current_templates
->start
->opcode_modifier
.size32
)
3088 && flag_code
!= CODE_64BIT
3089 && (current_templates
->start
->opcode_modifier
.size32
3090 ^ (flag_code
== CODE_16BIT
)))
3092 as_bad (_("redundant %s prefix"),
3093 current_templates
->start
->name
);
3096 /* Add prefix, checking for repeated prefixes. */
3097 switch (add_prefix (current_templates
->start
->base_opcode
))
3102 expecting_string_instruction
= current_templates
->start
->name
;
3105 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3112 if (!current_templates
)
3114 /* Check if we should swap operand in encoding. */
3115 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3121 current_templates
= hash_find (op_hash
, mnemonic
);
3124 if (!current_templates
)
3127 /* See if we can get a match by trimming off a suffix. */
3130 case WORD_MNEM_SUFFIX
:
3131 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3132 i
.suffix
= SHORT_MNEM_SUFFIX
;
3134 case BYTE_MNEM_SUFFIX
:
3135 case QWORD_MNEM_SUFFIX
:
3136 i
.suffix
= mnem_p
[-1];
3138 current_templates
= hash_find (op_hash
, mnemonic
);
3140 case SHORT_MNEM_SUFFIX
:
3141 case LONG_MNEM_SUFFIX
:
3144 i
.suffix
= mnem_p
[-1];
3146 current_templates
= hash_find (op_hash
, mnemonic
);
3154 if (intel_float_operand (mnemonic
) == 1)
3155 i
.suffix
= SHORT_MNEM_SUFFIX
;
3157 i
.suffix
= LONG_MNEM_SUFFIX
;
3159 current_templates
= hash_find (op_hash
, mnemonic
);
3163 if (!current_templates
)
3165 as_bad (_("no such instruction: `%s'"), token_start
);
3170 if (current_templates
->start
->opcode_modifier
.jump
3171 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3173 /* Check for a branch hint. We allow ",pt" and ",pn" for
3174 predict taken and predict not taken respectively.
3175 I'm not sure that branch hints actually do anything on loop
3176 and jcxz insns (JumpByte) for current Pentium4 chips. They
3177 may work in the future and it doesn't hurt to accept them
3179 if (l
[0] == ',' && l
[1] == 'p')
3183 if (!add_prefix (DS_PREFIX_OPCODE
))
3187 else if (l
[2] == 'n')
3189 if (!add_prefix (CS_PREFIX_OPCODE
))
3195 /* Any other comma loses. */
3198 as_bad (_("invalid character %s in mnemonic"),
3199 output_invalid (*l
));
3203 /* Check if instruction is supported on specified architecture. */
3205 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3207 supported
|= cpu_flags_match (t
);
3208 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3212 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3214 as_bad (flag_code
== CODE_64BIT
3215 ? _("`%s' is not supported in 64-bit mode")
3216 : _("`%s' is only supported in 64-bit mode"),
3217 current_templates
->start
->name
);
3220 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3222 as_bad (_("`%s' is not supported on `%s%s'"),
3223 current_templates
->start
->name
,
3224 cpu_arch_name
? cpu_arch_name
: default_arch
,
3225 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3230 if (!cpu_arch_flags
.bitfield
.cpui386
3231 && (flag_code
!= CODE_16BIT
))
3233 as_warn (_("use .code16 to ensure correct addressing mode"));
3236 /* Check for rep/repne without a string instruction. */
3237 if (expecting_string_instruction
)
3239 static templates override
;
3241 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3242 if (t
->opcode_modifier
.isstring
)
3244 if (t
>= current_templates
->end
)
3246 as_bad (_("expecting string instruction after `%s'"),
3247 expecting_string_instruction
);
3250 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3251 if (!t
->opcode_modifier
.isstring
)
3254 current_templates
= &override
;
3261 parse_operands (char *l
, const char *mnemonic
)
3265 /* 1 if operand is pending after ','. */
3266 unsigned int expecting_operand
= 0;
3268 /* Non-zero if operand parens not balanced. */
3269 unsigned int paren_not_balanced
;
3271 while (*l
!= END_OF_INSN
)
3273 /* Skip optional white space before operand. */
3274 if (is_space_char (*l
))
3276 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3278 as_bad (_("invalid character %s before operand %d"),
3279 output_invalid (*l
),
3283 token_start
= l
; /* after white space */
3284 paren_not_balanced
= 0;
3285 while (paren_not_balanced
|| *l
!= ',')
3287 if (*l
== END_OF_INSN
)
3289 if (paren_not_balanced
)
3292 as_bad (_("unbalanced parenthesis in operand %d."),
3295 as_bad (_("unbalanced brackets in operand %d."),
3300 break; /* we are done */
3302 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3304 as_bad (_("invalid character %s in operand %d"),
3305 output_invalid (*l
),
3312 ++paren_not_balanced
;
3314 --paren_not_balanced
;
3319 ++paren_not_balanced
;
3321 --paren_not_balanced
;
3325 if (l
!= token_start
)
3326 { /* Yes, we've read in another operand. */
3327 unsigned int operand_ok
;
3328 this_operand
= i
.operands
++;
3329 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3330 if (i
.operands
> MAX_OPERANDS
)
3332 as_bad (_("spurious operands; (%d operands/instruction max)"),
3336 /* Now parse operand adding info to 'i' as we go along. */
3337 END_STRING_AND_SAVE (l
);
3341 i386_intel_operand (token_start
,
3342 intel_float_operand (mnemonic
));
3344 operand_ok
= i386_att_operand (token_start
);
3346 RESTORE_END_STRING (l
);
3352 if (expecting_operand
)
3354 expecting_operand_after_comma
:
3355 as_bad (_("expecting operand after ','; got nothing"));
3360 as_bad (_("expecting operand before ','; got nothing"));
3365 /* Now *l must be either ',' or END_OF_INSN. */
3368 if (*++l
== END_OF_INSN
)
3370 /* Just skip it, if it's \n complain. */
3371 goto expecting_operand_after_comma
;
3373 expecting_operand
= 1;
3380 swap_2_operands (int xchg1
, int xchg2
)
3382 union i386_op temp_op
;
3383 i386_operand_type temp_type
;
3384 enum bfd_reloc_code_real temp_reloc
;
3386 temp_type
= i
.types
[xchg2
];
3387 i
.types
[xchg2
] = i
.types
[xchg1
];
3388 i
.types
[xchg1
] = temp_type
;
3389 temp_op
= i
.op
[xchg2
];
3390 i
.op
[xchg2
] = i
.op
[xchg1
];
3391 i
.op
[xchg1
] = temp_op
;
3392 temp_reloc
= i
.reloc
[xchg2
];
3393 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3394 i
.reloc
[xchg1
] = temp_reloc
;
3398 swap_operands (void)
3404 swap_2_operands (1, i
.operands
- 2);
3407 swap_2_operands (0, i
.operands
- 1);
3413 if (i
.mem_operands
== 2)
3415 const seg_entry
*temp_seg
;
3416 temp_seg
= i
.seg
[0];
3417 i
.seg
[0] = i
.seg
[1];
3418 i
.seg
[1] = temp_seg
;
3422 /* Try to ensure constant immediates are represented in the smallest
3427 char guess_suffix
= 0;
3431 guess_suffix
= i
.suffix
;
3432 else if (i
.reg_operands
)
3434 /* Figure out a suffix from the last register operand specified.
3435 We can't do this properly yet, ie. excluding InOutPortReg,
3436 but the following works for instructions with immediates.
3437 In any case, we can't set i.suffix yet. */
3438 for (op
= i
.operands
; --op
>= 0;)
3439 if (i
.types
[op
].bitfield
.reg8
)
3441 guess_suffix
= BYTE_MNEM_SUFFIX
;
3444 else if (i
.types
[op
].bitfield
.reg16
)
3446 guess_suffix
= WORD_MNEM_SUFFIX
;
3449 else if (i
.types
[op
].bitfield
.reg32
)
3451 guess_suffix
= LONG_MNEM_SUFFIX
;
3454 else if (i
.types
[op
].bitfield
.reg64
)
3456 guess_suffix
= QWORD_MNEM_SUFFIX
;
3460 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3461 guess_suffix
= WORD_MNEM_SUFFIX
;
3463 for (op
= i
.operands
; --op
>= 0;)
3464 if (operand_type_check (i
.types
[op
], imm
))
3466 switch (i
.op
[op
].imms
->X_op
)
3469 /* If a suffix is given, this operand may be shortened. */
3470 switch (guess_suffix
)
3472 case LONG_MNEM_SUFFIX
:
3473 i
.types
[op
].bitfield
.imm32
= 1;
3474 i
.types
[op
].bitfield
.imm64
= 1;
3476 case WORD_MNEM_SUFFIX
:
3477 i
.types
[op
].bitfield
.imm16
= 1;
3478 i
.types
[op
].bitfield
.imm32
= 1;
3479 i
.types
[op
].bitfield
.imm32s
= 1;
3480 i
.types
[op
].bitfield
.imm64
= 1;
3482 case BYTE_MNEM_SUFFIX
:
3483 i
.types
[op
].bitfield
.imm8
= 1;
3484 i
.types
[op
].bitfield
.imm8s
= 1;
3485 i
.types
[op
].bitfield
.imm16
= 1;
3486 i
.types
[op
].bitfield
.imm32
= 1;
3487 i
.types
[op
].bitfield
.imm32s
= 1;
3488 i
.types
[op
].bitfield
.imm64
= 1;
3492 /* If this operand is at most 16 bits, convert it
3493 to a signed 16 bit number before trying to see
3494 whether it will fit in an even smaller size.
3495 This allows a 16-bit operand such as $0xffe0 to
3496 be recognised as within Imm8S range. */
3497 if ((i
.types
[op
].bitfield
.imm16
)
3498 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3500 i
.op
[op
].imms
->X_add_number
=
3501 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3503 if ((i
.types
[op
].bitfield
.imm32
)
3504 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3507 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3508 ^ ((offsetT
) 1 << 31))
3509 - ((offsetT
) 1 << 31));
3512 = operand_type_or (i
.types
[op
],
3513 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3515 /* We must avoid matching of Imm32 templates when 64bit
3516 only immediate is available. */
3517 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3518 i
.types
[op
].bitfield
.imm32
= 0;
3525 /* Symbols and expressions. */
3527 /* Convert symbolic operand to proper sizes for matching, but don't
3528 prevent matching a set of insns that only supports sizes other
3529 than those matching the insn suffix. */
3531 i386_operand_type mask
, allowed
;
3534 operand_type_set (&mask
, 0);
3535 operand_type_set (&allowed
, 0);
3537 for (t
= current_templates
->start
;
3538 t
< current_templates
->end
;
3540 allowed
= operand_type_or (allowed
,
3541 t
->operand_types
[op
]);
3542 switch (guess_suffix
)
3544 case QWORD_MNEM_SUFFIX
:
3545 mask
.bitfield
.imm64
= 1;
3546 mask
.bitfield
.imm32s
= 1;
3548 case LONG_MNEM_SUFFIX
:
3549 mask
.bitfield
.imm32
= 1;
3551 case WORD_MNEM_SUFFIX
:
3552 mask
.bitfield
.imm16
= 1;
3554 case BYTE_MNEM_SUFFIX
:
3555 mask
.bitfield
.imm8
= 1;
3560 allowed
= operand_type_and (mask
, allowed
);
3561 if (!operand_type_all_zero (&allowed
))
3562 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3569 /* Try to use the smallest displacement type too. */
3571 optimize_disp (void)
3575 for (op
= i
.operands
; --op
>= 0;)
3576 if (operand_type_check (i
.types
[op
], disp
))
3578 if (i
.op
[op
].disps
->X_op
== O_constant
)
3580 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3582 if (i
.types
[op
].bitfield
.disp16
3583 && (disp
& ~(offsetT
) 0xffff) == 0)
3585 /* If this operand is at most 16 bits, convert
3586 to a signed 16 bit number and don't use 64bit
3588 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3589 i
.types
[op
].bitfield
.disp64
= 0;
3591 if (i
.types
[op
].bitfield
.disp32
3592 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3594 /* If this operand is at most 32 bits, convert
3595 to a signed 32 bit number and don't use 64bit
3597 disp
&= (((offsetT
) 2 << 31) - 1);
3598 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3599 i
.types
[op
].bitfield
.disp64
= 0;
3601 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3603 i
.types
[op
].bitfield
.disp8
= 0;
3604 i
.types
[op
].bitfield
.disp16
= 0;
3605 i
.types
[op
].bitfield
.disp32
= 0;
3606 i
.types
[op
].bitfield
.disp32s
= 0;
3607 i
.types
[op
].bitfield
.disp64
= 0;
3611 else if (flag_code
== CODE_64BIT
)
3613 if (fits_in_signed_long (disp
))
3615 i
.types
[op
].bitfield
.disp64
= 0;
3616 i
.types
[op
].bitfield
.disp32s
= 1;
3618 if (fits_in_unsigned_long (disp
))
3619 i
.types
[op
].bitfield
.disp32
= 1;
3621 if ((i
.types
[op
].bitfield
.disp32
3622 || i
.types
[op
].bitfield
.disp32s
3623 || i
.types
[op
].bitfield
.disp16
)
3624 && fits_in_signed_byte (disp
))
3625 i
.types
[op
].bitfield
.disp8
= 1;
3627 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3628 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3630 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3631 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3632 i
.types
[op
].bitfield
.disp8
= 0;
3633 i
.types
[op
].bitfield
.disp16
= 0;
3634 i
.types
[op
].bitfield
.disp32
= 0;
3635 i
.types
[op
].bitfield
.disp32s
= 0;
3636 i
.types
[op
].bitfield
.disp64
= 0;
3639 /* We only support 64bit displacement on constants. */
3640 i
.types
[op
].bitfield
.disp64
= 0;
3644 static const template *
3645 match_template (void)
3647 /* Points to template once we've found it. */
3649 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3650 i386_operand_type overlap4
;
3651 unsigned int found_reverse_match
;
3652 i386_opcode_modifier suffix_check
;
3653 i386_operand_type operand_types
[MAX_OPERANDS
];
3654 int addr_prefix_disp
;
3656 unsigned int found_cpu_match
;
3657 unsigned int check_register
;
3659 #if MAX_OPERANDS != 5
3660 # error "MAX_OPERANDS must be 5."
3663 found_reverse_match
= 0;
3664 addr_prefix_disp
= -1;
3666 memset (&suffix_check
, 0, sizeof (suffix_check
));
3667 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3668 suffix_check
.no_bsuf
= 1;
3669 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3670 suffix_check
.no_wsuf
= 1;
3671 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3672 suffix_check
.no_ssuf
= 1;
3673 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3674 suffix_check
.no_lsuf
= 1;
3675 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3676 suffix_check
.no_qsuf
= 1;
3677 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3678 suffix_check
.no_ldsuf
= 1;
3680 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3682 addr_prefix_disp
= -1;
3684 /* Must have right number of operands. */
3685 if (i
.operands
!= t
->operands
)
3688 /* Check processor support. */
3689 found_cpu_match
= (cpu_flags_match (t
)
3690 == CPU_FLAGS_PERFECT_MATCH
);
3691 if (!found_cpu_match
)
3694 /* Check old gcc support. */
3695 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3698 /* Check AT&T mnemonic. */
3699 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3702 /* Check AT&T syntax Intel syntax. */
3703 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3704 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3707 /* Check the suffix, except for some instructions in intel mode. */
3708 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3709 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3710 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3711 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3712 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3713 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3714 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3717 if (!operand_size_match (t
))
3720 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3721 operand_types
[j
] = t
->operand_types
[j
];
3723 /* In general, don't allow 64-bit operands in 32-bit mode. */
3724 if (i
.suffix
== QWORD_MNEM_SUFFIX
3725 && flag_code
!= CODE_64BIT
3727 ? (!t
->opcode_modifier
.ignoresize
3728 && !intel_float_operand (t
->name
))
3729 : intel_float_operand (t
->name
) != 2)
3730 && ((!operand_types
[0].bitfield
.regmmx
3731 && !operand_types
[0].bitfield
.regxmm
3732 && !operand_types
[0].bitfield
.regymm
)
3733 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3734 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3735 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3736 && (t
->base_opcode
!= 0x0fc7
3737 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3740 /* In general, don't allow 32-bit operands on pre-386. */
3741 else if (i
.suffix
== LONG_MNEM_SUFFIX
3742 && !cpu_arch_flags
.bitfield
.cpui386
3744 ? (!t
->opcode_modifier
.ignoresize
3745 && !intel_float_operand (t
->name
))
3746 : intel_float_operand (t
->name
) != 2)
3747 && ((!operand_types
[0].bitfield
.regmmx
3748 && !operand_types
[0].bitfield
.regxmm
)
3749 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3750 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3753 /* Do not verify operands when there are none. */
3757 /* We've found a match; break out of loop. */
3761 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3762 into Disp32/Disp16/Disp32 operand. */
3763 if (i
.prefix
[ADDR_PREFIX
] != 0)
3765 /* There should be only one Disp operand. */
3769 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3771 if (operand_types
[j
].bitfield
.disp16
)
3773 addr_prefix_disp
= j
;
3774 operand_types
[j
].bitfield
.disp32
= 1;
3775 operand_types
[j
].bitfield
.disp16
= 0;
3781 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3783 if (operand_types
[j
].bitfield
.disp32
)
3785 addr_prefix_disp
= j
;
3786 operand_types
[j
].bitfield
.disp32
= 0;
3787 operand_types
[j
].bitfield
.disp16
= 1;
3793 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3795 if (operand_types
[j
].bitfield
.disp64
)
3797 addr_prefix_disp
= j
;
3798 operand_types
[j
].bitfield
.disp64
= 0;
3799 operand_types
[j
].bitfield
.disp32
= 1;
3807 /* We check register size only if size of operands can be
3808 encoded the canonical way. */
3809 check_register
= t
->opcode_modifier
.w
;
3810 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3811 switch (t
->operands
)
3814 if (!operand_type_match (overlap0
, i
.types
[0]))
3818 /* xchg %eax, %eax is a special case. It is an aliase for nop
3819 only in 32bit mode and we can use opcode 0x90. In 64bit
3820 mode, we can't use 0x90 for xchg %eax, %eax since it should
3821 zero-extend %eax to %rax. */
3822 if (flag_code
== CODE_64BIT
3823 && t
->base_opcode
== 0x90
3824 && operand_type_equal (&i
.types
[0], &acc32
)
3825 && operand_type_equal (&i
.types
[1], &acc32
))
3829 /* If we swap operand in encoding, we either match
3830 the next one or reverse direction of operands. */
3831 if (t
->opcode_modifier
.s
)
3833 else if (t
->opcode_modifier
.d
)
3838 /* If we swap operand in encoding, we match the next one. */
3839 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3843 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3844 if (!operand_type_match (overlap0
, i
.types
[0])
3845 || !operand_type_match (overlap1
, i
.types
[1])
3847 && !operand_type_register_match (overlap0
, i
.types
[0],
3849 overlap1
, i
.types
[1],
3852 /* Check if other direction is valid ... */
3853 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3857 /* Try reversing direction of operands. */
3858 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3859 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3860 if (!operand_type_match (overlap0
, i
.types
[0])
3861 || !operand_type_match (overlap1
, i
.types
[1])
3863 && !operand_type_register_match (overlap0
,
3870 /* Does not match either direction. */
3873 /* found_reverse_match holds which of D or FloatDR
3875 if (t
->opcode_modifier
.d
)
3876 found_reverse_match
= Opcode_D
;
3877 else if (t
->opcode_modifier
.floatd
)
3878 found_reverse_match
= Opcode_FloatD
;
3880 found_reverse_match
= 0;
3881 if (t
->opcode_modifier
.floatr
)
3882 found_reverse_match
|= Opcode_FloatR
;
3886 /* Found a forward 2 operand match here. */
3887 switch (t
->operands
)
3890 overlap4
= operand_type_and (i
.types
[4],
3893 overlap3
= operand_type_and (i
.types
[3],
3896 overlap2
= operand_type_and (i
.types
[2],
3901 switch (t
->operands
)
3904 if (!operand_type_match (overlap4
, i
.types
[4])
3905 || !operand_type_register_match (overlap3
,
3913 if (!operand_type_match (overlap3
, i
.types
[3])
3915 && !operand_type_register_match (overlap2
,
3923 /* Here we make use of the fact that there are no
3924 reverse match 3 operand instructions, and all 3
3925 operand instructions only need to be checked for
3926 register consistency between operands 2 and 3. */
3927 if (!operand_type_match (overlap2
, i
.types
[2])
3929 && !operand_type_register_match (overlap1
,
3939 /* Found either forward/reverse 2, 3 or 4 operand match here:
3940 slip through to break. */
3942 if (!found_cpu_match
)
3944 found_reverse_match
= 0;
3948 /* We've found a match; break out of loop. */
3952 if (t
== current_templates
->end
)
3954 /* We found no match. */
3956 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3957 current_templates
->start
->name
);
3959 as_bad (_("suffix or operands invalid for `%s'"),
3960 current_templates
->start
->name
);
3964 if (!quiet_warnings
)
3967 && (i
.types
[0].bitfield
.jumpabsolute
3968 != operand_types
[0].bitfield
.jumpabsolute
))
3970 as_warn (_("indirect %s without `*'"), t
->name
);
3973 if (t
->opcode_modifier
.isprefix
3974 && t
->opcode_modifier
.ignoresize
)
3976 /* Warn them that a data or address size prefix doesn't
3977 affect assembly of the next line of code. */
3978 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3982 /* Copy the template we found. */
3985 if (addr_prefix_disp
!= -1)
3986 i
.tm
.operand_types
[addr_prefix_disp
]
3987 = operand_types
[addr_prefix_disp
];
3989 if (found_reverse_match
)
3991 /* If we found a reverse match we must alter the opcode
3992 direction bit. found_reverse_match holds bits to change
3993 (different for int & float insns). */
3995 i
.tm
.base_opcode
^= found_reverse_match
;
3997 i
.tm
.operand_types
[0] = operand_types
[1];
3998 i
.tm
.operand_types
[1] = operand_types
[0];
4007 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4008 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4010 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4012 as_bad (_("`%s' operand %d must use `%ses' segment"),
4018 /* There's only ever one segment override allowed per instruction.
4019 This instruction possibly has a legal segment override on the
4020 second operand, so copy the segment to where non-string
4021 instructions store it, allowing common code. */
4022 i
.seg
[0] = i
.seg
[1];
4024 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4026 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4028 as_bad (_("`%s' operand %d must use `%ses' segment"),
4039 process_suffix (void)
4041 /* If matched instruction specifies an explicit instruction mnemonic
4043 if (i
.tm
.opcode_modifier
.size16
)
4044 i
.suffix
= WORD_MNEM_SUFFIX
;
4045 else if (i
.tm
.opcode_modifier
.size32
)
4046 i
.suffix
= LONG_MNEM_SUFFIX
;
4047 else if (i
.tm
.opcode_modifier
.size64
)
4048 i
.suffix
= QWORD_MNEM_SUFFIX
;
4049 else if (i
.reg_operands
)
4051 /* If there's no instruction mnemonic suffix we try to invent one
4052 based on register operands. */
4055 /* We take i.suffix from the last register operand specified,
4056 Destination register type is more significant than source
4057 register type. crc32 in SSE4.2 prefers source register
4059 if (i
.tm
.base_opcode
== 0xf20f38f1)
4061 if (i
.types
[0].bitfield
.reg16
)
4062 i
.suffix
= WORD_MNEM_SUFFIX
;
4063 else if (i
.types
[0].bitfield
.reg32
)
4064 i
.suffix
= LONG_MNEM_SUFFIX
;
4065 else if (i
.types
[0].bitfield
.reg64
)
4066 i
.suffix
= QWORD_MNEM_SUFFIX
;
4068 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4070 if (i
.types
[0].bitfield
.reg8
)
4071 i
.suffix
= BYTE_MNEM_SUFFIX
;
4078 if (i
.tm
.base_opcode
== 0xf20f38f1
4079 || i
.tm
.base_opcode
== 0xf20f38f0)
4081 /* We have to know the operand size for crc32. */
4082 as_bad (_("ambiguous memory operand size for `%s`"),
4087 for (op
= i
.operands
; --op
>= 0;)
4088 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4090 if (i
.types
[op
].bitfield
.reg8
)
4092 i
.suffix
= BYTE_MNEM_SUFFIX
;
4095 else if (i
.types
[op
].bitfield
.reg16
)
4097 i
.suffix
= WORD_MNEM_SUFFIX
;
4100 else if (i
.types
[op
].bitfield
.reg32
)
4102 i
.suffix
= LONG_MNEM_SUFFIX
;
4105 else if (i
.types
[op
].bitfield
.reg64
)
4107 i
.suffix
= QWORD_MNEM_SUFFIX
;
4113 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4115 if (!check_byte_reg ())
4118 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4120 if (!check_long_reg ())
4123 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4126 && i
.tm
.opcode_modifier
.ignoresize
4127 && i
.tm
.opcode_modifier
.no_qsuf
)
4129 else if (!check_qword_reg ())
4132 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4134 if (!check_word_reg ())
4137 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4138 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4140 /* Skip if the instruction has x/y suffix. match_template
4141 should check if it is a valid suffix. */
4143 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4144 /* Do nothing if the instruction is going to ignore the prefix. */
4149 else if (i
.tm
.opcode_modifier
.defaultsize
4151 /* exclude fldenv/frstor/fsave/fstenv */
4152 && i
.tm
.opcode_modifier
.no_ssuf
)
4154 i
.suffix
= stackop_size
;
4156 else if (intel_syntax
4158 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4159 || i
.tm
.opcode_modifier
.jumpbyte
4160 || i
.tm
.opcode_modifier
.jumpintersegment
4161 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4162 && i
.tm
.extension_opcode
<= 3)))
4167 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4169 i
.suffix
= QWORD_MNEM_SUFFIX
;
4173 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4174 i
.suffix
= LONG_MNEM_SUFFIX
;
4177 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4178 i
.suffix
= WORD_MNEM_SUFFIX
;
4187 if (i
.tm
.opcode_modifier
.w
)
4189 as_bad (_("no instruction mnemonic suffix given and "
4190 "no register operands; can't size instruction"));
4196 unsigned int suffixes
;
4198 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4199 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4201 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4203 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4205 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4207 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4210 /* There are more than suffix matches. */
4211 if (i
.tm
.opcode_modifier
.w
4212 || ((suffixes
& (suffixes
- 1))
4213 && !i
.tm
.opcode_modifier
.defaultsize
4214 && !i
.tm
.opcode_modifier
.ignoresize
))
4216 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4222 /* Change the opcode based on the operand size given by i.suffix;
4223 We don't need to change things for byte insns. */
4226 && i
.suffix
!= BYTE_MNEM_SUFFIX
4227 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4228 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4230 /* It's not a byte, select word/dword operation. */
4231 if (i
.tm
.opcode_modifier
.w
)
4233 if (i
.tm
.opcode_modifier
.shortform
)
4234 i
.tm
.base_opcode
|= 8;
4236 i
.tm
.base_opcode
|= 1;
4239 /* Now select between word & dword operations via the operand
4240 size prefix, except for instructions that will ignore this
4242 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4244 /* The address size override prefix changes the size of the
4246 if ((flag_code
== CODE_32BIT
4247 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4248 || (flag_code
!= CODE_32BIT
4249 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4250 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4253 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4254 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4255 && !i
.tm
.opcode_modifier
.ignoresize
4256 && !i
.tm
.opcode_modifier
.floatmf
4257 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4258 || (flag_code
== CODE_64BIT
4259 && i
.tm
.opcode_modifier
.jumpbyte
)))
4261 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4263 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4264 prefix
= ADDR_PREFIX_OPCODE
;
4266 if (!add_prefix (prefix
))
4270 /* Set mode64 for an operand. */
4271 if (i
.suffix
== QWORD_MNEM_SUFFIX
4272 && flag_code
== CODE_64BIT
4273 && !i
.tm
.opcode_modifier
.norex64
)
4275 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4276 need rex64. cmpxchg8b is also a special case. */
4277 if (! (i
.operands
== 2
4278 && i
.tm
.base_opcode
== 0x90
4279 && i
.tm
.extension_opcode
== None
4280 && operand_type_equal (&i
.types
[0], &acc64
)
4281 && operand_type_equal (&i
.types
[1], &acc64
))
4282 && ! (i
.operands
== 1
4283 && i
.tm
.base_opcode
== 0xfc7
4284 && i
.tm
.extension_opcode
== 1
4285 && !operand_type_check (i
.types
[0], reg
)
4286 && operand_type_check (i
.types
[0], anymem
)))
4290 /* Size floating point instruction. */
4291 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4292 if (i
.tm
.opcode_modifier
.floatmf
)
4293 i
.tm
.base_opcode
^= 4;
4300 check_byte_reg (void)
4304 for (op
= i
.operands
; --op
>= 0;)
4306 /* If this is an eight bit register, it's OK. If it's the 16 or
4307 32 bit version of an eight bit register, we will just use the
4308 low portion, and that's OK too. */
4309 if (i
.types
[op
].bitfield
.reg8
)
4312 /* Don't generate this warning if not needed. */
4313 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4316 /* crc32 doesn't generate this warning. */
4317 if (i
.tm
.base_opcode
== 0xf20f38f0)
4320 if ((i
.types
[op
].bitfield
.reg16
4321 || i
.types
[op
].bitfield
.reg32
4322 || i
.types
[op
].bitfield
.reg64
)
4323 && i
.op
[op
].regs
->reg_num
< 4)
4325 /* Prohibit these changes in the 64bit mode, since the
4326 lowering is more complicated. */
4327 if (flag_code
== CODE_64BIT
4328 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4330 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4331 register_prefix
, i
.op
[op
].regs
->reg_name
,
4335 #if REGISTER_WARNINGS
4337 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4338 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4340 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4341 ? REGNAM_AL
- REGNAM_AX
4342 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4344 i
.op
[op
].regs
->reg_name
,
4349 /* Any other register is bad. */
4350 if (i
.types
[op
].bitfield
.reg16
4351 || i
.types
[op
].bitfield
.reg32
4352 || i
.types
[op
].bitfield
.reg64
4353 || i
.types
[op
].bitfield
.regmmx
4354 || i
.types
[op
].bitfield
.regxmm
4355 || i
.types
[op
].bitfield
.regymm
4356 || i
.types
[op
].bitfield
.sreg2
4357 || i
.types
[op
].bitfield
.sreg3
4358 || i
.types
[op
].bitfield
.control
4359 || i
.types
[op
].bitfield
.debug
4360 || i
.types
[op
].bitfield
.test
4361 || i
.types
[op
].bitfield
.floatreg
4362 || i
.types
[op
].bitfield
.floatacc
)
4364 as_bad (_("`%s%s' not allowed with `%s%c'"),
4366 i
.op
[op
].regs
->reg_name
,
4376 check_long_reg (void)
4380 for (op
= i
.operands
; --op
>= 0;)
4381 /* Reject eight bit registers, except where the template requires
4382 them. (eg. movzb) */
4383 if (i
.types
[op
].bitfield
.reg8
4384 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4385 || i
.tm
.operand_types
[op
].bitfield
.reg32
4386 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4388 as_bad (_("`%s%s' not allowed with `%s%c'"),
4390 i
.op
[op
].regs
->reg_name
,
4395 /* Warn if the e prefix on a general reg is missing. */
4396 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4397 && i
.types
[op
].bitfield
.reg16
4398 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4399 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4401 /* Prohibit these changes in the 64bit mode, since the
4402 lowering is more complicated. */
4403 if (flag_code
== CODE_64BIT
)
4405 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4406 register_prefix
, i
.op
[op
].regs
->reg_name
,
4410 #if REGISTER_WARNINGS
4412 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4414 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4416 i
.op
[op
].regs
->reg_name
,
4420 /* Warn if the r prefix on a general reg is missing. */
4421 else if (i
.types
[op
].bitfield
.reg64
4422 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4423 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4426 && i
.tm
.opcode_modifier
.toqword
4427 && !i
.types
[0].bitfield
.regxmm
)
4429 /* Convert to QWORD. We want REX byte. */
4430 i
.suffix
= QWORD_MNEM_SUFFIX
;
4434 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4435 register_prefix
, i
.op
[op
].regs
->reg_name
,
4444 check_qword_reg (void)
4448 for (op
= i
.operands
; --op
>= 0; )
4449 /* Reject eight bit registers, except where the template requires
4450 them. (eg. movzb) */
4451 if (i
.types
[op
].bitfield
.reg8
4452 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4453 || i
.tm
.operand_types
[op
].bitfield
.reg32
4454 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4456 as_bad (_("`%s%s' not allowed with `%s%c'"),
4458 i
.op
[op
].regs
->reg_name
,
4463 /* Warn if the e prefix on a general reg is missing. */
4464 else if ((i
.types
[op
].bitfield
.reg16
4465 || i
.types
[op
].bitfield
.reg32
)
4466 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4467 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4469 /* Prohibit these changes in the 64bit mode, since the
4470 lowering is more complicated. */
4472 && i
.tm
.opcode_modifier
.todword
4473 && !i
.types
[0].bitfield
.regxmm
)
4475 /* Convert to DWORD. We don't want REX byte. */
4476 i
.suffix
= LONG_MNEM_SUFFIX
;
4480 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4481 register_prefix
, i
.op
[op
].regs
->reg_name
,
4490 check_word_reg (void)
4493 for (op
= i
.operands
; --op
>= 0;)
4494 /* Reject eight bit registers, except where the template requires
4495 them. (eg. movzb) */
4496 if (i
.types
[op
].bitfield
.reg8
4497 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4498 || i
.tm
.operand_types
[op
].bitfield
.reg32
4499 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4501 as_bad (_("`%s%s' not allowed with `%s%c'"),
4503 i
.op
[op
].regs
->reg_name
,
4508 /* Warn if the e prefix on a general reg is present. */
4509 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4510 && i
.types
[op
].bitfield
.reg32
4511 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4512 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4514 /* Prohibit these changes in the 64bit mode, since the
4515 lowering is more complicated. */
4516 if (flag_code
== CODE_64BIT
)
4518 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4519 register_prefix
, i
.op
[op
].regs
->reg_name
,
4524 #if REGISTER_WARNINGS
4525 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4527 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4529 i
.op
[op
].regs
->reg_name
,
4537 update_imm (unsigned int j
)
4539 i386_operand_type overlap
= i
.types
[j
];
4540 if ((overlap
.bitfield
.imm8
4541 || overlap
.bitfield
.imm8s
4542 || overlap
.bitfield
.imm16
4543 || overlap
.bitfield
.imm32
4544 || overlap
.bitfield
.imm32s
4545 || overlap
.bitfield
.imm64
)
4546 && !operand_type_equal (&overlap
, &imm8
)
4547 && !operand_type_equal (&overlap
, &imm8s
)
4548 && !operand_type_equal (&overlap
, &imm16
)
4549 && !operand_type_equal (&overlap
, &imm32
)
4550 && !operand_type_equal (&overlap
, &imm32s
)
4551 && !operand_type_equal (&overlap
, &imm64
))
4555 i386_operand_type temp
;
4557 operand_type_set (&temp
, 0);
4558 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4560 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4561 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4563 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4564 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4565 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4567 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4568 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4571 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4574 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4575 || operand_type_equal (&overlap
, &imm16_32
)
4576 || operand_type_equal (&overlap
, &imm16_32s
))
4578 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4583 if (!operand_type_equal (&overlap
, &imm8
)
4584 && !operand_type_equal (&overlap
, &imm8s
)
4585 && !operand_type_equal (&overlap
, &imm16
)
4586 && !operand_type_equal (&overlap
, &imm32
)
4587 && !operand_type_equal (&overlap
, &imm32s
)
4588 && !operand_type_equal (&overlap
, &imm64
))
4590 as_bad (_("no instruction mnemonic suffix given; "
4591 "can't determine immediate size"));
4595 i
.types
[j
] = overlap
;
4605 /* Update the first 2 immediate operands. */
4606 n
= i
.operands
> 2 ? 2 : i
.operands
;
4609 for (j
= 0; j
< n
; j
++)
4610 if (update_imm (j
) == 0)
4613 /* The 3rd operand can't be immediate operand. */
4614 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4621 bad_implicit_operand (int xmm
)
4623 const char *reg
= xmm
? "xmm0" : "ymm0";
4625 as_bad (_("the last operand of `%s' must be `%s%s'"),
4626 i
.tm
.name
, register_prefix
, reg
);
4628 as_bad (_("the first operand of `%s' must be `%s%s'"),
4629 i
.tm
.name
, register_prefix
, reg
);
4634 process_operands (void)
4636 /* Default segment register this instruction will use for memory
4637 accesses. 0 means unknown. This is only for optimizing out
4638 unnecessary segment overrides. */
4639 const seg_entry
*default_seg
= 0;
4641 if (i
.tm
.opcode_modifier
.sse2avx
4642 && (i
.tm
.opcode_modifier
.vexnds
4643 || i
.tm
.opcode_modifier
.vexndd
))
4645 unsigned int dup
= i
.operands
;
4646 unsigned int dest
= dup
- 1;
4649 /* The destination must be an xmm register. */
4650 gas_assert (i
.reg_operands
4651 && MAX_OPERANDS
> dup
4652 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4654 if (i
.tm
.opcode_modifier
.firstxmm0
)
4656 /* The first operand is implicit and must be xmm0. */
4657 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4658 if (i
.op
[0].regs
->reg_num
!= 0)
4659 return bad_implicit_operand (1);
4661 if (i
.tm
.opcode_modifier
.vex3sources
)
4663 /* Keep xmm0 for instructions with VEX prefix and 3
4669 /* We remove the first xmm0 and keep the number of
4670 operands unchanged, which in fact duplicates the
4672 for (j
= 1; j
< i
.operands
; j
++)
4674 i
.op
[j
- 1] = i
.op
[j
];
4675 i
.types
[j
- 1] = i
.types
[j
];
4676 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4680 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4682 gas_assert ((MAX_OPERANDS
- 1) > dup
4683 && i
.tm
.opcode_modifier
.vex3sources
);
4685 /* Add the implicit xmm0 for instructions with VEX prefix
4687 for (j
= i
.operands
; j
> 0; j
--)
4689 i
.op
[j
] = i
.op
[j
- 1];
4690 i
.types
[j
] = i
.types
[j
- 1];
4691 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4694 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4695 i
.types
[0] = regxmm
;
4696 i
.tm
.operand_types
[0] = regxmm
;
4699 i
.reg_operands
+= 2;
4704 i
.op
[dup
] = i
.op
[dest
];
4705 i
.types
[dup
] = i
.types
[dest
];
4706 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4715 i
.op
[dup
] = i
.op
[dest
];
4716 i
.types
[dup
] = i
.types
[dest
];
4717 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4720 if (i
.tm
.opcode_modifier
.immext
)
4723 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4727 /* The first operand is implicit and must be xmm0/ymm0. */
4728 gas_assert (i
.reg_operands
4729 && (operand_type_equal (&i
.types
[0], ®xmm
)
4730 || operand_type_equal (&i
.types
[0], ®ymm
)));
4731 if (i
.op
[0].regs
->reg_num
!= 0)
4732 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4734 for (j
= 1; j
< i
.operands
; j
++)
4736 i
.op
[j
- 1] = i
.op
[j
];
4737 i
.types
[j
- 1] = i
.types
[j
];
4739 /* We need to adjust fields in i.tm since they are used by
4740 build_modrm_byte. */
4741 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4748 else if (i
.tm
.opcode_modifier
.regkludge
)
4750 /* The imul $imm, %reg instruction is converted into
4751 imul $imm, %reg, %reg, and the clr %reg instruction
4752 is converted into xor %reg, %reg. */
4754 unsigned int first_reg_op
;
4756 if (operand_type_check (i
.types
[0], reg
))
4760 /* Pretend we saw the extra register operand. */
4761 gas_assert (i
.reg_operands
== 1
4762 && i
.op
[first_reg_op
+ 1].regs
== 0);
4763 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4764 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4769 if (i
.tm
.opcode_modifier
.shortform
)
4771 if (i
.types
[0].bitfield
.sreg2
4772 || i
.types
[0].bitfield
.sreg3
)
4774 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4775 && i
.op
[0].regs
->reg_num
== 1)
4777 as_bad (_("you can't `pop %scs'"), register_prefix
);
4780 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4781 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4786 /* The register or float register operand is in operand
4790 if (i
.types
[0].bitfield
.floatreg
4791 || operand_type_check (i
.types
[0], reg
))
4795 /* Register goes in low 3 bits of opcode. */
4796 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4797 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4799 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4801 /* Warn about some common errors, but press on regardless.
4802 The first case can be generated by gcc (<= 2.8.1). */
4803 if (i
.operands
== 2)
4805 /* Reversed arguments on faddp, fsubp, etc. */
4806 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4807 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4808 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4812 /* Extraneous `l' suffix on fp insn. */
4813 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4814 register_prefix
, i
.op
[0].regs
->reg_name
);
4819 else if (i
.tm
.opcode_modifier
.modrm
)
4821 /* The opcode is completed (modulo i.tm.extension_opcode which
4822 must be put into the modrm byte). Now, we make the modrm and
4823 index base bytes based on all the info we've collected. */
4825 default_seg
= build_modrm_byte ();
4827 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4831 else if (i
.tm
.opcode_modifier
.isstring
)
4833 /* For the string instructions that allow a segment override
4834 on one of their operands, the default segment is ds. */
4838 if (i
.tm
.base_opcode
== 0x8d /* lea */
4841 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4843 /* If a segment was explicitly specified, and the specified segment
4844 is not the default, use an opcode prefix to select it. If we
4845 never figured out what the default segment is, then default_seg
4846 will be zero at this point, and the specified segment prefix will
4848 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4850 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4856 static const seg_entry
*
4857 build_modrm_byte (void)
4859 const seg_entry
*default_seg
= 0;
4860 unsigned int source
, dest
;
4863 /* The first operand of instructions with VEX prefix and 3 sources
4864 must be VEX_Imm4. */
4865 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4868 unsigned int nds
, reg
;
4870 if (i
.tm
.opcode_modifier
.veximmext
4871 && i
.tm
.opcode_modifier
.immext
)
4873 dest
= i
.operands
- 2;
4874 gas_assert (dest
== 3);
4877 dest
= i
.operands
- 1;
4880 /* This instruction must have 4 register operands
4881 or 3 register operands plus 1 memory operand.
4882 It must have VexNDS and VexImmExt. */
4883 gas_assert ((i
.reg_operands
== 4
4884 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4885 && i
.tm
.opcode_modifier
.vexnds
4886 && i
.tm
.opcode_modifier
.veximmext
4887 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4888 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4890 /* Generate an 8bit immediate operand to encode the register
4892 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4893 i
.op
[i
.operands
].imms
= exp
;
4894 i
.types
[i
.operands
] = imm8
;
4896 /* If VexW1 is set, the first operand is the source and
4897 the second operand is encoded in the immediate operand. */
4898 if (i
.tm
.opcode_modifier
.vexw1
)
4908 /* FMA4 swaps REG and NDS. */
4909 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4916 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4917 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4919 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4920 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4922 exp
->X_op
= O_constant
;
4924 = ((i
.op
[reg
].regs
->reg_num
4925 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4926 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4931 /* i.reg_operands MUST be the number of real register operands;
4932 implicit registers do not count. If there are 3 register
4933 operands, it must be a instruction with VexNDS. For a
4934 instruction with VexNDD, the destination register is encoded
4935 in VEX prefix. If there are 4 register operands, it must be
4936 a instruction with VEX prefix and 3 sources. */
4937 if (i
.mem_operands
== 0
4938 && ((i
.reg_operands
== 2
4939 && !i
.tm
.opcode_modifier
.vexndd
)
4940 || (i
.reg_operands
== 3
4941 && i
.tm
.opcode_modifier
.vexnds
)
4942 || (i
.reg_operands
== 4 && vex_3_sources
)))
4950 /* When there are 3 operands, one of them may be immediate,
4951 which may be the first or the last operand. Otherwise,
4952 the first operand must be shift count register (cl) or it
4953 is an instruction with VexNDS. */
4954 gas_assert (i
.imm_operands
== 1
4955 || (i
.imm_operands
== 0
4956 && (i
.tm
.opcode_modifier
.vexnds
4957 || i
.types
[0].bitfield
.shiftcount
)));
4958 if (operand_type_check (i
.types
[0], imm
)
4959 || i
.types
[0].bitfield
.shiftcount
)
4965 /* When there are 4 operands, the first two must be 8bit
4966 immediate operands. The source operand will be the 3rd
4969 For instructions with VexNDS, if the first operand
4970 an imm8, the source operand is the 2nd one. If the last
4971 operand is imm8, the source operand is the first one. */
4972 gas_assert ((i
.imm_operands
== 2
4973 && i
.types
[0].bitfield
.imm8
4974 && i
.types
[1].bitfield
.imm8
)
4975 || (i
.tm
.opcode_modifier
.vexnds
4976 && i
.imm_operands
== 1
4977 && (i
.types
[0].bitfield
.imm8
4978 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4979 if (i
.tm
.opcode_modifier
.vexnds
)
4981 if (i
.types
[0].bitfield
.imm8
)
4999 if (i
.tm
.opcode_modifier
.vexnds
)
5001 /* For instructions with VexNDS, the register-only
5002 source operand must be XMM or YMM register. It is
5003 encoded in VEX prefix. We need to clear RegMem bit
5004 before calling operand_type_equal. */
5005 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5006 op
.bitfield
.regmem
= 0;
5007 if ((dest
+ 1) >= i
.operands
5008 || (!operand_type_equal (&op
, ®xmm
)
5009 && !operand_type_equal (&op
, ®ymm
)))
5011 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5017 /* One of the register operands will be encoded in the i.tm.reg
5018 field, the other in the combined i.tm.mode and i.tm.regmem
5019 fields. If no form of this instruction supports a memory
5020 destination operand, then we assume the source operand may
5021 sometimes be a memory operand and so we need to store the
5022 destination in the i.rm.reg field. */
5023 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5024 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5026 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5027 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5028 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5030 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5035 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5036 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5037 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5039 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5042 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5044 if (!i
.types
[0].bitfield
.control
5045 && !i
.types
[1].bitfield
.control
)
5047 i
.rex
&= ~(REX_R
| REX_B
);
5048 add_prefix (LOCK_PREFIX_OPCODE
);
5052 { /* If it's not 2 reg operands... */
5057 unsigned int fake_zero_displacement
= 0;
5060 for (op
= 0; op
< i
.operands
; op
++)
5061 if (operand_type_check (i
.types
[op
], anymem
))
5063 gas_assert (op
< i
.operands
);
5067 if (i
.base_reg
== 0)
5070 if (!i
.disp_operands
)
5071 fake_zero_displacement
= 1;
5072 if (i
.index_reg
== 0)
5074 /* Operand is just <disp> */
5075 if (flag_code
== CODE_64BIT
)
5077 /* 64bit mode overwrites the 32bit absolute
5078 addressing by RIP relative addressing and
5079 absolute addressing is encoded by one of the
5080 redundant SIB forms. */
5081 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5082 i
.sib
.base
= NO_BASE_REGISTER
;
5083 i
.sib
.index
= NO_INDEX_REGISTER
;
5084 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5085 ? disp32s
: disp32
);
5087 else if ((flag_code
== CODE_16BIT
)
5088 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5090 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5091 i
.types
[op
] = disp16
;
5095 i
.rm
.regmem
= NO_BASE_REGISTER
;
5096 i
.types
[op
] = disp32
;
5099 else /* !i.base_reg && i.index_reg */
5101 if (i
.index_reg
->reg_num
== RegEiz
5102 || i
.index_reg
->reg_num
== RegRiz
)
5103 i
.sib
.index
= NO_INDEX_REGISTER
;
5105 i
.sib
.index
= i
.index_reg
->reg_num
;
5106 i
.sib
.base
= NO_BASE_REGISTER
;
5107 i
.sib
.scale
= i
.log2_scale_factor
;
5108 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5109 i
.types
[op
].bitfield
.disp8
= 0;
5110 i
.types
[op
].bitfield
.disp16
= 0;
5111 i
.types
[op
].bitfield
.disp64
= 0;
5112 if (flag_code
!= CODE_64BIT
)
5114 /* Must be 32 bit */
5115 i
.types
[op
].bitfield
.disp32
= 1;
5116 i
.types
[op
].bitfield
.disp32s
= 0;
5120 i
.types
[op
].bitfield
.disp32
= 0;
5121 i
.types
[op
].bitfield
.disp32s
= 1;
5123 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5127 /* RIP addressing for 64bit mode. */
5128 else if (i
.base_reg
->reg_num
== RegRip
||
5129 i
.base_reg
->reg_num
== RegEip
)
5131 i
.rm
.regmem
= NO_BASE_REGISTER
;
5132 i
.types
[op
].bitfield
.disp8
= 0;
5133 i
.types
[op
].bitfield
.disp16
= 0;
5134 i
.types
[op
].bitfield
.disp32
= 0;
5135 i
.types
[op
].bitfield
.disp32s
= 1;
5136 i
.types
[op
].bitfield
.disp64
= 0;
5137 i
.flags
[op
] |= Operand_PCrel
;
5138 if (! i
.disp_operands
)
5139 fake_zero_displacement
= 1;
5141 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5143 switch (i
.base_reg
->reg_num
)
5146 if (i
.index_reg
== 0)
5148 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5149 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5153 if (i
.index_reg
== 0)
5156 if (operand_type_check (i
.types
[op
], disp
) == 0)
5158 /* fake (%bp) into 0(%bp) */
5159 i
.types
[op
].bitfield
.disp8
= 1;
5160 fake_zero_displacement
= 1;
5163 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5164 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5166 default: /* (%si) -> 4 or (%di) -> 5 */
5167 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5169 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5171 else /* i.base_reg and 32/64 bit mode */
5173 if (flag_code
== CODE_64BIT
5174 && operand_type_check (i
.types
[op
], disp
))
5176 i386_operand_type temp
;
5177 operand_type_set (&temp
, 0);
5178 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5180 if (i
.prefix
[ADDR_PREFIX
] == 0)
5181 i
.types
[op
].bitfield
.disp32s
= 1;
5183 i
.types
[op
].bitfield
.disp32
= 1;
5186 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5187 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5189 i
.sib
.base
= i
.base_reg
->reg_num
;
5190 /* x86-64 ignores REX prefix bit here to avoid decoder
5192 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5195 if (i
.disp_operands
== 0)
5197 fake_zero_displacement
= 1;
5198 i
.types
[op
].bitfield
.disp8
= 1;
5201 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5205 i
.sib
.scale
= i
.log2_scale_factor
;
5206 if (i
.index_reg
== 0)
5208 /* <disp>(%esp) becomes two byte modrm with no index
5209 register. We've already stored the code for esp
5210 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5211 Any base register besides %esp will not use the
5212 extra modrm byte. */
5213 i
.sib
.index
= NO_INDEX_REGISTER
;
5217 if (i
.index_reg
->reg_num
== RegEiz
5218 || i
.index_reg
->reg_num
== RegRiz
)
5219 i
.sib
.index
= NO_INDEX_REGISTER
;
5221 i
.sib
.index
= i
.index_reg
->reg_num
;
5222 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5223 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5228 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5229 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5232 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5235 if (fake_zero_displacement
)
5237 /* Fakes a zero displacement assuming that i.types[op]
5238 holds the correct displacement size. */
5241 gas_assert (i
.op
[op
].disps
== 0);
5242 exp
= &disp_expressions
[i
.disp_operands
++];
5243 i
.op
[op
].disps
= exp
;
5244 exp
->X_op
= O_constant
;
5245 exp
->X_add_number
= 0;
5246 exp
->X_add_symbol
= (symbolS
*) 0;
5247 exp
->X_op_symbol
= (symbolS
*) 0;
5255 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5256 (if any) based on i.tm.extension_opcode. Again, we must be
5257 careful to make sure that segment/control/debug/test/MMX
5258 registers are coded into the i.rm.reg field. */
5262 unsigned int vex_reg
= ~0;
5264 for (op
= 0; op
< i
.operands
; op
++)
5265 if (i
.types
[op
].bitfield
.reg8
5266 || i
.types
[op
].bitfield
.reg16
5267 || i
.types
[op
].bitfield
.reg32
5268 || i
.types
[op
].bitfield
.reg64
5269 || i
.types
[op
].bitfield
.regmmx
5270 || i
.types
[op
].bitfield
.regxmm
5271 || i
.types
[op
].bitfield
.regymm
5272 || i
.types
[op
].bitfield
.sreg2
5273 || i
.types
[op
].bitfield
.sreg3
5274 || i
.types
[op
].bitfield
.control
5275 || i
.types
[op
].bitfield
.debug
5276 || i
.types
[op
].bitfield
.test
)
5281 else if (i
.tm
.opcode_modifier
.vexnds
)
5283 /* For instructions with VexNDS, the register-only
5284 source operand is encoded in VEX prefix. */
5285 gas_assert (mem
!= (unsigned int) ~0);
5290 gas_assert (op
< i
.operands
);
5295 gas_assert (vex_reg
< i
.operands
);
5298 else if (i
.tm
.opcode_modifier
.vexndd
)
5300 /* For instructions with VexNDD, there should be
5301 no memory operand and the register destination
5302 is encoded in VEX prefix. */
5303 gas_assert (i
.mem_operands
== 0
5304 && (op
+ 2) == i
.operands
);
5308 gas_assert (op
< i
.operands
);
5310 if (vex_reg
!= (unsigned int) ~0)
5312 gas_assert (i
.reg_operands
== 2);
5314 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5316 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5319 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5322 /* If there is an extension opcode to put here, the
5323 register number must be put into the regmem field. */
5324 if (i
.tm
.extension_opcode
!= None
)
5326 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5327 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5332 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5333 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5337 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5338 must set it to 3 to indicate this is a register operand
5339 in the regmem field. */
5340 if (!i
.mem_operands
)
5344 /* Fill in i.rm.reg field with extension opcode (if any). */
5345 if (i
.tm
.extension_opcode
!= None
)
5346 i
.rm
.reg
= i
.tm
.extension_opcode
;
5352 output_branch (void)
5357 relax_substateT subtype
;
5362 if (flag_code
== CODE_16BIT
)
5366 if (i
.prefix
[DATA_PREFIX
] != 0)
5372 /* Pentium4 branch hints. */
5373 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5374 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5379 if (i
.prefix
[REX_PREFIX
] != 0)
5385 if (i
.prefixes
!= 0 && !intel_syntax
)
5386 as_warn (_("skipping prefixes on this instruction"));
5388 /* It's always a symbol; End frag & setup for relax.
5389 Make sure there is enough room in this frag for the largest
5390 instruction we may generate in md_convert_frag. This is 2
5391 bytes for the opcode and room for the prefix and largest
5393 frag_grow (prefix
+ 2 + 4);
5394 /* Prefix and 1 opcode byte go in fr_fix. */
5395 p
= frag_more (prefix
+ 1);
5396 if (i
.prefix
[DATA_PREFIX
] != 0)
5397 *p
++ = DATA_PREFIX_OPCODE
;
5398 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5399 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5400 *p
++ = i
.prefix
[SEG_PREFIX
];
5401 if (i
.prefix
[REX_PREFIX
] != 0)
5402 *p
++ = i
.prefix
[REX_PREFIX
];
5403 *p
= i
.tm
.base_opcode
;
5405 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5406 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5407 else if (cpu_arch_flags
.bitfield
.cpui386
)
5408 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5410 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5413 sym
= i
.op
[0].disps
->X_add_symbol
;
5414 off
= i
.op
[0].disps
->X_add_number
;
5416 if (i
.op
[0].disps
->X_op
!= O_constant
5417 && i
.op
[0].disps
->X_op
!= O_symbol
)
5419 /* Handle complex expressions. */
5420 sym
= make_expr_symbol (i
.op
[0].disps
);
5424 /* 1 possible extra opcode + 4 byte displacement go in var part.
5425 Pass reloc in fr_var. */
5426 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5436 if (i
.tm
.opcode_modifier
.jumpbyte
)
5438 /* This is a loop or jecxz type instruction. */
5440 if (i
.prefix
[ADDR_PREFIX
] != 0)
5442 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5445 /* Pentium4 branch hints. */
5446 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5447 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5449 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5458 if (flag_code
== CODE_16BIT
)
5461 if (i
.prefix
[DATA_PREFIX
] != 0)
5463 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5473 if (i
.prefix
[REX_PREFIX
] != 0)
5475 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5479 if (i
.prefixes
!= 0 && !intel_syntax
)
5480 as_warn (_("skipping prefixes on this instruction"));
5482 p
= frag_more (1 + size
);
5483 *p
++ = i
.tm
.base_opcode
;
5485 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5486 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5488 /* All jumps handled here are signed, but don't use a signed limit
5489 check for 32 and 16 bit jumps as we want to allow wrap around at
5490 4G and 64k respectively. */
5492 fixP
->fx_signed
= 1;
5496 output_interseg_jump (void)
5504 if (flag_code
== CODE_16BIT
)
5508 if (i
.prefix
[DATA_PREFIX
] != 0)
5514 if (i
.prefix
[REX_PREFIX
] != 0)
5524 if (i
.prefixes
!= 0 && !intel_syntax
)
5525 as_warn (_("skipping prefixes on this instruction"));
5527 /* 1 opcode; 2 segment; offset */
5528 p
= frag_more (prefix
+ 1 + 2 + size
);
5530 if (i
.prefix
[DATA_PREFIX
] != 0)
5531 *p
++ = DATA_PREFIX_OPCODE
;
5533 if (i
.prefix
[REX_PREFIX
] != 0)
5534 *p
++ = i
.prefix
[REX_PREFIX
];
5536 *p
++ = i
.tm
.base_opcode
;
5537 if (i
.op
[1].imms
->X_op
== O_constant
)
5539 offsetT n
= i
.op
[1].imms
->X_add_number
;
5542 && !fits_in_unsigned_word (n
)
5543 && !fits_in_signed_word (n
))
5545 as_bad (_("16-bit jump out of range"));
5548 md_number_to_chars (p
, n
, size
);
5551 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5552 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5553 if (i
.op
[0].imms
->X_op
!= O_constant
)
5554 as_bad (_("can't handle non absolute segment in `%s'"),
5556 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5562 fragS
*insn_start_frag
;
5563 offsetT insn_start_off
;
5565 /* Tie dwarf2 debug info to the address at the start of the insn.
5566 We can't do this after the insn has been output as the current
5567 frag may have been closed off. eg. by frag_var. */
5568 dwarf2_emit_insn (0);
5570 insn_start_frag
= frag_now
;
5571 insn_start_off
= frag_now_fix ();
5574 if (i
.tm
.opcode_modifier
.jump
)
5576 else if (i
.tm
.opcode_modifier
.jumpbyte
5577 || i
.tm
.opcode_modifier
.jumpdword
)
5579 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5580 output_interseg_jump ();
5583 /* Output normal instructions here. */
5587 unsigned int prefix
;
5589 /* Since the VEX prefix contains the implicit prefix, we don't
5590 need the explicit prefix. */
5591 if (!i
.tm
.opcode_modifier
.vex
)
5593 switch (i
.tm
.opcode_length
)
5596 if (i
.tm
.base_opcode
& 0xff000000)
5598 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5603 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5605 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5606 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5609 if (prefix
!= REPE_PREFIX_OPCODE
5610 || (i
.prefix
[LOCKREP_PREFIX
]
5611 != REPE_PREFIX_OPCODE
))
5612 add_prefix (prefix
);
5615 add_prefix (prefix
);
5624 /* The prefix bytes. */
5625 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5627 FRAG_APPEND_1_CHAR (*q
);
5630 if (i
.tm
.opcode_modifier
.vex
)
5632 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5637 /* REX byte is encoded in VEX prefix. */
5641 FRAG_APPEND_1_CHAR (*q
);
5644 /* There should be no other prefixes for instructions
5649 /* Now the VEX prefix. */
5650 p
= frag_more (i
.vex
.length
);
5651 for (j
= 0; j
< i
.vex
.length
; j
++)
5652 p
[j
] = i
.vex
.bytes
[j
];
5655 /* Now the opcode; be careful about word order here! */
5656 if (i
.tm
.opcode_length
== 1)
5658 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5662 switch (i
.tm
.opcode_length
)
5666 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5676 /* Put out high byte first: can't use md_number_to_chars! */
5677 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5678 *p
= i
.tm
.base_opcode
& 0xff;
5681 /* Now the modrm byte and sib byte (if present). */
5682 if (i
.tm
.opcode_modifier
.modrm
)
5684 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5687 /* If i.rm.regmem == ESP (4)
5688 && i.rm.mode != (Register mode)
5690 ==> need second modrm byte. */
5691 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5693 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5694 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5696 | i
.sib
.scale
<< 6));
5699 if (i
.disp_operands
)
5700 output_disp (insn_start_frag
, insn_start_off
);
5703 output_imm (insn_start_frag
, insn_start_off
);
5709 pi ("" /*line*/, &i
);
5711 #endif /* DEBUG386 */
5714 /* Return the size of the displacement operand N. */
5717 disp_size (unsigned int n
)
5720 if (i
.types
[n
].bitfield
.disp64
)
5722 else if (i
.types
[n
].bitfield
.disp8
)
5724 else if (i
.types
[n
].bitfield
.disp16
)
5729 /* Return the size of the immediate operand N. */
5732 imm_size (unsigned int n
)
5735 if (i
.types
[n
].bitfield
.imm64
)
5737 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5739 else if (i
.types
[n
].bitfield
.imm16
)
5745 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5750 for (n
= 0; n
< i
.operands
; n
++)
5752 if (operand_type_check (i
.types
[n
], disp
))
5754 if (i
.op
[n
].disps
->X_op
== O_constant
)
5756 int size
= disp_size (n
);
5759 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5761 p
= frag_more (size
);
5762 md_number_to_chars (p
, val
, size
);
5766 enum bfd_reloc_code_real reloc_type
;
5767 int size
= disp_size (n
);
5768 int sign
= i
.types
[n
].bitfield
.disp32s
;
5769 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5771 /* We can't have 8 bit displacement here. */
5772 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5774 /* The PC relative address is computed relative
5775 to the instruction boundary, so in case immediate
5776 fields follows, we need to adjust the value. */
5777 if (pcrel
&& i
.imm_operands
)
5782 for (n1
= 0; n1
< i
.operands
; n1
++)
5783 if (operand_type_check (i
.types
[n1
], imm
))
5785 /* Only one immediate is allowed for PC
5786 relative address. */
5787 gas_assert (sz
== 0);
5789 i
.op
[n
].disps
->X_add_number
-= sz
;
5791 /* We should find the immediate. */
5792 gas_assert (sz
!= 0);
5795 p
= frag_more (size
);
5796 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5798 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5799 && (((reloc_type
== BFD_RELOC_32
5800 || reloc_type
== BFD_RELOC_X86_64_32S
5801 || (reloc_type
== BFD_RELOC_64
5803 && (i
.op
[n
].disps
->X_op
== O_symbol
5804 || (i
.op
[n
].disps
->X_op
== O_add
5805 && ((symbol_get_value_expression
5806 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5808 || reloc_type
== BFD_RELOC_32_PCREL
))
5812 if (insn_start_frag
== frag_now
)
5813 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5818 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5819 for (fr
= insn_start_frag
->fr_next
;
5820 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5822 add
+= p
- frag_now
->fr_literal
;
5827 reloc_type
= BFD_RELOC_386_GOTPC
;
5828 i
.op
[n
].imms
->X_add_number
+= add
;
5830 else if (reloc_type
== BFD_RELOC_64
)
5831 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5833 /* Don't do the adjustment for x86-64, as there
5834 the pcrel addressing is relative to the _next_
5835 insn, and that is taken care of in other code. */
5836 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5838 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5839 i
.op
[n
].disps
, pcrel
, reloc_type
);
5846 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5851 for (n
= 0; n
< i
.operands
; n
++)
5853 if (operand_type_check (i
.types
[n
], imm
))
5855 if (i
.op
[n
].imms
->X_op
== O_constant
)
5857 int size
= imm_size (n
);
5860 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5862 p
= frag_more (size
);
5863 md_number_to_chars (p
, val
, size
);
5867 /* Not absolute_section.
5868 Need a 32-bit fixup (don't support 8bit
5869 non-absolute imms). Try to support other
5871 enum bfd_reloc_code_real reloc_type
;
5872 int size
= imm_size (n
);
5875 if (i
.types
[n
].bitfield
.imm32s
5876 && (i
.suffix
== QWORD_MNEM_SUFFIX
5877 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5882 p
= frag_more (size
);
5883 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5885 /* This is tough to explain. We end up with this one if we
5886 * have operands that look like
5887 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5888 * obtain the absolute address of the GOT, and it is strongly
5889 * preferable from a performance point of view to avoid using
5890 * a runtime relocation for this. The actual sequence of
5891 * instructions often look something like:
5896 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5898 * The call and pop essentially return the absolute address
5899 * of the label .L66 and store it in %ebx. The linker itself
5900 * will ultimately change the first operand of the addl so
5901 * that %ebx points to the GOT, but to keep things simple, the
5902 * .o file must have this operand set so that it generates not
5903 * the absolute address of .L66, but the absolute address of
5904 * itself. This allows the linker itself simply treat a GOTPC
5905 * relocation as asking for a pcrel offset to the GOT to be
5906 * added in, and the addend of the relocation is stored in the
5907 * operand field for the instruction itself.
5909 * Our job here is to fix the operand so that it would add
5910 * the correct offset so that %ebx would point to itself. The
5911 * thing that is tricky is that .-.L66 will point to the
5912 * beginning of the instruction, so we need to further modify
5913 * the operand so that it will point to itself. There are
5914 * other cases where you have something like:
5916 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5918 * and here no correction would be required. Internally in
5919 * the assembler we treat operands of this form as not being
5920 * pcrel since the '.' is explicitly mentioned, and I wonder
5921 * whether it would simplify matters to do it this way. Who
5922 * knows. In earlier versions of the PIC patches, the
5923 * pcrel_adjust field was used to store the correction, but
5924 * since the expression is not pcrel, I felt it would be
5925 * confusing to do it this way. */
5927 if ((reloc_type
== BFD_RELOC_32
5928 || reloc_type
== BFD_RELOC_X86_64_32S
5929 || reloc_type
== BFD_RELOC_64
)
5931 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5932 && (i
.op
[n
].imms
->X_op
== O_symbol
5933 || (i
.op
[n
].imms
->X_op
== O_add
5934 && ((symbol_get_value_expression
5935 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5940 if (insn_start_frag
== frag_now
)
5941 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5946 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5947 for (fr
= insn_start_frag
->fr_next
;
5948 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5950 add
+= p
- frag_now
->fr_literal
;
5954 reloc_type
= BFD_RELOC_386_GOTPC
;
5956 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5958 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5959 i
.op
[n
].imms
->X_add_number
+= add
;
5961 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5962 i
.op
[n
].imms
, 0, reloc_type
);
5968 /* x86_cons_fix_new is called via the expression parsing code when a
5969 reloc is needed. We use this hook to get the correct .got reloc. */
5970 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5971 static int cons_sign
= -1;
5974 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5977 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5979 got_reloc
= NO_RELOC
;
5982 if (exp
->X_op
== O_secrel
)
5984 exp
->X_op
= O_symbol
;
5985 r
= BFD_RELOC_32_SECREL
;
5989 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5992 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5993 # define lex_got(reloc, adjust, types) NULL
5995 /* Parse operands of the form
5996 <symbol>@GOTOFF+<nnn>
5997 and similar .plt or .got references.
5999 If we find one, set up the correct relocation in RELOC and copy the
6000 input string, minus the `@GOTOFF' into a malloc'd buffer for
6001 parsing by the calling routine. Return this buffer, and if ADJUST
6002 is non-null set it to the length of the string we removed from the
6003 input line. Otherwise return NULL. */
6005 lex_got (enum bfd_reloc_code_real
*reloc
,
6007 i386_operand_type
*types
)
6009 /* Some of the relocations depend on the size of what field is to
6010 be relocated. But in our callers i386_immediate and i386_displacement
6011 we don't yet know the operand size (this will be set by insn
6012 matching). Hence we record the word32 relocation here,
6013 and adjust the reloc according to the real size in reloc(). */
6014 static const struct {
6016 const enum bfd_reloc_code_real rel
[2];
6017 const i386_operand_type types64
;
6020 BFD_RELOC_X86_64_PLTOFF64
},
6021 OPERAND_TYPE_IMM64
},
6022 { "PLT", { BFD_RELOC_386_PLT32
,
6023 BFD_RELOC_X86_64_PLT32
},
6024 OPERAND_TYPE_IMM32_32S_DISP32
},
6026 BFD_RELOC_X86_64_GOTPLT64
},
6027 OPERAND_TYPE_IMM64_DISP64
},
6028 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6029 BFD_RELOC_X86_64_GOTOFF64
},
6030 OPERAND_TYPE_IMM64_DISP64
},
6032 BFD_RELOC_X86_64_GOTPCREL
},
6033 OPERAND_TYPE_IMM32_32S_DISP32
},
6034 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6035 BFD_RELOC_X86_64_TLSGD
},
6036 OPERAND_TYPE_IMM32_32S_DISP32
},
6037 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6039 OPERAND_TYPE_NONE
},
6041 BFD_RELOC_X86_64_TLSLD
},
6042 OPERAND_TYPE_IMM32_32S_DISP32
},
6043 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6044 BFD_RELOC_X86_64_GOTTPOFF
},
6045 OPERAND_TYPE_IMM32_32S_DISP32
},
6046 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6047 BFD_RELOC_X86_64_TPOFF32
},
6048 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6049 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6051 OPERAND_TYPE_NONE
},
6052 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6053 BFD_RELOC_X86_64_DTPOFF32
},
6055 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6056 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6058 OPERAND_TYPE_NONE
},
6059 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6061 OPERAND_TYPE_NONE
},
6062 { "GOT", { BFD_RELOC_386_GOT32
,
6063 BFD_RELOC_X86_64_GOT32
},
6064 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6065 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6066 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6067 OPERAND_TYPE_IMM32_32S_DISP32
},
6068 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6069 BFD_RELOC_X86_64_TLSDESC_CALL
},
6070 OPERAND_TYPE_IMM32_32S_DISP32
},
6078 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6079 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6082 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6086 len
= strlen (gotrel
[j
].str
);
6087 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6089 if (gotrel
[j
].rel
[object_64bit
] != 0)
6092 char *tmpbuf
, *past_reloc
;
6094 *reloc
= gotrel
[j
].rel
[object_64bit
];
6100 if (flag_code
!= CODE_64BIT
)
6102 types
->bitfield
.imm32
= 1;
6103 types
->bitfield
.disp32
= 1;
6106 *types
= gotrel
[j
].types64
;
6109 if (GOT_symbol
== NULL
)
6110 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6112 /* The length of the first part of our input line. */
6113 first
= cp
- input_line_pointer
;
6115 /* The second part goes from after the reloc token until
6116 (and including) an end_of_line char or comma. */
6117 past_reloc
= cp
+ 1 + len
;
6119 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6121 second
= cp
+ 1 - past_reloc
;
6123 /* Allocate and copy string. The trailing NUL shouldn't
6124 be necessary, but be safe. */
6125 tmpbuf
= xmalloc (first
+ second
+ 2);
6126 memcpy (tmpbuf
, input_line_pointer
, first
);
6127 if (second
!= 0 && *past_reloc
!= ' ')
6128 /* Replace the relocation token with ' ', so that
6129 errors like foo@GOTOFF1 will be detected. */
6130 tmpbuf
[first
++] = ' ';
6131 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6132 tmpbuf
[first
+ second
] = '\0';
6136 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6137 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6142 /* Might be a symbol version string. Don't as_bad here. */
6147 x86_cons (expressionS
*exp
, int size
)
6149 intel_syntax
= -intel_syntax
;
6151 if (size
== 4 || (object_64bit
&& size
== 8))
6153 /* Handle @GOTOFF and the like in an expression. */
6155 char *gotfree_input_line
;
6158 save
= input_line_pointer
;
6159 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6160 if (gotfree_input_line
)
6161 input_line_pointer
= gotfree_input_line
;
6165 if (gotfree_input_line
)
6167 /* expression () has merrily parsed up to the end of line,
6168 or a comma - in the wrong buffer. Transfer how far
6169 input_line_pointer has moved to the right buffer. */
6170 input_line_pointer
= (save
6171 + (input_line_pointer
- gotfree_input_line
)
6173 free (gotfree_input_line
);
6174 if (exp
->X_op
== O_constant
6175 || exp
->X_op
== O_absent
6176 || exp
->X_op
== O_illegal
6177 || exp
->X_op
== O_register
6178 || exp
->X_op
== O_big
)
6180 char c
= *input_line_pointer
;
6181 *input_line_pointer
= 0;
6182 as_bad (_("missing or invalid expression `%s'"), save
);
6183 *input_line_pointer
= c
;
6190 intel_syntax
= -intel_syntax
;
6193 i386_intel_simplify (exp
);
6197 static void signed_cons (int size
)
6199 if (flag_code
== CODE_64BIT
)
6207 pe_directive_secrel (dummy
)
6208 int dummy ATTRIBUTE_UNUSED
;
6215 if (exp
.X_op
== O_symbol
)
6216 exp
.X_op
= O_secrel
;
6218 emit_expr (&exp
, 4);
6220 while (*input_line_pointer
++ == ',');
6222 input_line_pointer
--;
6223 demand_empty_rest_of_line ();
6228 i386_immediate (char *imm_start
)
6230 char *save_input_line_pointer
;
6231 char *gotfree_input_line
;
6234 i386_operand_type types
;
6236 operand_type_set (&types
, ~0);
6238 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6240 as_bad (_("at most %d immediate operands are allowed"),
6241 MAX_IMMEDIATE_OPERANDS
);
6245 exp
= &im_expressions
[i
.imm_operands
++];
6246 i
.op
[this_operand
].imms
= exp
;
6248 if (is_space_char (*imm_start
))
6251 save_input_line_pointer
= input_line_pointer
;
6252 input_line_pointer
= imm_start
;
6254 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6255 if (gotfree_input_line
)
6256 input_line_pointer
= gotfree_input_line
;
6258 exp_seg
= expression (exp
);
6261 if (*input_line_pointer
)
6262 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6264 input_line_pointer
= save_input_line_pointer
;
6265 if (gotfree_input_line
)
6267 free (gotfree_input_line
);
6269 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6270 exp
->X_op
= O_illegal
;
6273 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6277 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6278 i386_operand_type types
, const char *imm_start
)
6280 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6282 as_bad (_("missing or invalid immediate expression `%s'"),
6286 else if (exp
->X_op
== O_constant
)
6288 /* Size it properly later. */
6289 i
.types
[this_operand
].bitfield
.imm64
= 1;
6290 /* If BFD64, sign extend val. */
6291 if (!use_rela_relocations
6292 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6294 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6296 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6297 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6298 && exp_seg
!= absolute_section
6299 && exp_seg
!= text_section
6300 && exp_seg
!= data_section
6301 && exp_seg
!= bss_section
6302 && exp_seg
!= undefined_section
6303 && !bfd_is_com_section (exp_seg
))
6305 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6309 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6311 as_bad (_("illegal immediate register operand %s"), imm_start
);
6316 /* This is an address. The size of the address will be
6317 determined later, depending on destination register,
6318 suffix, or the default for the section. */
6319 i
.types
[this_operand
].bitfield
.imm8
= 1;
6320 i
.types
[this_operand
].bitfield
.imm16
= 1;
6321 i
.types
[this_operand
].bitfield
.imm32
= 1;
6322 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6323 i
.types
[this_operand
].bitfield
.imm64
= 1;
6324 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6332 i386_scale (char *scale
)
6335 char *save
= input_line_pointer
;
6337 input_line_pointer
= scale
;
6338 val
= get_absolute_expression ();
6343 i
.log2_scale_factor
= 0;
6346 i
.log2_scale_factor
= 1;
6349 i
.log2_scale_factor
= 2;
6352 i
.log2_scale_factor
= 3;
6356 char sep
= *input_line_pointer
;
6358 *input_line_pointer
= '\0';
6359 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6361 *input_line_pointer
= sep
;
6362 input_line_pointer
= save
;
6366 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6368 as_warn (_("scale factor of %d without an index register"),
6369 1 << i
.log2_scale_factor
);
6370 i
.log2_scale_factor
= 0;
6372 scale
= input_line_pointer
;
6373 input_line_pointer
= save
;
6378 i386_displacement (char *disp_start
, char *disp_end
)
6382 char *save_input_line_pointer
;
6383 char *gotfree_input_line
;
6385 i386_operand_type bigdisp
, types
= anydisp
;
6388 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6390 as_bad (_("at most %d displacement operands are allowed"),
6391 MAX_MEMORY_OPERANDS
);
6395 operand_type_set (&bigdisp
, 0);
6396 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6397 || (!current_templates
->start
->opcode_modifier
.jump
6398 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6400 bigdisp
.bitfield
.disp32
= 1;
6401 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6402 if (flag_code
== CODE_64BIT
)
6406 bigdisp
.bitfield
.disp32s
= 1;
6407 bigdisp
.bitfield
.disp64
= 1;
6410 else if ((flag_code
== CODE_16BIT
) ^ override
)
6412 bigdisp
.bitfield
.disp32
= 0;
6413 bigdisp
.bitfield
.disp16
= 1;
6418 /* For PC-relative branches, the width of the displacement
6419 is dependent upon data size, not address size. */
6420 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6421 if (flag_code
== CODE_64BIT
)
6423 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6424 bigdisp
.bitfield
.disp16
= 1;
6427 bigdisp
.bitfield
.disp32
= 1;
6428 bigdisp
.bitfield
.disp32s
= 1;
6434 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6436 : LONG_MNEM_SUFFIX
));
6437 bigdisp
.bitfield
.disp32
= 1;
6438 if ((flag_code
== CODE_16BIT
) ^ override
)
6440 bigdisp
.bitfield
.disp32
= 0;
6441 bigdisp
.bitfield
.disp16
= 1;
6445 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6448 exp
= &disp_expressions
[i
.disp_operands
];
6449 i
.op
[this_operand
].disps
= exp
;
6451 save_input_line_pointer
= input_line_pointer
;
6452 input_line_pointer
= disp_start
;
6453 END_STRING_AND_SAVE (disp_end
);
6455 #ifndef GCC_ASM_O_HACK
6456 #define GCC_ASM_O_HACK 0
6459 END_STRING_AND_SAVE (disp_end
+ 1);
6460 if (i
.types
[this_operand
].bitfield
.baseIndex
6461 && displacement_string_end
[-1] == '+')
6463 /* This hack is to avoid a warning when using the "o"
6464 constraint within gcc asm statements.
6467 #define _set_tssldt_desc(n,addr,limit,type) \
6468 __asm__ __volatile__ ( \
6470 "movw %w1,2+%0\n\t" \
6472 "movb %b1,4+%0\n\t" \
6473 "movb %4,5+%0\n\t" \
6474 "movb $0,6+%0\n\t" \
6475 "movb %h1,7+%0\n\t" \
6477 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6479 This works great except that the output assembler ends
6480 up looking a bit weird if it turns out that there is
6481 no offset. You end up producing code that looks like:
6494 So here we provide the missing zero. */
6496 *displacement_string_end
= '0';
6499 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6500 if (gotfree_input_line
)
6501 input_line_pointer
= gotfree_input_line
;
6503 exp_seg
= expression (exp
);
6506 if (*input_line_pointer
)
6507 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6509 RESTORE_END_STRING (disp_end
+ 1);
6511 input_line_pointer
= save_input_line_pointer
;
6512 if (gotfree_input_line
)
6514 free (gotfree_input_line
);
6516 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6517 exp
->X_op
= O_illegal
;
6520 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6522 RESTORE_END_STRING (disp_end
);
6528 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6529 i386_operand_type types
, const char *disp_start
)
6531 i386_operand_type bigdisp
;
6534 /* We do this to make sure that the section symbol is in
6535 the symbol table. We will ultimately change the relocation
6536 to be relative to the beginning of the section. */
6537 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6538 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6539 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6541 if (exp
->X_op
!= O_symbol
)
6544 if (S_IS_LOCAL (exp
->X_add_symbol
)
6545 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6546 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6547 exp
->X_op
= O_subtract
;
6548 exp
->X_op_symbol
= GOT_symbol
;
6549 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6550 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6551 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6552 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6554 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6557 else if (exp
->X_op
== O_absent
6558 || exp
->X_op
== O_illegal
6559 || exp
->X_op
== O_big
)
6562 as_bad (_("missing or invalid displacement expression `%s'"),
6567 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6568 else if (exp
->X_op
!= O_constant
6569 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6570 && exp_seg
!= absolute_section
6571 && exp_seg
!= text_section
6572 && exp_seg
!= data_section
6573 && exp_seg
!= bss_section
6574 && exp_seg
!= undefined_section
6575 && !bfd_is_com_section (exp_seg
))
6577 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6582 /* Check if this is a displacement only operand. */
6583 bigdisp
= i
.types
[this_operand
];
6584 bigdisp
.bitfield
.disp8
= 0;
6585 bigdisp
.bitfield
.disp16
= 0;
6586 bigdisp
.bitfield
.disp32
= 0;
6587 bigdisp
.bitfield
.disp32s
= 0;
6588 bigdisp
.bitfield
.disp64
= 0;
6589 if (operand_type_all_zero (&bigdisp
))
6590 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6596 /* Make sure the memory operand we've been dealt is valid.
6597 Return 1 on success, 0 on a failure. */
6600 i386_index_check (const char *operand_string
)
6603 const char *kind
= "base/index";
6604 #if INFER_ADDR_PREFIX
6610 if (current_templates
->start
->opcode_modifier
.isstring
6611 && !current_templates
->start
->opcode_modifier
.immext
6612 && (current_templates
->end
[-1].opcode_modifier
.isstring
6615 /* Memory operands of string insns are special in that they only allow
6616 a single register (rDI, rSI, or rBX) as their memory address. */
6617 unsigned int expected
;
6619 kind
= "string address";
6621 if (current_templates
->start
->opcode_modifier
.w
)
6623 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6625 if (!type
.bitfield
.baseindex
6626 || ((!i
.mem_operands
!= !intel_syntax
)
6627 && current_templates
->end
[-1].operand_types
[1]
6628 .bitfield
.baseindex
))
6629 type
= current_templates
->end
[-1].operand_types
[1];
6630 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6633 expected
= 3 /* rBX */;
6635 if (!i
.base_reg
|| i
.index_reg
6636 || operand_type_check (i
.types
[this_operand
], disp
))
6638 else if (!(flag_code
== CODE_64BIT
6639 ? i
.prefix
[ADDR_PREFIX
]
6640 ? i
.base_reg
->reg_type
.bitfield
.reg32
6641 : i
.base_reg
->reg_type
.bitfield
.reg64
6642 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6643 ? i
.base_reg
->reg_type
.bitfield
.reg32
6644 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6646 else if (i
.base_reg
->reg_num
!= expected
)
6653 for (j
= 0; j
< i386_regtab_size
; ++j
)
6654 if ((flag_code
== CODE_64BIT
6655 ? i
.prefix
[ADDR_PREFIX
]
6656 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6657 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6658 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6659 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6660 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6661 && i386_regtab
[j
].reg_num
== expected
)
6663 gas_assert (j
< i386_regtab_size
);
6664 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6666 intel_syntax
? '[' : '(',
6668 i386_regtab
[j
].reg_name
,
6669 intel_syntax
? ']' : ')');
6673 else if (flag_code
== CODE_64BIT
)
6676 && ((i
.prefix
[ADDR_PREFIX
] == 0
6677 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6678 || (i
.prefix
[ADDR_PREFIX
]
6679 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6681 || i
.base_reg
->reg_num
!=
6682 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6684 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6685 || (i
.prefix
[ADDR_PREFIX
] == 0
6686 && i
.index_reg
->reg_num
!= RegRiz
6687 && !i
.index_reg
->reg_type
.bitfield
.reg64
6689 || (i
.prefix
[ADDR_PREFIX
]
6690 && i
.index_reg
->reg_num
!= RegEiz
6691 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6696 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6700 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6701 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6703 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6704 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6706 && i
.base_reg
->reg_num
< 6
6707 && i
.index_reg
->reg_num
>= 6
6708 && i
.log2_scale_factor
== 0))))
6715 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6717 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6718 && i
.index_reg
->reg_num
!= RegEiz
)
6719 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6725 #if INFER_ADDR_PREFIX
6726 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6728 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6730 /* Change the size of any displacement too. At most one of
6731 Disp16 or Disp32 is set.
6732 FIXME. There doesn't seem to be any real need for separate
6733 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6734 Removing them would probably clean up the code quite a lot. */
6735 if (flag_code
!= CODE_64BIT
6736 && (i
.types
[this_operand
].bitfield
.disp16
6737 || i
.types
[this_operand
].bitfield
.disp32
))
6738 i
.types
[this_operand
]
6739 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6744 as_bad (_("`%s' is not a valid %s expression"),
6749 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6751 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6752 ? flag_code
== CODE_32BIT
6761 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6765 i386_att_operand (char *operand_string
)
6769 char *op_string
= operand_string
;
6771 if (is_space_char (*op_string
))
6774 /* We check for an absolute prefix (differentiating,
6775 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6776 if (*op_string
== ABSOLUTE_PREFIX
)
6779 if (is_space_char (*op_string
))
6781 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6784 /* Check if operand is a register. */
6785 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6787 i386_operand_type temp
;
6789 /* Check for a segment override by searching for ':' after a
6790 segment register. */
6792 if (is_space_char (*op_string
))
6794 if (*op_string
== ':'
6795 && (r
->reg_type
.bitfield
.sreg2
6796 || r
->reg_type
.bitfield
.sreg3
))
6801 i
.seg
[i
.mem_operands
] = &es
;
6804 i
.seg
[i
.mem_operands
] = &cs
;
6807 i
.seg
[i
.mem_operands
] = &ss
;
6810 i
.seg
[i
.mem_operands
] = &ds
;
6813 i
.seg
[i
.mem_operands
] = &fs
;
6816 i
.seg
[i
.mem_operands
] = &gs
;
6820 /* Skip the ':' and whitespace. */
6822 if (is_space_char (*op_string
))
6825 if (!is_digit_char (*op_string
)
6826 && !is_identifier_char (*op_string
)
6827 && *op_string
!= '('
6828 && *op_string
!= ABSOLUTE_PREFIX
)
6830 as_bad (_("bad memory operand `%s'"), op_string
);
6833 /* Handle case of %es:*foo. */
6834 if (*op_string
== ABSOLUTE_PREFIX
)
6837 if (is_space_char (*op_string
))
6839 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6841 goto do_memory_reference
;
6845 as_bad (_("junk `%s' after register"), op_string
);
6849 temp
.bitfield
.baseindex
= 0;
6850 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6852 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6853 i
.op
[this_operand
].regs
= r
;
6856 else if (*op_string
== REGISTER_PREFIX
)
6858 as_bad (_("bad register name `%s'"), op_string
);
6861 else if (*op_string
== IMMEDIATE_PREFIX
)
6864 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6866 as_bad (_("immediate operand illegal with absolute jump"));
6869 if (!i386_immediate (op_string
))
6872 else if (is_digit_char (*op_string
)
6873 || is_identifier_char (*op_string
)
6874 || *op_string
== '(')
6876 /* This is a memory reference of some sort. */
6879 /* Start and end of displacement string expression (if found). */
6880 char *displacement_string_start
;
6881 char *displacement_string_end
;
6883 do_memory_reference
:
6884 if ((i
.mem_operands
== 1
6885 && !current_templates
->start
->opcode_modifier
.isstring
)
6886 || i
.mem_operands
== 2)
6888 as_bad (_("too many memory references for `%s'"),
6889 current_templates
->start
->name
);
6893 /* Check for base index form. We detect the base index form by
6894 looking for an ')' at the end of the operand, searching
6895 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6897 base_string
= op_string
+ strlen (op_string
);
6900 if (is_space_char (*base_string
))
6903 /* If we only have a displacement, set-up for it to be parsed later. */
6904 displacement_string_start
= op_string
;
6905 displacement_string_end
= base_string
+ 1;
6907 if (*base_string
== ')')
6910 unsigned int parens_balanced
= 1;
6911 /* We've already checked that the number of left & right ()'s are
6912 equal, so this loop will not be infinite. */
6916 if (*base_string
== ')')
6918 if (*base_string
== '(')
6921 while (parens_balanced
);
6923 temp_string
= base_string
;
6925 /* Skip past '(' and whitespace. */
6927 if (is_space_char (*base_string
))
6930 if (*base_string
== ','
6931 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6934 displacement_string_end
= temp_string
;
6936 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6940 base_string
= end_op
;
6941 if (is_space_char (*base_string
))
6945 /* There may be an index reg or scale factor here. */
6946 if (*base_string
== ',')
6949 if (is_space_char (*base_string
))
6952 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6955 base_string
= end_op
;
6956 if (is_space_char (*base_string
))
6958 if (*base_string
== ',')
6961 if (is_space_char (*base_string
))
6964 else if (*base_string
!= ')')
6966 as_bad (_("expecting `,' or `)' "
6967 "after index register in `%s'"),
6972 else if (*base_string
== REGISTER_PREFIX
)
6974 as_bad (_("bad register name `%s'"), base_string
);
6978 /* Check for scale factor. */
6979 if (*base_string
!= ')')
6981 char *end_scale
= i386_scale (base_string
);
6986 base_string
= end_scale
;
6987 if (is_space_char (*base_string
))
6989 if (*base_string
!= ')')
6991 as_bad (_("expecting `)' "
6992 "after scale factor in `%s'"),
6997 else if (!i
.index_reg
)
6999 as_bad (_("expecting index register or scale factor "
7000 "after `,'; got '%c'"),
7005 else if (*base_string
!= ')')
7007 as_bad (_("expecting `,' or `)' "
7008 "after base register in `%s'"),
7013 else if (*base_string
== REGISTER_PREFIX
)
7015 as_bad (_("bad register name `%s'"), base_string
);
7020 /* If there's an expression beginning the operand, parse it,
7021 assuming displacement_string_start and
7022 displacement_string_end are meaningful. */
7023 if (displacement_string_start
!= displacement_string_end
)
7025 if (!i386_displacement (displacement_string_start
,
7026 displacement_string_end
))
7030 /* Special case for (%dx) while doing input/output op. */
7032 && operand_type_equal (&i
.base_reg
->reg_type
,
7033 ®16_inoutportreg
)
7035 && i
.log2_scale_factor
== 0
7036 && i
.seg
[i
.mem_operands
] == 0
7037 && !operand_type_check (i
.types
[this_operand
], disp
))
7039 i
.types
[this_operand
] = inoutportreg
;
7043 if (i386_index_check (operand_string
) == 0)
7045 i
.types
[this_operand
].bitfield
.mem
= 1;
7050 /* It's not a memory operand; argh! */
7051 as_bad (_("invalid char %s beginning operand %d `%s'"),
7052 output_invalid (*op_string
),
7057 return 1; /* Normal return. */
7060 /* md_estimate_size_before_relax()
7062 Called just before relax() for rs_machine_dependent frags. The x86
7063 assembler uses these frags to handle variable size jump
7066 Any symbol that is now undefined will not become defined.
7067 Return the correct fr_subtype in the frag.
7068 Return the initial "guess for variable size of frag" to caller.
7069 The guess is actually the growth beyond the fixed part. Whatever
7070 we do to grow the fixed or variable part contributes to our
7074 md_estimate_size_before_relax (fragP
, segment
)
7078 /* We've already got fragP->fr_subtype right; all we have to do is
7079 check for un-relaxable symbols. On an ELF system, we can't relax
7080 an externally visible symbol, because it may be overridden by a
7082 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7083 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7085 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7086 || S_IS_WEAK (fragP
->fr_symbol
)
7087 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7088 & BSF_GNU_INDIRECT_FUNCTION
))))
7090 #if defined (OBJ_COFF) && defined (TE_PE)
7091 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7092 && S_IS_WEAK (fragP
->fr_symbol
))
7096 /* Symbol is undefined in this segment, or we need to keep a
7097 reloc so that weak symbols can be overridden. */
7098 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7099 enum bfd_reloc_code_real reloc_type
;
7100 unsigned char *opcode
;
7103 if (fragP
->fr_var
!= NO_RELOC
)
7104 reloc_type
= fragP
->fr_var
;
7106 reloc_type
= BFD_RELOC_16_PCREL
;
7108 reloc_type
= BFD_RELOC_32_PCREL
;
7110 old_fr_fix
= fragP
->fr_fix
;
7111 opcode
= (unsigned char *) fragP
->fr_opcode
;
7113 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7116 /* Make jmp (0xeb) a (d)word displacement jump. */
7118 fragP
->fr_fix
+= size
;
7119 fix_new (fragP
, old_fr_fix
, size
,
7121 fragP
->fr_offset
, 1,
7127 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7129 /* Negate the condition, and branch past an
7130 unconditional jump. */
7133 /* Insert an unconditional jump. */
7135 /* We added two extra opcode bytes, and have a two byte
7137 fragP
->fr_fix
+= 2 + 2;
7138 fix_new (fragP
, old_fr_fix
+ 2, 2,
7140 fragP
->fr_offset
, 1,
7147 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7152 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7154 fragP
->fr_offset
, 1,
7156 fixP
->fx_signed
= 1;
7160 /* This changes the byte-displacement jump 0x7N
7161 to the (d)word-displacement jump 0x0f,0x8N. */
7162 opcode
[1] = opcode
[0] + 0x10;
7163 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7164 /* We've added an opcode byte. */
7165 fragP
->fr_fix
+= 1 + size
;
7166 fix_new (fragP
, old_fr_fix
+ 1, size
,
7168 fragP
->fr_offset
, 1,
7173 BAD_CASE (fragP
->fr_subtype
);
7177 return fragP
->fr_fix
- old_fr_fix
;
7180 /* Guess size depending on current relax state. Initially the relax
7181 state will correspond to a short jump and we return 1, because
7182 the variable part of the frag (the branch offset) is one byte
7183 long. However, we can relax a section more than once and in that
7184 case we must either set fr_subtype back to the unrelaxed state,
7185 or return the value for the appropriate branch. */
7186 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7189 /* Called after relax() is finished.
7191 In: Address of frag.
7192 fr_type == rs_machine_dependent.
7193 fr_subtype is what the address relaxed to.
7195 Out: Any fixSs and constants are set up.
7196 Caller will turn frag into a ".space 0". */
7199 md_convert_frag (abfd
, sec
, fragP
)
7200 bfd
*abfd ATTRIBUTE_UNUSED
;
7201 segT sec ATTRIBUTE_UNUSED
;
7204 unsigned char *opcode
;
7205 unsigned char *where_to_put_displacement
= NULL
;
7206 offsetT target_address
;
7207 offsetT opcode_address
;
7208 unsigned int extension
= 0;
7209 offsetT displacement_from_opcode_start
;
7211 opcode
= (unsigned char *) fragP
->fr_opcode
;
7213 /* Address we want to reach in file space. */
7214 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7216 /* Address opcode resides at in file space. */
7217 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7219 /* Displacement from opcode start to fill into instruction. */
7220 displacement_from_opcode_start
= target_address
- opcode_address
;
7222 if ((fragP
->fr_subtype
& BIG
) == 0)
7224 /* Don't have to change opcode. */
7225 extension
= 1; /* 1 opcode + 1 displacement */
7226 where_to_put_displacement
= &opcode
[1];
7230 if (no_cond_jump_promotion
7231 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7232 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7233 _("long jump required"));
7235 switch (fragP
->fr_subtype
)
7237 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7238 extension
= 4; /* 1 opcode + 4 displacement */
7240 where_to_put_displacement
= &opcode
[1];
7243 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7244 extension
= 2; /* 1 opcode + 2 displacement */
7246 where_to_put_displacement
= &opcode
[1];
7249 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7250 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7251 extension
= 5; /* 2 opcode + 4 displacement */
7252 opcode
[1] = opcode
[0] + 0x10;
7253 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7254 where_to_put_displacement
= &opcode
[2];
7257 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7258 extension
= 3; /* 2 opcode + 2 displacement */
7259 opcode
[1] = opcode
[0] + 0x10;
7260 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7261 where_to_put_displacement
= &opcode
[2];
7264 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7269 where_to_put_displacement
= &opcode
[3];
7273 BAD_CASE (fragP
->fr_subtype
);
7278 /* If size if less then four we are sure that the operand fits,
7279 but if it's 4, then it could be that the displacement is larger
7281 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7283 && ((addressT
) (displacement_from_opcode_start
- extension
7284 + ((addressT
) 1 << 31))
7285 > (((addressT
) 2 << 31) - 1)))
7287 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7288 _("jump target out of range"));
7289 /* Make us emit 0. */
7290 displacement_from_opcode_start
= extension
;
7292 /* Now put displacement after opcode. */
7293 md_number_to_chars ((char *) where_to_put_displacement
,
7294 (valueT
) (displacement_from_opcode_start
- extension
),
7295 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7296 fragP
->fr_fix
+= extension
;
7299 /* Apply a fixup (fixS) to segment data, once it has been determined
7300 by our caller that we have all the info we need to fix it up.
7302 On the 386, immediates, displacements, and data pointers are all in
7303 the same (little-endian) format, so we don't need to care about which
7307 md_apply_fix (fixP
, valP
, seg
)
7308 /* The fix we're to put in. */
7310 /* Pointer to the value of the bits. */
7312 /* Segment fix is from. */
7313 segT seg ATTRIBUTE_UNUSED
;
7315 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7316 valueT value
= *valP
;
7318 #if !defined (TE_Mach)
7321 switch (fixP
->fx_r_type
)
7327 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7330 case BFD_RELOC_X86_64_32S
:
7331 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7334 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7337 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7342 if (fixP
->fx_addsy
!= NULL
7343 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7344 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7345 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7346 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7347 && !use_rela_relocations
)
7349 /* This is a hack. There should be a better way to handle this.
7350 This covers for the fact that bfd_install_relocation will
7351 subtract the current location (for partial_inplace, PC relative
7352 relocations); see more below. */
7356 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7359 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7361 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7364 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7367 || (symbol_section_p (fixP
->fx_addsy
)
7368 && sym_seg
!= absolute_section
))
7369 && !generic_force_reloc (fixP
))
7371 /* Yes, we add the values in twice. This is because
7372 bfd_install_relocation subtracts them out again. I think
7373 bfd_install_relocation is broken, but I don't dare change
7375 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7379 #if defined (OBJ_COFF) && defined (TE_PE)
7380 /* For some reason, the PE format does not store a
7381 section address offset for a PC relative symbol. */
7382 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7383 || S_IS_WEAK (fixP
->fx_addsy
))
7384 value
+= md_pcrel_from (fixP
);
7387 #if defined (OBJ_COFF) && defined (TE_PE)
7388 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7390 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7394 /* Fix a few things - the dynamic linker expects certain values here,
7395 and we must not disappoint it. */
7396 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7397 if (IS_ELF
&& fixP
->fx_addsy
)
7398 switch (fixP
->fx_r_type
)
7400 case BFD_RELOC_386_PLT32
:
7401 case BFD_RELOC_X86_64_PLT32
:
7402 /* Make the jump instruction point to the address of the operand. At
7403 runtime we merely add the offset to the actual PLT entry. */
7407 case BFD_RELOC_386_TLS_GD
:
7408 case BFD_RELOC_386_TLS_LDM
:
7409 case BFD_RELOC_386_TLS_IE_32
:
7410 case BFD_RELOC_386_TLS_IE
:
7411 case BFD_RELOC_386_TLS_GOTIE
:
7412 case BFD_RELOC_386_TLS_GOTDESC
:
7413 case BFD_RELOC_X86_64_TLSGD
:
7414 case BFD_RELOC_X86_64_TLSLD
:
7415 case BFD_RELOC_X86_64_GOTTPOFF
:
7416 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7417 value
= 0; /* Fully resolved at runtime. No addend. */
7419 case BFD_RELOC_386_TLS_LE
:
7420 case BFD_RELOC_386_TLS_LDO_32
:
7421 case BFD_RELOC_386_TLS_LE_32
:
7422 case BFD_RELOC_X86_64_DTPOFF32
:
7423 case BFD_RELOC_X86_64_DTPOFF64
:
7424 case BFD_RELOC_X86_64_TPOFF32
:
7425 case BFD_RELOC_X86_64_TPOFF64
:
7426 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7429 case BFD_RELOC_386_TLS_DESC_CALL
:
7430 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7431 value
= 0; /* Fully resolved at runtime. No addend. */
7432 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7436 case BFD_RELOC_386_GOT32
:
7437 case BFD_RELOC_X86_64_GOT32
:
7438 value
= 0; /* Fully resolved at runtime. No addend. */
7441 case BFD_RELOC_VTABLE_INHERIT
:
7442 case BFD_RELOC_VTABLE_ENTRY
:
7449 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7451 #endif /* !defined (TE_Mach) */
7453 /* Are we finished with this relocation now? */
7454 if (fixP
->fx_addsy
== NULL
)
7456 #if defined (OBJ_COFF) && defined (TE_PE)
7457 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7460 /* Remember value for tc_gen_reloc. */
7461 fixP
->fx_addnumber
= value
;
7462 /* Clear out the frag for now. */
7466 else if (use_rela_relocations
)
7468 fixP
->fx_no_overflow
= 1;
7469 /* Remember value for tc_gen_reloc. */
7470 fixP
->fx_addnumber
= value
;
7474 md_number_to_chars (p
, value
, fixP
->fx_size
);
7478 md_atof (int type
, char *litP
, int *sizeP
)
7480 /* This outputs the LITTLENUMs in REVERSE order;
7481 in accord with the bigendian 386. */
7482 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7485 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7488 output_invalid (int c
)
7491 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7494 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7495 "(0x%x)", (unsigned char) c
);
7496 return output_invalid_buf
;
7499 /* REG_STRING starts *before* REGISTER_PREFIX. */
7501 static const reg_entry
*
7502 parse_real_register (char *reg_string
, char **end_op
)
7504 char *s
= reg_string
;
7506 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7509 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7510 if (*s
== REGISTER_PREFIX
)
7513 if (is_space_char (*s
))
7517 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7519 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7520 return (const reg_entry
*) NULL
;
7524 /* For naked regs, make sure that we are not dealing with an identifier.
7525 This prevents confusing an identifier like `eax_var' with register
7527 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7528 return (const reg_entry
*) NULL
;
7532 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7534 /* Handle floating point regs, allowing spaces in the (i) part. */
7535 if (r
== i386_regtab
/* %st is first entry of table */)
7537 if (is_space_char (*s
))
7542 if (is_space_char (*s
))
7544 if (*s
>= '0' && *s
<= '7')
7548 if (is_space_char (*s
))
7553 r
= hash_find (reg_hash
, "st(0)");
7558 /* We have "%st(" then garbage. */
7559 return (const reg_entry
*) NULL
;
7563 if (r
== NULL
|| allow_pseudo_reg
)
7566 if (operand_type_all_zero (&r
->reg_type
))
7567 return (const reg_entry
*) NULL
;
7569 if ((r
->reg_type
.bitfield
.reg32
7570 || r
->reg_type
.bitfield
.sreg3
7571 || r
->reg_type
.bitfield
.control
7572 || r
->reg_type
.bitfield
.debug
7573 || r
->reg_type
.bitfield
.test
)
7574 && !cpu_arch_flags
.bitfield
.cpui386
)
7575 return (const reg_entry
*) NULL
;
7577 if (r
->reg_type
.bitfield
.floatreg
7578 && !cpu_arch_flags
.bitfield
.cpu8087
7579 && !cpu_arch_flags
.bitfield
.cpu287
7580 && !cpu_arch_flags
.bitfield
.cpu387
)
7581 return (const reg_entry
*) NULL
;
7583 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7584 return (const reg_entry
*) NULL
;
7586 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7587 return (const reg_entry
*) NULL
;
7589 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7590 return (const reg_entry
*) NULL
;
7592 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7593 if (!allow_index_reg
7594 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7595 return (const reg_entry
*) NULL
;
7597 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7598 || r
->reg_type
.bitfield
.reg64
)
7599 && (!cpu_arch_flags
.bitfield
.cpulm
7600 || !operand_type_equal (&r
->reg_type
, &control
))
7601 && flag_code
!= CODE_64BIT
)
7602 return (const reg_entry
*) NULL
;
7604 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7605 return (const reg_entry
*) NULL
;
7610 /* REG_STRING starts *before* REGISTER_PREFIX. */
7612 static const reg_entry
*
7613 parse_register (char *reg_string
, char **end_op
)
7617 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7618 r
= parse_real_register (reg_string
, end_op
);
7623 char *save
= input_line_pointer
;
7627 input_line_pointer
= reg_string
;
7628 c
= get_symbol_end ();
7629 symbolP
= symbol_find (reg_string
);
7630 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7632 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7634 know (e
->X_op
== O_register
);
7635 know (e
->X_add_number
>= 0
7636 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7637 r
= i386_regtab
+ e
->X_add_number
;
7638 *end_op
= input_line_pointer
;
7640 *input_line_pointer
= c
;
7641 input_line_pointer
= save
;
7647 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7650 char *end
= input_line_pointer
;
7653 r
= parse_register (name
, &input_line_pointer
);
7654 if (r
&& end
<= input_line_pointer
)
7656 *nextcharP
= *input_line_pointer
;
7657 *input_line_pointer
= 0;
7658 e
->X_op
= O_register
;
7659 e
->X_add_number
= r
- i386_regtab
;
7662 input_line_pointer
= end
;
7664 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7668 md_operand (expressionS
*e
)
7673 switch (*input_line_pointer
)
7675 case REGISTER_PREFIX
:
7676 r
= parse_real_register (input_line_pointer
, &end
);
7679 e
->X_op
= O_register
;
7680 e
->X_add_number
= r
- i386_regtab
;
7681 input_line_pointer
= end
;
7686 gas_assert (intel_syntax
);
7687 end
= input_line_pointer
++;
7689 if (*input_line_pointer
== ']')
7691 ++input_line_pointer
;
7692 e
->X_op_symbol
= make_expr_symbol (e
);
7693 e
->X_add_symbol
= NULL
;
7694 e
->X_add_number
= 0;
7700 input_line_pointer
= end
;
7707 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7708 const char *md_shortopts
= "kVQ:sqn";
7710 const char *md_shortopts
= "qn";
7713 #define OPTION_32 (OPTION_MD_BASE + 0)
7714 #define OPTION_64 (OPTION_MD_BASE + 1)
7715 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7716 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7717 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7718 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7719 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7720 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7721 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7722 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7723 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7724 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7726 struct option md_longopts
[] =
7728 {"32", no_argument
, NULL
, OPTION_32
},
7729 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7730 || defined (TE_PE) || defined (TE_PEP))
7731 {"64", no_argument
, NULL
, OPTION_64
},
7733 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7734 {"march", required_argument
, NULL
, OPTION_MARCH
},
7735 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7736 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7737 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7738 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7739 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7740 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7741 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7742 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7743 {NULL
, no_argument
, NULL
, 0}
7745 size_t md_longopts_size
= sizeof (md_longopts
);
7748 md_parse_option (int c
, char *arg
)
7756 optimize_align_code
= 0;
7763 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7764 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7765 should be emitted or not. FIXME: Not implemented. */
7769 /* -V: SVR4 argument to print version ID. */
7771 print_version_id ();
7774 /* -k: Ignore for FreeBSD compatibility. */
7779 /* -s: On i386 Solaris, this tells the native assembler to use
7780 .stab instead of .stab.excl. We always use .stab anyhow. */
7783 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7784 || defined (TE_PE) || defined (TE_PEP))
7787 const char **list
, **l
;
7789 list
= bfd_target_list ();
7790 for (l
= list
; *l
!= NULL
; l
++)
7791 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7792 || strcmp (*l
, "coff-x86-64") == 0
7793 || strcmp (*l
, "pe-x86-64") == 0
7794 || strcmp (*l
, "pei-x86-64") == 0)
7796 default_arch
= "x86_64";
7800 as_fatal (_("No compiled in support for x86_64"));
7807 default_arch
= "i386";
7811 #ifdef SVR4_COMMENT_CHARS
7816 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7818 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7822 i386_comment_chars
= n
;
7828 arch
= xstrdup (arg
);
7832 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7833 next
= strchr (arch
, '+');
7836 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7838 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7841 cpu_arch_name
= cpu_arch
[i
].name
;
7842 cpu_sub_arch_name
= NULL
;
7843 cpu_arch_flags
= cpu_arch
[i
].flags
;
7844 cpu_arch_isa
= cpu_arch
[i
].type
;
7845 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7846 if (!cpu_arch_tune_set
)
7848 cpu_arch_tune
= cpu_arch_isa
;
7849 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7853 else if (*cpu_arch
[i
].name
== '.'
7854 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7856 /* ISA entension. */
7857 i386_cpu_flags flags
;
7859 if (strncmp (arch
, "no", 2))
7860 flags
= cpu_flags_or (cpu_arch_flags
,
7863 flags
= cpu_flags_and_not (cpu_arch_flags
,
7865 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7867 if (cpu_sub_arch_name
)
7869 char *name
= cpu_sub_arch_name
;
7870 cpu_sub_arch_name
= concat (name
,
7872 (const char *) NULL
);
7876 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7877 cpu_arch_flags
= flags
;
7883 if (i
>= ARRAY_SIZE (cpu_arch
))
7884 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7888 while (next
!= NULL
);
7893 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7894 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7896 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7898 cpu_arch_tune_set
= 1;
7899 cpu_arch_tune
= cpu_arch
[i
].type
;
7900 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7904 if (i
>= ARRAY_SIZE (cpu_arch
))
7905 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7908 case OPTION_MMNEMONIC
:
7909 if (strcasecmp (arg
, "att") == 0)
7911 else if (strcasecmp (arg
, "intel") == 0)
7914 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7917 case OPTION_MSYNTAX
:
7918 if (strcasecmp (arg
, "att") == 0)
7920 else if (strcasecmp (arg
, "intel") == 0)
7923 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7926 case OPTION_MINDEX_REG
:
7927 allow_index_reg
= 1;
7930 case OPTION_MNAKED_REG
:
7931 allow_naked_reg
= 1;
7934 case OPTION_MOLD_GCC
:
7938 case OPTION_MSSE2AVX
:
7942 case OPTION_MSSE_CHECK
:
7943 if (strcasecmp (arg
, "error") == 0)
7944 sse_check
= sse_check_error
;
7945 else if (strcasecmp (arg
, "warning") == 0)
7946 sse_check
= sse_check_warning
;
7947 else if (strcasecmp (arg
, "none") == 0)
7948 sse_check
= sse_check_none
;
7950 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7960 md_show_usage (stream
)
7963 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7964 fprintf (stream
, _("\
7966 -V print assembler version number\n\
7969 fprintf (stream
, _("\
7970 -n Do not optimize code alignment\n\
7971 -q quieten some warnings\n"));
7972 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7973 fprintf (stream
, _("\
7976 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7977 || defined (TE_PE) || defined (TE_PEP))
7978 fprintf (stream
, _("\
7979 --32/--64 generate 32bit/64bit code\n"));
7981 #ifdef SVR4_COMMENT_CHARS
7982 fprintf (stream
, _("\
7983 --divide do not treat `/' as a comment character\n"));
7985 fprintf (stream
, _("\
7986 --divide ignored\n"));
7988 fprintf (stream
, _("\
7989 -march=CPU[,+EXTENSION...]\n\
7990 generate code for CPU and EXTENSION, CPU is one of:\n\
7991 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7992 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7993 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
7994 amdfam10, generic32, generic64\n\
7995 EXTENSION is combination of:\n\
7996 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
7997 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
7998 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
7999 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8000 svme, abm, padlock, fma4\n"));
8001 fprintf (stream
, _("\
8002 -mtune=CPU optimize for CPU, CPU is one of:\n\
8003 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8004 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8005 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8006 amdfam10, generic32, generic64\n"));
8007 fprintf (stream
, _("\
8008 -msse2avx encode SSE instructions with VEX prefix\n"));
8009 fprintf (stream
, _("\
8010 -msse-check=[none|error|warning]\n\
8011 check SSE instructions\n"));
8012 fprintf (stream
, _("\
8013 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8014 fprintf (stream
, _("\
8015 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8016 fprintf (stream
, _("\
8017 -mindex-reg support pseudo index registers\n"));
8018 fprintf (stream
, _("\
8019 -mnaked-reg don't require `%%' prefix for registers\n"));
8020 fprintf (stream
, _("\
8021 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8024 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8025 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8026 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8028 /* Pick the target format to use. */
8031 i386_target_format (void)
8033 if (!strcmp (default_arch
, "x86_64"))
8035 set_code_flag (CODE_64BIT
);
8036 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8038 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8039 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8040 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8041 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8042 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8043 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8044 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8045 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8046 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8047 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8048 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8050 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8052 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8053 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8054 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8055 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8056 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8057 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8058 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8059 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8060 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8061 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8064 else if (!strcmp (default_arch
, "i386"))
8066 set_code_flag (CODE_32BIT
);
8067 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8069 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8070 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8071 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8073 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8075 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8076 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8077 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8081 as_fatal (_("Unknown architecture"));
8082 switch (OUTPUT_FLAVOR
)
8084 #if defined (TE_PE) || defined (TE_PEP)
8085 case bfd_target_coff_flavour
:
8086 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8088 #ifdef OBJ_MAYBE_AOUT
8089 case bfd_target_aout_flavour
:
8090 return AOUT_TARGET_FORMAT
;
8093 case bfd_target_coff_flavour
:
8095 #elif defined (OBJ_MAYBE_COFF)
8096 case bfd_target_coff_flavour
:
8099 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8100 case bfd_target_elf_flavour
:
8102 if (flag_code
== CODE_64BIT
)
8105 use_rela_relocations
= 1;
8107 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8109 if (flag_code
!= CODE_64BIT
)
8110 as_fatal (_("Intel L1OM is 64bit only"));
8111 return ELF_TARGET_L1OM_FORMAT
;
8114 return (flag_code
== CODE_64BIT
8115 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8118 #if defined (OBJ_MACH_O)
8119 case bfd_target_mach_o_flavour
:
8120 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8128 #endif /* OBJ_MAYBE_ more than one */
8130 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8132 i386_elf_emit_arch_note (void)
8134 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8137 asection
*seg
= now_seg
;
8138 subsegT subseg
= now_subseg
;
8139 Elf_Internal_Note i_note
;
8140 Elf_External_Note e_note
;
8141 asection
*note_secp
;
8144 /* Create the .note section. */
8145 note_secp
= subseg_new (".note", 0);
8146 bfd_set_section_flags (stdoutput
,
8148 SEC_HAS_CONTENTS
| SEC_READONLY
);
8150 /* Process the arch string. */
8151 len
= strlen (cpu_arch_name
);
8153 i_note
.namesz
= len
+ 1;
8155 i_note
.type
= NT_ARCH
;
8156 p
= frag_more (sizeof (e_note
.namesz
));
8157 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8158 p
= frag_more (sizeof (e_note
.descsz
));
8159 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8160 p
= frag_more (sizeof (e_note
.type
));
8161 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8162 p
= frag_more (len
+ 1);
8163 strcpy (p
, cpu_arch_name
);
8165 frag_align (2, 0, 0);
8167 subseg_set (seg
, subseg
);
8173 md_undefined_symbol (name
)
8176 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8177 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8178 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8179 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8183 if (symbol_find (name
))
8184 as_bad (_("GOT already in symbol table"));
8185 GOT_symbol
= symbol_new (name
, undefined_section
,
8186 (valueT
) 0, &zero_address_frag
);
8193 /* Round up a section size to the appropriate boundary. */
8196 md_section_align (segment
, size
)
8197 segT segment ATTRIBUTE_UNUSED
;
8200 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8201 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8203 /* For a.out, force the section size to be aligned. If we don't do
8204 this, BFD will align it for us, but it will not write out the
8205 final bytes of the section. This may be a bug in BFD, but it is
8206 easier to fix it here since that is how the other a.out targets
8210 align
= bfd_get_section_alignment (stdoutput
, segment
);
8211 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8218 /* On the i386, PC-relative offsets are relative to the start of the
8219 next instruction. That is, the address of the offset, plus its
8220 size, since the offset is always the last part of the insn. */
8223 md_pcrel_from (fixS
*fixP
)
8225 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8231 s_bss (int ignore ATTRIBUTE_UNUSED
)
8235 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8237 obj_elf_section_change_hook ();
8239 temp
= get_absolute_expression ();
8240 subseg_set (bss_section
, (subsegT
) temp
);
8241 demand_empty_rest_of_line ();
8247 i386_validate_fix (fixS
*fixp
)
8249 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8251 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8255 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8260 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8262 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8269 tc_gen_reloc (section
, fixp
)
8270 asection
*section ATTRIBUTE_UNUSED
;
8274 bfd_reloc_code_real_type code
;
8276 switch (fixp
->fx_r_type
)
8278 case BFD_RELOC_X86_64_PLT32
:
8279 case BFD_RELOC_X86_64_GOT32
:
8280 case BFD_RELOC_X86_64_GOTPCREL
:
8281 case BFD_RELOC_386_PLT32
:
8282 case BFD_RELOC_386_GOT32
:
8283 case BFD_RELOC_386_GOTOFF
:
8284 case BFD_RELOC_386_GOTPC
:
8285 case BFD_RELOC_386_TLS_GD
:
8286 case BFD_RELOC_386_TLS_LDM
:
8287 case BFD_RELOC_386_TLS_LDO_32
:
8288 case BFD_RELOC_386_TLS_IE_32
:
8289 case BFD_RELOC_386_TLS_IE
:
8290 case BFD_RELOC_386_TLS_GOTIE
:
8291 case BFD_RELOC_386_TLS_LE_32
:
8292 case BFD_RELOC_386_TLS_LE
:
8293 case BFD_RELOC_386_TLS_GOTDESC
:
8294 case BFD_RELOC_386_TLS_DESC_CALL
:
8295 case BFD_RELOC_X86_64_TLSGD
:
8296 case BFD_RELOC_X86_64_TLSLD
:
8297 case BFD_RELOC_X86_64_DTPOFF32
:
8298 case BFD_RELOC_X86_64_DTPOFF64
:
8299 case BFD_RELOC_X86_64_GOTTPOFF
:
8300 case BFD_RELOC_X86_64_TPOFF32
:
8301 case BFD_RELOC_X86_64_TPOFF64
:
8302 case BFD_RELOC_X86_64_GOTOFF64
:
8303 case BFD_RELOC_X86_64_GOTPC32
:
8304 case BFD_RELOC_X86_64_GOT64
:
8305 case BFD_RELOC_X86_64_GOTPCREL64
:
8306 case BFD_RELOC_X86_64_GOTPC64
:
8307 case BFD_RELOC_X86_64_GOTPLT64
:
8308 case BFD_RELOC_X86_64_PLTOFF64
:
8309 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8310 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8312 case BFD_RELOC_VTABLE_ENTRY
:
8313 case BFD_RELOC_VTABLE_INHERIT
:
8315 case BFD_RELOC_32_SECREL
:
8317 code
= fixp
->fx_r_type
;
8319 case BFD_RELOC_X86_64_32S
:
8320 if (!fixp
->fx_pcrel
)
8322 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8323 code
= fixp
->fx_r_type
;
8329 switch (fixp
->fx_size
)
8332 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8333 _("can not do %d byte pc-relative relocation"),
8335 code
= BFD_RELOC_32_PCREL
;
8337 case 1: code
= BFD_RELOC_8_PCREL
; break;
8338 case 2: code
= BFD_RELOC_16_PCREL
; break;
8339 case 4: code
= BFD_RELOC_32_PCREL
; break;
8341 case 8: code
= BFD_RELOC_64_PCREL
; break;
8347 switch (fixp
->fx_size
)
8350 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8351 _("can not do %d byte relocation"),
8353 code
= BFD_RELOC_32
;
8355 case 1: code
= BFD_RELOC_8
; break;
8356 case 2: code
= BFD_RELOC_16
; break;
8357 case 4: code
= BFD_RELOC_32
; break;
8359 case 8: code
= BFD_RELOC_64
; break;
8366 if ((code
== BFD_RELOC_32
8367 || code
== BFD_RELOC_32_PCREL
8368 || code
== BFD_RELOC_X86_64_32S
)
8370 && fixp
->fx_addsy
== GOT_symbol
)
8373 code
= BFD_RELOC_386_GOTPC
;
8375 code
= BFD_RELOC_X86_64_GOTPC32
;
8377 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8379 && fixp
->fx_addsy
== GOT_symbol
)
8381 code
= BFD_RELOC_X86_64_GOTPC64
;
8384 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8385 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8386 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8388 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8390 if (!use_rela_relocations
)
8392 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8393 vtable entry to be used in the relocation's section offset. */
8394 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8395 rel
->address
= fixp
->fx_offset
;
8396 #if defined (OBJ_COFF) && defined (TE_PE)
8397 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8398 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8403 /* Use the rela in 64bit mode. */
8406 if (!fixp
->fx_pcrel
)
8407 rel
->addend
= fixp
->fx_offset
;
8411 case BFD_RELOC_X86_64_PLT32
:
8412 case BFD_RELOC_X86_64_GOT32
:
8413 case BFD_RELOC_X86_64_GOTPCREL
:
8414 case BFD_RELOC_X86_64_TLSGD
:
8415 case BFD_RELOC_X86_64_TLSLD
:
8416 case BFD_RELOC_X86_64_GOTTPOFF
:
8417 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8418 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8419 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8422 rel
->addend
= (section
->vma
8424 + fixp
->fx_addnumber
8425 + md_pcrel_from (fixp
));
8430 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8431 if (rel
->howto
== NULL
)
8433 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8434 _("cannot represent relocation type %s"),
8435 bfd_get_reloc_code_name (code
));
8436 /* Set howto to a garbage value so that we can keep going. */
8437 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8438 gas_assert (rel
->howto
!= NULL
);
8444 #include "tc-i386-intel.c"
8447 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8449 int saved_naked_reg
;
8450 char saved_register_dot
;
8452 saved_naked_reg
= allow_naked_reg
;
8453 allow_naked_reg
= 1;
8454 saved_register_dot
= register_chars
['.'];
8455 register_chars
['.'] = '.';
8456 allow_pseudo_reg
= 1;
8457 expression_and_evaluate (exp
);
8458 allow_pseudo_reg
= 0;
8459 register_chars
['.'] = saved_register_dot
;
8460 allow_naked_reg
= saved_naked_reg
;
8462 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8464 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8466 exp
->X_op
= O_constant
;
8467 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8468 .dw2_regnum
[flag_code
>> 1];
8471 exp
->X_op
= O_illegal
;
8476 tc_x86_frame_initial_instructions (void)
8478 static unsigned int sp_regno
[2];
8480 if (!sp_regno
[flag_code
>> 1])
8482 char *saved_input
= input_line_pointer
;
8483 char sp
[][4] = {"esp", "rsp"};
8486 input_line_pointer
= sp
[flag_code
>> 1];
8487 tc_x86_parse_to_dw2regnum (&exp
);
8488 gas_assert (exp
.X_op
== O_constant
);
8489 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8490 input_line_pointer
= saved_input
;
8493 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8494 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8498 i386_elf_section_type (const char *str
, size_t len
)
8500 if (flag_code
== CODE_64BIT
8501 && len
== sizeof ("unwind") - 1
8502 && strncmp (str
, "unwind", 6) == 0)
8503 return SHT_X86_64_UNWIND
;
8510 i386_solaris_fix_up_eh_frame (segT sec
)
8512 if (flag_code
== CODE_64BIT
)
8513 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8519 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8523 expr
.X_op
= O_secrel
;
8524 expr
.X_add_symbol
= symbol
;
8525 expr
.X_add_number
= 0;
8526 emit_expr (&expr
, size
);
8530 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8531 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8534 x86_64_section_letter (int letter
, char **ptr_msg
)
8536 if (flag_code
== CODE_64BIT
)
8539 return SHF_X86_64_LARGE
;
8541 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8544 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8549 x86_64_section_word (char *str
, size_t len
)
8551 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8552 return SHF_X86_64_LARGE
;
8558 handle_large_common (int small ATTRIBUTE_UNUSED
)
8560 if (flag_code
!= CODE_64BIT
)
8562 s_comm_internal (0, elf_common_parse
);
8563 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8567 static segT lbss_section
;
8568 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8569 asection
*saved_bss_section
= bss_section
;
8571 if (lbss_section
== NULL
)
8573 flagword applicable
;
8575 subsegT subseg
= now_subseg
;
8577 /* The .lbss section is for local .largecomm symbols. */
8578 lbss_section
= subseg_new (".lbss", 0);
8579 applicable
= bfd_applicable_section_flags (stdoutput
);
8580 bfd_set_section_flags (stdoutput
, lbss_section
,
8581 applicable
& SEC_ALLOC
);
8582 seg_info (lbss_section
)->bss
= 1;
8584 subseg_set (seg
, subseg
);
8587 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8588 bss_section
= lbss_section
;
8590 s_comm_internal (0, elf_common_parse
);
8592 elf_com_section_ptr
= saved_com_section_ptr
;
8593 bss_section
= saved_bss_section
;
8596 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */