1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 enum processor_type type
; /* arch type */
132 i386_cpu_flags flags
; /* cpu feature flags */
136 static void set_code_flag (int);
137 static void set_16bit_gcc_code_flag (int);
138 static void set_intel_syntax (int);
139 static void set_intel_mnemonic (int);
140 static void set_allow_index_reg (int);
141 static void set_sse_check (int);
142 static void set_cpu_arch (int);
144 static void pe_directive_secrel (int);
146 static void signed_cons (int);
147 static char *output_invalid (int c
);
148 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
150 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
152 static int i386_att_operand (char *);
153 static int i386_intel_operand (char *, int);
154 static int i386_intel_simplify (expressionS
*);
155 static int i386_intel_parse_name (const char *, expressionS
*);
156 static const reg_entry
*parse_register (char *, char **);
157 static char *parse_insn (char *, char *);
158 static char *parse_operands (char *, const char *);
159 static void swap_operands (void);
160 static void swap_2_operands (int, int);
161 static void optimize_imm (void);
162 static void optimize_disp (void);
163 static const insn_template
*match_template (void);
164 static int check_string (void);
165 static int process_suffix (void);
166 static int check_byte_reg (void);
167 static int check_long_reg (void);
168 static int check_qword_reg (void);
169 static int check_word_reg (void);
170 static int finalize_imm (void);
171 static int process_operands (void);
172 static const seg_entry
*build_modrm_byte (void);
173 static void output_insn (void);
174 static void output_imm (fragS
*, offsetT
);
175 static void output_disp (fragS
*, offsetT
);
177 static void s_bss (int);
179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
180 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
183 static const char *default_arch
= DEFAULT_ARCH
;
188 /* VEX prefix is either 2 byte or 3 byte. */
189 unsigned char bytes
[3];
191 /* Destination or source register specifier. */
192 const reg_entry
*register_specifier
;
195 /* 'md_assemble ()' gathers together information and puts it into a
202 const reg_entry
*regs
;
207 /* TM holds the template for the insn were currently assembling. */
210 /* SUFFIX holds the instruction size suffix for byte, word, dword
211 or qword, if given. */
214 /* OPERANDS gives the number of given operands. */
215 unsigned int operands
;
217 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
218 of given register, displacement, memory operands and immediate
220 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
222 /* TYPES [i] is the type (see above #defines) which tells us how to
223 use OP[i] for the corresponding operand. */
224 i386_operand_type types
[MAX_OPERANDS
];
226 /* Displacement expression, immediate expression, or register for each
228 union i386_op op
[MAX_OPERANDS
];
230 /* Flags for operands. */
231 unsigned int flags
[MAX_OPERANDS
];
232 #define Operand_PCrel 1
234 /* Relocation type for operand */
235 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
237 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
238 the base index byte below. */
239 const reg_entry
*base_reg
;
240 const reg_entry
*index_reg
;
241 unsigned int log2_scale_factor
;
243 /* SEG gives the seg_entries of this insn. They are zero unless
244 explicit segment overrides are given. */
245 const seg_entry
*seg
[2];
247 /* PREFIX holds all the given prefix opcodes (usually null).
248 PREFIXES is the number of prefix opcodes. */
249 unsigned int prefixes
;
250 unsigned char prefix
[MAX_PREFIXES
];
252 /* RM and SIB are the modrm byte and the sib byte where the
253 addressing modes of this insn are encoded. */
259 /* Swap operand in encoding. */
260 unsigned int swap_operand
;
263 typedef struct _i386_insn i386_insn
;
265 /* List of chars besides those in app.c:symbol_chars that can start an
266 operand. Used to prevent the scrubber eating vital white-space. */
267 const char extra_symbol_chars
[] = "*%-(["
276 #if (defined (TE_I386AIX) \
277 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
278 && !defined (TE_GNU) \
279 && !defined (TE_LINUX) \
280 && !defined (TE_NETWARE) \
281 && !defined (TE_FreeBSD) \
282 && !defined (TE_NetBSD)))
283 /* This array holds the chars that always start a comment. If the
284 pre-processor is disabled, these aren't very useful. The option
285 --divide will remove '/' from this list. */
286 const char *i386_comment_chars
= "#/";
287 #define SVR4_COMMENT_CHARS 1
288 #define PREFIX_SEPARATOR '\\'
291 const char *i386_comment_chars
= "#";
292 #define PREFIX_SEPARATOR '/'
295 /* This array holds the chars that only start a comment at the beginning of
296 a line. If the line seems to have the form '# 123 filename'
297 .line and .file directives will appear in the pre-processed output.
298 Note that input_file.c hand checks for '#' at the beginning of the
299 first line of the input file. This is because the compiler outputs
300 #NO_APP at the beginning of its output.
301 Also note that comments started like this one will always work if
302 '/' isn't otherwise defined. */
303 const char line_comment_chars
[] = "#/";
305 const char line_separator_chars
[] = ";";
307 /* Chars that can be used to separate mant from exp in floating point
309 const char EXP_CHARS
[] = "eE";
311 /* Chars that mean this number is a floating point constant
314 const char FLT_CHARS
[] = "fFdDxX";
316 /* Tables for lexical analysis. */
317 static char mnemonic_chars
[256];
318 static char register_chars
[256];
319 static char operand_chars
[256];
320 static char identifier_chars
[256];
321 static char digit_chars
[256];
323 /* Lexical macros. */
324 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
325 #define is_operand_char(x) (operand_chars[(unsigned char) x])
326 #define is_register_char(x) (register_chars[(unsigned char) x])
327 #define is_space_char(x) ((x) == ' ')
328 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
329 #define is_digit_char(x) (digit_chars[(unsigned char) x])
331 /* All non-digit non-letter characters that may occur in an operand. */
332 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
334 /* md_assemble() always leaves the strings it's passed unaltered. To
335 effect this we maintain a stack of saved characters that we've smashed
336 with '\0's (indicating end of strings for various sub-fields of the
337 assembler instruction). */
338 static char save_stack
[32];
339 static char *save_stack_p
;
340 #define END_STRING_AND_SAVE(s) \
341 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
342 #define RESTORE_END_STRING(s) \
343 do { *(s) = *--save_stack_p; } while (0)
345 /* The instruction we're assembling. */
348 /* Possible templates for current insn. */
349 static const templates
*current_templates
;
351 /* Per instruction expressionS buffers: max displacements & immediates. */
352 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
353 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
355 /* Current operand we are working on. */
356 static int this_operand
= -1;
358 /* We support four different modes. FLAG_CODE variable is used to distinguish
366 static enum flag_code flag_code
;
367 static unsigned int object_64bit
;
368 static int use_rela_relocations
= 0;
370 /* The names used to print error messages. */
371 static const char *flag_code_names
[] =
378 /* 1 for intel syntax,
380 static int intel_syntax
= 0;
382 /* 1 for intel mnemonic,
383 0 if att mnemonic. */
384 static int intel_mnemonic
= !SYSV386_COMPAT
;
386 /* 1 if support old (<= 2.8.1) versions of gcc. */
387 static int old_gcc
= OLDGCC_COMPAT
;
389 /* 1 if pseudo registers are permitted. */
390 static int allow_pseudo_reg
= 0;
392 /* 1 if register prefix % not required. */
393 static int allow_naked_reg
= 0;
395 /* 1 if pseudo index register, eiz/riz, is allowed . */
396 static int allow_index_reg
= 0;
406 /* Register prefix used for error message. */
407 static const char *register_prefix
= "%";
409 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
410 leave, push, and pop instructions so that gcc has the same stack
411 frame as in 32 bit mode. */
412 static char stackop_size
= '\0';
414 /* Non-zero to optimize code alignment. */
415 int optimize_align_code
= 1;
417 /* Non-zero to quieten some warnings. */
418 static int quiet_warnings
= 0;
421 static const char *cpu_arch_name
= NULL
;
422 static char *cpu_sub_arch_name
= NULL
;
424 /* CPU feature flags. */
425 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
427 /* If we have selected a cpu we are generating instructions for. */
428 static int cpu_arch_tune_set
= 0;
430 /* Cpu we are generating instructions for. */
431 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
433 /* CPU feature flags of cpu we are generating instructions for. */
434 static i386_cpu_flags cpu_arch_tune_flags
;
436 /* CPU instruction set architecture used. */
437 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
439 /* CPU feature flags of instruction set architecture used. */
440 i386_cpu_flags cpu_arch_isa_flags
;
442 /* If set, conditional jumps are not automatically promoted to handle
443 larger than a byte offset. */
444 static unsigned int no_cond_jump_promotion
= 0;
446 /* Encode SSE instructions with VEX prefix. */
447 static unsigned int sse2avx
;
449 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
450 static symbolS
*GOT_symbol
;
452 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
453 unsigned int x86_dwarf2_return_column
;
455 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
456 int x86_cie_data_alignment
;
458 /* Interface to relax_segment.
459 There are 3 major relax states for 386 jump insns because the
460 different types of jumps add different sizes to frags when we're
461 figuring out what sort of jump to choose to reach a given label. */
464 #define UNCOND_JUMP 0
466 #define COND_JUMP86 2
471 #define SMALL16 (SMALL | CODE16)
473 #define BIG16 (BIG | CODE16)
477 #define INLINE __inline__
483 #define ENCODE_RELAX_STATE(type, size) \
484 ((relax_substateT) (((type) << 2) | (size)))
485 #define TYPE_FROM_RELAX_STATE(s) \
487 #define DISP_SIZE_FROM_RELAX_STATE(s) \
488 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
490 /* This table is used by relax_frag to promote short jumps to long
491 ones where necessary. SMALL (short) jumps may be promoted to BIG
492 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
493 don't allow a short jump in a 32 bit code segment to be promoted to
494 a 16 bit offset jump because it's slower (requires data size
495 prefix), and doesn't work, unless the destination is in the bottom
496 64k of the code segment (The top 16 bits of eip are zeroed). */
498 const relax_typeS md_relax_table
[] =
501 1) most positive reach of this state,
502 2) most negative reach of this state,
503 3) how many bytes this mode will have in the variable part of the frag
504 4) which index into the table to try if we can't fit into this one. */
506 /* UNCOND_JUMP states. */
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
508 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
509 /* dword jmp adds 4 bytes to frag:
510 0 extra opcode bytes, 4 displacement bytes. */
512 /* word jmp adds 2 byte2 to frag:
513 0 extra opcode bytes, 2 displacement bytes. */
516 /* COND_JUMP states. */
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
518 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
519 /* dword conditionals adds 5 bytes to frag:
520 1 extra opcode byte, 4 displacement bytes. */
522 /* word conditionals add 3 bytes to frag:
523 1 extra opcode byte, 2 displacement bytes. */
526 /* COND_JUMP86 states. */
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
528 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
529 /* dword conditionals adds 5 bytes to frag:
530 1 extra opcode byte, 4 displacement bytes. */
532 /* word conditionals add 4 bytes to frag:
533 1 displacement byte and a 3 byte long branch insn. */
537 static const arch_entry cpu_arch
[] =
539 { "generic32", PROCESSOR_GENERIC32
,
540 CPU_GENERIC32_FLAGS
},
541 { "generic64", PROCESSOR_GENERIC64
,
542 CPU_GENERIC64_FLAGS
},
543 { "i8086", PROCESSOR_UNKNOWN
,
545 { "i186", PROCESSOR_UNKNOWN
,
547 { "i286", PROCESSOR_UNKNOWN
,
549 { "i386", PROCESSOR_I386
,
551 { "i486", PROCESSOR_I486
,
553 { "i586", PROCESSOR_PENTIUM
,
555 { "i686", PROCESSOR_PENTIUMPRO
,
557 { "pentium", PROCESSOR_PENTIUM
,
559 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
561 { "pentiumii", PROCESSOR_PENTIUMPRO
,
563 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
565 { "pentium4", PROCESSOR_PENTIUM4
,
567 { "prescott", PROCESSOR_NOCONA
,
569 { "nocona", PROCESSOR_NOCONA
,
571 { "yonah", PROCESSOR_CORE
,
573 { "core", PROCESSOR_CORE
,
575 { "merom", PROCESSOR_CORE2
,
577 { "core2", PROCESSOR_CORE2
,
579 { "corei7", PROCESSOR_COREI7
,
581 { "l1om", PROCESSOR_L1OM
,
583 { "k6", PROCESSOR_K6
,
585 { "k6_2", PROCESSOR_K6
,
587 { "athlon", PROCESSOR_ATHLON
,
589 { "sledgehammer", PROCESSOR_K8
,
591 { "opteron", PROCESSOR_K8
,
593 { "k8", PROCESSOR_K8
,
595 { "amdfam10", PROCESSOR_AMDFAM10
,
596 CPU_AMDFAM10_FLAGS
},
597 { ".8087", PROCESSOR_UNKNOWN
,
599 { ".287", PROCESSOR_UNKNOWN
,
601 { ".387", PROCESSOR_UNKNOWN
,
603 { ".no87", PROCESSOR_UNKNOWN
,
605 { ".mmx", PROCESSOR_UNKNOWN
,
607 { ".nommx", PROCESSOR_UNKNOWN
,
609 { ".sse", PROCESSOR_UNKNOWN
,
611 { ".sse2", PROCESSOR_UNKNOWN
,
613 { ".sse3", PROCESSOR_UNKNOWN
,
615 { ".ssse3", PROCESSOR_UNKNOWN
,
617 { ".sse4.1", PROCESSOR_UNKNOWN
,
619 { ".sse4.2", PROCESSOR_UNKNOWN
,
621 { ".sse4", PROCESSOR_UNKNOWN
,
623 { ".nosse", PROCESSOR_UNKNOWN
,
625 { ".avx", PROCESSOR_UNKNOWN
,
627 { ".noavx", PROCESSOR_UNKNOWN
,
629 { ".vmx", PROCESSOR_UNKNOWN
,
631 { ".smx", PROCESSOR_UNKNOWN
,
633 { ".xsave", PROCESSOR_UNKNOWN
,
635 { ".aes", PROCESSOR_UNKNOWN
,
637 { ".pclmul", PROCESSOR_UNKNOWN
,
639 { ".clmul", PROCESSOR_UNKNOWN
,
641 { ".fma", PROCESSOR_UNKNOWN
,
643 { ".fma4", PROCESSOR_UNKNOWN
,
645 { ".xop", PROCESSOR_UNKNOWN
,
647 { ".cvt16", PROCESSOR_UNKNOWN
,
649 { ".lwp", PROCESSOR_UNKNOWN
,
651 { ".movbe", PROCESSOR_UNKNOWN
,
653 { ".ept", PROCESSOR_UNKNOWN
,
655 { ".clflush", PROCESSOR_UNKNOWN
,
657 { ".syscall", PROCESSOR_UNKNOWN
,
659 { ".rdtscp", PROCESSOR_UNKNOWN
,
661 { ".3dnow", PROCESSOR_UNKNOWN
,
663 { ".3dnowa", PROCESSOR_UNKNOWN
,
665 { ".padlock", PROCESSOR_UNKNOWN
,
667 { ".pacifica", PROCESSOR_UNKNOWN
,
669 { ".svme", PROCESSOR_UNKNOWN
,
671 { ".sse4a", PROCESSOR_UNKNOWN
,
673 { ".abm", PROCESSOR_UNKNOWN
,
678 /* Like s_lcomm_internal in gas/read.c but the alignment string
679 is allowed to be optional. */
682 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
689 && *input_line_pointer
== ',')
691 align
= parse_align (needs_align
- 1);
693 if (align
== (addressT
) -1)
708 bss_alloc (symbolP
, size
, align
);
713 pe_lcomm (int needs_align
)
715 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
719 const pseudo_typeS md_pseudo_table
[] =
721 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
722 {"align", s_align_bytes
, 0},
724 {"align", s_align_ptwo
, 0},
726 {"arch", set_cpu_arch
, 0},
730 {"lcomm", pe_lcomm
, 1},
732 {"ffloat", float_cons
, 'f'},
733 {"dfloat", float_cons
, 'd'},
734 {"tfloat", float_cons
, 'x'},
736 {"slong", signed_cons
, 4},
737 {"noopt", s_ignore
, 0},
738 {"optim", s_ignore
, 0},
739 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
740 {"code16", set_code_flag
, CODE_16BIT
},
741 {"code32", set_code_flag
, CODE_32BIT
},
742 {"code64", set_code_flag
, CODE_64BIT
},
743 {"intel_syntax", set_intel_syntax
, 1},
744 {"att_syntax", set_intel_syntax
, 0},
745 {"intel_mnemonic", set_intel_mnemonic
, 1},
746 {"att_mnemonic", set_intel_mnemonic
, 0},
747 {"allow_index_reg", set_allow_index_reg
, 1},
748 {"disallow_index_reg", set_allow_index_reg
, 0},
749 {"sse_check", set_sse_check
, 0},
750 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
751 {"largecomm", handle_large_common
, 0},
753 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
754 {"loc", dwarf2_directive_loc
, 0},
755 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
758 {"secrel32", pe_directive_secrel
, 0},
763 /* For interface with expression (). */
764 extern char *input_line_pointer
;
766 /* Hash table for instruction mnemonic lookup. */
767 static struct hash_control
*op_hash
;
769 /* Hash table for register lookup. */
770 static struct hash_control
*reg_hash
;
773 i386_align_code (fragS
*fragP
, int count
)
775 /* Various efficient no-op patterns for aligning code labels.
776 Note: Don't try to assemble the instructions in the comments.
777 0L and 0w are not legal. */
778 static const char f32_1
[] =
780 static const char f32_2
[] =
781 {0x66,0x90}; /* xchg %ax,%ax */
782 static const char f32_3
[] =
783 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
784 static const char f32_4
[] =
785 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
786 static const char f32_5
[] =
788 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
789 static const char f32_6
[] =
790 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
791 static const char f32_7
[] =
792 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
793 static const char f32_8
[] =
795 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
796 static const char f32_9
[] =
797 {0x89,0xf6, /* movl %esi,%esi */
798 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
799 static const char f32_10
[] =
800 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_11
[] =
803 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f32_12
[] =
806 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
807 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
808 static const char f32_13
[] =
809 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_14
[] =
812 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
814 static const char f16_3
[] =
815 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
816 static const char f16_4
[] =
817 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
818 static const char f16_5
[] =
820 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
821 static const char f16_6
[] =
822 {0x89,0xf6, /* mov %si,%si */
823 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
824 static const char f16_7
[] =
825 {0x8d,0x74,0x00, /* lea 0(%si),%si */
826 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
827 static const char f16_8
[] =
828 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
829 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
830 static const char jump_31
[] =
831 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
832 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
833 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
835 static const char *const f32_patt
[] = {
836 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
837 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
839 static const char *const f16_patt
[] = {
840 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
843 static const char alt_3
[] =
845 /* nopl 0(%[re]ax) */
846 static const char alt_4
[] =
847 {0x0f,0x1f,0x40,0x00};
848 /* nopl 0(%[re]ax,%[re]ax,1) */
849 static const char alt_5
[] =
850 {0x0f,0x1f,0x44,0x00,0x00};
851 /* nopw 0(%[re]ax,%[re]ax,1) */
852 static const char alt_6
[] =
853 {0x66,0x0f,0x1f,0x44,0x00,0x00};
854 /* nopl 0L(%[re]ax) */
855 static const char alt_7
[] =
856 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
857 /* nopl 0L(%[re]ax,%[re]ax,1) */
858 static const char alt_8
[] =
859 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
860 /* nopw 0L(%[re]ax,%[re]ax,1) */
861 static const char alt_9
[] =
862 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
863 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
864 static const char alt_10
[] =
865 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
867 nopw %cs:0L(%[re]ax,%[re]ax,1) */
868 static const char alt_long_11
[] =
870 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
873 nopw %cs:0L(%[re]ax,%[re]ax,1) */
874 static const char alt_long_12
[] =
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_13
[] =
886 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
891 nopw %cs:0L(%[re]ax,%[re]ax,1) */
892 static const char alt_long_14
[] =
897 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_long_15
[] =
910 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 /* nopl 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_11
[] =
914 {0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
917 nopw 0(%[re]ax,%[re]ax,1) */
918 static const char alt_short_12
[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x66,0x0f,0x1f,0x44,0x00,0x00};
921 /* nopw 0(%[re]ax,%[re]ax,1)
923 static const char alt_short_13
[] =
924 {0x66,0x0f,0x1f,0x44,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
928 static const char alt_short_14
[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
932 nopl 0L(%[re]ax,%[re]ax,1) */
933 static const char alt_short_15
[] =
934 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
935 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
936 static const char *const alt_short_patt
[] = {
937 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
938 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
939 alt_short_14
, alt_short_15
941 static const char *const alt_long_patt
[] = {
942 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
943 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
944 alt_long_14
, alt_long_15
947 /* Only align for at least a positive non-zero boundary. */
948 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
951 /* We need to decide which NOP sequence to use for 32bit and
952 64bit. When -mtune= is used:
954 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
955 PROCESSOR_GENERIC32, f32_patt will be used.
956 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
957 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
958 PROCESSOR_GENERIC64, alt_long_patt will be used.
959 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
960 PROCESSOR_AMDFAM10, alt_short_patt will be used.
962 When -mtune= isn't used, alt_long_patt will be used if
963 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
966 When -march= or .arch is used, we can't use anything beyond
967 cpu_arch_isa_flags. */
969 if (flag_code
== CODE_16BIT
)
973 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
975 /* Adjust jump offset. */
976 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
979 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
980 f16_patt
[count
- 1], count
);
984 const char *const *patt
= NULL
;
986 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
988 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
989 switch (cpu_arch_tune
)
991 case PROCESSOR_UNKNOWN
:
992 /* We use cpu_arch_isa_flags to check if we SHOULD
993 optimize for Cpu686. */
994 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
995 patt
= alt_long_patt
;
999 case PROCESSOR_PENTIUMPRO
:
1000 case PROCESSOR_PENTIUM4
:
1001 case PROCESSOR_NOCONA
:
1002 case PROCESSOR_CORE
:
1003 case PROCESSOR_CORE2
:
1004 case PROCESSOR_COREI7
:
1005 case PROCESSOR_L1OM
:
1006 case PROCESSOR_GENERIC64
:
1007 patt
= alt_long_patt
;
1010 case PROCESSOR_ATHLON
:
1012 case PROCESSOR_AMDFAM10
:
1013 patt
= alt_short_patt
;
1015 case PROCESSOR_I386
:
1016 case PROCESSOR_I486
:
1017 case PROCESSOR_PENTIUM
:
1018 case PROCESSOR_GENERIC32
:
1025 switch (fragP
->tc_frag_data
.tune
)
1027 case PROCESSOR_UNKNOWN
:
1028 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1029 PROCESSOR_UNKNOWN. */
1033 case PROCESSOR_I386
:
1034 case PROCESSOR_I486
:
1035 case PROCESSOR_PENTIUM
:
1037 case PROCESSOR_ATHLON
:
1039 case PROCESSOR_AMDFAM10
:
1040 case PROCESSOR_GENERIC32
:
1041 /* We use cpu_arch_isa_flags to check if we CAN optimize
1043 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1044 patt
= alt_short_patt
;
1048 case PROCESSOR_PENTIUMPRO
:
1049 case PROCESSOR_PENTIUM4
:
1050 case PROCESSOR_NOCONA
:
1051 case PROCESSOR_CORE
:
1052 case PROCESSOR_CORE2
:
1053 case PROCESSOR_COREI7
:
1054 case PROCESSOR_L1OM
:
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1066 if (patt
== f32_patt
)
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1073 /* For 64bit, the limit is 3 bytes. */
1074 if (flag_code
== CODE_64BIT
1075 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1080 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1081 patt
[count
- 1], count
);
1084 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1086 /* Adjust jump offset. */
1087 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1092 /* Maximum length of an instruction is 15 byte. If the
1093 padding is greater than 15 bytes and we don't use jump,
1094 we have to break it into smaller pieces. */
1095 int padding
= count
;
1096 while (padding
> 15)
1099 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1104 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1105 patt
[padding
- 1], padding
);
1108 fragP
->fr_var
= count
;
1112 operand_type_all_zero (const union i386_operand_type
*x
)
1114 switch (ARRAY_SIZE(x
->array
))
1123 return !x
->array
[0];
1130 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1132 switch (ARRAY_SIZE(x
->array
))
1147 operand_type_equal (const union i386_operand_type
*x
,
1148 const union i386_operand_type
*y
)
1150 switch (ARRAY_SIZE(x
->array
))
1153 if (x
->array
[2] != y
->array
[2])
1156 if (x
->array
[1] != y
->array
[1])
1159 return x
->array
[0] == y
->array
[0];
1167 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1169 switch (ARRAY_SIZE(x
->array
))
1178 return !x
->array
[0];
1185 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1187 switch (ARRAY_SIZE(x
->array
))
1202 cpu_flags_equal (const union i386_cpu_flags
*x
,
1203 const union i386_cpu_flags
*y
)
1205 switch (ARRAY_SIZE(x
->array
))
1208 if (x
->array
[2] != y
->array
[2])
1211 if (x
->array
[1] != y
->array
[1])
1214 return x
->array
[0] == y
->array
[0];
1222 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1224 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1225 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1228 static INLINE i386_cpu_flags
1229 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1231 switch (ARRAY_SIZE (x
.array
))
1234 x
.array
[2] &= y
.array
[2];
1236 x
.array
[1] &= y
.array
[1];
1238 x
.array
[0] &= y
.array
[0];
1246 static INLINE i386_cpu_flags
1247 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1249 switch (ARRAY_SIZE (x
.array
))
1252 x
.array
[2] |= y
.array
[2];
1254 x
.array
[1] |= y
.array
[1];
1256 x
.array
[0] |= y
.array
[0];
1264 static INLINE i386_cpu_flags
1265 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1267 switch (ARRAY_SIZE (x
.array
))
1270 x
.array
[2] &= ~y
.array
[2];
1272 x
.array
[1] &= ~y
.array
[1];
1274 x
.array
[0] &= ~y
.array
[0];
1282 #define CPU_FLAGS_ARCH_MATCH 0x1
1283 #define CPU_FLAGS_64BIT_MATCH 0x2
1284 #define CPU_FLAGS_AES_MATCH 0x4
1285 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1286 #define CPU_FLAGS_AVX_MATCH 0x10
1288 #define CPU_FLAGS_32BIT_MATCH \
1289 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1290 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1291 #define CPU_FLAGS_PERFECT_MATCH \
1292 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1294 /* Return CPU flags match bits. */
1297 cpu_flags_match (const insn_template
*t
)
1299 i386_cpu_flags x
= t
->cpu_flags
;
1300 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1302 x
.bitfield
.cpu64
= 0;
1303 x
.bitfield
.cpuno64
= 0;
1305 if (cpu_flags_all_zero (&x
))
1307 /* This instruction is available on all archs. */
1308 match
|= CPU_FLAGS_32BIT_MATCH
;
1312 /* This instruction is available only on some archs. */
1313 i386_cpu_flags cpu
= cpu_arch_flags
;
1315 cpu
.bitfield
.cpu64
= 0;
1316 cpu
.bitfield
.cpuno64
= 0;
1317 cpu
= cpu_flags_and (x
, cpu
);
1318 if (!cpu_flags_all_zero (&cpu
))
1320 if (x
.bitfield
.cpuavx
)
1322 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1323 if (cpu
.bitfield
.cpuavx
)
1325 /* Check SSE2AVX. */
1326 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1328 match
|= (CPU_FLAGS_ARCH_MATCH
1329 | CPU_FLAGS_AVX_MATCH
);
1331 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1332 match
|= CPU_FLAGS_AES_MATCH
;
1334 if (!x
.bitfield
.cpupclmul
1335 || cpu
.bitfield
.cpupclmul
)
1336 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1340 match
|= CPU_FLAGS_ARCH_MATCH
;
1343 match
|= CPU_FLAGS_32BIT_MATCH
;
1349 static INLINE i386_operand_type
1350 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1352 switch (ARRAY_SIZE (x
.array
))
1355 x
.array
[2] &= y
.array
[2];
1357 x
.array
[1] &= y
.array
[1];
1359 x
.array
[0] &= y
.array
[0];
1367 static INLINE i386_operand_type
1368 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1370 switch (ARRAY_SIZE (x
.array
))
1373 x
.array
[2] |= y
.array
[2];
1375 x
.array
[1] |= y
.array
[1];
1377 x
.array
[0] |= y
.array
[0];
1385 static INLINE i386_operand_type
1386 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1388 switch (ARRAY_SIZE (x
.array
))
1391 x
.array
[2] ^= y
.array
[2];
1393 x
.array
[1] ^= y
.array
[1];
1395 x
.array
[0] ^= y
.array
[0];
1403 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1404 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1405 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1406 static const i386_operand_type inoutportreg
1407 = OPERAND_TYPE_INOUTPORTREG
;
1408 static const i386_operand_type reg16_inoutportreg
1409 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1410 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1411 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1412 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1413 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1414 static const i386_operand_type anydisp
1415 = OPERAND_TYPE_ANYDISP
;
1416 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1417 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1418 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1419 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1420 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1421 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1422 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1423 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1424 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1425 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1426 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1437 operand_type_check (i386_operand_type t
, enum operand_type c
)
1442 return (t
.bitfield
.reg8
1445 || t
.bitfield
.reg64
);
1448 return (t
.bitfield
.imm8
1452 || t
.bitfield
.imm32s
1453 || t
.bitfield
.imm64
);
1456 return (t
.bitfield
.disp8
1457 || t
.bitfield
.disp16
1458 || t
.bitfield
.disp32
1459 || t
.bitfield
.disp32s
1460 || t
.bitfield
.disp64
);
1463 return (t
.bitfield
.disp8
1464 || t
.bitfield
.disp16
1465 || t
.bitfield
.disp32
1466 || t
.bitfield
.disp32s
1467 || t
.bitfield
.disp64
1468 || t
.bitfield
.baseindex
);
1477 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1478 operand J for instruction template T. */
1481 match_reg_size (const insn_template
*t
, unsigned int j
)
1483 return !((i
.types
[j
].bitfield
.byte
1484 && !t
->operand_types
[j
].bitfield
.byte
)
1485 || (i
.types
[j
].bitfield
.word
1486 && !t
->operand_types
[j
].bitfield
.word
)
1487 || (i
.types
[j
].bitfield
.dword
1488 && !t
->operand_types
[j
].bitfield
.dword
)
1489 || (i
.types
[j
].bitfield
.qword
1490 && !t
->operand_types
[j
].bitfield
.qword
));
1493 /* Return 1 if there is no conflict in any size on operand J for
1494 instruction template T. */
1497 match_mem_size (const insn_template
*t
, unsigned int j
)
1499 return (match_reg_size (t
, j
)
1500 && !((i
.types
[j
].bitfield
.unspecified
1501 && !t
->operand_types
[j
].bitfield
.unspecified
)
1502 || (i
.types
[j
].bitfield
.fword
1503 && !t
->operand_types
[j
].bitfield
.fword
)
1504 || (i
.types
[j
].bitfield
.tbyte
1505 && !t
->operand_types
[j
].bitfield
.tbyte
)
1506 || (i
.types
[j
].bitfield
.xmmword
1507 && !t
->operand_types
[j
].bitfield
.xmmword
)
1508 || (i
.types
[j
].bitfield
.ymmword
1509 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1512 /* Return 1 if there is no size conflict on any operands for
1513 instruction template T. */
1516 operand_size_match (const insn_template
*t
)
1521 /* Don't check jump instructions. */
1522 if (t
->opcode_modifier
.jump
1523 || t
->opcode_modifier
.jumpbyte
1524 || t
->opcode_modifier
.jumpdword
1525 || t
->opcode_modifier
.jumpintersegment
)
1528 /* Check memory and accumulator operand size. */
1529 for (j
= 0; j
< i
.operands
; j
++)
1531 if (t
->operand_types
[j
].bitfield
.anysize
)
1534 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1540 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1548 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1551 /* Check reverse. */
1552 gas_assert (i
.operands
== 2);
1555 for (j
= 0; j
< 2; j
++)
1557 if (t
->operand_types
[j
].bitfield
.acc
1558 && !match_reg_size (t
, j
? 0 : 1))
1564 if (i
.types
[j
].bitfield
.mem
1565 && !match_mem_size (t
, j
? 0 : 1))
1576 operand_type_match (i386_operand_type overlap
,
1577 i386_operand_type given
)
1579 i386_operand_type temp
= overlap
;
1581 temp
.bitfield
.jumpabsolute
= 0;
1582 temp
.bitfield
.unspecified
= 0;
1583 temp
.bitfield
.byte
= 0;
1584 temp
.bitfield
.word
= 0;
1585 temp
.bitfield
.dword
= 0;
1586 temp
.bitfield
.fword
= 0;
1587 temp
.bitfield
.qword
= 0;
1588 temp
.bitfield
.tbyte
= 0;
1589 temp
.bitfield
.xmmword
= 0;
1590 temp
.bitfield
.ymmword
= 0;
1591 if (operand_type_all_zero (&temp
))
1594 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1595 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1598 /* If given types g0 and g1 are registers they must be of the same type
1599 unless the expected operand type register overlap is null.
1600 Note that Acc in a template matches every size of reg. */
1603 operand_type_register_match (i386_operand_type m0
,
1604 i386_operand_type g0
,
1605 i386_operand_type t0
,
1606 i386_operand_type m1
,
1607 i386_operand_type g1
,
1608 i386_operand_type t1
)
1610 if (!operand_type_check (g0
, reg
))
1613 if (!operand_type_check (g1
, reg
))
1616 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1617 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1618 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1619 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1622 if (m0
.bitfield
.acc
)
1624 t0
.bitfield
.reg8
= 1;
1625 t0
.bitfield
.reg16
= 1;
1626 t0
.bitfield
.reg32
= 1;
1627 t0
.bitfield
.reg64
= 1;
1630 if (m1
.bitfield
.acc
)
1632 t1
.bitfield
.reg8
= 1;
1633 t1
.bitfield
.reg16
= 1;
1634 t1
.bitfield
.reg32
= 1;
1635 t1
.bitfield
.reg64
= 1;
1638 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1639 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1640 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1641 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1644 static INLINE
unsigned int
1645 mode_from_disp_size (i386_operand_type t
)
1647 if (t
.bitfield
.disp8
)
1649 else if (t
.bitfield
.disp16
1650 || t
.bitfield
.disp32
1651 || t
.bitfield
.disp32s
)
1658 fits_in_signed_byte (offsetT num
)
1660 return (num
>= -128) && (num
<= 127);
1664 fits_in_unsigned_byte (offsetT num
)
1666 return (num
& 0xff) == num
;
1670 fits_in_unsigned_word (offsetT num
)
1672 return (num
& 0xffff) == num
;
1676 fits_in_signed_word (offsetT num
)
1678 return (-32768 <= num
) && (num
<= 32767);
1682 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1687 return (!(((offsetT
) -1 << 31) & num
)
1688 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1690 } /* fits_in_signed_long() */
1693 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1698 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1700 } /* fits_in_unsigned_long() */
1702 static i386_operand_type
1703 smallest_imm_type (offsetT num
)
1705 i386_operand_type t
;
1707 operand_type_set (&t
, 0);
1708 t
.bitfield
.imm64
= 1;
1710 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1712 /* This code is disabled on the 486 because all the Imm1 forms
1713 in the opcode table are slower on the i486. They're the
1714 versions with the implicitly specified single-position
1715 displacement, which has another syntax if you really want to
1717 t
.bitfield
.imm1
= 1;
1718 t
.bitfield
.imm8
= 1;
1719 t
.bitfield
.imm8s
= 1;
1720 t
.bitfield
.imm16
= 1;
1721 t
.bitfield
.imm32
= 1;
1722 t
.bitfield
.imm32s
= 1;
1724 else if (fits_in_signed_byte (num
))
1726 t
.bitfield
.imm8
= 1;
1727 t
.bitfield
.imm8s
= 1;
1728 t
.bitfield
.imm16
= 1;
1729 t
.bitfield
.imm32
= 1;
1730 t
.bitfield
.imm32s
= 1;
1732 else if (fits_in_unsigned_byte (num
))
1734 t
.bitfield
.imm8
= 1;
1735 t
.bitfield
.imm16
= 1;
1736 t
.bitfield
.imm32
= 1;
1737 t
.bitfield
.imm32s
= 1;
1739 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1741 t
.bitfield
.imm16
= 1;
1742 t
.bitfield
.imm32
= 1;
1743 t
.bitfield
.imm32s
= 1;
1745 else if (fits_in_signed_long (num
))
1747 t
.bitfield
.imm32
= 1;
1748 t
.bitfield
.imm32s
= 1;
1750 else if (fits_in_unsigned_long (num
))
1751 t
.bitfield
.imm32
= 1;
1757 offset_in_range (offsetT val
, int size
)
1763 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1764 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1765 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1767 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1773 /* If BFD64, sign extend val for 32bit address mode. */
1774 if (flag_code
!= CODE_64BIT
1775 || i
.prefix
[ADDR_PREFIX
])
1776 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1777 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1780 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1782 char buf1
[40], buf2
[40];
1784 sprint_value (buf1
, val
);
1785 sprint_value (buf2
, val
& mask
);
1786 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1800 a. PREFIX_EXIST if attempting to add a prefix where one from the
1801 same class already exists.
1802 b. PREFIX_LOCK if lock prefix is added.
1803 c. PREFIX_REP if rep/repne prefix is added.
1804 d. PREFIX_OTHER if other prefix is added.
1807 static enum PREFIX_GROUP
1808 add_prefix (unsigned int prefix
)
1810 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1813 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1814 && flag_code
== CODE_64BIT
)
1816 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1817 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1818 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1829 case CS_PREFIX_OPCODE
:
1830 case DS_PREFIX_OPCODE
:
1831 case ES_PREFIX_OPCODE
:
1832 case FS_PREFIX_OPCODE
:
1833 case GS_PREFIX_OPCODE
:
1834 case SS_PREFIX_OPCODE
:
1838 case REPNE_PREFIX_OPCODE
:
1839 case REPE_PREFIX_OPCODE
:
1844 case LOCK_PREFIX_OPCODE
:
1853 case ADDR_PREFIX_OPCODE
:
1857 case DATA_PREFIX_OPCODE
:
1861 if (i
.prefix
[q
] != 0)
1869 i
.prefix
[q
] |= prefix
;
1872 as_bad (_("same type of prefix used twice"));
1878 set_code_flag (int value
)
1880 flag_code
= (enum flag_code
) value
;
1881 if (flag_code
== CODE_64BIT
)
1883 cpu_arch_flags
.bitfield
.cpu64
= 1;
1884 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1888 cpu_arch_flags
.bitfield
.cpu64
= 0;
1889 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1891 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1893 as_bad (_("64bit mode not supported on this CPU."));
1895 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1897 as_bad (_("32bit mode not supported on this CPU."));
1899 stackop_size
= '\0';
1903 set_16bit_gcc_code_flag (int new_code_flag
)
1905 flag_code
= (enum flag_code
) new_code_flag
;
1906 if (flag_code
!= CODE_16BIT
)
1908 cpu_arch_flags
.bitfield
.cpu64
= 0;
1909 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1910 stackop_size
= LONG_MNEM_SUFFIX
;
1914 set_intel_syntax (int syntax_flag
)
1916 /* Find out if register prefixing is specified. */
1917 int ask_naked_reg
= 0;
1920 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1922 char *string
= input_line_pointer
;
1923 int e
= get_symbol_end ();
1925 if (strcmp (string
, "prefix") == 0)
1927 else if (strcmp (string
, "noprefix") == 0)
1930 as_bad (_("bad argument to syntax directive."));
1931 *input_line_pointer
= e
;
1933 demand_empty_rest_of_line ();
1935 intel_syntax
= syntax_flag
;
1937 if (ask_naked_reg
== 0)
1938 allow_naked_reg
= (intel_syntax
1939 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1941 allow_naked_reg
= (ask_naked_reg
< 0);
1943 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1945 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1946 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1947 register_prefix
= allow_naked_reg
? "" : "%";
1951 set_intel_mnemonic (int mnemonic_flag
)
1953 intel_mnemonic
= mnemonic_flag
;
1957 set_allow_index_reg (int flag
)
1959 allow_index_reg
= flag
;
1963 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1967 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1969 char *string
= input_line_pointer
;
1970 int e
= get_symbol_end ();
1972 if (strcmp (string
, "none") == 0)
1973 sse_check
= sse_check_none
;
1974 else if (strcmp (string
, "warning") == 0)
1975 sse_check
= sse_check_warning
;
1976 else if (strcmp (string
, "error") == 0)
1977 sse_check
= sse_check_error
;
1979 as_bad (_("bad argument to sse_check directive."));
1980 *input_line_pointer
= e
;
1983 as_bad (_("missing argument for sse_check directive"));
1985 demand_empty_rest_of_line ();
1989 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1990 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1992 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1993 static const char *arch
;
1995 /* Intel LIOM is only supported on ELF. */
2001 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2002 use default_arch. */
2003 arch
= cpu_arch_name
;
2005 arch
= default_arch
;
2008 /* If we are targeting Intel L1OM, we must enable it. */
2009 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2010 || new_flag
.bitfield
.cpul1om
)
2013 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2018 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2022 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2024 char *string
= input_line_pointer
;
2025 int e
= get_symbol_end ();
2027 i386_cpu_flags flags
;
2029 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2031 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2033 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2037 cpu_arch_name
= cpu_arch
[i
].name
;
2038 cpu_sub_arch_name
= NULL
;
2039 cpu_arch_flags
= cpu_arch
[i
].flags
;
2040 if (flag_code
== CODE_64BIT
)
2042 cpu_arch_flags
.bitfield
.cpu64
= 1;
2043 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2047 cpu_arch_flags
.bitfield
.cpu64
= 0;
2048 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2050 cpu_arch_isa
= cpu_arch
[i
].type
;
2051 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2052 if (!cpu_arch_tune_set
)
2054 cpu_arch_tune
= cpu_arch_isa
;
2055 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2060 if (strncmp (string
+ 1, "no", 2))
2061 flags
= cpu_flags_or (cpu_arch_flags
,
2064 flags
= cpu_flags_and_not (cpu_arch_flags
,
2066 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2068 if (cpu_sub_arch_name
)
2070 char *name
= cpu_sub_arch_name
;
2071 cpu_sub_arch_name
= concat (name
,
2073 (const char *) NULL
);
2077 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2078 cpu_arch_flags
= flags
;
2080 *input_line_pointer
= e
;
2081 demand_empty_rest_of_line ();
2085 if (i
>= ARRAY_SIZE (cpu_arch
))
2086 as_bad (_("no such architecture: `%s'"), string
);
2088 *input_line_pointer
= e
;
2091 as_bad (_("missing cpu architecture"));
2093 no_cond_jump_promotion
= 0;
2094 if (*input_line_pointer
== ','
2095 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2097 char *string
= ++input_line_pointer
;
2098 int e
= get_symbol_end ();
2100 if (strcmp (string
, "nojumps") == 0)
2101 no_cond_jump_promotion
= 1;
2102 else if (strcmp (string
, "jumps") == 0)
2105 as_bad (_("no such architecture modifier: `%s'"), string
);
2107 *input_line_pointer
= e
;
2110 demand_empty_rest_of_line ();
2113 enum bfd_architecture
2116 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2118 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2119 || flag_code
!= CODE_64BIT
)
2120 as_fatal (_("Intel L1OM is 64bit ELF only"));
2121 return bfd_arch_l1om
;
2124 return bfd_arch_i386
;
2130 if (!strcmp (default_arch
, "x86_64"))
2132 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2134 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2135 as_fatal (_("Intel L1OM is 64bit ELF only"));
2136 return bfd_mach_l1om
;
2139 return bfd_mach_x86_64
;
2141 else if (!strcmp (default_arch
, "i386"))
2142 return bfd_mach_i386_i386
;
2144 as_fatal (_("Unknown architecture"));
2150 const char *hash_err
;
2152 /* Initialize op_hash hash table. */
2153 op_hash
= hash_new ();
2156 const insn_template
*optab
;
2157 templates
*core_optab
;
2159 /* Setup for loop. */
2161 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2162 core_optab
->start
= optab
;
2167 if (optab
->name
== NULL
2168 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2170 /* different name --> ship out current template list;
2171 add to hash table; & begin anew. */
2172 core_optab
->end
= optab
;
2173 hash_err
= hash_insert (op_hash
,
2175 (void *) core_optab
);
2178 as_fatal (_("Internal Error: Can't hash %s: %s"),
2182 if (optab
->name
== NULL
)
2184 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2185 core_optab
->start
= optab
;
2190 /* Initialize reg_hash hash table. */
2191 reg_hash
= hash_new ();
2193 const reg_entry
*regtab
;
2194 unsigned int regtab_size
= i386_regtab_size
;
2196 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2198 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2200 as_fatal (_("Internal Error: Can't hash %s: %s"),
2206 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2211 for (c
= 0; c
< 256; c
++)
2216 mnemonic_chars
[c
] = c
;
2217 register_chars
[c
] = c
;
2218 operand_chars
[c
] = c
;
2220 else if (ISLOWER (c
))
2222 mnemonic_chars
[c
] = c
;
2223 register_chars
[c
] = c
;
2224 operand_chars
[c
] = c
;
2226 else if (ISUPPER (c
))
2228 mnemonic_chars
[c
] = TOLOWER (c
);
2229 register_chars
[c
] = mnemonic_chars
[c
];
2230 operand_chars
[c
] = c
;
2233 if (ISALPHA (c
) || ISDIGIT (c
))
2234 identifier_chars
[c
] = c
;
2237 identifier_chars
[c
] = c
;
2238 operand_chars
[c
] = c
;
2243 identifier_chars
['@'] = '@';
2246 identifier_chars
['?'] = '?';
2247 operand_chars
['?'] = '?';
2249 digit_chars
['-'] = '-';
2250 mnemonic_chars
['_'] = '_';
2251 mnemonic_chars
['-'] = '-';
2252 mnemonic_chars
['.'] = '.';
2253 identifier_chars
['_'] = '_';
2254 identifier_chars
['.'] = '.';
2256 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2257 operand_chars
[(unsigned char) *p
] = *p
;
2260 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2263 record_alignment (text_section
, 2);
2264 record_alignment (data_section
, 2);
2265 record_alignment (bss_section
, 2);
2269 if (flag_code
== CODE_64BIT
)
2271 x86_dwarf2_return_column
= 16;
2272 x86_cie_data_alignment
= -8;
2276 x86_dwarf2_return_column
= 8;
2277 x86_cie_data_alignment
= -4;
2282 i386_print_statistics (FILE *file
)
2284 hash_print_statistics (file
, "i386 opcode", op_hash
);
2285 hash_print_statistics (file
, "i386 register", reg_hash
);
2290 /* Debugging routines for md_assemble. */
2291 static void pte (insn_template
*);
2292 static void pt (i386_operand_type
);
2293 static void pe (expressionS
*);
2294 static void ps (symbolS
*);
2297 pi (char *line
, i386_insn
*x
)
2301 fprintf (stdout
, "%s: template ", line
);
2303 fprintf (stdout
, " address: base %s index %s scale %x\n",
2304 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2305 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2306 x
->log2_scale_factor
);
2307 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2308 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2309 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2310 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2311 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2312 (x
->rex
& REX_W
) != 0,
2313 (x
->rex
& REX_R
) != 0,
2314 (x
->rex
& REX_X
) != 0,
2315 (x
->rex
& REX_B
) != 0);
2316 for (i
= 0; i
< x
->operands
; i
++)
2318 fprintf (stdout
, " #%d: ", i
+ 1);
2320 fprintf (stdout
, "\n");
2321 if (x
->types
[i
].bitfield
.reg8
2322 || x
->types
[i
].bitfield
.reg16
2323 || x
->types
[i
].bitfield
.reg32
2324 || x
->types
[i
].bitfield
.reg64
2325 || x
->types
[i
].bitfield
.regmmx
2326 || x
->types
[i
].bitfield
.regxmm
2327 || x
->types
[i
].bitfield
.regymm
2328 || x
->types
[i
].bitfield
.sreg2
2329 || x
->types
[i
].bitfield
.sreg3
2330 || x
->types
[i
].bitfield
.control
2331 || x
->types
[i
].bitfield
.debug
2332 || x
->types
[i
].bitfield
.test
)
2333 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2334 if (operand_type_check (x
->types
[i
], imm
))
2336 if (operand_type_check (x
->types
[i
], disp
))
2337 pe (x
->op
[i
].disps
);
2342 pte (insn_template
*t
)
2345 fprintf (stdout
, " %d operands ", t
->operands
);
2346 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2347 if (t
->extension_opcode
!= None
)
2348 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2349 if (t
->opcode_modifier
.d
)
2350 fprintf (stdout
, "D");
2351 if (t
->opcode_modifier
.w
)
2352 fprintf (stdout
, "W");
2353 fprintf (stdout
, "\n");
2354 for (i
= 0; i
< t
->operands
; i
++)
2356 fprintf (stdout
, " #%d type ", i
+ 1);
2357 pt (t
->operand_types
[i
]);
2358 fprintf (stdout
, "\n");
2365 fprintf (stdout
, " operation %d\n", e
->X_op
);
2366 fprintf (stdout
, " add_number %ld (%lx)\n",
2367 (long) e
->X_add_number
, (long) e
->X_add_number
);
2368 if (e
->X_add_symbol
)
2370 fprintf (stdout
, " add_symbol ");
2371 ps (e
->X_add_symbol
);
2372 fprintf (stdout
, "\n");
2376 fprintf (stdout
, " op_symbol ");
2377 ps (e
->X_op_symbol
);
2378 fprintf (stdout
, "\n");
2385 fprintf (stdout
, "%s type %s%s",
2387 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2388 segment_name (S_GET_SEGMENT (s
)));
2391 static struct type_name
2393 i386_operand_type mask
;
2396 const type_names
[] =
2398 { OPERAND_TYPE_REG8
, "r8" },
2399 { OPERAND_TYPE_REG16
, "r16" },
2400 { OPERAND_TYPE_REG32
, "r32" },
2401 { OPERAND_TYPE_REG64
, "r64" },
2402 { OPERAND_TYPE_IMM8
, "i8" },
2403 { OPERAND_TYPE_IMM8
, "i8s" },
2404 { OPERAND_TYPE_IMM16
, "i16" },
2405 { OPERAND_TYPE_IMM32
, "i32" },
2406 { OPERAND_TYPE_IMM32S
, "i32s" },
2407 { OPERAND_TYPE_IMM64
, "i64" },
2408 { OPERAND_TYPE_IMM1
, "i1" },
2409 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2410 { OPERAND_TYPE_DISP8
, "d8" },
2411 { OPERAND_TYPE_DISP16
, "d16" },
2412 { OPERAND_TYPE_DISP32
, "d32" },
2413 { OPERAND_TYPE_DISP32S
, "d32s" },
2414 { OPERAND_TYPE_DISP64
, "d64" },
2415 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2416 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2417 { OPERAND_TYPE_CONTROL
, "control reg" },
2418 { OPERAND_TYPE_TEST
, "test reg" },
2419 { OPERAND_TYPE_DEBUG
, "debug reg" },
2420 { OPERAND_TYPE_FLOATREG
, "FReg" },
2421 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2422 { OPERAND_TYPE_SREG2
, "SReg2" },
2423 { OPERAND_TYPE_SREG3
, "SReg3" },
2424 { OPERAND_TYPE_ACC
, "Acc" },
2425 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2426 { OPERAND_TYPE_REGMMX
, "rMMX" },
2427 { OPERAND_TYPE_REGXMM
, "rXMM" },
2428 { OPERAND_TYPE_REGYMM
, "rYMM" },
2429 { OPERAND_TYPE_ESSEG
, "es" },
2433 pt (i386_operand_type t
)
2436 i386_operand_type a
;
2438 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2440 a
= operand_type_and (t
, type_names
[j
].mask
);
2441 if (!operand_type_all_zero (&a
))
2442 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2447 #endif /* DEBUG386 */
2449 static bfd_reloc_code_real_type
2450 reloc (unsigned int size
,
2453 bfd_reloc_code_real_type other
)
2455 if (other
!= NO_RELOC
)
2457 reloc_howto_type
*reloc
;
2462 case BFD_RELOC_X86_64_GOT32
:
2463 return BFD_RELOC_X86_64_GOT64
;
2465 case BFD_RELOC_X86_64_PLTOFF64
:
2466 return BFD_RELOC_X86_64_PLTOFF64
;
2468 case BFD_RELOC_X86_64_GOTPC32
:
2469 other
= BFD_RELOC_X86_64_GOTPC64
;
2471 case BFD_RELOC_X86_64_GOTPCREL
:
2472 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2474 case BFD_RELOC_X86_64_TPOFF32
:
2475 other
= BFD_RELOC_X86_64_TPOFF64
;
2477 case BFD_RELOC_X86_64_DTPOFF32
:
2478 other
= BFD_RELOC_X86_64_DTPOFF64
;
2484 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2485 if (size
== 4 && flag_code
!= CODE_64BIT
)
2488 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2490 as_bad (_("unknown relocation (%u)"), other
);
2491 else if (size
!= bfd_get_reloc_size (reloc
))
2492 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2493 bfd_get_reloc_size (reloc
),
2495 else if (pcrel
&& !reloc
->pc_relative
)
2496 as_bad (_("non-pc-relative relocation for pc-relative field"));
2497 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2499 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2501 as_bad (_("relocated field and relocation type differ in signedness"));
2510 as_bad (_("there are no unsigned pc-relative relocations"));
2513 case 1: return BFD_RELOC_8_PCREL
;
2514 case 2: return BFD_RELOC_16_PCREL
;
2515 case 4: return BFD_RELOC_32_PCREL
;
2516 case 8: return BFD_RELOC_64_PCREL
;
2518 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2525 case 4: return BFD_RELOC_X86_64_32S
;
2530 case 1: return BFD_RELOC_8
;
2531 case 2: return BFD_RELOC_16
;
2532 case 4: return BFD_RELOC_32
;
2533 case 8: return BFD_RELOC_64
;
2535 as_bad (_("cannot do %s %u byte relocation"),
2536 sign
> 0 ? "signed" : "unsigned", size
);
2542 /* Here we decide which fixups can be adjusted to make them relative to
2543 the beginning of the section instead of the symbol. Basically we need
2544 to make sure that the dynamic relocations are done correctly, so in
2545 some cases we force the original symbol to be used. */
2548 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2550 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2554 /* Don't adjust pc-relative references to merge sections in 64-bit
2556 if (use_rela_relocations
2557 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2561 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2562 and changed later by validate_fix. */
2563 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2564 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2567 /* adjust_reloc_syms doesn't know about the GOT. */
2568 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2569 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2570 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2571 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2572 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2573 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2574 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2575 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2576 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2577 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2578 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2579 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2580 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2581 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2582 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2583 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2584 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2585 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2586 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2587 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2588 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2589 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2590 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2591 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2592 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2593 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2594 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2595 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2602 intel_float_operand (const char *mnemonic
)
2604 /* Note that the value returned is meaningful only for opcodes with (memory)
2605 operands, hence the code here is free to improperly handle opcodes that
2606 have no operands (for better performance and smaller code). */
2608 if (mnemonic
[0] != 'f')
2609 return 0; /* non-math */
2611 switch (mnemonic
[1])
2613 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2614 the fs segment override prefix not currently handled because no
2615 call path can make opcodes without operands get here */
2617 return 2 /* integer op */;
2619 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2620 return 3; /* fldcw/fldenv */
2623 if (mnemonic
[2] != 'o' /* fnop */)
2624 return 3; /* non-waiting control op */
2627 if (mnemonic
[2] == 's')
2628 return 3; /* frstor/frstpm */
2631 if (mnemonic
[2] == 'a')
2632 return 3; /* fsave */
2633 if (mnemonic
[2] == 't')
2635 switch (mnemonic
[3])
2637 case 'c': /* fstcw */
2638 case 'd': /* fstdw */
2639 case 'e': /* fstenv */
2640 case 's': /* fsts[gw] */
2646 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2647 return 0; /* fxsave/fxrstor are not really math ops */
2654 /* Build the VEX prefix. */
2657 build_vex_prefix (const insn_template
*t
)
2659 unsigned int register_specifier
;
2660 unsigned int implied_prefix
;
2661 unsigned int vector_length
;
2663 /* Check register specifier. */
2664 if (i
.vex
.register_specifier
)
2666 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2667 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2668 register_specifier
+= 8;
2669 register_specifier
= ~register_specifier
& 0xf;
2672 register_specifier
= 0xf;
2674 /* Use 2-byte VEX prefix by swappping destination and source
2677 && i
.operands
== i
.reg_operands
2678 && i
.tm
.opcode_modifier
.vex0f
2679 && i
.tm
.opcode_modifier
.s
2682 unsigned int xchg
= i
.operands
- 1;
2683 union i386_op temp_op
;
2684 i386_operand_type temp_type
;
2686 temp_type
= i
.types
[xchg
];
2687 i
.types
[xchg
] = i
.types
[0];
2688 i
.types
[0] = temp_type
;
2689 temp_op
= i
.op
[xchg
];
2690 i
.op
[xchg
] = i
.op
[0];
2693 gas_assert (i
.rm
.mode
== 3);
2697 i
.rm
.regmem
= i
.rm
.reg
;
2700 /* Use the next insn. */
2704 vector_length
= i
.tm
.opcode_modifier
.vex
== 2 ? 1 : 0;
2706 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2711 case DATA_PREFIX_OPCODE
:
2714 case REPE_PREFIX_OPCODE
:
2717 case REPNE_PREFIX_OPCODE
:
2724 /* Use 2-byte VEX prefix if possible. */
2725 if (i
.tm
.opcode_modifier
.vex0f
2726 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2728 /* 2-byte VEX prefix. */
2732 i
.vex
.bytes
[0] = 0xc5;
2734 /* Check the REX.R bit. */
2735 r
= (i
.rex
& REX_R
) ? 0 : 1;
2736 i
.vex
.bytes
[1] = (r
<< 7
2737 | register_specifier
<< 3
2738 | vector_length
<< 2
2743 /* 3-byte VEX prefix. */
2747 i
.vex
.bytes
[0] = 0xc4;
2749 if (i
.tm
.opcode_modifier
.vex0f
)
2751 else if (i
.tm
.opcode_modifier
.vex0f38
)
2753 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2755 else if (i
.tm
.opcode_modifier
.xop08
)
2758 i
.vex
.bytes
[0] = 0x8f;
2760 else if (i
.tm
.opcode_modifier
.xop09
)
2763 i
.vex
.bytes
[0] = 0x8f;
2765 else if (i
.tm
.opcode_modifier
.xop0a
)
2768 i
.vex
.bytes
[0] = 0x8f;
2773 /* The high 3 bits of the second VEX byte are 1's compliment
2774 of RXB bits from REX. */
2775 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2777 /* Check the REX.W bit. */
2778 w
= (i
.rex
& REX_W
) ? 1 : 0;
2779 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2784 if (i
.tm
.opcode_modifier
.vexw1
)
2788 i
.vex
.bytes
[2] = (w
<< 7
2789 | register_specifier
<< 3
2790 | vector_length
<< 2
2796 process_immext (void)
2800 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2802 /* SSE3 Instructions have the fixed operands with an opcode
2803 suffix which is coded in the same place as an 8-bit immediate
2804 field would be. Here we check those operands and remove them
2808 for (x
= 0; x
< i
.operands
; x
++)
2809 if (i
.op
[x
].regs
->reg_num
!= x
)
2810 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2811 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2817 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2818 which is coded in the same place as an 8-bit immediate field
2819 would be. Here we fake an 8-bit immediate operand from the
2820 opcode suffix stored in tm.extension_opcode.
2822 AVX instructions also use this encoding, for some of
2823 3 argument instructions. */
2825 gas_assert (i
.imm_operands
== 0
2827 || (i
.tm
.opcode_modifier
.vex
2828 && i
.operands
<= 4)));
2830 exp
= &im_expressions
[i
.imm_operands
++];
2831 i
.op
[i
.operands
].imms
= exp
;
2832 i
.types
[i
.operands
] = imm8
;
2834 exp
->X_op
= O_constant
;
2835 exp
->X_add_number
= i
.tm
.extension_opcode
;
2836 i
.tm
.extension_opcode
= None
;
2839 /* This is the guts of the machine-dependent assembler. LINE points to a
2840 machine dependent instruction. This function is supposed to emit
2841 the frags/bytes it assembles to. */
2844 md_assemble (char *line
)
2847 char mnemonic
[MAX_MNEM_SIZE
];
2848 const insn_template
*t
;
2850 /* Initialize globals. */
2851 memset (&i
, '\0', sizeof (i
));
2852 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2853 i
.reloc
[j
] = NO_RELOC
;
2854 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2855 memset (im_expressions
, '\0', sizeof (im_expressions
));
2856 save_stack_p
= save_stack
;
2858 /* First parse an instruction mnemonic & call i386_operand for the operands.
2859 We assume that the scrubber has arranged it so that line[0] is the valid
2860 start of a (possibly prefixed) mnemonic. */
2862 line
= parse_insn (line
, mnemonic
);
2866 line
= parse_operands (line
, mnemonic
);
2871 /* Now we've parsed the mnemonic into a set of templates, and have the
2872 operands at hand. */
2874 /* All intel opcodes have reversed operands except for "bound" and
2875 "enter". We also don't reverse intersegment "jmp" and "call"
2876 instructions with 2 immediate operands so that the immediate segment
2877 precedes the offset, as it does when in AT&T mode. */
2880 && (strcmp (mnemonic
, "bound") != 0)
2881 && (strcmp (mnemonic
, "invlpga") != 0)
2882 && !(operand_type_check (i
.types
[0], imm
)
2883 && operand_type_check (i
.types
[1], imm
)))
2886 /* The order of the immediates should be reversed
2887 for 2 immediates extrq and insertq instructions */
2888 if (i
.imm_operands
== 2
2889 && (strcmp (mnemonic
, "extrq") == 0
2890 || strcmp (mnemonic
, "insertq") == 0))
2891 swap_2_operands (0, 1);
2896 /* Don't optimize displacement for movabs since it only takes 64bit
2899 && (flag_code
!= CODE_64BIT
2900 || strcmp (mnemonic
, "movabs") != 0))
2903 /* Next, we find a template that matches the given insn,
2904 making sure the overlap of the given operands types is consistent
2905 with the template operand types. */
2907 if (!(t
= match_template ()))
2910 if (sse_check
!= sse_check_none
2911 && !i
.tm
.opcode_modifier
.noavx
2912 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2913 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2914 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2915 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2916 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2917 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2919 (sse_check
== sse_check_warning
2921 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2924 /* Zap movzx and movsx suffix. The suffix has been set from
2925 "word ptr" or "byte ptr" on the source operand in Intel syntax
2926 or extracted from mnemonic in AT&T syntax. But we'll use
2927 the destination register to choose the suffix for encoding. */
2928 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2930 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2931 there is no suffix, the default will be byte extension. */
2932 if (i
.reg_operands
!= 2
2935 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2940 if (i
.tm
.opcode_modifier
.fwait
)
2941 if (!add_prefix (FWAIT_OPCODE
))
2944 /* Check for lock without a lockable instruction. Destination operand
2945 must be memory unless it is xchg (0x86). */
2946 if (i
.prefix
[LOCK_PREFIX
]
2947 && (!i
.tm
.opcode_modifier
.islockable
2948 || i
.mem_operands
== 0
2949 || (i
.tm
.base_opcode
!= 0x86
2950 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2952 as_bad (_("expecting lockable instruction after `lock'"));
2956 /* Check string instruction segment overrides. */
2957 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2959 if (!check_string ())
2961 i
.disp_operands
= 0;
2964 if (!process_suffix ())
2967 /* Update operand types. */
2968 for (j
= 0; j
< i
.operands
; j
++)
2969 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2971 /* Make still unresolved immediate matches conform to size of immediate
2972 given in i.suffix. */
2973 if (!finalize_imm ())
2976 if (i
.types
[0].bitfield
.imm1
)
2977 i
.imm_operands
= 0; /* kludge for shift insns. */
2979 /* We only need to check those implicit registers for instructions
2980 with 3 operands or less. */
2981 if (i
.operands
<= 3)
2982 for (j
= 0; j
< i
.operands
; j
++)
2983 if (i
.types
[j
].bitfield
.inoutportreg
2984 || i
.types
[j
].bitfield
.shiftcount
2985 || i
.types
[j
].bitfield
.acc
2986 || i
.types
[j
].bitfield
.floatacc
)
2989 /* ImmExt should be processed after SSE2AVX. */
2990 if (!i
.tm
.opcode_modifier
.sse2avx
2991 && i
.tm
.opcode_modifier
.immext
)
2994 /* For insns with operands there are more diddles to do to the opcode. */
2997 if (!process_operands ())
3000 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3002 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3003 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3006 if (i
.tm
.opcode_modifier
.vex
)
3007 build_vex_prefix (t
);
3009 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3010 instructions may define INT_OPCODE as well, so avoid this corner
3011 case for those instructions that use MODRM. */
3012 if (i
.tm
.base_opcode
== INT_OPCODE
3013 && i
.op
[0].imms
->X_add_number
== 3
3014 && !i
.tm
.opcode_modifier
.modrm
)
3016 i
.tm
.base_opcode
= INT3_OPCODE
;
3020 if ((i
.tm
.opcode_modifier
.jump
3021 || i
.tm
.opcode_modifier
.jumpbyte
3022 || i
.tm
.opcode_modifier
.jumpdword
)
3023 && i
.op
[0].disps
->X_op
== O_constant
)
3025 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3026 the absolute address given by the constant. Since ix86 jumps and
3027 calls are pc relative, we need to generate a reloc. */
3028 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3029 i
.op
[0].disps
->X_op
= O_symbol
;
3032 if (i
.tm
.opcode_modifier
.rex64
)
3035 /* For 8 bit registers we need an empty rex prefix. Also if the
3036 instruction already has a prefix, we need to convert old
3037 registers to new ones. */
3039 if ((i
.types
[0].bitfield
.reg8
3040 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3041 || (i
.types
[1].bitfield
.reg8
3042 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3043 || ((i
.types
[0].bitfield
.reg8
3044 || i
.types
[1].bitfield
.reg8
)
3049 i
.rex
|= REX_OPCODE
;
3050 for (x
= 0; x
< 2; x
++)
3052 /* Look for 8 bit operand that uses old registers. */
3053 if (i
.types
[x
].bitfield
.reg8
3054 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3056 /* In case it is "hi" register, give up. */
3057 if (i
.op
[x
].regs
->reg_num
> 3)
3058 as_bad (_("can't encode register '%s%s' in an "
3059 "instruction requiring REX prefix."),
3060 register_prefix
, i
.op
[x
].regs
->reg_name
);
3062 /* Otherwise it is equivalent to the extended register.
3063 Since the encoding doesn't change this is merely
3064 cosmetic cleanup for debug output. */
3066 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3072 add_prefix (REX_OPCODE
| i
.rex
);
3074 /* We are ready to output the insn. */
3079 parse_insn (char *line
, char *mnemonic
)
3082 char *token_start
= l
;
3085 const insn_template
*t
;
3088 /* Non-zero if we found a prefix only acceptable with string insns. */
3089 const char *expecting_string_instruction
= NULL
;
3094 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3099 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3101 as_bad (_("no such instruction: `%s'"), token_start
);
3106 if (!is_space_char (*l
)
3107 && *l
!= END_OF_INSN
3109 || (*l
!= PREFIX_SEPARATOR
3112 as_bad (_("invalid character %s in mnemonic"),
3113 output_invalid (*l
));
3116 if (token_start
== l
)
3118 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3119 as_bad (_("expecting prefix; got nothing"));
3121 as_bad (_("expecting mnemonic; got nothing"));
3125 /* Look up instruction (or prefix) via hash table. */
3126 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3128 if (*l
!= END_OF_INSN
3129 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3130 && current_templates
3131 && current_templates
->start
->opcode_modifier
.isprefix
)
3133 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3135 as_bad ((flag_code
!= CODE_64BIT
3136 ? _("`%s' is only supported in 64-bit mode")
3137 : _("`%s' is not supported in 64-bit mode")),
3138 current_templates
->start
->name
);
3141 /* If we are in 16-bit mode, do not allow addr16 or data16.
3142 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3143 if ((current_templates
->start
->opcode_modifier
.size16
3144 || current_templates
->start
->opcode_modifier
.size32
)
3145 && flag_code
!= CODE_64BIT
3146 && (current_templates
->start
->opcode_modifier
.size32
3147 ^ (flag_code
== CODE_16BIT
)))
3149 as_bad (_("redundant %s prefix"),
3150 current_templates
->start
->name
);
3153 /* Add prefix, checking for repeated prefixes. */
3154 switch (add_prefix (current_templates
->start
->base_opcode
))
3159 expecting_string_instruction
= current_templates
->start
->name
;
3164 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3171 if (!current_templates
)
3173 /* Check if we should swap operand in encoding. */
3174 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3180 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3183 if (!current_templates
)
3186 /* See if we can get a match by trimming off a suffix. */
3189 case WORD_MNEM_SUFFIX
:
3190 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3191 i
.suffix
= SHORT_MNEM_SUFFIX
;
3193 case BYTE_MNEM_SUFFIX
:
3194 case QWORD_MNEM_SUFFIX
:
3195 i
.suffix
= mnem_p
[-1];
3197 current_templates
= (const templates
*) hash_find (op_hash
,
3200 case SHORT_MNEM_SUFFIX
:
3201 case LONG_MNEM_SUFFIX
:
3204 i
.suffix
= mnem_p
[-1];
3206 current_templates
= (const templates
*) hash_find (op_hash
,
3215 if (intel_float_operand (mnemonic
) == 1)
3216 i
.suffix
= SHORT_MNEM_SUFFIX
;
3218 i
.suffix
= LONG_MNEM_SUFFIX
;
3220 current_templates
= (const templates
*) hash_find (op_hash
,
3225 if (!current_templates
)
3227 as_bad (_("no such instruction: `%s'"), token_start
);
3232 if (current_templates
->start
->opcode_modifier
.jump
3233 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3235 /* Check for a branch hint. We allow ",pt" and ",pn" for
3236 predict taken and predict not taken respectively.
3237 I'm not sure that branch hints actually do anything on loop
3238 and jcxz insns (JumpByte) for current Pentium4 chips. They
3239 may work in the future and it doesn't hurt to accept them
3241 if (l
[0] == ',' && l
[1] == 'p')
3245 if (!add_prefix (DS_PREFIX_OPCODE
))
3249 else if (l
[2] == 'n')
3251 if (!add_prefix (CS_PREFIX_OPCODE
))
3257 /* Any other comma loses. */
3260 as_bad (_("invalid character %s in mnemonic"),
3261 output_invalid (*l
));
3265 /* Check if instruction is supported on specified architecture. */
3267 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3269 supported
|= cpu_flags_match (t
);
3270 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3274 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3276 as_bad (flag_code
== CODE_64BIT
3277 ? _("`%s' is not supported in 64-bit mode")
3278 : _("`%s' is only supported in 64-bit mode"),
3279 current_templates
->start
->name
);
3282 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3284 as_bad (_("`%s' is not supported on `%s%s'"),
3285 current_templates
->start
->name
,
3286 cpu_arch_name
? cpu_arch_name
: default_arch
,
3287 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3292 if (!cpu_arch_flags
.bitfield
.cpui386
3293 && (flag_code
!= CODE_16BIT
))
3295 as_warn (_("use .code16 to ensure correct addressing mode"));
3298 /* Check for rep/repne without a string instruction. */
3299 if (expecting_string_instruction
)
3301 static templates override
;
3303 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3304 if (t
->opcode_modifier
.isstring
)
3306 if (t
>= current_templates
->end
)
3308 as_bad (_("expecting string instruction after `%s'"),
3309 expecting_string_instruction
);
3312 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3313 if (!t
->opcode_modifier
.isstring
)
3316 current_templates
= &override
;
3323 parse_operands (char *l
, const char *mnemonic
)
3327 /* 1 if operand is pending after ','. */
3328 unsigned int expecting_operand
= 0;
3330 /* Non-zero if operand parens not balanced. */
3331 unsigned int paren_not_balanced
;
3333 while (*l
!= END_OF_INSN
)
3335 /* Skip optional white space before operand. */
3336 if (is_space_char (*l
))
3338 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3340 as_bad (_("invalid character %s before operand %d"),
3341 output_invalid (*l
),
3345 token_start
= l
; /* after white space */
3346 paren_not_balanced
= 0;
3347 while (paren_not_balanced
|| *l
!= ',')
3349 if (*l
== END_OF_INSN
)
3351 if (paren_not_balanced
)
3354 as_bad (_("unbalanced parenthesis in operand %d."),
3357 as_bad (_("unbalanced brackets in operand %d."),
3362 break; /* we are done */
3364 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3366 as_bad (_("invalid character %s in operand %d"),
3367 output_invalid (*l
),
3374 ++paren_not_balanced
;
3376 --paren_not_balanced
;
3381 ++paren_not_balanced
;
3383 --paren_not_balanced
;
3387 if (l
!= token_start
)
3388 { /* Yes, we've read in another operand. */
3389 unsigned int operand_ok
;
3390 this_operand
= i
.operands
++;
3391 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3392 if (i
.operands
> MAX_OPERANDS
)
3394 as_bad (_("spurious operands; (%d operands/instruction max)"),
3398 /* Now parse operand adding info to 'i' as we go along. */
3399 END_STRING_AND_SAVE (l
);
3403 i386_intel_operand (token_start
,
3404 intel_float_operand (mnemonic
));
3406 operand_ok
= i386_att_operand (token_start
);
3408 RESTORE_END_STRING (l
);
3414 if (expecting_operand
)
3416 expecting_operand_after_comma
:
3417 as_bad (_("expecting operand after ','; got nothing"));
3422 as_bad (_("expecting operand before ','; got nothing"));
3427 /* Now *l must be either ',' or END_OF_INSN. */
3430 if (*++l
== END_OF_INSN
)
3432 /* Just skip it, if it's \n complain. */
3433 goto expecting_operand_after_comma
;
3435 expecting_operand
= 1;
3442 swap_2_operands (int xchg1
, int xchg2
)
3444 union i386_op temp_op
;
3445 i386_operand_type temp_type
;
3446 enum bfd_reloc_code_real temp_reloc
;
3448 temp_type
= i
.types
[xchg2
];
3449 i
.types
[xchg2
] = i
.types
[xchg1
];
3450 i
.types
[xchg1
] = temp_type
;
3451 temp_op
= i
.op
[xchg2
];
3452 i
.op
[xchg2
] = i
.op
[xchg1
];
3453 i
.op
[xchg1
] = temp_op
;
3454 temp_reloc
= i
.reloc
[xchg2
];
3455 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3456 i
.reloc
[xchg1
] = temp_reloc
;
3460 swap_operands (void)
3466 swap_2_operands (1, i
.operands
- 2);
3469 swap_2_operands (0, i
.operands
- 1);
3475 if (i
.mem_operands
== 2)
3477 const seg_entry
*temp_seg
;
3478 temp_seg
= i
.seg
[0];
3479 i
.seg
[0] = i
.seg
[1];
3480 i
.seg
[1] = temp_seg
;
3484 /* Try to ensure constant immediates are represented in the smallest
3489 char guess_suffix
= 0;
3493 guess_suffix
= i
.suffix
;
3494 else if (i
.reg_operands
)
3496 /* Figure out a suffix from the last register operand specified.
3497 We can't do this properly yet, ie. excluding InOutPortReg,
3498 but the following works for instructions with immediates.
3499 In any case, we can't set i.suffix yet. */
3500 for (op
= i
.operands
; --op
>= 0;)
3501 if (i
.types
[op
].bitfield
.reg8
)
3503 guess_suffix
= BYTE_MNEM_SUFFIX
;
3506 else if (i
.types
[op
].bitfield
.reg16
)
3508 guess_suffix
= WORD_MNEM_SUFFIX
;
3511 else if (i
.types
[op
].bitfield
.reg32
)
3513 guess_suffix
= LONG_MNEM_SUFFIX
;
3516 else if (i
.types
[op
].bitfield
.reg64
)
3518 guess_suffix
= QWORD_MNEM_SUFFIX
;
3522 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3523 guess_suffix
= WORD_MNEM_SUFFIX
;
3525 for (op
= i
.operands
; --op
>= 0;)
3526 if (operand_type_check (i
.types
[op
], imm
))
3528 switch (i
.op
[op
].imms
->X_op
)
3531 /* If a suffix is given, this operand may be shortened. */
3532 switch (guess_suffix
)
3534 case LONG_MNEM_SUFFIX
:
3535 i
.types
[op
].bitfield
.imm32
= 1;
3536 i
.types
[op
].bitfield
.imm64
= 1;
3538 case WORD_MNEM_SUFFIX
:
3539 i
.types
[op
].bitfield
.imm16
= 1;
3540 i
.types
[op
].bitfield
.imm32
= 1;
3541 i
.types
[op
].bitfield
.imm32s
= 1;
3542 i
.types
[op
].bitfield
.imm64
= 1;
3544 case BYTE_MNEM_SUFFIX
:
3545 i
.types
[op
].bitfield
.imm8
= 1;
3546 i
.types
[op
].bitfield
.imm8s
= 1;
3547 i
.types
[op
].bitfield
.imm16
= 1;
3548 i
.types
[op
].bitfield
.imm32
= 1;
3549 i
.types
[op
].bitfield
.imm32s
= 1;
3550 i
.types
[op
].bitfield
.imm64
= 1;
3554 /* If this operand is at most 16 bits, convert it
3555 to a signed 16 bit number before trying to see
3556 whether it will fit in an even smaller size.
3557 This allows a 16-bit operand such as $0xffe0 to
3558 be recognised as within Imm8S range. */
3559 if ((i
.types
[op
].bitfield
.imm16
)
3560 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3562 i
.op
[op
].imms
->X_add_number
=
3563 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3565 if ((i
.types
[op
].bitfield
.imm32
)
3566 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3569 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3570 ^ ((offsetT
) 1 << 31))
3571 - ((offsetT
) 1 << 31));
3574 = operand_type_or (i
.types
[op
],
3575 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3577 /* We must avoid matching of Imm32 templates when 64bit
3578 only immediate is available. */
3579 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3580 i
.types
[op
].bitfield
.imm32
= 0;
3587 /* Symbols and expressions. */
3589 /* Convert symbolic operand to proper sizes for matching, but don't
3590 prevent matching a set of insns that only supports sizes other
3591 than those matching the insn suffix. */
3593 i386_operand_type mask
, allowed
;
3594 const insn_template
*t
;
3596 operand_type_set (&mask
, 0);
3597 operand_type_set (&allowed
, 0);
3599 for (t
= current_templates
->start
;
3600 t
< current_templates
->end
;
3602 allowed
= operand_type_or (allowed
,
3603 t
->operand_types
[op
]);
3604 switch (guess_suffix
)
3606 case QWORD_MNEM_SUFFIX
:
3607 mask
.bitfield
.imm64
= 1;
3608 mask
.bitfield
.imm32s
= 1;
3610 case LONG_MNEM_SUFFIX
:
3611 mask
.bitfield
.imm32
= 1;
3613 case WORD_MNEM_SUFFIX
:
3614 mask
.bitfield
.imm16
= 1;
3616 case BYTE_MNEM_SUFFIX
:
3617 mask
.bitfield
.imm8
= 1;
3622 allowed
= operand_type_and (mask
, allowed
);
3623 if (!operand_type_all_zero (&allowed
))
3624 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3631 /* Try to use the smallest displacement type too. */
3633 optimize_disp (void)
3637 for (op
= i
.operands
; --op
>= 0;)
3638 if (operand_type_check (i
.types
[op
], disp
))
3640 if (i
.op
[op
].disps
->X_op
== O_constant
)
3642 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3644 if (i
.types
[op
].bitfield
.disp16
3645 && (disp
& ~(offsetT
) 0xffff) == 0)
3647 /* If this operand is at most 16 bits, convert
3648 to a signed 16 bit number and don't use 64bit
3650 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3651 i
.types
[op
].bitfield
.disp64
= 0;
3653 if (i
.types
[op
].bitfield
.disp32
3654 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3656 /* If this operand is at most 32 bits, convert
3657 to a signed 32 bit number and don't use 64bit
3659 disp
&= (((offsetT
) 2 << 31) - 1);
3660 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3661 i
.types
[op
].bitfield
.disp64
= 0;
3663 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3665 i
.types
[op
].bitfield
.disp8
= 0;
3666 i
.types
[op
].bitfield
.disp16
= 0;
3667 i
.types
[op
].bitfield
.disp32
= 0;
3668 i
.types
[op
].bitfield
.disp32s
= 0;
3669 i
.types
[op
].bitfield
.disp64
= 0;
3673 else if (flag_code
== CODE_64BIT
)
3675 if (fits_in_signed_long (disp
))
3677 i
.types
[op
].bitfield
.disp64
= 0;
3678 i
.types
[op
].bitfield
.disp32s
= 1;
3680 if (i
.prefix
[ADDR_PREFIX
]
3681 && fits_in_unsigned_long (disp
))
3682 i
.types
[op
].bitfield
.disp32
= 1;
3684 if ((i
.types
[op
].bitfield
.disp32
3685 || i
.types
[op
].bitfield
.disp32s
3686 || i
.types
[op
].bitfield
.disp16
)
3687 && fits_in_signed_byte (disp
))
3688 i
.types
[op
].bitfield
.disp8
= 1;
3690 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3691 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3693 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3694 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3695 i
.types
[op
].bitfield
.disp8
= 0;
3696 i
.types
[op
].bitfield
.disp16
= 0;
3697 i
.types
[op
].bitfield
.disp32
= 0;
3698 i
.types
[op
].bitfield
.disp32s
= 0;
3699 i
.types
[op
].bitfield
.disp64
= 0;
3702 /* We only support 64bit displacement on constants. */
3703 i
.types
[op
].bitfield
.disp64
= 0;
3707 static const insn_template
*
3708 match_template (void)
3710 /* Points to template once we've found it. */
3711 const insn_template
*t
;
3712 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3713 i386_operand_type overlap4
;
3714 unsigned int found_reverse_match
;
3715 i386_opcode_modifier suffix_check
;
3716 i386_operand_type operand_types
[MAX_OPERANDS
];
3717 int addr_prefix_disp
;
3719 unsigned int found_cpu_match
;
3720 unsigned int check_register
;
3722 #if MAX_OPERANDS != 5
3723 # error "MAX_OPERANDS must be 5."
3726 found_reverse_match
= 0;
3727 addr_prefix_disp
= -1;
3729 memset (&suffix_check
, 0, sizeof (suffix_check
));
3730 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3731 suffix_check
.no_bsuf
= 1;
3732 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3733 suffix_check
.no_wsuf
= 1;
3734 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3735 suffix_check
.no_ssuf
= 1;
3736 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3737 suffix_check
.no_lsuf
= 1;
3738 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3739 suffix_check
.no_qsuf
= 1;
3740 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3741 suffix_check
.no_ldsuf
= 1;
3743 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3745 addr_prefix_disp
= -1;
3747 /* Must have right number of operands. */
3748 if (i
.operands
!= t
->operands
)
3751 /* Check processor support. */
3752 found_cpu_match
= (cpu_flags_match (t
)
3753 == CPU_FLAGS_PERFECT_MATCH
);
3754 if (!found_cpu_match
)
3757 /* Check old gcc support. */
3758 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3761 /* Check AT&T mnemonic. */
3762 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3765 /* Check AT&T syntax Intel syntax. */
3766 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3767 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3770 /* Check the suffix, except for some instructions in intel mode. */
3771 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3772 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3773 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3774 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3775 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3776 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3777 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3780 if (!operand_size_match (t
))
3783 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3784 operand_types
[j
] = t
->operand_types
[j
];
3786 /* In general, don't allow 64-bit operands in 32-bit mode. */
3787 if (i
.suffix
== QWORD_MNEM_SUFFIX
3788 && flag_code
!= CODE_64BIT
3790 ? (!t
->opcode_modifier
.ignoresize
3791 && !intel_float_operand (t
->name
))
3792 : intel_float_operand (t
->name
) != 2)
3793 && ((!operand_types
[0].bitfield
.regmmx
3794 && !operand_types
[0].bitfield
.regxmm
3795 && !operand_types
[0].bitfield
.regymm
)
3796 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3797 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3798 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3799 && (t
->base_opcode
!= 0x0fc7
3800 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3803 /* In general, don't allow 32-bit operands on pre-386. */
3804 else if (i
.suffix
== LONG_MNEM_SUFFIX
3805 && !cpu_arch_flags
.bitfield
.cpui386
3807 ? (!t
->opcode_modifier
.ignoresize
3808 && !intel_float_operand (t
->name
))
3809 : intel_float_operand (t
->name
) != 2)
3810 && ((!operand_types
[0].bitfield
.regmmx
3811 && !operand_types
[0].bitfield
.regxmm
)
3812 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3813 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3816 /* Do not verify operands when there are none. */
3820 /* We've found a match; break out of loop. */
3824 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3825 into Disp32/Disp16/Disp32 operand. */
3826 if (i
.prefix
[ADDR_PREFIX
] != 0)
3828 /* There should be only one Disp operand. */
3832 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3834 if (operand_types
[j
].bitfield
.disp16
)
3836 addr_prefix_disp
= j
;
3837 operand_types
[j
].bitfield
.disp32
= 1;
3838 operand_types
[j
].bitfield
.disp16
= 0;
3844 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3846 if (operand_types
[j
].bitfield
.disp32
)
3848 addr_prefix_disp
= j
;
3849 operand_types
[j
].bitfield
.disp32
= 0;
3850 operand_types
[j
].bitfield
.disp16
= 1;
3856 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3858 if (operand_types
[j
].bitfield
.disp64
)
3860 addr_prefix_disp
= j
;
3861 operand_types
[j
].bitfield
.disp64
= 0;
3862 operand_types
[j
].bitfield
.disp32
= 1;
3870 /* We check register size only if size of operands can be
3871 encoded the canonical way. */
3872 check_register
= t
->opcode_modifier
.w
;
3873 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3874 switch (t
->operands
)
3877 if (!operand_type_match (overlap0
, i
.types
[0]))
3881 /* xchg %eax, %eax is a special case. It is an aliase for nop
3882 only in 32bit mode and we can use opcode 0x90. In 64bit
3883 mode, we can't use 0x90 for xchg %eax, %eax since it should
3884 zero-extend %eax to %rax. */
3885 if (flag_code
== CODE_64BIT
3886 && t
->base_opcode
== 0x90
3887 && operand_type_equal (&i
.types
[0], &acc32
)
3888 && operand_type_equal (&i
.types
[1], &acc32
))
3892 /* If we swap operand in encoding, we either match
3893 the next one or reverse direction of operands. */
3894 if (t
->opcode_modifier
.s
)
3896 else if (t
->opcode_modifier
.d
)
3901 /* If we swap operand in encoding, we match the next one. */
3902 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3906 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3907 if (!operand_type_match (overlap0
, i
.types
[0])
3908 || !operand_type_match (overlap1
, i
.types
[1])
3910 && !operand_type_register_match (overlap0
, i
.types
[0],
3912 overlap1
, i
.types
[1],
3915 /* Check if other direction is valid ... */
3916 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3920 /* Try reversing direction of operands. */
3921 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3922 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3923 if (!operand_type_match (overlap0
, i
.types
[0])
3924 || !operand_type_match (overlap1
, i
.types
[1])
3926 && !operand_type_register_match (overlap0
,
3933 /* Does not match either direction. */
3936 /* found_reverse_match holds which of D or FloatDR
3938 if (t
->opcode_modifier
.d
)
3939 found_reverse_match
= Opcode_D
;
3940 else if (t
->opcode_modifier
.floatd
)
3941 found_reverse_match
= Opcode_FloatD
;
3943 found_reverse_match
= 0;
3944 if (t
->opcode_modifier
.floatr
)
3945 found_reverse_match
|= Opcode_FloatR
;
3949 /* Found a forward 2 operand match here. */
3950 switch (t
->operands
)
3953 overlap4
= operand_type_and (i
.types
[4],
3956 overlap3
= operand_type_and (i
.types
[3],
3959 overlap2
= operand_type_and (i
.types
[2],
3964 switch (t
->operands
)
3967 if (!operand_type_match (overlap4
, i
.types
[4])
3968 || !operand_type_register_match (overlap3
,
3976 if (!operand_type_match (overlap3
, i
.types
[3])
3978 && !operand_type_register_match (overlap2
,
3986 /* Here we make use of the fact that there are no
3987 reverse match 3 operand instructions, and all 3
3988 operand instructions only need to be checked for
3989 register consistency between operands 2 and 3. */
3990 if (!operand_type_match (overlap2
, i
.types
[2])
3992 && !operand_type_register_match (overlap1
,
4002 /* Found either forward/reverse 2, 3 or 4 operand match here:
4003 slip through to break. */
4005 if (!found_cpu_match
)
4007 found_reverse_match
= 0;
4011 /* We've found a match; break out of loop. */
4015 if (t
== current_templates
->end
)
4017 /* We found no match. */
4019 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
4020 current_templates
->start
->name
);
4022 as_bad (_("suffix or operands invalid for `%s'"),
4023 current_templates
->start
->name
);
4027 if (!quiet_warnings
)
4030 && (i
.types
[0].bitfield
.jumpabsolute
4031 != operand_types
[0].bitfield
.jumpabsolute
))
4033 as_warn (_("indirect %s without `*'"), t
->name
);
4036 if (t
->opcode_modifier
.isprefix
4037 && t
->opcode_modifier
.ignoresize
)
4039 /* Warn them that a data or address size prefix doesn't
4040 affect assembly of the next line of code. */
4041 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4045 /* Copy the template we found. */
4048 if (addr_prefix_disp
!= -1)
4049 i
.tm
.operand_types
[addr_prefix_disp
]
4050 = operand_types
[addr_prefix_disp
];
4052 if (found_reverse_match
)
4054 /* If we found a reverse match we must alter the opcode
4055 direction bit. found_reverse_match holds bits to change
4056 (different for int & float insns). */
4058 i
.tm
.base_opcode
^= found_reverse_match
;
4060 i
.tm
.operand_types
[0] = operand_types
[1];
4061 i
.tm
.operand_types
[1] = operand_types
[0];
4070 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4071 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4073 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4075 as_bad (_("`%s' operand %d must use `%ses' segment"),
4081 /* There's only ever one segment override allowed per instruction.
4082 This instruction possibly has a legal segment override on the
4083 second operand, so copy the segment to where non-string
4084 instructions store it, allowing common code. */
4085 i
.seg
[0] = i
.seg
[1];
4087 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4089 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4091 as_bad (_("`%s' operand %d must use `%ses' segment"),
4102 process_suffix (void)
4104 /* If matched instruction specifies an explicit instruction mnemonic
4106 if (i
.tm
.opcode_modifier
.size16
)
4107 i
.suffix
= WORD_MNEM_SUFFIX
;
4108 else if (i
.tm
.opcode_modifier
.size32
)
4109 i
.suffix
= LONG_MNEM_SUFFIX
;
4110 else if (i
.tm
.opcode_modifier
.size64
)
4111 i
.suffix
= QWORD_MNEM_SUFFIX
;
4112 else if (i
.reg_operands
)
4114 /* If there's no instruction mnemonic suffix we try to invent one
4115 based on register operands. */
4118 /* We take i.suffix from the last register operand specified,
4119 Destination register type is more significant than source
4120 register type. crc32 in SSE4.2 prefers source register
4122 if (i
.tm
.base_opcode
== 0xf20f38f1)
4124 if (i
.types
[0].bitfield
.reg16
)
4125 i
.suffix
= WORD_MNEM_SUFFIX
;
4126 else if (i
.types
[0].bitfield
.reg32
)
4127 i
.suffix
= LONG_MNEM_SUFFIX
;
4128 else if (i
.types
[0].bitfield
.reg64
)
4129 i
.suffix
= QWORD_MNEM_SUFFIX
;
4131 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4133 if (i
.types
[0].bitfield
.reg8
)
4134 i
.suffix
= BYTE_MNEM_SUFFIX
;
4141 if (i
.tm
.base_opcode
== 0xf20f38f1
4142 || i
.tm
.base_opcode
== 0xf20f38f0)
4144 /* We have to know the operand size for crc32. */
4145 as_bad (_("ambiguous memory operand size for `%s`"),
4150 for (op
= i
.operands
; --op
>= 0;)
4151 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4153 if (i
.types
[op
].bitfield
.reg8
)
4155 i
.suffix
= BYTE_MNEM_SUFFIX
;
4158 else if (i
.types
[op
].bitfield
.reg16
)
4160 i
.suffix
= WORD_MNEM_SUFFIX
;
4163 else if (i
.types
[op
].bitfield
.reg32
)
4165 i
.suffix
= LONG_MNEM_SUFFIX
;
4168 else if (i
.types
[op
].bitfield
.reg64
)
4170 i
.suffix
= QWORD_MNEM_SUFFIX
;
4176 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4178 if (!check_byte_reg ())
4181 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4183 if (!check_long_reg ())
4186 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4189 && i
.tm
.opcode_modifier
.ignoresize
4190 && i
.tm
.opcode_modifier
.no_qsuf
)
4192 else if (!check_qword_reg ())
4195 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4197 if (!check_word_reg ())
4200 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4201 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4203 /* Skip if the instruction has x/y suffix. match_template
4204 should check if it is a valid suffix. */
4206 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4207 /* Do nothing if the instruction is going to ignore the prefix. */
4212 else if (i
.tm
.opcode_modifier
.defaultsize
4214 /* exclude fldenv/frstor/fsave/fstenv */
4215 && i
.tm
.opcode_modifier
.no_ssuf
)
4217 i
.suffix
= stackop_size
;
4219 else if (intel_syntax
4221 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4222 || i
.tm
.opcode_modifier
.jumpbyte
4223 || i
.tm
.opcode_modifier
.jumpintersegment
4224 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4225 && i
.tm
.extension_opcode
<= 3)))
4230 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4232 i
.suffix
= QWORD_MNEM_SUFFIX
;
4236 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4237 i
.suffix
= LONG_MNEM_SUFFIX
;
4240 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4241 i
.suffix
= WORD_MNEM_SUFFIX
;
4250 if (i
.tm
.opcode_modifier
.w
)
4252 as_bad (_("no instruction mnemonic suffix given and "
4253 "no register operands; can't size instruction"));
4259 unsigned int suffixes
;
4261 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4262 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4264 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4266 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4268 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4270 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4273 /* There are more than suffix matches. */
4274 if (i
.tm
.opcode_modifier
.w
4275 || ((suffixes
& (suffixes
- 1))
4276 && !i
.tm
.opcode_modifier
.defaultsize
4277 && !i
.tm
.opcode_modifier
.ignoresize
))
4279 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4285 /* Change the opcode based on the operand size given by i.suffix;
4286 We don't need to change things for byte insns. */
4289 && i
.suffix
!= BYTE_MNEM_SUFFIX
4290 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4291 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4293 /* It's not a byte, select word/dword operation. */
4294 if (i
.tm
.opcode_modifier
.w
)
4296 if (i
.tm
.opcode_modifier
.shortform
)
4297 i
.tm
.base_opcode
|= 8;
4299 i
.tm
.base_opcode
|= 1;
4302 /* Now select between word & dword operations via the operand
4303 size prefix, except for instructions that will ignore this
4305 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4307 /* The address size override prefix changes the size of the
4309 if ((flag_code
== CODE_32BIT
4310 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4311 || (flag_code
!= CODE_32BIT
4312 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4313 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4316 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4317 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4318 && !i
.tm
.opcode_modifier
.ignoresize
4319 && !i
.tm
.opcode_modifier
.floatmf
4320 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4321 || (flag_code
== CODE_64BIT
4322 && i
.tm
.opcode_modifier
.jumpbyte
)))
4324 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4326 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4327 prefix
= ADDR_PREFIX_OPCODE
;
4329 if (!add_prefix (prefix
))
4333 /* Set mode64 for an operand. */
4334 if (i
.suffix
== QWORD_MNEM_SUFFIX
4335 && flag_code
== CODE_64BIT
4336 && !i
.tm
.opcode_modifier
.norex64
)
4338 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4339 need rex64. cmpxchg8b is also a special case. */
4340 if (! (i
.operands
== 2
4341 && i
.tm
.base_opcode
== 0x90
4342 && i
.tm
.extension_opcode
== None
4343 && operand_type_equal (&i
.types
[0], &acc64
)
4344 && operand_type_equal (&i
.types
[1], &acc64
))
4345 && ! (i
.operands
== 1
4346 && i
.tm
.base_opcode
== 0xfc7
4347 && i
.tm
.extension_opcode
== 1
4348 && !operand_type_check (i
.types
[0], reg
)
4349 && operand_type_check (i
.types
[0], anymem
)))
4353 /* Size floating point instruction. */
4354 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4355 if (i
.tm
.opcode_modifier
.floatmf
)
4356 i
.tm
.base_opcode
^= 4;
4363 check_byte_reg (void)
4367 for (op
= i
.operands
; --op
>= 0;)
4369 /* If this is an eight bit register, it's OK. If it's the 16 or
4370 32 bit version of an eight bit register, we will just use the
4371 low portion, and that's OK too. */
4372 if (i
.types
[op
].bitfield
.reg8
)
4375 /* Don't generate this warning if not needed. */
4376 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4379 /* crc32 doesn't generate this warning. */
4380 if (i
.tm
.base_opcode
== 0xf20f38f0)
4383 if ((i
.types
[op
].bitfield
.reg16
4384 || i
.types
[op
].bitfield
.reg32
4385 || i
.types
[op
].bitfield
.reg64
)
4386 && i
.op
[op
].regs
->reg_num
< 4)
4388 /* Prohibit these changes in the 64bit mode, since the
4389 lowering is more complicated. */
4390 if (flag_code
== CODE_64BIT
4391 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4393 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4394 register_prefix
, i
.op
[op
].regs
->reg_name
,
4398 #if REGISTER_WARNINGS
4400 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4401 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4403 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4404 ? REGNAM_AL
- REGNAM_AX
4405 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4407 i
.op
[op
].regs
->reg_name
,
4412 /* Any other register is bad. */
4413 if (i
.types
[op
].bitfield
.reg16
4414 || i
.types
[op
].bitfield
.reg32
4415 || i
.types
[op
].bitfield
.reg64
4416 || i
.types
[op
].bitfield
.regmmx
4417 || i
.types
[op
].bitfield
.regxmm
4418 || i
.types
[op
].bitfield
.regymm
4419 || i
.types
[op
].bitfield
.sreg2
4420 || i
.types
[op
].bitfield
.sreg3
4421 || i
.types
[op
].bitfield
.control
4422 || i
.types
[op
].bitfield
.debug
4423 || i
.types
[op
].bitfield
.test
4424 || i
.types
[op
].bitfield
.floatreg
4425 || i
.types
[op
].bitfield
.floatacc
)
4427 as_bad (_("`%s%s' not allowed with `%s%c'"),
4429 i
.op
[op
].regs
->reg_name
,
4439 check_long_reg (void)
4443 for (op
= i
.operands
; --op
>= 0;)
4444 /* Reject eight bit registers, except where the template requires
4445 them. (eg. movzb) */
4446 if (i
.types
[op
].bitfield
.reg8
4447 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4448 || i
.tm
.operand_types
[op
].bitfield
.reg32
4449 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4451 as_bad (_("`%s%s' not allowed with `%s%c'"),
4453 i
.op
[op
].regs
->reg_name
,
4458 /* Warn if the e prefix on a general reg is missing. */
4459 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4460 && i
.types
[op
].bitfield
.reg16
4461 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4462 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4464 /* Prohibit these changes in the 64bit mode, since the
4465 lowering is more complicated. */
4466 if (flag_code
== CODE_64BIT
)
4468 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4469 register_prefix
, i
.op
[op
].regs
->reg_name
,
4473 #if REGISTER_WARNINGS
4475 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4477 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4479 i
.op
[op
].regs
->reg_name
,
4483 /* Warn if the r prefix on a general reg is missing. */
4484 else if (i
.types
[op
].bitfield
.reg64
4485 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4486 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4489 && i
.tm
.opcode_modifier
.toqword
4490 && !i
.types
[0].bitfield
.regxmm
)
4492 /* Convert to QWORD. We want REX byte. */
4493 i
.suffix
= QWORD_MNEM_SUFFIX
;
4497 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4498 register_prefix
, i
.op
[op
].regs
->reg_name
,
4507 check_qword_reg (void)
4511 for (op
= i
.operands
; --op
>= 0; )
4512 /* Reject eight bit registers, except where the template requires
4513 them. (eg. movzb) */
4514 if (i
.types
[op
].bitfield
.reg8
4515 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4516 || i
.tm
.operand_types
[op
].bitfield
.reg32
4517 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4519 as_bad (_("`%s%s' not allowed with `%s%c'"),
4521 i
.op
[op
].regs
->reg_name
,
4526 /* Warn if the e prefix on a general reg is missing. */
4527 else if ((i
.types
[op
].bitfield
.reg16
4528 || i
.types
[op
].bitfield
.reg32
)
4529 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4530 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4532 /* Prohibit these changes in the 64bit mode, since the
4533 lowering is more complicated. */
4535 && i
.tm
.opcode_modifier
.todword
4536 && !i
.types
[0].bitfield
.regxmm
)
4538 /* Convert to DWORD. We don't want REX byte. */
4539 i
.suffix
= LONG_MNEM_SUFFIX
;
4543 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4544 register_prefix
, i
.op
[op
].regs
->reg_name
,
4553 check_word_reg (void)
4556 for (op
= i
.operands
; --op
>= 0;)
4557 /* Reject eight bit registers, except where the template requires
4558 them. (eg. movzb) */
4559 if (i
.types
[op
].bitfield
.reg8
4560 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4561 || i
.tm
.operand_types
[op
].bitfield
.reg32
4562 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4564 as_bad (_("`%s%s' not allowed with `%s%c'"),
4566 i
.op
[op
].regs
->reg_name
,
4571 /* Warn if the e prefix on a general reg is present. */
4572 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4573 && i
.types
[op
].bitfield
.reg32
4574 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4575 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4577 /* Prohibit these changes in the 64bit mode, since the
4578 lowering is more complicated. */
4579 if (flag_code
== CODE_64BIT
)
4581 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4582 register_prefix
, i
.op
[op
].regs
->reg_name
,
4587 #if REGISTER_WARNINGS
4588 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4590 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4592 i
.op
[op
].regs
->reg_name
,
4600 update_imm (unsigned int j
)
4602 i386_operand_type overlap
= i
.types
[j
];
4603 if ((overlap
.bitfield
.imm8
4604 || overlap
.bitfield
.imm8s
4605 || overlap
.bitfield
.imm16
4606 || overlap
.bitfield
.imm32
4607 || overlap
.bitfield
.imm32s
4608 || overlap
.bitfield
.imm64
)
4609 && !operand_type_equal (&overlap
, &imm8
)
4610 && !operand_type_equal (&overlap
, &imm8s
)
4611 && !operand_type_equal (&overlap
, &imm16
)
4612 && !operand_type_equal (&overlap
, &imm32
)
4613 && !operand_type_equal (&overlap
, &imm32s
)
4614 && !operand_type_equal (&overlap
, &imm64
))
4618 i386_operand_type temp
;
4620 operand_type_set (&temp
, 0);
4621 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4623 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4624 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4626 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4627 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4628 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4630 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4631 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4634 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4637 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4638 || operand_type_equal (&overlap
, &imm16_32
)
4639 || operand_type_equal (&overlap
, &imm16_32s
))
4641 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4646 if (!operand_type_equal (&overlap
, &imm8
)
4647 && !operand_type_equal (&overlap
, &imm8s
)
4648 && !operand_type_equal (&overlap
, &imm16
)
4649 && !operand_type_equal (&overlap
, &imm32
)
4650 && !operand_type_equal (&overlap
, &imm32s
)
4651 && !operand_type_equal (&overlap
, &imm64
))
4653 as_bad (_("no instruction mnemonic suffix given; "
4654 "can't determine immediate size"));
4658 i
.types
[j
] = overlap
;
4668 /* Update the first 2 immediate operands. */
4669 n
= i
.operands
> 2 ? 2 : i
.operands
;
4672 for (j
= 0; j
< n
; j
++)
4673 if (update_imm (j
) == 0)
4676 /* The 3rd operand can't be immediate operand. */
4677 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4684 bad_implicit_operand (int xmm
)
4686 const char *reg
= xmm
? "xmm0" : "ymm0";
4688 as_bad (_("the last operand of `%s' must be `%s%s'"),
4689 i
.tm
.name
, register_prefix
, reg
);
4691 as_bad (_("the first operand of `%s' must be `%s%s'"),
4692 i
.tm
.name
, register_prefix
, reg
);
4697 process_operands (void)
4699 /* Default segment register this instruction will use for memory
4700 accesses. 0 means unknown. This is only for optimizing out
4701 unnecessary segment overrides. */
4702 const seg_entry
*default_seg
= 0;
4704 if (i
.tm
.opcode_modifier
.sse2avx
4705 && (i
.tm
.opcode_modifier
.vexnds
4706 || i
.tm
.opcode_modifier
.vexndd
))
4708 unsigned int dup
= i
.operands
;
4709 unsigned int dest
= dup
- 1;
4712 /* The destination must be an xmm register. */
4713 gas_assert (i
.reg_operands
4714 && MAX_OPERANDS
> dup
4715 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4717 if (i
.tm
.opcode_modifier
.firstxmm0
)
4719 /* The first operand is implicit and must be xmm0. */
4720 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4721 if (i
.op
[0].regs
->reg_num
!= 0)
4722 return bad_implicit_operand (1);
4724 if (i
.tm
.opcode_modifier
.vex3sources
)
4726 /* Keep xmm0 for instructions with VEX prefix and 3
4732 /* We remove the first xmm0 and keep the number of
4733 operands unchanged, which in fact duplicates the
4735 for (j
= 1; j
< i
.operands
; j
++)
4737 i
.op
[j
- 1] = i
.op
[j
];
4738 i
.types
[j
- 1] = i
.types
[j
];
4739 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4743 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4745 gas_assert ((MAX_OPERANDS
- 1) > dup
4746 && i
.tm
.opcode_modifier
.vex3sources
);
4748 /* Add the implicit xmm0 for instructions with VEX prefix
4750 for (j
= i
.operands
; j
> 0; j
--)
4752 i
.op
[j
] = i
.op
[j
- 1];
4753 i
.types
[j
] = i
.types
[j
- 1];
4754 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4757 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4758 i
.types
[0] = regxmm
;
4759 i
.tm
.operand_types
[0] = regxmm
;
4762 i
.reg_operands
+= 2;
4767 i
.op
[dup
] = i
.op
[dest
];
4768 i
.types
[dup
] = i
.types
[dest
];
4769 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4778 i
.op
[dup
] = i
.op
[dest
];
4779 i
.types
[dup
] = i
.types
[dest
];
4780 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4783 if (i
.tm
.opcode_modifier
.immext
)
4786 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4790 /* The first operand is implicit and must be xmm0/ymm0. */
4791 gas_assert (i
.reg_operands
4792 && (operand_type_equal (&i
.types
[0], ®xmm
)
4793 || operand_type_equal (&i
.types
[0], ®ymm
)));
4794 if (i
.op
[0].regs
->reg_num
!= 0)
4795 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4797 for (j
= 1; j
< i
.operands
; j
++)
4799 i
.op
[j
- 1] = i
.op
[j
];
4800 i
.types
[j
- 1] = i
.types
[j
];
4802 /* We need to adjust fields in i.tm since they are used by
4803 build_modrm_byte. */
4804 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4811 else if (i
.tm
.opcode_modifier
.regkludge
)
4813 /* The imul $imm, %reg instruction is converted into
4814 imul $imm, %reg, %reg, and the clr %reg instruction
4815 is converted into xor %reg, %reg. */
4817 unsigned int first_reg_op
;
4819 if (operand_type_check (i
.types
[0], reg
))
4823 /* Pretend we saw the extra register operand. */
4824 gas_assert (i
.reg_operands
== 1
4825 && i
.op
[first_reg_op
+ 1].regs
== 0);
4826 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4827 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4832 if (i
.tm
.opcode_modifier
.shortform
)
4834 if (i
.types
[0].bitfield
.sreg2
4835 || i
.types
[0].bitfield
.sreg3
)
4837 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4838 && i
.op
[0].regs
->reg_num
== 1)
4840 as_bad (_("you can't `pop %scs'"), register_prefix
);
4843 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4844 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4849 /* The register or float register operand is in operand
4853 if (i
.types
[0].bitfield
.floatreg
4854 || operand_type_check (i
.types
[0], reg
))
4858 /* Register goes in low 3 bits of opcode. */
4859 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4860 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4862 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4864 /* Warn about some common errors, but press on regardless.
4865 The first case can be generated by gcc (<= 2.8.1). */
4866 if (i
.operands
== 2)
4868 /* Reversed arguments on faddp, fsubp, etc. */
4869 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4870 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4871 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4875 /* Extraneous `l' suffix on fp insn. */
4876 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4877 register_prefix
, i
.op
[0].regs
->reg_name
);
4882 else if (i
.tm
.opcode_modifier
.modrm
)
4884 /* The opcode is completed (modulo i.tm.extension_opcode which
4885 must be put into the modrm byte). Now, we make the modrm and
4886 index base bytes based on all the info we've collected. */
4888 default_seg
= build_modrm_byte ();
4890 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4894 else if (i
.tm
.opcode_modifier
.isstring
)
4896 /* For the string instructions that allow a segment override
4897 on one of their operands, the default segment is ds. */
4901 if (i
.tm
.base_opcode
== 0x8d /* lea */
4904 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4906 /* If a segment was explicitly specified, and the specified segment
4907 is not the default, use an opcode prefix to select it. If we
4908 never figured out what the default segment is, then default_seg
4909 will be zero at this point, and the specified segment prefix will
4911 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4913 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4919 static const seg_entry
*
4920 build_modrm_byte (void)
4922 const seg_entry
*default_seg
= 0;
4923 unsigned int source
, dest
;
4924 int vex_3_sources
, vex_2_sources
;
4926 /* The first operand of instructions with VEX prefix and 3 sources
4927 must be VEX_Imm4. */
4928 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4929 vex_2_sources
= i
.tm
.opcode_modifier
.vex2sources
;
4932 unsigned int nds
, reg
;
4935 if (i
.tm
.opcode_modifier
.veximmext
4936 && i
.tm
.opcode_modifier
.immext
)
4938 dest
= i
.operands
- 2;
4939 gas_assert (dest
== 3);
4942 dest
= i
.operands
- 1;
4945 /* This instruction must have 4 register operands
4946 or 3 register operands plus 1 memory operand.
4947 It must have VexNDS and VexImmExt. */
4948 gas_assert ((i
.reg_operands
== 4
4949 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4950 && i
.tm
.opcode_modifier
.vexnds
4951 && i
.tm
.opcode_modifier
.veximmext
4952 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4953 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4955 /* Generate an 8bit immediate operand to encode the register
4957 exp
= &im_expressions
[i
.imm_operands
++];
4958 i
.op
[i
.operands
].imms
= exp
;
4959 i
.types
[i
.operands
] = imm8
;
4961 /* If VexW1 is set, the first operand is the source and
4962 the second operand is encoded in the immediate operand. */
4963 if (i
.tm
.opcode_modifier
.vexw1
)
4973 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4974 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4976 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4977 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4979 exp
->X_op
= O_constant
;
4981 = ((i
.op
[reg
].regs
->reg_num
4982 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4983 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4988 /* i.reg_operands MUST be the number of real register operands;
4989 implicit registers do not count. If there are 3 register
4990 operands, it must be a instruction with VexNDS. For a
4991 instruction with VexNDD, the destination register is encoded
4992 in VEX prefix. If there are 4 register operands, it must be
4993 a instruction with VEX prefix and 3 sources. */
4994 if (i
.mem_operands
== 0
4995 && ((i
.reg_operands
== 2
4996 && !i
.tm
.opcode_modifier
.vexndd
4997 && !i
.tm
.opcode_modifier
.vexlwp
)
4998 || (i
.reg_operands
== 3
4999 && i
.tm
.opcode_modifier
.vexnds
)
5000 || (i
.reg_operands
== 4 && vex_3_sources
)))
5008 /* When there are 3 operands, one of them may be immediate,
5009 which may be the first or the last operand. Otherwise,
5010 the first operand must be shift count register (cl) or it
5011 is an instruction with VexNDS. */
5012 gas_assert (i
.imm_operands
== 1
5013 || (i
.imm_operands
== 0
5014 && (i
.tm
.opcode_modifier
.vexnds
5015 || i
.types
[0].bitfield
.shiftcount
)));
5016 if (operand_type_check (i
.types
[0], imm
)
5017 || i
.types
[0].bitfield
.shiftcount
)
5023 /* When there are 4 operands, the first two must be 8bit
5024 immediate operands. The source operand will be the 3rd
5027 For instructions with VexNDS, if the first operand
5028 an imm8, the source operand is the 2nd one. If the last
5029 operand is imm8, the source operand is the first one. */
5030 gas_assert ((i
.imm_operands
== 2
5031 && i
.types
[0].bitfield
.imm8
5032 && i
.types
[1].bitfield
.imm8
)
5033 || (i
.tm
.opcode_modifier
.vexnds
5034 && i
.imm_operands
== 1
5035 && (i
.types
[0].bitfield
.imm8
5036 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5037 if (i
.tm
.opcode_modifier
.vexnds
)
5039 if (i
.types
[0].bitfield
.imm8
)
5057 if (i
.tm
.opcode_modifier
.vexnds
)
5059 /* For instructions with VexNDS, the register-only
5060 source operand must be XMM or YMM register. It is
5061 encoded in VEX prefix. We need to clear RegMem bit
5062 before calling operand_type_equal. */
5063 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5064 op
.bitfield
.regmem
= 0;
5065 if ((dest
+ 1) >= i
.operands
5066 || (!operand_type_equal (&op
, ®xmm
)
5067 && !operand_type_equal (&op
, ®ymm
)))
5069 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5075 /* One of the register operands will be encoded in the i.tm.reg
5076 field, the other in the combined i.tm.mode and i.tm.regmem
5077 fields. If no form of this instruction supports a memory
5078 destination operand, then we assume the source operand may
5079 sometimes be a memory operand and so we need to store the
5080 destination in the i.rm.reg field. */
5081 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5082 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5084 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5085 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5086 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5088 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5093 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5094 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5095 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5097 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5100 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5102 if (!i
.types
[0].bitfield
.control
5103 && !i
.types
[1].bitfield
.control
)
5105 i
.rex
&= ~(REX_R
| REX_B
);
5106 add_prefix (LOCK_PREFIX_OPCODE
);
5110 { /* If it's not 2 reg operands... */
5115 unsigned int fake_zero_displacement
= 0;
5118 for (op
= 0; op
< i
.operands
; op
++)
5119 if (operand_type_check (i
.types
[op
], anymem
))
5121 gas_assert (op
< i
.operands
);
5125 if (i
.base_reg
== 0)
5128 if (!i
.disp_operands
)
5129 fake_zero_displacement
= 1;
5130 if (i
.index_reg
== 0)
5132 /* Operand is just <disp> */
5133 if (flag_code
== CODE_64BIT
)
5135 /* 64bit mode overwrites the 32bit absolute
5136 addressing by RIP relative addressing and
5137 absolute addressing is encoded by one of the
5138 redundant SIB forms. */
5139 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5140 i
.sib
.base
= NO_BASE_REGISTER
;
5141 i
.sib
.index
= NO_INDEX_REGISTER
;
5142 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5143 ? disp32s
: disp32
);
5145 else if ((flag_code
== CODE_16BIT
)
5146 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5148 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5149 i
.types
[op
] = disp16
;
5153 i
.rm
.regmem
= NO_BASE_REGISTER
;
5154 i
.types
[op
] = disp32
;
5157 else /* !i.base_reg && i.index_reg */
5159 if (i
.index_reg
->reg_num
== RegEiz
5160 || i
.index_reg
->reg_num
== RegRiz
)
5161 i
.sib
.index
= NO_INDEX_REGISTER
;
5163 i
.sib
.index
= i
.index_reg
->reg_num
;
5164 i
.sib
.base
= NO_BASE_REGISTER
;
5165 i
.sib
.scale
= i
.log2_scale_factor
;
5166 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5167 i
.types
[op
].bitfield
.disp8
= 0;
5168 i
.types
[op
].bitfield
.disp16
= 0;
5169 i
.types
[op
].bitfield
.disp64
= 0;
5170 if (flag_code
!= CODE_64BIT
)
5172 /* Must be 32 bit */
5173 i
.types
[op
].bitfield
.disp32
= 1;
5174 i
.types
[op
].bitfield
.disp32s
= 0;
5178 i
.types
[op
].bitfield
.disp32
= 0;
5179 i
.types
[op
].bitfield
.disp32s
= 1;
5181 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5185 /* RIP addressing for 64bit mode. */
5186 else if (i
.base_reg
->reg_num
== RegRip
||
5187 i
.base_reg
->reg_num
== RegEip
)
5189 i
.rm
.regmem
= NO_BASE_REGISTER
;
5190 i
.types
[op
].bitfield
.disp8
= 0;
5191 i
.types
[op
].bitfield
.disp16
= 0;
5192 i
.types
[op
].bitfield
.disp32
= 0;
5193 i
.types
[op
].bitfield
.disp32s
= 1;
5194 i
.types
[op
].bitfield
.disp64
= 0;
5195 i
.flags
[op
] |= Operand_PCrel
;
5196 if (! i
.disp_operands
)
5197 fake_zero_displacement
= 1;
5199 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5201 switch (i
.base_reg
->reg_num
)
5204 if (i
.index_reg
== 0)
5206 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5207 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5211 if (i
.index_reg
== 0)
5214 if (operand_type_check (i
.types
[op
], disp
) == 0)
5216 /* fake (%bp) into 0(%bp) */
5217 i
.types
[op
].bitfield
.disp8
= 1;
5218 fake_zero_displacement
= 1;
5221 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5222 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5224 default: /* (%si) -> 4 or (%di) -> 5 */
5225 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5227 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5229 else /* i.base_reg and 32/64 bit mode */
5231 if (flag_code
== CODE_64BIT
5232 && operand_type_check (i
.types
[op
], disp
))
5234 i386_operand_type temp
;
5235 operand_type_set (&temp
, 0);
5236 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5238 if (i
.prefix
[ADDR_PREFIX
] == 0)
5239 i
.types
[op
].bitfield
.disp32s
= 1;
5241 i
.types
[op
].bitfield
.disp32
= 1;
5244 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5245 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5247 i
.sib
.base
= i
.base_reg
->reg_num
;
5248 /* x86-64 ignores REX prefix bit here to avoid decoder
5250 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5253 if (i
.disp_operands
== 0)
5255 fake_zero_displacement
= 1;
5256 i
.types
[op
].bitfield
.disp8
= 1;
5259 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5263 i
.sib
.scale
= i
.log2_scale_factor
;
5264 if (i
.index_reg
== 0)
5266 /* <disp>(%esp) becomes two byte modrm with no index
5267 register. We've already stored the code for esp
5268 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5269 Any base register besides %esp will not use the
5270 extra modrm byte. */
5271 i
.sib
.index
= NO_INDEX_REGISTER
;
5275 if (i
.index_reg
->reg_num
== RegEiz
5276 || i
.index_reg
->reg_num
== RegRiz
)
5277 i
.sib
.index
= NO_INDEX_REGISTER
;
5279 i
.sib
.index
= i
.index_reg
->reg_num
;
5280 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5281 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5286 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5287 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5290 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5293 if (fake_zero_displacement
)
5295 /* Fakes a zero displacement assuming that i.types[op]
5296 holds the correct displacement size. */
5299 gas_assert (i
.op
[op
].disps
== 0);
5300 exp
= &disp_expressions
[i
.disp_operands
++];
5301 i
.op
[op
].disps
= exp
;
5302 exp
->X_op
= O_constant
;
5303 exp
->X_add_number
= 0;
5304 exp
->X_add_symbol
= (symbolS
*) 0;
5305 exp
->X_op_symbol
= (symbolS
*) 0;
5315 if (operand_type_check (i
.types
[0], imm
))
5316 i
.vex
.register_specifier
= NULL
;
5319 /* VEX.vvvv encodes one of the sources when the first
5320 operand is not an immediate. */
5321 if (i
.tm
.opcode_modifier
.vexw0
)
5322 i
.vex
.register_specifier
= i
.op
[0].regs
;
5324 i
.vex
.register_specifier
= i
.op
[1].regs
;
5327 /* Destination is a XMM register encoded in the ModRM.reg
5329 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5330 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5333 /* ModRM.rm and VEX.B encodes the other source. */
5334 if (!i
.mem_operands
)
5338 if (i
.tm
.opcode_modifier
.vexw0
)
5339 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5341 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5343 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5347 else if (i
.tm
.opcode_modifier
.vexlwp
)
5349 i
.vex
.register_specifier
= i
.op
[2].regs
;
5350 if (!i
.mem_operands
)
5353 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5354 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5358 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5359 (if any) based on i.tm.extension_opcode. Again, we must be
5360 careful to make sure that segment/control/debug/test/MMX
5361 registers are coded into the i.rm.reg field. */
5362 else if (i
.reg_operands
)
5365 unsigned int vex_reg
= ~0;
5367 for (op
= 0; op
< i
.operands
; op
++)
5368 if (i
.types
[op
].bitfield
.reg8
5369 || i
.types
[op
].bitfield
.reg16
5370 || i
.types
[op
].bitfield
.reg32
5371 || i
.types
[op
].bitfield
.reg64
5372 || i
.types
[op
].bitfield
.regmmx
5373 || i
.types
[op
].bitfield
.regxmm
5374 || i
.types
[op
].bitfield
.regymm
5375 || i
.types
[op
].bitfield
.sreg2
5376 || i
.types
[op
].bitfield
.sreg3
5377 || i
.types
[op
].bitfield
.control
5378 || i
.types
[op
].bitfield
.debug
5379 || i
.types
[op
].bitfield
.test
)
5384 else if (i
.tm
.opcode_modifier
.vexnds
)
5386 /* For instructions with VexNDS, the register-only
5387 source operand is encoded in VEX prefix. */
5388 gas_assert (mem
!= (unsigned int) ~0);
5393 gas_assert (op
< i
.operands
);
5398 gas_assert (vex_reg
< i
.operands
);
5401 else if (i
.tm
.opcode_modifier
.vexndd
)
5403 /* For instructions with VexNDD, there should be
5404 no memory operand and the register destination
5405 is encoded in VEX prefix. */
5406 gas_assert (i
.mem_operands
== 0
5407 && (op
+ 2) == i
.operands
);
5411 gas_assert (op
< i
.operands
);
5413 if (vex_reg
!= (unsigned int) ~0)
5415 gas_assert (i
.reg_operands
== 2);
5417 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5419 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5423 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5426 /* Don't set OP operand twice. */
5429 /* If there is an extension opcode to put here, the
5430 register number must be put into the regmem field. */
5431 if (i
.tm
.extension_opcode
!= None
)
5433 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5434 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5439 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5440 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5445 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5446 must set it to 3 to indicate this is a register operand
5447 in the regmem field. */
5448 if (!i
.mem_operands
)
5452 /* Fill in i.rm.reg field with extension opcode (if any). */
5453 if (i
.tm
.extension_opcode
!= None
)
5454 i
.rm
.reg
= i
.tm
.extension_opcode
;
5460 output_branch (void)
5465 relax_substateT subtype
;
5470 if (flag_code
== CODE_16BIT
)
5474 if (i
.prefix
[DATA_PREFIX
] != 0)
5480 /* Pentium4 branch hints. */
5481 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5482 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5487 if (i
.prefix
[REX_PREFIX
] != 0)
5493 if (i
.prefixes
!= 0 && !intel_syntax
)
5494 as_warn (_("skipping prefixes on this instruction"));
5496 /* It's always a symbol; End frag & setup for relax.
5497 Make sure there is enough room in this frag for the largest
5498 instruction we may generate in md_convert_frag. This is 2
5499 bytes for the opcode and room for the prefix and largest
5501 frag_grow (prefix
+ 2 + 4);
5502 /* Prefix and 1 opcode byte go in fr_fix. */
5503 p
= frag_more (prefix
+ 1);
5504 if (i
.prefix
[DATA_PREFIX
] != 0)
5505 *p
++ = DATA_PREFIX_OPCODE
;
5506 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5507 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5508 *p
++ = i
.prefix
[SEG_PREFIX
];
5509 if (i
.prefix
[REX_PREFIX
] != 0)
5510 *p
++ = i
.prefix
[REX_PREFIX
];
5511 *p
= i
.tm
.base_opcode
;
5513 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5514 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5515 else if (cpu_arch_flags
.bitfield
.cpui386
)
5516 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5518 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5521 sym
= i
.op
[0].disps
->X_add_symbol
;
5522 off
= i
.op
[0].disps
->X_add_number
;
5524 if (i
.op
[0].disps
->X_op
!= O_constant
5525 && i
.op
[0].disps
->X_op
!= O_symbol
)
5527 /* Handle complex expressions. */
5528 sym
= make_expr_symbol (i
.op
[0].disps
);
5532 /* 1 possible extra opcode + 4 byte displacement go in var part.
5533 Pass reloc in fr_var. */
5534 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5544 if (i
.tm
.opcode_modifier
.jumpbyte
)
5546 /* This is a loop or jecxz type instruction. */
5548 if (i
.prefix
[ADDR_PREFIX
] != 0)
5550 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5553 /* Pentium4 branch hints. */
5554 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5555 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5557 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5566 if (flag_code
== CODE_16BIT
)
5569 if (i
.prefix
[DATA_PREFIX
] != 0)
5571 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5581 if (i
.prefix
[REX_PREFIX
] != 0)
5583 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5587 if (i
.prefixes
!= 0 && !intel_syntax
)
5588 as_warn (_("skipping prefixes on this instruction"));
5590 p
= frag_more (1 + size
);
5591 *p
++ = i
.tm
.base_opcode
;
5593 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5594 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5596 /* All jumps handled here are signed, but don't use a signed limit
5597 check for 32 and 16 bit jumps as we want to allow wrap around at
5598 4G and 64k respectively. */
5600 fixP
->fx_signed
= 1;
5604 output_interseg_jump (void)
5612 if (flag_code
== CODE_16BIT
)
5616 if (i
.prefix
[DATA_PREFIX
] != 0)
5622 if (i
.prefix
[REX_PREFIX
] != 0)
5632 if (i
.prefixes
!= 0 && !intel_syntax
)
5633 as_warn (_("skipping prefixes on this instruction"));
5635 /* 1 opcode; 2 segment; offset */
5636 p
= frag_more (prefix
+ 1 + 2 + size
);
5638 if (i
.prefix
[DATA_PREFIX
] != 0)
5639 *p
++ = DATA_PREFIX_OPCODE
;
5641 if (i
.prefix
[REX_PREFIX
] != 0)
5642 *p
++ = i
.prefix
[REX_PREFIX
];
5644 *p
++ = i
.tm
.base_opcode
;
5645 if (i
.op
[1].imms
->X_op
== O_constant
)
5647 offsetT n
= i
.op
[1].imms
->X_add_number
;
5650 && !fits_in_unsigned_word (n
)
5651 && !fits_in_signed_word (n
))
5653 as_bad (_("16-bit jump out of range"));
5656 md_number_to_chars (p
, n
, size
);
5659 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5660 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5661 if (i
.op
[0].imms
->X_op
!= O_constant
)
5662 as_bad (_("can't handle non absolute segment in `%s'"),
5664 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5670 fragS
*insn_start_frag
;
5671 offsetT insn_start_off
;
5673 /* Tie dwarf2 debug info to the address at the start of the insn.
5674 We can't do this after the insn has been output as the current
5675 frag may have been closed off. eg. by frag_var. */
5676 dwarf2_emit_insn (0);
5678 insn_start_frag
= frag_now
;
5679 insn_start_off
= frag_now_fix ();
5682 if (i
.tm
.opcode_modifier
.jump
)
5684 else if (i
.tm
.opcode_modifier
.jumpbyte
5685 || i
.tm
.opcode_modifier
.jumpdword
)
5687 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5688 output_interseg_jump ();
5691 /* Output normal instructions here. */
5695 unsigned int prefix
;
5697 /* Since the VEX prefix contains the implicit prefix, we don't
5698 need the explicit prefix. */
5699 if (!i
.tm
.opcode_modifier
.vex
)
5701 switch (i
.tm
.opcode_length
)
5704 if (i
.tm
.base_opcode
& 0xff000000)
5706 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5711 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5713 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5714 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5717 if (prefix
!= REPE_PREFIX_OPCODE
5718 || (i
.prefix
[REP_PREFIX
]
5719 != REPE_PREFIX_OPCODE
))
5720 add_prefix (prefix
);
5723 add_prefix (prefix
);
5732 /* The prefix bytes. */
5733 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5735 FRAG_APPEND_1_CHAR (*q
);
5738 if (i
.tm
.opcode_modifier
.vex
)
5740 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5745 /* REX byte is encoded in VEX prefix. */
5749 FRAG_APPEND_1_CHAR (*q
);
5752 /* There should be no other prefixes for instructions
5757 /* Now the VEX prefix. */
5758 p
= frag_more (i
.vex
.length
);
5759 for (j
= 0; j
< i
.vex
.length
; j
++)
5760 p
[j
] = i
.vex
.bytes
[j
];
5763 /* Now the opcode; be careful about word order here! */
5764 if (i
.tm
.opcode_length
== 1)
5766 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5770 switch (i
.tm
.opcode_length
)
5774 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5784 /* Put out high byte first: can't use md_number_to_chars! */
5785 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5786 *p
= i
.tm
.base_opcode
& 0xff;
5789 /* Now the modrm byte and sib byte (if present). */
5790 if (i
.tm
.opcode_modifier
.modrm
)
5792 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5795 /* If i.rm.regmem == ESP (4)
5796 && i.rm.mode != (Register mode)
5798 ==> need second modrm byte. */
5799 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5801 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5802 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5804 | i
.sib
.scale
<< 6));
5807 if (i
.disp_operands
)
5808 output_disp (insn_start_frag
, insn_start_off
);
5811 output_imm (insn_start_frag
, insn_start_off
);
5817 pi ("" /*line*/, &i
);
5819 #endif /* DEBUG386 */
5822 /* Return the size of the displacement operand N. */
5825 disp_size (unsigned int n
)
5828 if (i
.types
[n
].bitfield
.disp64
)
5830 else if (i
.types
[n
].bitfield
.disp8
)
5832 else if (i
.types
[n
].bitfield
.disp16
)
5837 /* Return the size of the immediate operand N. */
5840 imm_size (unsigned int n
)
5843 if (i
.types
[n
].bitfield
.imm64
)
5845 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5847 else if (i
.types
[n
].bitfield
.imm16
)
5853 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5858 for (n
= 0; n
< i
.operands
; n
++)
5860 if (operand_type_check (i
.types
[n
], disp
))
5862 if (i
.op
[n
].disps
->X_op
== O_constant
)
5864 int size
= disp_size (n
);
5867 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5869 p
= frag_more (size
);
5870 md_number_to_chars (p
, val
, size
);
5874 enum bfd_reloc_code_real reloc_type
;
5875 int size
= disp_size (n
);
5876 int sign
= i
.types
[n
].bitfield
.disp32s
;
5877 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5879 /* We can't have 8 bit displacement here. */
5880 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5882 /* The PC relative address is computed relative
5883 to the instruction boundary, so in case immediate
5884 fields follows, we need to adjust the value. */
5885 if (pcrel
&& i
.imm_operands
)
5890 for (n1
= 0; n1
< i
.operands
; n1
++)
5891 if (operand_type_check (i
.types
[n1
], imm
))
5893 /* Only one immediate is allowed for PC
5894 relative address. */
5895 gas_assert (sz
== 0);
5897 i
.op
[n
].disps
->X_add_number
-= sz
;
5899 /* We should find the immediate. */
5900 gas_assert (sz
!= 0);
5903 p
= frag_more (size
);
5904 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5906 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5907 && (((reloc_type
== BFD_RELOC_32
5908 || reloc_type
== BFD_RELOC_X86_64_32S
5909 || (reloc_type
== BFD_RELOC_64
5911 && (i
.op
[n
].disps
->X_op
== O_symbol
5912 || (i
.op
[n
].disps
->X_op
== O_add
5913 && ((symbol_get_value_expression
5914 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5916 || reloc_type
== BFD_RELOC_32_PCREL
))
5920 if (insn_start_frag
== frag_now
)
5921 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5926 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5927 for (fr
= insn_start_frag
->fr_next
;
5928 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5930 add
+= p
- frag_now
->fr_literal
;
5935 reloc_type
= BFD_RELOC_386_GOTPC
;
5936 i
.op
[n
].imms
->X_add_number
+= add
;
5938 else if (reloc_type
== BFD_RELOC_64
)
5939 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5941 /* Don't do the adjustment for x86-64, as there
5942 the pcrel addressing is relative to the _next_
5943 insn, and that is taken care of in other code. */
5944 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5946 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5947 i
.op
[n
].disps
, pcrel
, reloc_type
);
5954 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5959 for (n
= 0; n
< i
.operands
; n
++)
5961 if (operand_type_check (i
.types
[n
], imm
))
5963 if (i
.op
[n
].imms
->X_op
== O_constant
)
5965 int size
= imm_size (n
);
5968 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5970 p
= frag_more (size
);
5971 md_number_to_chars (p
, val
, size
);
5975 /* Not absolute_section.
5976 Need a 32-bit fixup (don't support 8bit
5977 non-absolute imms). Try to support other
5979 enum bfd_reloc_code_real reloc_type
;
5980 int size
= imm_size (n
);
5983 if (i
.types
[n
].bitfield
.imm32s
5984 && (i
.suffix
== QWORD_MNEM_SUFFIX
5985 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5990 p
= frag_more (size
);
5991 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5993 /* This is tough to explain. We end up with this one if we
5994 * have operands that look like
5995 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5996 * obtain the absolute address of the GOT, and it is strongly
5997 * preferable from a performance point of view to avoid using
5998 * a runtime relocation for this. The actual sequence of
5999 * instructions often look something like:
6004 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6006 * The call and pop essentially return the absolute address
6007 * of the label .L66 and store it in %ebx. The linker itself
6008 * will ultimately change the first operand of the addl so
6009 * that %ebx points to the GOT, but to keep things simple, the
6010 * .o file must have this operand set so that it generates not
6011 * the absolute address of .L66, but the absolute address of
6012 * itself. This allows the linker itself simply treat a GOTPC
6013 * relocation as asking for a pcrel offset to the GOT to be
6014 * added in, and the addend of the relocation is stored in the
6015 * operand field for the instruction itself.
6017 * Our job here is to fix the operand so that it would add
6018 * the correct offset so that %ebx would point to itself. The
6019 * thing that is tricky is that .-.L66 will point to the
6020 * beginning of the instruction, so we need to further modify
6021 * the operand so that it will point to itself. There are
6022 * other cases where you have something like:
6024 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6026 * and here no correction would be required. Internally in
6027 * the assembler we treat operands of this form as not being
6028 * pcrel since the '.' is explicitly mentioned, and I wonder
6029 * whether it would simplify matters to do it this way. Who
6030 * knows. In earlier versions of the PIC patches, the
6031 * pcrel_adjust field was used to store the correction, but
6032 * since the expression is not pcrel, I felt it would be
6033 * confusing to do it this way. */
6035 if ((reloc_type
== BFD_RELOC_32
6036 || reloc_type
== BFD_RELOC_X86_64_32S
6037 || reloc_type
== BFD_RELOC_64
)
6039 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6040 && (i
.op
[n
].imms
->X_op
== O_symbol
6041 || (i
.op
[n
].imms
->X_op
== O_add
6042 && ((symbol_get_value_expression
6043 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6048 if (insn_start_frag
== frag_now
)
6049 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6054 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6055 for (fr
= insn_start_frag
->fr_next
;
6056 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6058 add
+= p
- frag_now
->fr_literal
;
6062 reloc_type
= BFD_RELOC_386_GOTPC
;
6064 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6066 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6067 i
.op
[n
].imms
->X_add_number
+= add
;
6069 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6070 i
.op
[n
].imms
, 0, reloc_type
);
6076 /* x86_cons_fix_new is called via the expression parsing code when a
6077 reloc is needed. We use this hook to get the correct .got reloc. */
6078 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6079 static int cons_sign
= -1;
6082 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6085 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6087 got_reloc
= NO_RELOC
;
6090 if (exp
->X_op
== O_secrel
)
6092 exp
->X_op
= O_symbol
;
6093 r
= BFD_RELOC_32_SECREL
;
6097 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6100 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6101 # define lex_got(reloc, adjust, types) NULL
6103 /* Parse operands of the form
6104 <symbol>@GOTOFF+<nnn>
6105 and similar .plt or .got references.
6107 If we find one, set up the correct relocation in RELOC and copy the
6108 input string, minus the `@GOTOFF' into a malloc'd buffer for
6109 parsing by the calling routine. Return this buffer, and if ADJUST
6110 is non-null set it to the length of the string we removed from the
6111 input line. Otherwise return NULL. */
6113 lex_got (enum bfd_reloc_code_real
*reloc
,
6115 i386_operand_type
*types
)
6117 /* Some of the relocations depend on the size of what field is to
6118 be relocated. But in our callers i386_immediate and i386_displacement
6119 we don't yet know the operand size (this will be set by insn
6120 matching). Hence we record the word32 relocation here,
6121 and adjust the reloc according to the real size in reloc(). */
6122 static const struct {
6124 const enum bfd_reloc_code_real rel
[2];
6125 const i386_operand_type types64
;
6127 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6128 BFD_RELOC_X86_64_PLTOFF64
},
6129 OPERAND_TYPE_IMM64
},
6130 { "PLT", { BFD_RELOC_386_PLT32
,
6131 BFD_RELOC_X86_64_PLT32
},
6132 OPERAND_TYPE_IMM32_32S_DISP32
},
6133 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6134 BFD_RELOC_X86_64_GOTPLT64
},
6135 OPERAND_TYPE_IMM64_DISP64
},
6136 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6137 BFD_RELOC_X86_64_GOTOFF64
},
6138 OPERAND_TYPE_IMM64_DISP64
},
6139 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6140 BFD_RELOC_X86_64_GOTPCREL
},
6141 OPERAND_TYPE_IMM32_32S_DISP32
},
6142 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6143 BFD_RELOC_X86_64_TLSGD
},
6144 OPERAND_TYPE_IMM32_32S_DISP32
},
6145 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6146 _dummy_first_bfd_reloc_code_real
},
6147 OPERAND_TYPE_NONE
},
6148 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6149 BFD_RELOC_X86_64_TLSLD
},
6150 OPERAND_TYPE_IMM32_32S_DISP32
},
6151 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6152 BFD_RELOC_X86_64_GOTTPOFF
},
6153 OPERAND_TYPE_IMM32_32S_DISP32
},
6154 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6155 BFD_RELOC_X86_64_TPOFF32
},
6156 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6157 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6158 _dummy_first_bfd_reloc_code_real
},
6159 OPERAND_TYPE_NONE
},
6160 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6161 BFD_RELOC_X86_64_DTPOFF32
},
6163 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6164 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6165 _dummy_first_bfd_reloc_code_real
},
6166 OPERAND_TYPE_NONE
},
6167 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6168 _dummy_first_bfd_reloc_code_real
},
6169 OPERAND_TYPE_NONE
},
6170 { "GOT", { BFD_RELOC_386_GOT32
,
6171 BFD_RELOC_X86_64_GOT32
},
6172 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6173 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6174 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6175 OPERAND_TYPE_IMM32_32S_DISP32
},
6176 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6177 BFD_RELOC_X86_64_TLSDESC_CALL
},
6178 OPERAND_TYPE_IMM32_32S_DISP32
},
6186 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6187 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6190 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6194 len
= strlen (gotrel
[j
].str
);
6195 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6197 if (gotrel
[j
].rel
[object_64bit
] != 0)
6200 char *tmpbuf
, *past_reloc
;
6202 *reloc
= gotrel
[j
].rel
[object_64bit
];
6208 if (flag_code
!= CODE_64BIT
)
6210 types
->bitfield
.imm32
= 1;
6211 types
->bitfield
.disp32
= 1;
6214 *types
= gotrel
[j
].types64
;
6217 if (GOT_symbol
== NULL
)
6218 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6220 /* The length of the first part of our input line. */
6221 first
= cp
- input_line_pointer
;
6223 /* The second part goes from after the reloc token until
6224 (and including) an end_of_line char or comma. */
6225 past_reloc
= cp
+ 1 + len
;
6227 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6229 second
= cp
+ 1 - past_reloc
;
6231 /* Allocate and copy string. The trailing NUL shouldn't
6232 be necessary, but be safe. */
6233 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6234 memcpy (tmpbuf
, input_line_pointer
, first
);
6235 if (second
!= 0 && *past_reloc
!= ' ')
6236 /* Replace the relocation token with ' ', so that
6237 errors like foo@GOTOFF1 will be detected. */
6238 tmpbuf
[first
++] = ' ';
6239 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6240 tmpbuf
[first
+ second
] = '\0';
6244 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6245 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6250 /* Might be a symbol version string. Don't as_bad here. */
6255 x86_cons (expressionS
*exp
, int size
)
6257 intel_syntax
= -intel_syntax
;
6259 if (size
== 4 || (object_64bit
&& size
== 8))
6261 /* Handle @GOTOFF and the like in an expression. */
6263 char *gotfree_input_line
;
6266 save
= input_line_pointer
;
6267 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6268 if (gotfree_input_line
)
6269 input_line_pointer
= gotfree_input_line
;
6273 if (gotfree_input_line
)
6275 /* expression () has merrily parsed up to the end of line,
6276 or a comma - in the wrong buffer. Transfer how far
6277 input_line_pointer has moved to the right buffer. */
6278 input_line_pointer
= (save
6279 + (input_line_pointer
- gotfree_input_line
)
6281 free (gotfree_input_line
);
6282 if (exp
->X_op
== O_constant
6283 || exp
->X_op
== O_absent
6284 || exp
->X_op
== O_illegal
6285 || exp
->X_op
== O_register
6286 || exp
->X_op
== O_big
)
6288 char c
= *input_line_pointer
;
6289 *input_line_pointer
= 0;
6290 as_bad (_("missing or invalid expression `%s'"), save
);
6291 *input_line_pointer
= c
;
6298 intel_syntax
= -intel_syntax
;
6301 i386_intel_simplify (exp
);
6306 signed_cons (int size
)
6308 if (flag_code
== CODE_64BIT
)
6316 pe_directive_secrel (dummy
)
6317 int dummy ATTRIBUTE_UNUSED
;
6324 if (exp
.X_op
== O_symbol
)
6325 exp
.X_op
= O_secrel
;
6327 emit_expr (&exp
, 4);
6329 while (*input_line_pointer
++ == ',');
6331 input_line_pointer
--;
6332 demand_empty_rest_of_line ();
6337 i386_immediate (char *imm_start
)
6339 char *save_input_line_pointer
;
6340 char *gotfree_input_line
;
6343 i386_operand_type types
;
6345 operand_type_set (&types
, ~0);
6347 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6349 as_bad (_("at most %d immediate operands are allowed"),
6350 MAX_IMMEDIATE_OPERANDS
);
6354 exp
= &im_expressions
[i
.imm_operands
++];
6355 i
.op
[this_operand
].imms
= exp
;
6357 if (is_space_char (*imm_start
))
6360 save_input_line_pointer
= input_line_pointer
;
6361 input_line_pointer
= imm_start
;
6363 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6364 if (gotfree_input_line
)
6365 input_line_pointer
= gotfree_input_line
;
6367 exp_seg
= expression (exp
);
6370 if (*input_line_pointer
)
6371 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6373 input_line_pointer
= save_input_line_pointer
;
6374 if (gotfree_input_line
)
6376 free (gotfree_input_line
);
6378 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6379 exp
->X_op
= O_illegal
;
6382 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6386 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6387 i386_operand_type types
, const char *imm_start
)
6389 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6392 as_bad (_("missing or invalid immediate expression `%s'"),
6396 else if (exp
->X_op
== O_constant
)
6398 /* Size it properly later. */
6399 i
.types
[this_operand
].bitfield
.imm64
= 1;
6400 /* If BFD64, sign extend val. */
6401 if (!use_rela_relocations
6402 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6404 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6406 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6407 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6408 && exp_seg
!= absolute_section
6409 && exp_seg
!= text_section
6410 && exp_seg
!= data_section
6411 && exp_seg
!= bss_section
6412 && exp_seg
!= undefined_section
6413 && !bfd_is_com_section (exp_seg
))
6415 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6419 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6422 as_bad (_("illegal immediate register operand %s"), imm_start
);
6427 /* This is an address. The size of the address will be
6428 determined later, depending on destination register,
6429 suffix, or the default for the section. */
6430 i
.types
[this_operand
].bitfield
.imm8
= 1;
6431 i
.types
[this_operand
].bitfield
.imm16
= 1;
6432 i
.types
[this_operand
].bitfield
.imm32
= 1;
6433 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6434 i
.types
[this_operand
].bitfield
.imm64
= 1;
6435 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6443 i386_scale (char *scale
)
6446 char *save
= input_line_pointer
;
6448 input_line_pointer
= scale
;
6449 val
= get_absolute_expression ();
6454 i
.log2_scale_factor
= 0;
6457 i
.log2_scale_factor
= 1;
6460 i
.log2_scale_factor
= 2;
6463 i
.log2_scale_factor
= 3;
6467 char sep
= *input_line_pointer
;
6469 *input_line_pointer
= '\0';
6470 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6472 *input_line_pointer
= sep
;
6473 input_line_pointer
= save
;
6477 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6479 as_warn (_("scale factor of %d without an index register"),
6480 1 << i
.log2_scale_factor
);
6481 i
.log2_scale_factor
= 0;
6483 scale
= input_line_pointer
;
6484 input_line_pointer
= save
;
6489 i386_displacement (char *disp_start
, char *disp_end
)
6493 char *save_input_line_pointer
;
6494 char *gotfree_input_line
;
6496 i386_operand_type bigdisp
, types
= anydisp
;
6499 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6501 as_bad (_("at most %d displacement operands are allowed"),
6502 MAX_MEMORY_OPERANDS
);
6506 operand_type_set (&bigdisp
, 0);
6507 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6508 || (!current_templates
->start
->opcode_modifier
.jump
6509 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6511 bigdisp
.bitfield
.disp32
= 1;
6512 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6513 if (flag_code
== CODE_64BIT
)
6517 bigdisp
.bitfield
.disp32s
= 1;
6518 bigdisp
.bitfield
.disp64
= 1;
6521 else if ((flag_code
== CODE_16BIT
) ^ override
)
6523 bigdisp
.bitfield
.disp32
= 0;
6524 bigdisp
.bitfield
.disp16
= 1;
6529 /* For PC-relative branches, the width of the displacement
6530 is dependent upon data size, not address size. */
6531 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6532 if (flag_code
== CODE_64BIT
)
6534 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6535 bigdisp
.bitfield
.disp16
= 1;
6538 bigdisp
.bitfield
.disp32
= 1;
6539 bigdisp
.bitfield
.disp32s
= 1;
6545 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6547 : LONG_MNEM_SUFFIX
));
6548 bigdisp
.bitfield
.disp32
= 1;
6549 if ((flag_code
== CODE_16BIT
) ^ override
)
6551 bigdisp
.bitfield
.disp32
= 0;
6552 bigdisp
.bitfield
.disp16
= 1;
6556 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6559 exp
= &disp_expressions
[i
.disp_operands
];
6560 i
.op
[this_operand
].disps
= exp
;
6562 save_input_line_pointer
= input_line_pointer
;
6563 input_line_pointer
= disp_start
;
6564 END_STRING_AND_SAVE (disp_end
);
6566 #ifndef GCC_ASM_O_HACK
6567 #define GCC_ASM_O_HACK 0
6570 END_STRING_AND_SAVE (disp_end
+ 1);
6571 if (i
.types
[this_operand
].bitfield
.baseIndex
6572 && displacement_string_end
[-1] == '+')
6574 /* This hack is to avoid a warning when using the "o"
6575 constraint within gcc asm statements.
6578 #define _set_tssldt_desc(n,addr,limit,type) \
6579 __asm__ __volatile__ ( \
6581 "movw %w1,2+%0\n\t" \
6583 "movb %b1,4+%0\n\t" \
6584 "movb %4,5+%0\n\t" \
6585 "movb $0,6+%0\n\t" \
6586 "movb %h1,7+%0\n\t" \
6588 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6590 This works great except that the output assembler ends
6591 up looking a bit weird if it turns out that there is
6592 no offset. You end up producing code that looks like:
6605 So here we provide the missing zero. */
6607 *displacement_string_end
= '0';
6610 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6611 if (gotfree_input_line
)
6612 input_line_pointer
= gotfree_input_line
;
6614 exp_seg
= expression (exp
);
6617 if (*input_line_pointer
)
6618 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6620 RESTORE_END_STRING (disp_end
+ 1);
6622 input_line_pointer
= save_input_line_pointer
;
6623 if (gotfree_input_line
)
6625 free (gotfree_input_line
);
6627 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6628 exp
->X_op
= O_illegal
;
6631 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6633 RESTORE_END_STRING (disp_end
);
6639 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6640 i386_operand_type types
, const char *disp_start
)
6642 i386_operand_type bigdisp
;
6645 /* We do this to make sure that the section symbol is in
6646 the symbol table. We will ultimately change the relocation
6647 to be relative to the beginning of the section. */
6648 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6649 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6650 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6652 if (exp
->X_op
!= O_symbol
)
6655 if (S_IS_LOCAL (exp
->X_add_symbol
)
6656 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6657 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6658 exp
->X_op
= O_subtract
;
6659 exp
->X_op_symbol
= GOT_symbol
;
6660 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6661 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6662 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6663 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6665 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6668 else if (exp
->X_op
== O_absent
6669 || exp
->X_op
== O_illegal
6670 || exp
->X_op
== O_big
)
6673 as_bad (_("missing or invalid displacement expression `%s'"),
6678 else if (flag_code
== CODE_64BIT
6679 && !i
.prefix
[ADDR_PREFIX
]
6680 && exp
->X_op
== O_constant
)
6682 /* Since displacement is signed extended to 64bit, don't allow
6683 disp32 and turn off disp32s if they are out of range. */
6684 i
.types
[this_operand
].bitfield
.disp32
= 0;
6685 if (!fits_in_signed_long (exp
->X_add_number
))
6687 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6688 if (i
.types
[this_operand
].bitfield
.baseindex
)
6690 as_bad (_("0x%lx out range of signed 32bit displacement"),
6691 (long) exp
->X_add_number
);
6697 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6698 else if (exp
->X_op
!= O_constant
6699 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6700 && exp_seg
!= absolute_section
6701 && exp_seg
!= text_section
6702 && exp_seg
!= data_section
6703 && exp_seg
!= bss_section
6704 && exp_seg
!= undefined_section
6705 && !bfd_is_com_section (exp_seg
))
6707 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6712 /* Check if this is a displacement only operand. */
6713 bigdisp
= i
.types
[this_operand
];
6714 bigdisp
.bitfield
.disp8
= 0;
6715 bigdisp
.bitfield
.disp16
= 0;
6716 bigdisp
.bitfield
.disp32
= 0;
6717 bigdisp
.bitfield
.disp32s
= 0;
6718 bigdisp
.bitfield
.disp64
= 0;
6719 if (operand_type_all_zero (&bigdisp
))
6720 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6726 /* Make sure the memory operand we've been dealt is valid.
6727 Return 1 on success, 0 on a failure. */
6730 i386_index_check (const char *operand_string
)
6733 const char *kind
= "base/index";
6734 #if INFER_ADDR_PREFIX
6740 if (current_templates
->start
->opcode_modifier
.isstring
6741 && !current_templates
->start
->opcode_modifier
.immext
6742 && (current_templates
->end
[-1].opcode_modifier
.isstring
6745 /* Memory operands of string insns are special in that they only allow
6746 a single register (rDI, rSI, or rBX) as their memory address. */
6747 unsigned int expected
;
6749 kind
= "string address";
6751 if (current_templates
->start
->opcode_modifier
.w
)
6753 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6755 if (!type
.bitfield
.baseindex
6756 || ((!i
.mem_operands
!= !intel_syntax
)
6757 && current_templates
->end
[-1].operand_types
[1]
6758 .bitfield
.baseindex
))
6759 type
= current_templates
->end
[-1].operand_types
[1];
6760 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6763 expected
= 3 /* rBX */;
6765 if (!i
.base_reg
|| i
.index_reg
6766 || operand_type_check (i
.types
[this_operand
], disp
))
6768 else if (!(flag_code
== CODE_64BIT
6769 ? i
.prefix
[ADDR_PREFIX
]
6770 ? i
.base_reg
->reg_type
.bitfield
.reg32
6771 : i
.base_reg
->reg_type
.bitfield
.reg64
6772 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6773 ? i
.base_reg
->reg_type
.bitfield
.reg32
6774 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6776 else if (i
.base_reg
->reg_num
!= expected
)
6783 for (j
= 0; j
< i386_regtab_size
; ++j
)
6784 if ((flag_code
== CODE_64BIT
6785 ? i
.prefix
[ADDR_PREFIX
]
6786 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6787 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6788 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6789 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6790 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6791 && i386_regtab
[j
].reg_num
== expected
)
6793 gas_assert (j
< i386_regtab_size
);
6794 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6796 intel_syntax
? '[' : '(',
6798 i386_regtab
[j
].reg_name
,
6799 intel_syntax
? ']' : ')');
6803 else if (flag_code
== CODE_64BIT
)
6806 && ((i
.prefix
[ADDR_PREFIX
] == 0
6807 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6808 || (i
.prefix
[ADDR_PREFIX
]
6809 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6811 || i
.base_reg
->reg_num
!=
6812 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6814 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6815 || (i
.prefix
[ADDR_PREFIX
] == 0
6816 && i
.index_reg
->reg_num
!= RegRiz
6817 && !i
.index_reg
->reg_type
.bitfield
.reg64
6819 || (i
.prefix
[ADDR_PREFIX
]
6820 && i
.index_reg
->reg_num
!= RegEiz
6821 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6826 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6830 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6831 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6833 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6834 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6836 && i
.base_reg
->reg_num
< 6
6837 && i
.index_reg
->reg_num
>= 6
6838 && i
.log2_scale_factor
== 0))))
6845 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6847 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6848 && i
.index_reg
->reg_num
!= RegEiz
)
6849 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6855 #if INFER_ADDR_PREFIX
6856 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6858 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6860 /* Change the size of any displacement too. At most one of
6861 Disp16 or Disp32 is set.
6862 FIXME. There doesn't seem to be any real need for separate
6863 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6864 Removing them would probably clean up the code quite a lot. */
6865 if (flag_code
!= CODE_64BIT
6866 && (i
.types
[this_operand
].bitfield
.disp16
6867 || i
.types
[this_operand
].bitfield
.disp32
))
6868 i
.types
[this_operand
]
6869 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6874 as_bad (_("`%s' is not a valid %s expression"),
6879 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6881 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6882 ? flag_code
== CODE_32BIT
6891 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6895 i386_att_operand (char *operand_string
)
6899 char *op_string
= operand_string
;
6901 if (is_space_char (*op_string
))
6904 /* We check for an absolute prefix (differentiating,
6905 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6906 if (*op_string
== ABSOLUTE_PREFIX
)
6909 if (is_space_char (*op_string
))
6911 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6914 /* Check if operand is a register. */
6915 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6917 i386_operand_type temp
;
6919 /* Check for a segment override by searching for ':' after a
6920 segment register. */
6922 if (is_space_char (*op_string
))
6924 if (*op_string
== ':'
6925 && (r
->reg_type
.bitfield
.sreg2
6926 || r
->reg_type
.bitfield
.sreg3
))
6931 i
.seg
[i
.mem_operands
] = &es
;
6934 i
.seg
[i
.mem_operands
] = &cs
;
6937 i
.seg
[i
.mem_operands
] = &ss
;
6940 i
.seg
[i
.mem_operands
] = &ds
;
6943 i
.seg
[i
.mem_operands
] = &fs
;
6946 i
.seg
[i
.mem_operands
] = &gs
;
6950 /* Skip the ':' and whitespace. */
6952 if (is_space_char (*op_string
))
6955 if (!is_digit_char (*op_string
)
6956 && !is_identifier_char (*op_string
)
6957 && *op_string
!= '('
6958 && *op_string
!= ABSOLUTE_PREFIX
)
6960 as_bad (_("bad memory operand `%s'"), op_string
);
6963 /* Handle case of %es:*foo. */
6964 if (*op_string
== ABSOLUTE_PREFIX
)
6967 if (is_space_char (*op_string
))
6969 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6971 goto do_memory_reference
;
6975 as_bad (_("junk `%s' after register"), op_string
);
6979 temp
.bitfield
.baseindex
= 0;
6980 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6982 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6983 i
.op
[this_operand
].regs
= r
;
6986 else if (*op_string
== REGISTER_PREFIX
)
6988 as_bad (_("bad register name `%s'"), op_string
);
6991 else if (*op_string
== IMMEDIATE_PREFIX
)
6994 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6996 as_bad (_("immediate operand illegal with absolute jump"));
6999 if (!i386_immediate (op_string
))
7002 else if (is_digit_char (*op_string
)
7003 || is_identifier_char (*op_string
)
7004 || *op_string
== '(')
7006 /* This is a memory reference of some sort. */
7009 /* Start and end of displacement string expression (if found). */
7010 char *displacement_string_start
;
7011 char *displacement_string_end
;
7013 do_memory_reference
:
7014 if ((i
.mem_operands
== 1
7015 && !current_templates
->start
->opcode_modifier
.isstring
)
7016 || i
.mem_operands
== 2)
7018 as_bad (_("too many memory references for `%s'"),
7019 current_templates
->start
->name
);
7023 /* Check for base index form. We detect the base index form by
7024 looking for an ')' at the end of the operand, searching
7025 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7027 base_string
= op_string
+ strlen (op_string
);
7030 if (is_space_char (*base_string
))
7033 /* If we only have a displacement, set-up for it to be parsed later. */
7034 displacement_string_start
= op_string
;
7035 displacement_string_end
= base_string
+ 1;
7037 if (*base_string
== ')')
7040 unsigned int parens_balanced
= 1;
7041 /* We've already checked that the number of left & right ()'s are
7042 equal, so this loop will not be infinite. */
7046 if (*base_string
== ')')
7048 if (*base_string
== '(')
7051 while (parens_balanced
);
7053 temp_string
= base_string
;
7055 /* Skip past '(' and whitespace. */
7057 if (is_space_char (*base_string
))
7060 if (*base_string
== ','
7061 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7064 displacement_string_end
= temp_string
;
7066 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7070 base_string
= end_op
;
7071 if (is_space_char (*base_string
))
7075 /* There may be an index reg or scale factor here. */
7076 if (*base_string
== ',')
7079 if (is_space_char (*base_string
))
7082 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7085 base_string
= end_op
;
7086 if (is_space_char (*base_string
))
7088 if (*base_string
== ',')
7091 if (is_space_char (*base_string
))
7094 else if (*base_string
!= ')')
7096 as_bad (_("expecting `,' or `)' "
7097 "after index register in `%s'"),
7102 else if (*base_string
== REGISTER_PREFIX
)
7104 as_bad (_("bad register name `%s'"), base_string
);
7108 /* Check for scale factor. */
7109 if (*base_string
!= ')')
7111 char *end_scale
= i386_scale (base_string
);
7116 base_string
= end_scale
;
7117 if (is_space_char (*base_string
))
7119 if (*base_string
!= ')')
7121 as_bad (_("expecting `)' "
7122 "after scale factor in `%s'"),
7127 else if (!i
.index_reg
)
7129 as_bad (_("expecting index register or scale factor "
7130 "after `,'; got '%c'"),
7135 else if (*base_string
!= ')')
7137 as_bad (_("expecting `,' or `)' "
7138 "after base register in `%s'"),
7143 else if (*base_string
== REGISTER_PREFIX
)
7145 as_bad (_("bad register name `%s'"), base_string
);
7150 /* If there's an expression beginning the operand, parse it,
7151 assuming displacement_string_start and
7152 displacement_string_end are meaningful. */
7153 if (displacement_string_start
!= displacement_string_end
)
7155 if (!i386_displacement (displacement_string_start
,
7156 displacement_string_end
))
7160 /* Special case for (%dx) while doing input/output op. */
7162 && operand_type_equal (&i
.base_reg
->reg_type
,
7163 ®16_inoutportreg
)
7165 && i
.log2_scale_factor
== 0
7166 && i
.seg
[i
.mem_operands
] == 0
7167 && !operand_type_check (i
.types
[this_operand
], disp
))
7169 i
.types
[this_operand
] = inoutportreg
;
7173 if (i386_index_check (operand_string
) == 0)
7175 i
.types
[this_operand
].bitfield
.mem
= 1;
7180 /* It's not a memory operand; argh! */
7181 as_bad (_("invalid char %s beginning operand %d `%s'"),
7182 output_invalid (*op_string
),
7187 return 1; /* Normal return. */
7190 /* md_estimate_size_before_relax()
7192 Called just before relax() for rs_machine_dependent frags. The x86
7193 assembler uses these frags to handle variable size jump
7196 Any symbol that is now undefined will not become defined.
7197 Return the correct fr_subtype in the frag.
7198 Return the initial "guess for variable size of frag" to caller.
7199 The guess is actually the growth beyond the fixed part. Whatever
7200 we do to grow the fixed or variable part contributes to our
7204 md_estimate_size_before_relax (fragP
, segment
)
7208 /* We've already got fragP->fr_subtype right; all we have to do is
7209 check for un-relaxable symbols. On an ELF system, we can't relax
7210 an externally visible symbol, because it may be overridden by a
7212 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7215 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7216 || S_IS_WEAK (fragP
->fr_symbol
)
7217 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7218 & BSF_GNU_INDIRECT_FUNCTION
))))
7220 #if defined (OBJ_COFF) && defined (TE_PE)
7221 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7222 && S_IS_WEAK (fragP
->fr_symbol
))
7226 /* Symbol is undefined in this segment, or we need to keep a
7227 reloc so that weak symbols can be overridden. */
7228 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7229 enum bfd_reloc_code_real reloc_type
;
7230 unsigned char *opcode
;
7233 if (fragP
->fr_var
!= NO_RELOC
)
7234 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7236 reloc_type
= BFD_RELOC_16_PCREL
;
7238 reloc_type
= BFD_RELOC_32_PCREL
;
7240 old_fr_fix
= fragP
->fr_fix
;
7241 opcode
= (unsigned char *) fragP
->fr_opcode
;
7243 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7246 /* Make jmp (0xeb) a (d)word displacement jump. */
7248 fragP
->fr_fix
+= size
;
7249 fix_new (fragP
, old_fr_fix
, size
,
7251 fragP
->fr_offset
, 1,
7257 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7259 /* Negate the condition, and branch past an
7260 unconditional jump. */
7263 /* Insert an unconditional jump. */
7265 /* We added two extra opcode bytes, and have a two byte
7267 fragP
->fr_fix
+= 2 + 2;
7268 fix_new (fragP
, old_fr_fix
+ 2, 2,
7270 fragP
->fr_offset
, 1,
7277 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7282 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7284 fragP
->fr_offset
, 1,
7286 fixP
->fx_signed
= 1;
7290 /* This changes the byte-displacement jump 0x7N
7291 to the (d)word-displacement jump 0x0f,0x8N. */
7292 opcode
[1] = opcode
[0] + 0x10;
7293 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7294 /* We've added an opcode byte. */
7295 fragP
->fr_fix
+= 1 + size
;
7296 fix_new (fragP
, old_fr_fix
+ 1, size
,
7298 fragP
->fr_offset
, 1,
7303 BAD_CASE (fragP
->fr_subtype
);
7307 return fragP
->fr_fix
- old_fr_fix
;
7310 /* Guess size depending on current relax state. Initially the relax
7311 state will correspond to a short jump and we return 1, because
7312 the variable part of the frag (the branch offset) is one byte
7313 long. However, we can relax a section more than once and in that
7314 case we must either set fr_subtype back to the unrelaxed state,
7315 or return the value for the appropriate branch. */
7316 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7319 /* Called after relax() is finished.
7321 In: Address of frag.
7322 fr_type == rs_machine_dependent.
7323 fr_subtype is what the address relaxed to.
7325 Out: Any fixSs and constants are set up.
7326 Caller will turn frag into a ".space 0". */
7329 md_convert_frag (abfd
, sec
, fragP
)
7330 bfd
*abfd ATTRIBUTE_UNUSED
;
7331 segT sec ATTRIBUTE_UNUSED
;
7334 unsigned char *opcode
;
7335 unsigned char *where_to_put_displacement
= NULL
;
7336 offsetT target_address
;
7337 offsetT opcode_address
;
7338 unsigned int extension
= 0;
7339 offsetT displacement_from_opcode_start
;
7341 opcode
= (unsigned char *) fragP
->fr_opcode
;
7343 /* Address we want to reach in file space. */
7344 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7346 /* Address opcode resides at in file space. */
7347 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7349 /* Displacement from opcode start to fill into instruction. */
7350 displacement_from_opcode_start
= target_address
- opcode_address
;
7352 if ((fragP
->fr_subtype
& BIG
) == 0)
7354 /* Don't have to change opcode. */
7355 extension
= 1; /* 1 opcode + 1 displacement */
7356 where_to_put_displacement
= &opcode
[1];
7360 if (no_cond_jump_promotion
7361 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7362 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7363 _("long jump required"));
7365 switch (fragP
->fr_subtype
)
7367 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7368 extension
= 4; /* 1 opcode + 4 displacement */
7370 where_to_put_displacement
= &opcode
[1];
7373 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7374 extension
= 2; /* 1 opcode + 2 displacement */
7376 where_to_put_displacement
= &opcode
[1];
7379 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7380 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7381 extension
= 5; /* 2 opcode + 4 displacement */
7382 opcode
[1] = opcode
[0] + 0x10;
7383 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7384 where_to_put_displacement
= &opcode
[2];
7387 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7388 extension
= 3; /* 2 opcode + 2 displacement */
7389 opcode
[1] = opcode
[0] + 0x10;
7390 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7391 where_to_put_displacement
= &opcode
[2];
7394 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7399 where_to_put_displacement
= &opcode
[3];
7403 BAD_CASE (fragP
->fr_subtype
);
7408 /* If size if less then four we are sure that the operand fits,
7409 but if it's 4, then it could be that the displacement is larger
7411 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7413 && ((addressT
) (displacement_from_opcode_start
- extension
7414 + ((addressT
) 1 << 31))
7415 > (((addressT
) 2 << 31) - 1)))
7417 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7418 _("jump target out of range"));
7419 /* Make us emit 0. */
7420 displacement_from_opcode_start
= extension
;
7422 /* Now put displacement after opcode. */
7423 md_number_to_chars ((char *) where_to_put_displacement
,
7424 (valueT
) (displacement_from_opcode_start
- extension
),
7425 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7426 fragP
->fr_fix
+= extension
;
7429 /* Apply a fixup (fixS) to segment data, once it has been determined
7430 by our caller that we have all the info we need to fix it up.
7432 On the 386, immediates, displacements, and data pointers are all in
7433 the same (little-endian) format, so we don't need to care about which
7437 md_apply_fix (fixP
, valP
, seg
)
7438 /* The fix we're to put in. */
7440 /* Pointer to the value of the bits. */
7442 /* Segment fix is from. */
7443 segT seg ATTRIBUTE_UNUSED
;
7445 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7446 valueT value
= *valP
;
7448 #if !defined (TE_Mach)
7451 switch (fixP
->fx_r_type
)
7457 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7460 case BFD_RELOC_X86_64_32S
:
7461 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7464 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7467 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7472 if (fixP
->fx_addsy
!= NULL
7473 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7474 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7475 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7476 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7477 && !use_rela_relocations
)
7479 /* This is a hack. There should be a better way to handle this.
7480 This covers for the fact that bfd_install_relocation will
7481 subtract the current location (for partial_inplace, PC relative
7482 relocations); see more below. */
7486 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7489 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7491 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7494 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7497 || (symbol_section_p (fixP
->fx_addsy
)
7498 && sym_seg
!= absolute_section
))
7499 && !generic_force_reloc (fixP
))
7501 /* Yes, we add the values in twice. This is because
7502 bfd_install_relocation subtracts them out again. I think
7503 bfd_install_relocation is broken, but I don't dare change
7505 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7509 #if defined (OBJ_COFF) && defined (TE_PE)
7510 /* For some reason, the PE format does not store a
7511 section address offset for a PC relative symbol. */
7512 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7513 || S_IS_WEAK (fixP
->fx_addsy
))
7514 value
+= md_pcrel_from (fixP
);
7517 #if defined (OBJ_COFF) && defined (TE_PE)
7518 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7520 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7524 /* Fix a few things - the dynamic linker expects certain values here,
7525 and we must not disappoint it. */
7526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7527 if (IS_ELF
&& fixP
->fx_addsy
)
7528 switch (fixP
->fx_r_type
)
7530 case BFD_RELOC_386_PLT32
:
7531 case BFD_RELOC_X86_64_PLT32
:
7532 /* Make the jump instruction point to the address of the operand. At
7533 runtime we merely add the offset to the actual PLT entry. */
7537 case BFD_RELOC_386_TLS_GD
:
7538 case BFD_RELOC_386_TLS_LDM
:
7539 case BFD_RELOC_386_TLS_IE_32
:
7540 case BFD_RELOC_386_TLS_IE
:
7541 case BFD_RELOC_386_TLS_GOTIE
:
7542 case BFD_RELOC_386_TLS_GOTDESC
:
7543 case BFD_RELOC_X86_64_TLSGD
:
7544 case BFD_RELOC_X86_64_TLSLD
:
7545 case BFD_RELOC_X86_64_GOTTPOFF
:
7546 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7547 value
= 0; /* Fully resolved at runtime. No addend. */
7549 case BFD_RELOC_386_TLS_LE
:
7550 case BFD_RELOC_386_TLS_LDO_32
:
7551 case BFD_RELOC_386_TLS_LE_32
:
7552 case BFD_RELOC_X86_64_DTPOFF32
:
7553 case BFD_RELOC_X86_64_DTPOFF64
:
7554 case BFD_RELOC_X86_64_TPOFF32
:
7555 case BFD_RELOC_X86_64_TPOFF64
:
7556 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7559 case BFD_RELOC_386_TLS_DESC_CALL
:
7560 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7561 value
= 0; /* Fully resolved at runtime. No addend. */
7562 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7566 case BFD_RELOC_386_GOT32
:
7567 case BFD_RELOC_X86_64_GOT32
:
7568 value
= 0; /* Fully resolved at runtime. No addend. */
7571 case BFD_RELOC_VTABLE_INHERIT
:
7572 case BFD_RELOC_VTABLE_ENTRY
:
7579 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7581 #endif /* !defined (TE_Mach) */
7583 /* Are we finished with this relocation now? */
7584 if (fixP
->fx_addsy
== NULL
)
7586 #if defined (OBJ_COFF) && defined (TE_PE)
7587 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7590 /* Remember value for tc_gen_reloc. */
7591 fixP
->fx_addnumber
= value
;
7592 /* Clear out the frag for now. */
7596 else if (use_rela_relocations
)
7598 fixP
->fx_no_overflow
= 1;
7599 /* Remember value for tc_gen_reloc. */
7600 fixP
->fx_addnumber
= value
;
7604 md_number_to_chars (p
, value
, fixP
->fx_size
);
7608 md_atof (int type
, char *litP
, int *sizeP
)
7610 /* This outputs the LITTLENUMs in REVERSE order;
7611 in accord with the bigendian 386. */
7612 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7615 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7618 output_invalid (int c
)
7621 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7624 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7625 "(0x%x)", (unsigned char) c
);
7626 return output_invalid_buf
;
7629 /* REG_STRING starts *before* REGISTER_PREFIX. */
7631 static const reg_entry
*
7632 parse_real_register (char *reg_string
, char **end_op
)
7634 char *s
= reg_string
;
7636 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7639 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7640 if (*s
== REGISTER_PREFIX
)
7643 if (is_space_char (*s
))
7647 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7649 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7650 return (const reg_entry
*) NULL
;
7654 /* For naked regs, make sure that we are not dealing with an identifier.
7655 This prevents confusing an identifier like `eax_var' with register
7657 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7658 return (const reg_entry
*) NULL
;
7662 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7664 /* Handle floating point regs, allowing spaces in the (i) part. */
7665 if (r
== i386_regtab
/* %st is first entry of table */)
7667 if (is_space_char (*s
))
7672 if (is_space_char (*s
))
7674 if (*s
>= '0' && *s
<= '7')
7678 if (is_space_char (*s
))
7683 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7688 /* We have "%st(" then garbage. */
7689 return (const reg_entry
*) NULL
;
7693 if (r
== NULL
|| allow_pseudo_reg
)
7696 if (operand_type_all_zero (&r
->reg_type
))
7697 return (const reg_entry
*) NULL
;
7699 if ((r
->reg_type
.bitfield
.reg32
7700 || r
->reg_type
.bitfield
.sreg3
7701 || r
->reg_type
.bitfield
.control
7702 || r
->reg_type
.bitfield
.debug
7703 || r
->reg_type
.bitfield
.test
)
7704 && !cpu_arch_flags
.bitfield
.cpui386
)
7705 return (const reg_entry
*) NULL
;
7707 if (r
->reg_type
.bitfield
.floatreg
7708 && !cpu_arch_flags
.bitfield
.cpu8087
7709 && !cpu_arch_flags
.bitfield
.cpu287
7710 && !cpu_arch_flags
.bitfield
.cpu387
)
7711 return (const reg_entry
*) NULL
;
7713 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7714 return (const reg_entry
*) NULL
;
7716 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7717 return (const reg_entry
*) NULL
;
7719 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7720 return (const reg_entry
*) NULL
;
7722 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7723 if (!allow_index_reg
7724 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7725 return (const reg_entry
*) NULL
;
7727 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7728 || r
->reg_type
.bitfield
.reg64
)
7729 && (!cpu_arch_flags
.bitfield
.cpulm
7730 || !operand_type_equal (&r
->reg_type
, &control
))
7731 && flag_code
!= CODE_64BIT
)
7732 return (const reg_entry
*) NULL
;
7734 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7735 return (const reg_entry
*) NULL
;
7740 /* REG_STRING starts *before* REGISTER_PREFIX. */
7742 static const reg_entry
*
7743 parse_register (char *reg_string
, char **end_op
)
7747 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7748 r
= parse_real_register (reg_string
, end_op
);
7753 char *save
= input_line_pointer
;
7757 input_line_pointer
= reg_string
;
7758 c
= get_symbol_end ();
7759 symbolP
= symbol_find (reg_string
);
7760 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7762 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7764 know (e
->X_op
== O_register
);
7765 know (e
->X_add_number
>= 0
7766 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7767 r
= i386_regtab
+ e
->X_add_number
;
7768 *end_op
= input_line_pointer
;
7770 *input_line_pointer
= c
;
7771 input_line_pointer
= save
;
7777 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7780 char *end
= input_line_pointer
;
7783 r
= parse_register (name
, &input_line_pointer
);
7784 if (r
&& end
<= input_line_pointer
)
7786 *nextcharP
= *input_line_pointer
;
7787 *input_line_pointer
= 0;
7788 e
->X_op
= O_register
;
7789 e
->X_add_number
= r
- i386_regtab
;
7792 input_line_pointer
= end
;
7794 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7798 md_operand (expressionS
*e
)
7803 switch (*input_line_pointer
)
7805 case REGISTER_PREFIX
:
7806 r
= parse_real_register (input_line_pointer
, &end
);
7809 e
->X_op
= O_register
;
7810 e
->X_add_number
= r
- i386_regtab
;
7811 input_line_pointer
= end
;
7816 gas_assert (intel_syntax
);
7817 end
= input_line_pointer
++;
7819 if (*input_line_pointer
== ']')
7821 ++input_line_pointer
;
7822 e
->X_op_symbol
= make_expr_symbol (e
);
7823 e
->X_add_symbol
= NULL
;
7824 e
->X_add_number
= 0;
7830 input_line_pointer
= end
;
7837 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7838 const char *md_shortopts
= "kVQ:sqn";
7840 const char *md_shortopts
= "qn";
7843 #define OPTION_32 (OPTION_MD_BASE + 0)
7844 #define OPTION_64 (OPTION_MD_BASE + 1)
7845 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7846 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7847 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7848 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7849 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7850 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7851 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7852 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7853 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7854 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7856 struct option md_longopts
[] =
7858 {"32", no_argument
, NULL
, OPTION_32
},
7859 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7860 || defined (TE_PE) || defined (TE_PEP))
7861 {"64", no_argument
, NULL
, OPTION_64
},
7863 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7864 {"march", required_argument
, NULL
, OPTION_MARCH
},
7865 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7866 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7867 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7868 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7869 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7870 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7871 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7872 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7873 {NULL
, no_argument
, NULL
, 0}
7875 size_t md_longopts_size
= sizeof (md_longopts
);
7878 md_parse_option (int c
, char *arg
)
7886 optimize_align_code
= 0;
7893 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7894 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7895 should be emitted or not. FIXME: Not implemented. */
7899 /* -V: SVR4 argument to print version ID. */
7901 print_version_id ();
7904 /* -k: Ignore for FreeBSD compatibility. */
7909 /* -s: On i386 Solaris, this tells the native assembler to use
7910 .stab instead of .stab.excl. We always use .stab anyhow. */
7913 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7914 || defined (TE_PE) || defined (TE_PEP))
7917 const char **list
, **l
;
7919 list
= bfd_target_list ();
7920 for (l
= list
; *l
!= NULL
; l
++)
7921 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7922 || strcmp (*l
, "coff-x86-64") == 0
7923 || strcmp (*l
, "pe-x86-64") == 0
7924 || strcmp (*l
, "pei-x86-64") == 0)
7926 default_arch
= "x86_64";
7930 as_fatal (_("No compiled in support for x86_64"));
7937 default_arch
= "i386";
7941 #ifdef SVR4_COMMENT_CHARS
7946 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7948 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7952 i386_comment_chars
= n
;
7958 arch
= xstrdup (arg
);
7962 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7963 next
= strchr (arch
, '+');
7966 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7968 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7971 cpu_arch_name
= cpu_arch
[i
].name
;
7972 cpu_sub_arch_name
= NULL
;
7973 cpu_arch_flags
= cpu_arch
[i
].flags
;
7974 cpu_arch_isa
= cpu_arch
[i
].type
;
7975 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7976 if (!cpu_arch_tune_set
)
7978 cpu_arch_tune
= cpu_arch_isa
;
7979 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7983 else if (*cpu_arch
[i
].name
== '.'
7984 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7986 /* ISA entension. */
7987 i386_cpu_flags flags
;
7989 if (strncmp (arch
, "no", 2))
7990 flags
= cpu_flags_or (cpu_arch_flags
,
7993 flags
= cpu_flags_and_not (cpu_arch_flags
,
7995 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7997 if (cpu_sub_arch_name
)
7999 char *name
= cpu_sub_arch_name
;
8000 cpu_sub_arch_name
= concat (name
,
8002 (const char *) NULL
);
8006 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8007 cpu_arch_flags
= flags
;
8013 if (i
>= ARRAY_SIZE (cpu_arch
))
8014 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8018 while (next
!= NULL
);
8023 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8024 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8026 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8028 cpu_arch_tune_set
= 1;
8029 cpu_arch_tune
= cpu_arch
[i
].type
;
8030 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8034 if (i
>= ARRAY_SIZE (cpu_arch
))
8035 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8038 case OPTION_MMNEMONIC
:
8039 if (strcasecmp (arg
, "att") == 0)
8041 else if (strcasecmp (arg
, "intel") == 0)
8044 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8047 case OPTION_MSYNTAX
:
8048 if (strcasecmp (arg
, "att") == 0)
8050 else if (strcasecmp (arg
, "intel") == 0)
8053 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8056 case OPTION_MINDEX_REG
:
8057 allow_index_reg
= 1;
8060 case OPTION_MNAKED_REG
:
8061 allow_naked_reg
= 1;
8064 case OPTION_MOLD_GCC
:
8068 case OPTION_MSSE2AVX
:
8072 case OPTION_MSSE_CHECK
:
8073 if (strcasecmp (arg
, "error") == 0)
8074 sse_check
= sse_check_error
;
8075 else if (strcasecmp (arg
, "warning") == 0)
8076 sse_check
= sse_check_warning
;
8077 else if (strcasecmp (arg
, "none") == 0)
8078 sse_check
= sse_check_none
;
8080 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8090 md_show_usage (stream
)
8093 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8094 fprintf (stream
, _("\
8096 -V print assembler version number\n\
8099 fprintf (stream
, _("\
8100 -n Do not optimize code alignment\n\
8101 -q quieten some warnings\n"));
8102 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8103 fprintf (stream
, _("\
8106 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8107 || defined (TE_PE) || defined (TE_PEP))
8108 fprintf (stream
, _("\
8109 --32/--64 generate 32bit/64bit code\n"));
8111 #ifdef SVR4_COMMENT_CHARS
8112 fprintf (stream
, _("\
8113 --divide do not treat `/' as a comment character\n"));
8115 fprintf (stream
, _("\
8116 --divide ignored\n"));
8118 fprintf (stream
, _("\
8119 -march=CPU[,+EXTENSION...]\n\
8120 generate code for CPU and EXTENSION, CPU is one of:\n\
8121 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8122 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8123 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8124 amdfam10, generic32, generic64\n\
8125 EXTENSION is combination of:\n\
8126 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8127 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8128 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8129 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8130 svme, abm, padlock, fma4, xop, cvt16, lwp\n"));
8131 fprintf (stream
, _("\
8132 -mtune=CPU optimize for CPU, CPU is one of:\n\
8133 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8134 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8135 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8136 amdfam10, generic32, generic64\n"));
8137 fprintf (stream
, _("\
8138 -msse2avx encode SSE instructions with VEX prefix\n"));
8139 fprintf (stream
, _("\
8140 -msse-check=[none|error|warning]\n\
8141 check SSE instructions\n"));
8142 fprintf (stream
, _("\
8143 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8144 fprintf (stream
, _("\
8145 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8146 fprintf (stream
, _("\
8147 -mindex-reg support pseudo index registers\n"));
8148 fprintf (stream
, _("\
8149 -mnaked-reg don't require `%%' prefix for registers\n"));
8150 fprintf (stream
, _("\
8151 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8154 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8155 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8156 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8158 /* Pick the target format to use. */
8161 i386_target_format (void)
8163 if (!strcmp (default_arch
, "x86_64"))
8165 set_code_flag (CODE_64BIT
);
8166 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8168 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8169 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8170 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8171 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8172 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8173 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8174 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8175 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8176 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8177 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8178 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8180 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8182 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8183 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8184 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8185 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8186 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8187 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8188 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8189 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8190 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8191 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8194 else if (!strcmp (default_arch
, "i386"))
8196 set_code_flag (CODE_32BIT
);
8197 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8199 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8200 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8201 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8203 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8205 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8206 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8207 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8211 as_fatal (_("Unknown architecture"));
8212 switch (OUTPUT_FLAVOR
)
8214 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8215 case bfd_target_aout_flavour
:
8216 return AOUT_TARGET_FORMAT
;
8218 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8219 # if defined (TE_PE) || defined (TE_PEP)
8220 case bfd_target_coff_flavour
:
8221 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8222 # elif defined (TE_GO32)
8223 case bfd_target_coff_flavour
:
8226 case bfd_target_coff_flavour
:
8230 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8231 case bfd_target_elf_flavour
:
8233 if (flag_code
== CODE_64BIT
)
8236 use_rela_relocations
= 1;
8238 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8240 if (flag_code
!= CODE_64BIT
)
8241 as_fatal (_("Intel L1OM is 64bit only"));
8242 return ELF_TARGET_L1OM_FORMAT
;
8245 return (flag_code
== CODE_64BIT
8246 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8249 #if defined (OBJ_MACH_O)
8250 case bfd_target_mach_o_flavour
:
8251 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8259 #endif /* OBJ_MAYBE_ more than one */
8261 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8263 i386_elf_emit_arch_note (void)
8265 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8268 asection
*seg
= now_seg
;
8269 subsegT subseg
= now_subseg
;
8270 Elf_Internal_Note i_note
;
8271 Elf_External_Note e_note
;
8272 asection
*note_secp
;
8275 /* Create the .note section. */
8276 note_secp
= subseg_new (".note", 0);
8277 bfd_set_section_flags (stdoutput
,
8279 SEC_HAS_CONTENTS
| SEC_READONLY
);
8281 /* Process the arch string. */
8282 len
= strlen (cpu_arch_name
);
8284 i_note
.namesz
= len
+ 1;
8286 i_note
.type
= NT_ARCH
;
8287 p
= frag_more (sizeof (e_note
.namesz
));
8288 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8289 p
= frag_more (sizeof (e_note
.descsz
));
8290 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8291 p
= frag_more (sizeof (e_note
.type
));
8292 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8293 p
= frag_more (len
+ 1);
8294 strcpy (p
, cpu_arch_name
);
8296 frag_align (2, 0, 0);
8298 subseg_set (seg
, subseg
);
8304 md_undefined_symbol (name
)
8307 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8308 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8309 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8310 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8314 if (symbol_find (name
))
8315 as_bad (_("GOT already in symbol table"));
8316 GOT_symbol
= symbol_new (name
, undefined_section
,
8317 (valueT
) 0, &zero_address_frag
);
8324 /* Round up a section size to the appropriate boundary. */
8327 md_section_align (segment
, size
)
8328 segT segment ATTRIBUTE_UNUSED
;
8331 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8332 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8334 /* For a.out, force the section size to be aligned. If we don't do
8335 this, BFD will align it for us, but it will not write out the
8336 final bytes of the section. This may be a bug in BFD, but it is
8337 easier to fix it here since that is how the other a.out targets
8341 align
= bfd_get_section_alignment (stdoutput
, segment
);
8342 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8349 /* On the i386, PC-relative offsets are relative to the start of the
8350 next instruction. That is, the address of the offset, plus its
8351 size, since the offset is always the last part of the insn. */
8354 md_pcrel_from (fixS
*fixP
)
8356 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8362 s_bss (int ignore ATTRIBUTE_UNUSED
)
8366 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8368 obj_elf_section_change_hook ();
8370 temp
= get_absolute_expression ();
8371 subseg_set (bss_section
, (subsegT
) temp
);
8372 demand_empty_rest_of_line ();
8378 i386_validate_fix (fixS
*fixp
)
8380 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8382 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8386 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8391 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8393 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8400 tc_gen_reloc (section
, fixp
)
8401 asection
*section ATTRIBUTE_UNUSED
;
8405 bfd_reloc_code_real_type code
;
8407 switch (fixp
->fx_r_type
)
8409 case BFD_RELOC_X86_64_PLT32
:
8410 case BFD_RELOC_X86_64_GOT32
:
8411 case BFD_RELOC_X86_64_GOTPCREL
:
8412 case BFD_RELOC_386_PLT32
:
8413 case BFD_RELOC_386_GOT32
:
8414 case BFD_RELOC_386_GOTOFF
:
8415 case BFD_RELOC_386_GOTPC
:
8416 case BFD_RELOC_386_TLS_GD
:
8417 case BFD_RELOC_386_TLS_LDM
:
8418 case BFD_RELOC_386_TLS_LDO_32
:
8419 case BFD_RELOC_386_TLS_IE_32
:
8420 case BFD_RELOC_386_TLS_IE
:
8421 case BFD_RELOC_386_TLS_GOTIE
:
8422 case BFD_RELOC_386_TLS_LE_32
:
8423 case BFD_RELOC_386_TLS_LE
:
8424 case BFD_RELOC_386_TLS_GOTDESC
:
8425 case BFD_RELOC_386_TLS_DESC_CALL
:
8426 case BFD_RELOC_X86_64_TLSGD
:
8427 case BFD_RELOC_X86_64_TLSLD
:
8428 case BFD_RELOC_X86_64_DTPOFF32
:
8429 case BFD_RELOC_X86_64_DTPOFF64
:
8430 case BFD_RELOC_X86_64_GOTTPOFF
:
8431 case BFD_RELOC_X86_64_TPOFF32
:
8432 case BFD_RELOC_X86_64_TPOFF64
:
8433 case BFD_RELOC_X86_64_GOTOFF64
:
8434 case BFD_RELOC_X86_64_GOTPC32
:
8435 case BFD_RELOC_X86_64_GOT64
:
8436 case BFD_RELOC_X86_64_GOTPCREL64
:
8437 case BFD_RELOC_X86_64_GOTPC64
:
8438 case BFD_RELOC_X86_64_GOTPLT64
:
8439 case BFD_RELOC_X86_64_PLTOFF64
:
8440 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8441 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8443 case BFD_RELOC_VTABLE_ENTRY
:
8444 case BFD_RELOC_VTABLE_INHERIT
:
8446 case BFD_RELOC_32_SECREL
:
8448 code
= fixp
->fx_r_type
;
8450 case BFD_RELOC_X86_64_32S
:
8451 if (!fixp
->fx_pcrel
)
8453 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8454 code
= fixp
->fx_r_type
;
8460 switch (fixp
->fx_size
)
8463 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8464 _("can not do %d byte pc-relative relocation"),
8466 code
= BFD_RELOC_32_PCREL
;
8468 case 1: code
= BFD_RELOC_8_PCREL
; break;
8469 case 2: code
= BFD_RELOC_16_PCREL
; break;
8470 case 4: code
= BFD_RELOC_32_PCREL
; break;
8472 case 8: code
= BFD_RELOC_64_PCREL
; break;
8478 switch (fixp
->fx_size
)
8481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8482 _("can not do %d byte relocation"),
8484 code
= BFD_RELOC_32
;
8486 case 1: code
= BFD_RELOC_8
; break;
8487 case 2: code
= BFD_RELOC_16
; break;
8488 case 4: code
= BFD_RELOC_32
; break;
8490 case 8: code
= BFD_RELOC_64
; break;
8497 if ((code
== BFD_RELOC_32
8498 || code
== BFD_RELOC_32_PCREL
8499 || code
== BFD_RELOC_X86_64_32S
)
8501 && fixp
->fx_addsy
== GOT_symbol
)
8504 code
= BFD_RELOC_386_GOTPC
;
8506 code
= BFD_RELOC_X86_64_GOTPC32
;
8508 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8510 && fixp
->fx_addsy
== GOT_symbol
)
8512 code
= BFD_RELOC_X86_64_GOTPC64
;
8515 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8516 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8517 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8519 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8521 if (!use_rela_relocations
)
8523 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8524 vtable entry to be used in the relocation's section offset. */
8525 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8526 rel
->address
= fixp
->fx_offset
;
8527 #if defined (OBJ_COFF) && defined (TE_PE)
8528 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8529 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8534 /* Use the rela in 64bit mode. */
8537 if (!fixp
->fx_pcrel
)
8538 rel
->addend
= fixp
->fx_offset
;
8542 case BFD_RELOC_X86_64_PLT32
:
8543 case BFD_RELOC_X86_64_GOT32
:
8544 case BFD_RELOC_X86_64_GOTPCREL
:
8545 case BFD_RELOC_X86_64_TLSGD
:
8546 case BFD_RELOC_X86_64_TLSLD
:
8547 case BFD_RELOC_X86_64_GOTTPOFF
:
8548 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8549 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8550 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8553 rel
->addend
= (section
->vma
8555 + fixp
->fx_addnumber
8556 + md_pcrel_from (fixp
));
8561 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8562 if (rel
->howto
== NULL
)
8564 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8565 _("cannot represent relocation type %s"),
8566 bfd_get_reloc_code_name (code
));
8567 /* Set howto to a garbage value so that we can keep going. */
8568 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8569 gas_assert (rel
->howto
!= NULL
);
8575 #include "tc-i386-intel.c"
8578 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8580 int saved_naked_reg
;
8581 char saved_register_dot
;
8583 saved_naked_reg
= allow_naked_reg
;
8584 allow_naked_reg
= 1;
8585 saved_register_dot
= register_chars
['.'];
8586 register_chars
['.'] = '.';
8587 allow_pseudo_reg
= 1;
8588 expression_and_evaluate (exp
);
8589 allow_pseudo_reg
= 0;
8590 register_chars
['.'] = saved_register_dot
;
8591 allow_naked_reg
= saved_naked_reg
;
8593 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8595 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8597 exp
->X_op
= O_constant
;
8598 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8599 .dw2_regnum
[flag_code
>> 1];
8602 exp
->X_op
= O_illegal
;
8607 tc_x86_frame_initial_instructions (void)
8609 static unsigned int sp_regno
[2];
8611 if (!sp_regno
[flag_code
>> 1])
8613 char *saved_input
= input_line_pointer
;
8614 char sp
[][4] = {"esp", "rsp"};
8617 input_line_pointer
= sp
[flag_code
>> 1];
8618 tc_x86_parse_to_dw2regnum (&exp
);
8619 gas_assert (exp
.X_op
== O_constant
);
8620 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8621 input_line_pointer
= saved_input
;
8624 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8625 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8629 i386_elf_section_type (const char *str
, size_t len
)
8631 if (flag_code
== CODE_64BIT
8632 && len
== sizeof ("unwind") - 1
8633 && strncmp (str
, "unwind", 6) == 0)
8634 return SHT_X86_64_UNWIND
;
8641 i386_solaris_fix_up_eh_frame (segT sec
)
8643 if (flag_code
== CODE_64BIT
)
8644 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8650 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8654 expr
.X_op
= O_secrel
;
8655 expr
.X_add_symbol
= symbol
;
8656 expr
.X_add_number
= 0;
8657 emit_expr (&expr
, size
);
8661 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8662 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8665 x86_64_section_letter (int letter
, char **ptr_msg
)
8667 if (flag_code
== CODE_64BIT
)
8670 return SHF_X86_64_LARGE
;
8672 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8675 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8680 x86_64_section_word (char *str
, size_t len
)
8682 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8683 return SHF_X86_64_LARGE
;
8689 handle_large_common (int small ATTRIBUTE_UNUSED
)
8691 if (flag_code
!= CODE_64BIT
)
8693 s_comm_internal (0, elf_common_parse
);
8694 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8698 static segT lbss_section
;
8699 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8700 asection
*saved_bss_section
= bss_section
;
8702 if (lbss_section
== NULL
)
8704 flagword applicable
;
8706 subsegT subseg
= now_subseg
;
8708 /* The .lbss section is for local .largecomm symbols. */
8709 lbss_section
= subseg_new (".lbss", 0);
8710 applicable
= bfd_applicable_section_flags (stdoutput
);
8711 bfd_set_section_flags (stdoutput
, lbss_section
,
8712 applicable
& SEC_ALLOC
);
8713 seg_info (lbss_section
)->bss
= 1;
8715 subseg_set (seg
, subseg
);
8718 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8719 bss_section
= lbss_section
;
8721 s_comm_internal (0, elf_common_parse
);
8723 elf_com_section_ptr
= saved_com_section_ptr
;
8724 bss_section
= saved_bss_section
;
8727 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */