1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
135 unsigned int negated
; /* turn off indicated flags. */
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_sse_check (int);
146 static void set_cpu_arch (int);
148 static void pe_directive_secrel (int);
150 static void signed_cons (int);
151 static char *output_invalid (int c
);
152 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
154 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS
*);
159 static int i386_intel_parse_name (const char *, expressionS
*);
160 static const reg_entry
*parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (int, int);
165 static void optimize_imm (void);
166 static void optimize_disp (void);
167 static const insn_template
*match_template (void);
168 static int check_string (void);
169 static int process_suffix (void);
170 static int check_byte_reg (void);
171 static int check_long_reg (void);
172 static int check_qword_reg (void);
173 static int check_word_reg (void);
174 static int finalize_imm (void);
175 static int process_operands (void);
176 static const seg_entry
*build_modrm_byte (void);
177 static void output_insn (void);
178 static void output_imm (fragS
*, offsetT
);
179 static void output_disp (fragS
*, offsetT
);
181 static void s_bss (int);
183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
187 static const char *default_arch
= DEFAULT_ARCH
;
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes
[3];
195 /* Destination or source register specifier. */
196 const reg_entry
*register_specifier
;
199 /* 'md_assemble ()' gathers together information and puts it into a
206 const reg_entry
*regs
;
211 operand_size_mismatch
,
212 operand_type_mismatch
,
213 register_type_mismatch
,
214 number_of_operands_mismatch
,
215 invalid_instruction_suffix
,
218 unsupported_with_intel_mnemonic
,
225 /* TM holds the template for the insn were currently assembling. */
228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
232 /* OPERANDS gives the number of given operands. */
233 unsigned int operands
;
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
238 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
240 /* TYPES [i] is the type (see above #defines) which tells us how to
241 use OP[i] for the corresponding operand. */
242 i386_operand_type types
[MAX_OPERANDS
];
244 /* Displacement expression, immediate expression, or register for each
246 union i386_op op
[MAX_OPERANDS
];
248 /* Flags for operands. */
249 unsigned int flags
[MAX_OPERANDS
];
250 #define Operand_PCrel 1
252 /* Relocation type for operand */
253 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry
*base_reg
;
258 const reg_entry
*index_reg
;
259 unsigned int log2_scale_factor
;
261 /* SEG gives the seg_entries of this insn. They are zero unless
262 explicit segment overrides are given. */
263 const seg_entry
*seg
[2];
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes
;
268 unsigned char prefix
[MAX_PREFIXES
];
270 /* RM and SIB are the modrm byte and the sib byte where the
271 addressing modes of this insn are encoded. */
277 /* Swap operand in encoding. */
278 unsigned int swap_operand
;
280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding
;
284 enum i386_error error
;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
= -1;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static unsigned int disallow_64bit_reloc
;
393 static int use_rela_relocations
= 0;
395 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
396 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
397 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
399 /* The ELF ABI to use. */
407 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
410 /* The names used to print error messages. */
411 static const char *flag_code_names
[] =
418 /* 1 for intel syntax,
420 static int intel_syntax
= 0;
422 /* 1 for intel mnemonic,
423 0 if att mnemonic. */
424 static int intel_mnemonic
= !SYSV386_COMPAT
;
426 /* 1 if support old (<= 2.8.1) versions of gcc. */
427 static int old_gcc
= OLDGCC_COMPAT
;
429 /* 1 if pseudo registers are permitted. */
430 static int allow_pseudo_reg
= 0;
432 /* 1 if register prefix % not required. */
433 static int allow_naked_reg
= 0;
435 /* 1 if pseudo index register, eiz/riz, is allowed . */
436 static int allow_index_reg
= 0;
446 /* Register prefix used for error message. */
447 static const char *register_prefix
= "%";
449 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
450 leave, push, and pop instructions so that gcc has the same stack
451 frame as in 32 bit mode. */
452 static char stackop_size
= '\0';
454 /* Non-zero to optimize code alignment. */
455 int optimize_align_code
= 1;
457 /* Non-zero to quieten some warnings. */
458 static int quiet_warnings
= 0;
461 static const char *cpu_arch_name
= NULL
;
462 static char *cpu_sub_arch_name
= NULL
;
464 /* CPU feature flags. */
465 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
467 /* If we have selected a cpu we are generating instructions for. */
468 static int cpu_arch_tune_set
= 0;
470 /* Cpu we are generating instructions for. */
471 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
473 /* CPU feature flags of cpu we are generating instructions for. */
474 static i386_cpu_flags cpu_arch_tune_flags
;
476 /* CPU instruction set architecture used. */
477 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
479 /* CPU feature flags of instruction set architecture used. */
480 i386_cpu_flags cpu_arch_isa_flags
;
482 /* If set, conditional jumps are not automatically promoted to handle
483 larger than a byte offset. */
484 static unsigned int no_cond_jump_promotion
= 0;
486 /* Encode SSE instructions with VEX prefix. */
487 static unsigned int sse2avx
;
489 /* Encode scalar AVX instructions with specific vector length. */
496 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
497 static symbolS
*GOT_symbol
;
499 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
500 unsigned int x86_dwarf2_return_column
;
502 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
503 int x86_cie_data_alignment
;
505 /* The dwarf2 stack alignment, adjusted for 32 or 64 bit. */
506 static int x86_cie_stack_alignment
;
508 /* Interface to relax_segment.
509 There are 3 major relax states for 386 jump insns because the
510 different types of jumps add different sizes to frags when we're
511 figuring out what sort of jump to choose to reach a given label. */
514 #define UNCOND_JUMP 0
516 #define COND_JUMP86 2
521 #define SMALL16 (SMALL | CODE16)
523 #define BIG16 (BIG | CODE16)
527 #define INLINE __inline__
533 #define ENCODE_RELAX_STATE(type, size) \
534 ((relax_substateT) (((type) << 2) | (size)))
535 #define TYPE_FROM_RELAX_STATE(s) \
537 #define DISP_SIZE_FROM_RELAX_STATE(s) \
538 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
540 /* This table is used by relax_frag to promote short jumps to long
541 ones where necessary. SMALL (short) jumps may be promoted to BIG
542 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
543 don't allow a short jump in a 32 bit code segment to be promoted to
544 a 16 bit offset jump because it's slower (requires data size
545 prefix), and doesn't work, unless the destination is in the bottom
546 64k of the code segment (The top 16 bits of eip are zeroed). */
548 const relax_typeS md_relax_table
[] =
551 1) most positive reach of this state,
552 2) most negative reach of this state,
553 3) how many bytes this mode will have in the variable part of the frag
554 4) which index into the table to try if we can't fit into this one. */
556 /* UNCOND_JUMP states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
559 /* dword jmp adds 4 bytes to frag:
560 0 extra opcode bytes, 4 displacement bytes. */
562 /* word jmp adds 2 byte2 to frag:
563 0 extra opcode bytes, 2 displacement bytes. */
566 /* COND_JUMP states. */
567 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
569 /* dword conditionals adds 5 bytes to frag:
570 1 extra opcode byte, 4 displacement bytes. */
572 /* word conditionals add 3 bytes to frag:
573 1 extra opcode byte, 2 displacement bytes. */
576 /* COND_JUMP86 states. */
577 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
578 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
579 /* dword conditionals adds 5 bytes to frag:
580 1 extra opcode byte, 4 displacement bytes. */
582 /* word conditionals add 4 bytes to frag:
583 1 displacement byte and a 3 byte long branch insn. */
587 static const arch_entry cpu_arch
[] =
589 /* Do not replace the first two entries - i386_target_format()
590 relies on them being there in this order. */
591 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
592 CPU_GENERIC32_FLAGS
, 0, 0 },
593 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
594 CPU_GENERIC64_FLAGS
, 0, 0 },
595 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
596 CPU_NONE_FLAGS
, 0, 0 },
597 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
598 CPU_I186_FLAGS
, 0, 0 },
599 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
600 CPU_I286_FLAGS
, 0, 0 },
601 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
602 CPU_I386_FLAGS
, 0, 0 },
603 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
604 CPU_I486_FLAGS
, 0, 0 },
605 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
606 CPU_I586_FLAGS
, 0, 0 },
607 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
608 CPU_I686_FLAGS
, 0, 0 },
609 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
610 CPU_I586_FLAGS
, 0, 0 },
611 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
612 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
613 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
614 CPU_P2_FLAGS
, 0, 0 },
615 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
616 CPU_P3_FLAGS
, 0, 0 },
617 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
618 CPU_P4_FLAGS
, 0, 0 },
619 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
620 CPU_CORE_FLAGS
, 0, 0 },
621 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
622 CPU_NOCONA_FLAGS
, 0, 0 },
623 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
624 CPU_CORE_FLAGS
, 1, 0 },
625 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
626 CPU_CORE_FLAGS
, 0, 0 },
627 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
628 CPU_CORE2_FLAGS
, 1, 0 },
629 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
630 CPU_CORE2_FLAGS
, 0, 0 },
631 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
632 CPU_COREI7_FLAGS
, 0, 0 },
633 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
634 CPU_L1OM_FLAGS
, 0, 0 },
635 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
636 CPU_K6_FLAGS
, 0, 0 },
637 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
638 CPU_K6_2_FLAGS
, 0, 0 },
639 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
640 CPU_ATHLON_FLAGS
, 0, 0 },
641 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
642 CPU_K8_FLAGS
, 1, 0 },
643 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
644 CPU_K8_FLAGS
, 0, 0 },
645 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
646 CPU_K8_FLAGS
, 0, 0 },
647 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
648 CPU_AMDFAM10_FLAGS
, 0, 0 },
649 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
650 CPU_BDVER1_FLAGS
, 0, 0 },
651 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
652 CPU_8087_FLAGS
, 0, 0 },
653 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
654 CPU_287_FLAGS
, 0, 0 },
655 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
656 CPU_387_FLAGS
, 0, 0 },
657 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
658 CPU_ANY87_FLAGS
, 0, 1 },
659 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
660 CPU_MMX_FLAGS
, 0, 0 },
661 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
662 CPU_3DNOWA_FLAGS
, 0, 1 },
663 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
664 CPU_SSE_FLAGS
, 0, 0 },
665 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
666 CPU_SSE2_FLAGS
, 0, 0 },
667 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
668 CPU_SSE3_FLAGS
, 0, 0 },
669 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
670 CPU_SSSE3_FLAGS
, 0, 0 },
671 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
672 CPU_SSE4_1_FLAGS
, 0, 0 },
673 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
674 CPU_SSE4_2_FLAGS
, 0, 0 },
675 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
676 CPU_SSE4_2_FLAGS
, 0, 0 },
677 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
678 CPU_ANY_SSE_FLAGS
, 0, 1 },
679 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
680 CPU_AVX_FLAGS
, 0, 0 },
681 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
682 CPU_ANY_AVX_FLAGS
, 0, 1 },
683 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
684 CPU_VMX_FLAGS
, 0, 0 },
685 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
686 CPU_SMX_FLAGS
, 0, 0 },
687 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
688 CPU_XSAVE_FLAGS
, 0, 0 },
689 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
690 CPU_XSAVEOPT_FLAGS
, 0, 0 },
691 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
692 CPU_AES_FLAGS
, 0, 0 },
693 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
694 CPU_PCLMUL_FLAGS
, 0, 0 },
695 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
696 CPU_PCLMUL_FLAGS
, 1, 0 },
697 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
698 CPU_FSGSBASE_FLAGS
, 0, 0 },
699 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
700 CPU_RDRND_FLAGS
, 0, 0 },
701 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
702 CPU_F16C_FLAGS
, 0, 0 },
703 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
704 CPU_FMA_FLAGS
, 0, 0 },
705 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
706 CPU_FMA4_FLAGS
, 0, 0 },
707 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
708 CPU_XOP_FLAGS
, 0, 0 },
709 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
710 CPU_LWP_FLAGS
, 0, 0 },
711 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
712 CPU_MOVBE_FLAGS
, 0, 0 },
713 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
714 CPU_EPT_FLAGS
, 0, 0 },
715 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
716 CPU_CLFLUSH_FLAGS
, 0, 0 },
717 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
718 CPU_NOP_FLAGS
, 0, 0 },
719 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
720 CPU_SYSCALL_FLAGS
, 0, 0 },
721 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
722 CPU_RDTSCP_FLAGS
, 0, 0 },
723 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
724 CPU_3DNOW_FLAGS
, 0, 0 },
725 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
726 CPU_3DNOWA_FLAGS
, 0, 0 },
727 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
728 CPU_PADLOCK_FLAGS
, 0, 0 },
729 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
730 CPU_SVME_FLAGS
, 1, 0 },
731 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
732 CPU_SVME_FLAGS
, 0, 0 },
733 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
734 CPU_SSE4A_FLAGS
, 0, 0 },
735 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
736 CPU_ABM_FLAGS
, 0, 0 },
737 { STRING_COMMA_LEN (".bmi"), PROCESSOR_UNKNOWN
,
738 CPU_BMI_FLAGS
, 0, 0 },
739 { STRING_COMMA_LEN (".tbm"), PROCESSOR_UNKNOWN
,
740 CPU_TBM_FLAGS
, 0, 0 },
744 /* Like s_lcomm_internal in gas/read.c but the alignment string
745 is allowed to be optional. */
748 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
755 && *input_line_pointer
== ',')
757 align
= parse_align (needs_align
- 1);
759 if (align
== (addressT
) -1)
774 bss_alloc (symbolP
, size
, align
);
779 pe_lcomm (int needs_align
)
781 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
785 const pseudo_typeS md_pseudo_table
[] =
787 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
788 {"align", s_align_bytes
, 0},
790 {"align", s_align_ptwo
, 0},
792 {"arch", set_cpu_arch
, 0},
796 {"lcomm", pe_lcomm
, 1},
798 {"ffloat", float_cons
, 'f'},
799 {"dfloat", float_cons
, 'd'},
800 {"tfloat", float_cons
, 'x'},
802 {"slong", signed_cons
, 4},
803 {"noopt", s_ignore
, 0},
804 {"optim", s_ignore
, 0},
805 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
806 {"code16", set_code_flag
, CODE_16BIT
},
807 {"code32", set_code_flag
, CODE_32BIT
},
808 {"code64", set_code_flag
, CODE_64BIT
},
809 {"intel_syntax", set_intel_syntax
, 1},
810 {"att_syntax", set_intel_syntax
, 0},
811 {"intel_mnemonic", set_intel_mnemonic
, 1},
812 {"att_mnemonic", set_intel_mnemonic
, 0},
813 {"allow_index_reg", set_allow_index_reg
, 1},
814 {"disallow_index_reg", set_allow_index_reg
, 0},
815 {"sse_check", set_sse_check
, 0},
816 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
817 {"largecomm", handle_large_common
, 0},
819 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
820 {"loc", dwarf2_directive_loc
, 0},
821 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
824 {"secrel32", pe_directive_secrel
, 0},
829 /* For interface with expression (). */
830 extern char *input_line_pointer
;
832 /* Hash table for instruction mnemonic lookup. */
833 static struct hash_control
*op_hash
;
835 /* Hash table for register lookup. */
836 static struct hash_control
*reg_hash
;
839 i386_align_code (fragS
*fragP
, int count
)
841 /* Various efficient no-op patterns for aligning code labels.
842 Note: Don't try to assemble the instructions in the comments.
843 0L and 0w are not legal. */
844 static const char f32_1
[] =
846 static const char f32_2
[] =
847 {0x66,0x90}; /* xchg %ax,%ax */
848 static const char f32_3
[] =
849 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
850 static const char f32_4
[] =
851 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
852 static const char f32_5
[] =
854 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
855 static const char f32_6
[] =
856 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
857 static const char f32_7
[] =
858 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
859 static const char f32_8
[] =
861 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
862 static const char f32_9
[] =
863 {0x89,0xf6, /* movl %esi,%esi */
864 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
865 static const char f32_10
[] =
866 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
867 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
868 static const char f32_11
[] =
869 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
870 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
871 static const char f32_12
[] =
872 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
873 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
874 static const char f32_13
[] =
875 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
876 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
877 static const char f32_14
[] =
878 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
879 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
880 static const char f16_3
[] =
881 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
882 static const char f16_4
[] =
883 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
884 static const char f16_5
[] =
886 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
887 static const char f16_6
[] =
888 {0x89,0xf6, /* mov %si,%si */
889 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
890 static const char f16_7
[] =
891 {0x8d,0x74,0x00, /* lea 0(%si),%si */
892 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
893 static const char f16_8
[] =
894 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
895 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
896 static const char jump_31
[] =
897 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
898 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
899 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
900 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
901 static const char *const f32_patt
[] = {
902 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
903 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
905 static const char *const f16_patt
[] = {
906 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
909 static const char alt_3
[] =
911 /* nopl 0(%[re]ax) */
912 static const char alt_4
[] =
913 {0x0f,0x1f,0x40,0x00};
914 /* nopl 0(%[re]ax,%[re]ax,1) */
915 static const char alt_5
[] =
916 {0x0f,0x1f,0x44,0x00,0x00};
917 /* nopw 0(%[re]ax,%[re]ax,1) */
918 static const char alt_6
[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00};
920 /* nopl 0L(%[re]ax) */
921 static const char alt_7
[] =
922 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
923 /* nopl 0L(%[re]ax,%[re]ax,1) */
924 static const char alt_8
[] =
925 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
926 /* nopw 0L(%[re]ax,%[re]ax,1) */
927 static const char alt_9
[] =
928 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
929 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
930 static const char alt_10
[] =
931 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
933 nopw %cs:0L(%[re]ax,%[re]ax,1) */
934 static const char alt_long_11
[] =
936 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
939 nopw %cs:0L(%[re]ax,%[re]ax,1) */
940 static const char alt_long_12
[] =
943 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
947 nopw %cs:0L(%[re]ax,%[re]ax,1) */
948 static const char alt_long_13
[] =
952 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
957 nopw %cs:0L(%[re]ax,%[re]ax,1) */
958 static const char alt_long_14
[] =
963 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
969 nopw %cs:0L(%[re]ax,%[re]ax,1) */
970 static const char alt_long_15
[] =
976 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
977 /* nopl 0(%[re]ax,%[re]ax,1)
978 nopw 0(%[re]ax,%[re]ax,1) */
979 static const char alt_short_11
[] =
980 {0x0f,0x1f,0x44,0x00,0x00,
981 0x66,0x0f,0x1f,0x44,0x00,0x00};
982 /* nopw 0(%[re]ax,%[re]ax,1)
983 nopw 0(%[re]ax,%[re]ax,1) */
984 static const char alt_short_12
[] =
985 {0x66,0x0f,0x1f,0x44,0x00,0x00,
986 0x66,0x0f,0x1f,0x44,0x00,0x00};
987 /* nopw 0(%[re]ax,%[re]ax,1)
989 static const char alt_short_13
[] =
990 {0x66,0x0f,0x1f,0x44,0x00,0x00,
991 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
994 static const char alt_short_14
[] =
995 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
996 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
998 nopl 0L(%[re]ax,%[re]ax,1) */
999 static const char alt_short_15
[] =
1000 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
1001 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
1002 static const char *const alt_short_patt
[] = {
1003 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1004 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
1005 alt_short_14
, alt_short_15
1007 static const char *const alt_long_patt
[] = {
1008 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
1009 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
1010 alt_long_14
, alt_long_15
1013 /* Only align for at least a positive non-zero boundary. */
1014 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1017 /* We need to decide which NOP sequence to use for 32bit and
1018 64bit. When -mtune= is used:
1020 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1021 PROCESSOR_GENERIC32, f32_patt will be used.
1022 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1023 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1024 PROCESSOR_GENERIC64, alt_long_patt will be used.
1025 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1026 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
1029 When -mtune= isn't used, alt_long_patt will be used if
1030 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1033 When -march= or .arch is used, we can't use anything beyond
1034 cpu_arch_isa_flags. */
1036 if (flag_code
== CODE_16BIT
)
1040 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1042 /* Adjust jump offset. */
1043 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1046 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1047 f16_patt
[count
- 1], count
);
1051 const char *const *patt
= NULL
;
1053 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1055 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1056 switch (cpu_arch_tune
)
1058 case PROCESSOR_UNKNOWN
:
1059 /* We use cpu_arch_isa_flags to check if we SHOULD
1060 optimize with nops. */
1061 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1062 patt
= alt_long_patt
;
1066 case PROCESSOR_PENTIUM4
:
1067 case PROCESSOR_NOCONA
:
1068 case PROCESSOR_CORE
:
1069 case PROCESSOR_CORE2
:
1070 case PROCESSOR_COREI7
:
1071 case PROCESSOR_L1OM
:
1072 case PROCESSOR_GENERIC64
:
1073 patt
= alt_long_patt
;
1076 case PROCESSOR_ATHLON
:
1078 case PROCESSOR_AMDFAM10
:
1079 case PROCESSOR_BDVER1
:
1080 patt
= alt_short_patt
;
1082 case PROCESSOR_I386
:
1083 case PROCESSOR_I486
:
1084 case PROCESSOR_PENTIUM
:
1085 case PROCESSOR_PENTIUMPRO
:
1086 case PROCESSOR_GENERIC32
:
1093 switch (fragP
->tc_frag_data
.tune
)
1095 case PROCESSOR_UNKNOWN
:
1096 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1097 PROCESSOR_UNKNOWN. */
1101 case PROCESSOR_I386
:
1102 case PROCESSOR_I486
:
1103 case PROCESSOR_PENTIUM
:
1105 case PROCESSOR_ATHLON
:
1107 case PROCESSOR_AMDFAM10
:
1108 case PROCESSOR_BDVER1
:
1109 case PROCESSOR_GENERIC32
:
1110 /* We use cpu_arch_isa_flags to check if we CAN optimize
1112 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1113 patt
= alt_short_patt
;
1117 case PROCESSOR_PENTIUMPRO
:
1118 case PROCESSOR_PENTIUM4
:
1119 case PROCESSOR_NOCONA
:
1120 case PROCESSOR_CORE
:
1121 case PROCESSOR_CORE2
:
1122 case PROCESSOR_COREI7
:
1123 case PROCESSOR_L1OM
:
1124 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1125 patt
= alt_long_patt
;
1129 case PROCESSOR_GENERIC64
:
1130 patt
= alt_long_patt
;
1135 if (patt
== f32_patt
)
1137 /* If the padding is less than 15 bytes, we use the normal
1138 ones. Otherwise, we use a jump instruction and adjust
1142 /* For 64bit, the limit is 3 bytes. */
1143 if (flag_code
== CODE_64BIT
1144 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1149 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1150 patt
[count
- 1], count
);
1153 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1155 /* Adjust jump offset. */
1156 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1161 /* Maximum length of an instruction is 15 byte. If the
1162 padding is greater than 15 bytes and we don't use jump,
1163 we have to break it into smaller pieces. */
1164 int padding
= count
;
1165 while (padding
> 15)
1168 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1173 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1174 patt
[padding
- 1], padding
);
1177 fragP
->fr_var
= count
;
1181 operand_type_all_zero (const union i386_operand_type
*x
)
1183 switch (ARRAY_SIZE(x
->array
))
1192 return !x
->array
[0];
1199 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1201 switch (ARRAY_SIZE(x
->array
))
1216 operand_type_equal (const union i386_operand_type
*x
,
1217 const union i386_operand_type
*y
)
1219 switch (ARRAY_SIZE(x
->array
))
1222 if (x
->array
[2] != y
->array
[2])
1225 if (x
->array
[1] != y
->array
[1])
1228 return x
->array
[0] == y
->array
[0];
1236 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1238 switch (ARRAY_SIZE(x
->array
))
1247 return !x
->array
[0];
1254 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1256 switch (ARRAY_SIZE(x
->array
))
1271 cpu_flags_equal (const union i386_cpu_flags
*x
,
1272 const union i386_cpu_flags
*y
)
1274 switch (ARRAY_SIZE(x
->array
))
1277 if (x
->array
[2] != y
->array
[2])
1280 if (x
->array
[1] != y
->array
[1])
1283 return x
->array
[0] == y
->array
[0];
1291 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1293 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1294 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1297 static INLINE i386_cpu_flags
1298 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1300 switch (ARRAY_SIZE (x
.array
))
1303 x
.array
[2] &= y
.array
[2];
1305 x
.array
[1] &= y
.array
[1];
1307 x
.array
[0] &= y
.array
[0];
1315 static INLINE i386_cpu_flags
1316 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1318 switch (ARRAY_SIZE (x
.array
))
1321 x
.array
[2] |= y
.array
[2];
1323 x
.array
[1] |= y
.array
[1];
1325 x
.array
[0] |= y
.array
[0];
1333 static INLINE i386_cpu_flags
1334 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1336 switch (ARRAY_SIZE (x
.array
))
1339 x
.array
[2] &= ~y
.array
[2];
1341 x
.array
[1] &= ~y
.array
[1];
1343 x
.array
[0] &= ~y
.array
[0];
1351 #define CPU_FLAGS_ARCH_MATCH 0x1
1352 #define CPU_FLAGS_64BIT_MATCH 0x2
1353 #define CPU_FLAGS_AES_MATCH 0x4
1354 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1355 #define CPU_FLAGS_AVX_MATCH 0x10
1357 #define CPU_FLAGS_32BIT_MATCH \
1358 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1359 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1360 #define CPU_FLAGS_PERFECT_MATCH \
1361 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1363 /* Return CPU flags match bits. */
1366 cpu_flags_match (const insn_template
*t
)
1368 i386_cpu_flags x
= t
->cpu_flags
;
1369 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1371 x
.bitfield
.cpu64
= 0;
1372 x
.bitfield
.cpuno64
= 0;
1374 if (cpu_flags_all_zero (&x
))
1376 /* This instruction is available on all archs. */
1377 match
|= CPU_FLAGS_32BIT_MATCH
;
1381 /* This instruction is available only on some archs. */
1382 i386_cpu_flags cpu
= cpu_arch_flags
;
1384 cpu
.bitfield
.cpu64
= 0;
1385 cpu
.bitfield
.cpuno64
= 0;
1386 cpu
= cpu_flags_and (x
, cpu
);
1387 if (!cpu_flags_all_zero (&cpu
))
1389 if (x
.bitfield
.cpuavx
)
1391 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1392 if (cpu
.bitfield
.cpuavx
)
1394 /* Check SSE2AVX. */
1395 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1397 match
|= (CPU_FLAGS_ARCH_MATCH
1398 | CPU_FLAGS_AVX_MATCH
);
1400 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1401 match
|= CPU_FLAGS_AES_MATCH
;
1403 if (!x
.bitfield
.cpupclmul
1404 || cpu
.bitfield
.cpupclmul
)
1405 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1409 match
|= CPU_FLAGS_ARCH_MATCH
;
1412 match
|= CPU_FLAGS_32BIT_MATCH
;
1418 static INLINE i386_operand_type
1419 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1421 switch (ARRAY_SIZE (x
.array
))
1424 x
.array
[2] &= y
.array
[2];
1426 x
.array
[1] &= y
.array
[1];
1428 x
.array
[0] &= y
.array
[0];
1436 static INLINE i386_operand_type
1437 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1439 switch (ARRAY_SIZE (x
.array
))
1442 x
.array
[2] |= y
.array
[2];
1444 x
.array
[1] |= y
.array
[1];
1446 x
.array
[0] |= y
.array
[0];
1454 static INLINE i386_operand_type
1455 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1457 switch (ARRAY_SIZE (x
.array
))
1460 x
.array
[2] ^= y
.array
[2];
1462 x
.array
[1] ^= y
.array
[1];
1464 x
.array
[0] ^= y
.array
[0];
1472 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1473 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1474 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1475 static const i386_operand_type inoutportreg
1476 = OPERAND_TYPE_INOUTPORTREG
;
1477 static const i386_operand_type reg16_inoutportreg
1478 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1479 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1480 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1481 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1482 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1483 static const i386_operand_type anydisp
1484 = OPERAND_TYPE_ANYDISP
;
1485 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1486 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1487 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1488 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1489 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1490 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1491 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1492 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1493 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1494 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1495 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1496 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1507 operand_type_check (i386_operand_type t
, enum operand_type c
)
1512 return (t
.bitfield
.reg8
1515 || t
.bitfield
.reg64
);
1518 return (t
.bitfield
.imm8
1522 || t
.bitfield
.imm32s
1523 || t
.bitfield
.imm64
);
1526 return (t
.bitfield
.disp8
1527 || t
.bitfield
.disp16
1528 || t
.bitfield
.disp32
1529 || t
.bitfield
.disp32s
1530 || t
.bitfield
.disp64
);
1533 return (t
.bitfield
.disp8
1534 || t
.bitfield
.disp16
1535 || t
.bitfield
.disp32
1536 || t
.bitfield
.disp32s
1537 || t
.bitfield
.disp64
1538 || t
.bitfield
.baseindex
);
1547 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1548 operand J for instruction template T. */
1551 match_reg_size (const insn_template
*t
, unsigned int j
)
1553 return !((i
.types
[j
].bitfield
.byte
1554 && !t
->operand_types
[j
].bitfield
.byte
)
1555 || (i
.types
[j
].bitfield
.word
1556 && !t
->operand_types
[j
].bitfield
.word
)
1557 || (i
.types
[j
].bitfield
.dword
1558 && !t
->operand_types
[j
].bitfield
.dword
)
1559 || (i
.types
[j
].bitfield
.qword
1560 && !t
->operand_types
[j
].bitfield
.qword
));
1563 /* Return 1 if there is no conflict in any size on operand J for
1564 instruction template T. */
1567 match_mem_size (const insn_template
*t
, unsigned int j
)
1569 return (match_reg_size (t
, j
)
1570 && !((i
.types
[j
].bitfield
.unspecified
1571 && !t
->operand_types
[j
].bitfield
.unspecified
)
1572 || (i
.types
[j
].bitfield
.fword
1573 && !t
->operand_types
[j
].bitfield
.fword
)
1574 || (i
.types
[j
].bitfield
.tbyte
1575 && !t
->operand_types
[j
].bitfield
.tbyte
)
1576 || (i
.types
[j
].bitfield
.xmmword
1577 && !t
->operand_types
[j
].bitfield
.xmmword
)
1578 || (i
.types
[j
].bitfield
.ymmword
1579 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1582 /* Return 1 if there is no size conflict on any operands for
1583 instruction template T. */
1586 operand_size_match (const insn_template
*t
)
1591 /* Don't check jump instructions. */
1592 if (t
->opcode_modifier
.jump
1593 || t
->opcode_modifier
.jumpbyte
1594 || t
->opcode_modifier
.jumpdword
1595 || t
->opcode_modifier
.jumpintersegment
)
1598 /* Check memory and accumulator operand size. */
1599 for (j
= 0; j
< i
.operands
; j
++)
1601 if (t
->operand_types
[j
].bitfield
.anysize
)
1604 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1610 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1619 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1622 i
.error
= operand_size_mismatch
;
1626 /* Check reverse. */
1627 gas_assert (i
.operands
== 2);
1630 for (j
= 0; j
< 2; j
++)
1632 if (t
->operand_types
[j
].bitfield
.acc
1633 && !match_reg_size (t
, j
? 0 : 1))
1636 if (i
.types
[j
].bitfield
.mem
1637 && !match_mem_size (t
, j
? 0 : 1))
1645 operand_type_match (i386_operand_type overlap
,
1646 i386_operand_type given
)
1648 i386_operand_type temp
= overlap
;
1650 temp
.bitfield
.jumpabsolute
= 0;
1651 temp
.bitfield
.unspecified
= 0;
1652 temp
.bitfield
.byte
= 0;
1653 temp
.bitfield
.word
= 0;
1654 temp
.bitfield
.dword
= 0;
1655 temp
.bitfield
.fword
= 0;
1656 temp
.bitfield
.qword
= 0;
1657 temp
.bitfield
.tbyte
= 0;
1658 temp
.bitfield
.xmmword
= 0;
1659 temp
.bitfield
.ymmword
= 0;
1660 if (operand_type_all_zero (&temp
))
1663 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1664 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1668 i
.error
= operand_type_mismatch
;
1672 /* If given types g0 and g1 are registers they must be of the same type
1673 unless the expected operand type register overlap is null.
1674 Note that Acc in a template matches every size of reg. */
1677 operand_type_register_match (i386_operand_type m0
,
1678 i386_operand_type g0
,
1679 i386_operand_type t0
,
1680 i386_operand_type m1
,
1681 i386_operand_type g1
,
1682 i386_operand_type t1
)
1684 if (!operand_type_check (g0
, reg
))
1687 if (!operand_type_check (g1
, reg
))
1690 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1691 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1692 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1693 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1696 if (m0
.bitfield
.acc
)
1698 t0
.bitfield
.reg8
= 1;
1699 t0
.bitfield
.reg16
= 1;
1700 t0
.bitfield
.reg32
= 1;
1701 t0
.bitfield
.reg64
= 1;
1704 if (m1
.bitfield
.acc
)
1706 t1
.bitfield
.reg8
= 1;
1707 t1
.bitfield
.reg16
= 1;
1708 t1
.bitfield
.reg32
= 1;
1709 t1
.bitfield
.reg64
= 1;
1712 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1713 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1714 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1715 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1718 i
.error
= register_type_mismatch
;
1723 static INLINE
unsigned int
1724 mode_from_disp_size (i386_operand_type t
)
1726 if (t
.bitfield
.disp8
)
1728 else if (t
.bitfield
.disp16
1729 || t
.bitfield
.disp32
1730 || t
.bitfield
.disp32s
)
1737 fits_in_signed_byte (offsetT num
)
1739 return (num
>= -128) && (num
<= 127);
1743 fits_in_unsigned_byte (offsetT num
)
1745 return (num
& 0xff) == num
;
1749 fits_in_unsigned_word (offsetT num
)
1751 return (num
& 0xffff) == num
;
1755 fits_in_signed_word (offsetT num
)
1757 return (-32768 <= num
) && (num
<= 32767);
1761 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1766 return (!(((offsetT
) -1 << 31) & num
)
1767 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1769 } /* fits_in_signed_long() */
1772 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1777 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1779 } /* fits_in_unsigned_long() */
1782 fits_in_imm4 (offsetT num
)
1784 return (num
& 0xf) == num
;
1787 static i386_operand_type
1788 smallest_imm_type (offsetT num
)
1790 i386_operand_type t
;
1792 operand_type_set (&t
, 0);
1793 t
.bitfield
.imm64
= 1;
1795 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1797 /* This code is disabled on the 486 because all the Imm1 forms
1798 in the opcode table are slower on the i486. They're the
1799 versions with the implicitly specified single-position
1800 displacement, which has another syntax if you really want to
1802 t
.bitfield
.imm1
= 1;
1803 t
.bitfield
.imm8
= 1;
1804 t
.bitfield
.imm8s
= 1;
1805 t
.bitfield
.imm16
= 1;
1806 t
.bitfield
.imm32
= 1;
1807 t
.bitfield
.imm32s
= 1;
1809 else if (fits_in_signed_byte (num
))
1811 t
.bitfield
.imm8
= 1;
1812 t
.bitfield
.imm8s
= 1;
1813 t
.bitfield
.imm16
= 1;
1814 t
.bitfield
.imm32
= 1;
1815 t
.bitfield
.imm32s
= 1;
1817 else if (fits_in_unsigned_byte (num
))
1819 t
.bitfield
.imm8
= 1;
1820 t
.bitfield
.imm16
= 1;
1821 t
.bitfield
.imm32
= 1;
1822 t
.bitfield
.imm32s
= 1;
1824 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1826 t
.bitfield
.imm16
= 1;
1827 t
.bitfield
.imm32
= 1;
1828 t
.bitfield
.imm32s
= 1;
1830 else if (fits_in_signed_long (num
))
1832 t
.bitfield
.imm32
= 1;
1833 t
.bitfield
.imm32s
= 1;
1835 else if (fits_in_unsigned_long (num
))
1836 t
.bitfield
.imm32
= 1;
1842 offset_in_range (offsetT val
, int size
)
1848 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1849 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1850 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1852 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1858 /* If BFD64, sign extend val for 32bit address mode. */
1859 if (flag_code
!= CODE_64BIT
1860 || i
.prefix
[ADDR_PREFIX
])
1861 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1862 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1865 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1867 char buf1
[40], buf2
[40];
1869 sprint_value (buf1
, val
);
1870 sprint_value (buf2
, val
& mask
);
1871 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1885 a. PREFIX_EXIST if attempting to add a prefix where one from the
1886 same class already exists.
1887 b. PREFIX_LOCK if lock prefix is added.
1888 c. PREFIX_REP if rep/repne prefix is added.
1889 d. PREFIX_OTHER if other prefix is added.
1892 static enum PREFIX_GROUP
1893 add_prefix (unsigned int prefix
)
1895 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1898 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1899 && flag_code
== CODE_64BIT
)
1901 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1902 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1903 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1914 case CS_PREFIX_OPCODE
:
1915 case DS_PREFIX_OPCODE
:
1916 case ES_PREFIX_OPCODE
:
1917 case FS_PREFIX_OPCODE
:
1918 case GS_PREFIX_OPCODE
:
1919 case SS_PREFIX_OPCODE
:
1923 case REPNE_PREFIX_OPCODE
:
1924 case REPE_PREFIX_OPCODE
:
1929 case LOCK_PREFIX_OPCODE
:
1938 case ADDR_PREFIX_OPCODE
:
1942 case DATA_PREFIX_OPCODE
:
1946 if (i
.prefix
[q
] != 0)
1954 i
.prefix
[q
] |= prefix
;
1957 as_bad (_("same type of prefix used twice"));
1963 update_code_flag (int value
, int check
)
1965 PRINTF_LIKE ((*as_error
));
1967 flag_code
= (enum flag_code
) value
;
1968 if (flag_code
== CODE_64BIT
)
1970 cpu_arch_flags
.bitfield
.cpu64
= 1;
1971 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1975 cpu_arch_flags
.bitfield
.cpu64
= 0;
1976 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1978 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1981 as_error
= as_fatal
;
1984 (*as_error
) (_("64bit mode not supported on `%s'."),
1985 cpu_arch_name
? cpu_arch_name
: default_arch
);
1987 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1990 as_error
= as_fatal
;
1993 (*as_error
) (_("32bit mode not supported on `%s'."),
1994 cpu_arch_name
? cpu_arch_name
: default_arch
);
1996 stackop_size
= '\0';
2000 set_code_flag (int value
)
2002 update_code_flag (value
, 0);
2006 set_16bit_gcc_code_flag (int new_code_flag
)
2008 flag_code
= (enum flag_code
) new_code_flag
;
2009 if (flag_code
!= CODE_16BIT
)
2011 cpu_arch_flags
.bitfield
.cpu64
= 0;
2012 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2013 stackop_size
= LONG_MNEM_SUFFIX
;
2017 set_intel_syntax (int syntax_flag
)
2019 /* Find out if register prefixing is specified. */
2020 int ask_naked_reg
= 0;
2023 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2025 char *string
= input_line_pointer
;
2026 int e
= get_symbol_end ();
2028 if (strcmp (string
, "prefix") == 0)
2030 else if (strcmp (string
, "noprefix") == 0)
2033 as_bad (_("bad argument to syntax directive."));
2034 *input_line_pointer
= e
;
2036 demand_empty_rest_of_line ();
2038 intel_syntax
= syntax_flag
;
2040 if (ask_naked_reg
== 0)
2041 allow_naked_reg
= (intel_syntax
2042 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2044 allow_naked_reg
= (ask_naked_reg
< 0);
2046 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2048 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2049 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2050 register_prefix
= allow_naked_reg
? "" : "%";
2054 set_intel_mnemonic (int mnemonic_flag
)
2056 intel_mnemonic
= mnemonic_flag
;
2060 set_allow_index_reg (int flag
)
2062 allow_index_reg
= flag
;
2066 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2070 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2072 char *string
= input_line_pointer
;
2073 int e
= get_symbol_end ();
2075 if (strcmp (string
, "none") == 0)
2076 sse_check
= sse_check_none
;
2077 else if (strcmp (string
, "warning") == 0)
2078 sse_check
= sse_check_warning
;
2079 else if (strcmp (string
, "error") == 0)
2080 sse_check
= sse_check_error
;
2082 as_bad (_("bad argument to sse_check directive."));
2083 *input_line_pointer
= e
;
2086 as_bad (_("missing argument for sse_check directive"));
2088 demand_empty_rest_of_line ();
2092 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2093 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2095 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2096 static const char *arch
;
2098 /* Intel LIOM is only supported on ELF. */
2104 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2105 use default_arch. */
2106 arch
= cpu_arch_name
;
2108 arch
= default_arch
;
2111 /* If we are targeting Intel L1OM, we must enable it. */
2112 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2113 || new_flag
.bitfield
.cpul1om
)
2116 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2121 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2125 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2127 char *string
= input_line_pointer
;
2128 int e
= get_symbol_end ();
2130 i386_cpu_flags flags
;
2132 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2134 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2136 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2140 cpu_arch_name
= cpu_arch
[j
].name
;
2141 cpu_sub_arch_name
= NULL
;
2142 cpu_arch_flags
= cpu_arch
[j
].flags
;
2143 if (flag_code
== CODE_64BIT
)
2145 cpu_arch_flags
.bitfield
.cpu64
= 1;
2146 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2150 cpu_arch_flags
.bitfield
.cpu64
= 0;
2151 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2153 cpu_arch_isa
= cpu_arch
[j
].type
;
2154 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2155 if (!cpu_arch_tune_set
)
2157 cpu_arch_tune
= cpu_arch_isa
;
2158 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2163 if (!cpu_arch
[j
].negated
)
2164 flags
= cpu_flags_or (cpu_arch_flags
,
2167 flags
= cpu_flags_and_not (cpu_arch_flags
,
2169 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2171 if (cpu_sub_arch_name
)
2173 char *name
= cpu_sub_arch_name
;
2174 cpu_sub_arch_name
= concat (name
,
2176 (const char *) NULL
);
2180 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2181 cpu_arch_flags
= flags
;
2182 cpu_arch_isa_flags
= flags
;
2184 *input_line_pointer
= e
;
2185 demand_empty_rest_of_line ();
2189 if (j
>= ARRAY_SIZE (cpu_arch
))
2190 as_bad (_("no such architecture: `%s'"), string
);
2192 *input_line_pointer
= e
;
2195 as_bad (_("missing cpu architecture"));
2197 no_cond_jump_promotion
= 0;
2198 if (*input_line_pointer
== ','
2199 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2201 char *string
= ++input_line_pointer
;
2202 int e
= get_symbol_end ();
2204 if (strcmp (string
, "nojumps") == 0)
2205 no_cond_jump_promotion
= 1;
2206 else if (strcmp (string
, "jumps") == 0)
2209 as_bad (_("no such architecture modifier: `%s'"), string
);
2211 *input_line_pointer
= e
;
2214 demand_empty_rest_of_line ();
2217 enum bfd_architecture
2220 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2222 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2223 || flag_code
!= CODE_64BIT
)
2224 as_fatal (_("Intel L1OM is 64bit ELF only"));
2225 return bfd_arch_l1om
;
2228 return bfd_arch_i386
;
2234 if (!strncmp (default_arch
, "x86_64", 6))
2236 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2238 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2239 || default_arch
[6] != '\0')
2240 as_fatal (_("Intel L1OM is 64bit ELF only"));
2241 return bfd_mach_l1om
;
2243 else if (default_arch
[6] == '\0')
2244 return bfd_mach_x86_64
;
2246 return bfd_mach_x64_32
;
2248 else if (!strcmp (default_arch
, "i386"))
2249 return bfd_mach_i386_i386
;
2251 as_fatal (_("Unknown architecture"));
2257 const char *hash_err
;
2259 /* Initialize op_hash hash table. */
2260 op_hash
= hash_new ();
2263 const insn_template
*optab
;
2264 templates
*core_optab
;
2266 /* Setup for loop. */
2268 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2269 core_optab
->start
= optab
;
2274 if (optab
->name
== NULL
2275 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2277 /* different name --> ship out current template list;
2278 add to hash table; & begin anew. */
2279 core_optab
->end
= optab
;
2280 hash_err
= hash_insert (op_hash
,
2282 (void *) core_optab
);
2285 as_fatal (_("Internal Error: Can't hash %s: %s"),
2289 if (optab
->name
== NULL
)
2291 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2292 core_optab
->start
= optab
;
2297 /* Initialize reg_hash hash table. */
2298 reg_hash
= hash_new ();
2300 const reg_entry
*regtab
;
2301 unsigned int regtab_size
= i386_regtab_size
;
2303 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2305 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2307 as_fatal (_("Internal Error: Can't hash %s: %s"),
2313 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2318 for (c
= 0; c
< 256; c
++)
2323 mnemonic_chars
[c
] = c
;
2324 register_chars
[c
] = c
;
2325 operand_chars
[c
] = c
;
2327 else if (ISLOWER (c
))
2329 mnemonic_chars
[c
] = c
;
2330 register_chars
[c
] = c
;
2331 operand_chars
[c
] = c
;
2333 else if (ISUPPER (c
))
2335 mnemonic_chars
[c
] = TOLOWER (c
);
2336 register_chars
[c
] = mnemonic_chars
[c
];
2337 operand_chars
[c
] = c
;
2340 if (ISALPHA (c
) || ISDIGIT (c
))
2341 identifier_chars
[c
] = c
;
2344 identifier_chars
[c
] = c
;
2345 operand_chars
[c
] = c
;
2350 identifier_chars
['@'] = '@';
2353 identifier_chars
['?'] = '?';
2354 operand_chars
['?'] = '?';
2356 digit_chars
['-'] = '-';
2357 mnemonic_chars
['_'] = '_';
2358 mnemonic_chars
['-'] = '-';
2359 mnemonic_chars
['.'] = '.';
2360 identifier_chars
['_'] = '_';
2361 identifier_chars
['.'] = '.';
2363 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2364 operand_chars
[(unsigned char) *p
] = *p
;
2367 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2370 record_alignment (text_section
, 2);
2371 record_alignment (data_section
, 2);
2372 record_alignment (bss_section
, 2);
2376 if (flag_code
== CODE_64BIT
)
2378 #if defined (OBJ_COFF) && defined (TE_PE)
2379 x86_dwarf2_return_column
= (OUTPUT_FLAVOR
== bfd_target_coff_flavour
2382 x86_dwarf2_return_column
= 16;
2384 if (!x86_cie_data_alignment
)
2385 x86_cie_data_alignment
= -8;
2386 x86_cie_stack_alignment
= -8;
2390 x86_dwarf2_return_column
= 8;
2391 x86_cie_data_alignment
= -4;
2392 x86_cie_stack_alignment
= -4;
2397 i386_print_statistics (FILE *file
)
2399 hash_print_statistics (file
, "i386 opcode", op_hash
);
2400 hash_print_statistics (file
, "i386 register", reg_hash
);
2405 /* Debugging routines for md_assemble. */
2406 static void pte (insn_template
*);
2407 static void pt (i386_operand_type
);
2408 static void pe (expressionS
*);
2409 static void ps (symbolS
*);
2412 pi (char *line
, i386_insn
*x
)
2416 fprintf (stdout
, "%s: template ", line
);
2418 fprintf (stdout
, " address: base %s index %s scale %x\n",
2419 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2420 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2421 x
->log2_scale_factor
);
2422 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2423 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2424 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2425 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2426 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2427 (x
->rex
& REX_W
) != 0,
2428 (x
->rex
& REX_R
) != 0,
2429 (x
->rex
& REX_X
) != 0,
2430 (x
->rex
& REX_B
) != 0);
2431 for (j
= 0; j
< x
->operands
; j
++)
2433 fprintf (stdout
, " #%d: ", j
+ 1);
2435 fprintf (stdout
, "\n");
2436 if (x
->types
[j
].bitfield
.reg8
2437 || x
->types
[j
].bitfield
.reg16
2438 || x
->types
[j
].bitfield
.reg32
2439 || x
->types
[j
].bitfield
.reg64
2440 || x
->types
[j
].bitfield
.regmmx
2441 || x
->types
[j
].bitfield
.regxmm
2442 || x
->types
[j
].bitfield
.regymm
2443 || x
->types
[j
].bitfield
.sreg2
2444 || x
->types
[j
].bitfield
.sreg3
2445 || x
->types
[j
].bitfield
.control
2446 || x
->types
[j
].bitfield
.debug
2447 || x
->types
[j
].bitfield
.test
)
2448 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2449 if (operand_type_check (x
->types
[j
], imm
))
2451 if (operand_type_check (x
->types
[j
], disp
))
2452 pe (x
->op
[j
].disps
);
2457 pte (insn_template
*t
)
2460 fprintf (stdout
, " %d operands ", t
->operands
);
2461 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2462 if (t
->extension_opcode
!= None
)
2463 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2464 if (t
->opcode_modifier
.d
)
2465 fprintf (stdout
, "D");
2466 if (t
->opcode_modifier
.w
)
2467 fprintf (stdout
, "W");
2468 fprintf (stdout
, "\n");
2469 for (j
= 0; j
< t
->operands
; j
++)
2471 fprintf (stdout
, " #%d type ", j
+ 1);
2472 pt (t
->operand_types
[j
]);
2473 fprintf (stdout
, "\n");
2480 fprintf (stdout
, " operation %d\n", e
->X_op
);
2481 fprintf (stdout
, " add_number %ld (%lx)\n",
2482 (long) e
->X_add_number
, (long) e
->X_add_number
);
2483 if (e
->X_add_symbol
)
2485 fprintf (stdout
, " add_symbol ");
2486 ps (e
->X_add_symbol
);
2487 fprintf (stdout
, "\n");
2491 fprintf (stdout
, " op_symbol ");
2492 ps (e
->X_op_symbol
);
2493 fprintf (stdout
, "\n");
2500 fprintf (stdout
, "%s type %s%s",
2502 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2503 segment_name (S_GET_SEGMENT (s
)));
2506 static struct type_name
2508 i386_operand_type mask
;
2511 const type_names
[] =
2513 { OPERAND_TYPE_REG8
, "r8" },
2514 { OPERAND_TYPE_REG16
, "r16" },
2515 { OPERAND_TYPE_REG32
, "r32" },
2516 { OPERAND_TYPE_REG64
, "r64" },
2517 { OPERAND_TYPE_IMM8
, "i8" },
2518 { OPERAND_TYPE_IMM8
, "i8s" },
2519 { OPERAND_TYPE_IMM16
, "i16" },
2520 { OPERAND_TYPE_IMM32
, "i32" },
2521 { OPERAND_TYPE_IMM32S
, "i32s" },
2522 { OPERAND_TYPE_IMM64
, "i64" },
2523 { OPERAND_TYPE_IMM1
, "i1" },
2524 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2525 { OPERAND_TYPE_DISP8
, "d8" },
2526 { OPERAND_TYPE_DISP16
, "d16" },
2527 { OPERAND_TYPE_DISP32
, "d32" },
2528 { OPERAND_TYPE_DISP32S
, "d32s" },
2529 { OPERAND_TYPE_DISP64
, "d64" },
2530 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2531 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2532 { OPERAND_TYPE_CONTROL
, "control reg" },
2533 { OPERAND_TYPE_TEST
, "test reg" },
2534 { OPERAND_TYPE_DEBUG
, "debug reg" },
2535 { OPERAND_TYPE_FLOATREG
, "FReg" },
2536 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2537 { OPERAND_TYPE_SREG2
, "SReg2" },
2538 { OPERAND_TYPE_SREG3
, "SReg3" },
2539 { OPERAND_TYPE_ACC
, "Acc" },
2540 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2541 { OPERAND_TYPE_REGMMX
, "rMMX" },
2542 { OPERAND_TYPE_REGXMM
, "rXMM" },
2543 { OPERAND_TYPE_REGYMM
, "rYMM" },
2544 { OPERAND_TYPE_ESSEG
, "es" },
2548 pt (i386_operand_type t
)
2551 i386_operand_type a
;
2553 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2555 a
= operand_type_and (t
, type_names
[j
].mask
);
2556 if (!operand_type_all_zero (&a
))
2557 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2562 #endif /* DEBUG386 */
2564 static bfd_reloc_code_real_type
2565 reloc (unsigned int size
,
2568 bfd_reloc_code_real_type other
)
2570 if (other
!= NO_RELOC
)
2572 reloc_howto_type
*rel
;
2577 case BFD_RELOC_X86_64_GOT32
:
2578 return BFD_RELOC_X86_64_GOT64
;
2580 case BFD_RELOC_X86_64_PLTOFF64
:
2581 return BFD_RELOC_X86_64_PLTOFF64
;
2583 case BFD_RELOC_X86_64_GOTPC32
:
2584 other
= BFD_RELOC_X86_64_GOTPC64
;
2586 case BFD_RELOC_X86_64_GOTPCREL
:
2587 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2589 case BFD_RELOC_X86_64_TPOFF32
:
2590 other
= BFD_RELOC_X86_64_TPOFF64
;
2592 case BFD_RELOC_X86_64_DTPOFF32
:
2593 other
= BFD_RELOC_X86_64_DTPOFF64
;
2599 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2600 if (size
== 4 && (flag_code
!= CODE_64BIT
|| disallow_64bit_reloc
))
2603 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2605 as_bad (_("unknown relocation (%u)"), other
);
2606 else if (size
!= bfd_get_reloc_size (rel
))
2607 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2608 bfd_get_reloc_size (rel
),
2610 else if (pcrel
&& !rel
->pc_relative
)
2611 as_bad (_("non-pc-relative relocation for pc-relative field"));
2612 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2614 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2616 as_bad (_("relocated field and relocation type differ in signedness"));
2625 as_bad (_("there are no unsigned pc-relative relocations"));
2628 case 1: return BFD_RELOC_8_PCREL
;
2629 case 2: return BFD_RELOC_16_PCREL
;
2630 case 4: return BFD_RELOC_32_PCREL
;
2631 case 8: return BFD_RELOC_64_PCREL
;
2633 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2640 case 4: return BFD_RELOC_X86_64_32S
;
2645 case 1: return BFD_RELOC_8
;
2646 case 2: return BFD_RELOC_16
;
2647 case 4: return BFD_RELOC_32
;
2648 case 8: return BFD_RELOC_64
;
2650 as_bad (_("cannot do %s %u byte relocation"),
2651 sign
> 0 ? "signed" : "unsigned", size
);
2657 /* Here we decide which fixups can be adjusted to make them relative to
2658 the beginning of the section instead of the symbol. Basically we need
2659 to make sure that the dynamic relocations are done correctly, so in
2660 some cases we force the original symbol to be used. */
2663 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2665 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2669 /* Don't adjust pc-relative references to merge sections in 64-bit
2671 if (use_rela_relocations
2672 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2676 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2677 and changed later by validate_fix. */
2678 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2679 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2682 /* adjust_reloc_syms doesn't know about the GOT. */
2683 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2684 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2685 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2686 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2687 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2688 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2689 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2690 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2691 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2692 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2693 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2694 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2695 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2696 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2697 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2698 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2699 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2700 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2701 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2702 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2703 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2704 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2705 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2706 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2707 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2708 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2709 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2710 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2717 intel_float_operand (const char *mnemonic
)
2719 /* Note that the value returned is meaningful only for opcodes with (memory)
2720 operands, hence the code here is free to improperly handle opcodes that
2721 have no operands (for better performance and smaller code). */
2723 if (mnemonic
[0] != 'f')
2724 return 0; /* non-math */
2726 switch (mnemonic
[1])
2728 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2729 the fs segment override prefix not currently handled because no
2730 call path can make opcodes without operands get here */
2732 return 2 /* integer op */;
2734 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2735 return 3; /* fldcw/fldenv */
2738 if (mnemonic
[2] != 'o' /* fnop */)
2739 return 3; /* non-waiting control op */
2742 if (mnemonic
[2] == 's')
2743 return 3; /* frstor/frstpm */
2746 if (mnemonic
[2] == 'a')
2747 return 3; /* fsave */
2748 if (mnemonic
[2] == 't')
2750 switch (mnemonic
[3])
2752 case 'c': /* fstcw */
2753 case 'd': /* fstdw */
2754 case 'e': /* fstenv */
2755 case 's': /* fsts[gw] */
2761 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2762 return 0; /* fxsave/fxrstor are not really math ops */
2769 /* Build the VEX prefix. */
2772 build_vex_prefix (const insn_template
*t
)
2774 unsigned int register_specifier
;
2775 unsigned int implied_prefix
;
2776 unsigned int vector_length
;
2778 /* Check register specifier. */
2779 if (i
.vex
.register_specifier
)
2781 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2782 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2783 register_specifier
+= 8;
2784 register_specifier
= ~register_specifier
& 0xf;
2787 register_specifier
= 0xf;
2789 /* Use 2-byte VEX prefix by swappping destination and source
2792 && i
.operands
== i
.reg_operands
2793 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2794 && i
.tm
.opcode_modifier
.s
2797 unsigned int xchg
= i
.operands
- 1;
2798 union i386_op temp_op
;
2799 i386_operand_type temp_type
;
2801 temp_type
= i
.types
[xchg
];
2802 i
.types
[xchg
] = i
.types
[0];
2803 i
.types
[0] = temp_type
;
2804 temp_op
= i
.op
[xchg
];
2805 i
.op
[xchg
] = i
.op
[0];
2808 gas_assert (i
.rm
.mode
== 3);
2812 i
.rm
.regmem
= i
.rm
.reg
;
2815 /* Use the next insn. */
2819 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2820 vector_length
= avxscalar
;
2822 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2824 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2829 case DATA_PREFIX_OPCODE
:
2832 case REPE_PREFIX_OPCODE
:
2835 case REPNE_PREFIX_OPCODE
:
2842 /* Use 2-byte VEX prefix if possible. */
2843 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2844 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2845 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2847 /* 2-byte VEX prefix. */
2851 i
.vex
.bytes
[0] = 0xc5;
2853 /* Check the REX.R bit. */
2854 r
= (i
.rex
& REX_R
) ? 0 : 1;
2855 i
.vex
.bytes
[1] = (r
<< 7
2856 | register_specifier
<< 3
2857 | vector_length
<< 2
2862 /* 3-byte VEX prefix. */
2867 switch (i
.tm
.opcode_modifier
.vexopcode
)
2871 i
.vex
.bytes
[0] = 0xc4;
2875 i
.vex
.bytes
[0] = 0xc4;
2879 i
.vex
.bytes
[0] = 0xc4;
2883 i
.vex
.bytes
[0] = 0x8f;
2887 i
.vex
.bytes
[0] = 0x8f;
2891 i
.vex
.bytes
[0] = 0x8f;
2897 /* The high 3 bits of the second VEX byte are 1's compliment
2898 of RXB bits from REX. */
2899 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2901 /* Check the REX.W bit. */
2902 w
= (i
.rex
& REX_W
) ? 1 : 0;
2903 if (i
.tm
.opcode_modifier
.vexw
)
2908 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2912 i
.vex
.bytes
[2] = (w
<< 7
2913 | register_specifier
<< 3
2914 | vector_length
<< 2
2920 process_immext (void)
2924 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2926 /* SSE3 Instructions have the fixed operands with an opcode
2927 suffix which is coded in the same place as an 8-bit immediate
2928 field would be. Here we check those operands and remove them
2932 for (x
= 0; x
< i
.operands
; x
++)
2933 if (i
.op
[x
].regs
->reg_num
!= x
)
2934 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2935 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2941 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2942 which is coded in the same place as an 8-bit immediate field
2943 would be. Here we fake an 8-bit immediate operand from the
2944 opcode suffix stored in tm.extension_opcode.
2946 AVX instructions also use this encoding, for some of
2947 3 argument instructions. */
2949 gas_assert (i
.imm_operands
== 0
2951 || (i
.tm
.opcode_modifier
.vex
2952 && i
.operands
<= 4)));
2954 exp
= &im_expressions
[i
.imm_operands
++];
2955 i
.op
[i
.operands
].imms
= exp
;
2956 i
.types
[i
.operands
] = imm8
;
2958 exp
->X_op
= O_constant
;
2959 exp
->X_add_number
= i
.tm
.extension_opcode
;
2960 i
.tm
.extension_opcode
= None
;
2963 /* This is the guts of the machine-dependent assembler. LINE points to a
2964 machine dependent instruction. This function is supposed to emit
2965 the frags/bytes it assembles to. */
2968 md_assemble (char *line
)
2971 char mnemonic
[MAX_MNEM_SIZE
];
2972 const insn_template
*t
;
2974 /* Initialize globals. */
2975 memset (&i
, '\0', sizeof (i
));
2976 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2977 i
.reloc
[j
] = NO_RELOC
;
2978 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2979 memset (im_expressions
, '\0', sizeof (im_expressions
));
2980 save_stack_p
= save_stack
;
2982 /* First parse an instruction mnemonic & call i386_operand for the operands.
2983 We assume that the scrubber has arranged it so that line[0] is the valid
2984 start of a (possibly prefixed) mnemonic. */
2986 line
= parse_insn (line
, mnemonic
);
2990 line
= parse_operands (line
, mnemonic
);
2995 /* Now we've parsed the mnemonic into a set of templates, and have the
2996 operands at hand. */
2998 /* All intel opcodes have reversed operands except for "bound" and
2999 "enter". We also don't reverse intersegment "jmp" and "call"
3000 instructions with 2 immediate operands so that the immediate segment
3001 precedes the offset, as it does when in AT&T mode. */
3004 && (strcmp (mnemonic
, "bound") != 0)
3005 && (strcmp (mnemonic
, "invlpga") != 0)
3006 && !(operand_type_check (i
.types
[0], imm
)
3007 && operand_type_check (i
.types
[1], imm
)))
3010 /* The order of the immediates should be reversed
3011 for 2 immediates extrq and insertq instructions */
3012 if (i
.imm_operands
== 2
3013 && (strcmp (mnemonic
, "extrq") == 0
3014 || strcmp (mnemonic
, "insertq") == 0))
3015 swap_2_operands (0, 1);
3020 /* Don't optimize displacement for movabs since it only takes 64bit
3023 && !i
.disp32_encoding
3024 && (flag_code
!= CODE_64BIT
3025 || strcmp (mnemonic
, "movabs") != 0))
3028 /* Next, we find a template that matches the given insn,
3029 making sure the overlap of the given operands types is consistent
3030 with the template operand types. */
3032 if (!(t
= match_template ()))
3035 if (sse_check
!= sse_check_none
3036 && !i
.tm
.opcode_modifier
.noavx
3037 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3038 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3039 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3040 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3041 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3042 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3044 (sse_check
== sse_check_warning
3046 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3049 /* Zap movzx and movsx suffix. The suffix has been set from
3050 "word ptr" or "byte ptr" on the source operand in Intel syntax
3051 or extracted from mnemonic in AT&T syntax. But we'll use
3052 the destination register to choose the suffix for encoding. */
3053 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3055 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3056 there is no suffix, the default will be byte extension. */
3057 if (i
.reg_operands
!= 2
3060 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3065 if (i
.tm
.opcode_modifier
.fwait
)
3066 if (!add_prefix (FWAIT_OPCODE
))
3069 /* Check for lock without a lockable instruction. Destination operand
3070 must be memory unless it is xchg (0x86). */
3071 if (i
.prefix
[LOCK_PREFIX
]
3072 && (!i
.tm
.opcode_modifier
.islockable
3073 || i
.mem_operands
== 0
3074 || (i
.tm
.base_opcode
!= 0x86
3075 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3077 as_bad (_("expecting lockable instruction after `lock'"));
3081 /* Check string instruction segment overrides. */
3082 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3084 if (!check_string ())
3086 i
.disp_operands
= 0;
3089 if (!process_suffix ())
3092 /* Update operand types. */
3093 for (j
= 0; j
< i
.operands
; j
++)
3094 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3096 /* Make still unresolved immediate matches conform to size of immediate
3097 given in i.suffix. */
3098 if (!finalize_imm ())
3101 if (i
.types
[0].bitfield
.imm1
)
3102 i
.imm_operands
= 0; /* kludge for shift insns. */
3104 /* We only need to check those implicit registers for instructions
3105 with 3 operands or less. */
3106 if (i
.operands
<= 3)
3107 for (j
= 0; j
< i
.operands
; j
++)
3108 if (i
.types
[j
].bitfield
.inoutportreg
3109 || i
.types
[j
].bitfield
.shiftcount
3110 || i
.types
[j
].bitfield
.acc
3111 || i
.types
[j
].bitfield
.floatacc
)
3114 /* ImmExt should be processed after SSE2AVX. */
3115 if (!i
.tm
.opcode_modifier
.sse2avx
3116 && i
.tm
.opcode_modifier
.immext
)
3119 /* For insns with operands there are more diddles to do to the opcode. */
3122 if (!process_operands ())
3125 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3127 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3128 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3131 if (i
.tm
.opcode_modifier
.vex
)
3132 build_vex_prefix (t
);
3134 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3135 instructions may define INT_OPCODE as well, so avoid this corner
3136 case for those instructions that use MODRM. */
3137 if (i
.tm
.base_opcode
== INT_OPCODE
3138 && !i
.tm
.opcode_modifier
.modrm
3139 && i
.op
[0].imms
->X_add_number
== 3)
3141 i
.tm
.base_opcode
= INT3_OPCODE
;
3145 if ((i
.tm
.opcode_modifier
.jump
3146 || i
.tm
.opcode_modifier
.jumpbyte
3147 || i
.tm
.opcode_modifier
.jumpdword
)
3148 && i
.op
[0].disps
->X_op
== O_constant
)
3150 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3151 the absolute address given by the constant. Since ix86 jumps and
3152 calls are pc relative, we need to generate a reloc. */
3153 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3154 i
.op
[0].disps
->X_op
= O_symbol
;
3157 if (i
.tm
.opcode_modifier
.rex64
)
3160 /* For 8 bit registers we need an empty rex prefix. Also if the
3161 instruction already has a prefix, we need to convert old
3162 registers to new ones. */
3164 if ((i
.types
[0].bitfield
.reg8
3165 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3166 || (i
.types
[1].bitfield
.reg8
3167 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3168 || ((i
.types
[0].bitfield
.reg8
3169 || i
.types
[1].bitfield
.reg8
)
3174 i
.rex
|= REX_OPCODE
;
3175 for (x
= 0; x
< 2; x
++)
3177 /* Look for 8 bit operand that uses old registers. */
3178 if (i
.types
[x
].bitfield
.reg8
3179 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3181 /* In case it is "hi" register, give up. */
3182 if (i
.op
[x
].regs
->reg_num
> 3)
3183 as_bad (_("can't encode register '%s%s' in an "
3184 "instruction requiring REX prefix."),
3185 register_prefix
, i
.op
[x
].regs
->reg_name
);
3187 /* Otherwise it is equivalent to the extended register.
3188 Since the encoding doesn't change this is merely
3189 cosmetic cleanup for debug output. */
3191 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3197 add_prefix (REX_OPCODE
| i
.rex
);
3199 /* We are ready to output the insn. */
3204 parse_insn (char *line
, char *mnemonic
)
3207 char *token_start
= l
;
3210 const insn_template
*t
;
3213 /* Non-zero if we found a prefix only acceptable with string insns. */
3214 const char *expecting_string_instruction
= NULL
;
3219 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3224 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3226 as_bad (_("no such instruction: `%s'"), token_start
);
3231 if (!is_space_char (*l
)
3232 && *l
!= END_OF_INSN
3234 || (*l
!= PREFIX_SEPARATOR
3237 as_bad (_("invalid character %s in mnemonic"),
3238 output_invalid (*l
));
3241 if (token_start
== l
)
3243 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3244 as_bad (_("expecting prefix; got nothing"));
3246 as_bad (_("expecting mnemonic; got nothing"));
3250 /* Look up instruction (or prefix) via hash table. */
3251 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3253 if (*l
!= END_OF_INSN
3254 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3255 && current_templates
3256 && current_templates
->start
->opcode_modifier
.isprefix
)
3258 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3260 as_bad ((flag_code
!= CODE_64BIT
3261 ? _("`%s' is only supported in 64-bit mode")
3262 : _("`%s' is not supported in 64-bit mode")),
3263 current_templates
->start
->name
);
3266 /* If we are in 16-bit mode, do not allow addr16 or data16.
3267 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3268 if ((current_templates
->start
->opcode_modifier
.size16
3269 || current_templates
->start
->opcode_modifier
.size32
)
3270 && flag_code
!= CODE_64BIT
3271 && (current_templates
->start
->opcode_modifier
.size32
3272 ^ (flag_code
== CODE_16BIT
)))
3274 as_bad (_("redundant %s prefix"),
3275 current_templates
->start
->name
);
3278 /* Add prefix, checking for repeated prefixes. */
3279 switch (add_prefix (current_templates
->start
->base_opcode
))
3284 expecting_string_instruction
= current_templates
->start
->name
;
3289 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3296 if (!current_templates
)
3298 /* Check if we should swap operand or force 32bit displacement in
3300 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3302 else if (mnem_p
- 4 == dot_p
3306 i
.disp32_encoding
= 1;
3311 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3314 if (!current_templates
)
3317 /* See if we can get a match by trimming off a suffix. */
3320 case WORD_MNEM_SUFFIX
:
3321 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3322 i
.suffix
= SHORT_MNEM_SUFFIX
;
3324 case BYTE_MNEM_SUFFIX
:
3325 case QWORD_MNEM_SUFFIX
:
3326 i
.suffix
= mnem_p
[-1];
3328 current_templates
= (const templates
*) hash_find (op_hash
,
3331 case SHORT_MNEM_SUFFIX
:
3332 case LONG_MNEM_SUFFIX
:
3335 i
.suffix
= mnem_p
[-1];
3337 current_templates
= (const templates
*) hash_find (op_hash
,
3346 if (intel_float_operand (mnemonic
) == 1)
3347 i
.suffix
= SHORT_MNEM_SUFFIX
;
3349 i
.suffix
= LONG_MNEM_SUFFIX
;
3351 current_templates
= (const templates
*) hash_find (op_hash
,
3356 if (!current_templates
)
3358 as_bad (_("no such instruction: `%s'"), token_start
);
3363 if (current_templates
->start
->opcode_modifier
.jump
3364 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3366 /* Check for a branch hint. We allow ",pt" and ",pn" for
3367 predict taken and predict not taken respectively.
3368 I'm not sure that branch hints actually do anything on loop
3369 and jcxz insns (JumpByte) for current Pentium4 chips. They
3370 may work in the future and it doesn't hurt to accept them
3372 if (l
[0] == ',' && l
[1] == 'p')
3376 if (!add_prefix (DS_PREFIX_OPCODE
))
3380 else if (l
[2] == 'n')
3382 if (!add_prefix (CS_PREFIX_OPCODE
))
3388 /* Any other comma loses. */
3391 as_bad (_("invalid character %s in mnemonic"),
3392 output_invalid (*l
));
3396 /* Check if instruction is supported on specified architecture. */
3398 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3400 supported
|= cpu_flags_match (t
);
3401 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3405 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3407 as_bad (flag_code
== CODE_64BIT
3408 ? _("`%s' is not supported in 64-bit mode")
3409 : _("`%s' is only supported in 64-bit mode"),
3410 current_templates
->start
->name
);
3413 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3415 as_bad (_("`%s' is not supported on `%s%s'"),
3416 current_templates
->start
->name
,
3417 cpu_arch_name
? cpu_arch_name
: default_arch
,
3418 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3423 if (!cpu_arch_flags
.bitfield
.cpui386
3424 && (flag_code
!= CODE_16BIT
))
3426 as_warn (_("use .code16 to ensure correct addressing mode"));
3429 /* Check for rep/repne without a string instruction. */
3430 if (expecting_string_instruction
)
3432 static templates override
;
3434 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3435 if (t
->opcode_modifier
.isstring
)
3437 if (t
>= current_templates
->end
)
3439 as_bad (_("expecting string instruction after `%s'"),
3440 expecting_string_instruction
);
3443 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3444 if (!t
->opcode_modifier
.isstring
)
3447 current_templates
= &override
;
3454 parse_operands (char *l
, const char *mnemonic
)
3458 /* 1 if operand is pending after ','. */
3459 unsigned int expecting_operand
= 0;
3461 /* Non-zero if operand parens not balanced. */
3462 unsigned int paren_not_balanced
;
3464 while (*l
!= END_OF_INSN
)
3466 /* Skip optional white space before operand. */
3467 if (is_space_char (*l
))
3469 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3471 as_bad (_("invalid character %s before operand %d"),
3472 output_invalid (*l
),
3476 token_start
= l
; /* after white space */
3477 paren_not_balanced
= 0;
3478 while (paren_not_balanced
|| *l
!= ',')
3480 if (*l
== END_OF_INSN
)
3482 if (paren_not_balanced
)
3485 as_bad (_("unbalanced parenthesis in operand %d."),
3488 as_bad (_("unbalanced brackets in operand %d."),
3493 break; /* we are done */
3495 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3497 as_bad (_("invalid character %s in operand %d"),
3498 output_invalid (*l
),
3505 ++paren_not_balanced
;
3507 --paren_not_balanced
;
3512 ++paren_not_balanced
;
3514 --paren_not_balanced
;
3518 if (l
!= token_start
)
3519 { /* Yes, we've read in another operand. */
3520 unsigned int operand_ok
;
3521 this_operand
= i
.operands
++;
3522 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3523 if (i
.operands
> MAX_OPERANDS
)
3525 as_bad (_("spurious operands; (%d operands/instruction max)"),
3529 /* Now parse operand adding info to 'i' as we go along. */
3530 END_STRING_AND_SAVE (l
);
3534 i386_intel_operand (token_start
,
3535 intel_float_operand (mnemonic
));
3537 operand_ok
= i386_att_operand (token_start
);
3539 RESTORE_END_STRING (l
);
3545 if (expecting_operand
)
3547 expecting_operand_after_comma
:
3548 as_bad (_("expecting operand after ','; got nothing"));
3553 as_bad (_("expecting operand before ','; got nothing"));
3558 /* Now *l must be either ',' or END_OF_INSN. */
3561 if (*++l
== END_OF_INSN
)
3563 /* Just skip it, if it's \n complain. */
3564 goto expecting_operand_after_comma
;
3566 expecting_operand
= 1;
3573 swap_2_operands (int xchg1
, int xchg2
)
3575 union i386_op temp_op
;
3576 i386_operand_type temp_type
;
3577 enum bfd_reloc_code_real temp_reloc
;
3579 temp_type
= i
.types
[xchg2
];
3580 i
.types
[xchg2
] = i
.types
[xchg1
];
3581 i
.types
[xchg1
] = temp_type
;
3582 temp_op
= i
.op
[xchg2
];
3583 i
.op
[xchg2
] = i
.op
[xchg1
];
3584 i
.op
[xchg1
] = temp_op
;
3585 temp_reloc
= i
.reloc
[xchg2
];
3586 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3587 i
.reloc
[xchg1
] = temp_reloc
;
3591 swap_operands (void)
3597 swap_2_operands (1, i
.operands
- 2);
3600 swap_2_operands (0, i
.operands
- 1);
3606 if (i
.mem_operands
== 2)
3608 const seg_entry
*temp_seg
;
3609 temp_seg
= i
.seg
[0];
3610 i
.seg
[0] = i
.seg
[1];
3611 i
.seg
[1] = temp_seg
;
3615 /* Try to ensure constant immediates are represented in the smallest
3620 char guess_suffix
= 0;
3624 guess_suffix
= i
.suffix
;
3625 else if (i
.reg_operands
)
3627 /* Figure out a suffix from the last register operand specified.
3628 We can't do this properly yet, ie. excluding InOutPortReg,
3629 but the following works for instructions with immediates.
3630 In any case, we can't set i.suffix yet. */
3631 for (op
= i
.operands
; --op
>= 0;)
3632 if (i
.types
[op
].bitfield
.reg8
)
3634 guess_suffix
= BYTE_MNEM_SUFFIX
;
3637 else if (i
.types
[op
].bitfield
.reg16
)
3639 guess_suffix
= WORD_MNEM_SUFFIX
;
3642 else if (i
.types
[op
].bitfield
.reg32
)
3644 guess_suffix
= LONG_MNEM_SUFFIX
;
3647 else if (i
.types
[op
].bitfield
.reg64
)
3649 guess_suffix
= QWORD_MNEM_SUFFIX
;
3653 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3654 guess_suffix
= WORD_MNEM_SUFFIX
;
3656 for (op
= i
.operands
; --op
>= 0;)
3657 if (operand_type_check (i
.types
[op
], imm
))
3659 switch (i
.op
[op
].imms
->X_op
)
3662 /* If a suffix is given, this operand may be shortened. */
3663 switch (guess_suffix
)
3665 case LONG_MNEM_SUFFIX
:
3666 i
.types
[op
].bitfield
.imm32
= 1;
3667 i
.types
[op
].bitfield
.imm64
= 1;
3669 case WORD_MNEM_SUFFIX
:
3670 i
.types
[op
].bitfield
.imm16
= 1;
3671 i
.types
[op
].bitfield
.imm32
= 1;
3672 i
.types
[op
].bitfield
.imm32s
= 1;
3673 i
.types
[op
].bitfield
.imm64
= 1;
3675 case BYTE_MNEM_SUFFIX
:
3676 i
.types
[op
].bitfield
.imm8
= 1;
3677 i
.types
[op
].bitfield
.imm8s
= 1;
3678 i
.types
[op
].bitfield
.imm16
= 1;
3679 i
.types
[op
].bitfield
.imm32
= 1;
3680 i
.types
[op
].bitfield
.imm32s
= 1;
3681 i
.types
[op
].bitfield
.imm64
= 1;
3685 /* If this operand is at most 16 bits, convert it
3686 to a signed 16 bit number before trying to see
3687 whether it will fit in an even smaller size.
3688 This allows a 16-bit operand such as $0xffe0 to
3689 be recognised as within Imm8S range. */
3690 if ((i
.types
[op
].bitfield
.imm16
)
3691 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3693 i
.op
[op
].imms
->X_add_number
=
3694 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3696 if ((i
.types
[op
].bitfield
.imm32
)
3697 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3700 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3701 ^ ((offsetT
) 1 << 31))
3702 - ((offsetT
) 1 << 31));
3705 = operand_type_or (i
.types
[op
],
3706 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3708 /* We must avoid matching of Imm32 templates when 64bit
3709 only immediate is available. */
3710 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3711 i
.types
[op
].bitfield
.imm32
= 0;
3718 /* Symbols and expressions. */
3720 /* Convert symbolic operand to proper sizes for matching, but don't
3721 prevent matching a set of insns that only supports sizes other
3722 than those matching the insn suffix. */
3724 i386_operand_type mask
, allowed
;
3725 const insn_template
*t
;
3727 operand_type_set (&mask
, 0);
3728 operand_type_set (&allowed
, 0);
3730 for (t
= current_templates
->start
;
3731 t
< current_templates
->end
;
3733 allowed
= operand_type_or (allowed
,
3734 t
->operand_types
[op
]);
3735 switch (guess_suffix
)
3737 case QWORD_MNEM_SUFFIX
:
3738 mask
.bitfield
.imm64
= 1;
3739 mask
.bitfield
.imm32s
= 1;
3741 case LONG_MNEM_SUFFIX
:
3742 mask
.bitfield
.imm32
= 1;
3744 case WORD_MNEM_SUFFIX
:
3745 mask
.bitfield
.imm16
= 1;
3747 case BYTE_MNEM_SUFFIX
:
3748 mask
.bitfield
.imm8
= 1;
3753 allowed
= operand_type_and (mask
, allowed
);
3754 if (!operand_type_all_zero (&allowed
))
3755 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3762 /* Try to use the smallest displacement type too. */
3764 optimize_disp (void)
3768 for (op
= i
.operands
; --op
>= 0;)
3769 if (operand_type_check (i
.types
[op
], disp
))
3771 if (i
.op
[op
].disps
->X_op
== O_constant
)
3773 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3775 if (i
.types
[op
].bitfield
.disp16
3776 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3778 /* If this operand is at most 16 bits, convert
3779 to a signed 16 bit number and don't use 64bit
3781 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3782 i
.types
[op
].bitfield
.disp64
= 0;
3784 if (i
.types
[op
].bitfield
.disp32
3785 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3787 /* If this operand is at most 32 bits, convert
3788 to a signed 32 bit number and don't use 64bit
3790 op_disp
&= (((offsetT
) 2 << 31) - 1);
3791 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3792 i
.types
[op
].bitfield
.disp64
= 0;
3794 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3796 i
.types
[op
].bitfield
.disp8
= 0;
3797 i
.types
[op
].bitfield
.disp16
= 0;
3798 i
.types
[op
].bitfield
.disp32
= 0;
3799 i
.types
[op
].bitfield
.disp32s
= 0;
3800 i
.types
[op
].bitfield
.disp64
= 0;
3804 else if (flag_code
== CODE_64BIT
)
3806 if (fits_in_signed_long (op_disp
))
3808 i
.types
[op
].bitfield
.disp64
= 0;
3809 i
.types
[op
].bitfield
.disp32s
= 1;
3811 if (i
.prefix
[ADDR_PREFIX
]
3812 && fits_in_unsigned_long (op_disp
))
3813 i
.types
[op
].bitfield
.disp32
= 1;
3815 if ((i
.types
[op
].bitfield
.disp32
3816 || i
.types
[op
].bitfield
.disp32s
3817 || i
.types
[op
].bitfield
.disp16
)
3818 && fits_in_signed_byte (op_disp
))
3819 i
.types
[op
].bitfield
.disp8
= 1;
3821 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3822 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3824 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3825 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3826 i
.types
[op
].bitfield
.disp8
= 0;
3827 i
.types
[op
].bitfield
.disp16
= 0;
3828 i
.types
[op
].bitfield
.disp32
= 0;
3829 i
.types
[op
].bitfield
.disp32s
= 0;
3830 i
.types
[op
].bitfield
.disp64
= 0;
3833 /* We only support 64bit displacement on constants. */
3834 i
.types
[op
].bitfield
.disp64
= 0;
3838 /* Check if operands are valid for the instruction. Update VEX
3842 VEX_check_operands (const insn_template
*t
)
3844 if (!t
->opcode_modifier
.vex
)
3847 /* Only check VEX_Imm4, which must be the first operand. */
3848 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3850 if (i
.op
[0].imms
->X_op
!= O_constant
3851 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3857 /* Turn off Imm8 so that update_imm won't complain. */
3858 i
.types
[0] = vec_imm4
;
3864 static const insn_template
*
3865 match_template (void)
3867 /* Points to template once we've found it. */
3868 const insn_template
*t
;
3869 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3870 i386_operand_type overlap4
;
3871 unsigned int found_reverse_match
;
3872 i386_opcode_modifier suffix_check
;
3873 i386_operand_type operand_types
[MAX_OPERANDS
];
3874 int addr_prefix_disp
;
3876 unsigned int found_cpu_match
;
3877 unsigned int check_register
;
3879 #if MAX_OPERANDS != 5
3880 # error "MAX_OPERANDS must be 5."
3883 found_reverse_match
= 0;
3884 addr_prefix_disp
= -1;
3886 memset (&suffix_check
, 0, sizeof (suffix_check
));
3887 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3888 suffix_check
.no_bsuf
= 1;
3889 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3890 suffix_check
.no_wsuf
= 1;
3891 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3892 suffix_check
.no_ssuf
= 1;
3893 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3894 suffix_check
.no_lsuf
= 1;
3895 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3896 suffix_check
.no_qsuf
= 1;
3897 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3898 suffix_check
.no_ldsuf
= 1;
3900 /* Must have right number of operands. */
3901 i
.error
= number_of_operands_mismatch
;
3903 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3905 addr_prefix_disp
= -1;
3907 if (i
.operands
!= t
->operands
)
3910 /* Check processor support. */
3911 i
.error
= unsupported
;
3912 found_cpu_match
= (cpu_flags_match (t
)
3913 == CPU_FLAGS_PERFECT_MATCH
);
3914 if (!found_cpu_match
)
3917 /* Check old gcc support. */
3918 i
.error
= old_gcc_only
;
3919 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3922 /* Check AT&T mnemonic. */
3923 i
.error
= unsupported_with_intel_mnemonic
;
3924 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3927 /* Check AT&T/Intel syntax. */
3928 i
.error
= unsupported_syntax
;
3929 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3930 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3933 /* Check the suffix, except for some instructions in intel mode. */
3934 i
.error
= invalid_instruction_suffix
;
3935 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3936 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3937 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3938 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3939 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3940 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3941 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3944 if (!operand_size_match (t
))
3947 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3948 operand_types
[j
] = t
->operand_types
[j
];
3950 /* In general, don't allow 64-bit operands in 32-bit mode. */
3951 if (i
.suffix
== QWORD_MNEM_SUFFIX
3952 && flag_code
!= CODE_64BIT
3954 ? (!t
->opcode_modifier
.ignoresize
3955 && !intel_float_operand (t
->name
))
3956 : intel_float_operand (t
->name
) != 2)
3957 && ((!operand_types
[0].bitfield
.regmmx
3958 && !operand_types
[0].bitfield
.regxmm
3959 && !operand_types
[0].bitfield
.regymm
)
3960 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3961 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3962 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3963 && (t
->base_opcode
!= 0x0fc7
3964 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3967 /* In general, don't allow 32-bit operands on pre-386. */
3968 else if (i
.suffix
== LONG_MNEM_SUFFIX
3969 && !cpu_arch_flags
.bitfield
.cpui386
3971 ? (!t
->opcode_modifier
.ignoresize
3972 && !intel_float_operand (t
->name
))
3973 : intel_float_operand (t
->name
) != 2)
3974 && ((!operand_types
[0].bitfield
.regmmx
3975 && !operand_types
[0].bitfield
.regxmm
)
3976 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3977 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3980 /* Do not verify operands when there are none. */
3984 /* We've found a match; break out of loop. */
3988 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3989 into Disp32/Disp16/Disp32 operand. */
3990 if (i
.prefix
[ADDR_PREFIX
] != 0)
3992 /* There should be only one Disp operand. */
3996 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3998 if (operand_types
[j
].bitfield
.disp16
)
4000 addr_prefix_disp
= j
;
4001 operand_types
[j
].bitfield
.disp32
= 1;
4002 operand_types
[j
].bitfield
.disp16
= 0;
4008 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4010 if (operand_types
[j
].bitfield
.disp32
)
4012 addr_prefix_disp
= j
;
4013 operand_types
[j
].bitfield
.disp32
= 0;
4014 operand_types
[j
].bitfield
.disp16
= 1;
4020 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4022 if (operand_types
[j
].bitfield
.disp64
)
4024 addr_prefix_disp
= j
;
4025 operand_types
[j
].bitfield
.disp64
= 0;
4026 operand_types
[j
].bitfield
.disp32
= 1;
4034 /* We check register size if needed. */
4035 check_register
= t
->opcode_modifier
.checkregsize
;
4036 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4037 switch (t
->operands
)
4040 if (!operand_type_match (overlap0
, i
.types
[0]))
4044 /* xchg %eax, %eax is a special case. It is an aliase for nop
4045 only in 32bit mode and we can use opcode 0x90. In 64bit
4046 mode, we can't use 0x90 for xchg %eax, %eax since it should
4047 zero-extend %eax to %rax. */
4048 if (flag_code
== CODE_64BIT
4049 && t
->base_opcode
== 0x90
4050 && operand_type_equal (&i
.types
[0], &acc32
)
4051 && operand_type_equal (&i
.types
[1], &acc32
))
4055 /* If we swap operand in encoding, we either match
4056 the next one or reverse direction of operands. */
4057 if (t
->opcode_modifier
.s
)
4059 else if (t
->opcode_modifier
.d
)
4064 /* If we swap operand in encoding, we match the next one. */
4065 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4069 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4070 if (!operand_type_match (overlap0
, i
.types
[0])
4071 || !operand_type_match (overlap1
, i
.types
[1])
4073 && !operand_type_register_match (overlap0
, i
.types
[0],
4075 overlap1
, i
.types
[1],
4078 /* Check if other direction is valid ... */
4079 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4083 /* Try reversing direction of operands. */
4084 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4085 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4086 if (!operand_type_match (overlap0
, i
.types
[0])
4087 || !operand_type_match (overlap1
, i
.types
[1])
4089 && !operand_type_register_match (overlap0
,
4096 /* Does not match either direction. */
4099 /* found_reverse_match holds which of D or FloatDR
4101 if (t
->opcode_modifier
.d
)
4102 found_reverse_match
= Opcode_D
;
4103 else if (t
->opcode_modifier
.floatd
)
4104 found_reverse_match
= Opcode_FloatD
;
4106 found_reverse_match
= 0;
4107 if (t
->opcode_modifier
.floatr
)
4108 found_reverse_match
|= Opcode_FloatR
;
4112 /* Found a forward 2 operand match here. */
4113 switch (t
->operands
)
4116 overlap4
= operand_type_and (i
.types
[4],
4119 overlap3
= operand_type_and (i
.types
[3],
4122 overlap2
= operand_type_and (i
.types
[2],
4127 switch (t
->operands
)
4130 if (!operand_type_match (overlap4
, i
.types
[4])
4131 || !operand_type_register_match (overlap3
,
4139 if (!operand_type_match (overlap3
, i
.types
[3])
4141 && !operand_type_register_match (overlap2
,
4149 /* Here we make use of the fact that there are no
4150 reverse match 3 operand instructions, and all 3
4151 operand instructions only need to be checked for
4152 register consistency between operands 2 and 3. */
4153 if (!operand_type_match (overlap2
, i
.types
[2])
4155 && !operand_type_register_match (overlap1
,
4165 /* Found either forward/reverse 2, 3 or 4 operand match here:
4166 slip through to break. */
4168 if (!found_cpu_match
)
4170 found_reverse_match
= 0;
4174 /* Check if VEX operands are valid. */
4175 if (VEX_check_operands (t
))
4178 /* We've found a match; break out of loop. */
4182 if (t
== current_templates
->end
)
4184 /* We found no match. */
4185 const char *err_msg
;
4190 case operand_size_mismatch
:
4191 err_msg
= _("operand size mismatch");
4193 case operand_type_mismatch
:
4194 err_msg
= _("operand type mismatch");
4196 case register_type_mismatch
:
4197 err_msg
= _("register type mismatch");
4199 case number_of_operands_mismatch
:
4200 err_msg
= _("number of operands mismatch");
4202 case invalid_instruction_suffix
:
4203 err_msg
= _("invalid instruction suffix");
4206 err_msg
= _("Imm4 isn't the first operand");
4209 err_msg
= _("only supported with old gcc");
4211 case unsupported_with_intel_mnemonic
:
4212 err_msg
= _("unsupported with Intel mnemonic");
4214 case unsupported_syntax
:
4215 err_msg
= _("unsupported syntax");
4218 err_msg
= _("unsupported");
4221 as_bad (_("%s for `%s'"), err_msg
,
4222 current_templates
->start
->name
);
4226 if (!quiet_warnings
)
4229 && (i
.types
[0].bitfield
.jumpabsolute
4230 != operand_types
[0].bitfield
.jumpabsolute
))
4232 as_warn (_("indirect %s without `*'"), t
->name
);
4235 if (t
->opcode_modifier
.isprefix
4236 && t
->opcode_modifier
.ignoresize
)
4238 /* Warn them that a data or address size prefix doesn't
4239 affect assembly of the next line of code. */
4240 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4244 /* Copy the template we found. */
4247 if (addr_prefix_disp
!= -1)
4248 i
.tm
.operand_types
[addr_prefix_disp
]
4249 = operand_types
[addr_prefix_disp
];
4251 if (found_reverse_match
)
4253 /* If we found a reverse match we must alter the opcode
4254 direction bit. found_reverse_match holds bits to change
4255 (different for int & float insns). */
4257 i
.tm
.base_opcode
^= found_reverse_match
;
4259 i
.tm
.operand_types
[0] = operand_types
[1];
4260 i
.tm
.operand_types
[1] = operand_types
[0];
4269 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4270 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4272 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4274 as_bad (_("`%s' operand %d must use `%ses' segment"),
4280 /* There's only ever one segment override allowed per instruction.
4281 This instruction possibly has a legal segment override on the
4282 second operand, so copy the segment to where non-string
4283 instructions store it, allowing common code. */
4284 i
.seg
[0] = i
.seg
[1];
4286 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4288 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4290 as_bad (_("`%s' operand %d must use `%ses' segment"),
4301 process_suffix (void)
4303 /* If matched instruction specifies an explicit instruction mnemonic
4305 if (i
.tm
.opcode_modifier
.size16
)
4306 i
.suffix
= WORD_MNEM_SUFFIX
;
4307 else if (i
.tm
.opcode_modifier
.size32
)
4308 i
.suffix
= LONG_MNEM_SUFFIX
;
4309 else if (i
.tm
.opcode_modifier
.size64
)
4310 i
.suffix
= QWORD_MNEM_SUFFIX
;
4311 else if (i
.reg_operands
)
4313 /* If there's no instruction mnemonic suffix we try to invent one
4314 based on register operands. */
4317 /* We take i.suffix from the last register operand specified,
4318 Destination register type is more significant than source
4319 register type. crc32 in SSE4.2 prefers source register
4321 if (i
.tm
.base_opcode
== 0xf20f38f1)
4323 if (i
.types
[0].bitfield
.reg16
)
4324 i
.suffix
= WORD_MNEM_SUFFIX
;
4325 else if (i
.types
[0].bitfield
.reg32
)
4326 i
.suffix
= LONG_MNEM_SUFFIX
;
4327 else if (i
.types
[0].bitfield
.reg64
)
4328 i
.suffix
= QWORD_MNEM_SUFFIX
;
4330 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4332 if (i
.types
[0].bitfield
.reg8
)
4333 i
.suffix
= BYTE_MNEM_SUFFIX
;
4340 if (i
.tm
.base_opcode
== 0xf20f38f1
4341 || i
.tm
.base_opcode
== 0xf20f38f0)
4343 /* We have to know the operand size for crc32. */
4344 as_bad (_("ambiguous memory operand size for `%s`"),
4349 for (op
= i
.operands
; --op
>= 0;)
4350 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4352 if (i
.types
[op
].bitfield
.reg8
)
4354 i
.suffix
= BYTE_MNEM_SUFFIX
;
4357 else if (i
.types
[op
].bitfield
.reg16
)
4359 i
.suffix
= WORD_MNEM_SUFFIX
;
4362 else if (i
.types
[op
].bitfield
.reg32
)
4364 i
.suffix
= LONG_MNEM_SUFFIX
;
4367 else if (i
.types
[op
].bitfield
.reg64
)
4369 i
.suffix
= QWORD_MNEM_SUFFIX
;
4375 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4378 && i
.tm
.opcode_modifier
.ignoresize
4379 && i
.tm
.opcode_modifier
.no_bsuf
)
4381 else if (!check_byte_reg ())
4384 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4387 && i
.tm
.opcode_modifier
.ignoresize
4388 && i
.tm
.opcode_modifier
.no_lsuf
)
4390 else if (!check_long_reg ())
4393 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4396 && i
.tm
.opcode_modifier
.ignoresize
4397 && i
.tm
.opcode_modifier
.no_qsuf
)
4399 else if (!check_qword_reg ())
4402 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4405 && i
.tm
.opcode_modifier
.ignoresize
4406 && i
.tm
.opcode_modifier
.no_wsuf
)
4408 else if (!check_word_reg ())
4411 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4412 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4414 /* Skip if the instruction has x/y suffix. match_template
4415 should check if it is a valid suffix. */
4417 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4418 /* Do nothing if the instruction is going to ignore the prefix. */
4423 else if (i
.tm
.opcode_modifier
.defaultsize
4425 /* exclude fldenv/frstor/fsave/fstenv */
4426 && i
.tm
.opcode_modifier
.no_ssuf
)
4428 i
.suffix
= stackop_size
;
4430 else if (intel_syntax
4432 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4433 || i
.tm
.opcode_modifier
.jumpbyte
4434 || i
.tm
.opcode_modifier
.jumpintersegment
4435 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4436 && i
.tm
.extension_opcode
<= 3)))
4441 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4443 i
.suffix
= QWORD_MNEM_SUFFIX
;
4447 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4448 i
.suffix
= LONG_MNEM_SUFFIX
;
4451 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4452 i
.suffix
= WORD_MNEM_SUFFIX
;
4461 if (i
.tm
.opcode_modifier
.w
)
4463 as_bad (_("no instruction mnemonic suffix given and "
4464 "no register operands; can't size instruction"));
4470 unsigned int suffixes
;
4472 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4473 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4475 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4477 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4479 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4481 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4484 /* There are more than suffix matches. */
4485 if (i
.tm
.opcode_modifier
.w
4486 || ((suffixes
& (suffixes
- 1))
4487 && !i
.tm
.opcode_modifier
.defaultsize
4488 && !i
.tm
.opcode_modifier
.ignoresize
))
4490 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4496 /* Change the opcode based on the operand size given by i.suffix;
4497 We don't need to change things for byte insns. */
4500 && i
.suffix
!= BYTE_MNEM_SUFFIX
4501 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4502 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4504 /* It's not a byte, select word/dword operation. */
4505 if (i
.tm
.opcode_modifier
.w
)
4507 if (i
.tm
.opcode_modifier
.shortform
)
4508 i
.tm
.base_opcode
|= 8;
4510 i
.tm
.base_opcode
|= 1;
4513 /* Now select between word & dword operations via the operand
4514 size prefix, except for instructions that will ignore this
4516 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4518 /* The address size override prefix changes the size of the
4520 if ((flag_code
== CODE_32BIT
4521 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4522 || (flag_code
!= CODE_32BIT
4523 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4524 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4527 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4528 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4529 && !i
.tm
.opcode_modifier
.ignoresize
4530 && !i
.tm
.opcode_modifier
.floatmf
4531 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4532 || (flag_code
== CODE_64BIT
4533 && i
.tm
.opcode_modifier
.jumpbyte
)))
4535 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4537 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4538 prefix
= ADDR_PREFIX_OPCODE
;
4540 if (!add_prefix (prefix
))
4544 /* Set mode64 for an operand. */
4545 if (i
.suffix
== QWORD_MNEM_SUFFIX
4546 && flag_code
== CODE_64BIT
4547 && !i
.tm
.opcode_modifier
.norex64
)
4549 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4550 need rex64. cmpxchg8b is also a special case. */
4551 if (! (i
.operands
== 2
4552 && i
.tm
.base_opcode
== 0x90
4553 && i
.tm
.extension_opcode
== None
4554 && operand_type_equal (&i
.types
[0], &acc64
)
4555 && operand_type_equal (&i
.types
[1], &acc64
))
4556 && ! (i
.operands
== 1
4557 && i
.tm
.base_opcode
== 0xfc7
4558 && i
.tm
.extension_opcode
== 1
4559 && !operand_type_check (i
.types
[0], reg
)
4560 && operand_type_check (i
.types
[0], anymem
)))
4564 /* Size floating point instruction. */
4565 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4566 if (i
.tm
.opcode_modifier
.floatmf
)
4567 i
.tm
.base_opcode
^= 4;
4574 check_byte_reg (void)
4578 for (op
= i
.operands
; --op
>= 0;)
4580 /* If this is an eight bit register, it's OK. If it's the 16 or
4581 32 bit version of an eight bit register, we will just use the
4582 low portion, and that's OK too. */
4583 if (i
.types
[op
].bitfield
.reg8
)
4586 /* crc32 doesn't generate this warning. */
4587 if (i
.tm
.base_opcode
== 0xf20f38f0)
4590 if ((i
.types
[op
].bitfield
.reg16
4591 || i
.types
[op
].bitfield
.reg32
4592 || i
.types
[op
].bitfield
.reg64
)
4593 && i
.op
[op
].regs
->reg_num
< 4)
4595 /* Prohibit these changes in the 64bit mode, since the
4596 lowering is more complicated. */
4597 if (flag_code
== CODE_64BIT
4598 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4600 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4601 register_prefix
, i
.op
[op
].regs
->reg_name
,
4605 #if REGISTER_WARNINGS
4607 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4608 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4610 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4611 ? REGNAM_AL
- REGNAM_AX
4612 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4614 i
.op
[op
].regs
->reg_name
,
4619 /* Any other register is bad. */
4620 if (i
.types
[op
].bitfield
.reg16
4621 || i
.types
[op
].bitfield
.reg32
4622 || i
.types
[op
].bitfield
.reg64
4623 || i
.types
[op
].bitfield
.regmmx
4624 || i
.types
[op
].bitfield
.regxmm
4625 || i
.types
[op
].bitfield
.regymm
4626 || i
.types
[op
].bitfield
.sreg2
4627 || i
.types
[op
].bitfield
.sreg3
4628 || i
.types
[op
].bitfield
.control
4629 || i
.types
[op
].bitfield
.debug
4630 || i
.types
[op
].bitfield
.test
4631 || i
.types
[op
].bitfield
.floatreg
4632 || i
.types
[op
].bitfield
.floatacc
)
4634 as_bad (_("`%s%s' not allowed with `%s%c'"),
4636 i
.op
[op
].regs
->reg_name
,
4646 check_long_reg (void)
4650 for (op
= i
.operands
; --op
>= 0;)
4651 /* Reject eight bit registers, except where the template requires
4652 them. (eg. movzb) */
4653 if (i
.types
[op
].bitfield
.reg8
4654 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4655 || i
.tm
.operand_types
[op
].bitfield
.reg32
4656 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4658 as_bad (_("`%s%s' not allowed with `%s%c'"),
4660 i
.op
[op
].regs
->reg_name
,
4665 /* Warn if the e prefix on a general reg is missing. */
4666 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4667 && i
.types
[op
].bitfield
.reg16
4668 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4669 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4671 /* Prohibit these changes in the 64bit mode, since the
4672 lowering is more complicated. */
4673 if (flag_code
== CODE_64BIT
)
4675 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4676 register_prefix
, i
.op
[op
].regs
->reg_name
,
4680 #if REGISTER_WARNINGS
4682 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4684 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4686 i
.op
[op
].regs
->reg_name
,
4690 /* Warn if the r prefix on a general reg is missing. */
4691 else if (i
.types
[op
].bitfield
.reg64
4692 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4693 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4696 && i
.tm
.opcode_modifier
.toqword
4697 && !i
.types
[0].bitfield
.regxmm
)
4699 /* Convert to QWORD. We want REX byte. */
4700 i
.suffix
= QWORD_MNEM_SUFFIX
;
4704 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4705 register_prefix
, i
.op
[op
].regs
->reg_name
,
4714 check_qword_reg (void)
4718 for (op
= i
.operands
; --op
>= 0; )
4719 /* Reject eight bit registers, except where the template requires
4720 them. (eg. movzb) */
4721 if (i
.types
[op
].bitfield
.reg8
4722 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4723 || i
.tm
.operand_types
[op
].bitfield
.reg32
4724 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4726 as_bad (_("`%s%s' not allowed with `%s%c'"),
4728 i
.op
[op
].regs
->reg_name
,
4733 /* Warn if the e prefix on a general reg is missing. */
4734 else if ((i
.types
[op
].bitfield
.reg16
4735 || i
.types
[op
].bitfield
.reg32
)
4736 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4737 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4739 /* Prohibit these changes in the 64bit mode, since the
4740 lowering is more complicated. */
4742 && i
.tm
.opcode_modifier
.todword
4743 && !i
.types
[0].bitfield
.regxmm
)
4745 /* Convert to DWORD. We don't want REX byte. */
4746 i
.suffix
= LONG_MNEM_SUFFIX
;
4750 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4751 register_prefix
, i
.op
[op
].regs
->reg_name
,
4760 check_word_reg (void)
4763 for (op
= i
.operands
; --op
>= 0;)
4764 /* Reject eight bit registers, except where the template requires
4765 them. (eg. movzb) */
4766 if (i
.types
[op
].bitfield
.reg8
4767 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4768 || i
.tm
.operand_types
[op
].bitfield
.reg32
4769 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4771 as_bad (_("`%s%s' not allowed with `%s%c'"),
4773 i
.op
[op
].regs
->reg_name
,
4778 /* Warn if the e prefix on a general reg is present. */
4779 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4780 && i
.types
[op
].bitfield
.reg32
4781 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4782 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4784 /* Prohibit these changes in the 64bit mode, since the
4785 lowering is more complicated. */
4786 if (flag_code
== CODE_64BIT
)
4788 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4789 register_prefix
, i
.op
[op
].regs
->reg_name
,
4794 #if REGISTER_WARNINGS
4795 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4797 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4799 i
.op
[op
].regs
->reg_name
,
4807 update_imm (unsigned int j
)
4809 i386_operand_type overlap
= i
.types
[j
];
4810 if ((overlap
.bitfield
.imm8
4811 || overlap
.bitfield
.imm8s
4812 || overlap
.bitfield
.imm16
4813 || overlap
.bitfield
.imm32
4814 || overlap
.bitfield
.imm32s
4815 || overlap
.bitfield
.imm64
)
4816 && !operand_type_equal (&overlap
, &imm8
)
4817 && !operand_type_equal (&overlap
, &imm8s
)
4818 && !operand_type_equal (&overlap
, &imm16
)
4819 && !operand_type_equal (&overlap
, &imm32
)
4820 && !operand_type_equal (&overlap
, &imm32s
)
4821 && !operand_type_equal (&overlap
, &imm64
))
4825 i386_operand_type temp
;
4827 operand_type_set (&temp
, 0);
4828 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4830 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4831 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4833 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4834 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4835 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4837 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4838 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4841 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4844 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4845 || operand_type_equal (&overlap
, &imm16_32
)
4846 || operand_type_equal (&overlap
, &imm16_32s
))
4848 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4853 if (!operand_type_equal (&overlap
, &imm8
)
4854 && !operand_type_equal (&overlap
, &imm8s
)
4855 && !operand_type_equal (&overlap
, &imm16
)
4856 && !operand_type_equal (&overlap
, &imm32
)
4857 && !operand_type_equal (&overlap
, &imm32s
)
4858 && !operand_type_equal (&overlap
, &imm64
))
4860 as_bad (_("no instruction mnemonic suffix given; "
4861 "can't determine immediate size"));
4865 i
.types
[j
] = overlap
;
4875 /* Update the first 2 immediate operands. */
4876 n
= i
.operands
> 2 ? 2 : i
.operands
;
4879 for (j
= 0; j
< n
; j
++)
4880 if (update_imm (j
) == 0)
4883 /* The 3rd operand can't be immediate operand. */
4884 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4891 bad_implicit_operand (int xmm
)
4893 const char *ireg
= xmm
? "xmm0" : "ymm0";
4896 as_bad (_("the last operand of `%s' must be `%s%s'"),
4897 i
.tm
.name
, register_prefix
, ireg
);
4899 as_bad (_("the first operand of `%s' must be `%s%s'"),
4900 i
.tm
.name
, register_prefix
, ireg
);
4905 process_operands (void)
4907 /* Default segment register this instruction will use for memory
4908 accesses. 0 means unknown. This is only for optimizing out
4909 unnecessary segment overrides. */
4910 const seg_entry
*default_seg
= 0;
4912 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4914 unsigned int dupl
= i
.operands
;
4915 unsigned int dest
= dupl
- 1;
4918 /* The destination must be an xmm register. */
4919 gas_assert (i
.reg_operands
4920 && MAX_OPERANDS
> dupl
4921 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4923 if (i
.tm
.opcode_modifier
.firstxmm0
)
4925 /* The first operand is implicit and must be xmm0. */
4926 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4927 if (i
.op
[0].regs
->reg_num
!= 0)
4928 return bad_implicit_operand (1);
4930 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4932 /* Keep xmm0 for instructions with VEX prefix and 3
4938 /* We remove the first xmm0 and keep the number of
4939 operands unchanged, which in fact duplicates the
4941 for (j
= 1; j
< i
.operands
; j
++)
4943 i
.op
[j
- 1] = i
.op
[j
];
4944 i
.types
[j
- 1] = i
.types
[j
];
4945 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4949 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4951 gas_assert ((MAX_OPERANDS
- 1) > dupl
4952 && (i
.tm
.opcode_modifier
.vexsources
4955 /* Add the implicit xmm0 for instructions with VEX prefix
4957 for (j
= i
.operands
; j
> 0; j
--)
4959 i
.op
[j
] = i
.op
[j
- 1];
4960 i
.types
[j
] = i
.types
[j
- 1];
4961 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4964 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4965 i
.types
[0] = regxmm
;
4966 i
.tm
.operand_types
[0] = regxmm
;
4969 i
.reg_operands
+= 2;
4974 i
.op
[dupl
] = i
.op
[dest
];
4975 i
.types
[dupl
] = i
.types
[dest
];
4976 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4985 i
.op
[dupl
] = i
.op
[dest
];
4986 i
.types
[dupl
] = i
.types
[dest
];
4987 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4990 if (i
.tm
.opcode_modifier
.immext
)
4993 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4997 /* The first operand is implicit and must be xmm0/ymm0. */
4998 gas_assert (i
.reg_operands
4999 && (operand_type_equal (&i
.types
[0], ®xmm
)
5000 || operand_type_equal (&i
.types
[0], ®ymm
)));
5001 if (i
.op
[0].regs
->reg_num
!= 0)
5002 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5004 for (j
= 1; j
< i
.operands
; j
++)
5006 i
.op
[j
- 1] = i
.op
[j
];
5007 i
.types
[j
- 1] = i
.types
[j
];
5009 /* We need to adjust fields in i.tm since they are used by
5010 build_modrm_byte. */
5011 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5018 else if (i
.tm
.opcode_modifier
.regkludge
)
5020 /* The imul $imm, %reg instruction is converted into
5021 imul $imm, %reg, %reg, and the clr %reg instruction
5022 is converted into xor %reg, %reg. */
5024 unsigned int first_reg_op
;
5026 if (operand_type_check (i
.types
[0], reg
))
5030 /* Pretend we saw the extra register operand. */
5031 gas_assert (i
.reg_operands
== 1
5032 && i
.op
[first_reg_op
+ 1].regs
== 0);
5033 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5034 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5039 if (i
.tm
.opcode_modifier
.shortform
)
5041 if (i
.types
[0].bitfield
.sreg2
5042 || i
.types
[0].bitfield
.sreg3
)
5044 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5045 && i
.op
[0].regs
->reg_num
== 1)
5047 as_bad (_("you can't `pop %scs'"), register_prefix
);
5050 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5051 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5056 /* The register or float register operand is in operand
5060 if (i
.types
[0].bitfield
.floatreg
5061 || operand_type_check (i
.types
[0], reg
))
5065 /* Register goes in low 3 bits of opcode. */
5066 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5067 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5069 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5071 /* Warn about some common errors, but press on regardless.
5072 The first case can be generated by gcc (<= 2.8.1). */
5073 if (i
.operands
== 2)
5075 /* Reversed arguments on faddp, fsubp, etc. */
5076 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5077 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5078 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5082 /* Extraneous `l' suffix on fp insn. */
5083 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5084 register_prefix
, i
.op
[0].regs
->reg_name
);
5089 else if (i
.tm
.opcode_modifier
.modrm
)
5091 /* The opcode is completed (modulo i.tm.extension_opcode which
5092 must be put into the modrm byte). Now, we make the modrm and
5093 index base bytes based on all the info we've collected. */
5095 default_seg
= build_modrm_byte ();
5097 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5101 else if (i
.tm
.opcode_modifier
.isstring
)
5103 /* For the string instructions that allow a segment override
5104 on one of their operands, the default segment is ds. */
5108 if (i
.tm
.base_opcode
== 0x8d /* lea */
5111 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5113 /* If a segment was explicitly specified, and the specified segment
5114 is not the default, use an opcode prefix to select it. If we
5115 never figured out what the default segment is, then default_seg
5116 will be zero at this point, and the specified segment prefix will
5118 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5120 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5126 static const seg_entry
*
5127 build_modrm_byte (void)
5129 const seg_entry
*default_seg
= 0;
5130 unsigned int source
, dest
;
5133 /* The first operand of instructions with VEX prefix and 3 sources
5134 must be VEX_Imm4. */
5135 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5138 unsigned int nds
, reg_slot
;
5141 if (i
.tm
.opcode_modifier
.veximmext
5142 && i
.tm
.opcode_modifier
.immext
)
5144 dest
= i
.operands
- 2;
5145 gas_assert (dest
== 3);
5148 dest
= i
.operands
- 1;
5151 /* There are 2 kinds of instructions:
5152 1. 5 operands: 4 register operands or 3 register operands
5153 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5154 VexW0 or VexW1. The destination must be either XMM or YMM
5156 2. 4 operands: 4 register operands or 3 register operands
5157 plus 1 memory operand, VexXDS, and VexImmExt */
5158 gas_assert ((i
.reg_operands
== 4
5159 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5160 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5161 && (i
.tm
.opcode_modifier
.veximmext
5162 || (i
.imm_operands
== 1
5163 && i
.types
[0].bitfield
.vec_imm4
5164 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5165 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5166 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5167 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5169 if (i
.imm_operands
== 0)
5171 /* When there is no immediate operand, generate an 8bit
5172 immediate operand to encode the first operand. */
5173 exp
= &im_expressions
[i
.imm_operands
++];
5174 i
.op
[i
.operands
].imms
= exp
;
5175 i
.types
[i
.operands
] = imm8
;
5177 /* If VexW1 is set, the first operand is the source and
5178 the second operand is encoded in the immediate operand. */
5179 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5190 /* FMA swaps REG and NDS. */
5191 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5199 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5201 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5203 exp
->X_op
= O_constant
;
5205 = ((i
.op
[reg_slot
].regs
->reg_num
5206 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5211 unsigned int imm_slot
;
5213 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5215 /* If VexW0 is set, the third operand is the source and
5216 the second operand is encoded in the immediate
5223 /* VexW1 is set, the second operand is the source and
5224 the third operand is encoded in the immediate
5230 if (i
.tm
.opcode_modifier
.immext
)
5232 /* When ImmExt is set, the immdiate byte is the last
5234 imm_slot
= i
.operands
- 1;
5242 /* Turn on Imm8 so that output_imm will generate it. */
5243 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5246 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5248 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5250 i
.op
[imm_slot
].imms
->X_add_number
5251 |= ((i
.op
[reg_slot
].regs
->reg_num
5252 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5256 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5257 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5259 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5264 /* i.reg_operands MUST be the number of real register operands;
5265 implicit registers do not count. If there are 3 register
5266 operands, it must be a instruction with VexNDS. For a
5267 instruction with VexNDD, the destination register is encoded
5268 in VEX prefix. If there are 4 register operands, it must be
5269 a instruction with VEX prefix and 3 sources. */
5270 if (i
.mem_operands
== 0
5271 && ((i
.reg_operands
== 2
5272 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5273 || (i
.reg_operands
== 3
5274 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5275 || (i
.reg_operands
== 4 && vex_3_sources
)))
5283 /* When there are 3 operands, one of them may be immediate,
5284 which may be the first or the last operand. Otherwise,
5285 the first operand must be shift count register (cl) or it
5286 is an instruction with VexNDS. */
5287 gas_assert (i
.imm_operands
== 1
5288 || (i
.imm_operands
== 0
5289 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5290 || i
.types
[0].bitfield
.shiftcount
)));
5291 if (operand_type_check (i
.types
[0], imm
)
5292 || i
.types
[0].bitfield
.shiftcount
)
5298 /* When there are 4 operands, the first two must be 8bit
5299 immediate operands. The source operand will be the 3rd
5302 For instructions with VexNDS, if the first operand
5303 an imm8, the source operand is the 2nd one. If the last
5304 operand is imm8, the source operand is the first one. */
5305 gas_assert ((i
.imm_operands
== 2
5306 && i
.types
[0].bitfield
.imm8
5307 && i
.types
[1].bitfield
.imm8
)
5308 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5309 && i
.imm_operands
== 1
5310 && (i
.types
[0].bitfield
.imm8
5311 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5312 if (i
.imm_operands
== 2)
5316 if (i
.types
[0].bitfield
.imm8
)
5332 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5334 /* For instructions with VexNDS, the register-only
5335 source operand must be 32/64bit integer, XMM or
5336 YMM register. It is encoded in VEX prefix. We
5337 need to clear RegMem bit before calling
5338 operand_type_equal. */
5340 i386_operand_type op
;
5343 /* Check register-only source operand when two source
5344 operands are swapped. */
5345 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5346 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5354 op
= i
.tm
.operand_types
[vvvv
];
5355 op
.bitfield
.regmem
= 0;
5356 if ((dest
+ 1) >= i
.operands
5357 || (op
.bitfield
.reg32
!= 1
5358 && !op
.bitfield
.reg64
!= 1
5359 && !operand_type_equal (&op
, ®xmm
)
5360 && !operand_type_equal (&op
, ®ymm
)))
5362 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5368 /* One of the register operands will be encoded in the i.tm.reg
5369 field, the other in the combined i.tm.mode and i.tm.regmem
5370 fields. If no form of this instruction supports a memory
5371 destination operand, then we assume the source operand may
5372 sometimes be a memory operand and so we need to store the
5373 destination in the i.rm.reg field. */
5374 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5375 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5377 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5378 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5379 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5381 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5386 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5387 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5388 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5390 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5393 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5395 if (!i
.types
[0].bitfield
.control
5396 && !i
.types
[1].bitfield
.control
)
5398 i
.rex
&= ~(REX_R
| REX_B
);
5399 add_prefix (LOCK_PREFIX_OPCODE
);
5403 { /* If it's not 2 reg operands... */
5408 unsigned int fake_zero_displacement
= 0;
5411 for (op
= 0; op
< i
.operands
; op
++)
5412 if (operand_type_check (i
.types
[op
], anymem
))
5414 gas_assert (op
< i
.operands
);
5418 if (i
.base_reg
== 0)
5421 if (!i
.disp_operands
)
5422 fake_zero_displacement
= 1;
5423 if (i
.index_reg
== 0)
5425 /* Operand is just <disp> */
5426 if (flag_code
== CODE_64BIT
)
5428 /* 64bit mode overwrites the 32bit absolute
5429 addressing by RIP relative addressing and
5430 absolute addressing is encoded by one of the
5431 redundant SIB forms. */
5432 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5433 i
.sib
.base
= NO_BASE_REGISTER
;
5434 i
.sib
.index
= NO_INDEX_REGISTER
;
5435 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5436 ? disp32s
: disp32
);
5438 else if ((flag_code
== CODE_16BIT
)
5439 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5441 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5442 i
.types
[op
] = disp16
;
5446 i
.rm
.regmem
= NO_BASE_REGISTER
;
5447 i
.types
[op
] = disp32
;
5450 else /* !i.base_reg && i.index_reg */
5452 if (i
.index_reg
->reg_num
== RegEiz
5453 || i
.index_reg
->reg_num
== RegRiz
)
5454 i
.sib
.index
= NO_INDEX_REGISTER
;
5456 i
.sib
.index
= i
.index_reg
->reg_num
;
5457 i
.sib
.base
= NO_BASE_REGISTER
;
5458 i
.sib
.scale
= i
.log2_scale_factor
;
5459 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5460 i
.types
[op
].bitfield
.disp8
= 0;
5461 i
.types
[op
].bitfield
.disp16
= 0;
5462 i
.types
[op
].bitfield
.disp64
= 0;
5463 if (flag_code
!= CODE_64BIT
)
5465 /* Must be 32 bit */
5466 i
.types
[op
].bitfield
.disp32
= 1;
5467 i
.types
[op
].bitfield
.disp32s
= 0;
5471 i
.types
[op
].bitfield
.disp32
= 0;
5472 i
.types
[op
].bitfield
.disp32s
= 1;
5474 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5478 /* RIP addressing for 64bit mode. */
5479 else if (i
.base_reg
->reg_num
== RegRip
||
5480 i
.base_reg
->reg_num
== RegEip
)
5482 i
.rm
.regmem
= NO_BASE_REGISTER
;
5483 i
.types
[op
].bitfield
.disp8
= 0;
5484 i
.types
[op
].bitfield
.disp16
= 0;
5485 i
.types
[op
].bitfield
.disp32
= 0;
5486 i
.types
[op
].bitfield
.disp32s
= 1;
5487 i
.types
[op
].bitfield
.disp64
= 0;
5488 i
.flags
[op
] |= Operand_PCrel
;
5489 if (! i
.disp_operands
)
5490 fake_zero_displacement
= 1;
5492 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5494 switch (i
.base_reg
->reg_num
)
5497 if (i
.index_reg
== 0)
5499 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5500 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5504 if (i
.index_reg
== 0)
5507 if (operand_type_check (i
.types
[op
], disp
) == 0)
5509 /* fake (%bp) into 0(%bp) */
5510 i
.types
[op
].bitfield
.disp8
= 1;
5511 fake_zero_displacement
= 1;
5514 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5515 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5517 default: /* (%si) -> 4 or (%di) -> 5 */
5518 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5520 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5522 else /* i.base_reg and 32/64 bit mode */
5524 if (flag_code
== CODE_64BIT
5525 && operand_type_check (i
.types
[op
], disp
))
5527 i386_operand_type temp
;
5528 operand_type_set (&temp
, 0);
5529 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5531 if (i
.prefix
[ADDR_PREFIX
] == 0)
5532 i
.types
[op
].bitfield
.disp32s
= 1;
5534 i
.types
[op
].bitfield
.disp32
= 1;
5537 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5538 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5540 i
.sib
.base
= i
.base_reg
->reg_num
;
5541 /* x86-64 ignores REX prefix bit here to avoid decoder
5543 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5546 if (i
.disp_operands
== 0)
5548 fake_zero_displacement
= 1;
5549 i
.types
[op
].bitfield
.disp8
= 1;
5552 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5556 i
.sib
.scale
= i
.log2_scale_factor
;
5557 if (i
.index_reg
== 0)
5559 /* <disp>(%esp) becomes two byte modrm with no index
5560 register. We've already stored the code for esp
5561 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5562 Any base register besides %esp will not use the
5563 extra modrm byte. */
5564 i
.sib
.index
= NO_INDEX_REGISTER
;
5568 if (i
.index_reg
->reg_num
== RegEiz
5569 || i
.index_reg
->reg_num
== RegRiz
)
5570 i
.sib
.index
= NO_INDEX_REGISTER
;
5572 i
.sib
.index
= i
.index_reg
->reg_num
;
5573 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5574 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5579 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5580 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5583 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5586 if (fake_zero_displacement
)
5588 /* Fakes a zero displacement assuming that i.types[op]
5589 holds the correct displacement size. */
5592 gas_assert (i
.op
[op
].disps
== 0);
5593 exp
= &disp_expressions
[i
.disp_operands
++];
5594 i
.op
[op
].disps
= exp
;
5595 exp
->X_op
= O_constant
;
5596 exp
->X_add_number
= 0;
5597 exp
->X_add_symbol
= (symbolS
*) 0;
5598 exp
->X_op_symbol
= (symbolS
*) 0;
5606 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5608 if (operand_type_check (i
.types
[0], imm
))
5609 i
.vex
.register_specifier
= NULL
;
5612 /* VEX.vvvv encodes one of the sources when the first
5613 operand is not an immediate. */
5614 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5615 i
.vex
.register_specifier
= i
.op
[0].regs
;
5617 i
.vex
.register_specifier
= i
.op
[1].regs
;
5620 /* Destination is a XMM register encoded in the ModRM.reg
5622 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5623 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5626 /* ModRM.rm and VEX.B encodes the other source. */
5627 if (!i
.mem_operands
)
5631 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5632 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5634 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5636 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5640 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5642 i
.vex
.register_specifier
= i
.op
[2].regs
;
5643 if (!i
.mem_operands
)
5646 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5647 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5651 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5652 (if any) based on i.tm.extension_opcode. Again, we must be
5653 careful to make sure that segment/control/debug/test/MMX
5654 registers are coded into the i.rm.reg field. */
5655 else if (i
.reg_operands
)
5658 unsigned int vex_reg
= ~0;
5660 for (op
= 0; op
< i
.operands
; op
++)
5661 if (i
.types
[op
].bitfield
.reg8
5662 || i
.types
[op
].bitfield
.reg16
5663 || i
.types
[op
].bitfield
.reg32
5664 || i
.types
[op
].bitfield
.reg64
5665 || i
.types
[op
].bitfield
.regmmx
5666 || i
.types
[op
].bitfield
.regxmm
5667 || i
.types
[op
].bitfield
.regymm
5668 || i
.types
[op
].bitfield
.sreg2
5669 || i
.types
[op
].bitfield
.sreg3
5670 || i
.types
[op
].bitfield
.control
5671 || i
.types
[op
].bitfield
.debug
5672 || i
.types
[op
].bitfield
.test
)
5677 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5679 /* For instructions with VexNDS, the register-only
5680 source operand is encoded in VEX prefix. */
5681 gas_assert (mem
!= (unsigned int) ~0);
5686 gas_assert (op
< i
.operands
);
5690 /* Check register-only source operand when two source
5691 operands are swapped. */
5692 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5693 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5697 gas_assert (mem
== (vex_reg
+ 1)
5698 && op
< i
.operands
);
5703 gas_assert (vex_reg
< i
.operands
);
5707 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5709 /* For instructions with VexNDD, the register destination
5710 is encoded in VEX prefix. */
5711 if (i
.mem_operands
== 0)
5713 /* There is no memory operand. */
5714 gas_assert ((op
+ 2) == i
.operands
);
5719 /* There are only 2 operands. */
5720 gas_assert (op
< 2 && i
.operands
== 2);
5725 gas_assert (op
< i
.operands
);
5727 if (vex_reg
!= (unsigned int) ~0)
5729 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5731 if (type
->bitfield
.reg32
!= 1
5732 && type
->bitfield
.reg64
!= 1
5733 && !operand_type_equal (type
, ®xmm
)
5734 && !operand_type_equal (type
, ®ymm
))
5737 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5740 /* Don't set OP operand twice. */
5743 /* If there is an extension opcode to put here, the
5744 register number must be put into the regmem field. */
5745 if (i
.tm
.extension_opcode
!= None
)
5747 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5748 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5753 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5754 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5759 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5760 must set it to 3 to indicate this is a register operand
5761 in the regmem field. */
5762 if (!i
.mem_operands
)
5766 /* Fill in i.rm.reg field with extension opcode (if any). */
5767 if (i
.tm
.extension_opcode
!= None
)
5768 i
.rm
.reg
= i
.tm
.extension_opcode
;
5774 output_branch (void)
5780 relax_substateT subtype
;
5784 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
5785 size
= i
.disp32_encoding
? BIG
: SMALL
;
5788 if (i
.prefix
[DATA_PREFIX
] != 0)
5794 /* Pentium4 branch hints. */
5795 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5796 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5801 if (i
.prefix
[REX_PREFIX
] != 0)
5807 if (i
.prefixes
!= 0 && !intel_syntax
)
5808 as_warn (_("skipping prefixes on this instruction"));
5810 /* It's always a symbol; End frag & setup for relax.
5811 Make sure there is enough room in this frag for the largest
5812 instruction we may generate in md_convert_frag. This is 2
5813 bytes for the opcode and room for the prefix and largest
5815 frag_grow (prefix
+ 2 + 4);
5816 /* Prefix and 1 opcode byte go in fr_fix. */
5817 p
= frag_more (prefix
+ 1);
5818 if (i
.prefix
[DATA_PREFIX
] != 0)
5819 *p
++ = DATA_PREFIX_OPCODE
;
5820 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5821 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5822 *p
++ = i
.prefix
[SEG_PREFIX
];
5823 if (i
.prefix
[REX_PREFIX
] != 0)
5824 *p
++ = i
.prefix
[REX_PREFIX
];
5825 *p
= i
.tm
.base_opcode
;
5827 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5828 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
5829 else if (cpu_arch_flags
.bitfield
.cpui386
)
5830 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
5832 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
5835 sym
= i
.op
[0].disps
->X_add_symbol
;
5836 off
= i
.op
[0].disps
->X_add_number
;
5838 if (i
.op
[0].disps
->X_op
!= O_constant
5839 && i
.op
[0].disps
->X_op
!= O_symbol
)
5841 /* Handle complex expressions. */
5842 sym
= make_expr_symbol (i
.op
[0].disps
);
5846 /* 1 possible extra opcode + 4 byte displacement go in var part.
5847 Pass reloc in fr_var. */
5848 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5858 if (i
.tm
.opcode_modifier
.jumpbyte
)
5860 /* This is a loop or jecxz type instruction. */
5862 if (i
.prefix
[ADDR_PREFIX
] != 0)
5864 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5867 /* Pentium4 branch hints. */
5868 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5869 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5871 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5880 if (flag_code
== CODE_16BIT
)
5883 if (i
.prefix
[DATA_PREFIX
] != 0)
5885 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5895 if (i
.prefix
[REX_PREFIX
] != 0)
5897 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5901 if (i
.prefixes
!= 0 && !intel_syntax
)
5902 as_warn (_("skipping prefixes on this instruction"));
5904 p
= frag_more (1 + size
);
5905 *p
++ = i
.tm
.base_opcode
;
5907 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5908 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5910 /* All jumps handled here are signed, but don't use a signed limit
5911 check for 32 and 16 bit jumps as we want to allow wrap around at
5912 4G and 64k respectively. */
5914 fixP
->fx_signed
= 1;
5918 output_interseg_jump (void)
5926 if (flag_code
== CODE_16BIT
)
5930 if (i
.prefix
[DATA_PREFIX
] != 0)
5936 if (i
.prefix
[REX_PREFIX
] != 0)
5946 if (i
.prefixes
!= 0 && !intel_syntax
)
5947 as_warn (_("skipping prefixes on this instruction"));
5949 /* 1 opcode; 2 segment; offset */
5950 p
= frag_more (prefix
+ 1 + 2 + size
);
5952 if (i
.prefix
[DATA_PREFIX
] != 0)
5953 *p
++ = DATA_PREFIX_OPCODE
;
5955 if (i
.prefix
[REX_PREFIX
] != 0)
5956 *p
++ = i
.prefix
[REX_PREFIX
];
5958 *p
++ = i
.tm
.base_opcode
;
5959 if (i
.op
[1].imms
->X_op
== O_constant
)
5961 offsetT n
= i
.op
[1].imms
->X_add_number
;
5964 && !fits_in_unsigned_word (n
)
5965 && !fits_in_signed_word (n
))
5967 as_bad (_("16-bit jump out of range"));
5970 md_number_to_chars (p
, n
, size
);
5973 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5974 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5975 if (i
.op
[0].imms
->X_op
!= O_constant
)
5976 as_bad (_("can't handle non absolute segment in `%s'"),
5978 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5984 fragS
*insn_start_frag
;
5985 offsetT insn_start_off
;
5987 /* Tie dwarf2 debug info to the address at the start of the insn.
5988 We can't do this after the insn has been output as the current
5989 frag may have been closed off. eg. by frag_var. */
5990 dwarf2_emit_insn (0);
5992 insn_start_frag
= frag_now
;
5993 insn_start_off
= frag_now_fix ();
5996 if (i
.tm
.opcode_modifier
.jump
)
5998 else if (i
.tm
.opcode_modifier
.jumpbyte
5999 || i
.tm
.opcode_modifier
.jumpdword
)
6001 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
6002 output_interseg_jump ();
6005 /* Output normal instructions here. */
6009 unsigned int prefix
;
6011 /* Since the VEX prefix contains the implicit prefix, we don't
6012 need the explicit prefix. */
6013 if (!i
.tm
.opcode_modifier
.vex
)
6015 switch (i
.tm
.opcode_length
)
6018 if (i
.tm
.base_opcode
& 0xff000000)
6020 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6025 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6027 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6028 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6031 if (prefix
!= REPE_PREFIX_OPCODE
6032 || (i
.prefix
[REP_PREFIX
]
6033 != REPE_PREFIX_OPCODE
))
6034 add_prefix (prefix
);
6037 add_prefix (prefix
);
6046 /* The prefix bytes. */
6047 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6049 FRAG_APPEND_1_CHAR (*q
);
6052 if (i
.tm
.opcode_modifier
.vex
)
6054 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6059 /* REX byte is encoded in VEX prefix. */
6063 FRAG_APPEND_1_CHAR (*q
);
6066 /* There should be no other prefixes for instructions
6071 /* Now the VEX prefix. */
6072 p
= frag_more (i
.vex
.length
);
6073 for (j
= 0; j
< i
.vex
.length
; j
++)
6074 p
[j
] = i
.vex
.bytes
[j
];
6077 /* Now the opcode; be careful about word order here! */
6078 if (i
.tm
.opcode_length
== 1)
6080 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6084 switch (i
.tm
.opcode_length
)
6088 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6098 /* Put out high byte first: can't use md_number_to_chars! */
6099 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6100 *p
= i
.tm
.base_opcode
& 0xff;
6103 /* Now the modrm byte and sib byte (if present). */
6104 if (i
.tm
.opcode_modifier
.modrm
)
6106 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6109 /* If i.rm.regmem == ESP (4)
6110 && i.rm.mode != (Register mode)
6112 ==> need second modrm byte. */
6113 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6115 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6116 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6118 | i
.sib
.scale
<< 6));
6121 if (i
.disp_operands
)
6122 output_disp (insn_start_frag
, insn_start_off
);
6125 output_imm (insn_start_frag
, insn_start_off
);
6131 pi ("" /*line*/, &i
);
6133 #endif /* DEBUG386 */
6136 /* Return the size of the displacement operand N. */
6139 disp_size (unsigned int n
)
6142 if (i
.types
[n
].bitfield
.disp64
)
6144 else if (i
.types
[n
].bitfield
.disp8
)
6146 else if (i
.types
[n
].bitfield
.disp16
)
6151 /* Return the size of the immediate operand N. */
6154 imm_size (unsigned int n
)
6157 if (i
.types
[n
].bitfield
.imm64
)
6159 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6161 else if (i
.types
[n
].bitfield
.imm16
)
6167 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6172 for (n
= 0; n
< i
.operands
; n
++)
6174 if (operand_type_check (i
.types
[n
], disp
))
6176 if (i
.op
[n
].disps
->X_op
== O_constant
)
6178 int size
= disp_size (n
);
6181 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6183 p
= frag_more (size
);
6184 md_number_to_chars (p
, val
, size
);
6188 enum bfd_reloc_code_real reloc_type
;
6189 int size
= disp_size (n
);
6190 int sign
= i
.types
[n
].bitfield
.disp32s
;
6191 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6193 /* We can't have 8 bit displacement here. */
6194 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6196 /* The PC relative address is computed relative
6197 to the instruction boundary, so in case immediate
6198 fields follows, we need to adjust the value. */
6199 if (pcrel
&& i
.imm_operands
)
6204 for (n1
= 0; n1
< i
.operands
; n1
++)
6205 if (operand_type_check (i
.types
[n1
], imm
))
6207 /* Only one immediate is allowed for PC
6208 relative address. */
6209 gas_assert (sz
== 0);
6211 i
.op
[n
].disps
->X_add_number
-= sz
;
6213 /* We should find the immediate. */
6214 gas_assert (sz
!= 0);
6217 p
= frag_more (size
);
6218 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6220 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6221 && (((reloc_type
== BFD_RELOC_32
6222 || reloc_type
== BFD_RELOC_X86_64_32S
6223 || (reloc_type
== BFD_RELOC_64
6225 && (i
.op
[n
].disps
->X_op
== O_symbol
6226 || (i
.op
[n
].disps
->X_op
== O_add
6227 && ((symbol_get_value_expression
6228 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6230 || reloc_type
== BFD_RELOC_32_PCREL
))
6234 if (insn_start_frag
== frag_now
)
6235 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6240 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6241 for (fr
= insn_start_frag
->fr_next
;
6242 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6244 add
+= p
- frag_now
->fr_literal
;
6249 reloc_type
= BFD_RELOC_386_GOTPC
;
6250 i
.op
[n
].imms
->X_add_number
+= add
;
6252 else if (reloc_type
== BFD_RELOC_64
)
6253 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6255 /* Don't do the adjustment for x86-64, as there
6256 the pcrel addressing is relative to the _next_
6257 insn, and that is taken care of in other code. */
6258 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6260 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6261 i
.op
[n
].disps
, pcrel
, reloc_type
);
6268 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6273 for (n
= 0; n
< i
.operands
; n
++)
6275 if (operand_type_check (i
.types
[n
], imm
))
6277 if (i
.op
[n
].imms
->X_op
== O_constant
)
6279 int size
= imm_size (n
);
6282 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6284 p
= frag_more (size
);
6285 md_number_to_chars (p
, val
, size
);
6289 /* Not absolute_section.
6290 Need a 32-bit fixup (don't support 8bit
6291 non-absolute imms). Try to support other
6293 enum bfd_reloc_code_real reloc_type
;
6294 int size
= imm_size (n
);
6297 if (i
.types
[n
].bitfield
.imm32s
6298 && (i
.suffix
== QWORD_MNEM_SUFFIX
6299 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6304 p
= frag_more (size
);
6305 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6307 /* This is tough to explain. We end up with this one if we
6308 * have operands that look like
6309 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6310 * obtain the absolute address of the GOT, and it is strongly
6311 * preferable from a performance point of view to avoid using
6312 * a runtime relocation for this. The actual sequence of
6313 * instructions often look something like:
6318 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6320 * The call and pop essentially return the absolute address
6321 * of the label .L66 and store it in %ebx. The linker itself
6322 * will ultimately change the first operand of the addl so
6323 * that %ebx points to the GOT, but to keep things simple, the
6324 * .o file must have this operand set so that it generates not
6325 * the absolute address of .L66, but the absolute address of
6326 * itself. This allows the linker itself simply treat a GOTPC
6327 * relocation as asking for a pcrel offset to the GOT to be
6328 * added in, and the addend of the relocation is stored in the
6329 * operand field for the instruction itself.
6331 * Our job here is to fix the operand so that it would add
6332 * the correct offset so that %ebx would point to itself. The
6333 * thing that is tricky is that .-.L66 will point to the
6334 * beginning of the instruction, so we need to further modify
6335 * the operand so that it will point to itself. There are
6336 * other cases where you have something like:
6338 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6340 * and here no correction would be required. Internally in
6341 * the assembler we treat operands of this form as not being
6342 * pcrel since the '.' is explicitly mentioned, and I wonder
6343 * whether it would simplify matters to do it this way. Who
6344 * knows. In earlier versions of the PIC patches, the
6345 * pcrel_adjust field was used to store the correction, but
6346 * since the expression is not pcrel, I felt it would be
6347 * confusing to do it this way. */
6349 if ((reloc_type
== BFD_RELOC_32
6350 || reloc_type
== BFD_RELOC_X86_64_32S
6351 || reloc_type
== BFD_RELOC_64
)
6353 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6354 && (i
.op
[n
].imms
->X_op
== O_symbol
6355 || (i
.op
[n
].imms
->X_op
== O_add
6356 && ((symbol_get_value_expression
6357 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6362 if (insn_start_frag
== frag_now
)
6363 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6368 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6369 for (fr
= insn_start_frag
->fr_next
;
6370 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6372 add
+= p
- frag_now
->fr_literal
;
6376 reloc_type
= BFD_RELOC_386_GOTPC
;
6378 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6380 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6381 i
.op
[n
].imms
->X_add_number
+= add
;
6383 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6384 i
.op
[n
].imms
, 0, reloc_type
);
6390 /* x86_cons_fix_new is called via the expression parsing code when a
6391 reloc is needed. We use this hook to get the correct .got reloc. */
6392 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6393 static int cons_sign
= -1;
6396 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6399 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6401 got_reloc
= NO_RELOC
;
6404 if (exp
->X_op
== O_secrel
)
6406 exp
->X_op
= O_symbol
;
6407 r
= BFD_RELOC_32_SECREL
;
6411 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6414 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6415 # define lex_got(reloc, adjust, types) NULL
6417 /* Parse operands of the form
6418 <symbol>@GOTOFF+<nnn>
6419 and similar .plt or .got references.
6421 If we find one, set up the correct relocation in RELOC and copy the
6422 input string, minus the `@GOTOFF' into a malloc'd buffer for
6423 parsing by the calling routine. Return this buffer, and if ADJUST
6424 is non-null set it to the length of the string we removed from the
6425 input line. Otherwise return NULL. */
6427 lex_got (enum bfd_reloc_code_real
*rel
,
6429 i386_operand_type
*types
)
6431 /* Some of the relocations depend on the size of what field is to
6432 be relocated. But in our callers i386_immediate and i386_displacement
6433 we don't yet know the operand size (this will be set by insn
6434 matching). Hence we record the word32 relocation here,
6435 and adjust the reloc according to the real size in reloc(). */
6436 static const struct {
6439 const enum bfd_reloc_code_real rel
[2];
6440 const i386_operand_type types64
;
6442 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6443 BFD_RELOC_X86_64_PLTOFF64
},
6444 OPERAND_TYPE_IMM64
},
6445 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6446 BFD_RELOC_X86_64_PLT32
},
6447 OPERAND_TYPE_IMM32_32S_DISP32
},
6448 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6449 BFD_RELOC_X86_64_GOTPLT64
},
6450 OPERAND_TYPE_IMM64_DISP64
},
6451 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6452 BFD_RELOC_X86_64_GOTOFF64
},
6453 OPERAND_TYPE_IMM64_DISP64
},
6454 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6455 BFD_RELOC_X86_64_GOTPCREL
},
6456 OPERAND_TYPE_IMM32_32S_DISP32
},
6457 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6458 BFD_RELOC_X86_64_TLSGD
},
6459 OPERAND_TYPE_IMM32_32S_DISP32
},
6460 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6461 _dummy_first_bfd_reloc_code_real
},
6462 OPERAND_TYPE_NONE
},
6463 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6464 BFD_RELOC_X86_64_TLSLD
},
6465 OPERAND_TYPE_IMM32_32S_DISP32
},
6466 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6467 BFD_RELOC_X86_64_GOTTPOFF
},
6468 OPERAND_TYPE_IMM32_32S_DISP32
},
6469 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6470 BFD_RELOC_X86_64_TPOFF32
},
6471 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6472 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6473 _dummy_first_bfd_reloc_code_real
},
6474 OPERAND_TYPE_NONE
},
6475 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6476 BFD_RELOC_X86_64_DTPOFF32
},
6477 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6478 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6479 _dummy_first_bfd_reloc_code_real
},
6480 OPERAND_TYPE_NONE
},
6481 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6482 _dummy_first_bfd_reloc_code_real
},
6483 OPERAND_TYPE_NONE
},
6484 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6485 BFD_RELOC_X86_64_GOT32
},
6486 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6487 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6488 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6489 OPERAND_TYPE_IMM32_32S_DISP32
},
6490 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6491 BFD_RELOC_X86_64_TLSDESC_CALL
},
6492 OPERAND_TYPE_IMM32_32S_DISP32
},
6500 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6501 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6504 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6506 int len
= gotrel
[j
].len
;
6507 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6509 if (gotrel
[j
].rel
[object_64bit
] != 0)
6512 char *tmpbuf
, *past_reloc
;
6514 *rel
= gotrel
[j
].rel
[object_64bit
];
6520 if (flag_code
!= CODE_64BIT
)
6522 types
->bitfield
.imm32
= 1;
6523 types
->bitfield
.disp32
= 1;
6526 *types
= gotrel
[j
].types64
;
6529 if (GOT_symbol
== NULL
)
6530 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6532 /* The length of the first part of our input line. */
6533 first
= cp
- input_line_pointer
;
6535 /* The second part goes from after the reloc token until
6536 (and including) an end_of_line char or comma. */
6537 past_reloc
= cp
+ 1 + len
;
6539 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6541 second
= cp
+ 1 - past_reloc
;
6543 /* Allocate and copy string. The trailing NUL shouldn't
6544 be necessary, but be safe. */
6545 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6546 memcpy (tmpbuf
, input_line_pointer
, first
);
6547 if (second
!= 0 && *past_reloc
!= ' ')
6548 /* Replace the relocation token with ' ', so that
6549 errors like foo@GOTOFF1 will be detected. */
6550 tmpbuf
[first
++] = ' ';
6551 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6552 tmpbuf
[first
+ second
] = '\0';
6556 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6557 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6562 /* Might be a symbol version string. Don't as_bad here. */
6567 x86_cons (expressionS
*exp
, int size
)
6569 intel_syntax
= -intel_syntax
;
6572 if (size
== 4 || (object_64bit
&& size
== 8))
6574 /* Handle @GOTOFF and the like in an expression. */
6576 char *gotfree_input_line
;
6579 save
= input_line_pointer
;
6580 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6581 if (gotfree_input_line
)
6582 input_line_pointer
= gotfree_input_line
;
6586 if (gotfree_input_line
)
6588 /* expression () has merrily parsed up to the end of line,
6589 or a comma - in the wrong buffer. Transfer how far
6590 input_line_pointer has moved to the right buffer. */
6591 input_line_pointer
= (save
6592 + (input_line_pointer
- gotfree_input_line
)
6594 free (gotfree_input_line
);
6595 if (exp
->X_op
== O_constant
6596 || exp
->X_op
== O_absent
6597 || exp
->X_op
== O_illegal
6598 || exp
->X_op
== O_register
6599 || exp
->X_op
== O_big
)
6601 char c
= *input_line_pointer
;
6602 *input_line_pointer
= 0;
6603 as_bad (_("missing or invalid expression `%s'"), save
);
6604 *input_line_pointer
= c
;
6611 intel_syntax
= -intel_syntax
;
6614 i386_intel_simplify (exp
);
6619 signed_cons (int size
)
6621 if (flag_code
== CODE_64BIT
)
6629 pe_directive_secrel (dummy
)
6630 int dummy ATTRIBUTE_UNUSED
;
6637 if (exp
.X_op
== O_symbol
)
6638 exp
.X_op
= O_secrel
;
6640 emit_expr (&exp
, 4);
6642 while (*input_line_pointer
++ == ',');
6644 input_line_pointer
--;
6645 demand_empty_rest_of_line ();
6650 i386_immediate (char *imm_start
)
6652 char *save_input_line_pointer
;
6653 char *gotfree_input_line
;
6656 i386_operand_type types
;
6658 operand_type_set (&types
, ~0);
6660 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6662 as_bad (_("at most %d immediate operands are allowed"),
6663 MAX_IMMEDIATE_OPERANDS
);
6667 exp
= &im_expressions
[i
.imm_operands
++];
6668 i
.op
[this_operand
].imms
= exp
;
6670 if (is_space_char (*imm_start
))
6673 save_input_line_pointer
= input_line_pointer
;
6674 input_line_pointer
= imm_start
;
6676 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6677 if (gotfree_input_line
)
6678 input_line_pointer
= gotfree_input_line
;
6680 exp_seg
= expression (exp
);
6683 if (*input_line_pointer
)
6684 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6686 input_line_pointer
= save_input_line_pointer
;
6687 if (gotfree_input_line
)
6689 free (gotfree_input_line
);
6691 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6692 exp
->X_op
= O_illegal
;
6695 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6699 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6700 i386_operand_type types
, const char *imm_start
)
6702 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6705 as_bad (_("missing or invalid immediate expression `%s'"),
6709 else if (exp
->X_op
== O_constant
)
6711 /* Size it properly later. */
6712 i
.types
[this_operand
].bitfield
.imm64
= 1;
6713 /* If not 64bit, sign extend val. */
6714 if (flag_code
!= CODE_64BIT
6715 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6717 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6719 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6720 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6721 && exp_seg
!= absolute_section
6722 && exp_seg
!= text_section
6723 && exp_seg
!= data_section
6724 && exp_seg
!= bss_section
6725 && exp_seg
!= undefined_section
6726 && !bfd_is_com_section (exp_seg
))
6728 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6732 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6735 as_bad (_("illegal immediate register operand %s"), imm_start
);
6740 /* This is an address. The size of the address will be
6741 determined later, depending on destination register,
6742 suffix, or the default for the section. */
6743 i
.types
[this_operand
].bitfield
.imm8
= 1;
6744 i
.types
[this_operand
].bitfield
.imm16
= 1;
6745 i
.types
[this_operand
].bitfield
.imm32
= 1;
6746 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6747 i
.types
[this_operand
].bitfield
.imm64
= 1;
6748 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6756 i386_scale (char *scale
)
6759 char *save
= input_line_pointer
;
6761 input_line_pointer
= scale
;
6762 val
= get_absolute_expression ();
6767 i
.log2_scale_factor
= 0;
6770 i
.log2_scale_factor
= 1;
6773 i
.log2_scale_factor
= 2;
6776 i
.log2_scale_factor
= 3;
6780 char sep
= *input_line_pointer
;
6782 *input_line_pointer
= '\0';
6783 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6785 *input_line_pointer
= sep
;
6786 input_line_pointer
= save
;
6790 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6792 as_warn (_("scale factor of %d without an index register"),
6793 1 << i
.log2_scale_factor
);
6794 i
.log2_scale_factor
= 0;
6796 scale
= input_line_pointer
;
6797 input_line_pointer
= save
;
6802 i386_displacement (char *disp_start
, char *disp_end
)
6806 char *save_input_line_pointer
;
6807 char *gotfree_input_line
;
6809 i386_operand_type bigdisp
, types
= anydisp
;
6812 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6814 as_bad (_("at most %d displacement operands are allowed"),
6815 MAX_MEMORY_OPERANDS
);
6819 operand_type_set (&bigdisp
, 0);
6820 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6821 || (!current_templates
->start
->opcode_modifier
.jump
6822 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6824 bigdisp
.bitfield
.disp32
= 1;
6825 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6826 if (flag_code
== CODE_64BIT
)
6830 bigdisp
.bitfield
.disp32s
= 1;
6831 bigdisp
.bitfield
.disp64
= 1;
6834 else if ((flag_code
== CODE_16BIT
) ^ override
)
6836 bigdisp
.bitfield
.disp32
= 0;
6837 bigdisp
.bitfield
.disp16
= 1;
6842 /* For PC-relative branches, the width of the displacement
6843 is dependent upon data size, not address size. */
6844 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6845 if (flag_code
== CODE_64BIT
)
6847 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6848 bigdisp
.bitfield
.disp16
= 1;
6851 bigdisp
.bitfield
.disp32
= 1;
6852 bigdisp
.bitfield
.disp32s
= 1;
6858 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6860 : LONG_MNEM_SUFFIX
));
6861 bigdisp
.bitfield
.disp32
= 1;
6862 if ((flag_code
== CODE_16BIT
) ^ override
)
6864 bigdisp
.bitfield
.disp32
= 0;
6865 bigdisp
.bitfield
.disp16
= 1;
6869 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6872 exp
= &disp_expressions
[i
.disp_operands
];
6873 i
.op
[this_operand
].disps
= exp
;
6875 save_input_line_pointer
= input_line_pointer
;
6876 input_line_pointer
= disp_start
;
6877 END_STRING_AND_SAVE (disp_end
);
6879 #ifndef GCC_ASM_O_HACK
6880 #define GCC_ASM_O_HACK 0
6883 END_STRING_AND_SAVE (disp_end
+ 1);
6884 if (i
.types
[this_operand
].bitfield
.baseIndex
6885 && displacement_string_end
[-1] == '+')
6887 /* This hack is to avoid a warning when using the "o"
6888 constraint within gcc asm statements.
6891 #define _set_tssldt_desc(n,addr,limit,type) \
6892 __asm__ __volatile__ ( \
6894 "movw %w1,2+%0\n\t" \
6896 "movb %b1,4+%0\n\t" \
6897 "movb %4,5+%0\n\t" \
6898 "movb $0,6+%0\n\t" \
6899 "movb %h1,7+%0\n\t" \
6901 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6903 This works great except that the output assembler ends
6904 up looking a bit weird if it turns out that there is
6905 no offset. You end up producing code that looks like:
6918 So here we provide the missing zero. */
6920 *displacement_string_end
= '0';
6923 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6924 if (gotfree_input_line
)
6925 input_line_pointer
= gotfree_input_line
;
6927 exp_seg
= expression (exp
);
6930 if (*input_line_pointer
)
6931 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6933 RESTORE_END_STRING (disp_end
+ 1);
6935 input_line_pointer
= save_input_line_pointer
;
6936 if (gotfree_input_line
)
6938 free (gotfree_input_line
);
6940 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6941 exp
->X_op
= O_illegal
;
6944 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6946 RESTORE_END_STRING (disp_end
);
6952 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6953 i386_operand_type types
, const char *disp_start
)
6955 i386_operand_type bigdisp
;
6958 /* We do this to make sure that the section symbol is in
6959 the symbol table. We will ultimately change the relocation
6960 to be relative to the beginning of the section. */
6961 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6962 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6963 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6965 if (exp
->X_op
!= O_symbol
)
6968 if (S_IS_LOCAL (exp
->X_add_symbol
)
6969 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
6970 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
6971 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6972 exp
->X_op
= O_subtract
;
6973 exp
->X_op_symbol
= GOT_symbol
;
6974 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6975 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6976 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6977 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6979 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6982 else if (exp
->X_op
== O_absent
6983 || exp
->X_op
== O_illegal
6984 || exp
->X_op
== O_big
)
6987 as_bad (_("missing or invalid displacement expression `%s'"),
6992 else if (flag_code
== CODE_64BIT
6993 && !i
.prefix
[ADDR_PREFIX
]
6994 && exp
->X_op
== O_constant
)
6996 /* Since displacement is signed extended to 64bit, don't allow
6997 disp32 and turn off disp32s if they are out of range. */
6998 i
.types
[this_operand
].bitfield
.disp32
= 0;
6999 if (!fits_in_signed_long (exp
->X_add_number
))
7001 i
.types
[this_operand
].bitfield
.disp32s
= 0;
7002 if (i
.types
[this_operand
].bitfield
.baseindex
)
7004 as_bad (_("0x%lx out range of signed 32bit displacement"),
7005 (long) exp
->X_add_number
);
7011 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
7012 else if (exp
->X_op
!= O_constant
7013 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
7014 && exp_seg
!= absolute_section
7015 && exp_seg
!= text_section
7016 && exp_seg
!= data_section
7017 && exp_seg
!= bss_section
7018 && exp_seg
!= undefined_section
7019 && !bfd_is_com_section (exp_seg
))
7021 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7026 /* Check if this is a displacement only operand. */
7027 bigdisp
= i
.types
[this_operand
];
7028 bigdisp
.bitfield
.disp8
= 0;
7029 bigdisp
.bitfield
.disp16
= 0;
7030 bigdisp
.bitfield
.disp32
= 0;
7031 bigdisp
.bitfield
.disp32s
= 0;
7032 bigdisp
.bitfield
.disp64
= 0;
7033 if (operand_type_all_zero (&bigdisp
))
7034 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7040 /* Make sure the memory operand we've been dealt is valid.
7041 Return 1 on success, 0 on a failure. */
7044 i386_index_check (const char *operand_string
)
7047 const char *kind
= "base/index";
7048 #if INFER_ADDR_PREFIX
7054 if (current_templates
->start
->opcode_modifier
.isstring
7055 && !current_templates
->start
->opcode_modifier
.immext
7056 && (current_templates
->end
[-1].opcode_modifier
.isstring
7059 /* Memory operands of string insns are special in that they only allow
7060 a single register (rDI, rSI, or rBX) as their memory address. */
7061 unsigned int expected
;
7063 kind
= "string address";
7065 if (current_templates
->start
->opcode_modifier
.w
)
7067 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7069 if (!type
.bitfield
.baseindex
7070 || ((!i
.mem_operands
!= !intel_syntax
)
7071 && current_templates
->end
[-1].operand_types
[1]
7072 .bitfield
.baseindex
))
7073 type
= current_templates
->end
[-1].operand_types
[1];
7074 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7077 expected
= 3 /* rBX */;
7079 if (!i
.base_reg
|| i
.index_reg
7080 || operand_type_check (i
.types
[this_operand
], disp
))
7082 else if (!(flag_code
== CODE_64BIT
7083 ? i
.prefix
[ADDR_PREFIX
]
7084 ? i
.base_reg
->reg_type
.bitfield
.reg32
7085 : i
.base_reg
->reg_type
.bitfield
.reg64
7086 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7087 ? i
.base_reg
->reg_type
.bitfield
.reg32
7088 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7090 else if (i
.base_reg
->reg_num
!= expected
)
7097 for (j
= 0; j
< i386_regtab_size
; ++j
)
7098 if ((flag_code
== CODE_64BIT
7099 ? i
.prefix
[ADDR_PREFIX
]
7100 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7101 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7102 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7103 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7104 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7105 && i386_regtab
[j
].reg_num
== expected
)
7107 gas_assert (j
< i386_regtab_size
);
7108 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7110 intel_syntax
? '[' : '(',
7112 i386_regtab
[j
].reg_name
,
7113 intel_syntax
? ']' : ')');
7117 else if (flag_code
== CODE_64BIT
)
7120 && ((i
.prefix
[ADDR_PREFIX
] == 0
7121 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7122 || (i
.prefix
[ADDR_PREFIX
]
7123 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7125 || i
.base_reg
->reg_num
!=
7126 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7128 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7129 || (i
.prefix
[ADDR_PREFIX
] == 0
7130 && i
.index_reg
->reg_num
!= RegRiz
7131 && !i
.index_reg
->reg_type
.bitfield
.reg64
7133 || (i
.prefix
[ADDR_PREFIX
]
7134 && i
.index_reg
->reg_num
!= RegEiz
7135 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7140 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7144 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7145 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7147 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7148 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7150 && i
.base_reg
->reg_num
< 6
7151 && i
.index_reg
->reg_num
>= 6
7152 && i
.log2_scale_factor
== 0))))
7159 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7161 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7162 && i
.index_reg
->reg_num
!= RegEiz
)
7163 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7169 #if INFER_ADDR_PREFIX
7170 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7172 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7174 /* Change the size of any displacement too. At most one of
7175 Disp16 or Disp32 is set.
7176 FIXME. There doesn't seem to be any real need for separate
7177 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7178 Removing them would probably clean up the code quite a lot. */
7179 if (flag_code
!= CODE_64BIT
7180 && (i
.types
[this_operand
].bitfield
.disp16
7181 || i
.types
[this_operand
].bitfield
.disp32
))
7182 i
.types
[this_operand
]
7183 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7188 as_bad (_("`%s' is not a valid %s expression"),
7193 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7195 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7196 ? flag_code
== CODE_32BIT
7205 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7209 i386_att_operand (char *operand_string
)
7213 char *op_string
= operand_string
;
7215 if (is_space_char (*op_string
))
7218 /* We check for an absolute prefix (differentiating,
7219 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7220 if (*op_string
== ABSOLUTE_PREFIX
)
7223 if (is_space_char (*op_string
))
7225 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7228 /* Check if operand is a register. */
7229 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7231 i386_operand_type temp
;
7233 /* Check for a segment override by searching for ':' after a
7234 segment register. */
7236 if (is_space_char (*op_string
))
7238 if (*op_string
== ':'
7239 && (r
->reg_type
.bitfield
.sreg2
7240 || r
->reg_type
.bitfield
.sreg3
))
7245 i
.seg
[i
.mem_operands
] = &es
;
7248 i
.seg
[i
.mem_operands
] = &cs
;
7251 i
.seg
[i
.mem_operands
] = &ss
;
7254 i
.seg
[i
.mem_operands
] = &ds
;
7257 i
.seg
[i
.mem_operands
] = &fs
;
7260 i
.seg
[i
.mem_operands
] = &gs
;
7264 /* Skip the ':' and whitespace. */
7266 if (is_space_char (*op_string
))
7269 if (!is_digit_char (*op_string
)
7270 && !is_identifier_char (*op_string
)
7271 && *op_string
!= '('
7272 && *op_string
!= ABSOLUTE_PREFIX
)
7274 as_bad (_("bad memory operand `%s'"), op_string
);
7277 /* Handle case of %es:*foo. */
7278 if (*op_string
== ABSOLUTE_PREFIX
)
7281 if (is_space_char (*op_string
))
7283 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7285 goto do_memory_reference
;
7289 as_bad (_("junk `%s' after register"), op_string
);
7293 temp
.bitfield
.baseindex
= 0;
7294 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7296 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7297 i
.op
[this_operand
].regs
= r
;
7300 else if (*op_string
== REGISTER_PREFIX
)
7302 as_bad (_("bad register name `%s'"), op_string
);
7305 else if (*op_string
== IMMEDIATE_PREFIX
)
7308 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7310 as_bad (_("immediate operand illegal with absolute jump"));
7313 if (!i386_immediate (op_string
))
7316 else if (is_digit_char (*op_string
)
7317 || is_identifier_char (*op_string
)
7318 || *op_string
== '(')
7320 /* This is a memory reference of some sort. */
7323 /* Start and end of displacement string expression (if found). */
7324 char *displacement_string_start
;
7325 char *displacement_string_end
;
7327 do_memory_reference
:
7328 if ((i
.mem_operands
== 1
7329 && !current_templates
->start
->opcode_modifier
.isstring
)
7330 || i
.mem_operands
== 2)
7332 as_bad (_("too many memory references for `%s'"),
7333 current_templates
->start
->name
);
7337 /* Check for base index form. We detect the base index form by
7338 looking for an ')' at the end of the operand, searching
7339 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7341 base_string
= op_string
+ strlen (op_string
);
7344 if (is_space_char (*base_string
))
7347 /* If we only have a displacement, set-up for it to be parsed later. */
7348 displacement_string_start
= op_string
;
7349 displacement_string_end
= base_string
+ 1;
7351 if (*base_string
== ')')
7354 unsigned int parens_balanced
= 1;
7355 /* We've already checked that the number of left & right ()'s are
7356 equal, so this loop will not be infinite. */
7360 if (*base_string
== ')')
7362 if (*base_string
== '(')
7365 while (parens_balanced
);
7367 temp_string
= base_string
;
7369 /* Skip past '(' and whitespace. */
7371 if (is_space_char (*base_string
))
7374 if (*base_string
== ','
7375 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7378 displacement_string_end
= temp_string
;
7380 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7384 base_string
= end_op
;
7385 if (is_space_char (*base_string
))
7389 /* There may be an index reg or scale factor here. */
7390 if (*base_string
== ',')
7393 if (is_space_char (*base_string
))
7396 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7399 base_string
= end_op
;
7400 if (is_space_char (*base_string
))
7402 if (*base_string
== ',')
7405 if (is_space_char (*base_string
))
7408 else if (*base_string
!= ')')
7410 as_bad (_("expecting `,' or `)' "
7411 "after index register in `%s'"),
7416 else if (*base_string
== REGISTER_PREFIX
)
7418 as_bad (_("bad register name `%s'"), base_string
);
7422 /* Check for scale factor. */
7423 if (*base_string
!= ')')
7425 char *end_scale
= i386_scale (base_string
);
7430 base_string
= end_scale
;
7431 if (is_space_char (*base_string
))
7433 if (*base_string
!= ')')
7435 as_bad (_("expecting `)' "
7436 "after scale factor in `%s'"),
7441 else if (!i
.index_reg
)
7443 as_bad (_("expecting index register or scale factor "
7444 "after `,'; got '%c'"),
7449 else if (*base_string
!= ')')
7451 as_bad (_("expecting `,' or `)' "
7452 "after base register in `%s'"),
7457 else if (*base_string
== REGISTER_PREFIX
)
7459 as_bad (_("bad register name `%s'"), base_string
);
7464 /* If there's an expression beginning the operand, parse it,
7465 assuming displacement_string_start and
7466 displacement_string_end are meaningful. */
7467 if (displacement_string_start
!= displacement_string_end
)
7469 if (!i386_displacement (displacement_string_start
,
7470 displacement_string_end
))
7474 /* Special case for (%dx) while doing input/output op. */
7476 && operand_type_equal (&i
.base_reg
->reg_type
,
7477 ®16_inoutportreg
)
7479 && i
.log2_scale_factor
== 0
7480 && i
.seg
[i
.mem_operands
] == 0
7481 && !operand_type_check (i
.types
[this_operand
], disp
))
7483 i
.types
[this_operand
] = inoutportreg
;
7487 if (i386_index_check (operand_string
) == 0)
7489 i
.types
[this_operand
].bitfield
.mem
= 1;
7494 /* It's not a memory operand; argh! */
7495 as_bad (_("invalid char %s beginning operand %d `%s'"),
7496 output_invalid (*op_string
),
7501 return 1; /* Normal return. */
7504 /* md_estimate_size_before_relax()
7506 Called just before relax() for rs_machine_dependent frags. The x86
7507 assembler uses these frags to handle variable size jump
7510 Any symbol that is now undefined will not become defined.
7511 Return the correct fr_subtype in the frag.
7512 Return the initial "guess for variable size of frag" to caller.
7513 The guess is actually the growth beyond the fixed part. Whatever
7514 we do to grow the fixed or variable part contributes to our
7518 md_estimate_size_before_relax (fragP
, segment
)
7522 /* We've already got fragP->fr_subtype right; all we have to do is
7523 check for un-relaxable symbols. On an ELF system, we can't relax
7524 an externally visible symbol, because it may be overridden by a
7526 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7527 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7529 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7530 || S_IS_WEAK (fragP
->fr_symbol
)
7531 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7532 & BSF_GNU_INDIRECT_FUNCTION
))))
7534 #if defined (OBJ_COFF) && defined (TE_PE)
7535 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7536 && S_IS_WEAK (fragP
->fr_symbol
))
7540 /* Symbol is undefined in this segment, or we need to keep a
7541 reloc so that weak symbols can be overridden. */
7542 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7543 enum bfd_reloc_code_real reloc_type
;
7544 unsigned char *opcode
;
7547 if (fragP
->fr_var
!= NO_RELOC
)
7548 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7550 reloc_type
= BFD_RELOC_16_PCREL
;
7552 reloc_type
= BFD_RELOC_32_PCREL
;
7554 old_fr_fix
= fragP
->fr_fix
;
7555 opcode
= (unsigned char *) fragP
->fr_opcode
;
7557 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7560 /* Make jmp (0xeb) a (d)word displacement jump. */
7562 fragP
->fr_fix
+= size
;
7563 fix_new (fragP
, old_fr_fix
, size
,
7565 fragP
->fr_offset
, 1,
7571 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7573 /* Negate the condition, and branch past an
7574 unconditional jump. */
7577 /* Insert an unconditional jump. */
7579 /* We added two extra opcode bytes, and have a two byte
7581 fragP
->fr_fix
+= 2 + 2;
7582 fix_new (fragP
, old_fr_fix
+ 2, 2,
7584 fragP
->fr_offset
, 1,
7591 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7596 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7598 fragP
->fr_offset
, 1,
7600 fixP
->fx_signed
= 1;
7604 /* This changes the byte-displacement jump 0x7N
7605 to the (d)word-displacement jump 0x0f,0x8N. */
7606 opcode
[1] = opcode
[0] + 0x10;
7607 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7608 /* We've added an opcode byte. */
7609 fragP
->fr_fix
+= 1 + size
;
7610 fix_new (fragP
, old_fr_fix
+ 1, size
,
7612 fragP
->fr_offset
, 1,
7617 BAD_CASE (fragP
->fr_subtype
);
7621 return fragP
->fr_fix
- old_fr_fix
;
7624 /* Guess size depending on current relax state. Initially the relax
7625 state will correspond to a short jump and we return 1, because
7626 the variable part of the frag (the branch offset) is one byte
7627 long. However, we can relax a section more than once and in that
7628 case we must either set fr_subtype back to the unrelaxed state,
7629 or return the value for the appropriate branch. */
7630 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7633 /* Called after relax() is finished.
7635 In: Address of frag.
7636 fr_type == rs_machine_dependent.
7637 fr_subtype is what the address relaxed to.
7639 Out: Any fixSs and constants are set up.
7640 Caller will turn frag into a ".space 0". */
7643 md_convert_frag (abfd
, sec
, fragP
)
7644 bfd
*abfd ATTRIBUTE_UNUSED
;
7645 segT sec ATTRIBUTE_UNUSED
;
7648 unsigned char *opcode
;
7649 unsigned char *where_to_put_displacement
= NULL
;
7650 offsetT target_address
;
7651 offsetT opcode_address
;
7652 unsigned int extension
= 0;
7653 offsetT displacement_from_opcode_start
;
7655 opcode
= (unsigned char *) fragP
->fr_opcode
;
7657 /* Address we want to reach in file space. */
7658 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7660 /* Address opcode resides at in file space. */
7661 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7663 /* Displacement from opcode start to fill into instruction. */
7664 displacement_from_opcode_start
= target_address
- opcode_address
;
7666 if ((fragP
->fr_subtype
& BIG
) == 0)
7668 /* Don't have to change opcode. */
7669 extension
= 1; /* 1 opcode + 1 displacement */
7670 where_to_put_displacement
= &opcode
[1];
7674 if (no_cond_jump_promotion
7675 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7676 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7677 _("long jump required"));
7679 switch (fragP
->fr_subtype
)
7681 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7682 extension
= 4; /* 1 opcode + 4 displacement */
7684 where_to_put_displacement
= &opcode
[1];
7687 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7688 extension
= 2; /* 1 opcode + 2 displacement */
7690 where_to_put_displacement
= &opcode
[1];
7693 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7694 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7695 extension
= 5; /* 2 opcode + 4 displacement */
7696 opcode
[1] = opcode
[0] + 0x10;
7697 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7698 where_to_put_displacement
= &opcode
[2];
7701 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7702 extension
= 3; /* 2 opcode + 2 displacement */
7703 opcode
[1] = opcode
[0] + 0x10;
7704 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7705 where_to_put_displacement
= &opcode
[2];
7708 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7713 where_to_put_displacement
= &opcode
[3];
7717 BAD_CASE (fragP
->fr_subtype
);
7722 /* If size if less then four we are sure that the operand fits,
7723 but if it's 4, then it could be that the displacement is larger
7725 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7727 && ((addressT
) (displacement_from_opcode_start
- extension
7728 + ((addressT
) 1 << 31))
7729 > (((addressT
) 2 << 31) - 1)))
7731 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7732 _("jump target out of range"));
7733 /* Make us emit 0. */
7734 displacement_from_opcode_start
= extension
;
7736 /* Now put displacement after opcode. */
7737 md_number_to_chars ((char *) where_to_put_displacement
,
7738 (valueT
) (displacement_from_opcode_start
- extension
),
7739 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7740 fragP
->fr_fix
+= extension
;
7743 /* Apply a fixup (fixS) to segment data, once it has been determined
7744 by our caller that we have all the info we need to fix it up.
7746 On the 386, immediates, displacements, and data pointers are all in
7747 the same (little-endian) format, so we don't need to care about which
7751 md_apply_fix (fixP
, valP
, seg
)
7752 /* The fix we're to put in. */
7754 /* Pointer to the value of the bits. */
7756 /* Segment fix is from. */
7757 segT seg ATTRIBUTE_UNUSED
;
7759 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7760 valueT value
= *valP
;
7762 #if !defined (TE_Mach)
7765 switch (fixP
->fx_r_type
)
7771 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7774 case BFD_RELOC_X86_64_32S
:
7775 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7778 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7781 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7786 if (fixP
->fx_addsy
!= NULL
7787 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7788 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7789 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7790 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7791 && !use_rela_relocations
)
7793 /* This is a hack. There should be a better way to handle this.
7794 This covers for the fact that bfd_install_relocation will
7795 subtract the current location (for partial_inplace, PC relative
7796 relocations); see more below. */
7800 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7803 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7805 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7808 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7811 || (symbol_section_p (fixP
->fx_addsy
)
7812 && sym_seg
!= absolute_section
))
7813 && !generic_force_reloc (fixP
))
7815 /* Yes, we add the values in twice. This is because
7816 bfd_install_relocation subtracts them out again. I think
7817 bfd_install_relocation is broken, but I don't dare change
7819 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7823 #if defined (OBJ_COFF) && defined (TE_PE)
7824 /* For some reason, the PE format does not store a
7825 section address offset for a PC relative symbol. */
7826 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7827 || S_IS_WEAK (fixP
->fx_addsy
))
7828 value
+= md_pcrel_from (fixP
);
7831 #if defined (OBJ_COFF) && defined (TE_PE)
7832 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7834 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7838 /* Fix a few things - the dynamic linker expects certain values here,
7839 and we must not disappoint it. */
7840 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7841 if (IS_ELF
&& fixP
->fx_addsy
)
7842 switch (fixP
->fx_r_type
)
7844 case BFD_RELOC_386_PLT32
:
7845 case BFD_RELOC_X86_64_PLT32
:
7846 /* Make the jump instruction point to the address of the operand. At
7847 runtime we merely add the offset to the actual PLT entry. */
7851 case BFD_RELOC_386_TLS_GD
:
7852 case BFD_RELOC_386_TLS_LDM
:
7853 case BFD_RELOC_386_TLS_IE_32
:
7854 case BFD_RELOC_386_TLS_IE
:
7855 case BFD_RELOC_386_TLS_GOTIE
:
7856 case BFD_RELOC_386_TLS_GOTDESC
:
7857 case BFD_RELOC_X86_64_TLSGD
:
7858 case BFD_RELOC_X86_64_TLSLD
:
7859 case BFD_RELOC_X86_64_GOTTPOFF
:
7860 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7861 value
= 0; /* Fully resolved at runtime. No addend. */
7863 case BFD_RELOC_386_TLS_LE
:
7864 case BFD_RELOC_386_TLS_LDO_32
:
7865 case BFD_RELOC_386_TLS_LE_32
:
7866 case BFD_RELOC_X86_64_DTPOFF32
:
7867 case BFD_RELOC_X86_64_DTPOFF64
:
7868 case BFD_RELOC_X86_64_TPOFF32
:
7869 case BFD_RELOC_X86_64_TPOFF64
:
7870 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7873 case BFD_RELOC_386_TLS_DESC_CALL
:
7874 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7875 value
= 0; /* Fully resolved at runtime. No addend. */
7876 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7880 case BFD_RELOC_386_GOT32
:
7881 case BFD_RELOC_X86_64_GOT32
:
7882 value
= 0; /* Fully resolved at runtime. No addend. */
7885 case BFD_RELOC_VTABLE_INHERIT
:
7886 case BFD_RELOC_VTABLE_ENTRY
:
7893 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7895 #endif /* !defined (TE_Mach) */
7897 /* Are we finished with this relocation now? */
7898 if (fixP
->fx_addsy
== NULL
)
7900 #if defined (OBJ_COFF) && defined (TE_PE)
7901 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7904 /* Remember value for tc_gen_reloc. */
7905 fixP
->fx_addnumber
= value
;
7906 /* Clear out the frag for now. */
7910 else if (use_rela_relocations
)
7912 fixP
->fx_no_overflow
= 1;
7913 /* Remember value for tc_gen_reloc. */
7914 fixP
->fx_addnumber
= value
;
7918 md_number_to_chars (p
, value
, fixP
->fx_size
);
7922 md_atof (int type
, char *litP
, int *sizeP
)
7924 /* This outputs the LITTLENUMs in REVERSE order;
7925 in accord with the bigendian 386. */
7926 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7929 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7932 output_invalid (int c
)
7935 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7938 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7939 "(0x%x)", (unsigned char) c
);
7940 return output_invalid_buf
;
7943 /* REG_STRING starts *before* REGISTER_PREFIX. */
7945 static const reg_entry
*
7946 parse_real_register (char *reg_string
, char **end_op
)
7948 char *s
= reg_string
;
7950 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7953 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7954 if (*s
== REGISTER_PREFIX
)
7957 if (is_space_char (*s
))
7961 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7963 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7964 return (const reg_entry
*) NULL
;
7968 /* For naked regs, make sure that we are not dealing with an identifier.
7969 This prevents confusing an identifier like `eax_var' with register
7971 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7972 return (const reg_entry
*) NULL
;
7976 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7978 /* Handle floating point regs, allowing spaces in the (i) part. */
7979 if (r
== i386_regtab
/* %st is first entry of table */)
7981 if (is_space_char (*s
))
7986 if (is_space_char (*s
))
7988 if (*s
>= '0' && *s
<= '7')
7992 if (is_space_char (*s
))
7997 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
8002 /* We have "%st(" then garbage. */
8003 return (const reg_entry
*) NULL
;
8007 if (r
== NULL
|| allow_pseudo_reg
)
8010 if (operand_type_all_zero (&r
->reg_type
))
8011 return (const reg_entry
*) NULL
;
8013 if ((r
->reg_type
.bitfield
.reg32
8014 || r
->reg_type
.bitfield
.sreg3
8015 || r
->reg_type
.bitfield
.control
8016 || r
->reg_type
.bitfield
.debug
8017 || r
->reg_type
.bitfield
.test
)
8018 && !cpu_arch_flags
.bitfield
.cpui386
)
8019 return (const reg_entry
*) NULL
;
8021 if (r
->reg_type
.bitfield
.floatreg
8022 && !cpu_arch_flags
.bitfield
.cpu8087
8023 && !cpu_arch_flags
.bitfield
.cpu287
8024 && !cpu_arch_flags
.bitfield
.cpu387
)
8025 return (const reg_entry
*) NULL
;
8027 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8028 return (const reg_entry
*) NULL
;
8030 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8031 return (const reg_entry
*) NULL
;
8033 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8034 return (const reg_entry
*) NULL
;
8036 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8037 if (!allow_index_reg
8038 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8039 return (const reg_entry
*) NULL
;
8041 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8042 || r
->reg_type
.bitfield
.reg64
)
8043 && (!cpu_arch_flags
.bitfield
.cpulm
8044 || !operand_type_equal (&r
->reg_type
, &control
))
8045 && flag_code
!= CODE_64BIT
)
8046 return (const reg_entry
*) NULL
;
8048 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8049 return (const reg_entry
*) NULL
;
8054 /* REG_STRING starts *before* REGISTER_PREFIX. */
8056 static const reg_entry
*
8057 parse_register (char *reg_string
, char **end_op
)
8061 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8062 r
= parse_real_register (reg_string
, end_op
);
8067 char *save
= input_line_pointer
;
8071 input_line_pointer
= reg_string
;
8072 c
= get_symbol_end ();
8073 symbolP
= symbol_find (reg_string
);
8074 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8076 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8078 know (e
->X_op
== O_register
);
8079 know (e
->X_add_number
>= 0
8080 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8081 r
= i386_regtab
+ e
->X_add_number
;
8082 *end_op
= input_line_pointer
;
8084 *input_line_pointer
= c
;
8085 input_line_pointer
= save
;
8091 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8094 char *end
= input_line_pointer
;
8097 r
= parse_register (name
, &input_line_pointer
);
8098 if (r
&& end
<= input_line_pointer
)
8100 *nextcharP
= *input_line_pointer
;
8101 *input_line_pointer
= 0;
8102 e
->X_op
= O_register
;
8103 e
->X_add_number
= r
- i386_regtab
;
8106 input_line_pointer
= end
;
8108 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8112 md_operand (expressionS
*e
)
8117 switch (*input_line_pointer
)
8119 case REGISTER_PREFIX
:
8120 r
= parse_real_register (input_line_pointer
, &end
);
8123 e
->X_op
= O_register
;
8124 e
->X_add_number
= r
- i386_regtab
;
8125 input_line_pointer
= end
;
8130 gas_assert (intel_syntax
);
8131 end
= input_line_pointer
++;
8133 if (*input_line_pointer
== ']')
8135 ++input_line_pointer
;
8136 e
->X_op_symbol
= make_expr_symbol (e
);
8137 e
->X_add_symbol
= NULL
;
8138 e
->X_add_number
= 0;
8144 input_line_pointer
= end
;
8151 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8152 const char *md_shortopts
= "kVQ:sqn";
8154 const char *md_shortopts
= "qn";
8157 #define OPTION_32 (OPTION_MD_BASE + 0)
8158 #define OPTION_64 (OPTION_MD_BASE + 1)
8159 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8160 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8161 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8162 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8163 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8164 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8165 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8166 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8167 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8168 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8169 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8170 #define OPTION_X32 (OPTION_MD_BASE + 13)
8172 struct option md_longopts
[] =
8174 {"32", no_argument
, NULL
, OPTION_32
},
8175 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8176 || defined (TE_PE) || defined (TE_PEP))
8177 {"64", no_argument
, NULL
, OPTION_64
},
8179 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8180 {"x32", no_argument
, NULL
, OPTION_X32
},
8182 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8183 {"march", required_argument
, NULL
, OPTION_MARCH
},
8184 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8185 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8186 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8187 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8188 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8189 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8190 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8191 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8192 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8193 {NULL
, no_argument
, NULL
, 0}
8195 size_t md_longopts_size
= sizeof (md_longopts
);
8198 md_parse_option (int c
, char *arg
)
8206 optimize_align_code
= 0;
8213 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8214 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8215 should be emitted or not. FIXME: Not implemented. */
8219 /* -V: SVR4 argument to print version ID. */
8221 print_version_id ();
8224 /* -k: Ignore for FreeBSD compatibility. */
8229 /* -s: On i386 Solaris, this tells the native assembler to use
8230 .stab instead of .stab.excl. We always use .stab anyhow. */
8233 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8234 || defined (TE_PE) || defined (TE_PEP))
8237 const char **list
, **l
;
8239 list
= bfd_target_list ();
8240 for (l
= list
; *l
!= NULL
; l
++)
8241 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8242 || strcmp (*l
, "coff-x86-64") == 0
8243 || strcmp (*l
, "pe-x86-64") == 0
8244 || strcmp (*l
, "pei-x86-64") == 0)
8246 default_arch
= "x86_64";
8250 as_fatal (_("No compiled in support for x86_64"));
8256 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8260 const char **list
, **l
;
8262 list
= bfd_target_list ();
8263 for (l
= list
; *l
!= NULL
; l
++)
8264 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8266 default_arch
= "x86_64:32";
8270 as_fatal (_("No compiled in support for 32bit x86_64"));
8274 as_fatal (_("32bit x86_64 is only supported for ELF"));
8279 default_arch
= "i386";
8283 #ifdef SVR4_COMMENT_CHARS
8288 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8290 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8294 i386_comment_chars
= n
;
8300 arch
= xstrdup (arg
);
8304 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8305 next
= strchr (arch
, '+');
8308 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8310 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8313 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8316 cpu_arch_name
= cpu_arch
[j
].name
;
8317 cpu_sub_arch_name
= NULL
;
8318 cpu_arch_flags
= cpu_arch
[j
].flags
;
8319 cpu_arch_isa
= cpu_arch
[j
].type
;
8320 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8321 if (!cpu_arch_tune_set
)
8323 cpu_arch_tune
= cpu_arch_isa
;
8324 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8328 else if (*cpu_arch
[j
].name
== '.'
8329 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8331 /* ISA entension. */
8332 i386_cpu_flags flags
;
8334 if (!cpu_arch
[j
].negated
)
8335 flags
= cpu_flags_or (cpu_arch_flags
,
8338 flags
= cpu_flags_and_not (cpu_arch_flags
,
8340 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8342 if (cpu_sub_arch_name
)
8344 char *name
= cpu_sub_arch_name
;
8345 cpu_sub_arch_name
= concat (name
,
8347 (const char *) NULL
);
8351 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8352 cpu_arch_flags
= flags
;
8353 cpu_arch_isa_flags
= flags
;
8359 if (j
>= ARRAY_SIZE (cpu_arch
))
8360 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8364 while (next
!= NULL
);
8369 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8370 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8372 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8374 cpu_arch_tune_set
= 1;
8375 cpu_arch_tune
= cpu_arch
[j
].type
;
8376 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8380 if (j
>= ARRAY_SIZE (cpu_arch
))
8381 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8384 case OPTION_MMNEMONIC
:
8385 if (strcasecmp (arg
, "att") == 0)
8387 else if (strcasecmp (arg
, "intel") == 0)
8390 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8393 case OPTION_MSYNTAX
:
8394 if (strcasecmp (arg
, "att") == 0)
8396 else if (strcasecmp (arg
, "intel") == 0)
8399 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8402 case OPTION_MINDEX_REG
:
8403 allow_index_reg
= 1;
8406 case OPTION_MNAKED_REG
:
8407 allow_naked_reg
= 1;
8410 case OPTION_MOLD_GCC
:
8414 case OPTION_MSSE2AVX
:
8418 case OPTION_MSSE_CHECK
:
8419 if (strcasecmp (arg
, "error") == 0)
8420 sse_check
= sse_check_error
;
8421 else if (strcasecmp (arg
, "warning") == 0)
8422 sse_check
= sse_check_warning
;
8423 else if (strcasecmp (arg
, "none") == 0)
8424 sse_check
= sse_check_none
;
8426 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8429 case OPTION_MAVXSCALAR
:
8430 if (strcasecmp (arg
, "128") == 0)
8432 else if (strcasecmp (arg
, "256") == 0)
8435 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8444 #define MESSAGE_TEMPLATE \
8448 show_arch (FILE *stream
, int ext
, int check
)
8450 static char message
[] = MESSAGE_TEMPLATE
;
8451 char *start
= message
+ 27;
8453 int size
= sizeof (MESSAGE_TEMPLATE
);
8460 left
= size
- (start
- message
);
8461 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8463 /* Should it be skipped? */
8464 if (cpu_arch
[j
].skip
)
8467 name
= cpu_arch
[j
].name
;
8468 len
= cpu_arch
[j
].len
;
8471 /* It is an extension. Skip if we aren't asked to show it. */
8482 /* It is an processor. Skip if we show only extension. */
8485 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8487 /* It is an impossible processor - skip. */
8491 /* Reserve 2 spaces for ", " or ",\0" */
8494 /* Check if there is any room. */
8502 p
= mempcpy (p
, name
, len
);
8506 /* Output the current message now and start a new one. */
8509 fprintf (stream
, "%s\n", message
);
8511 left
= size
- (start
- message
) - len
- 2;
8513 gas_assert (left
>= 0);
8515 p
= mempcpy (p
, name
, len
);
8520 fprintf (stream
, "%s\n", message
);
8524 md_show_usage (FILE *stream
)
8526 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8527 fprintf (stream
, _("\
8529 -V print assembler version number\n\
8532 fprintf (stream
, _("\
8533 -n Do not optimize code alignment\n\
8534 -q quieten some warnings\n"));
8535 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8536 fprintf (stream
, _("\
8539 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8540 || defined (TE_PE) || defined (TE_PEP))
8541 fprintf (stream
, _("\
8542 --32/--64/--x32 generate 32bit/64bit/x32 code\n"));
8544 #ifdef SVR4_COMMENT_CHARS
8545 fprintf (stream
, _("\
8546 --divide do not treat `/' as a comment character\n"));
8548 fprintf (stream
, _("\
8549 --divide ignored\n"));
8551 fprintf (stream
, _("\
8552 -march=CPU[,+EXTENSION...]\n\
8553 generate code for CPU and EXTENSION, CPU is one of:\n"));
8554 show_arch (stream
, 0, 1);
8555 fprintf (stream
, _("\
8556 EXTENSION is combination of:\n"));
8557 show_arch (stream
, 1, 0);
8558 fprintf (stream
, _("\
8559 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8560 show_arch (stream
, 0, 0);
8561 fprintf (stream
, _("\
8562 -msse2avx encode SSE instructions with VEX prefix\n"));
8563 fprintf (stream
, _("\
8564 -msse-check=[none|error|warning]\n\
8565 check SSE instructions\n"));
8566 fprintf (stream
, _("\
8567 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8569 fprintf (stream
, _("\
8570 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8571 fprintf (stream
, _("\
8572 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8573 fprintf (stream
, _("\
8574 -mindex-reg support pseudo index registers\n"));
8575 fprintf (stream
, _("\
8576 -mnaked-reg don't require `%%' prefix for registers\n"));
8577 fprintf (stream
, _("\
8578 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8581 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8582 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8583 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8585 /* Pick the target format to use. */
8588 i386_target_format (void)
8590 if (!strncmp (default_arch
, "x86_64", 6))
8592 update_code_flag (CODE_64BIT
, 1);
8593 if (default_arch
[6] == '\0')
8594 x86_elf_abi
= X86_64_ABI
;
8596 x86_elf_abi
= X86_64_X32_ABI
;
8598 else if (!strcmp (default_arch
, "i386"))
8599 update_code_flag (CODE_32BIT
, 1);
8601 as_fatal (_("Unknown architecture"));
8603 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8604 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8605 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8606 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8608 switch (OUTPUT_FLAVOR
)
8610 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8611 case bfd_target_aout_flavour
:
8612 return AOUT_TARGET_FORMAT
;
8614 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8615 # if defined (TE_PE) || defined (TE_PEP)
8616 case bfd_target_coff_flavour
:
8617 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8618 # elif defined (TE_GO32)
8619 case bfd_target_coff_flavour
:
8622 case bfd_target_coff_flavour
:
8626 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8627 case bfd_target_elf_flavour
:
8631 switch (x86_elf_abi
)
8634 format
= ELF_TARGET_FORMAT
;
8637 use_rela_relocations
= 1;
8639 format
= ELF_TARGET_FORMAT64
;
8641 case X86_64_X32_ABI
:
8642 use_rela_relocations
= 1;
8644 disallow_64bit_reloc
= 1;
8645 x86_cie_data_alignment
= -4;
8646 format
= ELF_TARGET_FORMAT32
;
8649 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8651 if (x86_elf_abi
!= X86_64_ABI
)
8652 as_fatal (_("Intel L1OM is 64bit only"));
8653 return ELF_TARGET_L1OM_FORMAT
;
8659 #if defined (OBJ_MACH_O)
8660 case bfd_target_mach_o_flavour
:
8661 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8669 #endif /* OBJ_MAYBE_ more than one */
8671 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8673 i386_elf_emit_arch_note (void)
8675 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8678 asection
*seg
= now_seg
;
8679 subsegT subseg
= now_subseg
;
8680 Elf_Internal_Note i_note
;
8681 Elf_External_Note e_note
;
8682 asection
*note_secp
;
8685 /* Create the .note section. */
8686 note_secp
= subseg_new (".note", 0);
8687 bfd_set_section_flags (stdoutput
,
8689 SEC_HAS_CONTENTS
| SEC_READONLY
);
8691 /* Process the arch string. */
8692 len
= strlen (cpu_arch_name
);
8694 i_note
.namesz
= len
+ 1;
8696 i_note
.type
= NT_ARCH
;
8697 p
= frag_more (sizeof (e_note
.namesz
));
8698 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8699 p
= frag_more (sizeof (e_note
.descsz
));
8700 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8701 p
= frag_more (sizeof (e_note
.type
));
8702 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8703 p
= frag_more (len
+ 1);
8704 strcpy (p
, cpu_arch_name
);
8706 frag_align (2, 0, 0);
8708 subseg_set (seg
, subseg
);
8714 md_undefined_symbol (name
)
8717 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8718 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8719 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8720 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8724 if (symbol_find (name
))
8725 as_bad (_("GOT already in symbol table"));
8726 GOT_symbol
= symbol_new (name
, undefined_section
,
8727 (valueT
) 0, &zero_address_frag
);
8734 /* Round up a section size to the appropriate boundary. */
8737 md_section_align (segment
, size
)
8738 segT segment ATTRIBUTE_UNUSED
;
8741 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8742 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8744 /* For a.out, force the section size to be aligned. If we don't do
8745 this, BFD will align it for us, but it will not write out the
8746 final bytes of the section. This may be a bug in BFD, but it is
8747 easier to fix it here since that is how the other a.out targets
8751 align
= bfd_get_section_alignment (stdoutput
, segment
);
8752 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8759 /* On the i386, PC-relative offsets are relative to the start of the
8760 next instruction. That is, the address of the offset, plus its
8761 size, since the offset is always the last part of the insn. */
8764 md_pcrel_from (fixS
*fixP
)
8766 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8772 s_bss (int ignore ATTRIBUTE_UNUSED
)
8776 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8778 obj_elf_section_change_hook ();
8780 temp
= get_absolute_expression ();
8781 subseg_set (bss_section
, (subsegT
) temp
);
8782 demand_empty_rest_of_line ();
8788 i386_validate_fix (fixS
*fixp
)
8790 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8792 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8796 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8801 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8803 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8810 tc_gen_reloc (section
, fixp
)
8811 asection
*section ATTRIBUTE_UNUSED
;
8815 bfd_reloc_code_real_type code
;
8817 switch (fixp
->fx_r_type
)
8819 case BFD_RELOC_X86_64_PLT32
:
8820 case BFD_RELOC_X86_64_GOT32
:
8821 case BFD_RELOC_X86_64_GOTPCREL
:
8822 case BFD_RELOC_386_PLT32
:
8823 case BFD_RELOC_386_GOT32
:
8824 case BFD_RELOC_386_GOTOFF
:
8825 case BFD_RELOC_386_GOTPC
:
8826 case BFD_RELOC_386_TLS_GD
:
8827 case BFD_RELOC_386_TLS_LDM
:
8828 case BFD_RELOC_386_TLS_LDO_32
:
8829 case BFD_RELOC_386_TLS_IE_32
:
8830 case BFD_RELOC_386_TLS_IE
:
8831 case BFD_RELOC_386_TLS_GOTIE
:
8832 case BFD_RELOC_386_TLS_LE_32
:
8833 case BFD_RELOC_386_TLS_LE
:
8834 case BFD_RELOC_386_TLS_GOTDESC
:
8835 case BFD_RELOC_386_TLS_DESC_CALL
:
8836 case BFD_RELOC_X86_64_TLSGD
:
8837 case BFD_RELOC_X86_64_TLSLD
:
8838 case BFD_RELOC_X86_64_DTPOFF32
:
8839 case BFD_RELOC_X86_64_DTPOFF64
:
8840 case BFD_RELOC_X86_64_GOTTPOFF
:
8841 case BFD_RELOC_X86_64_TPOFF32
:
8842 case BFD_RELOC_X86_64_TPOFF64
:
8843 case BFD_RELOC_X86_64_GOTOFF64
:
8844 case BFD_RELOC_X86_64_GOTPC32
:
8845 case BFD_RELOC_X86_64_GOT64
:
8846 case BFD_RELOC_X86_64_GOTPCREL64
:
8847 case BFD_RELOC_X86_64_GOTPC64
:
8848 case BFD_RELOC_X86_64_GOTPLT64
:
8849 case BFD_RELOC_X86_64_PLTOFF64
:
8850 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8851 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8853 case BFD_RELOC_VTABLE_ENTRY
:
8854 case BFD_RELOC_VTABLE_INHERIT
:
8856 case BFD_RELOC_32_SECREL
:
8858 code
= fixp
->fx_r_type
;
8860 case BFD_RELOC_X86_64_32S
:
8861 if (!fixp
->fx_pcrel
)
8863 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8864 code
= fixp
->fx_r_type
;
8870 switch (fixp
->fx_size
)
8873 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8874 _("can not do %d byte pc-relative relocation"),
8876 code
= BFD_RELOC_32_PCREL
;
8878 case 1: code
= BFD_RELOC_8_PCREL
; break;
8879 case 2: code
= BFD_RELOC_16_PCREL
; break;
8880 case 4: code
= BFD_RELOC_32_PCREL
; break;
8882 case 8: code
= BFD_RELOC_64_PCREL
; break;
8888 switch (fixp
->fx_size
)
8891 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8892 _("can not do %d byte relocation"),
8894 code
= BFD_RELOC_32
;
8896 case 1: code
= BFD_RELOC_8
; break;
8897 case 2: code
= BFD_RELOC_16
; break;
8898 case 4: code
= BFD_RELOC_32
; break;
8900 case 8: code
= BFD_RELOC_64
; break;
8907 if ((code
== BFD_RELOC_32
8908 || code
== BFD_RELOC_32_PCREL
8909 || code
== BFD_RELOC_X86_64_32S
)
8911 && fixp
->fx_addsy
== GOT_symbol
)
8914 code
= BFD_RELOC_386_GOTPC
;
8916 code
= BFD_RELOC_X86_64_GOTPC32
;
8918 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8920 && fixp
->fx_addsy
== GOT_symbol
)
8922 code
= BFD_RELOC_X86_64_GOTPC64
;
8925 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8926 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8927 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8929 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8931 if (!use_rela_relocations
)
8933 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8934 vtable entry to be used in the relocation's section offset. */
8935 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8936 rel
->address
= fixp
->fx_offset
;
8937 #if defined (OBJ_COFF) && defined (TE_PE)
8938 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8939 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8944 /* Use the rela in 64bit mode. */
8947 if (disallow_64bit_reloc
)
8951 case BFD_RELOC_X86_64_DTPOFF64
:
8952 case BFD_RELOC_X86_64_TPOFF64
:
8953 case BFD_RELOC_64_PCREL
:
8954 case BFD_RELOC_X86_64_GOTOFF64
:
8955 case BFD_RELOC_X86_64_GOT64
:
8956 case BFD_RELOC_X86_64_GOTPCREL64
:
8957 case BFD_RELOC_X86_64_GOTPC64
:
8958 case BFD_RELOC_X86_64_GOTPLT64
:
8959 case BFD_RELOC_X86_64_PLTOFF64
:
8960 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8961 _("cannot represent relocation type %s in x32 mode"),
8962 bfd_get_reloc_code_name (code
));
8968 if (!fixp
->fx_pcrel
)
8969 rel
->addend
= fixp
->fx_offset
;
8973 case BFD_RELOC_X86_64_PLT32
:
8974 case BFD_RELOC_X86_64_GOT32
:
8975 case BFD_RELOC_X86_64_GOTPCREL
:
8976 case BFD_RELOC_X86_64_TLSGD
:
8977 case BFD_RELOC_X86_64_TLSLD
:
8978 case BFD_RELOC_X86_64_GOTTPOFF
:
8979 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8980 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8981 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8984 rel
->addend
= (section
->vma
8986 + fixp
->fx_addnumber
8987 + md_pcrel_from (fixp
));
8992 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8993 if (rel
->howto
== NULL
)
8995 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8996 _("cannot represent relocation type %s"),
8997 bfd_get_reloc_code_name (code
));
8998 /* Set howto to a garbage value so that we can keep going. */
8999 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
9000 gas_assert (rel
->howto
!= NULL
);
9006 #include "tc-i386-intel.c"
9009 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9011 int saved_naked_reg
;
9012 char saved_register_dot
;
9014 saved_naked_reg
= allow_naked_reg
;
9015 allow_naked_reg
= 1;
9016 saved_register_dot
= register_chars
['.'];
9017 register_chars
['.'] = '.';
9018 allow_pseudo_reg
= 1;
9019 expression_and_evaluate (exp
);
9020 allow_pseudo_reg
= 0;
9021 register_chars
['.'] = saved_register_dot
;
9022 allow_naked_reg
= saved_naked_reg
;
9024 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
9026 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
9028 exp
->X_op
= O_constant
;
9029 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
9030 .dw2_regnum
[flag_code
>> 1];
9033 exp
->X_op
= O_illegal
;
9038 tc_x86_frame_initial_instructions (void)
9040 static unsigned int sp_regno
[2];
9042 if (!sp_regno
[flag_code
>> 1])
9044 char *saved_input
= input_line_pointer
;
9045 char sp
[][4] = {"esp", "rsp"};
9048 input_line_pointer
= sp
[flag_code
>> 1];
9049 tc_x86_parse_to_dw2regnum (&exp
);
9050 gas_assert (exp
.X_op
== O_constant
);
9051 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9052 input_line_pointer
= saved_input
;
9055 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_stack_alignment
);
9056 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_stack_alignment
);
9060 i386_elf_section_type (const char *str
, size_t len
)
9062 if (flag_code
== CODE_64BIT
9063 && len
== sizeof ("unwind") - 1
9064 && strncmp (str
, "unwind", 6) == 0)
9065 return SHT_X86_64_UNWIND
;
9072 i386_solaris_fix_up_eh_frame (segT sec
)
9074 if (flag_code
== CODE_64BIT
)
9075 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9081 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9085 exp
.X_op
= O_secrel
;
9086 exp
.X_add_symbol
= symbol
;
9087 exp
.X_add_number
= 0;
9088 emit_expr (&exp
, size
);
9092 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9093 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9096 x86_64_section_letter (int letter
, char **ptr_msg
)
9098 if (flag_code
== CODE_64BIT
)
9101 return SHF_X86_64_LARGE
;
9103 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9106 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9111 x86_64_section_word (char *str
, size_t len
)
9113 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9114 return SHF_X86_64_LARGE
;
9120 handle_large_common (int small ATTRIBUTE_UNUSED
)
9122 if (flag_code
!= CODE_64BIT
)
9124 s_comm_internal (0, elf_common_parse
);
9125 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9129 static segT lbss_section
;
9130 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9131 asection
*saved_bss_section
= bss_section
;
9133 if (lbss_section
== NULL
)
9135 flagword applicable
;
9137 subsegT subseg
= now_subseg
;
9139 /* The .lbss section is for local .largecomm symbols. */
9140 lbss_section
= subseg_new (".lbss", 0);
9141 applicable
= bfd_applicable_section_flags (stdoutput
);
9142 bfd_set_section_flags (stdoutput
, lbss_section
,
9143 applicable
& SEC_ALLOC
);
9144 seg_info (lbss_section
)->bss
= 1;
9146 subseg_set (seg
, subseg
);
9149 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9150 bss_section
= lbss_section
;
9152 s_comm_internal (0, elf_common_parse
);
9154 elf_com_section_ptr
= saved_com_section_ptr
;
9155 bss_section
= saved_bss_section
;
9158 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */