1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_att_operand (char *);
175 static int i386_intel_operand (char *, int);
176 static const reg_entry
*parse_register (char *, char **);
177 static char *parse_insn (char *, char *);
178 static char *parse_operands (char *, const char *);
179 static void swap_operands (void);
180 static void swap_2_operands (int, int);
181 static void optimize_imm (void);
182 static void optimize_disp (void);
183 static const template *match_template (void);
184 static int check_string (void);
185 static int process_suffix (void);
186 static int check_byte_reg (void);
187 static int check_long_reg (void);
188 static int check_qword_reg (void);
189 static int check_word_reg (void);
190 static int finalize_imm (void);
191 static void process_drex (void);
192 static int process_operands (void);
193 static const seg_entry
*build_modrm_byte (void);
194 static void output_insn (void);
195 static void output_imm (fragS
*, offsetT
);
196 static void output_disp (fragS
*, offsetT
);
198 static void s_bss (int);
200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
201 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
204 static const char *default_arch
= DEFAULT_ARCH
;
209 /* VEX prefix is either 2 byte or 3 byte. */
210 unsigned char bytes
[3];
212 /* Destination or source register specifier. */
213 const reg_entry
*register_specifier
;
216 /* 'md_assemble ()' gathers together information and puts it into a
223 const reg_entry
*regs
;
228 /* TM holds the template for the insn were currently assembling. */
231 /* SUFFIX holds the instruction size suffix for byte, word, dword
232 or qword, if given. */
235 /* OPERANDS gives the number of given operands. */
236 unsigned int operands
;
238 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
239 of given register, displacement, memory operands and immediate
241 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
243 /* TYPES [i] is the type (see above #defines) which tells us how to
244 use OP[i] for the corresponding operand. */
245 i386_operand_type types
[MAX_OPERANDS
];
247 /* Displacement expression, immediate expression, or register for each
249 union i386_op op
[MAX_OPERANDS
];
251 /* Flags for operands. */
252 unsigned int flags
[MAX_OPERANDS
];
253 #define Operand_PCrel 1
255 /* Relocation type for operand */
256 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
258 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
259 the base index byte below. */
260 const reg_entry
*base_reg
;
261 const reg_entry
*index_reg
;
262 unsigned int log2_scale_factor
;
264 /* SEG gives the seg_entries of this insn. They are zero unless
265 explicit segment overrides are given. */
266 const seg_entry
*seg
[2];
268 /* PREFIX holds all the given prefix opcodes (usually null).
269 PREFIXES is the number of prefix opcodes. */
270 unsigned int prefixes
;
271 unsigned char prefix
[MAX_PREFIXES
];
273 /* RM and SIB are the modrm byte and the sib byte where the
274 addressing modes of this insn are encoded. DREX is the byte
275 added by the SSE5 instructions. */
283 /* Swap operand in encoding. */
284 unsigned int swap_operand
: 1;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The names used to print error messages. */
395 static const char *flag_code_names
[] =
402 /* 1 for intel syntax,
404 static int intel_syntax
= 0;
406 /* 1 for intel mnemonic,
407 0 if att mnemonic. */
408 static int intel_mnemonic
= !SYSV386_COMPAT
;
410 /* 1 if support old (<= 2.8.1) versions of gcc. */
411 static int old_gcc
= OLDGCC_COMPAT
;
413 /* 1 if pseudo registers are permitted. */
414 static int allow_pseudo_reg
= 0;
416 /* 1 if register prefix % not required. */
417 static int allow_naked_reg
= 0;
419 /* 1 if pseudo index register, eiz/riz, is allowed . */
420 static int allow_index_reg
= 0;
430 /* Register prefix used for error message. */
431 static const char *register_prefix
= "%";
433 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
434 leave, push, and pop instructions so that gcc has the same stack
435 frame as in 32 bit mode. */
436 static char stackop_size
= '\0';
438 /* Non-zero to optimize code alignment. */
439 int optimize_align_code
= 1;
441 /* Non-zero to quieten some warnings. */
442 static int quiet_warnings
= 0;
445 static const char *cpu_arch_name
= NULL
;
446 static char *cpu_sub_arch_name
= NULL
;
448 /* CPU feature flags. */
449 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
451 /* If we have selected a cpu we are generating instructions for. */
452 static int cpu_arch_tune_set
= 0;
454 /* Cpu we are generating instructions for. */
455 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
457 /* CPU feature flags of cpu we are generating instructions for. */
458 static i386_cpu_flags cpu_arch_tune_flags
;
460 /* CPU instruction set architecture used. */
461 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of instruction set architecture used. */
464 i386_cpu_flags cpu_arch_isa_flags
;
466 /* If set, conditional jumps are not automatically promoted to handle
467 larger than a byte offset. */
468 static unsigned int no_cond_jump_promotion
= 0;
470 /* Encode SSE instructions with VEX prefix. */
471 static unsigned int sse2avx
;
473 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
474 static symbolS
*GOT_symbol
;
476 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
477 unsigned int x86_dwarf2_return_column
;
479 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
480 int x86_cie_data_alignment
;
482 /* Interface to relax_segment.
483 There are 3 major relax states for 386 jump insns because the
484 different types of jumps add different sizes to frags when we're
485 figuring out what sort of jump to choose to reach a given label. */
488 #define UNCOND_JUMP 0
490 #define COND_JUMP86 2
495 #define SMALL16 (SMALL | CODE16)
497 #define BIG16 (BIG | CODE16)
501 #define INLINE __inline__
507 #define ENCODE_RELAX_STATE(type, size) \
508 ((relax_substateT) (((type) << 2) | (size)))
509 #define TYPE_FROM_RELAX_STATE(s) \
511 #define DISP_SIZE_FROM_RELAX_STATE(s) \
512 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
514 /* This table is used by relax_frag to promote short jumps to long
515 ones where necessary. SMALL (short) jumps may be promoted to BIG
516 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
517 don't allow a short jump in a 32 bit code segment to be promoted to
518 a 16 bit offset jump because it's slower (requires data size
519 prefix), and doesn't work, unless the destination is in the bottom
520 64k of the code segment (The top 16 bits of eip are zeroed). */
522 const relax_typeS md_relax_table
[] =
525 1) most positive reach of this state,
526 2) most negative reach of this state,
527 3) how many bytes this mode will have in the variable part of the frag
528 4) which index into the table to try if we can't fit into this one. */
530 /* UNCOND_JUMP states. */
531 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
532 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
533 /* dword jmp adds 4 bytes to frag:
534 0 extra opcode bytes, 4 displacement bytes. */
536 /* word jmp adds 2 byte2 to frag:
537 0 extra opcode bytes, 2 displacement bytes. */
540 /* COND_JUMP states. */
541 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
542 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
543 /* dword conditionals adds 5 bytes to frag:
544 1 extra opcode byte, 4 displacement bytes. */
546 /* word conditionals add 3 bytes to frag:
547 1 extra opcode byte, 2 displacement bytes. */
550 /* COND_JUMP86 states. */
551 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
552 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
553 /* dword conditionals adds 5 bytes to frag:
554 1 extra opcode byte, 4 displacement bytes. */
556 /* word conditionals add 4 bytes to frag:
557 1 displacement byte and a 3 byte long branch insn. */
561 static const arch_entry cpu_arch
[] =
563 { "generic32", PROCESSOR_GENERIC32
,
564 CPU_GENERIC32_FLAGS
},
565 { "generic64", PROCESSOR_GENERIC64
,
566 CPU_GENERIC64_FLAGS
},
567 { "i8086", PROCESSOR_UNKNOWN
,
569 { "i186", PROCESSOR_UNKNOWN
,
571 { "i286", PROCESSOR_UNKNOWN
,
573 { "i386", PROCESSOR_I386
,
575 { "i486", PROCESSOR_I486
,
577 { "i586", PROCESSOR_PENTIUM
,
579 { "i686", PROCESSOR_PENTIUMPRO
,
581 { "pentium", PROCESSOR_PENTIUM
,
583 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
585 { "pentiumii", PROCESSOR_PENTIUMPRO
,
587 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
589 { "pentium4", PROCESSOR_PENTIUM4
,
591 { "prescott", PROCESSOR_NOCONA
,
593 { "nocona", PROCESSOR_NOCONA
,
595 { "yonah", PROCESSOR_CORE
,
597 { "core", PROCESSOR_CORE
,
599 { "merom", PROCESSOR_CORE2
,
601 { "core2", PROCESSOR_CORE2
,
603 { "corei7", PROCESSOR_COREI7
,
605 { "k6", PROCESSOR_K6
,
607 { "k6_2", PROCESSOR_K6
,
609 { "athlon", PROCESSOR_ATHLON
,
611 { "sledgehammer", PROCESSOR_K8
,
613 { "opteron", PROCESSOR_K8
,
615 { "k8", PROCESSOR_K8
,
617 { "amdfam10", PROCESSOR_AMDFAM10
,
618 CPU_AMDFAM10_FLAGS
},
619 { ".mmx", PROCESSOR_UNKNOWN
,
621 { ".sse", PROCESSOR_UNKNOWN
,
623 { ".sse2", PROCESSOR_UNKNOWN
,
625 { ".sse3", PROCESSOR_UNKNOWN
,
627 { ".ssse3", PROCESSOR_UNKNOWN
,
629 { ".sse4.1", PROCESSOR_UNKNOWN
,
631 { ".sse4.2", PROCESSOR_UNKNOWN
,
633 { ".sse4", PROCESSOR_UNKNOWN
,
635 { ".avx", PROCESSOR_UNKNOWN
,
637 { ".vmx", PROCESSOR_UNKNOWN
,
639 { ".smx", PROCESSOR_UNKNOWN
,
641 { ".xsave", PROCESSOR_UNKNOWN
,
643 { ".aes", PROCESSOR_UNKNOWN
,
645 { ".pclmul", PROCESSOR_UNKNOWN
,
647 { ".clmul", PROCESSOR_UNKNOWN
,
649 { ".fma", PROCESSOR_UNKNOWN
,
651 { ".movbe", PROCESSOR_UNKNOWN
,
653 { ".ept", PROCESSOR_UNKNOWN
,
655 { ".clflush", PROCESSOR_UNKNOWN
,
657 { ".syscall", PROCESSOR_UNKNOWN
,
659 { ".rdtscp", PROCESSOR_UNKNOWN
,
661 { ".3dnow", PROCESSOR_UNKNOWN
,
663 { ".3dnowa", PROCESSOR_UNKNOWN
,
665 { ".padlock", PROCESSOR_UNKNOWN
,
667 { ".pacifica", PROCESSOR_UNKNOWN
,
669 { ".svme", PROCESSOR_UNKNOWN
,
671 { ".sse4a", PROCESSOR_UNKNOWN
,
673 { ".abm", PROCESSOR_UNKNOWN
,
675 { ".sse5", PROCESSOR_UNKNOWN
,
680 /* Like s_lcomm_internal in gas/read.c but the alignment string
681 is allowed to be optional. */
684 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
691 && *input_line_pointer
== ',')
693 align
= parse_align (needs_align
- 1);
695 if (align
== (addressT
) -1)
710 bss_alloc (symbolP
, size
, align
);
715 pe_lcomm (int needs_align
)
717 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
721 const pseudo_typeS md_pseudo_table
[] =
723 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
724 {"align", s_align_bytes
, 0},
726 {"align", s_align_ptwo
, 0},
728 {"arch", set_cpu_arch
, 0},
732 {"lcomm", pe_lcomm
, 1},
734 {"ffloat", float_cons
, 'f'},
735 {"dfloat", float_cons
, 'd'},
736 {"tfloat", float_cons
, 'x'},
738 {"slong", signed_cons
, 4},
739 {"noopt", s_ignore
, 0},
740 {"optim", s_ignore
, 0},
741 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
742 {"code16", set_code_flag
, CODE_16BIT
},
743 {"code32", set_code_flag
, CODE_32BIT
},
744 {"code64", set_code_flag
, CODE_64BIT
},
745 {"intel_syntax", set_intel_syntax
, 1},
746 {"att_syntax", set_intel_syntax
, 0},
747 {"intel_mnemonic", set_intel_mnemonic
, 1},
748 {"att_mnemonic", set_intel_mnemonic
, 0},
749 {"allow_index_reg", set_allow_index_reg
, 1},
750 {"disallow_index_reg", set_allow_index_reg
, 0},
751 {"sse_check", set_sse_check
, 0},
752 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
753 {"largecomm", handle_large_common
, 0},
755 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
756 {"loc", dwarf2_directive_loc
, 0},
757 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
760 {"secrel32", pe_directive_secrel
, 0},
765 /* For interface with expression (). */
766 extern char *input_line_pointer
;
768 /* Hash table for instruction mnemonic lookup. */
769 static struct hash_control
*op_hash
;
771 /* Hash table for register lookup. */
772 static struct hash_control
*reg_hash
;
775 i386_align_code (fragS
*fragP
, int count
)
777 /* Various efficient no-op patterns for aligning code labels.
778 Note: Don't try to assemble the instructions in the comments.
779 0L and 0w are not legal. */
780 static const char f32_1
[] =
782 static const char f32_2
[] =
783 {0x66,0x90}; /* xchg %ax,%ax */
784 static const char f32_3
[] =
785 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
786 static const char f32_4
[] =
787 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
788 static const char f32_5
[] =
790 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
791 static const char f32_6
[] =
792 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
793 static const char f32_7
[] =
794 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
795 static const char f32_8
[] =
797 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
798 static const char f32_9
[] =
799 {0x89,0xf6, /* movl %esi,%esi */
800 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
801 static const char f32_10
[] =
802 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
803 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
804 static const char f32_11
[] =
805 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_12
[] =
808 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
809 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
810 static const char f32_13
[] =
811 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_14
[] =
814 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
815 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
816 static const char f16_3
[] =
817 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
818 static const char f16_4
[] =
819 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
820 static const char f16_5
[] =
822 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
823 static const char f16_6
[] =
824 {0x89,0xf6, /* mov %si,%si */
825 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
826 static const char f16_7
[] =
827 {0x8d,0x74,0x00, /* lea 0(%si),%si */
828 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
829 static const char f16_8
[] =
830 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
832 static const char jump_31
[] =
833 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
834 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
835 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
836 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
837 static const char *const f32_patt
[] = {
838 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
839 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
841 static const char *const f16_patt
[] = {
842 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
845 static const char alt_3
[] =
847 /* nopl 0(%[re]ax) */
848 static const char alt_4
[] =
849 {0x0f,0x1f,0x40,0x00};
850 /* nopl 0(%[re]ax,%[re]ax,1) */
851 static const char alt_5
[] =
852 {0x0f,0x1f,0x44,0x00,0x00};
853 /* nopw 0(%[re]ax,%[re]ax,1) */
854 static const char alt_6
[] =
855 {0x66,0x0f,0x1f,0x44,0x00,0x00};
856 /* nopl 0L(%[re]ax) */
857 static const char alt_7
[] =
858 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
859 /* nopl 0L(%[re]ax,%[re]ax,1) */
860 static const char alt_8
[] =
861 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 /* nopw 0L(%[re]ax,%[re]ax,1) */
863 static const char alt_9
[] =
864 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
865 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
866 static const char alt_10
[] =
867 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
869 nopw %cs:0L(%[re]ax,%[re]ax,1) */
870 static const char alt_long_11
[] =
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_12
[] =
879 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
883 nopw %cs:0L(%[re]ax,%[re]ax,1) */
884 static const char alt_long_13
[] =
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_14
[] =
899 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
905 nopw %cs:0L(%[re]ax,%[re]ax,1) */
906 static const char alt_long_15
[] =
912 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopl 0(%[re]ax,%[re]ax,1)
914 nopw 0(%[re]ax,%[re]ax,1) */
915 static const char alt_short_11
[] =
916 {0x0f,0x1f,0x44,0x00,0x00,
917 0x66,0x0f,0x1f,0x44,0x00,0x00};
918 /* nopw 0(%[re]ax,%[re]ax,1)
919 nopw 0(%[re]ax,%[re]ax,1) */
920 static const char alt_short_12
[] =
921 {0x66,0x0f,0x1f,0x44,0x00,0x00,
922 0x66,0x0f,0x1f,0x44,0x00,0x00};
923 /* nopw 0(%[re]ax,%[re]ax,1)
925 static const char alt_short_13
[] =
926 {0x66,0x0f,0x1f,0x44,0x00,0x00,
927 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
930 static const char alt_short_14
[] =
931 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
932 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
934 nopl 0L(%[re]ax,%[re]ax,1) */
935 static const char alt_short_15
[] =
936 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
937 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
938 static const char *const alt_short_patt
[] = {
939 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
940 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
941 alt_short_14
, alt_short_15
943 static const char *const alt_long_patt
[] = {
944 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
945 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
946 alt_long_14
, alt_long_15
949 /* Only align for at least a positive non-zero boundary. */
950 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
953 /* We need to decide which NOP sequence to use for 32bit and
954 64bit. When -mtune= is used:
956 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
957 PROCESSOR_GENERIC32, f32_patt will be used.
958 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
959 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
960 PROCESSOR_GENERIC64, alt_long_patt will be used.
961 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
962 PROCESSOR_AMDFAM10, alt_short_patt will be used.
964 When -mtune= isn't used, alt_long_patt will be used if
965 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
968 When -march= or .arch is used, we can't use anything beyond
969 cpu_arch_isa_flags. */
971 if (flag_code
== CODE_16BIT
)
975 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
977 /* Adjust jump offset. */
978 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
981 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
982 f16_patt
[count
- 1], count
);
986 const char *const *patt
= NULL
;
988 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
990 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
991 switch (cpu_arch_tune
)
993 case PROCESSOR_UNKNOWN
:
994 /* We use cpu_arch_isa_flags to check if we SHOULD
995 optimize for Cpu686. */
996 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
997 patt
= alt_long_patt
;
1001 case PROCESSOR_PENTIUMPRO
:
1002 case PROCESSOR_PENTIUM4
:
1003 case PROCESSOR_NOCONA
:
1004 case PROCESSOR_CORE
:
1005 case PROCESSOR_CORE2
:
1006 case PROCESSOR_COREI7
:
1007 case PROCESSOR_GENERIC64
:
1008 patt
= alt_long_patt
;
1011 case PROCESSOR_ATHLON
:
1013 case PROCESSOR_AMDFAM10
:
1014 patt
= alt_short_patt
;
1016 case PROCESSOR_I386
:
1017 case PROCESSOR_I486
:
1018 case PROCESSOR_PENTIUM
:
1019 case PROCESSOR_GENERIC32
:
1026 switch (fragP
->tc_frag_data
.tune
)
1028 case PROCESSOR_UNKNOWN
:
1029 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1030 PROCESSOR_UNKNOWN. */
1034 case PROCESSOR_I386
:
1035 case PROCESSOR_I486
:
1036 case PROCESSOR_PENTIUM
:
1038 case PROCESSOR_ATHLON
:
1040 case PROCESSOR_AMDFAM10
:
1041 case PROCESSOR_GENERIC32
:
1042 /* We use cpu_arch_isa_flags to check if we CAN optimize
1044 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1045 patt
= alt_short_patt
;
1049 case PROCESSOR_PENTIUMPRO
:
1050 case PROCESSOR_PENTIUM4
:
1051 case PROCESSOR_NOCONA
:
1052 case PROCESSOR_CORE
:
1053 case PROCESSOR_CORE2
:
1054 case PROCESSOR_COREI7
:
1055 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1056 patt
= alt_long_patt
;
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1066 if (patt
== f32_patt
)
1068 /* If the padding is less than 15 bytes, we use the normal
1069 ones. Otherwise, we use a jump instruction and adjust
1072 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1073 patt
[count
- 1], count
);
1076 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1078 /* Adjust jump offset. */
1079 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1084 /* Maximum length of an instruction is 15 byte. If the
1085 padding is greater than 15 bytes and we don't use jump,
1086 we have to break it into smaller pieces. */
1087 int padding
= count
;
1088 while (padding
> 15)
1091 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1096 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1097 patt
[padding
- 1], padding
);
1100 fragP
->fr_var
= count
;
1104 operand_type_all_zero (const union i386_operand_type
*x
)
1106 switch (ARRAY_SIZE(x
->array
))
1115 return !x
->array
[0];
1122 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1124 switch (ARRAY_SIZE(x
->array
))
1139 operand_type_equal (const union i386_operand_type
*x
,
1140 const union i386_operand_type
*y
)
1142 switch (ARRAY_SIZE(x
->array
))
1145 if (x
->array
[2] != y
->array
[2])
1148 if (x
->array
[1] != y
->array
[1])
1151 return x
->array
[0] == y
->array
[0];
1159 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1161 switch (ARRAY_SIZE(x
->array
))
1170 return !x
->array
[0];
1177 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1179 switch (ARRAY_SIZE(x
->array
))
1194 cpu_flags_equal (const union i386_cpu_flags
*x
,
1195 const union i386_cpu_flags
*y
)
1197 switch (ARRAY_SIZE(x
->array
))
1200 if (x
->array
[2] != y
->array
[2])
1203 if (x
->array
[1] != y
->array
[1])
1206 return x
->array
[0] == y
->array
[0];
1214 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1216 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1217 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1220 static INLINE i386_cpu_flags
1221 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1223 switch (ARRAY_SIZE (x
.array
))
1226 x
.array
[2] &= y
.array
[2];
1228 x
.array
[1] &= y
.array
[1];
1230 x
.array
[0] &= y
.array
[0];
1238 static INLINE i386_cpu_flags
1239 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1241 switch (ARRAY_SIZE (x
.array
))
1244 x
.array
[2] |= y
.array
[2];
1246 x
.array
[1] |= y
.array
[1];
1248 x
.array
[0] |= y
.array
[0];
1256 #define CPU_FLAGS_ARCH_MATCH 0x1
1257 #define CPU_FLAGS_64BIT_MATCH 0x2
1258 #define CPU_FLAGS_AES_MATCH 0x4
1259 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1260 #define CPU_FLAGS_AVX_MATCH 0x10
1262 #define CPU_FLAGS_32BIT_MATCH \
1263 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1264 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1265 #define CPU_FLAGS_PERFECT_MATCH \
1266 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1268 /* Return CPU flags match bits. */
1271 cpu_flags_match (const template *t
)
1273 i386_cpu_flags x
= t
->cpu_flags
;
1274 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1276 x
.bitfield
.cpu64
= 0;
1277 x
.bitfield
.cpuno64
= 0;
1279 if (cpu_flags_all_zero (&x
))
1281 /* This instruction is available on all archs. */
1282 match
|= CPU_FLAGS_32BIT_MATCH
;
1286 /* This instruction is available only on some archs. */
1287 i386_cpu_flags cpu
= cpu_arch_flags
;
1289 cpu
.bitfield
.cpu64
= 0;
1290 cpu
.bitfield
.cpuno64
= 0;
1291 cpu
= cpu_flags_and (x
, cpu
);
1292 if (!cpu_flags_all_zero (&cpu
))
1294 if (x
.bitfield
.cpuavx
)
1296 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1297 if (cpu
.bitfield
.cpuavx
)
1299 /* Check SSE2AVX. */
1300 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1302 match
|= (CPU_FLAGS_ARCH_MATCH
1303 | CPU_FLAGS_AVX_MATCH
);
1305 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1306 match
|= CPU_FLAGS_AES_MATCH
;
1308 if (!x
.bitfield
.cpupclmul
1309 || cpu
.bitfield
.cpupclmul
)
1310 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1314 match
|= CPU_FLAGS_ARCH_MATCH
;
1317 match
|= CPU_FLAGS_32BIT_MATCH
;
1323 static INLINE i386_operand_type
1324 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1326 switch (ARRAY_SIZE (x
.array
))
1329 x
.array
[2] &= y
.array
[2];
1331 x
.array
[1] &= y
.array
[1];
1333 x
.array
[0] &= y
.array
[0];
1341 static INLINE i386_operand_type
1342 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1344 switch (ARRAY_SIZE (x
.array
))
1347 x
.array
[2] |= y
.array
[2];
1349 x
.array
[1] |= y
.array
[1];
1351 x
.array
[0] |= y
.array
[0];
1359 static INLINE i386_operand_type
1360 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1362 switch (ARRAY_SIZE (x
.array
))
1365 x
.array
[2] ^= y
.array
[2];
1367 x
.array
[1] ^= y
.array
[1];
1369 x
.array
[0] ^= y
.array
[0];
1377 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1378 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1379 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1380 static const i386_operand_type inoutportreg
1381 = OPERAND_TYPE_INOUTPORTREG
;
1382 static const i386_operand_type reg16_inoutportreg
1383 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1384 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1385 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1386 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1387 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1388 static const i386_operand_type anydisp
1389 = OPERAND_TYPE_ANYDISP
;
1390 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1391 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1392 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1393 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1394 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1395 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1396 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1397 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1398 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1399 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1400 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1411 operand_type_check (i386_operand_type t
, enum operand_type c
)
1416 return (t
.bitfield
.reg8
1419 || t
.bitfield
.reg64
);
1422 return (t
.bitfield
.imm8
1426 || t
.bitfield
.imm32s
1427 || t
.bitfield
.imm64
);
1430 return (t
.bitfield
.disp8
1431 || t
.bitfield
.disp16
1432 || t
.bitfield
.disp32
1433 || t
.bitfield
.disp32s
1434 || t
.bitfield
.disp64
);
1437 return (t
.bitfield
.disp8
1438 || t
.bitfield
.disp16
1439 || t
.bitfield
.disp32
1440 || t
.bitfield
.disp32s
1441 || t
.bitfield
.disp64
1442 || t
.bitfield
.baseindex
);
1451 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1452 operand J for instruction template T. */
1455 match_reg_size (const template *t
, unsigned int j
)
1457 return !((i
.types
[j
].bitfield
.byte
1458 && !t
->operand_types
[j
].bitfield
.byte
)
1459 || (i
.types
[j
].bitfield
.word
1460 && !t
->operand_types
[j
].bitfield
.word
)
1461 || (i
.types
[j
].bitfield
.dword
1462 && !t
->operand_types
[j
].bitfield
.dword
)
1463 || (i
.types
[j
].bitfield
.qword
1464 && !t
->operand_types
[j
].bitfield
.qword
));
1467 /* Return 1 if there is no conflict in any size on operand J for
1468 instruction template T. */
1471 match_mem_size (const template *t
, unsigned int j
)
1473 return (match_reg_size (t
, j
)
1474 && !((i
.types
[j
].bitfield
.unspecified
1475 && !t
->operand_types
[j
].bitfield
.unspecified
)
1476 || (i
.types
[j
].bitfield
.fword
1477 && !t
->operand_types
[j
].bitfield
.fword
)
1478 || (i
.types
[j
].bitfield
.tbyte
1479 && !t
->operand_types
[j
].bitfield
.tbyte
)
1480 || (i
.types
[j
].bitfield
.xmmword
1481 && !t
->operand_types
[j
].bitfield
.xmmword
)
1482 || (i
.types
[j
].bitfield
.ymmword
1483 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1486 /* Return 1 if there is no size conflict on any operands for
1487 instruction template T. */
1490 operand_size_match (const template *t
)
1495 /* Don't check jump instructions. */
1496 if (t
->opcode_modifier
.jump
1497 || t
->opcode_modifier
.jumpbyte
1498 || t
->opcode_modifier
.jumpdword
1499 || t
->opcode_modifier
.jumpintersegment
)
1502 /* Check memory and accumulator operand size. */
1503 for (j
= 0; j
< i
.operands
; j
++)
1505 if (t
->operand_types
[j
].bitfield
.anysize
)
1508 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1514 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1522 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1525 /* Check reverse. */
1526 assert (i
.operands
== 2);
1529 for (j
= 0; j
< 2; j
++)
1531 if (t
->operand_types
[j
].bitfield
.acc
1532 && !match_reg_size (t
, j
? 0 : 1))
1538 if (i
.types
[j
].bitfield
.mem
1539 && !match_mem_size (t
, j
? 0 : 1))
1550 operand_type_match (i386_operand_type overlap
,
1551 i386_operand_type given
)
1553 i386_operand_type temp
= overlap
;
1555 temp
.bitfield
.jumpabsolute
= 0;
1556 temp
.bitfield
.unspecified
= 0;
1557 temp
.bitfield
.byte
= 0;
1558 temp
.bitfield
.word
= 0;
1559 temp
.bitfield
.dword
= 0;
1560 temp
.bitfield
.fword
= 0;
1561 temp
.bitfield
.qword
= 0;
1562 temp
.bitfield
.tbyte
= 0;
1563 temp
.bitfield
.xmmword
= 0;
1564 temp
.bitfield
.ymmword
= 0;
1565 if (operand_type_all_zero (&temp
))
1568 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1569 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1572 /* If given types g0 and g1 are registers they must be of the same type
1573 unless the expected operand type register overlap is null.
1574 Note that Acc in a template matches every size of reg. */
1577 operand_type_register_match (i386_operand_type m0
,
1578 i386_operand_type g0
,
1579 i386_operand_type t0
,
1580 i386_operand_type m1
,
1581 i386_operand_type g1
,
1582 i386_operand_type t1
)
1584 if (!operand_type_check (g0
, reg
))
1587 if (!operand_type_check (g1
, reg
))
1590 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1591 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1592 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1593 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1596 if (m0
.bitfield
.acc
)
1598 t0
.bitfield
.reg8
= 1;
1599 t0
.bitfield
.reg16
= 1;
1600 t0
.bitfield
.reg32
= 1;
1601 t0
.bitfield
.reg64
= 1;
1604 if (m1
.bitfield
.acc
)
1606 t1
.bitfield
.reg8
= 1;
1607 t1
.bitfield
.reg16
= 1;
1608 t1
.bitfield
.reg32
= 1;
1609 t1
.bitfield
.reg64
= 1;
1612 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1613 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1614 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1615 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1618 static INLINE
unsigned int
1619 mode_from_disp_size (i386_operand_type t
)
1621 if (t
.bitfield
.disp8
)
1623 else if (t
.bitfield
.disp16
1624 || t
.bitfield
.disp32
1625 || t
.bitfield
.disp32s
)
1632 fits_in_signed_byte (offsetT num
)
1634 return (num
>= -128) && (num
<= 127);
1638 fits_in_unsigned_byte (offsetT num
)
1640 return (num
& 0xff) == num
;
1644 fits_in_unsigned_word (offsetT num
)
1646 return (num
& 0xffff) == num
;
1650 fits_in_signed_word (offsetT num
)
1652 return (-32768 <= num
) && (num
<= 32767);
1656 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1661 return (!(((offsetT
) -1 << 31) & num
)
1662 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1664 } /* fits_in_signed_long() */
1667 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1672 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1674 } /* fits_in_unsigned_long() */
1676 static i386_operand_type
1677 smallest_imm_type (offsetT num
)
1679 i386_operand_type t
;
1681 operand_type_set (&t
, 0);
1682 t
.bitfield
.imm64
= 1;
1684 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1686 /* This code is disabled on the 486 because all the Imm1 forms
1687 in the opcode table are slower on the i486. They're the
1688 versions with the implicitly specified single-position
1689 displacement, which has another syntax if you really want to
1691 t
.bitfield
.imm1
= 1;
1692 t
.bitfield
.imm8
= 1;
1693 t
.bitfield
.imm8s
= 1;
1694 t
.bitfield
.imm16
= 1;
1695 t
.bitfield
.imm32
= 1;
1696 t
.bitfield
.imm32s
= 1;
1698 else if (fits_in_signed_byte (num
))
1700 t
.bitfield
.imm8
= 1;
1701 t
.bitfield
.imm8s
= 1;
1702 t
.bitfield
.imm16
= 1;
1703 t
.bitfield
.imm32
= 1;
1704 t
.bitfield
.imm32s
= 1;
1706 else if (fits_in_unsigned_byte (num
))
1708 t
.bitfield
.imm8
= 1;
1709 t
.bitfield
.imm16
= 1;
1710 t
.bitfield
.imm32
= 1;
1711 t
.bitfield
.imm32s
= 1;
1713 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1715 t
.bitfield
.imm16
= 1;
1716 t
.bitfield
.imm32
= 1;
1717 t
.bitfield
.imm32s
= 1;
1719 else if (fits_in_signed_long (num
))
1721 t
.bitfield
.imm32
= 1;
1722 t
.bitfield
.imm32s
= 1;
1724 else if (fits_in_unsigned_long (num
))
1725 t
.bitfield
.imm32
= 1;
1731 offset_in_range (offsetT val
, int size
)
1737 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1738 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1739 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1741 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1746 /* If BFD64, sign extend val. */
1747 if (!use_rela_relocations
)
1748 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1749 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1751 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1753 char buf1
[40], buf2
[40];
1755 sprint_value (buf1
, val
);
1756 sprint_value (buf2
, val
& mask
);
1757 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1762 /* Returns 0 if attempting to add a prefix where one from the same
1763 class already exists, 1 if non rep/repne added, 2 if rep/repne
1766 add_prefix (unsigned int prefix
)
1771 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1772 && flag_code
== CODE_64BIT
)
1774 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1775 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1776 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1787 case CS_PREFIX_OPCODE
:
1788 case DS_PREFIX_OPCODE
:
1789 case ES_PREFIX_OPCODE
:
1790 case FS_PREFIX_OPCODE
:
1791 case GS_PREFIX_OPCODE
:
1792 case SS_PREFIX_OPCODE
:
1796 case REPNE_PREFIX_OPCODE
:
1797 case REPE_PREFIX_OPCODE
:
1800 case LOCK_PREFIX_OPCODE
:
1808 case ADDR_PREFIX_OPCODE
:
1812 case DATA_PREFIX_OPCODE
:
1816 if (i
.prefix
[q
] != 0)
1824 i
.prefix
[q
] |= prefix
;
1827 as_bad (_("same type of prefix used twice"));
1833 set_code_flag (int value
)
1836 if (flag_code
== CODE_64BIT
)
1838 cpu_arch_flags
.bitfield
.cpu64
= 1;
1839 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1843 cpu_arch_flags
.bitfield
.cpu64
= 0;
1844 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1846 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1848 as_bad (_("64bit mode not supported on this CPU."));
1850 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1852 as_bad (_("32bit mode not supported on this CPU."));
1854 stackop_size
= '\0';
1858 set_16bit_gcc_code_flag (int new_code_flag
)
1860 flag_code
= new_code_flag
;
1861 if (flag_code
!= CODE_16BIT
)
1863 cpu_arch_flags
.bitfield
.cpu64
= 0;
1864 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1865 stackop_size
= LONG_MNEM_SUFFIX
;
1869 set_intel_syntax (int syntax_flag
)
1871 /* Find out if register prefixing is specified. */
1872 int ask_naked_reg
= 0;
1875 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1877 char *string
= input_line_pointer
;
1878 int e
= get_symbol_end ();
1880 if (strcmp (string
, "prefix") == 0)
1882 else if (strcmp (string
, "noprefix") == 0)
1885 as_bad (_("bad argument to syntax directive."));
1886 *input_line_pointer
= e
;
1888 demand_empty_rest_of_line ();
1890 intel_syntax
= syntax_flag
;
1892 if (ask_naked_reg
== 0)
1893 allow_naked_reg
= (intel_syntax
1894 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1896 allow_naked_reg
= (ask_naked_reg
< 0);
1898 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1899 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1900 register_prefix
= allow_naked_reg
? "" : "%";
1904 set_intel_mnemonic (int mnemonic_flag
)
1906 intel_mnemonic
= mnemonic_flag
;
1910 set_allow_index_reg (int flag
)
1912 allow_index_reg
= flag
;
1916 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1920 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1922 char *string
= input_line_pointer
;
1923 int e
= get_symbol_end ();
1925 if (strcmp (string
, "none") == 0)
1926 sse_check
= sse_check_none
;
1927 else if (strcmp (string
, "warning") == 0)
1928 sse_check
= sse_check_warning
;
1929 else if (strcmp (string
, "error") == 0)
1930 sse_check
= sse_check_error
;
1932 as_bad (_("bad argument to sse_check directive."));
1933 *input_line_pointer
= e
;
1936 as_bad (_("missing argument for sse_check directive"));
1938 demand_empty_rest_of_line ();
1942 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1946 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1948 char *string
= input_line_pointer
;
1949 int e
= get_symbol_end ();
1951 i386_cpu_flags flags
;
1953 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1955 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1959 cpu_arch_name
= cpu_arch
[i
].name
;
1960 cpu_sub_arch_name
= NULL
;
1961 cpu_arch_flags
= cpu_arch
[i
].flags
;
1962 if (flag_code
== CODE_64BIT
)
1964 cpu_arch_flags
.bitfield
.cpu64
= 1;
1965 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1969 cpu_arch_flags
.bitfield
.cpu64
= 0;
1970 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1972 cpu_arch_isa
= cpu_arch
[i
].type
;
1973 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1974 if (!cpu_arch_tune_set
)
1976 cpu_arch_tune
= cpu_arch_isa
;
1977 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1982 flags
= cpu_flags_or (cpu_arch_flags
,
1984 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1986 if (cpu_sub_arch_name
)
1988 char *name
= cpu_sub_arch_name
;
1989 cpu_sub_arch_name
= concat (name
,
1991 (const char *) NULL
);
1995 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1996 cpu_arch_flags
= flags
;
1998 *input_line_pointer
= e
;
1999 demand_empty_rest_of_line ();
2003 if (i
>= ARRAY_SIZE (cpu_arch
))
2004 as_bad (_("no such architecture: `%s'"), string
);
2006 *input_line_pointer
= e
;
2009 as_bad (_("missing cpu architecture"));
2011 no_cond_jump_promotion
= 0;
2012 if (*input_line_pointer
== ','
2013 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2015 char *string
= ++input_line_pointer
;
2016 int e
= get_symbol_end ();
2018 if (strcmp (string
, "nojumps") == 0)
2019 no_cond_jump_promotion
= 1;
2020 else if (strcmp (string
, "jumps") == 0)
2023 as_bad (_("no such architecture modifier: `%s'"), string
);
2025 *input_line_pointer
= e
;
2028 demand_empty_rest_of_line ();
2034 if (!strcmp (default_arch
, "x86_64"))
2035 return bfd_mach_x86_64
;
2036 else if (!strcmp (default_arch
, "i386"))
2037 return bfd_mach_i386_i386
;
2039 as_fatal (_("Unknown architecture"));
2045 const char *hash_err
;
2047 /* Initialize op_hash hash table. */
2048 op_hash
= hash_new ();
2051 const template *optab
;
2052 templates
*core_optab
;
2054 /* Setup for loop. */
2056 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2057 core_optab
->start
= optab
;
2062 if (optab
->name
== NULL
2063 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2065 /* different name --> ship out current template list;
2066 add to hash table; & begin anew. */
2067 core_optab
->end
= optab
;
2068 hash_err
= hash_insert (op_hash
,
2070 (void *) core_optab
);
2073 as_fatal (_("Internal Error: Can't hash %s: %s"),
2077 if (optab
->name
== NULL
)
2079 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2080 core_optab
->start
= optab
;
2085 /* Initialize reg_hash hash table. */
2086 reg_hash
= hash_new ();
2088 const reg_entry
*regtab
;
2089 unsigned int regtab_size
= i386_regtab_size
;
2091 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2093 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2095 as_fatal (_("Internal Error: Can't hash %s: %s"),
2101 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2106 for (c
= 0; c
< 256; c
++)
2111 mnemonic_chars
[c
] = c
;
2112 register_chars
[c
] = c
;
2113 operand_chars
[c
] = c
;
2115 else if (ISLOWER (c
))
2117 mnemonic_chars
[c
] = c
;
2118 register_chars
[c
] = c
;
2119 operand_chars
[c
] = c
;
2121 else if (ISUPPER (c
))
2123 mnemonic_chars
[c
] = TOLOWER (c
);
2124 register_chars
[c
] = mnemonic_chars
[c
];
2125 operand_chars
[c
] = c
;
2128 if (ISALPHA (c
) || ISDIGIT (c
))
2129 identifier_chars
[c
] = c
;
2132 identifier_chars
[c
] = c
;
2133 operand_chars
[c
] = c
;
2138 identifier_chars
['@'] = '@';
2141 identifier_chars
['?'] = '?';
2142 operand_chars
['?'] = '?';
2144 digit_chars
['-'] = '-';
2145 mnemonic_chars
['_'] = '_';
2146 mnemonic_chars
['-'] = '-';
2147 mnemonic_chars
['.'] = '.';
2148 identifier_chars
['_'] = '_';
2149 identifier_chars
['.'] = '.';
2151 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2152 operand_chars
[(unsigned char) *p
] = *p
;
2155 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2158 record_alignment (text_section
, 2);
2159 record_alignment (data_section
, 2);
2160 record_alignment (bss_section
, 2);
2164 if (flag_code
== CODE_64BIT
)
2166 x86_dwarf2_return_column
= 16;
2167 x86_cie_data_alignment
= -8;
2171 x86_dwarf2_return_column
= 8;
2172 x86_cie_data_alignment
= -4;
2177 i386_print_statistics (FILE *file
)
2179 hash_print_statistics (file
, "i386 opcode", op_hash
);
2180 hash_print_statistics (file
, "i386 register", reg_hash
);
2185 /* Debugging routines for md_assemble. */
2186 static void pte (template *);
2187 static void pt (i386_operand_type
);
2188 static void pe (expressionS
*);
2189 static void ps (symbolS
*);
2192 pi (char *line
, i386_insn
*x
)
2196 fprintf (stdout
, "%s: template ", line
);
2198 fprintf (stdout
, " address: base %s index %s scale %x\n",
2199 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2200 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2201 x
->log2_scale_factor
);
2202 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2203 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2204 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2205 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2206 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2207 (x
->rex
& REX_W
) != 0,
2208 (x
->rex
& REX_R
) != 0,
2209 (x
->rex
& REX_X
) != 0,
2210 (x
->rex
& REX_B
) != 0);
2211 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2212 x
->drex
.reg
, x
->drex
.rex
);
2213 for (i
= 0; i
< x
->operands
; i
++)
2215 fprintf (stdout
, " #%d: ", i
+ 1);
2217 fprintf (stdout
, "\n");
2218 if (x
->types
[i
].bitfield
.reg8
2219 || x
->types
[i
].bitfield
.reg16
2220 || x
->types
[i
].bitfield
.reg32
2221 || x
->types
[i
].bitfield
.reg64
2222 || x
->types
[i
].bitfield
.regmmx
2223 || x
->types
[i
].bitfield
.regxmm
2224 || x
->types
[i
].bitfield
.regymm
2225 || x
->types
[i
].bitfield
.sreg2
2226 || x
->types
[i
].bitfield
.sreg3
2227 || x
->types
[i
].bitfield
.control
2228 || x
->types
[i
].bitfield
.debug
2229 || x
->types
[i
].bitfield
.test
)
2230 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2231 if (operand_type_check (x
->types
[i
], imm
))
2233 if (operand_type_check (x
->types
[i
], disp
))
2234 pe (x
->op
[i
].disps
);
2242 fprintf (stdout
, " %d operands ", t
->operands
);
2243 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2244 if (t
->extension_opcode
!= None
)
2245 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2246 if (t
->opcode_modifier
.d
)
2247 fprintf (stdout
, "D");
2248 if (t
->opcode_modifier
.w
)
2249 fprintf (stdout
, "W");
2250 fprintf (stdout
, "\n");
2251 for (i
= 0; i
< t
->operands
; i
++)
2253 fprintf (stdout
, " #%d type ", i
+ 1);
2254 pt (t
->operand_types
[i
]);
2255 fprintf (stdout
, "\n");
2262 fprintf (stdout
, " operation %d\n", e
->X_op
);
2263 fprintf (stdout
, " add_number %ld (%lx)\n",
2264 (long) e
->X_add_number
, (long) e
->X_add_number
);
2265 if (e
->X_add_symbol
)
2267 fprintf (stdout
, " add_symbol ");
2268 ps (e
->X_add_symbol
);
2269 fprintf (stdout
, "\n");
2273 fprintf (stdout
, " op_symbol ");
2274 ps (e
->X_op_symbol
);
2275 fprintf (stdout
, "\n");
2282 fprintf (stdout
, "%s type %s%s",
2284 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2285 segment_name (S_GET_SEGMENT (s
)));
2288 static struct type_name
2290 i386_operand_type mask
;
2293 const type_names
[] =
2295 { OPERAND_TYPE_REG8
, "r8" },
2296 { OPERAND_TYPE_REG16
, "r16" },
2297 { OPERAND_TYPE_REG32
, "r32" },
2298 { OPERAND_TYPE_REG64
, "r64" },
2299 { OPERAND_TYPE_IMM8
, "i8" },
2300 { OPERAND_TYPE_IMM8
, "i8s" },
2301 { OPERAND_TYPE_IMM16
, "i16" },
2302 { OPERAND_TYPE_IMM32
, "i32" },
2303 { OPERAND_TYPE_IMM32S
, "i32s" },
2304 { OPERAND_TYPE_IMM64
, "i64" },
2305 { OPERAND_TYPE_IMM1
, "i1" },
2306 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2307 { OPERAND_TYPE_DISP8
, "d8" },
2308 { OPERAND_TYPE_DISP16
, "d16" },
2309 { OPERAND_TYPE_DISP32
, "d32" },
2310 { OPERAND_TYPE_DISP32S
, "d32s" },
2311 { OPERAND_TYPE_DISP64
, "d64" },
2312 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2313 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2314 { OPERAND_TYPE_CONTROL
, "control reg" },
2315 { OPERAND_TYPE_TEST
, "test reg" },
2316 { OPERAND_TYPE_DEBUG
, "debug reg" },
2317 { OPERAND_TYPE_FLOATREG
, "FReg" },
2318 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2319 { OPERAND_TYPE_SREG2
, "SReg2" },
2320 { OPERAND_TYPE_SREG3
, "SReg3" },
2321 { OPERAND_TYPE_ACC
, "Acc" },
2322 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2323 { OPERAND_TYPE_REGMMX
, "rMMX" },
2324 { OPERAND_TYPE_REGXMM
, "rXMM" },
2325 { OPERAND_TYPE_REGYMM
, "rYMM" },
2326 { OPERAND_TYPE_ESSEG
, "es" },
2330 pt (i386_operand_type t
)
2333 i386_operand_type a
;
2335 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2337 a
= operand_type_and (t
, type_names
[j
].mask
);
2338 if (!operand_type_all_zero (&a
))
2339 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2344 #endif /* DEBUG386 */
2346 static bfd_reloc_code_real_type
2347 reloc (unsigned int size
,
2350 bfd_reloc_code_real_type other
)
2352 if (other
!= NO_RELOC
)
2354 reloc_howto_type
*reloc
;
2359 case BFD_RELOC_X86_64_GOT32
:
2360 return BFD_RELOC_X86_64_GOT64
;
2362 case BFD_RELOC_X86_64_PLTOFF64
:
2363 return BFD_RELOC_X86_64_PLTOFF64
;
2365 case BFD_RELOC_X86_64_GOTPC32
:
2366 other
= BFD_RELOC_X86_64_GOTPC64
;
2368 case BFD_RELOC_X86_64_GOTPCREL
:
2369 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2371 case BFD_RELOC_X86_64_TPOFF32
:
2372 other
= BFD_RELOC_X86_64_TPOFF64
;
2374 case BFD_RELOC_X86_64_DTPOFF32
:
2375 other
= BFD_RELOC_X86_64_DTPOFF64
;
2381 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2382 if (size
== 4 && flag_code
!= CODE_64BIT
)
2385 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2387 as_bad (_("unknown relocation (%u)"), other
);
2388 else if (size
!= bfd_get_reloc_size (reloc
))
2389 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2390 bfd_get_reloc_size (reloc
),
2392 else if (pcrel
&& !reloc
->pc_relative
)
2393 as_bad (_("non-pc-relative relocation for pc-relative field"));
2394 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2396 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2398 as_bad (_("relocated field and relocation type differ in signedness"));
2407 as_bad (_("there are no unsigned pc-relative relocations"));
2410 case 1: return BFD_RELOC_8_PCREL
;
2411 case 2: return BFD_RELOC_16_PCREL
;
2412 case 4: return BFD_RELOC_32_PCREL
;
2413 case 8: return BFD_RELOC_64_PCREL
;
2415 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2422 case 4: return BFD_RELOC_X86_64_32S
;
2427 case 1: return BFD_RELOC_8
;
2428 case 2: return BFD_RELOC_16
;
2429 case 4: return BFD_RELOC_32
;
2430 case 8: return BFD_RELOC_64
;
2432 as_bad (_("cannot do %s %u byte relocation"),
2433 sign
> 0 ? "signed" : "unsigned", size
);
2437 return BFD_RELOC_NONE
;
2440 /* Here we decide which fixups can be adjusted to make them relative to
2441 the beginning of the section instead of the symbol. Basically we need
2442 to make sure that the dynamic relocations are done correctly, so in
2443 some cases we force the original symbol to be used. */
2446 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2448 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2452 /* Don't adjust pc-relative references to merge sections in 64-bit
2454 if (use_rela_relocations
2455 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2459 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2460 and changed later by validate_fix. */
2461 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2462 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2465 /* adjust_reloc_syms doesn't know about the GOT. */
2466 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2467 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2468 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2469 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2470 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2471 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2472 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2473 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2474 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2475 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2479 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2480 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2481 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2482 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2483 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2484 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2485 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2492 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2493 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2500 intel_float_operand (const char *mnemonic
)
2502 /* Note that the value returned is meaningful only for opcodes with (memory)
2503 operands, hence the code here is free to improperly handle opcodes that
2504 have no operands (for better performance and smaller code). */
2506 if (mnemonic
[0] != 'f')
2507 return 0; /* non-math */
2509 switch (mnemonic
[1])
2511 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2512 the fs segment override prefix not currently handled because no
2513 call path can make opcodes without operands get here */
2515 return 2 /* integer op */;
2517 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2518 return 3; /* fldcw/fldenv */
2521 if (mnemonic
[2] != 'o' /* fnop */)
2522 return 3; /* non-waiting control op */
2525 if (mnemonic
[2] == 's')
2526 return 3; /* frstor/frstpm */
2529 if (mnemonic
[2] == 'a')
2530 return 3; /* fsave */
2531 if (mnemonic
[2] == 't')
2533 switch (mnemonic
[3])
2535 case 'c': /* fstcw */
2536 case 'd': /* fstdw */
2537 case 'e': /* fstenv */
2538 case 's': /* fsts[gw] */
2544 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2545 return 0; /* fxsave/fxrstor are not really math ops */
2552 /* Build the VEX prefix. */
2555 build_vex_prefix (const template *t
)
2557 unsigned int register_specifier
;
2558 unsigned int implied_prefix
;
2559 unsigned int vector_length
;
2561 /* Check register specifier. */
2562 if (i
.vex
.register_specifier
)
2564 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2565 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2566 register_specifier
+= 8;
2567 register_specifier
= ~register_specifier
& 0xf;
2570 register_specifier
= 0xf;
2572 /* Use 2-byte VEX prefix by swappping destination and source
2575 && i
.operands
== i
.reg_operands
2576 && i
.tm
.opcode_modifier
.vex0f
2577 && i
.tm
.opcode_modifier
.s
2580 unsigned int xchg
= i
.operands
- 1;
2581 union i386_op temp_op
;
2582 i386_operand_type temp_type
;
2584 temp_type
= i
.types
[xchg
];
2585 i
.types
[xchg
] = i
.types
[0];
2586 i
.types
[0] = temp_type
;
2587 temp_op
= i
.op
[xchg
];
2588 i
.op
[xchg
] = i
.op
[0];
2591 assert (i
.rm
.mode
== 3);
2595 i
.rm
.regmem
= i
.rm
.reg
;
2598 /* Use the next insn. */
2602 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2604 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2609 case DATA_PREFIX_OPCODE
:
2612 case REPE_PREFIX_OPCODE
:
2615 case REPNE_PREFIX_OPCODE
:
2622 /* Use 2-byte VEX prefix if possible. */
2623 if (i
.tm
.opcode_modifier
.vex0f
2624 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2626 /* 2-byte VEX prefix. */
2630 i
.vex
.bytes
[0] = 0xc5;
2632 /* Check the REX.R bit. */
2633 r
= (i
.rex
& REX_R
) ? 0 : 1;
2634 i
.vex
.bytes
[1] = (r
<< 7
2635 | register_specifier
<< 3
2636 | vector_length
<< 2
2641 /* 3-byte VEX prefix. */
2644 if (i
.tm
.opcode_modifier
.vex0f
)
2646 else if (i
.tm
.opcode_modifier
.vex0f38
)
2648 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2654 i
.vex
.bytes
[0] = 0xc4;
2656 /* The high 3 bits of the second VEX byte are 1's compliment
2657 of RXB bits from REX. */
2658 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2660 /* Check the REX.W bit. */
2661 w
= (i
.rex
& REX_W
) ? 1 : 0;
2662 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2667 if (i
.tm
.opcode_modifier
.vexw1
)
2671 i
.vex
.bytes
[2] = (w
<< 7
2672 | register_specifier
<< 3
2673 | vector_length
<< 2
2679 process_immext (void)
2683 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2685 /* SSE3 Instructions have the fixed operands with an opcode
2686 suffix which is coded in the same place as an 8-bit immediate
2687 field would be. Here we check those operands and remove them
2691 for (x
= 0; x
< i
.operands
; x
++)
2692 if (i
.op
[x
].regs
->reg_num
!= x
)
2693 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2694 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2700 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2701 which is coded in the same place as an 8-bit immediate field
2702 would be. Here we fake an 8-bit immediate operand from the
2703 opcode suffix stored in tm.extension_opcode.
2705 SSE5 and AVX instructions also use this encoding, for some of
2706 3 argument instructions. */
2708 assert (i
.imm_operands
== 0
2710 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2712 || (i
.tm
.opcode_modifier
.vex
2713 && i
.operands
<= 4)));
2715 exp
= &im_expressions
[i
.imm_operands
++];
2716 i
.op
[i
.operands
].imms
= exp
;
2717 i
.types
[i
.operands
] = imm8
;
2719 exp
->X_op
= O_constant
;
2720 exp
->X_add_number
= i
.tm
.extension_opcode
;
2721 i
.tm
.extension_opcode
= None
;
2724 /* This is the guts of the machine-dependent assembler. LINE points to a
2725 machine dependent instruction. This function is supposed to emit
2726 the frags/bytes it assembles to. */
2729 md_assemble (char *line
)
2732 char mnemonic
[MAX_MNEM_SIZE
];
2735 /* Initialize globals. */
2736 memset (&i
, '\0', sizeof (i
));
2737 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2738 i
.reloc
[j
] = NO_RELOC
;
2739 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2740 memset (im_expressions
, '\0', sizeof (im_expressions
));
2741 save_stack_p
= save_stack
;
2743 /* First parse an instruction mnemonic & call i386_operand for the operands.
2744 We assume that the scrubber has arranged it so that line[0] is the valid
2745 start of a (possibly prefixed) mnemonic. */
2747 line
= parse_insn (line
, mnemonic
);
2751 line
= parse_operands (line
, mnemonic
);
2755 /* Now we've parsed the mnemonic into a set of templates, and have the
2756 operands at hand. */
2758 /* All intel opcodes have reversed operands except for "bound" and
2759 "enter". We also don't reverse intersegment "jmp" and "call"
2760 instructions with 2 immediate operands so that the immediate segment
2761 precedes the offset, as it does when in AT&T mode. */
2764 && (strcmp (mnemonic
, "bound") != 0)
2765 && (strcmp (mnemonic
, "invlpga") != 0)
2766 && !(operand_type_check (i
.types
[0], imm
)
2767 && operand_type_check (i
.types
[1], imm
)))
2770 /* The order of the immediates should be reversed
2771 for 2 immediates extrq and insertq instructions */
2772 if (i
.imm_operands
== 2
2773 && (strcmp (mnemonic
, "extrq") == 0
2774 || strcmp (mnemonic
, "insertq") == 0))
2775 swap_2_operands (0, 1);
2780 /* Don't optimize displacement for movabs since it only takes 64bit
2783 && (flag_code
!= CODE_64BIT
2784 || strcmp (mnemonic
, "movabs") != 0))
2787 /* Next, we find a template that matches the given insn,
2788 making sure the overlap of the given operands types is consistent
2789 with the template operand types. */
2791 if (!(t
= match_template ()))
2794 if (sse_check
!= sse_check_none
2795 && !i
.tm
.opcode_modifier
.noavx
2796 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2797 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2798 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2799 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2800 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2801 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2803 (sse_check
== sse_check_warning
2805 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2808 /* Zap movzx and movsx suffix. The suffix has been set from
2809 "word ptr" or "byte ptr" on the source operand in Intel syntax
2810 or extracted from mnemonic in AT&T syntax. But we'll use
2811 the destination register to choose the suffix for encoding. */
2812 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2814 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2815 there is no suffix, the default will be byte extension. */
2816 if (i
.reg_operands
!= 2
2819 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2824 if (i
.tm
.opcode_modifier
.fwait
)
2825 if (!add_prefix (FWAIT_OPCODE
))
2828 /* Check string instruction segment overrides. */
2829 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2831 if (!check_string ())
2833 i
.disp_operands
= 0;
2836 if (!process_suffix ())
2839 /* Make still unresolved immediate matches conform to size of immediate
2840 given in i.suffix. */
2841 if (!finalize_imm ())
2844 if (i
.types
[0].bitfield
.imm1
)
2845 i
.imm_operands
= 0; /* kludge for shift insns. */
2847 for (j
= 0; j
< 3; j
++)
2848 if (i
.types
[j
].bitfield
.inoutportreg
2849 || i
.types
[j
].bitfield
.shiftcount
2850 || i
.types
[j
].bitfield
.acc
2851 || i
.types
[j
].bitfield
.floatacc
)
2854 /* ImmExt should be processed after SSE2AVX. */
2855 if (!i
.tm
.opcode_modifier
.sse2avx
2856 && i
.tm
.opcode_modifier
.immext
)
2859 /* For insns with operands there are more diddles to do to the opcode. */
2862 if (!process_operands ())
2865 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2867 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2868 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2871 if (i
.tm
.opcode_modifier
.vex
)
2872 build_vex_prefix (t
);
2874 /* Handle conversion of 'int $3' --> special int3 insn. */
2875 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2877 i
.tm
.base_opcode
= INT3_OPCODE
;
2881 if ((i
.tm
.opcode_modifier
.jump
2882 || i
.tm
.opcode_modifier
.jumpbyte
2883 || i
.tm
.opcode_modifier
.jumpdword
)
2884 && i
.op
[0].disps
->X_op
== O_constant
)
2886 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2887 the absolute address given by the constant. Since ix86 jumps and
2888 calls are pc relative, we need to generate a reloc. */
2889 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2890 i
.op
[0].disps
->X_op
= O_symbol
;
2893 if (i
.tm
.opcode_modifier
.rex64
)
2896 /* For 8 bit registers we need an empty rex prefix. Also if the
2897 instruction already has a prefix, we need to convert old
2898 registers to new ones. */
2900 if ((i
.types
[0].bitfield
.reg8
2901 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2902 || (i
.types
[1].bitfield
.reg8
2903 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2904 || ((i
.types
[0].bitfield
.reg8
2905 || i
.types
[1].bitfield
.reg8
)
2910 i
.rex
|= REX_OPCODE
;
2911 for (x
= 0; x
< 2; x
++)
2913 /* Look for 8 bit operand that uses old registers. */
2914 if (i
.types
[x
].bitfield
.reg8
2915 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2917 /* In case it is "hi" register, give up. */
2918 if (i
.op
[x
].regs
->reg_num
> 3)
2919 as_bad (_("can't encode register '%s%s' in an "
2920 "instruction requiring REX prefix."),
2921 register_prefix
, i
.op
[x
].regs
->reg_name
);
2923 /* Otherwise it is equivalent to the extended register.
2924 Since the encoding doesn't change this is merely
2925 cosmetic cleanup for debug output. */
2927 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2932 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2934 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2939 else if (i
.rex
!= 0)
2940 add_prefix (REX_OPCODE
| i
.rex
);
2942 /* We are ready to output the insn. */
2947 parse_insn (char *line
, char *mnemonic
)
2950 char *token_start
= l
;
2956 /* Non-zero if we found a prefix only acceptable with string insns. */
2957 const char *expecting_string_instruction
= NULL
;
2962 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2967 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2969 as_bad (_("no such instruction: `%s'"), token_start
);
2974 if (!is_space_char (*l
)
2975 && *l
!= END_OF_INSN
2977 || (*l
!= PREFIX_SEPARATOR
2980 as_bad (_("invalid character %s in mnemonic"),
2981 output_invalid (*l
));
2984 if (token_start
== l
)
2986 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2987 as_bad (_("expecting prefix; got nothing"));
2989 as_bad (_("expecting mnemonic; got nothing"));
2993 /* Look up instruction (or prefix) via hash table. */
2994 current_templates
= hash_find (op_hash
, mnemonic
);
2996 if (*l
!= END_OF_INSN
2997 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2998 && current_templates
2999 && current_templates
->start
->opcode_modifier
.isprefix
)
3001 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3003 as_bad ((flag_code
!= CODE_64BIT
3004 ? _("`%s' is only supported in 64-bit mode")
3005 : _("`%s' is not supported in 64-bit mode")),
3006 current_templates
->start
->name
);
3009 /* If we are in 16-bit mode, do not allow addr16 or data16.
3010 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3011 if ((current_templates
->start
->opcode_modifier
.size16
3012 || current_templates
->start
->opcode_modifier
.size32
)
3013 && flag_code
!= CODE_64BIT
3014 && (current_templates
->start
->opcode_modifier
.size32
3015 ^ (flag_code
== CODE_16BIT
)))
3017 as_bad (_("redundant %s prefix"),
3018 current_templates
->start
->name
);
3021 /* Add prefix, checking for repeated prefixes. */
3022 switch (add_prefix (current_templates
->start
->base_opcode
))
3027 expecting_string_instruction
= current_templates
->start
->name
;
3030 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3037 if (!current_templates
)
3039 /* Check if we should swap operand in encoding. */
3040 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3046 current_templates
= hash_find (op_hash
, mnemonic
);
3049 if (!current_templates
)
3052 /* See if we can get a match by trimming off a suffix. */
3055 case WORD_MNEM_SUFFIX
:
3056 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3057 i
.suffix
= SHORT_MNEM_SUFFIX
;
3059 case BYTE_MNEM_SUFFIX
:
3060 case QWORD_MNEM_SUFFIX
:
3061 i
.suffix
= mnem_p
[-1];
3063 current_templates
= hash_find (op_hash
, mnemonic
);
3065 case SHORT_MNEM_SUFFIX
:
3066 case LONG_MNEM_SUFFIX
:
3069 i
.suffix
= mnem_p
[-1];
3071 current_templates
= hash_find (op_hash
, mnemonic
);
3079 if (intel_float_operand (mnemonic
) == 1)
3080 i
.suffix
= SHORT_MNEM_SUFFIX
;
3082 i
.suffix
= LONG_MNEM_SUFFIX
;
3084 current_templates
= hash_find (op_hash
, mnemonic
);
3088 if (!current_templates
)
3090 as_bad (_("no such instruction: `%s'"), token_start
);
3095 if (current_templates
->start
->opcode_modifier
.jump
3096 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3098 /* Check for a branch hint. We allow ",pt" and ",pn" for
3099 predict taken and predict not taken respectively.
3100 I'm not sure that branch hints actually do anything on loop
3101 and jcxz insns (JumpByte) for current Pentium4 chips. They
3102 may work in the future and it doesn't hurt to accept them
3104 if (l
[0] == ',' && l
[1] == 'p')
3108 if (!add_prefix (DS_PREFIX_OPCODE
))
3112 else if (l
[2] == 'n')
3114 if (!add_prefix (CS_PREFIX_OPCODE
))
3120 /* Any other comma loses. */
3123 as_bad (_("invalid character %s in mnemonic"),
3124 output_invalid (*l
));
3128 /* Check if instruction is supported on specified architecture. */
3130 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3132 supported
|= cpu_flags_match (t
);
3133 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3137 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3139 as_bad (flag_code
== CODE_64BIT
3140 ? _("`%s' is not supported in 64-bit mode")
3141 : _("`%s' is only supported in 64-bit mode"),
3142 current_templates
->start
->name
);
3145 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3147 as_bad (_("`%s' is not supported on `%s%s'"),
3148 current_templates
->start
->name
,
3149 cpu_arch_name
? cpu_arch_name
: default_arch
,
3150 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3155 if (!cpu_arch_flags
.bitfield
.cpui386
3156 && (flag_code
!= CODE_16BIT
))
3158 as_warn (_("use .code16 to ensure correct addressing mode"));
3161 /* Check for rep/repne without a string instruction. */
3162 if (expecting_string_instruction
)
3164 static templates override
;
3166 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3167 if (t
->opcode_modifier
.isstring
)
3169 if (t
>= current_templates
->end
)
3171 as_bad (_("expecting string instruction after `%s'"),
3172 expecting_string_instruction
);
3175 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3176 if (!t
->opcode_modifier
.isstring
)
3179 current_templates
= &override
;
3186 parse_operands (char *l
, const char *mnemonic
)
3190 /* 1 if operand is pending after ','. */
3191 unsigned int expecting_operand
= 0;
3193 /* Non-zero if operand parens not balanced. */
3194 unsigned int paren_not_balanced
;
3196 while (*l
!= END_OF_INSN
)
3198 /* Skip optional white space before operand. */
3199 if (is_space_char (*l
))
3201 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3203 as_bad (_("invalid character %s before operand %d"),
3204 output_invalid (*l
),
3208 token_start
= l
; /* after white space */
3209 paren_not_balanced
= 0;
3210 while (paren_not_balanced
|| *l
!= ',')
3212 if (*l
== END_OF_INSN
)
3214 if (paren_not_balanced
)
3217 as_bad (_("unbalanced parenthesis in operand %d."),
3220 as_bad (_("unbalanced brackets in operand %d."),
3225 break; /* we are done */
3227 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3229 as_bad (_("invalid character %s in operand %d"),
3230 output_invalid (*l
),
3237 ++paren_not_balanced
;
3239 --paren_not_balanced
;
3244 ++paren_not_balanced
;
3246 --paren_not_balanced
;
3250 if (l
!= token_start
)
3251 { /* Yes, we've read in another operand. */
3252 unsigned int operand_ok
;
3253 this_operand
= i
.operands
++;
3254 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3255 if (i
.operands
> MAX_OPERANDS
)
3257 as_bad (_("spurious operands; (%d operands/instruction max)"),
3261 /* Now parse operand adding info to 'i' as we go along. */
3262 END_STRING_AND_SAVE (l
);
3266 i386_intel_operand (token_start
,
3267 intel_float_operand (mnemonic
));
3269 operand_ok
= i386_att_operand (token_start
);
3271 RESTORE_END_STRING (l
);
3277 if (expecting_operand
)
3279 expecting_operand_after_comma
:
3280 as_bad (_("expecting operand after ','; got nothing"));
3285 as_bad (_("expecting operand before ','; got nothing"));
3290 /* Now *l must be either ',' or END_OF_INSN. */
3293 if (*++l
== END_OF_INSN
)
3295 /* Just skip it, if it's \n complain. */
3296 goto expecting_operand_after_comma
;
3298 expecting_operand
= 1;
3305 swap_2_operands (int xchg1
, int xchg2
)
3307 union i386_op temp_op
;
3308 i386_operand_type temp_type
;
3309 enum bfd_reloc_code_real temp_reloc
;
3311 temp_type
= i
.types
[xchg2
];
3312 i
.types
[xchg2
] = i
.types
[xchg1
];
3313 i
.types
[xchg1
] = temp_type
;
3314 temp_op
= i
.op
[xchg2
];
3315 i
.op
[xchg2
] = i
.op
[xchg1
];
3316 i
.op
[xchg1
] = temp_op
;
3317 temp_reloc
= i
.reloc
[xchg2
];
3318 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3319 i
.reloc
[xchg1
] = temp_reloc
;
3323 swap_operands (void)
3329 swap_2_operands (1, i
.operands
- 2);
3332 swap_2_operands (0, i
.operands
- 1);
3338 if (i
.mem_operands
== 2)
3340 const seg_entry
*temp_seg
;
3341 temp_seg
= i
.seg
[0];
3342 i
.seg
[0] = i
.seg
[1];
3343 i
.seg
[1] = temp_seg
;
3347 /* Try to ensure constant immediates are represented in the smallest
3352 char guess_suffix
= 0;
3356 guess_suffix
= i
.suffix
;
3357 else if (i
.reg_operands
)
3359 /* Figure out a suffix from the last register operand specified.
3360 We can't do this properly yet, ie. excluding InOutPortReg,
3361 but the following works for instructions with immediates.
3362 In any case, we can't set i.suffix yet. */
3363 for (op
= i
.operands
; --op
>= 0;)
3364 if (i
.types
[op
].bitfield
.reg8
)
3366 guess_suffix
= BYTE_MNEM_SUFFIX
;
3369 else if (i
.types
[op
].bitfield
.reg16
)
3371 guess_suffix
= WORD_MNEM_SUFFIX
;
3374 else if (i
.types
[op
].bitfield
.reg32
)
3376 guess_suffix
= LONG_MNEM_SUFFIX
;
3379 else if (i
.types
[op
].bitfield
.reg64
)
3381 guess_suffix
= QWORD_MNEM_SUFFIX
;
3385 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3386 guess_suffix
= WORD_MNEM_SUFFIX
;
3388 for (op
= i
.operands
; --op
>= 0;)
3389 if (operand_type_check (i
.types
[op
], imm
))
3391 switch (i
.op
[op
].imms
->X_op
)
3394 /* If a suffix is given, this operand may be shortened. */
3395 switch (guess_suffix
)
3397 case LONG_MNEM_SUFFIX
:
3398 i
.types
[op
].bitfield
.imm32
= 1;
3399 i
.types
[op
].bitfield
.imm64
= 1;
3401 case WORD_MNEM_SUFFIX
:
3402 i
.types
[op
].bitfield
.imm16
= 1;
3403 i
.types
[op
].bitfield
.imm32
= 1;
3404 i
.types
[op
].bitfield
.imm32s
= 1;
3405 i
.types
[op
].bitfield
.imm64
= 1;
3407 case BYTE_MNEM_SUFFIX
:
3408 i
.types
[op
].bitfield
.imm8
= 1;
3409 i
.types
[op
].bitfield
.imm8s
= 1;
3410 i
.types
[op
].bitfield
.imm16
= 1;
3411 i
.types
[op
].bitfield
.imm32
= 1;
3412 i
.types
[op
].bitfield
.imm32s
= 1;
3413 i
.types
[op
].bitfield
.imm64
= 1;
3417 /* If this operand is at most 16 bits, convert it
3418 to a signed 16 bit number before trying to see
3419 whether it will fit in an even smaller size.
3420 This allows a 16-bit operand such as $0xffe0 to
3421 be recognised as within Imm8S range. */
3422 if ((i
.types
[op
].bitfield
.imm16
)
3423 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3425 i
.op
[op
].imms
->X_add_number
=
3426 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3428 if ((i
.types
[op
].bitfield
.imm32
)
3429 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3432 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3433 ^ ((offsetT
) 1 << 31))
3434 - ((offsetT
) 1 << 31));
3437 = operand_type_or (i
.types
[op
],
3438 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3440 /* We must avoid matching of Imm32 templates when 64bit
3441 only immediate is available. */
3442 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3443 i
.types
[op
].bitfield
.imm32
= 0;
3450 /* Symbols and expressions. */
3452 /* Convert symbolic operand to proper sizes for matching, but don't
3453 prevent matching a set of insns that only supports sizes other
3454 than those matching the insn suffix. */
3456 i386_operand_type mask
, allowed
;
3459 operand_type_set (&mask
, 0);
3460 operand_type_set (&allowed
, 0);
3462 for (t
= current_templates
->start
;
3463 t
< current_templates
->end
;
3465 allowed
= operand_type_or (allowed
,
3466 t
->operand_types
[op
]);
3467 switch (guess_suffix
)
3469 case QWORD_MNEM_SUFFIX
:
3470 mask
.bitfield
.imm64
= 1;
3471 mask
.bitfield
.imm32s
= 1;
3473 case LONG_MNEM_SUFFIX
:
3474 mask
.bitfield
.imm32
= 1;
3476 case WORD_MNEM_SUFFIX
:
3477 mask
.bitfield
.imm16
= 1;
3479 case BYTE_MNEM_SUFFIX
:
3480 mask
.bitfield
.imm8
= 1;
3485 allowed
= operand_type_and (mask
, allowed
);
3486 if (!operand_type_all_zero (&allowed
))
3487 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3494 /* Try to use the smallest displacement type too. */
3496 optimize_disp (void)
3500 for (op
= i
.operands
; --op
>= 0;)
3501 if (operand_type_check (i
.types
[op
], disp
))
3503 if (i
.op
[op
].disps
->X_op
== O_constant
)
3505 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3507 if (i
.types
[op
].bitfield
.disp16
3508 && (disp
& ~(offsetT
) 0xffff) == 0)
3510 /* If this operand is at most 16 bits, convert
3511 to a signed 16 bit number and don't use 64bit
3513 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3514 i
.types
[op
].bitfield
.disp64
= 0;
3516 if (i
.types
[op
].bitfield
.disp32
3517 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3519 /* If this operand is at most 32 bits, convert
3520 to a signed 32 bit number and don't use 64bit
3522 disp
&= (((offsetT
) 2 << 31) - 1);
3523 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3524 i
.types
[op
].bitfield
.disp64
= 0;
3526 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3528 i
.types
[op
].bitfield
.disp8
= 0;
3529 i
.types
[op
].bitfield
.disp16
= 0;
3530 i
.types
[op
].bitfield
.disp32
= 0;
3531 i
.types
[op
].bitfield
.disp32s
= 0;
3532 i
.types
[op
].bitfield
.disp64
= 0;
3536 else if (flag_code
== CODE_64BIT
)
3538 if (fits_in_signed_long (disp
))
3540 i
.types
[op
].bitfield
.disp64
= 0;
3541 i
.types
[op
].bitfield
.disp32s
= 1;
3543 if (fits_in_unsigned_long (disp
))
3544 i
.types
[op
].bitfield
.disp32
= 1;
3546 if ((i
.types
[op
].bitfield
.disp32
3547 || i
.types
[op
].bitfield
.disp32s
3548 || i
.types
[op
].bitfield
.disp16
)
3549 && fits_in_signed_byte (disp
))
3550 i
.types
[op
].bitfield
.disp8
= 1;
3552 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3553 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3555 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3556 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3557 i
.types
[op
].bitfield
.disp8
= 0;
3558 i
.types
[op
].bitfield
.disp16
= 0;
3559 i
.types
[op
].bitfield
.disp32
= 0;
3560 i
.types
[op
].bitfield
.disp32s
= 0;
3561 i
.types
[op
].bitfield
.disp64
= 0;
3564 /* We only support 64bit displacement on constants. */
3565 i
.types
[op
].bitfield
.disp64
= 0;
3569 static const template *
3570 match_template (void)
3572 /* Points to template once we've found it. */
3574 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3575 i386_operand_type overlap4
;
3576 unsigned int found_reverse_match
;
3577 i386_opcode_modifier suffix_check
;
3578 i386_operand_type operand_types
[MAX_OPERANDS
];
3579 int addr_prefix_disp
;
3581 unsigned int found_cpu_match
;
3582 unsigned int check_register
;
3584 #if MAX_OPERANDS != 5
3585 # error "MAX_OPERANDS must be 5."
3588 found_reverse_match
= 0;
3589 addr_prefix_disp
= -1;
3591 memset (&suffix_check
, 0, sizeof (suffix_check
));
3592 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3593 suffix_check
.no_bsuf
= 1;
3594 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3595 suffix_check
.no_wsuf
= 1;
3596 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3597 suffix_check
.no_ssuf
= 1;
3598 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3599 suffix_check
.no_lsuf
= 1;
3600 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3601 suffix_check
.no_qsuf
= 1;
3602 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3603 suffix_check
.no_ldsuf
= 1;
3605 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3607 addr_prefix_disp
= -1;
3609 /* Must have right number of operands. */
3610 if (i
.operands
!= t
->operands
)
3613 /* Check processor support. */
3614 found_cpu_match
= (cpu_flags_match (t
)
3615 == CPU_FLAGS_PERFECT_MATCH
);
3616 if (!found_cpu_match
)
3619 /* Check old gcc support. */
3620 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3623 /* Check AT&T mnemonic. */
3624 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3627 /* Check AT&T syntax Intel syntax. */
3628 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3629 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3632 /* Check the suffix, except for some instructions in intel mode. */
3633 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3634 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3635 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3636 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3637 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3638 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3639 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3642 if (!operand_size_match (t
))
3645 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3646 operand_types
[j
] = t
->operand_types
[j
];
3648 /* In general, don't allow 64-bit operands in 32-bit mode. */
3649 if (i
.suffix
== QWORD_MNEM_SUFFIX
3650 && flag_code
!= CODE_64BIT
3652 ? (!t
->opcode_modifier
.ignoresize
3653 && !intel_float_operand (t
->name
))
3654 : intel_float_operand (t
->name
) != 2)
3655 && ((!operand_types
[0].bitfield
.regmmx
3656 && !operand_types
[0].bitfield
.regxmm
3657 && !operand_types
[0].bitfield
.regymm
)
3658 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3659 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3660 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3661 && (t
->base_opcode
!= 0x0fc7
3662 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3665 /* In general, don't allow 32-bit operands on pre-386. */
3666 else if (i
.suffix
== LONG_MNEM_SUFFIX
3667 && !cpu_arch_flags
.bitfield
.cpui386
3669 ? (!t
->opcode_modifier
.ignoresize
3670 && !intel_float_operand (t
->name
))
3671 : intel_float_operand (t
->name
) != 2)
3672 && ((!operand_types
[0].bitfield
.regmmx
3673 && !operand_types
[0].bitfield
.regxmm
)
3674 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3675 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3678 /* Do not verify operands when there are none. */
3682 /* We've found a match; break out of loop. */
3686 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3687 into Disp32/Disp16/Disp32 operand. */
3688 if (i
.prefix
[ADDR_PREFIX
] != 0)
3690 /* There should be only one Disp operand. */
3694 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3696 if (operand_types
[j
].bitfield
.disp16
)
3698 addr_prefix_disp
= j
;
3699 operand_types
[j
].bitfield
.disp32
= 1;
3700 operand_types
[j
].bitfield
.disp16
= 0;
3706 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3708 if (operand_types
[j
].bitfield
.disp32
)
3710 addr_prefix_disp
= j
;
3711 operand_types
[j
].bitfield
.disp32
= 0;
3712 operand_types
[j
].bitfield
.disp16
= 1;
3718 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3720 if (operand_types
[j
].bitfield
.disp64
)
3722 addr_prefix_disp
= j
;
3723 operand_types
[j
].bitfield
.disp64
= 0;
3724 operand_types
[j
].bitfield
.disp32
= 1;
3732 /* We check register size only if size of operands can be
3733 encoded the canonical way. */
3734 check_register
= t
->opcode_modifier
.w
;
3735 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3736 switch (t
->operands
)
3739 if (!operand_type_match (overlap0
, i
.types
[0]))
3743 /* xchg %eax, %eax is a special case. It is an aliase for nop
3744 only in 32bit mode and we can use opcode 0x90. In 64bit
3745 mode, we can't use 0x90 for xchg %eax, %eax since it should
3746 zero-extend %eax to %rax. */
3747 if (flag_code
== CODE_64BIT
3748 && t
->base_opcode
== 0x90
3749 && operand_type_equal (&i
.types
[0], &acc32
)
3750 && operand_type_equal (&i
.types
[1], &acc32
))
3754 /* If we swap operand in encoding, we either match
3755 the next one or reverse direction of operands. */
3756 if (t
->opcode_modifier
.s
)
3758 else if (t
->opcode_modifier
.d
)
3763 /* If we swap operand in encoding, we match the next one. */
3764 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3768 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3769 if (!operand_type_match (overlap0
, i
.types
[0])
3770 || !operand_type_match (overlap1
, i
.types
[1])
3772 && !operand_type_register_match (overlap0
, i
.types
[0],
3774 overlap1
, i
.types
[1],
3777 /* Check if other direction is valid ... */
3778 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3782 /* Try reversing direction of operands. */
3783 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3784 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3785 if (!operand_type_match (overlap0
, i
.types
[0])
3786 || !operand_type_match (overlap1
, i
.types
[1])
3788 && !operand_type_register_match (overlap0
,
3795 /* Does not match either direction. */
3798 /* found_reverse_match holds which of D or FloatDR
3800 if (t
->opcode_modifier
.d
)
3801 found_reverse_match
= Opcode_D
;
3802 else if (t
->opcode_modifier
.floatd
)
3803 found_reverse_match
= Opcode_FloatD
;
3805 found_reverse_match
= 0;
3806 if (t
->opcode_modifier
.floatr
)
3807 found_reverse_match
|= Opcode_FloatR
;
3811 /* Found a forward 2 operand match here. */
3812 switch (t
->operands
)
3815 overlap4
= operand_type_and (i
.types
[4],
3818 overlap3
= operand_type_and (i
.types
[3],
3821 overlap2
= operand_type_and (i
.types
[2],
3826 switch (t
->operands
)
3829 if (!operand_type_match (overlap4
, i
.types
[4])
3830 || !operand_type_register_match (overlap3
,
3838 if (!operand_type_match (overlap3
, i
.types
[3])
3840 && !operand_type_register_match (overlap2
,
3848 /* Here we make use of the fact that there are no
3849 reverse match 3 operand instructions, and all 3
3850 operand instructions only need to be checked for
3851 register consistency between operands 2 and 3. */
3852 if (!operand_type_match (overlap2
, i
.types
[2])
3854 && !operand_type_register_match (overlap1
,
3864 /* Found either forward/reverse 2, 3 or 4 operand match here:
3865 slip through to break. */
3867 if (!found_cpu_match
)
3869 found_reverse_match
= 0;
3873 /* We've found a match; break out of loop. */
3877 if (t
== current_templates
->end
)
3879 /* We found no match. */
3881 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3882 current_templates
->start
->name
);
3884 as_bad (_("suffix or operands invalid for `%s'"),
3885 current_templates
->start
->name
);
3889 if (!quiet_warnings
)
3892 && (i
.types
[0].bitfield
.jumpabsolute
3893 != operand_types
[0].bitfield
.jumpabsolute
))
3895 as_warn (_("indirect %s without `*'"), t
->name
);
3898 if (t
->opcode_modifier
.isprefix
3899 && t
->opcode_modifier
.ignoresize
)
3901 /* Warn them that a data or address size prefix doesn't
3902 affect assembly of the next line of code. */
3903 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3907 /* Copy the template we found. */
3910 if (addr_prefix_disp
!= -1)
3911 i
.tm
.operand_types
[addr_prefix_disp
]
3912 = operand_types
[addr_prefix_disp
];
3914 if (found_reverse_match
)
3916 /* If we found a reverse match we must alter the opcode
3917 direction bit. found_reverse_match holds bits to change
3918 (different for int & float insns). */
3920 i
.tm
.base_opcode
^= found_reverse_match
;
3922 i
.tm
.operand_types
[0] = operand_types
[1];
3923 i
.tm
.operand_types
[1] = operand_types
[0];
3932 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3933 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3935 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3937 as_bad (_("`%s' operand %d must use `%ses' segment"),
3943 /* There's only ever one segment override allowed per instruction.
3944 This instruction possibly has a legal segment override on the
3945 second operand, so copy the segment to where non-string
3946 instructions store it, allowing common code. */
3947 i
.seg
[0] = i
.seg
[1];
3949 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3951 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3953 as_bad (_("`%s' operand %d must use `%ses' segment"),
3964 process_suffix (void)
3966 /* If matched instruction specifies an explicit instruction mnemonic
3968 if (i
.tm
.opcode_modifier
.size16
)
3969 i
.suffix
= WORD_MNEM_SUFFIX
;
3970 else if (i
.tm
.opcode_modifier
.size32
)
3971 i
.suffix
= LONG_MNEM_SUFFIX
;
3972 else if (i
.tm
.opcode_modifier
.size64
)
3973 i
.suffix
= QWORD_MNEM_SUFFIX
;
3974 else if (i
.reg_operands
)
3976 /* If there's no instruction mnemonic suffix we try to invent one
3977 based on register operands. */
3980 /* We take i.suffix from the last register operand specified,
3981 Destination register type is more significant than source
3982 register type. crc32 in SSE4.2 prefers source register
3984 if (i
.tm
.base_opcode
== 0xf20f38f1)
3986 if (i
.types
[0].bitfield
.reg16
)
3987 i
.suffix
= WORD_MNEM_SUFFIX
;
3988 else if (i
.types
[0].bitfield
.reg32
)
3989 i
.suffix
= LONG_MNEM_SUFFIX
;
3990 else if (i
.types
[0].bitfield
.reg64
)
3991 i
.suffix
= QWORD_MNEM_SUFFIX
;
3993 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3995 if (i
.types
[0].bitfield
.reg8
)
3996 i
.suffix
= BYTE_MNEM_SUFFIX
;
4003 if (i
.tm
.base_opcode
== 0xf20f38f1
4004 || i
.tm
.base_opcode
== 0xf20f38f0)
4006 /* We have to know the operand size for crc32. */
4007 as_bad (_("ambiguous memory operand size for `%s`"),
4012 for (op
= i
.operands
; --op
>= 0;)
4013 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4015 if (i
.types
[op
].bitfield
.reg8
)
4017 i
.suffix
= BYTE_MNEM_SUFFIX
;
4020 else if (i
.types
[op
].bitfield
.reg16
)
4022 i
.suffix
= WORD_MNEM_SUFFIX
;
4025 else if (i
.types
[op
].bitfield
.reg32
)
4027 i
.suffix
= LONG_MNEM_SUFFIX
;
4030 else if (i
.types
[op
].bitfield
.reg64
)
4032 i
.suffix
= QWORD_MNEM_SUFFIX
;
4038 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4040 if (!check_byte_reg ())
4043 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4045 if (!check_long_reg ())
4048 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4051 && i
.tm
.opcode_modifier
.ignoresize
4052 && i
.tm
.opcode_modifier
.no_qsuf
)
4054 else if (!check_qword_reg ())
4057 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4059 if (!check_word_reg ())
4062 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4063 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4065 /* Skip if the instruction has x/y suffix. match_template
4066 should check if it is a valid suffix. */
4068 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4069 /* Do nothing if the instruction is going to ignore the prefix. */
4074 else if (i
.tm
.opcode_modifier
.defaultsize
4076 /* exclude fldenv/frstor/fsave/fstenv */
4077 && i
.tm
.opcode_modifier
.no_ssuf
)
4079 i
.suffix
= stackop_size
;
4081 else if (intel_syntax
4083 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4084 || i
.tm
.opcode_modifier
.jumpbyte
4085 || i
.tm
.opcode_modifier
.jumpintersegment
4086 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4087 && i
.tm
.extension_opcode
<= 3)))
4092 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4094 i
.suffix
= QWORD_MNEM_SUFFIX
;
4098 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4099 i
.suffix
= LONG_MNEM_SUFFIX
;
4102 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4103 i
.suffix
= WORD_MNEM_SUFFIX
;
4112 if (i
.tm
.opcode_modifier
.w
)
4114 as_bad (_("no instruction mnemonic suffix given and "
4115 "no register operands; can't size instruction"));
4121 unsigned int suffixes
;
4123 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4124 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4126 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4128 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4130 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4132 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4135 /* There are more than suffix matches. */
4136 if (i
.tm
.opcode_modifier
.w
4137 || ((suffixes
& (suffixes
- 1))
4138 && !i
.tm
.opcode_modifier
.defaultsize
4139 && !i
.tm
.opcode_modifier
.ignoresize
))
4141 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4147 /* Change the opcode based on the operand size given by i.suffix;
4148 We don't need to change things for byte insns. */
4151 && i
.suffix
!= BYTE_MNEM_SUFFIX
4152 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4153 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4155 /* It's not a byte, select word/dword operation. */
4156 if (i
.tm
.opcode_modifier
.w
)
4158 if (i
.tm
.opcode_modifier
.shortform
)
4159 i
.tm
.base_opcode
|= 8;
4161 i
.tm
.base_opcode
|= 1;
4164 /* Now select between word & dword operations via the operand
4165 size prefix, except for instructions that will ignore this
4167 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4169 /* The address size override prefix changes the size of the
4171 if ((flag_code
== CODE_32BIT
4172 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4173 || (flag_code
!= CODE_32BIT
4174 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4175 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4178 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4179 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4180 && !i
.tm
.opcode_modifier
.ignoresize
4181 && !i
.tm
.opcode_modifier
.floatmf
4182 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4183 || (flag_code
== CODE_64BIT
4184 && i
.tm
.opcode_modifier
.jumpbyte
)))
4186 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4188 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4189 prefix
= ADDR_PREFIX_OPCODE
;
4191 if (!add_prefix (prefix
))
4195 /* Set mode64 for an operand. */
4196 if (i
.suffix
== QWORD_MNEM_SUFFIX
4197 && flag_code
== CODE_64BIT
4198 && !i
.tm
.opcode_modifier
.norex64
)
4200 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4201 need rex64. cmpxchg8b is also a special case. */
4202 if (! (i
.operands
== 2
4203 && i
.tm
.base_opcode
== 0x90
4204 && i
.tm
.extension_opcode
== None
4205 && operand_type_equal (&i
.types
[0], &acc64
)
4206 && operand_type_equal (&i
.types
[1], &acc64
))
4207 && ! (i
.operands
== 1
4208 && i
.tm
.base_opcode
== 0xfc7
4209 && i
.tm
.extension_opcode
== 1
4210 && !operand_type_check (i
.types
[0], reg
)
4211 && operand_type_check (i
.types
[0], anymem
)))
4215 /* Size floating point instruction. */
4216 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4217 if (i
.tm
.opcode_modifier
.floatmf
)
4218 i
.tm
.base_opcode
^= 4;
4225 check_byte_reg (void)
4229 for (op
= i
.operands
; --op
>= 0;)
4231 /* If this is an eight bit register, it's OK. If it's the 16 or
4232 32 bit version of an eight bit register, we will just use the
4233 low portion, and that's OK too. */
4234 if (i
.types
[op
].bitfield
.reg8
)
4237 /* Don't generate this warning if not needed. */
4238 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4241 /* crc32 doesn't generate this warning. */
4242 if (i
.tm
.base_opcode
== 0xf20f38f0)
4245 if ((i
.types
[op
].bitfield
.reg16
4246 || i
.types
[op
].bitfield
.reg32
4247 || i
.types
[op
].bitfield
.reg64
)
4248 && i
.op
[op
].regs
->reg_num
< 4)
4250 /* Prohibit these changes in the 64bit mode, since the
4251 lowering is more complicated. */
4252 if (flag_code
== CODE_64BIT
4253 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4255 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4256 register_prefix
, i
.op
[op
].regs
->reg_name
,
4260 #if REGISTER_WARNINGS
4262 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4263 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4265 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4266 ? REGNAM_AL
- REGNAM_AX
4267 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4269 i
.op
[op
].regs
->reg_name
,
4274 /* Any other register is bad. */
4275 if (i
.types
[op
].bitfield
.reg16
4276 || i
.types
[op
].bitfield
.reg32
4277 || i
.types
[op
].bitfield
.reg64
4278 || i
.types
[op
].bitfield
.regmmx
4279 || i
.types
[op
].bitfield
.regxmm
4280 || i
.types
[op
].bitfield
.regymm
4281 || i
.types
[op
].bitfield
.sreg2
4282 || i
.types
[op
].bitfield
.sreg3
4283 || i
.types
[op
].bitfield
.control
4284 || i
.types
[op
].bitfield
.debug
4285 || i
.types
[op
].bitfield
.test
4286 || i
.types
[op
].bitfield
.floatreg
4287 || i
.types
[op
].bitfield
.floatacc
)
4289 as_bad (_("`%s%s' not allowed with `%s%c'"),
4291 i
.op
[op
].regs
->reg_name
,
4301 check_long_reg (void)
4305 for (op
= i
.operands
; --op
>= 0;)
4306 /* Reject eight bit registers, except where the template requires
4307 them. (eg. movzb) */
4308 if (i
.types
[op
].bitfield
.reg8
4309 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4310 || i
.tm
.operand_types
[op
].bitfield
.reg32
4311 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4313 as_bad (_("`%s%s' not allowed with `%s%c'"),
4315 i
.op
[op
].regs
->reg_name
,
4320 /* Warn if the e prefix on a general reg is missing. */
4321 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4322 && i
.types
[op
].bitfield
.reg16
4323 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4324 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4326 /* Prohibit these changes in the 64bit mode, since the
4327 lowering is more complicated. */
4328 if (flag_code
== CODE_64BIT
)
4330 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4331 register_prefix
, i
.op
[op
].regs
->reg_name
,
4335 #if REGISTER_WARNINGS
4337 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4339 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4341 i
.op
[op
].regs
->reg_name
,
4345 /* Warn if the r prefix on a general reg is missing. */
4346 else if (i
.types
[op
].bitfield
.reg64
4347 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4348 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4351 && i
.tm
.opcode_modifier
.toqword
4352 && !i
.types
[0].bitfield
.regxmm
)
4354 /* Convert to QWORD. We want REX byte. */
4355 i
.suffix
= QWORD_MNEM_SUFFIX
;
4359 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4360 register_prefix
, i
.op
[op
].regs
->reg_name
,
4369 check_qword_reg (void)
4373 for (op
= i
.operands
; --op
>= 0; )
4374 /* Reject eight bit registers, except where the template requires
4375 them. (eg. movzb) */
4376 if (i
.types
[op
].bitfield
.reg8
4377 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4378 || i
.tm
.operand_types
[op
].bitfield
.reg32
4379 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4381 as_bad (_("`%s%s' not allowed with `%s%c'"),
4383 i
.op
[op
].regs
->reg_name
,
4388 /* Warn if the e prefix on a general reg is missing. */
4389 else if ((i
.types
[op
].bitfield
.reg16
4390 || i
.types
[op
].bitfield
.reg32
)
4391 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4392 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4394 /* Prohibit these changes in the 64bit mode, since the
4395 lowering is more complicated. */
4397 && i
.tm
.opcode_modifier
.todword
4398 && !i
.types
[0].bitfield
.regxmm
)
4400 /* Convert to DWORD. We don't want REX byte. */
4401 i
.suffix
= LONG_MNEM_SUFFIX
;
4405 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4406 register_prefix
, i
.op
[op
].regs
->reg_name
,
4415 check_word_reg (void)
4418 for (op
= i
.operands
; --op
>= 0;)
4419 /* Reject eight bit registers, except where the template requires
4420 them. (eg. movzb) */
4421 if (i
.types
[op
].bitfield
.reg8
4422 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4423 || i
.tm
.operand_types
[op
].bitfield
.reg32
4424 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4426 as_bad (_("`%s%s' not allowed with `%s%c'"),
4428 i
.op
[op
].regs
->reg_name
,
4433 /* Warn if the e prefix on a general reg is present. */
4434 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4435 && i
.types
[op
].bitfield
.reg32
4436 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4437 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4439 /* Prohibit these changes in the 64bit mode, since the
4440 lowering is more complicated. */
4441 if (flag_code
== CODE_64BIT
)
4443 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4444 register_prefix
, i
.op
[op
].regs
->reg_name
,
4449 #if REGISTER_WARNINGS
4450 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4452 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4454 i
.op
[op
].regs
->reg_name
,
4462 update_imm (unsigned int j
)
4464 i386_operand_type overlap
;
4466 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4467 if ((overlap
.bitfield
.imm8
4468 || overlap
.bitfield
.imm8s
4469 || overlap
.bitfield
.imm16
4470 || overlap
.bitfield
.imm32
4471 || overlap
.bitfield
.imm32s
4472 || overlap
.bitfield
.imm64
)
4473 && !operand_type_equal (&overlap
, &imm8
)
4474 && !operand_type_equal (&overlap
, &imm8s
)
4475 && !operand_type_equal (&overlap
, &imm16
)
4476 && !operand_type_equal (&overlap
, &imm32
)
4477 && !operand_type_equal (&overlap
, &imm32s
)
4478 && !operand_type_equal (&overlap
, &imm64
))
4482 i386_operand_type temp
;
4484 operand_type_set (&temp
, 0);
4485 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4487 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4488 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4490 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4491 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4492 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4494 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4495 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4498 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4501 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4502 || operand_type_equal (&overlap
, &imm16_32
)
4503 || operand_type_equal (&overlap
, &imm16_32s
))
4505 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4510 if (!operand_type_equal (&overlap
, &imm8
)
4511 && !operand_type_equal (&overlap
, &imm8s
)
4512 && !operand_type_equal (&overlap
, &imm16
)
4513 && !operand_type_equal (&overlap
, &imm32
)
4514 && !operand_type_equal (&overlap
, &imm32s
)
4515 && !operand_type_equal (&overlap
, &imm64
))
4517 as_bad (_("no instruction mnemonic suffix given; "
4518 "can't determine immediate size"));
4522 i
.types
[j
] = overlap
;
4532 for (j
= 0; j
< 2; j
++)
4533 if (update_imm (j
) == 0)
4536 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4537 assert (operand_type_check (i
.types
[2], imm
) == 0);
4545 i
.drex
.modrm_reg
= 0;
4546 i
.drex
.modrm_regmem
= 0;
4548 /* SSE5 4 operand instructions must have the destination the same as
4549 one of the inputs. Figure out the destination register and cache
4550 it away in the drex field, and remember which fields to use for
4552 if (i
.tm
.opcode_modifier
.drex
4553 && i
.tm
.opcode_modifier
.drexv
4556 i
.tm
.extension_opcode
= None
;
4558 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4559 if (i
.types
[0].bitfield
.regxmm
!= 0
4560 && i
.types
[1].bitfield
.regxmm
!= 0
4561 && i
.types
[2].bitfield
.regxmm
!= 0
4562 && i
.types
[3].bitfield
.regxmm
!= 0
4563 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4564 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4566 /* Clear the arguments that are stored in drex. */
4567 operand_type_set (&i
.types
[0], 0);
4568 operand_type_set (&i
.types
[3], 0);
4569 i
.reg_operands
-= 2;
4571 /* There are two different ways to encode a 4 operand
4572 instruction with all registers that uses OC1 set to
4573 0 or 1. Favor setting OC1 to 0 since this mimics the
4574 actions of other SSE5 assemblers. Use modrm encoding 2
4575 for register/register. Include the high order bit that
4576 is normally stored in the REX byte in the register
4578 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4579 i
.drex
.modrm_reg
= 2;
4580 i
.drex
.modrm_regmem
= 1;
4581 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4582 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4585 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4586 else if (i
.types
[0].bitfield
.regxmm
!= 0
4587 && i
.types
[1].bitfield
.regxmm
!= 0
4588 && (i
.types
[2].bitfield
.regxmm
4589 || operand_type_check (i
.types
[2], anymem
))
4590 && i
.types
[3].bitfield
.regxmm
!= 0
4591 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4592 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4594 /* clear the arguments that are stored in drex */
4595 operand_type_set (&i
.types
[0], 0);
4596 operand_type_set (&i
.types
[3], 0);
4597 i
.reg_operands
-= 2;
4599 /* Specify the modrm encoding for memory addressing. Include
4600 the high order bit that is normally stored in the REX byte
4601 in the register field. */
4602 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4603 i
.drex
.modrm_reg
= 1;
4604 i
.drex
.modrm_regmem
= 2;
4605 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4606 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4609 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4610 else if (i
.types
[0].bitfield
.regxmm
!= 0
4611 && operand_type_check (i
.types
[1], anymem
) != 0
4612 && i
.types
[2].bitfield
.regxmm
!= 0
4613 && i
.types
[3].bitfield
.regxmm
!= 0
4614 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4615 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4617 /* Clear the arguments that are stored in drex. */
4618 operand_type_set (&i
.types
[0], 0);
4619 operand_type_set (&i
.types
[3], 0);
4620 i
.reg_operands
-= 2;
4622 /* Specify the modrm encoding for memory addressing. Include
4623 the high order bit that is normally stored in the REX byte
4624 in the register field. */
4625 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4626 i
.drex
.modrm_reg
= 2;
4627 i
.drex
.modrm_regmem
= 1;
4628 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4629 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4632 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4633 else if (i
.types
[0].bitfield
.regxmm
!= 0
4634 && i
.types
[1].bitfield
.regxmm
!= 0
4635 && i
.types
[2].bitfield
.regxmm
!= 0
4636 && i
.types
[3].bitfield
.regxmm
!= 0
4637 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4638 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4640 /* clear the arguments that are stored in drex */
4641 operand_type_set (&i
.types
[2], 0);
4642 operand_type_set (&i
.types
[3], 0);
4643 i
.reg_operands
-= 2;
4645 /* There are two different ways to encode a 4 operand
4646 instruction with all registers that uses OC1 set to
4647 0 or 1. Favor setting OC1 to 0 since this mimics the
4648 actions of other SSE5 assemblers. Use modrm encoding
4649 2 for register/register. Include the high order bit that
4650 is normally stored in the REX byte in the register
4652 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4653 i
.drex
.modrm_reg
= 1;
4654 i
.drex
.modrm_regmem
= 0;
4656 /* Remember the register, including the upper bits */
4657 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4658 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4661 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4662 else if (i
.types
[0].bitfield
.regxmm
!= 0
4663 && (i
.types
[1].bitfield
.regxmm
4664 || operand_type_check (i
.types
[1], anymem
))
4665 && i
.types
[2].bitfield
.regxmm
!= 0
4666 && i
.types
[3].bitfield
.regxmm
!= 0
4667 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4668 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4670 /* Clear the arguments that are stored in drex. */
4671 operand_type_set (&i
.types
[2], 0);
4672 operand_type_set (&i
.types
[3], 0);
4673 i
.reg_operands
-= 2;
4675 /* Specify the modrm encoding and remember the register
4676 including the bits normally stored in the REX byte. */
4677 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4678 i
.drex
.modrm_reg
= 0;
4679 i
.drex
.modrm_regmem
= 1;
4680 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4681 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4684 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4685 else if (operand_type_check (i
.types
[0], anymem
) != 0
4686 && i
.types
[1].bitfield
.regxmm
!= 0
4687 && i
.types
[2].bitfield
.regxmm
!= 0
4688 && i
.types
[3].bitfield
.regxmm
!= 0
4689 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4690 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4692 /* clear the arguments that are stored in drex */
4693 operand_type_set (&i
.types
[2], 0);
4694 operand_type_set (&i
.types
[3], 0);
4695 i
.reg_operands
-= 2;
4697 /* Specify the modrm encoding and remember the register
4698 including the bits normally stored in the REX byte. */
4699 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4700 i
.drex
.modrm_reg
= 1;
4701 i
.drex
.modrm_regmem
= 0;
4702 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4703 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4707 as_bad (_("Incorrect operands for the '%s' instruction"),
4711 /* SSE5 instructions with the DREX byte where the only memory operand
4712 is in the 2nd argument, and the first and last xmm register must
4713 match, and is encoded in the DREX byte. */
4714 else if (i
.tm
.opcode_modifier
.drex
4715 && !i
.tm
.opcode_modifier
.drexv
4718 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4719 if (i
.types
[0].bitfield
.regxmm
!= 0
4720 && (i
.types
[1].bitfield
.regxmm
4721 || operand_type_check(i
.types
[1], anymem
))
4722 && i
.types
[2].bitfield
.regxmm
!= 0
4723 && i
.types
[3].bitfield
.regxmm
!= 0
4724 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4725 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4727 /* clear the arguments that are stored in drex */
4728 operand_type_set (&i
.types
[0], 0);
4729 operand_type_set (&i
.types
[3], 0);
4730 i
.reg_operands
-= 2;
4732 /* Specify the modrm encoding and remember the register
4733 including the high bit normally stored in the REX
4735 i
.drex
.modrm_reg
= 2;
4736 i
.drex
.modrm_regmem
= 1;
4737 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4738 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4742 as_bad (_("Incorrect operands for the '%s' instruction"),
4746 /* SSE5 3 operand instructions that the result is a register, being
4747 either operand can be a memory operand, using OC0 to note which
4748 one is the memory. */
4749 else if (i
.tm
.opcode_modifier
.drex
4750 && i
.tm
.opcode_modifier
.drexv
4753 i
.tm
.extension_opcode
= None
;
4755 /* Case 1: 3 operand insn, src1 = register. */
4756 if (i
.types
[0].bitfield
.regxmm
!= 0
4757 && i
.types
[1].bitfield
.regxmm
!= 0
4758 && i
.types
[2].bitfield
.regxmm
!= 0)
4760 /* Clear the arguments that are stored in drex. */
4761 operand_type_set (&i
.types
[2], 0);
4764 /* Specify the modrm encoding and remember the register
4765 including the high bit normally stored in the REX byte. */
4766 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4767 i
.drex
.modrm_reg
= 1;
4768 i
.drex
.modrm_regmem
= 0;
4769 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4770 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4773 /* Case 2: 3 operand insn, src1 = memory. */
4774 else if (operand_type_check (i
.types
[0], anymem
) != 0
4775 && i
.types
[1].bitfield
.regxmm
!= 0
4776 && i
.types
[2].bitfield
.regxmm
!= 0)
4778 /* Clear the arguments that are stored in drex. */
4779 operand_type_set (&i
.types
[2], 0);
4782 /* Specify the modrm encoding and remember the register
4783 including the high bit normally stored in the REX
4785 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4786 i
.drex
.modrm_reg
= 1;
4787 i
.drex
.modrm_regmem
= 0;
4788 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4789 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4792 /* Case 3: 3 operand insn, src2 = memory. */
4793 else if (i
.types
[0].bitfield
.regxmm
!= 0
4794 && operand_type_check (i
.types
[1], anymem
) != 0
4795 && i
.types
[2].bitfield
.regxmm
!= 0)
4797 /* Clear the arguments that are stored in drex. */
4798 operand_type_set (&i
.types
[2], 0);
4801 /* Specify the modrm encoding and remember the register
4802 including the high bit normally stored in the REX byte. */
4803 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4804 i
.drex
.modrm_reg
= 0;
4805 i
.drex
.modrm_regmem
= 1;
4806 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4807 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4811 as_bad (_("Incorrect operands for the '%s' instruction"),
4815 /* SSE5 4 operand instructions that are the comparison instructions
4816 where the first operand is the immediate value of the comparison
4818 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4820 /* Case 1: 4 operand insn, src1 = reg/memory. */
4821 if (operand_type_check (i
.types
[0], imm
) != 0
4822 && (i
.types
[1].bitfield
.regxmm
4823 || operand_type_check (i
.types
[1], anymem
))
4824 && i
.types
[2].bitfield
.regxmm
!= 0
4825 && i
.types
[3].bitfield
.regxmm
!= 0)
4827 /* clear the arguments that are stored in drex */
4828 operand_type_set (&i
.types
[3], 0);
4831 /* Specify the modrm encoding and remember the register
4832 including the high bit normally stored in the REX byte. */
4833 i
.drex
.modrm_reg
= 2;
4834 i
.drex
.modrm_regmem
= 1;
4835 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4836 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4839 /* Case 2: 3 operand insn with ImmExt that places the
4840 opcode_extension as an immediate argument. This is used for
4841 all of the varients of comparison that supplies the appropriate
4842 value as part of the instruction. */
4843 else if ((i
.types
[0].bitfield
.regxmm
4844 || operand_type_check (i
.types
[0], anymem
))
4845 && i
.types
[1].bitfield
.regxmm
!= 0
4846 && i
.types
[2].bitfield
.regxmm
!= 0
4847 && operand_type_check (i
.types
[3], imm
) != 0)
4849 /* clear the arguments that are stored in drex */
4850 operand_type_set (&i
.types
[2], 0);
4853 /* Specify the modrm encoding and remember the register
4854 including the high bit normally stored in the REX byte. */
4855 i
.drex
.modrm_reg
= 1;
4856 i
.drex
.modrm_regmem
= 0;
4857 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4858 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4862 as_bad (_("Incorrect operands for the '%s' instruction"),
4866 else if (i
.tm
.opcode_modifier
.drex
4867 || i
.tm
.opcode_modifier
.drexv
4868 || i
.tm
.opcode_modifier
.drexc
)
4869 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4873 bad_implicit_operand (int xmm
)
4875 const char *reg
= xmm
? "xmm0" : "ymm0";
4877 as_bad (_("the last operand of `%s' must be `%s%s'"),
4878 i
.tm
.name
, register_prefix
, reg
);
4880 as_bad (_("the first operand of `%s' must be `%s%s'"),
4881 i
.tm
.name
, register_prefix
, reg
);
4886 process_operands (void)
4888 /* Default segment register this instruction will use for memory
4889 accesses. 0 means unknown. This is only for optimizing out
4890 unnecessary segment overrides. */
4891 const seg_entry
*default_seg
= 0;
4893 /* Handle all of the DREX munging that SSE5 needs. */
4894 if (i
.tm
.opcode_modifier
.drex
4895 || i
.tm
.opcode_modifier
.drexv
4896 || i
.tm
.opcode_modifier
.drexc
)
4899 if (i
.tm
.opcode_modifier
.sse2avx
4900 && (i
.tm
.opcode_modifier
.vexnds
4901 || i
.tm
.opcode_modifier
.vexndd
))
4903 unsigned int dup
= i
.operands
;
4904 unsigned int dest
= dup
- 1;
4907 /* The destination must be an xmm register. */
4908 assert (i
.reg_operands
4909 && MAX_OPERANDS
> dup
4910 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4912 if (i
.tm
.opcode_modifier
.firstxmm0
)
4914 /* The first operand is implicit and must be xmm0. */
4915 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4916 if (i
.op
[0].regs
->reg_num
!= 0)
4917 return bad_implicit_operand (1);
4919 if (i
.tm
.opcode_modifier
.vex3sources
)
4921 /* Keep xmm0 for instructions with VEX prefix and 3
4927 /* We remove the first xmm0 and keep the number of
4928 operands unchanged, which in fact duplicates the
4930 for (j
= 1; j
< i
.operands
; j
++)
4932 i
.op
[j
- 1] = i
.op
[j
];
4933 i
.types
[j
- 1] = i
.types
[j
];
4934 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4938 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4940 assert ((MAX_OPERANDS
- 1) > dup
4941 && i
.tm
.opcode_modifier
.vex3sources
);
4943 /* Add the implicit xmm0 for instructions with VEX prefix
4945 for (j
= i
.operands
; j
> 0; j
--)
4947 i
.op
[j
] = i
.op
[j
- 1];
4948 i
.types
[j
] = i
.types
[j
- 1];
4949 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4952 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4953 i
.types
[0] = regxmm
;
4954 i
.tm
.operand_types
[0] = regxmm
;
4957 i
.reg_operands
+= 2;
4962 i
.op
[dup
] = i
.op
[dest
];
4963 i
.types
[dup
] = i
.types
[dest
];
4964 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4973 i
.op
[dup
] = i
.op
[dest
];
4974 i
.types
[dup
] = i
.types
[dest
];
4975 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4978 if (i
.tm
.opcode_modifier
.immext
)
4981 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4985 /* The first operand is implicit and must be xmm0/ymm0. */
4986 assert (i
.reg_operands
4987 && (operand_type_equal (&i
.types
[0], ®xmm
)
4988 || operand_type_equal (&i
.types
[0], ®ymm
)));
4989 if (i
.op
[0].regs
->reg_num
!= 0)
4990 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4992 for (j
= 1; j
< i
.operands
; j
++)
4994 i
.op
[j
- 1] = i
.op
[j
];
4995 i
.types
[j
- 1] = i
.types
[j
];
4997 /* We need to adjust fields in i.tm since they are used by
4998 build_modrm_byte. */
4999 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5006 else if (i
.tm
.opcode_modifier
.regkludge
)
5008 /* The imul $imm, %reg instruction is converted into
5009 imul $imm, %reg, %reg, and the clr %reg instruction
5010 is converted into xor %reg, %reg. */
5012 unsigned int first_reg_op
;
5014 if (operand_type_check (i
.types
[0], reg
))
5018 /* Pretend we saw the extra register operand. */
5019 assert (i
.reg_operands
== 1
5020 && i
.op
[first_reg_op
+ 1].regs
== 0);
5021 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5022 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5027 if (i
.tm
.opcode_modifier
.shortform
)
5029 if (i
.types
[0].bitfield
.sreg2
5030 || i
.types
[0].bitfield
.sreg3
)
5032 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5033 && i
.op
[0].regs
->reg_num
== 1)
5035 as_bad (_("you can't `pop %scs'"), register_prefix
);
5038 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5039 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5044 /* The register or float register operand is in operand
5048 if (i
.types
[0].bitfield
.floatreg
5049 || operand_type_check (i
.types
[0], reg
))
5053 /* Register goes in low 3 bits of opcode. */
5054 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5055 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5057 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5059 /* Warn about some common errors, but press on regardless.
5060 The first case can be generated by gcc (<= 2.8.1). */
5061 if (i
.operands
== 2)
5063 /* Reversed arguments on faddp, fsubp, etc. */
5064 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5065 register_prefix
, i
.op
[1].regs
->reg_name
,
5066 register_prefix
, i
.op
[0].regs
->reg_name
);
5070 /* Extraneous `l' suffix on fp insn. */
5071 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5072 register_prefix
, i
.op
[0].regs
->reg_name
);
5077 else if (i
.tm
.opcode_modifier
.modrm
)
5079 /* The opcode is completed (modulo i.tm.extension_opcode which
5080 must be put into the modrm byte). Now, we make the modrm and
5081 index base bytes based on all the info we've collected. */
5083 default_seg
= build_modrm_byte ();
5085 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5089 else if (i
.tm
.opcode_modifier
.isstring
)
5091 /* For the string instructions that allow a segment override
5092 on one of their operands, the default segment is ds. */
5096 if (i
.tm
.base_opcode
== 0x8d /* lea */
5099 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5101 /* If a segment was explicitly specified, and the specified segment
5102 is not the default, use an opcode prefix to select it. If we
5103 never figured out what the default segment is, then default_seg
5104 will be zero at this point, and the specified segment prefix will
5106 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5108 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5114 static const seg_entry
*
5115 build_modrm_byte (void)
5117 const seg_entry
*default_seg
= 0;
5118 unsigned int source
, dest
;
5121 /* The first operand of instructions with VEX prefix and 3 sources
5122 must be VEX_Imm4. */
5123 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5126 unsigned int nds
, reg
;
5128 dest
= i
.operands
- 1;
5133 /* This instruction must have 4 operands: 4 register operands
5134 or 3 register operands plus 1 memory operand. It must have
5135 VexNDS and VexImmExt. */
5136 assert (i
.operands
== 4
5137 && (i
.reg_operands
== 4
5138 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5139 && i
.tm
.opcode_modifier
.vexnds
5140 && i
.tm
.opcode_modifier
.veximmext
5141 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
5143 || operand_type_equal (&i
.tm
.operand_types
[dest
],
5145 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
5147 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5149 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
5151 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5154 /* Generate an 8bit immediate operand to encode the register
5156 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5157 i
.op
[i
.operands
].imms
= exp
;
5158 i
.types
[i
.operands
] = imm8
;
5160 exp
->X_op
= O_constant
;
5162 = ((i
.op
[0].regs
->reg_num
5163 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5165 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5170 /* SSE5 4 operand instructions are encoded in such a way that one of
5171 the inputs must match the destination register. Process_drex hides
5172 the 3rd argument in the drex field, so that by the time we get
5173 here, it looks to GAS as if this is a 2 operand instruction. */
5174 if ((i
.tm
.opcode_modifier
.drex
5175 || i
.tm
.opcode_modifier
.drexv
5176 || i
.tm
.opcode_modifier
.drexc
)
5177 && i
.reg_operands
== 2)
5179 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5180 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5182 i
.rm
.reg
= reg
->reg_num
;
5183 i
.rm
.regmem
= regmem
->reg_num
;
5185 if ((reg
->reg_flags
& RegRex
) != 0)
5187 if ((regmem
->reg_flags
& RegRex
) != 0)
5191 /* i.reg_operands MUST be the number of real register operands;
5192 implicit registers do not count. If there are 3 register
5193 operands, it must be a instruction with VexNDS. For a
5194 instruction with VexNDD, the destination register is encoded
5195 in VEX prefix. If there are 4 register operands, it must be
5196 a instruction with VEX prefix and 3 sources. */
5197 else if (i
.mem_operands
== 0
5198 && ((i
.reg_operands
== 2
5199 && !i
.tm
.opcode_modifier
.vexndd
)
5200 || (i
.reg_operands
== 3
5201 && i
.tm
.opcode_modifier
.vexnds
)
5202 || (i
.reg_operands
== 4 && vex_3_sources
)))
5210 /* When there are 3 operands, one of them may be immediate,
5211 which may be the first or the last operand. Otherwise,
5212 the first operand must be shift count register (cl) or it
5213 is an instruction with VexNDS. */
5214 assert (i
.imm_operands
== 1
5215 || (i
.imm_operands
== 0
5216 && (i
.tm
.opcode_modifier
.vexnds
5217 || i
.types
[0].bitfield
.shiftcount
)));
5218 if (operand_type_check (i
.types
[0], imm
)
5219 || i
.types
[0].bitfield
.shiftcount
)
5225 /* When there are 4 operands, the first two must be 8bit
5226 immediate operands. The source operand will be the 3rd
5229 For instructions with VexNDS, if the first operand
5230 an imm8, the source operand is the 2nd one. If the last
5231 operand is imm8, the source operand is the first one. */
5232 assert ((i
.imm_operands
== 2
5233 && i
.types
[0].bitfield
.imm8
5234 && i
.types
[1].bitfield
.imm8
)
5235 || (i
.tm
.opcode_modifier
.vexnds
5236 && i
.imm_operands
== 1
5237 && (i
.types
[0].bitfield
.imm8
5238 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5239 if (i
.tm
.opcode_modifier
.vexnds
)
5241 if (i
.types
[0].bitfield
.imm8
)
5259 if (i
.tm
.opcode_modifier
.vexnds
)
5261 /* For instructions with VexNDS, the register-only
5262 source operand must be XMM or YMM register. It is
5263 encoded in VEX prefix. We need to clear RegMem bit
5264 before calling operand_type_equal. */
5265 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5266 op
.bitfield
.regmem
= 0;
5267 if ((dest
+ 1) >= i
.operands
5268 || (!operand_type_equal (&op
, ®xmm
)
5269 && !operand_type_equal (&op
, ®ymm
)))
5271 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5277 /* One of the register operands will be encoded in the i.tm.reg
5278 field, the other in the combined i.tm.mode and i.tm.regmem
5279 fields. If no form of this instruction supports a memory
5280 destination operand, then we assume the source operand may
5281 sometimes be a memory operand and so we need to store the
5282 destination in the i.rm.reg field. */
5283 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5284 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5286 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5287 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5288 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5290 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5295 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5296 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5297 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5299 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5302 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5304 if (!i
.types
[0].bitfield
.control
5305 && !i
.types
[1].bitfield
.control
)
5307 i
.rex
&= ~(REX_R
| REX_B
);
5308 add_prefix (LOCK_PREFIX_OPCODE
);
5312 { /* If it's not 2 reg operands... */
5317 unsigned int fake_zero_displacement
= 0;
5320 /* This has been precalculated for SSE5 instructions
5321 that have a DREX field earlier in process_drex. */
5322 if (i
.tm
.opcode_modifier
.drex
5323 || i
.tm
.opcode_modifier
.drexv
5324 || i
.tm
.opcode_modifier
.drexc
)
5325 op
= i
.drex
.modrm_regmem
;
5328 for (op
= 0; op
< i
.operands
; op
++)
5329 if (operand_type_check (i
.types
[op
], anymem
))
5331 assert (op
< i
.operands
);
5336 if (i
.base_reg
== 0)
5339 if (!i
.disp_operands
)
5340 fake_zero_displacement
= 1;
5341 if (i
.index_reg
== 0)
5343 /* Operand is just <disp> */
5344 if (flag_code
== CODE_64BIT
)
5346 /* 64bit mode overwrites the 32bit absolute
5347 addressing by RIP relative addressing and
5348 absolute addressing is encoded by one of the
5349 redundant SIB forms. */
5350 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5351 i
.sib
.base
= NO_BASE_REGISTER
;
5352 i
.sib
.index
= NO_INDEX_REGISTER
;
5353 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5354 ? disp32s
: disp32
);
5356 else if ((flag_code
== CODE_16BIT
)
5357 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5359 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5360 i
.types
[op
] = disp16
;
5364 i
.rm
.regmem
= NO_BASE_REGISTER
;
5365 i
.types
[op
] = disp32
;
5368 else /* !i.base_reg && i.index_reg */
5370 if (i
.index_reg
->reg_num
== RegEiz
5371 || i
.index_reg
->reg_num
== RegRiz
)
5372 i
.sib
.index
= NO_INDEX_REGISTER
;
5374 i
.sib
.index
= i
.index_reg
->reg_num
;
5375 i
.sib
.base
= NO_BASE_REGISTER
;
5376 i
.sib
.scale
= i
.log2_scale_factor
;
5377 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5378 i
.types
[op
].bitfield
.disp8
= 0;
5379 i
.types
[op
].bitfield
.disp16
= 0;
5380 i
.types
[op
].bitfield
.disp64
= 0;
5381 if (flag_code
!= CODE_64BIT
)
5383 /* Must be 32 bit */
5384 i
.types
[op
].bitfield
.disp32
= 1;
5385 i
.types
[op
].bitfield
.disp32s
= 0;
5389 i
.types
[op
].bitfield
.disp32
= 0;
5390 i
.types
[op
].bitfield
.disp32s
= 1;
5392 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5396 /* RIP addressing for 64bit mode. */
5397 else if (i
.base_reg
->reg_num
== RegRip
||
5398 i
.base_reg
->reg_num
== RegEip
)
5400 i
.rm
.regmem
= NO_BASE_REGISTER
;
5401 i
.types
[op
].bitfield
.disp8
= 0;
5402 i
.types
[op
].bitfield
.disp16
= 0;
5403 i
.types
[op
].bitfield
.disp32
= 0;
5404 i
.types
[op
].bitfield
.disp32s
= 1;
5405 i
.types
[op
].bitfield
.disp64
= 0;
5406 i
.flags
[op
] |= Operand_PCrel
;
5407 if (! i
.disp_operands
)
5408 fake_zero_displacement
= 1;
5410 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5412 switch (i
.base_reg
->reg_num
)
5415 if (i
.index_reg
== 0)
5417 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5418 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5422 if (i
.index_reg
== 0)
5425 if (operand_type_check (i
.types
[op
], disp
) == 0)
5427 /* fake (%bp) into 0(%bp) */
5428 i
.types
[op
].bitfield
.disp8
= 1;
5429 fake_zero_displacement
= 1;
5432 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5433 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5435 default: /* (%si) -> 4 or (%di) -> 5 */
5436 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5438 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5440 else /* i.base_reg and 32/64 bit mode */
5442 if (flag_code
== CODE_64BIT
5443 && operand_type_check (i
.types
[op
], disp
))
5445 i386_operand_type temp
;
5446 operand_type_set (&temp
, 0);
5447 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5449 if (i
.prefix
[ADDR_PREFIX
] == 0)
5450 i
.types
[op
].bitfield
.disp32s
= 1;
5452 i
.types
[op
].bitfield
.disp32
= 1;
5455 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5456 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5458 i
.sib
.base
= i
.base_reg
->reg_num
;
5459 /* x86-64 ignores REX prefix bit here to avoid decoder
5461 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5464 if (i
.disp_operands
== 0)
5466 fake_zero_displacement
= 1;
5467 i
.types
[op
].bitfield
.disp8
= 1;
5470 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5474 i
.sib
.scale
= i
.log2_scale_factor
;
5475 if (i
.index_reg
== 0)
5477 /* <disp>(%esp) becomes two byte modrm with no index
5478 register. We've already stored the code for esp
5479 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5480 Any base register besides %esp will not use the
5481 extra modrm byte. */
5482 i
.sib
.index
= NO_INDEX_REGISTER
;
5486 if (i
.index_reg
->reg_num
== RegEiz
5487 || i
.index_reg
->reg_num
== RegRiz
)
5488 i
.sib
.index
= NO_INDEX_REGISTER
;
5490 i
.sib
.index
= i
.index_reg
->reg_num
;
5491 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5492 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5497 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5498 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5501 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5504 if (fake_zero_displacement
)
5506 /* Fakes a zero displacement assuming that i.types[op]
5507 holds the correct displacement size. */
5510 assert (i
.op
[op
].disps
== 0);
5511 exp
= &disp_expressions
[i
.disp_operands
++];
5512 i
.op
[op
].disps
= exp
;
5513 exp
->X_op
= O_constant
;
5514 exp
->X_add_number
= 0;
5515 exp
->X_add_symbol
= (symbolS
*) 0;
5516 exp
->X_op_symbol
= (symbolS
*) 0;
5524 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5525 (if any) based on i.tm.extension_opcode. Again, we must be
5526 careful to make sure that segment/control/debug/test/MMX
5527 registers are coded into the i.rm.reg field. */
5532 /* This has been precalculated for SSE5 instructions
5533 that have a DREX field earlier in process_drex. */
5534 if (i
.tm
.opcode_modifier
.drex
5535 || i
.tm
.opcode_modifier
.drexv
5536 || i
.tm
.opcode_modifier
.drexc
)
5538 op
= i
.drex
.modrm_reg
;
5539 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5540 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5545 unsigned int vex_reg
= ~0;
5547 for (op
= 0; op
< i
.operands
; op
++)
5548 if (i
.types
[op
].bitfield
.reg8
5549 || i
.types
[op
].bitfield
.reg16
5550 || i
.types
[op
].bitfield
.reg32
5551 || i
.types
[op
].bitfield
.reg64
5552 || i
.types
[op
].bitfield
.regmmx
5553 || i
.types
[op
].bitfield
.regxmm
5554 || i
.types
[op
].bitfield
.regymm
5555 || i
.types
[op
].bitfield
.sreg2
5556 || i
.types
[op
].bitfield
.sreg3
5557 || i
.types
[op
].bitfield
.control
5558 || i
.types
[op
].bitfield
.debug
5559 || i
.types
[op
].bitfield
.test
)
5564 else if (i
.tm
.opcode_modifier
.vexnds
)
5566 /* For instructions with VexNDS, the register-only
5567 source operand is encoded in VEX prefix. */
5568 assert (mem
!= (unsigned int) ~0);
5573 assert (op
< i
.operands
);
5578 assert (vex_reg
< i
.operands
);
5581 else if (i
.tm
.opcode_modifier
.vexndd
)
5583 /* For instructions with VexNDD, there should be
5584 no memory operand and the register destination
5585 is encoded in VEX prefix. */
5586 assert (i
.mem_operands
== 0
5587 && (op
+ 2) == i
.operands
);
5591 assert (op
< i
.operands
);
5593 if (vex_reg
!= (unsigned int) ~0)
5595 assert (i
.reg_operands
== 2);
5597 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5599 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5602 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5605 /* If there is an extension opcode to put here, the
5606 register number must be put into the regmem field. */
5607 if (i
.tm
.extension_opcode
!= None
)
5609 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5610 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5615 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5616 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5621 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5622 must set it to 3 to indicate this is a register operand
5623 in the regmem field. */
5624 if (!i
.mem_operands
)
5628 /* Fill in i.rm.reg field with extension opcode (if any). */
5629 if (i
.tm
.extension_opcode
!= None
5630 && !(i
.tm
.opcode_modifier
.drex
5631 || i
.tm
.opcode_modifier
.drexv
5632 || i
.tm
.opcode_modifier
.drexc
))
5633 i
.rm
.reg
= i
.tm
.extension_opcode
;
5639 output_branch (void)
5644 relax_substateT subtype
;
5649 if (flag_code
== CODE_16BIT
)
5653 if (i
.prefix
[DATA_PREFIX
] != 0)
5659 /* Pentium4 branch hints. */
5660 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5661 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5666 if (i
.prefix
[REX_PREFIX
] != 0)
5672 if (i
.prefixes
!= 0 && !intel_syntax
)
5673 as_warn (_("skipping prefixes on this instruction"));
5675 /* It's always a symbol; End frag & setup for relax.
5676 Make sure there is enough room in this frag for the largest
5677 instruction we may generate in md_convert_frag. This is 2
5678 bytes for the opcode and room for the prefix and largest
5680 frag_grow (prefix
+ 2 + 4);
5681 /* Prefix and 1 opcode byte go in fr_fix. */
5682 p
= frag_more (prefix
+ 1);
5683 if (i
.prefix
[DATA_PREFIX
] != 0)
5684 *p
++ = DATA_PREFIX_OPCODE
;
5685 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5686 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5687 *p
++ = i
.prefix
[SEG_PREFIX
];
5688 if (i
.prefix
[REX_PREFIX
] != 0)
5689 *p
++ = i
.prefix
[REX_PREFIX
];
5690 *p
= i
.tm
.base_opcode
;
5692 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5693 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5694 else if (cpu_arch_flags
.bitfield
.cpui386
)
5695 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5697 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5700 sym
= i
.op
[0].disps
->X_add_symbol
;
5701 off
= i
.op
[0].disps
->X_add_number
;
5703 if (i
.op
[0].disps
->X_op
!= O_constant
5704 && i
.op
[0].disps
->X_op
!= O_symbol
)
5706 /* Handle complex expressions. */
5707 sym
= make_expr_symbol (i
.op
[0].disps
);
5711 /* 1 possible extra opcode + 4 byte displacement go in var part.
5712 Pass reloc in fr_var. */
5713 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5723 if (i
.tm
.opcode_modifier
.jumpbyte
)
5725 /* This is a loop or jecxz type instruction. */
5727 if (i
.prefix
[ADDR_PREFIX
] != 0)
5729 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5732 /* Pentium4 branch hints. */
5733 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5734 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5736 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5745 if (flag_code
== CODE_16BIT
)
5748 if (i
.prefix
[DATA_PREFIX
] != 0)
5750 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5760 if (i
.prefix
[REX_PREFIX
] != 0)
5762 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5766 if (i
.prefixes
!= 0 && !intel_syntax
)
5767 as_warn (_("skipping prefixes on this instruction"));
5769 p
= frag_more (1 + size
);
5770 *p
++ = i
.tm
.base_opcode
;
5772 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5773 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5775 /* All jumps handled here are signed, but don't use a signed limit
5776 check for 32 and 16 bit jumps as we want to allow wrap around at
5777 4G and 64k respectively. */
5779 fixP
->fx_signed
= 1;
5783 output_interseg_jump (void)
5791 if (flag_code
== CODE_16BIT
)
5795 if (i
.prefix
[DATA_PREFIX
] != 0)
5801 if (i
.prefix
[REX_PREFIX
] != 0)
5811 if (i
.prefixes
!= 0 && !intel_syntax
)
5812 as_warn (_("skipping prefixes on this instruction"));
5814 /* 1 opcode; 2 segment; offset */
5815 p
= frag_more (prefix
+ 1 + 2 + size
);
5817 if (i
.prefix
[DATA_PREFIX
] != 0)
5818 *p
++ = DATA_PREFIX_OPCODE
;
5820 if (i
.prefix
[REX_PREFIX
] != 0)
5821 *p
++ = i
.prefix
[REX_PREFIX
];
5823 *p
++ = i
.tm
.base_opcode
;
5824 if (i
.op
[1].imms
->X_op
== O_constant
)
5826 offsetT n
= i
.op
[1].imms
->X_add_number
;
5829 && !fits_in_unsigned_word (n
)
5830 && !fits_in_signed_word (n
))
5832 as_bad (_("16-bit jump out of range"));
5835 md_number_to_chars (p
, n
, size
);
5838 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5839 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5840 if (i
.op
[0].imms
->X_op
!= O_constant
)
5841 as_bad (_("can't handle non absolute segment in `%s'"),
5843 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5849 fragS
*insn_start_frag
;
5850 offsetT insn_start_off
;
5852 /* Tie dwarf2 debug info to the address at the start of the insn.
5853 We can't do this after the insn has been output as the current
5854 frag may have been closed off. eg. by frag_var. */
5855 dwarf2_emit_insn (0);
5857 insn_start_frag
= frag_now
;
5858 insn_start_off
= frag_now_fix ();
5861 if (i
.tm
.opcode_modifier
.jump
)
5863 else if (i
.tm
.opcode_modifier
.jumpbyte
5864 || i
.tm
.opcode_modifier
.jumpdword
)
5866 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5867 output_interseg_jump ();
5870 /* Output normal instructions here. */
5874 unsigned int prefix
;
5876 /* Since the VEX prefix contains the implicit prefix, we don't
5877 need the explicit prefix. */
5878 if (!i
.tm
.opcode_modifier
.vex
)
5880 switch (i
.tm
.opcode_length
)
5883 if (i
.tm
.base_opcode
& 0xff000000)
5885 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5890 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5892 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5893 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5896 if (prefix
!= REPE_PREFIX_OPCODE
5897 || (i
.prefix
[LOCKREP_PREFIX
]
5898 != REPE_PREFIX_OPCODE
))
5899 add_prefix (prefix
);
5902 add_prefix (prefix
);
5911 /* The prefix bytes. */
5912 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5914 FRAG_APPEND_1_CHAR (*q
);
5917 if (i
.tm
.opcode_modifier
.vex
)
5919 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5924 /* REX byte is encoded in VEX prefix. */
5928 FRAG_APPEND_1_CHAR (*q
);
5931 /* There should be no other prefixes for instructions
5936 /* Now the VEX prefix. */
5937 p
= frag_more (i
.vex
.length
);
5938 for (j
= 0; j
< i
.vex
.length
; j
++)
5939 p
[j
] = i
.vex
.bytes
[j
];
5942 /* Now the opcode; be careful about word order here! */
5943 if (i
.tm
.opcode_length
== 1)
5945 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5949 switch (i
.tm
.opcode_length
)
5953 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5963 /* Put out high byte first: can't use md_number_to_chars! */
5964 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5965 *p
= i
.tm
.base_opcode
& 0xff;
5967 /* On SSE5, encode the OC1 bit in the DREX field if this
5968 encoding has multiple formats. */
5969 if (i
.tm
.opcode_modifier
.drex
5970 && i
.tm
.opcode_modifier
.drexv
5971 && DREX_OC1 (i
.tm
.extension_opcode
))
5972 *p
|= DREX_OC1_MASK
;
5975 /* Now the modrm byte and sib byte (if present). */
5976 if (i
.tm
.opcode_modifier
.modrm
)
5978 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5981 /* If i.rm.regmem == ESP (4)
5982 && i.rm.mode != (Register mode)
5984 ==> need second modrm byte. */
5985 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5987 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5988 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5990 | i
.sib
.scale
<< 6));
5993 /* Write the DREX byte if needed. */
5994 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
5997 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
5999 /* Encode the OC0 bit if this encoding has multiple
6001 if ((i
.tm
.opcode_modifier
.drex
6002 || i
.tm
.opcode_modifier
.drexv
)
6003 && DREX_OC0 (i
.tm
.extension_opcode
))
6004 *p
|= DREX_OC0_MASK
;
6007 if (i
.disp_operands
)
6008 output_disp (insn_start_frag
, insn_start_off
);
6011 output_imm (insn_start_frag
, insn_start_off
);
6017 pi ("" /*line*/, &i
);
6019 #endif /* DEBUG386 */
6022 /* Return the size of the displacement operand N. */
6025 disp_size (unsigned int n
)
6028 if (i
.types
[n
].bitfield
.disp64
)
6030 else if (i
.types
[n
].bitfield
.disp8
)
6032 else if (i
.types
[n
].bitfield
.disp16
)
6037 /* Return the size of the immediate operand N. */
6040 imm_size (unsigned int n
)
6043 if (i
.types
[n
].bitfield
.imm64
)
6045 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6047 else if (i
.types
[n
].bitfield
.imm16
)
6053 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6058 for (n
= 0; n
< i
.operands
; n
++)
6060 if (operand_type_check (i
.types
[n
], disp
))
6062 if (i
.op
[n
].disps
->X_op
== O_constant
)
6064 int size
= disp_size (n
);
6067 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6069 p
= frag_more (size
);
6070 md_number_to_chars (p
, val
, size
);
6074 enum bfd_reloc_code_real reloc_type
;
6075 int size
= disp_size (n
);
6076 int sign
= i
.types
[n
].bitfield
.disp32s
;
6077 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6079 /* We can't have 8 bit displacement here. */
6080 assert (!i
.types
[n
].bitfield
.disp8
);
6082 /* The PC relative address is computed relative
6083 to the instruction boundary, so in case immediate
6084 fields follows, we need to adjust the value. */
6085 if (pcrel
&& i
.imm_operands
)
6090 for (n1
= 0; n1
< i
.operands
; n1
++)
6091 if (operand_type_check (i
.types
[n1
], imm
))
6093 /* Only one immediate is allowed for PC
6094 relative address. */
6097 i
.op
[n
].disps
->X_add_number
-= sz
;
6099 /* We should find the immediate. */
6103 p
= frag_more (size
);
6104 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6106 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6107 && (((reloc_type
== BFD_RELOC_32
6108 || reloc_type
== BFD_RELOC_X86_64_32S
6109 || (reloc_type
== BFD_RELOC_64
6111 && (i
.op
[n
].disps
->X_op
== O_symbol
6112 || (i
.op
[n
].disps
->X_op
== O_add
6113 && ((symbol_get_value_expression
6114 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6116 || reloc_type
== BFD_RELOC_32_PCREL
))
6120 if (insn_start_frag
== frag_now
)
6121 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6126 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6127 for (fr
= insn_start_frag
->fr_next
;
6128 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6130 add
+= p
- frag_now
->fr_literal
;
6135 reloc_type
= BFD_RELOC_386_GOTPC
;
6136 i
.op
[n
].imms
->X_add_number
+= add
;
6138 else if (reloc_type
== BFD_RELOC_64
)
6139 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6141 /* Don't do the adjustment for x86-64, as there
6142 the pcrel addressing is relative to the _next_
6143 insn, and that is taken care of in other code. */
6144 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6146 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6147 i
.op
[n
].disps
, pcrel
, reloc_type
);
6154 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6159 for (n
= 0; n
< i
.operands
; n
++)
6161 if (operand_type_check (i
.types
[n
], imm
))
6163 if (i
.op
[n
].imms
->X_op
== O_constant
)
6165 int size
= imm_size (n
);
6168 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6170 p
= frag_more (size
);
6171 md_number_to_chars (p
, val
, size
);
6175 /* Not absolute_section.
6176 Need a 32-bit fixup (don't support 8bit
6177 non-absolute imms). Try to support other
6179 enum bfd_reloc_code_real reloc_type
;
6180 int size
= imm_size (n
);
6183 if (i
.types
[n
].bitfield
.imm32s
6184 && (i
.suffix
== QWORD_MNEM_SUFFIX
6185 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6190 p
= frag_more (size
);
6191 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6193 /* This is tough to explain. We end up with this one if we
6194 * have operands that look like
6195 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6196 * obtain the absolute address of the GOT, and it is strongly
6197 * preferable from a performance point of view to avoid using
6198 * a runtime relocation for this. The actual sequence of
6199 * instructions often look something like:
6204 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6206 * The call and pop essentially return the absolute address
6207 * of the label .L66 and store it in %ebx. The linker itself
6208 * will ultimately change the first operand of the addl so
6209 * that %ebx points to the GOT, but to keep things simple, the
6210 * .o file must have this operand set so that it generates not
6211 * the absolute address of .L66, but the absolute address of
6212 * itself. This allows the linker itself simply treat a GOTPC
6213 * relocation as asking for a pcrel offset to the GOT to be
6214 * added in, and the addend of the relocation is stored in the
6215 * operand field for the instruction itself.
6217 * Our job here is to fix the operand so that it would add
6218 * the correct offset so that %ebx would point to itself. The
6219 * thing that is tricky is that .-.L66 will point to the
6220 * beginning of the instruction, so we need to further modify
6221 * the operand so that it will point to itself. There are
6222 * other cases where you have something like:
6224 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6226 * and here no correction would be required. Internally in
6227 * the assembler we treat operands of this form as not being
6228 * pcrel since the '.' is explicitly mentioned, and I wonder
6229 * whether it would simplify matters to do it this way. Who
6230 * knows. In earlier versions of the PIC patches, the
6231 * pcrel_adjust field was used to store the correction, but
6232 * since the expression is not pcrel, I felt it would be
6233 * confusing to do it this way. */
6235 if ((reloc_type
== BFD_RELOC_32
6236 || reloc_type
== BFD_RELOC_X86_64_32S
6237 || reloc_type
== BFD_RELOC_64
)
6239 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6240 && (i
.op
[n
].imms
->X_op
== O_symbol
6241 || (i
.op
[n
].imms
->X_op
== O_add
6242 && ((symbol_get_value_expression
6243 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6248 if (insn_start_frag
== frag_now
)
6249 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6254 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6255 for (fr
= insn_start_frag
->fr_next
;
6256 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6258 add
+= p
- frag_now
->fr_literal
;
6262 reloc_type
= BFD_RELOC_386_GOTPC
;
6264 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6266 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6267 i
.op
[n
].imms
->X_add_number
+= add
;
6269 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6270 i
.op
[n
].imms
, 0, reloc_type
);
6276 /* x86_cons_fix_new is called via the expression parsing code when a
6277 reloc is needed. We use this hook to get the correct .got reloc. */
6278 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6279 static int cons_sign
= -1;
6282 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6285 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6287 got_reloc
= NO_RELOC
;
6290 if (exp
->X_op
== O_secrel
)
6292 exp
->X_op
= O_symbol
;
6293 r
= BFD_RELOC_32_SECREL
;
6297 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6300 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6301 # define lex_got(reloc, adjust, types) NULL
6303 /* Parse operands of the form
6304 <symbol>@GOTOFF+<nnn>
6305 and similar .plt or .got references.
6307 If we find one, set up the correct relocation in RELOC and copy the
6308 input string, minus the `@GOTOFF' into a malloc'd buffer for
6309 parsing by the calling routine. Return this buffer, and if ADJUST
6310 is non-null set it to the length of the string we removed from the
6311 input line. Otherwise return NULL. */
6313 lex_got (enum bfd_reloc_code_real
*reloc
,
6315 i386_operand_type
*types
)
6317 /* Some of the relocations depend on the size of what field is to
6318 be relocated. But in our callers i386_immediate and i386_displacement
6319 we don't yet know the operand size (this will be set by insn
6320 matching). Hence we record the word32 relocation here,
6321 and adjust the reloc according to the real size in reloc(). */
6322 static const struct {
6324 const enum bfd_reloc_code_real rel
[2];
6325 const i386_operand_type types64
;
6328 BFD_RELOC_X86_64_PLTOFF64
},
6329 OPERAND_TYPE_IMM64
},
6330 { "PLT", { BFD_RELOC_386_PLT32
,
6331 BFD_RELOC_X86_64_PLT32
},
6332 OPERAND_TYPE_IMM32_32S_DISP32
},
6334 BFD_RELOC_X86_64_GOTPLT64
},
6335 OPERAND_TYPE_IMM64_DISP64
},
6336 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6337 BFD_RELOC_X86_64_GOTOFF64
},
6338 OPERAND_TYPE_IMM64_DISP64
},
6340 BFD_RELOC_X86_64_GOTPCREL
},
6341 OPERAND_TYPE_IMM32_32S_DISP32
},
6342 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6343 BFD_RELOC_X86_64_TLSGD
},
6344 OPERAND_TYPE_IMM32_32S_DISP32
},
6345 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6347 OPERAND_TYPE_NONE
},
6349 BFD_RELOC_X86_64_TLSLD
},
6350 OPERAND_TYPE_IMM32_32S_DISP32
},
6351 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6352 BFD_RELOC_X86_64_GOTTPOFF
},
6353 OPERAND_TYPE_IMM32_32S_DISP32
},
6354 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6355 BFD_RELOC_X86_64_TPOFF32
},
6356 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6357 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6359 OPERAND_TYPE_NONE
},
6360 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6361 BFD_RELOC_X86_64_DTPOFF32
},
6363 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6364 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6366 OPERAND_TYPE_NONE
},
6367 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6369 OPERAND_TYPE_NONE
},
6370 { "GOT", { BFD_RELOC_386_GOT32
,
6371 BFD_RELOC_X86_64_GOT32
},
6372 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6373 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6374 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6375 OPERAND_TYPE_IMM32_32S_DISP32
},
6376 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6377 BFD_RELOC_X86_64_TLSDESC_CALL
},
6378 OPERAND_TYPE_IMM32_32S_DISP32
},
6386 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6387 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6390 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6394 len
= strlen (gotrel
[j
].str
);
6395 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6397 if (gotrel
[j
].rel
[object_64bit
] != 0)
6400 char *tmpbuf
, *past_reloc
;
6402 *reloc
= gotrel
[j
].rel
[object_64bit
];
6408 if (flag_code
!= CODE_64BIT
)
6410 types
->bitfield
.imm32
= 1;
6411 types
->bitfield
.disp32
= 1;
6414 *types
= gotrel
[j
].types64
;
6417 if (GOT_symbol
== NULL
)
6418 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6420 /* The length of the first part of our input line. */
6421 first
= cp
- input_line_pointer
;
6423 /* The second part goes from after the reloc token until
6424 (and including) an end_of_line char or comma. */
6425 past_reloc
= cp
+ 1 + len
;
6427 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6429 second
= cp
+ 1 - past_reloc
;
6431 /* Allocate and copy string. The trailing NUL shouldn't
6432 be necessary, but be safe. */
6433 tmpbuf
= xmalloc (first
+ second
+ 2);
6434 memcpy (tmpbuf
, input_line_pointer
, first
);
6435 if (second
!= 0 && *past_reloc
!= ' ')
6436 /* Replace the relocation token with ' ', so that
6437 errors like foo@GOTOFF1 will be detected. */
6438 tmpbuf
[first
++] = ' ';
6439 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6440 tmpbuf
[first
+ second
] = '\0';
6444 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6445 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6450 /* Might be a symbol version string. Don't as_bad here. */
6455 x86_cons (expressionS
*exp
, int size
)
6457 if (size
== 4 || (object_64bit
&& size
== 8))
6459 /* Handle @GOTOFF and the like in an expression. */
6461 char *gotfree_input_line
;
6464 save
= input_line_pointer
;
6465 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6466 if (gotfree_input_line
)
6467 input_line_pointer
= gotfree_input_line
;
6471 if (gotfree_input_line
)
6473 /* expression () has merrily parsed up to the end of line,
6474 or a comma - in the wrong buffer. Transfer how far
6475 input_line_pointer has moved to the right buffer. */
6476 input_line_pointer
= (save
6477 + (input_line_pointer
- gotfree_input_line
)
6479 free (gotfree_input_line
);
6480 if (exp
->X_op
== O_constant
6481 || exp
->X_op
== O_absent
6482 || exp
->X_op
== O_illegal
6483 || exp
->X_op
== O_register
6484 || exp
->X_op
== O_big
)
6486 char c
= *input_line_pointer
;
6487 *input_line_pointer
= 0;
6488 as_bad (_("missing or invalid expression `%s'"), save
);
6489 *input_line_pointer
= c
;
6498 static void signed_cons (int size
)
6500 if (flag_code
== CODE_64BIT
)
6508 pe_directive_secrel (dummy
)
6509 int dummy ATTRIBUTE_UNUSED
;
6516 if (exp
.X_op
== O_symbol
)
6517 exp
.X_op
= O_secrel
;
6519 emit_expr (&exp
, 4);
6521 while (*input_line_pointer
++ == ',');
6523 input_line_pointer
--;
6524 demand_empty_rest_of_line ();
6529 i386_immediate (char *imm_start
)
6531 char *save_input_line_pointer
;
6532 char *gotfree_input_line
;
6535 i386_operand_type types
;
6537 operand_type_set (&types
, ~0);
6539 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6541 as_bad (_("at most %d immediate operands are allowed"),
6542 MAX_IMMEDIATE_OPERANDS
);
6546 exp
= &im_expressions
[i
.imm_operands
++];
6547 i
.op
[this_operand
].imms
= exp
;
6549 if (is_space_char (*imm_start
))
6552 save_input_line_pointer
= input_line_pointer
;
6553 input_line_pointer
= imm_start
;
6555 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6556 if (gotfree_input_line
)
6557 input_line_pointer
= gotfree_input_line
;
6559 exp_seg
= expression (exp
);
6562 if (*input_line_pointer
)
6563 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6565 input_line_pointer
= save_input_line_pointer
;
6566 if (gotfree_input_line
)
6567 free (gotfree_input_line
);
6569 if (exp
->X_op
== O_absent
6570 || exp
->X_op
== O_illegal
6571 || exp
->X_op
== O_big
6572 || (gotfree_input_line
6573 && (exp
->X_op
== O_constant
6574 || exp
->X_op
== O_register
)))
6576 as_bad (_("missing or invalid immediate expression `%s'"),
6580 else if (exp
->X_op
== O_constant
)
6582 /* Size it properly later. */
6583 i
.types
[this_operand
].bitfield
.imm64
= 1;
6584 /* If BFD64, sign extend val. */
6585 if (!use_rela_relocations
6586 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6588 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6590 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6591 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6592 && exp_seg
!= absolute_section
6593 && exp_seg
!= text_section
6594 && exp_seg
!= data_section
6595 && exp_seg
!= bss_section
6596 && exp_seg
!= undefined_section
6597 && !bfd_is_com_section (exp_seg
))
6599 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6603 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6605 as_bad (_("illegal immediate register operand %s"), imm_start
);
6610 /* This is an address. The size of the address will be
6611 determined later, depending on destination register,
6612 suffix, or the default for the section. */
6613 i
.types
[this_operand
].bitfield
.imm8
= 1;
6614 i
.types
[this_operand
].bitfield
.imm16
= 1;
6615 i
.types
[this_operand
].bitfield
.imm32
= 1;
6616 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6617 i
.types
[this_operand
].bitfield
.imm64
= 1;
6618 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6626 i386_scale (char *scale
)
6629 char *save
= input_line_pointer
;
6631 input_line_pointer
= scale
;
6632 val
= get_absolute_expression ();
6637 i
.log2_scale_factor
= 0;
6640 i
.log2_scale_factor
= 1;
6643 i
.log2_scale_factor
= 2;
6646 i
.log2_scale_factor
= 3;
6650 char sep
= *input_line_pointer
;
6652 *input_line_pointer
= '\0';
6653 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6655 *input_line_pointer
= sep
;
6656 input_line_pointer
= save
;
6660 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6662 as_warn (_("scale factor of %d without an index register"),
6663 1 << i
.log2_scale_factor
);
6664 i
.log2_scale_factor
= 0;
6666 scale
= input_line_pointer
;
6667 input_line_pointer
= save
;
6672 i386_displacement (char *disp_start
, char *disp_end
)
6676 char *save_input_line_pointer
;
6677 char *gotfree_input_line
;
6679 i386_operand_type bigdisp
, types
= anydisp
;
6682 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6684 as_bad (_("at most %d displacement operands are allowed"),
6685 MAX_MEMORY_OPERANDS
);
6689 operand_type_set (&bigdisp
, 0);
6690 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6691 || (!current_templates
->start
->opcode_modifier
.jump
6692 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6694 bigdisp
.bitfield
.disp32
= 1;
6695 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6696 if (flag_code
== CODE_64BIT
)
6700 bigdisp
.bitfield
.disp32s
= 1;
6701 bigdisp
.bitfield
.disp64
= 1;
6704 else if ((flag_code
== CODE_16BIT
) ^ override
)
6706 bigdisp
.bitfield
.disp32
= 0;
6707 bigdisp
.bitfield
.disp16
= 1;
6712 /* For PC-relative branches, the width of the displacement
6713 is dependent upon data size, not address size. */
6714 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6715 if (flag_code
== CODE_64BIT
)
6717 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6718 bigdisp
.bitfield
.disp16
= 1;
6721 bigdisp
.bitfield
.disp32
= 1;
6722 bigdisp
.bitfield
.disp32s
= 1;
6728 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6730 : LONG_MNEM_SUFFIX
));
6731 bigdisp
.bitfield
.disp32
= 1;
6732 if ((flag_code
== CODE_16BIT
) ^ override
)
6734 bigdisp
.bitfield
.disp32
= 0;
6735 bigdisp
.bitfield
.disp16
= 1;
6739 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6742 exp
= &disp_expressions
[i
.disp_operands
];
6743 i
.op
[this_operand
].disps
= exp
;
6745 save_input_line_pointer
= input_line_pointer
;
6746 input_line_pointer
= disp_start
;
6747 END_STRING_AND_SAVE (disp_end
);
6749 #ifndef GCC_ASM_O_HACK
6750 #define GCC_ASM_O_HACK 0
6753 END_STRING_AND_SAVE (disp_end
+ 1);
6754 if (i
.types
[this_operand
].bitfield
.baseIndex
6755 && displacement_string_end
[-1] == '+')
6757 /* This hack is to avoid a warning when using the "o"
6758 constraint within gcc asm statements.
6761 #define _set_tssldt_desc(n,addr,limit,type) \
6762 __asm__ __volatile__ ( \
6764 "movw %w1,2+%0\n\t" \
6766 "movb %b1,4+%0\n\t" \
6767 "movb %4,5+%0\n\t" \
6768 "movb $0,6+%0\n\t" \
6769 "movb %h1,7+%0\n\t" \
6771 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6773 This works great except that the output assembler ends
6774 up looking a bit weird if it turns out that there is
6775 no offset. You end up producing code that looks like:
6788 So here we provide the missing zero. */
6790 *displacement_string_end
= '0';
6793 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6794 if (gotfree_input_line
)
6795 input_line_pointer
= gotfree_input_line
;
6797 exp_seg
= expression (exp
);
6800 if (*input_line_pointer
)
6801 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6803 RESTORE_END_STRING (disp_end
+ 1);
6805 input_line_pointer
= save_input_line_pointer
;
6806 if (gotfree_input_line
)
6807 free (gotfree_input_line
);
6810 /* We do this to make sure that the section symbol is in
6811 the symbol table. We will ultimately change the relocation
6812 to be relative to the beginning of the section. */
6813 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6814 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6815 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6817 if (exp
->X_op
!= O_symbol
)
6820 if (S_IS_LOCAL (exp
->X_add_symbol
)
6821 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6822 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6823 exp
->X_op
= O_subtract
;
6824 exp
->X_op_symbol
= GOT_symbol
;
6825 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6826 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6827 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6828 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6830 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6833 else if (exp
->X_op
== O_absent
6834 || exp
->X_op
== O_illegal
6835 || exp
->X_op
== O_big
6836 || (gotfree_input_line
6837 && (exp
->X_op
== O_constant
6838 || exp
->X_op
== O_register
)))
6841 as_bad (_("missing or invalid displacement expression `%s'"),
6846 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6847 else if (exp
->X_op
!= O_constant
6848 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6849 && exp_seg
!= absolute_section
6850 && exp_seg
!= text_section
6851 && exp_seg
!= data_section
6852 && exp_seg
!= bss_section
6853 && exp_seg
!= undefined_section
6854 && !bfd_is_com_section (exp_seg
))
6856 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6861 RESTORE_END_STRING (disp_end
);
6863 /* Check if this is a displacement only operand. */
6864 bigdisp
= i
.types
[this_operand
];
6865 bigdisp
.bitfield
.disp8
= 0;
6866 bigdisp
.bitfield
.disp16
= 0;
6867 bigdisp
.bitfield
.disp32
= 0;
6868 bigdisp
.bitfield
.disp32s
= 0;
6869 bigdisp
.bitfield
.disp64
= 0;
6870 if (operand_type_all_zero (&bigdisp
))
6871 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6877 /* Make sure the memory operand we've been dealt is valid.
6878 Return 1 on success, 0 on a failure. */
6881 i386_index_check (const char *operand_string
)
6884 const char *kind
= "base/index";
6885 #if INFER_ADDR_PREFIX
6891 if (current_templates
->start
->opcode_modifier
.isstring
6892 && !current_templates
->start
->opcode_modifier
.immext
6893 && (current_templates
->end
[-1].opcode_modifier
.isstring
6896 /* Memory operands of string insns are special in that they only allow
6897 a single register (rDI, rSI, or rBX) as their memory address. */
6898 unsigned int expected
;
6900 kind
= "string address";
6902 if (current_templates
->start
->opcode_modifier
.w
)
6904 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6906 if (!type
.bitfield
.baseindex
6907 || ((!i
.mem_operands
!= !intel_syntax
)
6908 && current_templates
->end
[-1].operand_types
[1]
6909 .bitfield
.baseindex
))
6910 type
= current_templates
->end
[-1].operand_types
[1];
6911 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6914 expected
= 3 /* rBX */;
6916 if (!i
.base_reg
|| i
.index_reg
6917 || operand_type_check (i
.types
[this_operand
], disp
))
6919 else if (!(flag_code
== CODE_64BIT
6920 ? i
.prefix
[ADDR_PREFIX
]
6921 ? i
.base_reg
->reg_type
.bitfield
.reg32
6922 : i
.base_reg
->reg_type
.bitfield
.reg64
6923 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6924 ? i
.base_reg
->reg_type
.bitfield
.reg32
6925 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6927 else if (i
.base_reg
->reg_num
!= expected
)
6934 for (j
= 0; j
< i386_regtab_size
; ++j
)
6935 if ((flag_code
== CODE_64BIT
6936 ? i
.prefix
[ADDR_PREFIX
]
6937 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6938 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6939 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6940 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6941 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6942 && i386_regtab
[j
].reg_num
== expected
)
6944 assert (j
< i386_regtab_size
);
6945 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6947 intel_syntax
? '[' : '(',
6949 i386_regtab
[j
].reg_name
,
6950 intel_syntax
? ']' : ')');
6954 else if (flag_code
== CODE_64BIT
)
6957 && ((i
.prefix
[ADDR_PREFIX
] == 0
6958 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6959 || (i
.prefix
[ADDR_PREFIX
]
6960 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6962 || i
.base_reg
->reg_num
!=
6963 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6965 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6966 || (i
.prefix
[ADDR_PREFIX
] == 0
6967 && i
.index_reg
->reg_num
!= RegRiz
6968 && !i
.index_reg
->reg_type
.bitfield
.reg64
6970 || (i
.prefix
[ADDR_PREFIX
]
6971 && i
.index_reg
->reg_num
!= RegEiz
6972 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6977 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6981 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6982 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6984 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6985 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6987 && i
.base_reg
->reg_num
< 6
6988 && i
.index_reg
->reg_num
>= 6
6989 && i
.log2_scale_factor
== 0))))
6996 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6998 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6999 && i
.index_reg
->reg_num
!= RegEiz
)
7000 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7006 #if INFER_ADDR_PREFIX
7007 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7009 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7011 /* Change the size of any displacement too. At most one of
7012 Disp16 or Disp32 is set.
7013 FIXME. There doesn't seem to be any real need for separate
7014 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7015 Removing them would probably clean up the code quite a lot. */
7016 if (flag_code
!= CODE_64BIT
7017 && (i
.types
[this_operand
].bitfield
.disp16
7018 || i
.types
[this_operand
].bitfield
.disp32
))
7019 i
.types
[this_operand
]
7020 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7025 as_bad (_("`%s' is not a valid %s expression"),
7030 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7032 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7033 ? flag_code
== CODE_32BIT
7042 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7046 i386_att_operand (char *operand_string
)
7050 char *op_string
= operand_string
;
7052 if (is_space_char (*op_string
))
7055 /* We check for an absolute prefix (differentiating,
7056 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7057 if (*op_string
== ABSOLUTE_PREFIX
)
7060 if (is_space_char (*op_string
))
7062 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7065 /* Check if operand is a register. */
7066 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7068 i386_operand_type temp
;
7070 /* Check for a segment override by searching for ':' after a
7071 segment register. */
7073 if (is_space_char (*op_string
))
7075 if (*op_string
== ':'
7076 && (r
->reg_type
.bitfield
.sreg2
7077 || r
->reg_type
.bitfield
.sreg3
))
7082 i
.seg
[i
.mem_operands
] = &es
;
7085 i
.seg
[i
.mem_operands
] = &cs
;
7088 i
.seg
[i
.mem_operands
] = &ss
;
7091 i
.seg
[i
.mem_operands
] = &ds
;
7094 i
.seg
[i
.mem_operands
] = &fs
;
7097 i
.seg
[i
.mem_operands
] = &gs
;
7101 /* Skip the ':' and whitespace. */
7103 if (is_space_char (*op_string
))
7106 if (!is_digit_char (*op_string
)
7107 && !is_identifier_char (*op_string
)
7108 && *op_string
!= '('
7109 && *op_string
!= ABSOLUTE_PREFIX
)
7111 as_bad (_("bad memory operand `%s'"), op_string
);
7114 /* Handle case of %es:*foo. */
7115 if (*op_string
== ABSOLUTE_PREFIX
)
7118 if (is_space_char (*op_string
))
7120 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7122 goto do_memory_reference
;
7126 as_bad (_("junk `%s' after register"), op_string
);
7130 temp
.bitfield
.baseindex
= 0;
7131 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7133 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7134 i
.op
[this_operand
].regs
= r
;
7137 else if (*op_string
== REGISTER_PREFIX
)
7139 as_bad (_("bad register name `%s'"), op_string
);
7142 else if (*op_string
== IMMEDIATE_PREFIX
)
7145 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7147 as_bad (_("immediate operand illegal with absolute jump"));
7150 if (!i386_immediate (op_string
))
7153 else if (is_digit_char (*op_string
)
7154 || is_identifier_char (*op_string
)
7155 || *op_string
== '(')
7157 /* This is a memory reference of some sort. */
7160 /* Start and end of displacement string expression (if found). */
7161 char *displacement_string_start
;
7162 char *displacement_string_end
;
7164 do_memory_reference
:
7165 if ((i
.mem_operands
== 1
7166 && !current_templates
->start
->opcode_modifier
.isstring
)
7167 || i
.mem_operands
== 2)
7169 as_bad (_("too many memory references for `%s'"),
7170 current_templates
->start
->name
);
7174 /* Check for base index form. We detect the base index form by
7175 looking for an ')' at the end of the operand, searching
7176 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7178 base_string
= op_string
+ strlen (op_string
);
7181 if (is_space_char (*base_string
))
7184 /* If we only have a displacement, set-up for it to be parsed later. */
7185 displacement_string_start
= op_string
;
7186 displacement_string_end
= base_string
+ 1;
7188 if (*base_string
== ')')
7191 unsigned int parens_balanced
= 1;
7192 /* We've already checked that the number of left & right ()'s are
7193 equal, so this loop will not be infinite. */
7197 if (*base_string
== ')')
7199 if (*base_string
== '(')
7202 while (parens_balanced
);
7204 temp_string
= base_string
;
7206 /* Skip past '(' and whitespace. */
7208 if (is_space_char (*base_string
))
7211 if (*base_string
== ','
7212 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7215 displacement_string_end
= temp_string
;
7217 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7221 base_string
= end_op
;
7222 if (is_space_char (*base_string
))
7226 /* There may be an index reg or scale factor here. */
7227 if (*base_string
== ',')
7230 if (is_space_char (*base_string
))
7233 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7236 base_string
= end_op
;
7237 if (is_space_char (*base_string
))
7239 if (*base_string
== ',')
7242 if (is_space_char (*base_string
))
7245 else if (*base_string
!= ')')
7247 as_bad (_("expecting `,' or `)' "
7248 "after index register in `%s'"),
7253 else if (*base_string
== REGISTER_PREFIX
)
7255 as_bad (_("bad register name `%s'"), base_string
);
7259 /* Check for scale factor. */
7260 if (*base_string
!= ')')
7262 char *end_scale
= i386_scale (base_string
);
7267 base_string
= end_scale
;
7268 if (is_space_char (*base_string
))
7270 if (*base_string
!= ')')
7272 as_bad (_("expecting `)' "
7273 "after scale factor in `%s'"),
7278 else if (!i
.index_reg
)
7280 as_bad (_("expecting index register or scale factor "
7281 "after `,'; got '%c'"),
7286 else if (*base_string
!= ')')
7288 as_bad (_("expecting `,' or `)' "
7289 "after base register in `%s'"),
7294 else if (*base_string
== REGISTER_PREFIX
)
7296 as_bad (_("bad register name `%s'"), base_string
);
7301 /* If there's an expression beginning the operand, parse it,
7302 assuming displacement_string_start and
7303 displacement_string_end are meaningful. */
7304 if (displacement_string_start
!= displacement_string_end
)
7306 if (!i386_displacement (displacement_string_start
,
7307 displacement_string_end
))
7311 /* Special case for (%dx) while doing input/output op. */
7313 && operand_type_equal (&i
.base_reg
->reg_type
,
7314 ®16_inoutportreg
)
7316 && i
.log2_scale_factor
== 0
7317 && i
.seg
[i
.mem_operands
] == 0
7318 && !operand_type_check (i
.types
[this_operand
], disp
))
7320 i
.types
[this_operand
] = inoutportreg
;
7324 if (i386_index_check (operand_string
) == 0)
7326 i
.types
[this_operand
].bitfield
.mem
= 1;
7331 /* It's not a memory operand; argh! */
7332 as_bad (_("invalid char %s beginning operand %d `%s'"),
7333 output_invalid (*op_string
),
7338 return 1; /* Normal return. */
7341 /* md_estimate_size_before_relax()
7343 Called just before relax() for rs_machine_dependent frags. The x86
7344 assembler uses these frags to handle variable size jump
7347 Any symbol that is now undefined will not become defined.
7348 Return the correct fr_subtype in the frag.
7349 Return the initial "guess for variable size of frag" to caller.
7350 The guess is actually the growth beyond the fixed part. Whatever
7351 we do to grow the fixed or variable part contributes to our
7355 md_estimate_size_before_relax (fragP
, segment
)
7359 /* We've already got fragP->fr_subtype right; all we have to do is
7360 check for un-relaxable symbols. On an ELF system, we can't relax
7361 an externally visible symbol, because it may be overridden by a
7363 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7364 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7366 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7367 || S_IS_WEAK (fragP
->fr_symbol
)))
7371 /* Symbol is undefined in this segment, or we need to keep a
7372 reloc so that weak symbols can be overridden. */
7373 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7374 enum bfd_reloc_code_real reloc_type
;
7375 unsigned char *opcode
;
7378 if (fragP
->fr_var
!= NO_RELOC
)
7379 reloc_type
= fragP
->fr_var
;
7381 reloc_type
= BFD_RELOC_16_PCREL
;
7383 reloc_type
= BFD_RELOC_32_PCREL
;
7385 old_fr_fix
= fragP
->fr_fix
;
7386 opcode
= (unsigned char *) fragP
->fr_opcode
;
7388 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7391 /* Make jmp (0xeb) a (d)word displacement jump. */
7393 fragP
->fr_fix
+= size
;
7394 fix_new (fragP
, old_fr_fix
, size
,
7396 fragP
->fr_offset
, 1,
7402 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7404 /* Negate the condition, and branch past an
7405 unconditional jump. */
7408 /* Insert an unconditional jump. */
7410 /* We added two extra opcode bytes, and have a two byte
7412 fragP
->fr_fix
+= 2 + 2;
7413 fix_new (fragP
, old_fr_fix
+ 2, 2,
7415 fragP
->fr_offset
, 1,
7422 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7427 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7429 fragP
->fr_offset
, 1,
7431 fixP
->fx_signed
= 1;
7435 /* This changes the byte-displacement jump 0x7N
7436 to the (d)word-displacement jump 0x0f,0x8N. */
7437 opcode
[1] = opcode
[0] + 0x10;
7438 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7439 /* We've added an opcode byte. */
7440 fragP
->fr_fix
+= 1 + size
;
7441 fix_new (fragP
, old_fr_fix
+ 1, size
,
7443 fragP
->fr_offset
, 1,
7448 BAD_CASE (fragP
->fr_subtype
);
7452 return fragP
->fr_fix
- old_fr_fix
;
7455 /* Guess size depending on current relax state. Initially the relax
7456 state will correspond to a short jump and we return 1, because
7457 the variable part of the frag (the branch offset) is one byte
7458 long. However, we can relax a section more than once and in that
7459 case we must either set fr_subtype back to the unrelaxed state,
7460 or return the value for the appropriate branch. */
7461 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7464 /* Called after relax() is finished.
7466 In: Address of frag.
7467 fr_type == rs_machine_dependent.
7468 fr_subtype is what the address relaxed to.
7470 Out: Any fixSs and constants are set up.
7471 Caller will turn frag into a ".space 0". */
7474 md_convert_frag (abfd
, sec
, fragP
)
7475 bfd
*abfd ATTRIBUTE_UNUSED
;
7476 segT sec ATTRIBUTE_UNUSED
;
7479 unsigned char *opcode
;
7480 unsigned char *where_to_put_displacement
= NULL
;
7481 offsetT target_address
;
7482 offsetT opcode_address
;
7483 unsigned int extension
= 0;
7484 offsetT displacement_from_opcode_start
;
7486 opcode
= (unsigned char *) fragP
->fr_opcode
;
7488 /* Address we want to reach in file space. */
7489 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7491 /* Address opcode resides at in file space. */
7492 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7494 /* Displacement from opcode start to fill into instruction. */
7495 displacement_from_opcode_start
= target_address
- opcode_address
;
7497 if ((fragP
->fr_subtype
& BIG
) == 0)
7499 /* Don't have to change opcode. */
7500 extension
= 1; /* 1 opcode + 1 displacement */
7501 where_to_put_displacement
= &opcode
[1];
7505 if (no_cond_jump_promotion
7506 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7507 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7508 _("long jump required"));
7510 switch (fragP
->fr_subtype
)
7512 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7513 extension
= 4; /* 1 opcode + 4 displacement */
7515 where_to_put_displacement
= &opcode
[1];
7518 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7519 extension
= 2; /* 1 opcode + 2 displacement */
7521 where_to_put_displacement
= &opcode
[1];
7524 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7525 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7526 extension
= 5; /* 2 opcode + 4 displacement */
7527 opcode
[1] = opcode
[0] + 0x10;
7528 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7529 where_to_put_displacement
= &opcode
[2];
7532 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7533 extension
= 3; /* 2 opcode + 2 displacement */
7534 opcode
[1] = opcode
[0] + 0x10;
7535 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7536 where_to_put_displacement
= &opcode
[2];
7539 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7544 where_to_put_displacement
= &opcode
[3];
7548 BAD_CASE (fragP
->fr_subtype
);
7553 /* If size if less then four we are sure that the operand fits,
7554 but if it's 4, then it could be that the displacement is larger
7556 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7558 && ((addressT
) (displacement_from_opcode_start
- extension
7559 + ((addressT
) 1 << 31))
7560 > (((addressT
) 2 << 31) - 1)))
7562 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7563 _("jump target out of range"));
7564 /* Make us emit 0. */
7565 displacement_from_opcode_start
= extension
;
7567 /* Now put displacement after opcode. */
7568 md_number_to_chars ((char *) where_to_put_displacement
,
7569 (valueT
) (displacement_from_opcode_start
- extension
),
7570 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7571 fragP
->fr_fix
+= extension
;
7574 /* Apply a fixup (fixS) to segment data, once it has been determined
7575 by our caller that we have all the info we need to fix it up.
7577 On the 386, immediates, displacements, and data pointers are all in
7578 the same (little-endian) format, so we don't need to care about which
7582 md_apply_fix (fixP
, valP
, seg
)
7583 /* The fix we're to put in. */
7585 /* Pointer to the value of the bits. */
7587 /* Segment fix is from. */
7588 segT seg ATTRIBUTE_UNUSED
;
7590 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7591 valueT value
= *valP
;
7593 #if !defined (TE_Mach)
7596 switch (fixP
->fx_r_type
)
7602 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7605 case BFD_RELOC_X86_64_32S
:
7606 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7609 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7612 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7617 if (fixP
->fx_addsy
!= NULL
7618 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7619 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7620 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7621 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7622 && !use_rela_relocations
)
7624 /* This is a hack. There should be a better way to handle this.
7625 This covers for the fact that bfd_install_relocation will
7626 subtract the current location (for partial_inplace, PC relative
7627 relocations); see more below. */
7631 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7634 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7636 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7639 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7642 || (symbol_section_p (fixP
->fx_addsy
)
7643 && sym_seg
!= absolute_section
))
7644 && !generic_force_reloc (fixP
))
7646 /* Yes, we add the values in twice. This is because
7647 bfd_install_relocation subtracts them out again. I think
7648 bfd_install_relocation is broken, but I don't dare change
7650 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7654 #if defined (OBJ_COFF) && defined (TE_PE)
7655 /* For some reason, the PE format does not store a
7656 section address offset for a PC relative symbol. */
7657 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7658 || S_IS_WEAK (fixP
->fx_addsy
))
7659 value
+= md_pcrel_from (fixP
);
7663 /* Fix a few things - the dynamic linker expects certain values here,
7664 and we must not disappoint it. */
7665 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7666 if (IS_ELF
&& fixP
->fx_addsy
)
7667 switch (fixP
->fx_r_type
)
7669 case BFD_RELOC_386_PLT32
:
7670 case BFD_RELOC_X86_64_PLT32
:
7671 /* Make the jump instruction point to the address of the operand. At
7672 runtime we merely add the offset to the actual PLT entry. */
7676 case BFD_RELOC_386_TLS_GD
:
7677 case BFD_RELOC_386_TLS_LDM
:
7678 case BFD_RELOC_386_TLS_IE_32
:
7679 case BFD_RELOC_386_TLS_IE
:
7680 case BFD_RELOC_386_TLS_GOTIE
:
7681 case BFD_RELOC_386_TLS_GOTDESC
:
7682 case BFD_RELOC_X86_64_TLSGD
:
7683 case BFD_RELOC_X86_64_TLSLD
:
7684 case BFD_RELOC_X86_64_GOTTPOFF
:
7685 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7686 value
= 0; /* Fully resolved at runtime. No addend. */
7688 case BFD_RELOC_386_TLS_LE
:
7689 case BFD_RELOC_386_TLS_LDO_32
:
7690 case BFD_RELOC_386_TLS_LE_32
:
7691 case BFD_RELOC_X86_64_DTPOFF32
:
7692 case BFD_RELOC_X86_64_DTPOFF64
:
7693 case BFD_RELOC_X86_64_TPOFF32
:
7694 case BFD_RELOC_X86_64_TPOFF64
:
7695 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7698 case BFD_RELOC_386_TLS_DESC_CALL
:
7699 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7700 value
= 0; /* Fully resolved at runtime. No addend. */
7701 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7705 case BFD_RELOC_386_GOT32
:
7706 case BFD_RELOC_X86_64_GOT32
:
7707 value
= 0; /* Fully resolved at runtime. No addend. */
7710 case BFD_RELOC_VTABLE_INHERIT
:
7711 case BFD_RELOC_VTABLE_ENTRY
:
7718 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7720 #endif /* !defined (TE_Mach) */
7722 /* Are we finished with this relocation now? */
7723 if (fixP
->fx_addsy
== NULL
)
7725 else if (use_rela_relocations
)
7727 fixP
->fx_no_overflow
= 1;
7728 /* Remember value for tc_gen_reloc. */
7729 fixP
->fx_addnumber
= value
;
7733 md_number_to_chars (p
, value
, fixP
->fx_size
);
7737 md_atof (int type
, char *litP
, int *sizeP
)
7739 /* This outputs the LITTLENUMs in REVERSE order;
7740 in accord with the bigendian 386. */
7741 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7744 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7747 output_invalid (int c
)
7750 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7753 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7754 "(0x%x)", (unsigned char) c
);
7755 return output_invalid_buf
;
7758 /* REG_STRING starts *before* REGISTER_PREFIX. */
7760 static const reg_entry
*
7761 parse_real_register (char *reg_string
, char **end_op
)
7763 char *s
= reg_string
;
7765 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7768 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7769 if (*s
== REGISTER_PREFIX
)
7772 if (is_space_char (*s
))
7776 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7778 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7779 return (const reg_entry
*) NULL
;
7783 /* For naked regs, make sure that we are not dealing with an identifier.
7784 This prevents confusing an identifier like `eax_var' with register
7786 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7787 return (const reg_entry
*) NULL
;
7791 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7793 /* Handle floating point regs, allowing spaces in the (i) part. */
7794 if (r
== i386_regtab
/* %st is first entry of table */)
7796 if (is_space_char (*s
))
7801 if (is_space_char (*s
))
7803 if (*s
>= '0' && *s
<= '7')
7807 if (is_space_char (*s
))
7812 r
= hash_find (reg_hash
, "st(0)");
7817 /* We have "%st(" then garbage. */
7818 return (const reg_entry
*) NULL
;
7822 if (r
== NULL
|| allow_pseudo_reg
)
7825 if (operand_type_all_zero (&r
->reg_type
))
7826 return (const reg_entry
*) NULL
;
7828 if ((r
->reg_type
.bitfield
.reg32
7829 || r
->reg_type
.bitfield
.sreg3
7830 || r
->reg_type
.bitfield
.control
7831 || r
->reg_type
.bitfield
.debug
7832 || r
->reg_type
.bitfield
.test
)
7833 && !cpu_arch_flags
.bitfield
.cpui386
)
7834 return (const reg_entry
*) NULL
;
7836 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7837 return (const reg_entry
*) NULL
;
7839 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7840 return (const reg_entry
*) NULL
;
7842 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7843 return (const reg_entry
*) NULL
;
7845 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7846 if (!allow_index_reg
7847 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7848 return (const reg_entry
*) NULL
;
7850 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7851 || r
->reg_type
.bitfield
.reg64
)
7852 && (!cpu_arch_flags
.bitfield
.cpulm
7853 || !operand_type_equal (&r
->reg_type
, &control
))
7854 && flag_code
!= CODE_64BIT
)
7855 return (const reg_entry
*) NULL
;
7857 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7858 return (const reg_entry
*) NULL
;
7863 /* REG_STRING starts *before* REGISTER_PREFIX. */
7865 static const reg_entry
*
7866 parse_register (char *reg_string
, char **end_op
)
7870 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7871 r
= parse_real_register (reg_string
, end_op
);
7876 char *save
= input_line_pointer
;
7880 input_line_pointer
= reg_string
;
7881 c
= get_symbol_end ();
7882 symbolP
= symbol_find (reg_string
);
7883 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7885 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7887 know (e
->X_op
== O_register
);
7888 know (e
->X_add_number
>= 0
7889 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7890 r
= i386_regtab
+ e
->X_add_number
;
7891 *end_op
= input_line_pointer
;
7893 *input_line_pointer
= c
;
7894 input_line_pointer
= save
;
7900 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7903 char *end
= input_line_pointer
;
7906 r
= parse_register (name
, &input_line_pointer
);
7907 if (r
&& end
<= input_line_pointer
)
7909 *nextcharP
= *input_line_pointer
;
7910 *input_line_pointer
= 0;
7911 e
->X_op
= O_register
;
7912 e
->X_add_number
= r
- i386_regtab
;
7915 input_line_pointer
= end
;
7921 md_operand (expressionS
*e
)
7923 if (*input_line_pointer
== REGISTER_PREFIX
)
7926 const reg_entry
*r
= parse_real_register (input_line_pointer
, &end
);
7930 e
->X_op
= O_register
;
7931 e
->X_add_number
= r
- i386_regtab
;
7932 input_line_pointer
= end
;
7938 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7939 const char *md_shortopts
= "kVQ:sqn";
7941 const char *md_shortopts
= "qn";
7944 #define OPTION_32 (OPTION_MD_BASE + 0)
7945 #define OPTION_64 (OPTION_MD_BASE + 1)
7946 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7947 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7948 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7949 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7950 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7951 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7952 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7953 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7954 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7955 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7957 struct option md_longopts
[] =
7959 {"32", no_argument
, NULL
, OPTION_32
},
7960 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
7961 {"64", no_argument
, NULL
, OPTION_64
},
7963 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7964 {"march", required_argument
, NULL
, OPTION_MARCH
},
7965 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7966 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7967 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7968 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7969 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7970 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7971 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7972 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7973 {NULL
, no_argument
, NULL
, 0}
7975 size_t md_longopts_size
= sizeof (md_longopts
);
7978 md_parse_option (int c
, char *arg
)
7986 optimize_align_code
= 0;
7993 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7994 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7995 should be emitted or not. FIXME: Not implemented. */
7999 /* -V: SVR4 argument to print version ID. */
8001 print_version_id ();
8004 /* -k: Ignore for FreeBSD compatibility. */
8009 /* -s: On i386 Solaris, this tells the native assembler to use
8010 .stab instead of .stab.excl. We always use .stab anyhow. */
8013 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8016 const char **list
, **l
;
8018 list
= bfd_target_list ();
8019 for (l
= list
; *l
!= NULL
; l
++)
8020 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8021 || strcmp (*l
, "coff-x86-64") == 0
8022 || strcmp (*l
, "pe-x86-64") == 0
8023 || strcmp (*l
, "pei-x86-64") == 0)
8025 default_arch
= "x86_64";
8029 as_fatal (_("No compiled in support for x86_64"));
8036 default_arch
= "i386";
8040 #ifdef SVR4_COMMENT_CHARS
8045 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8047 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8051 i386_comment_chars
= n
;
8057 arch
= xstrdup (arg
);
8061 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8062 next
= strchr (arch
, '+');
8065 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8067 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8070 cpu_arch_name
= cpu_arch
[i
].name
;
8071 cpu_sub_arch_name
= NULL
;
8072 cpu_arch_flags
= cpu_arch
[i
].flags
;
8073 cpu_arch_isa
= cpu_arch
[i
].type
;
8074 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8075 if (!cpu_arch_tune_set
)
8077 cpu_arch_tune
= cpu_arch_isa
;
8078 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8082 else if (*cpu_arch
[i
].name
== '.'
8083 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8085 /* ISA entension. */
8086 i386_cpu_flags flags
;
8087 flags
= cpu_flags_or (cpu_arch_flags
,
8089 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8091 if (cpu_sub_arch_name
)
8093 char *name
= cpu_sub_arch_name
;
8094 cpu_sub_arch_name
= concat (name
,
8096 (const char *) NULL
);
8100 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8101 cpu_arch_flags
= flags
;
8107 if (i
>= ARRAY_SIZE (cpu_arch
))
8108 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8112 while (next
!= NULL
);
8117 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8118 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8120 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8122 cpu_arch_tune_set
= 1;
8123 cpu_arch_tune
= cpu_arch
[i
].type
;
8124 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8128 if (i
>= ARRAY_SIZE (cpu_arch
))
8129 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8132 case OPTION_MMNEMONIC
:
8133 if (strcasecmp (arg
, "att") == 0)
8135 else if (strcasecmp (arg
, "intel") == 0)
8138 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8141 case OPTION_MSYNTAX
:
8142 if (strcasecmp (arg
, "att") == 0)
8144 else if (strcasecmp (arg
, "intel") == 0)
8147 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8150 case OPTION_MINDEX_REG
:
8151 allow_index_reg
= 1;
8154 case OPTION_MNAKED_REG
:
8155 allow_naked_reg
= 1;
8158 case OPTION_MOLD_GCC
:
8162 case OPTION_MSSE2AVX
:
8166 case OPTION_MSSE_CHECK
:
8167 if (strcasecmp (arg
, "error") == 0)
8168 sse_check
= sse_check_error
;
8169 else if (strcasecmp (arg
, "warning") == 0)
8170 sse_check
= sse_check_warning
;
8171 else if (strcasecmp (arg
, "none") == 0)
8172 sse_check
= sse_check_none
;
8174 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8184 md_show_usage (stream
)
8187 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8188 fprintf (stream
, _("\
8190 -V print assembler version number\n\
8193 fprintf (stream
, _("\
8194 -n Do not optimize code alignment\n\
8195 -q quieten some warnings\n"));
8196 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8197 fprintf (stream
, _("\
8200 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8201 fprintf (stream
, _("\
8202 --32/--64 generate 32bit/64bit code\n"));
8204 #ifdef SVR4_COMMENT_CHARS
8205 fprintf (stream
, _("\
8206 --divide do not treat `/' as a comment character\n"));
8208 fprintf (stream
, _("\
8209 --divide ignored\n"));
8211 fprintf (stream
, _("\
8212 -march=CPU[,+EXTENSION...]\n\
8213 generate code for CPU and EXTENSION, CPU is one of:\n\
8214 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8215 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8216 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8217 generic32, generic64\n\
8218 EXTENSION is combination of:\n\
8219 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8220 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8221 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8222 sse5, svme, abm, padlock\n"));
8223 fprintf (stream
, _("\
8224 -mtune=CPU optimize for CPU, CPU is one of:\n\
8225 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8226 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8227 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8228 generic32, generic64\n"));
8229 fprintf (stream
, _("\
8230 -msse2avx encode SSE instructions with VEX prefix\n"));
8231 fprintf (stream
, _("\
8232 -msse-check=[none|error|warning]\n\
8233 check SSE instructions\n"));
8234 fprintf (stream
, _("\
8235 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8236 fprintf (stream
, _("\
8237 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8238 fprintf (stream
, _("\
8239 -mindex-reg support pseudo index registers\n"));
8240 fprintf (stream
, _("\
8241 -mnaked-reg don't require `%%' prefix for registers\n"));
8242 fprintf (stream
, _("\
8243 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8246 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8247 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8249 /* Pick the target format to use. */
8252 i386_target_format (void)
8254 if (!strcmp (default_arch
, "x86_64"))
8256 set_code_flag (CODE_64BIT
);
8257 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8259 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8260 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8261 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8262 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8263 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8264 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8265 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8266 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8267 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8268 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8270 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8272 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8273 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8274 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8275 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8276 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8277 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8278 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8279 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8280 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8281 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8284 else if (!strcmp (default_arch
, "i386"))
8286 set_code_flag (CODE_32BIT
);
8287 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8289 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8290 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8291 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8293 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8295 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8296 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8297 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8301 as_fatal (_("Unknown architecture"));
8302 switch (OUTPUT_FLAVOR
)
8305 case bfd_target_coff_flavour
:
8306 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8309 #ifdef OBJ_MAYBE_AOUT
8310 case bfd_target_aout_flavour
:
8311 return AOUT_TARGET_FORMAT
;
8313 #ifdef OBJ_MAYBE_COFF
8314 case bfd_target_coff_flavour
:
8317 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8318 case bfd_target_elf_flavour
:
8320 if (flag_code
== CODE_64BIT
)
8323 use_rela_relocations
= 1;
8325 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8334 #endif /* OBJ_MAYBE_ more than one */
8336 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8338 i386_elf_emit_arch_note (void)
8340 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8343 asection
*seg
= now_seg
;
8344 subsegT subseg
= now_subseg
;
8345 Elf_Internal_Note i_note
;
8346 Elf_External_Note e_note
;
8347 asection
*note_secp
;
8350 /* Create the .note section. */
8351 note_secp
= subseg_new (".note", 0);
8352 bfd_set_section_flags (stdoutput
,
8354 SEC_HAS_CONTENTS
| SEC_READONLY
);
8356 /* Process the arch string. */
8357 len
= strlen (cpu_arch_name
);
8359 i_note
.namesz
= len
+ 1;
8361 i_note
.type
= NT_ARCH
;
8362 p
= frag_more (sizeof (e_note
.namesz
));
8363 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8364 p
= frag_more (sizeof (e_note
.descsz
));
8365 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8366 p
= frag_more (sizeof (e_note
.type
));
8367 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8368 p
= frag_more (len
+ 1);
8369 strcpy (p
, cpu_arch_name
);
8371 frag_align (2, 0, 0);
8373 subseg_set (seg
, subseg
);
8379 md_undefined_symbol (name
)
8382 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8383 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8384 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8385 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8389 if (symbol_find (name
))
8390 as_bad (_("GOT already in symbol table"));
8391 GOT_symbol
= symbol_new (name
, undefined_section
,
8392 (valueT
) 0, &zero_address_frag
);
8399 /* Round up a section size to the appropriate boundary. */
8402 md_section_align (segment
, size
)
8403 segT segment ATTRIBUTE_UNUSED
;
8406 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8407 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8409 /* For a.out, force the section size to be aligned. If we don't do
8410 this, BFD will align it for us, but it will not write out the
8411 final bytes of the section. This may be a bug in BFD, but it is
8412 easier to fix it here since that is how the other a.out targets
8416 align
= bfd_get_section_alignment (stdoutput
, segment
);
8417 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8424 /* On the i386, PC-relative offsets are relative to the start of the
8425 next instruction. That is, the address of the offset, plus its
8426 size, since the offset is always the last part of the insn. */
8429 md_pcrel_from (fixS
*fixP
)
8431 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8437 s_bss (int ignore ATTRIBUTE_UNUSED
)
8441 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8443 obj_elf_section_change_hook ();
8445 temp
= get_absolute_expression ();
8446 subseg_set (bss_section
, (subsegT
) temp
);
8447 demand_empty_rest_of_line ();
8453 i386_validate_fix (fixS
*fixp
)
8455 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8457 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8461 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8466 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8468 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8475 tc_gen_reloc (section
, fixp
)
8476 asection
*section ATTRIBUTE_UNUSED
;
8480 bfd_reloc_code_real_type code
;
8482 switch (fixp
->fx_r_type
)
8484 case BFD_RELOC_X86_64_PLT32
:
8485 case BFD_RELOC_X86_64_GOT32
:
8486 case BFD_RELOC_X86_64_GOTPCREL
:
8487 case BFD_RELOC_386_PLT32
:
8488 case BFD_RELOC_386_GOT32
:
8489 case BFD_RELOC_386_GOTOFF
:
8490 case BFD_RELOC_386_GOTPC
:
8491 case BFD_RELOC_386_TLS_GD
:
8492 case BFD_RELOC_386_TLS_LDM
:
8493 case BFD_RELOC_386_TLS_LDO_32
:
8494 case BFD_RELOC_386_TLS_IE_32
:
8495 case BFD_RELOC_386_TLS_IE
:
8496 case BFD_RELOC_386_TLS_GOTIE
:
8497 case BFD_RELOC_386_TLS_LE_32
:
8498 case BFD_RELOC_386_TLS_LE
:
8499 case BFD_RELOC_386_TLS_GOTDESC
:
8500 case BFD_RELOC_386_TLS_DESC_CALL
:
8501 case BFD_RELOC_X86_64_TLSGD
:
8502 case BFD_RELOC_X86_64_TLSLD
:
8503 case BFD_RELOC_X86_64_DTPOFF32
:
8504 case BFD_RELOC_X86_64_DTPOFF64
:
8505 case BFD_RELOC_X86_64_GOTTPOFF
:
8506 case BFD_RELOC_X86_64_TPOFF32
:
8507 case BFD_RELOC_X86_64_TPOFF64
:
8508 case BFD_RELOC_X86_64_GOTOFF64
:
8509 case BFD_RELOC_X86_64_GOTPC32
:
8510 case BFD_RELOC_X86_64_GOT64
:
8511 case BFD_RELOC_X86_64_GOTPCREL64
:
8512 case BFD_RELOC_X86_64_GOTPC64
:
8513 case BFD_RELOC_X86_64_GOTPLT64
:
8514 case BFD_RELOC_X86_64_PLTOFF64
:
8515 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8516 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8518 case BFD_RELOC_VTABLE_ENTRY
:
8519 case BFD_RELOC_VTABLE_INHERIT
:
8521 case BFD_RELOC_32_SECREL
:
8523 code
= fixp
->fx_r_type
;
8525 case BFD_RELOC_X86_64_32S
:
8526 if (!fixp
->fx_pcrel
)
8528 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8529 code
= fixp
->fx_r_type
;
8535 switch (fixp
->fx_size
)
8538 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8539 _("can not do %d byte pc-relative relocation"),
8541 code
= BFD_RELOC_32_PCREL
;
8543 case 1: code
= BFD_RELOC_8_PCREL
; break;
8544 case 2: code
= BFD_RELOC_16_PCREL
; break;
8545 case 4: code
= BFD_RELOC_32_PCREL
; break;
8547 case 8: code
= BFD_RELOC_64_PCREL
; break;
8553 switch (fixp
->fx_size
)
8556 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8557 _("can not do %d byte relocation"),
8559 code
= BFD_RELOC_32
;
8561 case 1: code
= BFD_RELOC_8
; break;
8562 case 2: code
= BFD_RELOC_16
; break;
8563 case 4: code
= BFD_RELOC_32
; break;
8565 case 8: code
= BFD_RELOC_64
; break;
8572 if ((code
== BFD_RELOC_32
8573 || code
== BFD_RELOC_32_PCREL
8574 || code
== BFD_RELOC_X86_64_32S
)
8576 && fixp
->fx_addsy
== GOT_symbol
)
8579 code
= BFD_RELOC_386_GOTPC
;
8581 code
= BFD_RELOC_X86_64_GOTPC32
;
8583 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8585 && fixp
->fx_addsy
== GOT_symbol
)
8587 code
= BFD_RELOC_X86_64_GOTPC64
;
8590 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8591 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8592 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8594 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8596 if (!use_rela_relocations
)
8598 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8599 vtable entry to be used in the relocation's section offset. */
8600 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8601 rel
->address
= fixp
->fx_offset
;
8605 /* Use the rela in 64bit mode. */
8608 if (!fixp
->fx_pcrel
)
8609 rel
->addend
= fixp
->fx_offset
;
8613 case BFD_RELOC_X86_64_PLT32
:
8614 case BFD_RELOC_X86_64_GOT32
:
8615 case BFD_RELOC_X86_64_GOTPCREL
:
8616 case BFD_RELOC_X86_64_TLSGD
:
8617 case BFD_RELOC_X86_64_TLSLD
:
8618 case BFD_RELOC_X86_64_GOTTPOFF
:
8619 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8620 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8621 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8624 rel
->addend
= (section
->vma
8626 + fixp
->fx_addnumber
8627 + md_pcrel_from (fixp
));
8632 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8633 if (rel
->howto
== NULL
)
8635 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8636 _("cannot represent relocation type %s"),
8637 bfd_get_reloc_code_name (code
));
8638 /* Set howto to a garbage value so that we can keep going. */
8639 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8640 assert (rel
->howto
!= NULL
);
8647 /* Parse operands using Intel syntax. This implements a recursive descent
8648 parser based on the BNF grammar published in Appendix B of the MASM 6.1
8651 FIXME: We do not recognize the full operand grammar defined in the MASM
8652 documentation. In particular, all the structure/union and
8653 high-level macro operands are missing.
8655 Uppercase words are terminals, lower case words are non-terminals.
8656 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
8657 bars '|' denote choices. Most grammar productions are implemented in
8658 functions called 'intel_<production>'.
8660 Initial production is 'expr'.
8666 binOp & | AND | \| | OR | ^ | XOR
8668 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
8670 constant digits [[ radixOverride ]]
8672 dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD | YMMWORD
8710 => expr expr cmpOp e04
8713 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
8714 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
8716 hexdigit a | b | c | d | e | f
8717 | A | B | C | D | E | F
8723 mulOp * | / | % | MOD | << | SHL | >> | SHR
8727 register specialRegister
8731 segmentRegister CS | DS | ES | FS | GS | SS
8733 specialRegister CR0 | CR2 | CR3 | CR4
8734 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
8735 | TR3 | TR4 | TR5 | TR6 | TR7
8737 We simplify the grammar in obvious places (e.g., register parsing is
8738 done by calling parse_register) and eliminate immediate left recursion
8739 to implement a recursive-descent parser.
8743 expr' cmpOp e04 expr'
8795 /* Parsing structure for the intel syntax parser. Used to implement the
8796 semantic actions for the operand grammar. */
8797 struct intel_parser_s
8799 char *op_string
; /* The string being parsed. */
8800 int got_a_float
; /* Whether the operand is a float. */
8801 int op_modifier
; /* Operand modifier. */
8802 int is_mem
; /* 1 if operand is memory reference. */
8803 int in_offset
; /* >=1 if parsing operand of offset. */
8804 int in_bracket
; /* >=1 if parsing operand in brackets. */
8805 const reg_entry
*reg
; /* Last register reference found. */
8806 char *disp
; /* Displacement string being built. */
8807 char *next_operand
; /* Resume point when splitting operands. */
8810 static struct intel_parser_s intel_parser
;
8812 /* Token structure for parsing intel syntax. */
8815 int code
; /* Token code. */
8816 const reg_entry
*reg
; /* Register entry for register tokens. */
8817 char *str
; /* String representation. */
8820 static struct intel_token cur_token
, prev_token
;
8822 /* Token codes for the intel parser. Since T_SHORT is already used
8823 by COFF, undefine it first to prevent a warning. */
8841 #define T_YMMWORD 16
8843 /* Prototypes for intel parser functions. */
8844 static int intel_match_token (int);
8845 static void intel_putback_token (void);
8846 static void intel_get_token (void);
8847 static int intel_expr (void);
8848 static int intel_e04 (void);
8849 static int intel_e05 (void);
8850 static int intel_e06 (void);
8851 static int intel_e09 (void);
8852 static int intel_e10 (void);
8853 static int intel_e11 (void);
8856 i386_intel_operand (char *operand_string
, int got_a_float
)
8860 const reg_entry
*final_base
= i
.base_reg
;
8861 const reg_entry
*final_index
= i
.index_reg
;
8863 p
= intel_parser
.op_string
= xstrdup (operand_string
);
8864 intel_parser
.disp
= (char *) xmalloc (strlen (operand_string
) + 1);
8868 /* Initialize token holders. */
8869 cur_token
.code
= prev_token
.code
= T_NIL
;
8870 cur_token
.reg
= prev_token
.reg
= NULL
;
8871 cur_token
.str
= prev_token
.str
= NULL
;
8873 /* Initialize parser structure. */
8874 intel_parser
.got_a_float
= got_a_float
;
8875 intel_parser
.op_modifier
= 0;
8876 intel_parser
.is_mem
= 0;
8877 intel_parser
.in_offset
= 0;
8878 intel_parser
.in_bracket
= 0;
8879 intel_parser
.reg
= NULL
;
8880 intel_parser
.disp
[0] = '\0';
8881 intel_parser
.next_operand
= NULL
;
8886 /* Read the first token and start the parser. */
8888 ret
= intel_expr ();
8893 if (cur_token
.code
!= T_NIL
)
8895 as_bad (_("invalid operand for '%s' ('%s' unexpected)"),
8896 current_templates
->start
->name
, cur_token
.str
);
8899 /* If we found a memory reference, hand it over to i386_displacement
8900 to fill in the rest of the operand fields. */
8901 else if (intel_parser
.is_mem
)
8903 if ((i
.mem_operands
== 1
8904 && !current_templates
->start
->opcode_modifier
.isstring
)
8905 || i
.mem_operands
== 2)
8907 as_bad (_("too many memory references for '%s'"),
8908 current_templates
->start
->name
);
8913 char *s
= intel_parser
.disp
;
8915 if (!quiet_warnings
&& intel_parser
.is_mem
< 0)
8916 /* See the comments in intel_bracket_expr. */
8917 as_warn (_("Treating `%s' as memory reference"), operand_string
);
8919 /* Add the displacement expression. */
8921 ret
= i386_displacement (s
, s
+ strlen (s
));
8924 /* Swap base and index in 16-bit memory operands like
8925 [si+bx]. Since i386_index_check is also used in AT&T
8926 mode we have to do that here. */
8929 && i
.base_reg
->reg_type
.bitfield
.reg16
8930 && i
.index_reg
->reg_type
.bitfield
.reg16
8931 && i
.base_reg
->reg_num
>= 6
8932 && i
.index_reg
->reg_num
< 6)
8934 const reg_entry
*base
= i
.index_reg
;
8936 i
.index_reg
= i
.base_reg
;
8939 ret
= i386_index_check (operand_string
);
8943 i
.types
[this_operand
].bitfield
.mem
= 1;
8949 /* Constant and OFFSET expressions are handled by i386_immediate. */
8950 else if ((intel_parser
.op_modifier
& (1 << T_OFFSET
))
8951 || intel_parser
.reg
== NULL
)
8953 if (i
.mem_operands
< 2 && i
.seg
[i
.mem_operands
])
8955 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
8956 as_warn (_("Segment override ignored"));
8957 i
.seg
[i
.mem_operands
] = NULL
;
8959 ret
= i386_immediate (intel_parser
.disp
);
8962 if (!final_base
&& !final_index
)
8964 final_base
= i
.base_reg
;
8965 final_index
= i
.index_reg
;
8968 if (intel_parser
.next_operand
&& this_operand
>= MAX_OPERANDS
- 1)
8970 if (!ret
|| !intel_parser
.next_operand
)
8972 intel_parser
.op_string
= intel_parser
.next_operand
;
8973 this_operand
= i
.operands
++;
8974 i
.types
[this_operand
].bitfield
.unspecified
= 1;
8978 free (intel_parser
.disp
);
8980 if (final_base
|| final_index
)
8982 i
.base_reg
= final_base
;
8983 i
.index_reg
= final_index
;
8989 #define NUM_ADDRESS_REGS (!!i.base_reg + !!i.index_reg)
8993 expr' cmpOp e04 expr'
8998 /* XXX Implement the comparison operators. */
8999 return intel_e04 ();
9016 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9017 i
.base_reg
= i386_regtab
+ REGNAM_AL
; /* al is invalid as base */
9019 if (cur_token
.code
== '+')
9021 else if (cur_token
.code
== '-')
9022 nregs
= NUM_ADDRESS_REGS
;
9026 strcat (intel_parser
.disp
, cur_token
.str
);
9027 intel_match_token (cur_token
.code
);
9038 int nregs
= ~NUM_ADDRESS_REGS
;
9045 if (cur_token
.code
== '&'
9046 || cur_token
.code
== '|'
9047 || cur_token
.code
== '^')
9051 str
[0] = cur_token
.code
;
9053 strcat (intel_parser
.disp
, str
);
9058 intel_match_token (cur_token
.code
);
9063 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9064 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 1; /* cl is invalid as base */
9075 int nregs
= ~NUM_ADDRESS_REGS
;
9082 if (cur_token
.code
== '*'
9083 || cur_token
.code
== '/'
9084 || cur_token
.code
== '%')
9088 str
[0] = cur_token
.code
;
9090 strcat (intel_parser
.disp
, str
);
9092 else if (cur_token
.code
== T_SHL
)
9093 strcat (intel_parser
.disp
, "<<");
9094 else if (cur_token
.code
== T_SHR
)
9095 strcat (intel_parser
.disp
, ">>");
9099 intel_match_token (cur_token
.code
);
9104 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9105 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 2; /* dl is invalid as base */
9123 int nregs
= ~NUM_ADDRESS_REGS
;
9128 /* Don't consume constants here. */
9129 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9131 /* Need to look one token ahead - if the next token
9132 is a constant, the current token is its sign. */
9135 intel_match_token (cur_token
.code
);
9136 next_code
= cur_token
.code
;
9137 intel_putback_token ();
9138 if (next_code
== T_CONST
)
9142 /* e09 OFFSET e09 */
9143 if (cur_token
.code
== T_OFFSET
)
9146 ++intel_parser
.in_offset
;
9150 else if (cur_token
.code
== T_SHORT
)
9151 intel_parser
.op_modifier
|= 1 << T_SHORT
;
9154 else if (cur_token
.code
== '+')
9155 strcat (intel_parser
.disp
, "+");
9160 else if (cur_token
.code
== '-' || cur_token
.code
== '~')
9166 str
[0] = cur_token
.code
;
9168 strcat (intel_parser
.disp
, str
);
9175 intel_match_token (cur_token
.code
);
9183 /* e09' PTR e10 e09' */
9184 if (cur_token
.code
== T_PTR
)
9188 if (prev_token
.code
== T_BYTE
)
9190 suffix
= BYTE_MNEM_SUFFIX
;
9191 i
.types
[this_operand
].bitfield
.byte
= 1;
9194 else if (prev_token
.code
== T_WORD
)
9196 if ((current_templates
->start
->name
[0] == 'l'
9197 && current_templates
->start
->name
[2] == 's'
9198 && current_templates
->start
->name
[3] == 0)
9199 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9200 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9201 else if (intel_parser
.got_a_float
== 2) /* "fi..." */
9202 suffix
= SHORT_MNEM_SUFFIX
;
9204 suffix
= WORD_MNEM_SUFFIX
;
9205 i
.types
[this_operand
].bitfield
.word
= 1;
9208 else if (prev_token
.code
== T_DWORD
)
9210 if ((current_templates
->start
->name
[0] == 'l'
9211 && current_templates
->start
->name
[2] == 's'
9212 && current_templates
->start
->name
[3] == 0)
9213 || current_templates
->start
->base_opcode
== 0x62 /* bound */)
9214 suffix
= WORD_MNEM_SUFFIX
;
9215 else if (flag_code
== CODE_16BIT
9216 && (current_templates
->start
->opcode_modifier
.jump
9217 || current_templates
->start
->opcode_modifier
.jumpdword
))
9218 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9219 else if (intel_parser
.got_a_float
== 1) /* "f..." */
9220 suffix
= SHORT_MNEM_SUFFIX
;
9222 suffix
= LONG_MNEM_SUFFIX
;
9223 i
.types
[this_operand
].bitfield
.dword
= 1;
9226 else if (prev_token
.code
== T_FWORD
)
9228 if (current_templates
->start
->name
[0] == 'l'
9229 && current_templates
->start
->name
[2] == 's'
9230 && current_templates
->start
->name
[3] == 0)
9231 suffix
= LONG_MNEM_SUFFIX
;
9232 else if (!intel_parser
.got_a_float
)
9234 if (flag_code
== CODE_16BIT
)
9235 add_prefix (DATA_PREFIX_OPCODE
);
9236 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9239 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9240 i
.types
[this_operand
].bitfield
.fword
= 1;
9243 else if (prev_token
.code
== T_QWORD
)
9245 if (current_templates
->start
->base_opcode
== 0x62 /* bound */
9246 || intel_parser
.got_a_float
== 1) /* "f..." */
9247 suffix
= LONG_MNEM_SUFFIX
;
9249 suffix
= QWORD_MNEM_SUFFIX
;
9250 i
.types
[this_operand
].bitfield
.qword
= 1;
9253 else if (prev_token
.code
== T_TBYTE
)
9255 if (intel_parser
.got_a_float
== 1)
9256 suffix
= LONG_DOUBLE_MNEM_SUFFIX
;
9258 suffix
= BYTE_MNEM_SUFFIX
; /* so it will cause an error */
9261 else if (prev_token
.code
== T_XMMWORD
)
9263 suffix
= XMMWORD_MNEM_SUFFIX
;
9264 i
.types
[this_operand
].bitfield
.xmmword
= 1;
9267 else if (prev_token
.code
== T_YMMWORD
)
9269 suffix
= YMMWORD_MNEM_SUFFIX
;
9270 i
.types
[this_operand
].bitfield
.ymmword
= 1;
9275 as_bad (_("Unknown operand modifier `%s'"), prev_token
.str
);
9279 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9281 /* Operands for jump/call using 'ptr' notation denote absolute
9283 if (current_templates
->start
->opcode_modifier
.jump
9284 || current_templates
->start
->opcode_modifier
.jumpdword
)
9285 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9287 if (current_templates
->start
->base_opcode
== 0x8d /* lea */)
9291 else if (i
.suffix
!= suffix
)
9293 as_bad (_("Conflicting operand modifiers"));
9299 /* e09' : e10 e09' */
9300 else if (cur_token
.code
== ':')
9302 if (prev_token
.code
!= T_REG
)
9304 /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a
9305 segment/group identifier (which we don't have), using comma
9306 as the operand separator there is even less consistent, since
9307 there all branches only have a single operand. */
9308 if (this_operand
!= 0
9309 || intel_parser
.in_offset
9310 || intel_parser
.in_bracket
9311 || (!current_templates
->start
->opcode_modifier
.jump
9312 && !current_templates
->start
->opcode_modifier
.jumpdword
9313 && !current_templates
->start
->opcode_modifier
.jumpintersegment
9314 && !current_templates
->start
->operand_types
[0].bitfield
.jumpabsolute
))
9315 return intel_match_token (T_NIL
);
9316 /* Remember the start of the 2nd operand and terminate 1st
9318 XXX This isn't right, yet (when SSSS:OOOO is right operand of
9319 another expression), but it gets at least the simplest case
9320 (a plain number or symbol on the left side) right. */
9321 intel_parser
.next_operand
= intel_parser
.op_string
;
9322 *--intel_parser
.op_string
= '\0';
9323 return intel_match_token (':');
9331 intel_match_token (cur_token
.code
);
9337 --intel_parser
.in_offset
;
9340 if (NUM_ADDRESS_REGS
> nregs
)
9342 as_bad (_("Invalid operand to `OFFSET'"));
9345 intel_parser
.op_modifier
|= 1 << T_OFFSET
;
9348 if (nregs
>= 0 && NUM_ADDRESS_REGS
> nregs
)
9349 i
.base_reg
= i386_regtab
+ REGNAM_AL
+ 3; /* bl is invalid as base */
9354 intel_bracket_expr (void)
9356 int was_offset
= intel_parser
.op_modifier
& (1 << T_OFFSET
);
9357 const char *start
= intel_parser
.op_string
;
9360 if (i
.op
[this_operand
].regs
)
9361 return intel_match_token (T_NIL
);
9363 intel_match_token ('[');
9365 /* Mark as a memory operand only if it's not already known to be an
9366 offset expression. If it's an offset expression, we need to keep
9368 if (!intel_parser
.in_offset
)
9370 ++intel_parser
.in_bracket
;
9372 /* Operands for jump/call inside brackets denote absolute addresses. */
9373 if (current_templates
->start
->opcode_modifier
.jump
9374 || current_templates
->start
->opcode_modifier
.jumpdword
)
9375 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
9377 /* Unfortunately gas always diverged from MASM in a respect that can't
9378 be easily fixed without risking to break code sequences likely to be
9379 encountered (the testsuite even check for this): MASM doesn't consider
9380 an expression inside brackets unconditionally as a memory reference.
9381 When that is e.g. a constant, an offset expression, or the sum of the
9382 two, this is still taken as a constant load. gas, however, always
9383 treated these as memory references. As a compromise, we'll try to make
9384 offset expressions inside brackets work the MASM way (since that's
9385 less likely to be found in real world code), but make constants alone
9386 continue to work the traditional gas way. In either case, issue a
9388 intel_parser
.op_modifier
&= ~was_offset
;
9391 strcat (intel_parser
.disp
, "[");
9393 /* Add a '+' to the displacement string if necessary. */
9394 if (*intel_parser
.disp
!= '\0'
9395 && *(intel_parser
.disp
+ strlen (intel_parser
.disp
) - 1) != '+')
9396 strcat (intel_parser
.disp
, "+");
9399 && (len
= intel_parser
.op_string
- start
- 1,
9400 intel_match_token (']')))
9402 /* Preserve brackets when the operand is an offset expression. */
9403 if (intel_parser
.in_offset
)
9404 strcat (intel_parser
.disp
, "]");
9407 --intel_parser
.in_bracket
;
9408 if (i
.base_reg
|| i
.index_reg
)
9409 intel_parser
.is_mem
= 1;
9410 if (!intel_parser
.is_mem
)
9412 if (!(intel_parser
.op_modifier
& (1 << T_OFFSET
)))
9413 /* Defer the warning until all of the operand was parsed. */
9414 intel_parser
.is_mem
= -1;
9415 else if (!quiet_warnings
)
9416 as_warn (_("`[%.*s]' taken to mean just `%.*s'"),
9417 len
, start
, len
, start
);
9420 intel_parser
.op_modifier
|= was_offset
;
9437 while (cur_token
.code
== '[')
9439 if (!intel_bracket_expr ())
9465 switch (cur_token
.code
)
9469 intel_match_token ('(');
9470 strcat (intel_parser
.disp
, "(");
9472 if (intel_expr () && intel_match_token (')'))
9474 strcat (intel_parser
.disp
, ")");
9481 return intel_bracket_expr ();
9486 strcat (intel_parser
.disp
, cur_token
.str
);
9487 intel_match_token (cur_token
.code
);
9489 /* Mark as a memory operand only if it's not already known to be an
9490 offset expression. */
9491 if (!intel_parser
.in_offset
)
9492 intel_parser
.is_mem
= 1;
9499 const reg_entry
*reg
= intel_parser
.reg
= cur_token
.reg
;
9501 intel_match_token (T_REG
);
9503 /* Check for segment change. */
9504 if (cur_token
.code
== ':')
9506 if (!reg
->reg_type
.bitfield
.sreg2
9507 && !reg
->reg_type
.bitfield
.sreg3
)
9509 as_bad (_("`%s' is not a valid segment register"),
9513 else if (i
.mem_operands
>= 2)
9514 as_warn (_("Segment override ignored"));
9515 else if (i
.seg
[i
.mem_operands
])
9516 as_warn (_("Extra segment override ignored"));
9519 if (!intel_parser
.in_offset
)
9520 intel_parser
.is_mem
= 1;
9521 switch (reg
->reg_num
)
9524 i
.seg
[i
.mem_operands
] = &es
;
9527 i
.seg
[i
.mem_operands
] = &cs
;
9530 i
.seg
[i
.mem_operands
] = &ss
;
9533 i
.seg
[i
.mem_operands
] = &ds
;
9536 i
.seg
[i
.mem_operands
] = &fs
;
9539 i
.seg
[i
.mem_operands
] = &gs
;
9545 else if (reg
->reg_type
.bitfield
.sreg3
&& reg
->reg_num
== RegFlat
)
9547 as_bad (_("cannot use `FLAT' here"));
9551 /* Not a segment register. Check for register scaling. */
9552 else if (cur_token
.code
== '*')
9554 if (!intel_parser
.in_bracket
)
9556 as_bad (_("Register scaling only allowed in memory operands"));
9560 if (reg
->reg_type
.bitfield
.reg16
) /* Disallow things like [si*1]. */
9561 reg
= i386_regtab
+ REGNAM_AX
+ 4; /* sp is invalid as index */
9562 else if (i
.index_reg
)
9563 reg
= i386_regtab
+ REGNAM_EAX
+ 4; /* esp is invalid as index */
9565 /* What follows must be a valid scale. */
9566 intel_match_token ('*');
9568 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9570 /* Set the scale after setting the register (otherwise,
9571 i386_scale will complain) */
9572 if (cur_token
.code
== '+' || cur_token
.code
== '-')
9574 char *str
, sign
= cur_token
.code
;
9575 intel_match_token (cur_token
.code
);
9576 if (cur_token
.code
!= T_CONST
)
9578 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9582 str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9583 strcpy (str
+ 1, cur_token
.str
);
9585 if (!i386_scale (str
))
9589 else if (!i386_scale (cur_token
.str
))
9591 intel_match_token (cur_token
.code
);
9594 /* No scaling. If this is a memory operand, the register is either a
9595 base register (first occurrence) or an index register (second
9597 else if (intel_parser
.in_bracket
)
9602 else if (!i
.index_reg
)
9606 as_bad (_("Too many register references in memory operand"));
9610 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9613 /* It's neither base nor index. */
9614 else if (!intel_parser
.in_offset
&& !intel_parser
.is_mem
)
9616 i386_operand_type temp
= reg
->reg_type
;
9617 temp
.bitfield
.baseindex
= 0;
9618 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
9620 i
.types
[this_operand
].bitfield
.unspecified
= 0;
9621 i
.op
[this_operand
].regs
= reg
;
9626 as_bad (_("Invalid use of register"));
9630 /* Since registers are not part of the displacement string (except
9631 when we're parsing offset operands), we may need to remove any
9632 preceding '+' from the displacement string. */
9633 if (*intel_parser
.disp
!= '\0'
9634 && !intel_parser
.in_offset
)
9636 char *s
= intel_parser
.disp
;
9637 s
+= strlen (s
) - 1;
9662 intel_match_token (cur_token
.code
);
9664 if (cur_token
.code
== T_PTR
)
9667 /* It must have been an identifier. */
9668 intel_putback_token ();
9669 cur_token
.code
= T_ID
;
9675 if (!intel_parser
.in_offset
&& intel_parser
.is_mem
<= 0)
9679 /* The identifier represents a memory reference only if it's not
9680 preceded by an offset modifier and if it's not an equate. */
9681 symbolP
= symbol_find(cur_token
.str
);
9682 if (!symbolP
|| S_GET_SEGMENT(symbolP
) != absolute_section
)
9683 intel_parser
.is_mem
= 1;
9691 char *save_str
, sign
= 0;
9693 /* Allow constants that start with `+' or `-'. */
9694 if (cur_token
.code
== '-' || cur_token
.code
== '+')
9696 sign
= cur_token
.code
;
9697 intel_match_token (cur_token
.code
);
9698 if (cur_token
.code
!= T_CONST
)
9700 as_bad (_("Syntax error: Expecting a constant, got `%s'"),
9706 save_str
= (char *) xmalloc (strlen (cur_token
.str
) + 2);
9707 strcpy (save_str
+ !!sign
, cur_token
.str
);
9711 /* Get the next token to check for register scaling. */
9712 intel_match_token (cur_token
.code
);
9714 /* Check if this constant is a scaling factor for an
9716 if (cur_token
.code
== '*')
9718 if (intel_match_token ('*') && cur_token
.code
== T_REG
)
9720 const reg_entry
*reg
= cur_token
.reg
;
9722 if (!intel_parser
.in_bracket
)
9724 as_bad (_("Register scaling only allowed "
9725 "in memory operands"));
9729 /* Disallow things like [1*si].
9730 sp and esp are invalid as index. */
9731 if (reg
->reg_type
.bitfield
.reg16
)
9732 reg
= i386_regtab
+ REGNAM_AX
+ 4;
9733 else if (i
.index_reg
)
9734 reg
= i386_regtab
+ REGNAM_EAX
+ 4;
9736 /* The constant is followed by `* reg', so it must be
9739 i
.types
[this_operand
].bitfield
.baseindex
= 1;
9741 /* Set the scale after setting the register (otherwise,
9742 i386_scale will complain) */
9743 if (!i386_scale (save_str
))
9745 intel_match_token (T_REG
);
9747 /* Since registers are not part of the displacement
9748 string, we may need to remove any preceding '+' from
9749 the displacement string. */
9750 if (*intel_parser
.disp
!= '\0')
9752 char *s
= intel_parser
.disp
;
9753 s
+= strlen (s
) - 1;
9763 /* The constant was not used for register scaling. Since we have
9764 already consumed the token following `*' we now need to put it
9765 back in the stream. */
9766 intel_putback_token ();
9769 /* Add the constant to the displacement string. */
9770 strcat (intel_parser
.disp
, save_str
);
9777 as_bad (_("Unrecognized token '%s'"), cur_token
.str
);
9781 /* Match the given token against cur_token. If they match, read the next
9782 token from the operand string. */
9784 intel_match_token (int code
)
9786 if (cur_token
.code
== code
)
9793 as_bad (_("Unexpected token `%s'"), cur_token
.str
);
9798 /* Read a new token from intel_parser.op_string and store it in cur_token. */
9800 intel_get_token (void)
9803 const reg_entry
*reg
;
9804 struct intel_token new_token
;
9806 new_token
.code
= T_NIL
;
9807 new_token
.reg
= NULL
;
9808 new_token
.str
= NULL
;
9810 /* Free the memory allocated to the previous token and move
9811 cur_token to prev_token. */
9813 free (prev_token
.str
);
9815 prev_token
= cur_token
;
9817 /* Skip whitespace. */
9818 while (is_space_char (*intel_parser
.op_string
))
9819 intel_parser
.op_string
++;
9821 /* Return an empty token if we find nothing else on the line. */
9822 if (*intel_parser
.op_string
== '\0')
9824 cur_token
= new_token
;
9828 /* The new token cannot be larger than the remainder of the operand
9830 new_token
.str
= (char *) xmalloc (strlen (intel_parser
.op_string
) + 1);
9831 new_token
.str
[0] = '\0';
9833 if (strchr ("0123456789", *intel_parser
.op_string
))
9835 char *p
= new_token
.str
;
9836 char *q
= intel_parser
.op_string
;
9837 new_token
.code
= T_CONST
;
9839 /* Allow any kind of identifier char to encompass floating point and
9840 hexadecimal numbers. */
9841 while (is_identifier_char (*q
))
9845 /* Recognize special symbol names [0-9][bf]. */
9846 if (strlen (intel_parser
.op_string
) == 2
9847 && (intel_parser
.op_string
[1] == 'b'
9848 || intel_parser
.op_string
[1] == 'f'))
9849 new_token
.code
= T_ID
;
9852 else if ((reg
= parse_register (intel_parser
.op_string
, &end_op
)) != NULL
)
9854 size_t len
= end_op
- intel_parser
.op_string
;
9856 new_token
.code
= T_REG
;
9857 new_token
.reg
= reg
;
9859 memcpy (new_token
.str
, intel_parser
.op_string
, len
);
9860 new_token
.str
[len
] = '\0';
9863 else if (is_identifier_char (*intel_parser
.op_string
))
9865 char *p
= new_token
.str
;
9866 char *q
= intel_parser
.op_string
;
9868 /* A '.' or '$' followed by an identifier char is an identifier.
9869 Otherwise, it's operator '.' followed by an expression. */
9870 if ((*q
== '.' || *q
== '$') && !is_identifier_char (*(q
+ 1)))
9872 new_token
.code
= '.';
9873 new_token
.str
[0] = '.';
9874 new_token
.str
[1] = '\0';
9878 while (is_identifier_char (*q
) || *q
== '@')
9882 if (strcasecmp (new_token
.str
, "NOT") == 0)
9883 new_token
.code
= '~';
9885 else if (strcasecmp (new_token
.str
, "MOD") == 0)
9886 new_token
.code
= '%';
9888 else if (strcasecmp (new_token
.str
, "AND") == 0)
9889 new_token
.code
= '&';
9891 else if (strcasecmp (new_token
.str
, "OR") == 0)
9892 new_token
.code
= '|';
9894 else if (strcasecmp (new_token
.str
, "XOR") == 0)
9895 new_token
.code
= '^';
9897 else if (strcasecmp (new_token
.str
, "SHL") == 0)
9898 new_token
.code
= T_SHL
;
9900 else if (strcasecmp (new_token
.str
, "SHR") == 0)
9901 new_token
.code
= T_SHR
;
9903 else if (strcasecmp (new_token
.str
, "BYTE") == 0)
9904 new_token
.code
= T_BYTE
;
9906 else if (strcasecmp (new_token
.str
, "WORD") == 0)
9907 new_token
.code
= T_WORD
;
9909 else if (strcasecmp (new_token
.str
, "DWORD") == 0)
9910 new_token
.code
= T_DWORD
;
9912 else if (strcasecmp (new_token
.str
, "FWORD") == 0)
9913 new_token
.code
= T_FWORD
;
9915 else if (strcasecmp (new_token
.str
, "QWORD") == 0)
9916 new_token
.code
= T_QWORD
;
9918 else if (strcasecmp (new_token
.str
, "TBYTE") == 0
9919 /* XXX remove (gcc still uses it) */
9920 || strcasecmp (new_token
.str
, "XWORD") == 0)
9921 new_token
.code
= T_TBYTE
;
9923 else if (strcasecmp (new_token
.str
, "XMMWORD") == 0
9924 || strcasecmp (new_token
.str
, "OWORD") == 0)
9925 new_token
.code
= T_XMMWORD
;
9927 else if (strcasecmp (new_token
.str
, "YMMWORD") == 0)
9928 new_token
.code
= T_YMMWORD
;
9930 else if (strcasecmp (new_token
.str
, "PTR") == 0)
9931 new_token
.code
= T_PTR
;
9933 else if (strcasecmp (new_token
.str
, "SHORT") == 0)
9934 new_token
.code
= T_SHORT
;
9936 else if (strcasecmp (new_token
.str
, "OFFSET") == 0)
9938 new_token
.code
= T_OFFSET
;
9940 /* ??? This is not mentioned in the MASM grammar but gcc
9941 makes use of it with -mintel-syntax. OFFSET may be
9942 followed by FLAT: */
9943 if (strncasecmp (q
, " FLAT:", 6) == 0)
9944 strcat (new_token
.str
, " FLAT:");
9948 new_token
.code
= T_ID
;
9952 else if (strchr ("+-/*%|&^:[]()~", *intel_parser
.op_string
))
9954 new_token
.code
= *intel_parser
.op_string
;
9955 new_token
.str
[0] = *intel_parser
.op_string
;
9956 new_token
.str
[1] = '\0';
9959 else if (strchr ("<>", *intel_parser
.op_string
)
9960 && *intel_parser
.op_string
== *(intel_parser
.op_string
+ 1))
9962 new_token
.code
= *intel_parser
.op_string
== '<' ? T_SHL
: T_SHR
;
9963 new_token
.str
[0] = *intel_parser
.op_string
;
9964 new_token
.str
[1] = *intel_parser
.op_string
;
9965 new_token
.str
[2] = '\0';
9969 as_bad (_("Unrecognized token `%s'"), intel_parser
.op_string
);
9971 intel_parser
.op_string
+= strlen (new_token
.str
);
9972 cur_token
= new_token
;
9975 /* Put cur_token back into the token stream and make cur_token point to
9978 intel_putback_token (void)
9980 if (cur_token
.code
!= T_NIL
)
9982 intel_parser
.op_string
-= strlen (cur_token
.str
);
9983 free (cur_token
.str
);
9985 cur_token
= prev_token
;
9987 /* Forget prev_token. */
9988 prev_token
.code
= T_NIL
;
9989 prev_token
.reg
= NULL
;
9990 prev_token
.str
= NULL
;
9994 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
9996 int saved_naked_reg
;
9997 char saved_register_dot
;
9999 saved_naked_reg
= allow_naked_reg
;
10000 allow_naked_reg
= 1;
10001 saved_register_dot
= register_chars
['.'];
10002 register_chars
['.'] = '.';
10003 allow_pseudo_reg
= 1;
10004 expression_and_evaluate (exp
);
10005 allow_pseudo_reg
= 0;
10006 register_chars
['.'] = saved_register_dot
;
10007 allow_naked_reg
= saved_naked_reg
;
10009 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
10011 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
10013 exp
->X_op
= O_constant
;
10014 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
10015 .dw2_regnum
[flag_code
>> 1];
10018 exp
->X_op
= O_illegal
;
10023 tc_x86_frame_initial_instructions (void)
10025 static unsigned int sp_regno
[2];
10027 if (!sp_regno
[flag_code
>> 1])
10029 char *saved_input
= input_line_pointer
;
10030 char sp
[][4] = {"esp", "rsp"};
10033 input_line_pointer
= sp
[flag_code
>> 1];
10034 tc_x86_parse_to_dw2regnum (&exp
);
10035 assert (exp
.X_op
== O_constant
);
10036 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
10037 input_line_pointer
= saved_input
;
10040 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
10041 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
10045 i386_elf_section_type (const char *str
, size_t len
)
10047 if (flag_code
== CODE_64BIT
10048 && len
== sizeof ("unwind") - 1
10049 && strncmp (str
, "unwind", 6) == 0)
10050 return SHT_X86_64_UNWIND
;
10057 i386_solaris_fix_up_eh_frame (segT sec
)
10059 if (flag_code
== CODE_64BIT
)
10060 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
10066 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
10070 expr
.X_op
= O_secrel
;
10071 expr
.X_add_symbol
= symbol
;
10072 expr
.X_add_number
= 0;
10073 emit_expr (&expr
, size
);
10077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
10078 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
10081 x86_64_section_letter (int letter
, char **ptr_msg
)
10083 if (flag_code
== CODE_64BIT
)
10086 return SHF_X86_64_LARGE
;
10088 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
10091 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
10096 x86_64_section_word (char *str
, size_t len
)
10098 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
10099 return SHF_X86_64_LARGE
;
10105 handle_large_common (int small ATTRIBUTE_UNUSED
)
10107 if (flag_code
!= CODE_64BIT
)
10109 s_comm_internal (0, elf_common_parse
);
10110 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
10114 static segT lbss_section
;
10115 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
10116 asection
*saved_bss_section
= bss_section
;
10118 if (lbss_section
== NULL
)
10120 flagword applicable
;
10121 segT seg
= now_seg
;
10122 subsegT subseg
= now_subseg
;
10124 /* The .lbss section is for local .largecomm symbols. */
10125 lbss_section
= subseg_new (".lbss", 0);
10126 applicable
= bfd_applicable_section_flags (stdoutput
);
10127 bfd_set_section_flags (stdoutput
, lbss_section
,
10128 applicable
& SEC_ALLOC
);
10129 seg_info (lbss_section
)->bss
= 1;
10131 subseg_set (seg
, subseg
);
10134 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
10135 bss_section
= lbss_section
;
10137 s_comm_internal (0, elf_common_parse
);
10139 elf_com_section_ptr
= saved_com_section_ptr
;
10140 bss_section
= saved_bss_section
;
10143 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */