1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "k6", PROCESSOR_K6
,
582 { "k6_2", PROCESSOR_K6
,
584 { "athlon", PROCESSOR_ATHLON
,
586 { "sledgehammer", PROCESSOR_K8
,
588 { "opteron", PROCESSOR_K8
,
590 { "k8", PROCESSOR_K8
,
592 { "amdfam10", PROCESSOR_AMDFAM10
,
593 CPU_AMDFAM10_FLAGS
},
594 { ".8087", PROCESSOR_UNKNOWN
,
596 { ".287", PROCESSOR_UNKNOWN
,
598 { ".387", PROCESSOR_UNKNOWN
,
600 { ".no87", PROCESSOR_UNKNOWN
,
602 { ".mmx", PROCESSOR_UNKNOWN
,
604 { ".nommx", PROCESSOR_UNKNOWN
,
606 { ".sse", PROCESSOR_UNKNOWN
,
608 { ".sse2", PROCESSOR_UNKNOWN
,
610 { ".sse3", PROCESSOR_UNKNOWN
,
612 { ".ssse3", PROCESSOR_UNKNOWN
,
614 { ".sse4.1", PROCESSOR_UNKNOWN
,
616 { ".sse4.2", PROCESSOR_UNKNOWN
,
618 { ".sse4", PROCESSOR_UNKNOWN
,
620 { ".nosse", PROCESSOR_UNKNOWN
,
622 { ".avx", PROCESSOR_UNKNOWN
,
624 { ".noavx", PROCESSOR_UNKNOWN
,
626 { ".vmx", PROCESSOR_UNKNOWN
,
628 { ".smx", PROCESSOR_UNKNOWN
,
630 { ".xsave", PROCESSOR_UNKNOWN
,
632 { ".aes", PROCESSOR_UNKNOWN
,
634 { ".pclmul", PROCESSOR_UNKNOWN
,
636 { ".clmul", PROCESSOR_UNKNOWN
,
638 { ".fma", PROCESSOR_UNKNOWN
,
640 { ".fma4", PROCESSOR_UNKNOWN
,
642 { ".movbe", PROCESSOR_UNKNOWN
,
644 { ".ept", PROCESSOR_UNKNOWN
,
646 { ".clflush", PROCESSOR_UNKNOWN
,
648 { ".syscall", PROCESSOR_UNKNOWN
,
650 { ".rdtscp", PROCESSOR_UNKNOWN
,
652 { ".3dnow", PROCESSOR_UNKNOWN
,
654 { ".3dnowa", PROCESSOR_UNKNOWN
,
656 { ".padlock", PROCESSOR_UNKNOWN
,
658 { ".pacifica", PROCESSOR_UNKNOWN
,
660 { ".svme", PROCESSOR_UNKNOWN
,
662 { ".sse4a", PROCESSOR_UNKNOWN
,
664 { ".abm", PROCESSOR_UNKNOWN
,
669 /* Like s_lcomm_internal in gas/read.c but the alignment string
670 is allowed to be optional. */
673 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
680 && *input_line_pointer
== ',')
682 align
= parse_align (needs_align
- 1);
684 if (align
== (addressT
) -1)
699 bss_alloc (symbolP
, size
, align
);
704 pe_lcomm (int needs_align
)
706 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
710 const pseudo_typeS md_pseudo_table
[] =
712 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
713 {"align", s_align_bytes
, 0},
715 {"align", s_align_ptwo
, 0},
717 {"arch", set_cpu_arch
, 0},
721 {"lcomm", pe_lcomm
, 1},
723 {"ffloat", float_cons
, 'f'},
724 {"dfloat", float_cons
, 'd'},
725 {"tfloat", float_cons
, 'x'},
727 {"slong", signed_cons
, 4},
728 {"noopt", s_ignore
, 0},
729 {"optim", s_ignore
, 0},
730 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
731 {"code16", set_code_flag
, CODE_16BIT
},
732 {"code32", set_code_flag
, CODE_32BIT
},
733 {"code64", set_code_flag
, CODE_64BIT
},
734 {"intel_syntax", set_intel_syntax
, 1},
735 {"att_syntax", set_intel_syntax
, 0},
736 {"intel_mnemonic", set_intel_mnemonic
, 1},
737 {"att_mnemonic", set_intel_mnemonic
, 0},
738 {"allow_index_reg", set_allow_index_reg
, 1},
739 {"disallow_index_reg", set_allow_index_reg
, 0},
740 {"sse_check", set_sse_check
, 0},
741 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
742 {"largecomm", handle_large_common
, 0},
744 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
745 {"loc", dwarf2_directive_loc
, 0},
746 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
749 {"secrel32", pe_directive_secrel
, 0},
754 /* For interface with expression (). */
755 extern char *input_line_pointer
;
757 /* Hash table for instruction mnemonic lookup. */
758 static struct hash_control
*op_hash
;
760 /* Hash table for register lookup. */
761 static struct hash_control
*reg_hash
;
764 i386_align_code (fragS
*fragP
, int count
)
766 /* Various efficient no-op patterns for aligning code labels.
767 Note: Don't try to assemble the instructions in the comments.
768 0L and 0w are not legal. */
769 static const char f32_1
[] =
771 static const char f32_2
[] =
772 {0x66,0x90}; /* xchg %ax,%ax */
773 static const char f32_3
[] =
774 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
775 static const char f32_4
[] =
776 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
777 static const char f32_5
[] =
779 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
780 static const char f32_6
[] =
781 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
782 static const char f32_7
[] =
783 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
784 static const char f32_8
[] =
786 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
787 static const char f32_9
[] =
788 {0x89,0xf6, /* movl %esi,%esi */
789 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
790 static const char f32_10
[] =
791 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
792 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
793 static const char f32_11
[] =
794 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
795 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
796 static const char f32_12
[] =
797 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
798 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
799 static const char f32_13
[] =
800 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
801 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
802 static const char f32_14
[] =
803 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
804 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
805 static const char f16_3
[] =
806 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
807 static const char f16_4
[] =
808 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
809 static const char f16_5
[] =
811 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
812 static const char f16_6
[] =
813 {0x89,0xf6, /* mov %si,%si */
814 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
815 static const char f16_7
[] =
816 {0x8d,0x74,0x00, /* lea 0(%si),%si */
817 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
818 static const char f16_8
[] =
819 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
820 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
821 static const char jump_31
[] =
822 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
823 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
824 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
825 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
826 static const char *const f32_patt
[] = {
827 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
828 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
830 static const char *const f16_patt
[] = {
831 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
834 static const char alt_3
[] =
836 /* nopl 0(%[re]ax) */
837 static const char alt_4
[] =
838 {0x0f,0x1f,0x40,0x00};
839 /* nopl 0(%[re]ax,%[re]ax,1) */
840 static const char alt_5
[] =
841 {0x0f,0x1f,0x44,0x00,0x00};
842 /* nopw 0(%[re]ax,%[re]ax,1) */
843 static const char alt_6
[] =
844 {0x66,0x0f,0x1f,0x44,0x00,0x00};
845 /* nopl 0L(%[re]ax) */
846 static const char alt_7
[] =
847 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
848 /* nopl 0L(%[re]ax,%[re]ax,1) */
849 static const char alt_8
[] =
850 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
851 /* nopw 0L(%[re]ax,%[re]ax,1) */
852 static const char alt_9
[] =
853 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
854 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
855 static const char alt_10
[] =
856 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_long_11
[] =
861 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
864 nopw %cs:0L(%[re]ax,%[re]ax,1) */
865 static const char alt_long_12
[] =
868 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
872 nopw %cs:0L(%[re]ax,%[re]ax,1) */
873 static const char alt_long_13
[] =
877 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
882 nopw %cs:0L(%[re]ax,%[re]ax,1) */
883 static const char alt_long_14
[] =
888 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
894 nopw %cs:0L(%[re]ax,%[re]ax,1) */
895 static const char alt_long_15
[] =
901 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
902 /* nopl 0(%[re]ax,%[re]ax,1)
903 nopw 0(%[re]ax,%[re]ax,1) */
904 static const char alt_short_11
[] =
905 {0x0f,0x1f,0x44,0x00,0x00,
906 0x66,0x0f,0x1f,0x44,0x00,0x00};
907 /* nopw 0(%[re]ax,%[re]ax,1)
908 nopw 0(%[re]ax,%[re]ax,1) */
909 static const char alt_short_12
[] =
910 {0x66,0x0f,0x1f,0x44,0x00,0x00,
911 0x66,0x0f,0x1f,0x44,0x00,0x00};
912 /* nopw 0(%[re]ax,%[re]ax,1)
914 static const char alt_short_13
[] =
915 {0x66,0x0f,0x1f,0x44,0x00,0x00,
916 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
919 static const char alt_short_14
[] =
920 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
921 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
923 nopl 0L(%[re]ax,%[re]ax,1) */
924 static const char alt_short_15
[] =
925 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
926 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
927 static const char *const alt_short_patt
[] = {
928 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
929 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
930 alt_short_14
, alt_short_15
932 static const char *const alt_long_patt
[] = {
933 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
934 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
935 alt_long_14
, alt_long_15
938 /* Only align for at least a positive non-zero boundary. */
939 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
942 /* We need to decide which NOP sequence to use for 32bit and
943 64bit. When -mtune= is used:
945 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
946 PROCESSOR_GENERIC32, f32_patt will be used.
947 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
948 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
949 PROCESSOR_GENERIC64, alt_long_patt will be used.
950 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
951 PROCESSOR_AMDFAM10, alt_short_patt will be used.
953 When -mtune= isn't used, alt_long_patt will be used if
954 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
957 When -march= or .arch is used, we can't use anything beyond
958 cpu_arch_isa_flags. */
960 if (flag_code
== CODE_16BIT
)
964 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
966 /* Adjust jump offset. */
967 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
970 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
971 f16_patt
[count
- 1], count
);
975 const char *const *patt
= NULL
;
977 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
979 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
980 switch (cpu_arch_tune
)
982 case PROCESSOR_UNKNOWN
:
983 /* We use cpu_arch_isa_flags to check if we SHOULD
984 optimize for Cpu686. */
985 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
986 patt
= alt_long_patt
;
990 case PROCESSOR_PENTIUMPRO
:
991 case PROCESSOR_PENTIUM4
:
992 case PROCESSOR_NOCONA
:
994 case PROCESSOR_CORE2
:
995 case PROCESSOR_COREI7
:
996 case PROCESSOR_GENERIC64
:
997 patt
= alt_long_patt
;
1000 case PROCESSOR_ATHLON
:
1002 case PROCESSOR_AMDFAM10
:
1003 patt
= alt_short_patt
;
1005 case PROCESSOR_I386
:
1006 case PROCESSOR_I486
:
1007 case PROCESSOR_PENTIUM
:
1008 case PROCESSOR_GENERIC32
:
1015 switch (fragP
->tc_frag_data
.tune
)
1017 case PROCESSOR_UNKNOWN
:
1018 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1019 PROCESSOR_UNKNOWN. */
1023 case PROCESSOR_I386
:
1024 case PROCESSOR_I486
:
1025 case PROCESSOR_PENTIUM
:
1027 case PROCESSOR_ATHLON
:
1029 case PROCESSOR_AMDFAM10
:
1030 case PROCESSOR_GENERIC32
:
1031 /* We use cpu_arch_isa_flags to check if we CAN optimize
1033 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1034 patt
= alt_short_patt
;
1038 case PROCESSOR_PENTIUMPRO
:
1039 case PROCESSOR_PENTIUM4
:
1040 case PROCESSOR_NOCONA
:
1041 case PROCESSOR_CORE
:
1042 case PROCESSOR_CORE2
:
1043 case PROCESSOR_COREI7
:
1044 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1045 patt
= alt_long_patt
;
1049 case PROCESSOR_GENERIC64
:
1050 patt
= alt_long_patt
;
1055 if (patt
== f32_patt
)
1057 /* If the padding is less than 15 bytes, we use the normal
1058 ones. Otherwise, we use a jump instruction and adjust
1062 /* For 64bit, the limit is 3 bytes. */
1063 if (flag_code
== CODE_64BIT
1064 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1069 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1070 patt
[count
- 1], count
);
1073 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1075 /* Adjust jump offset. */
1076 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1081 /* Maximum length of an instruction is 15 byte. If the
1082 padding is greater than 15 bytes and we don't use jump,
1083 we have to break it into smaller pieces. */
1084 int padding
= count
;
1085 while (padding
> 15)
1088 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1093 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1094 patt
[padding
- 1], padding
);
1097 fragP
->fr_var
= count
;
1101 operand_type_all_zero (const union i386_operand_type
*x
)
1103 switch (ARRAY_SIZE(x
->array
))
1112 return !x
->array
[0];
1119 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1121 switch (ARRAY_SIZE(x
->array
))
1136 operand_type_equal (const union i386_operand_type
*x
,
1137 const union i386_operand_type
*y
)
1139 switch (ARRAY_SIZE(x
->array
))
1142 if (x
->array
[2] != y
->array
[2])
1145 if (x
->array
[1] != y
->array
[1])
1148 return x
->array
[0] == y
->array
[0];
1156 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1158 switch (ARRAY_SIZE(x
->array
))
1167 return !x
->array
[0];
1174 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1176 switch (ARRAY_SIZE(x
->array
))
1191 cpu_flags_equal (const union i386_cpu_flags
*x
,
1192 const union i386_cpu_flags
*y
)
1194 switch (ARRAY_SIZE(x
->array
))
1197 if (x
->array
[2] != y
->array
[2])
1200 if (x
->array
[1] != y
->array
[1])
1203 return x
->array
[0] == y
->array
[0];
1211 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1213 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1214 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1217 static INLINE i386_cpu_flags
1218 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1220 switch (ARRAY_SIZE (x
.array
))
1223 x
.array
[2] &= y
.array
[2];
1225 x
.array
[1] &= y
.array
[1];
1227 x
.array
[0] &= y
.array
[0];
1235 static INLINE i386_cpu_flags
1236 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1238 switch (ARRAY_SIZE (x
.array
))
1241 x
.array
[2] |= y
.array
[2];
1243 x
.array
[1] |= y
.array
[1];
1245 x
.array
[0] |= y
.array
[0];
1253 static INLINE i386_cpu_flags
1254 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1256 switch (ARRAY_SIZE (x
.array
))
1259 x
.array
[2] &= ~y
.array
[2];
1261 x
.array
[1] &= ~y
.array
[1];
1263 x
.array
[0] &= ~y
.array
[0];
1271 #define CPU_FLAGS_ARCH_MATCH 0x1
1272 #define CPU_FLAGS_64BIT_MATCH 0x2
1273 #define CPU_FLAGS_AES_MATCH 0x4
1274 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1275 #define CPU_FLAGS_AVX_MATCH 0x10
1277 #define CPU_FLAGS_32BIT_MATCH \
1278 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1279 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1280 #define CPU_FLAGS_PERFECT_MATCH \
1281 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1283 /* Return CPU flags match bits. */
1286 cpu_flags_match (const template *t
)
1288 i386_cpu_flags x
= t
->cpu_flags
;
1289 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1291 x
.bitfield
.cpu64
= 0;
1292 x
.bitfield
.cpuno64
= 0;
1294 if (cpu_flags_all_zero (&x
))
1296 /* This instruction is available on all archs. */
1297 match
|= CPU_FLAGS_32BIT_MATCH
;
1301 /* This instruction is available only on some archs. */
1302 i386_cpu_flags cpu
= cpu_arch_flags
;
1304 cpu
.bitfield
.cpu64
= 0;
1305 cpu
.bitfield
.cpuno64
= 0;
1306 cpu
= cpu_flags_and (x
, cpu
);
1307 if (!cpu_flags_all_zero (&cpu
))
1309 if (x
.bitfield
.cpuavx
)
1311 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1312 if (cpu
.bitfield
.cpuavx
)
1314 /* Check SSE2AVX. */
1315 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1317 match
|= (CPU_FLAGS_ARCH_MATCH
1318 | CPU_FLAGS_AVX_MATCH
);
1320 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1321 match
|= CPU_FLAGS_AES_MATCH
;
1323 if (!x
.bitfield
.cpupclmul
1324 || cpu
.bitfield
.cpupclmul
)
1325 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1329 match
|= CPU_FLAGS_ARCH_MATCH
;
1332 match
|= CPU_FLAGS_32BIT_MATCH
;
1338 static INLINE i386_operand_type
1339 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1341 switch (ARRAY_SIZE (x
.array
))
1344 x
.array
[2] &= y
.array
[2];
1346 x
.array
[1] &= y
.array
[1];
1348 x
.array
[0] &= y
.array
[0];
1356 static INLINE i386_operand_type
1357 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1359 switch (ARRAY_SIZE (x
.array
))
1362 x
.array
[2] |= y
.array
[2];
1364 x
.array
[1] |= y
.array
[1];
1366 x
.array
[0] |= y
.array
[0];
1374 static INLINE i386_operand_type
1375 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1377 switch (ARRAY_SIZE (x
.array
))
1380 x
.array
[2] ^= y
.array
[2];
1382 x
.array
[1] ^= y
.array
[1];
1384 x
.array
[0] ^= y
.array
[0];
1392 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1393 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1394 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1395 static const i386_operand_type inoutportreg
1396 = OPERAND_TYPE_INOUTPORTREG
;
1397 static const i386_operand_type reg16_inoutportreg
1398 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1399 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1400 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1401 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1402 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1403 static const i386_operand_type anydisp
1404 = OPERAND_TYPE_ANYDISP
;
1405 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1406 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1407 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1408 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1409 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1410 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1411 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1412 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1413 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1414 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1415 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1426 operand_type_check (i386_operand_type t
, enum operand_type c
)
1431 return (t
.bitfield
.reg8
1434 || t
.bitfield
.reg64
);
1437 return (t
.bitfield
.imm8
1441 || t
.bitfield
.imm32s
1442 || t
.bitfield
.imm64
);
1445 return (t
.bitfield
.disp8
1446 || t
.bitfield
.disp16
1447 || t
.bitfield
.disp32
1448 || t
.bitfield
.disp32s
1449 || t
.bitfield
.disp64
);
1452 return (t
.bitfield
.disp8
1453 || t
.bitfield
.disp16
1454 || t
.bitfield
.disp32
1455 || t
.bitfield
.disp32s
1456 || t
.bitfield
.disp64
1457 || t
.bitfield
.baseindex
);
1466 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1467 operand J for instruction template T. */
1470 match_reg_size (const template *t
, unsigned int j
)
1472 return !((i
.types
[j
].bitfield
.byte
1473 && !t
->operand_types
[j
].bitfield
.byte
)
1474 || (i
.types
[j
].bitfield
.word
1475 && !t
->operand_types
[j
].bitfield
.word
)
1476 || (i
.types
[j
].bitfield
.dword
1477 && !t
->operand_types
[j
].bitfield
.dword
)
1478 || (i
.types
[j
].bitfield
.qword
1479 && !t
->operand_types
[j
].bitfield
.qword
));
1482 /* Return 1 if there is no conflict in any size on operand J for
1483 instruction template T. */
1486 match_mem_size (const template *t
, unsigned int j
)
1488 return (match_reg_size (t
, j
)
1489 && !((i
.types
[j
].bitfield
.unspecified
1490 && !t
->operand_types
[j
].bitfield
.unspecified
)
1491 || (i
.types
[j
].bitfield
.fword
1492 && !t
->operand_types
[j
].bitfield
.fword
)
1493 || (i
.types
[j
].bitfield
.tbyte
1494 && !t
->operand_types
[j
].bitfield
.tbyte
)
1495 || (i
.types
[j
].bitfield
.xmmword
1496 && !t
->operand_types
[j
].bitfield
.xmmword
)
1497 || (i
.types
[j
].bitfield
.ymmword
1498 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1501 /* Return 1 if there is no size conflict on any operands for
1502 instruction template T. */
1505 operand_size_match (const template *t
)
1510 /* Don't check jump instructions. */
1511 if (t
->opcode_modifier
.jump
1512 || t
->opcode_modifier
.jumpbyte
1513 || t
->opcode_modifier
.jumpdword
1514 || t
->opcode_modifier
.jumpintersegment
)
1517 /* Check memory and accumulator operand size. */
1518 for (j
= 0; j
< i
.operands
; j
++)
1520 if (t
->operand_types
[j
].bitfield
.anysize
)
1523 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1529 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1537 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1540 /* Check reverse. */
1541 gas_assert (i
.operands
== 2);
1544 for (j
= 0; j
< 2; j
++)
1546 if (t
->operand_types
[j
].bitfield
.acc
1547 && !match_reg_size (t
, j
? 0 : 1))
1553 if (i
.types
[j
].bitfield
.mem
1554 && !match_mem_size (t
, j
? 0 : 1))
1565 operand_type_match (i386_operand_type overlap
,
1566 i386_operand_type given
)
1568 i386_operand_type temp
= overlap
;
1570 temp
.bitfield
.jumpabsolute
= 0;
1571 temp
.bitfield
.unspecified
= 0;
1572 temp
.bitfield
.byte
= 0;
1573 temp
.bitfield
.word
= 0;
1574 temp
.bitfield
.dword
= 0;
1575 temp
.bitfield
.fword
= 0;
1576 temp
.bitfield
.qword
= 0;
1577 temp
.bitfield
.tbyte
= 0;
1578 temp
.bitfield
.xmmword
= 0;
1579 temp
.bitfield
.ymmword
= 0;
1580 if (operand_type_all_zero (&temp
))
1583 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1584 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1587 /* If given types g0 and g1 are registers they must be of the same type
1588 unless the expected operand type register overlap is null.
1589 Note that Acc in a template matches every size of reg. */
1592 operand_type_register_match (i386_operand_type m0
,
1593 i386_operand_type g0
,
1594 i386_operand_type t0
,
1595 i386_operand_type m1
,
1596 i386_operand_type g1
,
1597 i386_operand_type t1
)
1599 if (!operand_type_check (g0
, reg
))
1602 if (!operand_type_check (g1
, reg
))
1605 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1606 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1607 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1608 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1611 if (m0
.bitfield
.acc
)
1613 t0
.bitfield
.reg8
= 1;
1614 t0
.bitfield
.reg16
= 1;
1615 t0
.bitfield
.reg32
= 1;
1616 t0
.bitfield
.reg64
= 1;
1619 if (m1
.bitfield
.acc
)
1621 t1
.bitfield
.reg8
= 1;
1622 t1
.bitfield
.reg16
= 1;
1623 t1
.bitfield
.reg32
= 1;
1624 t1
.bitfield
.reg64
= 1;
1627 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1628 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1629 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1630 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1633 static INLINE
unsigned int
1634 mode_from_disp_size (i386_operand_type t
)
1636 if (t
.bitfield
.disp8
)
1638 else if (t
.bitfield
.disp16
1639 || t
.bitfield
.disp32
1640 || t
.bitfield
.disp32s
)
1647 fits_in_signed_byte (offsetT num
)
1649 return (num
>= -128) && (num
<= 127);
1653 fits_in_unsigned_byte (offsetT num
)
1655 return (num
& 0xff) == num
;
1659 fits_in_unsigned_word (offsetT num
)
1661 return (num
& 0xffff) == num
;
1665 fits_in_signed_word (offsetT num
)
1667 return (-32768 <= num
) && (num
<= 32767);
1671 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1676 return (!(((offsetT
) -1 << 31) & num
)
1677 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1679 } /* fits_in_signed_long() */
1682 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1687 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1689 } /* fits_in_unsigned_long() */
1691 static i386_operand_type
1692 smallest_imm_type (offsetT num
)
1694 i386_operand_type t
;
1696 operand_type_set (&t
, 0);
1697 t
.bitfield
.imm64
= 1;
1699 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1701 /* This code is disabled on the 486 because all the Imm1 forms
1702 in the opcode table are slower on the i486. They're the
1703 versions with the implicitly specified single-position
1704 displacement, which has another syntax if you really want to
1706 t
.bitfield
.imm1
= 1;
1707 t
.bitfield
.imm8
= 1;
1708 t
.bitfield
.imm8s
= 1;
1709 t
.bitfield
.imm16
= 1;
1710 t
.bitfield
.imm32
= 1;
1711 t
.bitfield
.imm32s
= 1;
1713 else if (fits_in_signed_byte (num
))
1715 t
.bitfield
.imm8
= 1;
1716 t
.bitfield
.imm8s
= 1;
1717 t
.bitfield
.imm16
= 1;
1718 t
.bitfield
.imm32
= 1;
1719 t
.bitfield
.imm32s
= 1;
1721 else if (fits_in_unsigned_byte (num
))
1723 t
.bitfield
.imm8
= 1;
1724 t
.bitfield
.imm16
= 1;
1725 t
.bitfield
.imm32
= 1;
1726 t
.bitfield
.imm32s
= 1;
1728 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1730 t
.bitfield
.imm16
= 1;
1731 t
.bitfield
.imm32
= 1;
1732 t
.bitfield
.imm32s
= 1;
1734 else if (fits_in_signed_long (num
))
1736 t
.bitfield
.imm32
= 1;
1737 t
.bitfield
.imm32s
= 1;
1739 else if (fits_in_unsigned_long (num
))
1740 t
.bitfield
.imm32
= 1;
1746 offset_in_range (offsetT val
, int size
)
1752 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1753 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1754 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1756 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1761 /* If BFD64, sign extend val. */
1762 if (!use_rela_relocations
)
1763 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1764 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1766 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1768 char buf1
[40], buf2
[40];
1770 sprint_value (buf1
, val
);
1771 sprint_value (buf2
, val
& mask
);
1772 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1777 /* Returns 0 if attempting to add a prefix where one from the same
1778 class already exists, 1 if non rep/repne added, 2 if rep/repne
1781 add_prefix (unsigned int prefix
)
1786 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1787 && flag_code
== CODE_64BIT
)
1789 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1790 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1791 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1802 case CS_PREFIX_OPCODE
:
1803 case DS_PREFIX_OPCODE
:
1804 case ES_PREFIX_OPCODE
:
1805 case FS_PREFIX_OPCODE
:
1806 case GS_PREFIX_OPCODE
:
1807 case SS_PREFIX_OPCODE
:
1811 case REPNE_PREFIX_OPCODE
:
1812 case REPE_PREFIX_OPCODE
:
1815 case LOCK_PREFIX_OPCODE
:
1823 case ADDR_PREFIX_OPCODE
:
1827 case DATA_PREFIX_OPCODE
:
1831 if (i
.prefix
[q
] != 0)
1839 i
.prefix
[q
] |= prefix
;
1842 as_bad (_("same type of prefix used twice"));
1848 set_code_flag (int value
)
1851 if (flag_code
== CODE_64BIT
)
1853 cpu_arch_flags
.bitfield
.cpu64
= 1;
1854 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1858 cpu_arch_flags
.bitfield
.cpu64
= 0;
1859 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1861 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1863 as_bad (_("64bit mode not supported on this CPU."));
1865 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1867 as_bad (_("32bit mode not supported on this CPU."));
1869 stackop_size
= '\0';
1873 set_16bit_gcc_code_flag (int new_code_flag
)
1875 flag_code
= new_code_flag
;
1876 if (flag_code
!= CODE_16BIT
)
1878 cpu_arch_flags
.bitfield
.cpu64
= 0;
1879 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1880 stackop_size
= LONG_MNEM_SUFFIX
;
1884 set_intel_syntax (int syntax_flag
)
1886 /* Find out if register prefixing is specified. */
1887 int ask_naked_reg
= 0;
1890 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1892 char *string
= input_line_pointer
;
1893 int e
= get_symbol_end ();
1895 if (strcmp (string
, "prefix") == 0)
1897 else if (strcmp (string
, "noprefix") == 0)
1900 as_bad (_("bad argument to syntax directive."));
1901 *input_line_pointer
= e
;
1903 demand_empty_rest_of_line ();
1905 intel_syntax
= syntax_flag
;
1907 if (ask_naked_reg
== 0)
1908 allow_naked_reg
= (intel_syntax
1909 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1911 allow_naked_reg
= (ask_naked_reg
< 0);
1913 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1915 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1916 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1917 register_prefix
= allow_naked_reg
? "" : "%";
1921 set_intel_mnemonic (int mnemonic_flag
)
1923 intel_mnemonic
= mnemonic_flag
;
1927 set_allow_index_reg (int flag
)
1929 allow_index_reg
= flag
;
1933 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1937 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1939 char *string
= input_line_pointer
;
1940 int e
= get_symbol_end ();
1942 if (strcmp (string
, "none") == 0)
1943 sse_check
= sse_check_none
;
1944 else if (strcmp (string
, "warning") == 0)
1945 sse_check
= sse_check_warning
;
1946 else if (strcmp (string
, "error") == 0)
1947 sse_check
= sse_check_error
;
1949 as_bad (_("bad argument to sse_check directive."));
1950 *input_line_pointer
= e
;
1953 as_bad (_("missing argument for sse_check directive"));
1955 demand_empty_rest_of_line ();
1959 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1963 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1965 char *string
= input_line_pointer
;
1966 int e
= get_symbol_end ();
1968 i386_cpu_flags flags
;
1970 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1972 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1976 cpu_arch_name
= cpu_arch
[i
].name
;
1977 cpu_sub_arch_name
= NULL
;
1978 cpu_arch_flags
= cpu_arch
[i
].flags
;
1979 if (flag_code
== CODE_64BIT
)
1981 cpu_arch_flags
.bitfield
.cpu64
= 1;
1982 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1986 cpu_arch_flags
.bitfield
.cpu64
= 0;
1987 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1989 cpu_arch_isa
= cpu_arch
[i
].type
;
1990 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1991 if (!cpu_arch_tune_set
)
1993 cpu_arch_tune
= cpu_arch_isa
;
1994 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1999 if (strncmp (string
+ 1, "no", 2))
2000 flags
= cpu_flags_or (cpu_arch_flags
,
2003 flags
= cpu_flags_and_not (cpu_arch_flags
,
2005 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2007 if (cpu_sub_arch_name
)
2009 char *name
= cpu_sub_arch_name
;
2010 cpu_sub_arch_name
= concat (name
,
2012 (const char *) NULL
);
2016 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2017 cpu_arch_flags
= flags
;
2019 *input_line_pointer
= e
;
2020 demand_empty_rest_of_line ();
2024 if (i
>= ARRAY_SIZE (cpu_arch
))
2025 as_bad (_("no such architecture: `%s'"), string
);
2027 *input_line_pointer
= e
;
2030 as_bad (_("missing cpu architecture"));
2032 no_cond_jump_promotion
= 0;
2033 if (*input_line_pointer
== ','
2034 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2036 char *string
= ++input_line_pointer
;
2037 int e
= get_symbol_end ();
2039 if (strcmp (string
, "nojumps") == 0)
2040 no_cond_jump_promotion
= 1;
2041 else if (strcmp (string
, "jumps") == 0)
2044 as_bad (_("no such architecture modifier: `%s'"), string
);
2046 *input_line_pointer
= e
;
2049 demand_empty_rest_of_line ();
2055 if (!strcmp (default_arch
, "x86_64"))
2056 return bfd_mach_x86_64
;
2057 else if (!strcmp (default_arch
, "i386"))
2058 return bfd_mach_i386_i386
;
2060 as_fatal (_("Unknown architecture"));
2066 const char *hash_err
;
2068 /* Initialize op_hash hash table. */
2069 op_hash
= hash_new ();
2072 const template *optab
;
2073 templates
*core_optab
;
2075 /* Setup for loop. */
2077 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2078 core_optab
->start
= optab
;
2083 if (optab
->name
== NULL
2084 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2086 /* different name --> ship out current template list;
2087 add to hash table; & begin anew. */
2088 core_optab
->end
= optab
;
2089 hash_err
= hash_insert (op_hash
,
2091 (void *) core_optab
);
2094 as_fatal (_("Internal Error: Can't hash %s: %s"),
2098 if (optab
->name
== NULL
)
2100 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2101 core_optab
->start
= optab
;
2106 /* Initialize reg_hash hash table. */
2107 reg_hash
= hash_new ();
2109 const reg_entry
*regtab
;
2110 unsigned int regtab_size
= i386_regtab_size
;
2112 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2114 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2116 as_fatal (_("Internal Error: Can't hash %s: %s"),
2122 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2127 for (c
= 0; c
< 256; c
++)
2132 mnemonic_chars
[c
] = c
;
2133 register_chars
[c
] = c
;
2134 operand_chars
[c
] = c
;
2136 else if (ISLOWER (c
))
2138 mnemonic_chars
[c
] = c
;
2139 register_chars
[c
] = c
;
2140 operand_chars
[c
] = c
;
2142 else if (ISUPPER (c
))
2144 mnemonic_chars
[c
] = TOLOWER (c
);
2145 register_chars
[c
] = mnemonic_chars
[c
];
2146 operand_chars
[c
] = c
;
2149 if (ISALPHA (c
) || ISDIGIT (c
))
2150 identifier_chars
[c
] = c
;
2153 identifier_chars
[c
] = c
;
2154 operand_chars
[c
] = c
;
2159 identifier_chars
['@'] = '@';
2162 identifier_chars
['?'] = '?';
2163 operand_chars
['?'] = '?';
2165 digit_chars
['-'] = '-';
2166 mnemonic_chars
['_'] = '_';
2167 mnemonic_chars
['-'] = '-';
2168 mnemonic_chars
['.'] = '.';
2169 identifier_chars
['_'] = '_';
2170 identifier_chars
['.'] = '.';
2172 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2173 operand_chars
[(unsigned char) *p
] = *p
;
2176 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2179 record_alignment (text_section
, 2);
2180 record_alignment (data_section
, 2);
2181 record_alignment (bss_section
, 2);
2185 if (flag_code
== CODE_64BIT
)
2187 x86_dwarf2_return_column
= 16;
2188 x86_cie_data_alignment
= -8;
2192 x86_dwarf2_return_column
= 8;
2193 x86_cie_data_alignment
= -4;
2198 i386_print_statistics (FILE *file
)
2200 hash_print_statistics (file
, "i386 opcode", op_hash
);
2201 hash_print_statistics (file
, "i386 register", reg_hash
);
2206 /* Debugging routines for md_assemble. */
2207 static void pte (template *);
2208 static void pt (i386_operand_type
);
2209 static void pe (expressionS
*);
2210 static void ps (symbolS
*);
2213 pi (char *line
, i386_insn
*x
)
2217 fprintf (stdout
, "%s: template ", line
);
2219 fprintf (stdout
, " address: base %s index %s scale %x\n",
2220 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2221 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2222 x
->log2_scale_factor
);
2223 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2224 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2225 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2226 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2227 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2228 (x
->rex
& REX_W
) != 0,
2229 (x
->rex
& REX_R
) != 0,
2230 (x
->rex
& REX_X
) != 0,
2231 (x
->rex
& REX_B
) != 0);
2232 for (i
= 0; i
< x
->operands
; i
++)
2234 fprintf (stdout
, " #%d: ", i
+ 1);
2236 fprintf (stdout
, "\n");
2237 if (x
->types
[i
].bitfield
.reg8
2238 || x
->types
[i
].bitfield
.reg16
2239 || x
->types
[i
].bitfield
.reg32
2240 || x
->types
[i
].bitfield
.reg64
2241 || x
->types
[i
].bitfield
.regmmx
2242 || x
->types
[i
].bitfield
.regxmm
2243 || x
->types
[i
].bitfield
.regymm
2244 || x
->types
[i
].bitfield
.sreg2
2245 || x
->types
[i
].bitfield
.sreg3
2246 || x
->types
[i
].bitfield
.control
2247 || x
->types
[i
].bitfield
.debug
2248 || x
->types
[i
].bitfield
.test
)
2249 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2250 if (operand_type_check (x
->types
[i
], imm
))
2252 if (operand_type_check (x
->types
[i
], disp
))
2253 pe (x
->op
[i
].disps
);
2261 fprintf (stdout
, " %d operands ", t
->operands
);
2262 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2263 if (t
->extension_opcode
!= None
)
2264 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2265 if (t
->opcode_modifier
.d
)
2266 fprintf (stdout
, "D");
2267 if (t
->opcode_modifier
.w
)
2268 fprintf (stdout
, "W");
2269 fprintf (stdout
, "\n");
2270 for (i
= 0; i
< t
->operands
; i
++)
2272 fprintf (stdout
, " #%d type ", i
+ 1);
2273 pt (t
->operand_types
[i
]);
2274 fprintf (stdout
, "\n");
2281 fprintf (stdout
, " operation %d\n", e
->X_op
);
2282 fprintf (stdout
, " add_number %ld (%lx)\n",
2283 (long) e
->X_add_number
, (long) e
->X_add_number
);
2284 if (e
->X_add_symbol
)
2286 fprintf (stdout
, " add_symbol ");
2287 ps (e
->X_add_symbol
);
2288 fprintf (stdout
, "\n");
2292 fprintf (stdout
, " op_symbol ");
2293 ps (e
->X_op_symbol
);
2294 fprintf (stdout
, "\n");
2301 fprintf (stdout
, "%s type %s%s",
2303 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2304 segment_name (S_GET_SEGMENT (s
)));
2307 static struct type_name
2309 i386_operand_type mask
;
2312 const type_names
[] =
2314 { OPERAND_TYPE_REG8
, "r8" },
2315 { OPERAND_TYPE_REG16
, "r16" },
2316 { OPERAND_TYPE_REG32
, "r32" },
2317 { OPERAND_TYPE_REG64
, "r64" },
2318 { OPERAND_TYPE_IMM8
, "i8" },
2319 { OPERAND_TYPE_IMM8
, "i8s" },
2320 { OPERAND_TYPE_IMM16
, "i16" },
2321 { OPERAND_TYPE_IMM32
, "i32" },
2322 { OPERAND_TYPE_IMM32S
, "i32s" },
2323 { OPERAND_TYPE_IMM64
, "i64" },
2324 { OPERAND_TYPE_IMM1
, "i1" },
2325 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2326 { OPERAND_TYPE_DISP8
, "d8" },
2327 { OPERAND_TYPE_DISP16
, "d16" },
2328 { OPERAND_TYPE_DISP32
, "d32" },
2329 { OPERAND_TYPE_DISP32S
, "d32s" },
2330 { OPERAND_TYPE_DISP64
, "d64" },
2331 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2332 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2333 { OPERAND_TYPE_CONTROL
, "control reg" },
2334 { OPERAND_TYPE_TEST
, "test reg" },
2335 { OPERAND_TYPE_DEBUG
, "debug reg" },
2336 { OPERAND_TYPE_FLOATREG
, "FReg" },
2337 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2338 { OPERAND_TYPE_SREG2
, "SReg2" },
2339 { OPERAND_TYPE_SREG3
, "SReg3" },
2340 { OPERAND_TYPE_ACC
, "Acc" },
2341 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2342 { OPERAND_TYPE_REGMMX
, "rMMX" },
2343 { OPERAND_TYPE_REGXMM
, "rXMM" },
2344 { OPERAND_TYPE_REGYMM
, "rYMM" },
2345 { OPERAND_TYPE_ESSEG
, "es" },
2349 pt (i386_operand_type t
)
2352 i386_operand_type a
;
2354 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2356 a
= operand_type_and (t
, type_names
[j
].mask
);
2357 if (!operand_type_all_zero (&a
))
2358 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2363 #endif /* DEBUG386 */
2365 static bfd_reloc_code_real_type
2366 reloc (unsigned int size
,
2369 bfd_reloc_code_real_type other
)
2371 if (other
!= NO_RELOC
)
2373 reloc_howto_type
*reloc
;
2378 case BFD_RELOC_X86_64_GOT32
:
2379 return BFD_RELOC_X86_64_GOT64
;
2381 case BFD_RELOC_X86_64_PLTOFF64
:
2382 return BFD_RELOC_X86_64_PLTOFF64
;
2384 case BFD_RELOC_X86_64_GOTPC32
:
2385 other
= BFD_RELOC_X86_64_GOTPC64
;
2387 case BFD_RELOC_X86_64_GOTPCREL
:
2388 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2390 case BFD_RELOC_X86_64_TPOFF32
:
2391 other
= BFD_RELOC_X86_64_TPOFF64
;
2393 case BFD_RELOC_X86_64_DTPOFF32
:
2394 other
= BFD_RELOC_X86_64_DTPOFF64
;
2400 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2401 if (size
== 4 && flag_code
!= CODE_64BIT
)
2404 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2406 as_bad (_("unknown relocation (%u)"), other
);
2407 else if (size
!= bfd_get_reloc_size (reloc
))
2408 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2409 bfd_get_reloc_size (reloc
),
2411 else if (pcrel
&& !reloc
->pc_relative
)
2412 as_bad (_("non-pc-relative relocation for pc-relative field"));
2413 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2415 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2417 as_bad (_("relocated field and relocation type differ in signedness"));
2426 as_bad (_("there are no unsigned pc-relative relocations"));
2429 case 1: return BFD_RELOC_8_PCREL
;
2430 case 2: return BFD_RELOC_16_PCREL
;
2431 case 4: return BFD_RELOC_32_PCREL
;
2432 case 8: return BFD_RELOC_64_PCREL
;
2434 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2441 case 4: return BFD_RELOC_X86_64_32S
;
2446 case 1: return BFD_RELOC_8
;
2447 case 2: return BFD_RELOC_16
;
2448 case 4: return BFD_RELOC_32
;
2449 case 8: return BFD_RELOC_64
;
2451 as_bad (_("cannot do %s %u byte relocation"),
2452 sign
> 0 ? "signed" : "unsigned", size
);
2458 /* Here we decide which fixups can be adjusted to make them relative to
2459 the beginning of the section instead of the symbol. Basically we need
2460 to make sure that the dynamic relocations are done correctly, so in
2461 some cases we force the original symbol to be used. */
2464 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2466 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2470 /* Don't adjust pc-relative references to merge sections in 64-bit
2472 if (use_rela_relocations
2473 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2477 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2478 and changed later by validate_fix. */
2479 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2480 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2483 /* adjust_reloc_syms doesn't know about the GOT. */
2484 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2485 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2486 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2487 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2488 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2489 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2490 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2491 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2492 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2493 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2494 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2495 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2496 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2497 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2498 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2499 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2500 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2501 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2502 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2503 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2504 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2505 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2506 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2507 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2508 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2509 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2510 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2511 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2514 if (fixP
->fx_addsy
!= NULL
2515 && symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_GNU_INDIRECT_FUNCTION
)
2522 intel_float_operand (const char *mnemonic
)
2524 /* Note that the value returned is meaningful only for opcodes with (memory)
2525 operands, hence the code here is free to improperly handle opcodes that
2526 have no operands (for better performance and smaller code). */
2528 if (mnemonic
[0] != 'f')
2529 return 0; /* non-math */
2531 switch (mnemonic
[1])
2533 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2534 the fs segment override prefix not currently handled because no
2535 call path can make opcodes without operands get here */
2537 return 2 /* integer op */;
2539 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2540 return 3; /* fldcw/fldenv */
2543 if (mnemonic
[2] != 'o' /* fnop */)
2544 return 3; /* non-waiting control op */
2547 if (mnemonic
[2] == 's')
2548 return 3; /* frstor/frstpm */
2551 if (mnemonic
[2] == 'a')
2552 return 3; /* fsave */
2553 if (mnemonic
[2] == 't')
2555 switch (mnemonic
[3])
2557 case 'c': /* fstcw */
2558 case 'd': /* fstdw */
2559 case 'e': /* fstenv */
2560 case 's': /* fsts[gw] */
2566 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2567 return 0; /* fxsave/fxrstor are not really math ops */
2574 /* Build the VEX prefix. */
2577 build_vex_prefix (const template *t
)
2579 unsigned int register_specifier
;
2580 unsigned int implied_prefix
;
2581 unsigned int vector_length
;
2583 /* Check register specifier. */
2584 if (i
.vex
.register_specifier
)
2586 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2587 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2588 register_specifier
+= 8;
2589 register_specifier
= ~register_specifier
& 0xf;
2592 register_specifier
= 0xf;
2594 /* Use 2-byte VEX prefix by swappping destination and source
2597 && i
.operands
== i
.reg_operands
2598 && i
.tm
.opcode_modifier
.vex0f
2599 && i
.tm
.opcode_modifier
.s
2602 unsigned int xchg
= i
.operands
- 1;
2603 union i386_op temp_op
;
2604 i386_operand_type temp_type
;
2606 temp_type
= i
.types
[xchg
];
2607 i
.types
[xchg
] = i
.types
[0];
2608 i
.types
[0] = temp_type
;
2609 temp_op
= i
.op
[xchg
];
2610 i
.op
[xchg
] = i
.op
[0];
2613 gas_assert (i
.rm
.mode
== 3);
2617 i
.rm
.regmem
= i
.rm
.reg
;
2620 /* Use the next insn. */
2624 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2626 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2631 case DATA_PREFIX_OPCODE
:
2634 case REPE_PREFIX_OPCODE
:
2637 case REPNE_PREFIX_OPCODE
:
2644 /* Use 2-byte VEX prefix if possible. */
2645 if (i
.tm
.opcode_modifier
.vex0f
2646 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2648 /* 2-byte VEX prefix. */
2652 i
.vex
.bytes
[0] = 0xc5;
2654 /* Check the REX.R bit. */
2655 r
= (i
.rex
& REX_R
) ? 0 : 1;
2656 i
.vex
.bytes
[1] = (r
<< 7
2657 | register_specifier
<< 3
2658 | vector_length
<< 2
2663 /* 3-byte VEX prefix. */
2666 if (i
.tm
.opcode_modifier
.vex0f
)
2668 else if (i
.tm
.opcode_modifier
.vex0f38
)
2670 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2676 i
.vex
.bytes
[0] = 0xc4;
2678 /* The high 3 bits of the second VEX byte are 1's compliment
2679 of RXB bits from REX. */
2680 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2682 /* Check the REX.W bit. */
2683 w
= (i
.rex
& REX_W
) ? 1 : 0;
2684 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2689 if (i
.tm
.opcode_modifier
.vexw1
)
2693 i
.vex
.bytes
[2] = (w
<< 7
2694 | register_specifier
<< 3
2695 | vector_length
<< 2
2701 process_immext (void)
2705 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2707 /* SSE3 Instructions have the fixed operands with an opcode
2708 suffix which is coded in the same place as an 8-bit immediate
2709 field would be. Here we check those operands and remove them
2713 for (x
= 0; x
< i
.operands
; x
++)
2714 if (i
.op
[x
].regs
->reg_num
!= x
)
2715 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2716 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2722 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2723 which is coded in the same place as an 8-bit immediate field
2724 would be. Here we fake an 8-bit immediate operand from the
2725 opcode suffix stored in tm.extension_opcode.
2727 AVX instructions also use this encoding, for some of
2728 3 argument instructions. */
2730 gas_assert (i
.imm_operands
== 0
2732 || (i
.tm
.opcode_modifier
.vex
2733 && i
.operands
<= 4)));
2735 exp
= &im_expressions
[i
.imm_operands
++];
2736 i
.op
[i
.operands
].imms
= exp
;
2737 i
.types
[i
.operands
] = imm8
;
2739 exp
->X_op
= O_constant
;
2740 exp
->X_add_number
= i
.tm
.extension_opcode
;
2741 i
.tm
.extension_opcode
= None
;
2744 /* This is the guts of the machine-dependent assembler. LINE points to a
2745 machine dependent instruction. This function is supposed to emit
2746 the frags/bytes it assembles to. */
2749 md_assemble (char *line
)
2752 char mnemonic
[MAX_MNEM_SIZE
];
2755 /* Initialize globals. */
2756 memset (&i
, '\0', sizeof (i
));
2757 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2758 i
.reloc
[j
] = NO_RELOC
;
2759 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2760 memset (im_expressions
, '\0', sizeof (im_expressions
));
2761 save_stack_p
= save_stack
;
2763 /* First parse an instruction mnemonic & call i386_operand for the operands.
2764 We assume that the scrubber has arranged it so that line[0] is the valid
2765 start of a (possibly prefixed) mnemonic. */
2767 line
= parse_insn (line
, mnemonic
);
2771 line
= parse_operands (line
, mnemonic
);
2776 /* Now we've parsed the mnemonic into a set of templates, and have the
2777 operands at hand. */
2779 /* All intel opcodes have reversed operands except for "bound" and
2780 "enter". We also don't reverse intersegment "jmp" and "call"
2781 instructions with 2 immediate operands so that the immediate segment
2782 precedes the offset, as it does when in AT&T mode. */
2785 && (strcmp (mnemonic
, "bound") != 0)
2786 && (strcmp (mnemonic
, "invlpga") != 0)
2787 && !(operand_type_check (i
.types
[0], imm
)
2788 && operand_type_check (i
.types
[1], imm
)))
2791 /* The order of the immediates should be reversed
2792 for 2 immediates extrq and insertq instructions */
2793 if (i
.imm_operands
== 2
2794 && (strcmp (mnemonic
, "extrq") == 0
2795 || strcmp (mnemonic
, "insertq") == 0))
2796 swap_2_operands (0, 1);
2801 /* Don't optimize displacement for movabs since it only takes 64bit
2804 && (flag_code
!= CODE_64BIT
2805 || strcmp (mnemonic
, "movabs") != 0))
2808 /* Next, we find a template that matches the given insn,
2809 making sure the overlap of the given operands types is consistent
2810 with the template operand types. */
2812 if (!(t
= match_template ()))
2815 if (sse_check
!= sse_check_none
2816 && !i
.tm
.opcode_modifier
.noavx
2817 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2818 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2819 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2820 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2821 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2822 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2824 (sse_check
== sse_check_warning
2826 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2829 /* Zap movzx and movsx suffix. The suffix has been set from
2830 "word ptr" or "byte ptr" on the source operand in Intel syntax
2831 or extracted from mnemonic in AT&T syntax. But we'll use
2832 the destination register to choose the suffix for encoding. */
2833 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2835 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2836 there is no suffix, the default will be byte extension. */
2837 if (i
.reg_operands
!= 2
2840 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2845 if (i
.tm
.opcode_modifier
.fwait
)
2846 if (!add_prefix (FWAIT_OPCODE
))
2849 /* Check string instruction segment overrides. */
2850 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2852 if (!check_string ())
2854 i
.disp_operands
= 0;
2857 if (!process_suffix ())
2860 /* Update operand types. */
2861 for (j
= 0; j
< i
.operands
; j
++)
2862 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2864 /* Make still unresolved immediate matches conform to size of immediate
2865 given in i.suffix. */
2866 if (!finalize_imm ())
2869 if (i
.types
[0].bitfield
.imm1
)
2870 i
.imm_operands
= 0; /* kludge for shift insns. */
2872 /* We only need to check those implicit registers for instructions
2873 with 3 operands or less. */
2874 if (i
.operands
<= 3)
2875 for (j
= 0; j
< i
.operands
; j
++)
2876 if (i
.types
[j
].bitfield
.inoutportreg
2877 || i
.types
[j
].bitfield
.shiftcount
2878 || i
.types
[j
].bitfield
.acc
2879 || i
.types
[j
].bitfield
.floatacc
)
2882 /* ImmExt should be processed after SSE2AVX. */
2883 if (!i
.tm
.opcode_modifier
.sse2avx
2884 && i
.tm
.opcode_modifier
.immext
)
2887 /* For insns with operands there are more diddles to do to the opcode. */
2890 if (!process_operands ())
2893 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2895 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2896 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2899 if (i
.tm
.opcode_modifier
.vex
)
2900 build_vex_prefix (t
);
2902 /* Handle conversion of 'int $3' --> special int3 insn. */
2903 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2905 i
.tm
.base_opcode
= INT3_OPCODE
;
2909 if ((i
.tm
.opcode_modifier
.jump
2910 || i
.tm
.opcode_modifier
.jumpbyte
2911 || i
.tm
.opcode_modifier
.jumpdword
)
2912 && i
.op
[0].disps
->X_op
== O_constant
)
2914 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2915 the absolute address given by the constant. Since ix86 jumps and
2916 calls are pc relative, we need to generate a reloc. */
2917 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2918 i
.op
[0].disps
->X_op
= O_symbol
;
2921 if (i
.tm
.opcode_modifier
.rex64
)
2924 /* For 8 bit registers we need an empty rex prefix. Also if the
2925 instruction already has a prefix, we need to convert old
2926 registers to new ones. */
2928 if ((i
.types
[0].bitfield
.reg8
2929 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2930 || (i
.types
[1].bitfield
.reg8
2931 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2932 || ((i
.types
[0].bitfield
.reg8
2933 || i
.types
[1].bitfield
.reg8
)
2938 i
.rex
|= REX_OPCODE
;
2939 for (x
= 0; x
< 2; x
++)
2941 /* Look for 8 bit operand that uses old registers. */
2942 if (i
.types
[x
].bitfield
.reg8
2943 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2945 /* In case it is "hi" register, give up. */
2946 if (i
.op
[x
].regs
->reg_num
> 3)
2947 as_bad (_("can't encode register '%s%s' in an "
2948 "instruction requiring REX prefix."),
2949 register_prefix
, i
.op
[x
].regs
->reg_name
);
2951 /* Otherwise it is equivalent to the extended register.
2952 Since the encoding doesn't change this is merely
2953 cosmetic cleanup for debug output. */
2955 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2961 add_prefix (REX_OPCODE
| i
.rex
);
2963 /* We are ready to output the insn. */
2968 parse_insn (char *line
, char *mnemonic
)
2971 char *token_start
= l
;
2977 /* Non-zero if we found a prefix only acceptable with string insns. */
2978 const char *expecting_string_instruction
= NULL
;
2983 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2988 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2990 as_bad (_("no such instruction: `%s'"), token_start
);
2995 if (!is_space_char (*l
)
2996 && *l
!= END_OF_INSN
2998 || (*l
!= PREFIX_SEPARATOR
3001 as_bad (_("invalid character %s in mnemonic"),
3002 output_invalid (*l
));
3005 if (token_start
== l
)
3007 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3008 as_bad (_("expecting prefix; got nothing"));
3010 as_bad (_("expecting mnemonic; got nothing"));
3014 /* Look up instruction (or prefix) via hash table. */
3015 current_templates
= hash_find (op_hash
, mnemonic
);
3017 if (*l
!= END_OF_INSN
3018 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3019 && current_templates
3020 && current_templates
->start
->opcode_modifier
.isprefix
)
3022 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3024 as_bad ((flag_code
!= CODE_64BIT
3025 ? _("`%s' is only supported in 64-bit mode")
3026 : _("`%s' is not supported in 64-bit mode")),
3027 current_templates
->start
->name
);
3030 /* If we are in 16-bit mode, do not allow addr16 or data16.
3031 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3032 if ((current_templates
->start
->opcode_modifier
.size16
3033 || current_templates
->start
->opcode_modifier
.size32
)
3034 && flag_code
!= CODE_64BIT
3035 && (current_templates
->start
->opcode_modifier
.size32
3036 ^ (flag_code
== CODE_16BIT
)))
3038 as_bad (_("redundant %s prefix"),
3039 current_templates
->start
->name
);
3042 /* Add prefix, checking for repeated prefixes. */
3043 switch (add_prefix (current_templates
->start
->base_opcode
))
3048 expecting_string_instruction
= current_templates
->start
->name
;
3051 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3058 if (!current_templates
)
3060 /* Check if we should swap operand in encoding. */
3061 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3067 current_templates
= hash_find (op_hash
, mnemonic
);
3070 if (!current_templates
)
3073 /* See if we can get a match by trimming off a suffix. */
3076 case WORD_MNEM_SUFFIX
:
3077 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3078 i
.suffix
= SHORT_MNEM_SUFFIX
;
3080 case BYTE_MNEM_SUFFIX
:
3081 case QWORD_MNEM_SUFFIX
:
3082 i
.suffix
= mnem_p
[-1];
3084 current_templates
= hash_find (op_hash
, mnemonic
);
3086 case SHORT_MNEM_SUFFIX
:
3087 case LONG_MNEM_SUFFIX
:
3090 i
.suffix
= mnem_p
[-1];
3092 current_templates
= hash_find (op_hash
, mnemonic
);
3100 if (intel_float_operand (mnemonic
) == 1)
3101 i
.suffix
= SHORT_MNEM_SUFFIX
;
3103 i
.suffix
= LONG_MNEM_SUFFIX
;
3105 current_templates
= hash_find (op_hash
, mnemonic
);
3109 if (!current_templates
)
3111 as_bad (_("no such instruction: `%s'"), token_start
);
3116 if (current_templates
->start
->opcode_modifier
.jump
3117 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3119 /* Check for a branch hint. We allow ",pt" and ",pn" for
3120 predict taken and predict not taken respectively.
3121 I'm not sure that branch hints actually do anything on loop
3122 and jcxz insns (JumpByte) for current Pentium4 chips. They
3123 may work in the future and it doesn't hurt to accept them
3125 if (l
[0] == ',' && l
[1] == 'p')
3129 if (!add_prefix (DS_PREFIX_OPCODE
))
3133 else if (l
[2] == 'n')
3135 if (!add_prefix (CS_PREFIX_OPCODE
))
3141 /* Any other comma loses. */
3144 as_bad (_("invalid character %s in mnemonic"),
3145 output_invalid (*l
));
3149 /* Check if instruction is supported on specified architecture. */
3151 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3153 supported
|= cpu_flags_match (t
);
3154 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3158 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3160 as_bad (flag_code
== CODE_64BIT
3161 ? _("`%s' is not supported in 64-bit mode")
3162 : _("`%s' is only supported in 64-bit mode"),
3163 current_templates
->start
->name
);
3166 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3168 as_bad (_("`%s' is not supported on `%s%s'"),
3169 current_templates
->start
->name
,
3170 cpu_arch_name
? cpu_arch_name
: default_arch
,
3171 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3176 if (!cpu_arch_flags
.bitfield
.cpui386
3177 && (flag_code
!= CODE_16BIT
))
3179 as_warn (_("use .code16 to ensure correct addressing mode"));
3182 /* Check for rep/repne without a string instruction. */
3183 if (expecting_string_instruction
)
3185 static templates override
;
3187 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3188 if (t
->opcode_modifier
.isstring
)
3190 if (t
>= current_templates
->end
)
3192 as_bad (_("expecting string instruction after `%s'"),
3193 expecting_string_instruction
);
3196 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3197 if (!t
->opcode_modifier
.isstring
)
3200 current_templates
= &override
;
3207 parse_operands (char *l
, const char *mnemonic
)
3211 /* 1 if operand is pending after ','. */
3212 unsigned int expecting_operand
= 0;
3214 /* Non-zero if operand parens not balanced. */
3215 unsigned int paren_not_balanced
;
3217 while (*l
!= END_OF_INSN
)
3219 /* Skip optional white space before operand. */
3220 if (is_space_char (*l
))
3222 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3224 as_bad (_("invalid character %s before operand %d"),
3225 output_invalid (*l
),
3229 token_start
= l
; /* after white space */
3230 paren_not_balanced
= 0;
3231 while (paren_not_balanced
|| *l
!= ',')
3233 if (*l
== END_OF_INSN
)
3235 if (paren_not_balanced
)
3238 as_bad (_("unbalanced parenthesis in operand %d."),
3241 as_bad (_("unbalanced brackets in operand %d."),
3246 break; /* we are done */
3248 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3250 as_bad (_("invalid character %s in operand %d"),
3251 output_invalid (*l
),
3258 ++paren_not_balanced
;
3260 --paren_not_balanced
;
3265 ++paren_not_balanced
;
3267 --paren_not_balanced
;
3271 if (l
!= token_start
)
3272 { /* Yes, we've read in another operand. */
3273 unsigned int operand_ok
;
3274 this_operand
= i
.operands
++;
3275 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3276 if (i
.operands
> MAX_OPERANDS
)
3278 as_bad (_("spurious operands; (%d operands/instruction max)"),
3282 /* Now parse operand adding info to 'i' as we go along. */
3283 END_STRING_AND_SAVE (l
);
3287 i386_intel_operand (token_start
,
3288 intel_float_operand (mnemonic
));
3290 operand_ok
= i386_att_operand (token_start
);
3292 RESTORE_END_STRING (l
);
3298 if (expecting_operand
)
3300 expecting_operand_after_comma
:
3301 as_bad (_("expecting operand after ','; got nothing"));
3306 as_bad (_("expecting operand before ','; got nothing"));
3311 /* Now *l must be either ',' or END_OF_INSN. */
3314 if (*++l
== END_OF_INSN
)
3316 /* Just skip it, if it's \n complain. */
3317 goto expecting_operand_after_comma
;
3319 expecting_operand
= 1;
3326 swap_2_operands (int xchg1
, int xchg2
)
3328 union i386_op temp_op
;
3329 i386_operand_type temp_type
;
3330 enum bfd_reloc_code_real temp_reloc
;
3332 temp_type
= i
.types
[xchg2
];
3333 i
.types
[xchg2
] = i
.types
[xchg1
];
3334 i
.types
[xchg1
] = temp_type
;
3335 temp_op
= i
.op
[xchg2
];
3336 i
.op
[xchg2
] = i
.op
[xchg1
];
3337 i
.op
[xchg1
] = temp_op
;
3338 temp_reloc
= i
.reloc
[xchg2
];
3339 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3340 i
.reloc
[xchg1
] = temp_reloc
;
3344 swap_operands (void)
3350 swap_2_operands (1, i
.operands
- 2);
3353 swap_2_operands (0, i
.operands
- 1);
3359 if (i
.mem_operands
== 2)
3361 const seg_entry
*temp_seg
;
3362 temp_seg
= i
.seg
[0];
3363 i
.seg
[0] = i
.seg
[1];
3364 i
.seg
[1] = temp_seg
;
3368 /* Try to ensure constant immediates are represented in the smallest
3373 char guess_suffix
= 0;
3377 guess_suffix
= i
.suffix
;
3378 else if (i
.reg_operands
)
3380 /* Figure out a suffix from the last register operand specified.
3381 We can't do this properly yet, ie. excluding InOutPortReg,
3382 but the following works for instructions with immediates.
3383 In any case, we can't set i.suffix yet. */
3384 for (op
= i
.operands
; --op
>= 0;)
3385 if (i
.types
[op
].bitfield
.reg8
)
3387 guess_suffix
= BYTE_MNEM_SUFFIX
;
3390 else if (i
.types
[op
].bitfield
.reg16
)
3392 guess_suffix
= WORD_MNEM_SUFFIX
;
3395 else if (i
.types
[op
].bitfield
.reg32
)
3397 guess_suffix
= LONG_MNEM_SUFFIX
;
3400 else if (i
.types
[op
].bitfield
.reg64
)
3402 guess_suffix
= QWORD_MNEM_SUFFIX
;
3406 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3407 guess_suffix
= WORD_MNEM_SUFFIX
;
3409 for (op
= i
.operands
; --op
>= 0;)
3410 if (operand_type_check (i
.types
[op
], imm
))
3412 switch (i
.op
[op
].imms
->X_op
)
3415 /* If a suffix is given, this operand may be shortened. */
3416 switch (guess_suffix
)
3418 case LONG_MNEM_SUFFIX
:
3419 i
.types
[op
].bitfield
.imm32
= 1;
3420 i
.types
[op
].bitfield
.imm64
= 1;
3422 case WORD_MNEM_SUFFIX
:
3423 i
.types
[op
].bitfield
.imm16
= 1;
3424 i
.types
[op
].bitfield
.imm32
= 1;
3425 i
.types
[op
].bitfield
.imm32s
= 1;
3426 i
.types
[op
].bitfield
.imm64
= 1;
3428 case BYTE_MNEM_SUFFIX
:
3429 i
.types
[op
].bitfield
.imm8
= 1;
3430 i
.types
[op
].bitfield
.imm8s
= 1;
3431 i
.types
[op
].bitfield
.imm16
= 1;
3432 i
.types
[op
].bitfield
.imm32
= 1;
3433 i
.types
[op
].bitfield
.imm32s
= 1;
3434 i
.types
[op
].bitfield
.imm64
= 1;
3438 /* If this operand is at most 16 bits, convert it
3439 to a signed 16 bit number before trying to see
3440 whether it will fit in an even smaller size.
3441 This allows a 16-bit operand such as $0xffe0 to
3442 be recognised as within Imm8S range. */
3443 if ((i
.types
[op
].bitfield
.imm16
)
3444 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3446 i
.op
[op
].imms
->X_add_number
=
3447 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3449 if ((i
.types
[op
].bitfield
.imm32
)
3450 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3453 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3454 ^ ((offsetT
) 1 << 31))
3455 - ((offsetT
) 1 << 31));
3458 = operand_type_or (i
.types
[op
],
3459 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3461 /* We must avoid matching of Imm32 templates when 64bit
3462 only immediate is available. */
3463 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3464 i
.types
[op
].bitfield
.imm32
= 0;
3471 /* Symbols and expressions. */
3473 /* Convert symbolic operand to proper sizes for matching, but don't
3474 prevent matching a set of insns that only supports sizes other
3475 than those matching the insn suffix. */
3477 i386_operand_type mask
, allowed
;
3480 operand_type_set (&mask
, 0);
3481 operand_type_set (&allowed
, 0);
3483 for (t
= current_templates
->start
;
3484 t
< current_templates
->end
;
3486 allowed
= operand_type_or (allowed
,
3487 t
->operand_types
[op
]);
3488 switch (guess_suffix
)
3490 case QWORD_MNEM_SUFFIX
:
3491 mask
.bitfield
.imm64
= 1;
3492 mask
.bitfield
.imm32s
= 1;
3494 case LONG_MNEM_SUFFIX
:
3495 mask
.bitfield
.imm32
= 1;
3497 case WORD_MNEM_SUFFIX
:
3498 mask
.bitfield
.imm16
= 1;
3500 case BYTE_MNEM_SUFFIX
:
3501 mask
.bitfield
.imm8
= 1;
3506 allowed
= operand_type_and (mask
, allowed
);
3507 if (!operand_type_all_zero (&allowed
))
3508 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3515 /* Try to use the smallest displacement type too. */
3517 optimize_disp (void)
3521 for (op
= i
.operands
; --op
>= 0;)
3522 if (operand_type_check (i
.types
[op
], disp
))
3524 if (i
.op
[op
].disps
->X_op
== O_constant
)
3526 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3528 if (i
.types
[op
].bitfield
.disp16
3529 && (disp
& ~(offsetT
) 0xffff) == 0)
3531 /* If this operand is at most 16 bits, convert
3532 to a signed 16 bit number and don't use 64bit
3534 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3535 i
.types
[op
].bitfield
.disp64
= 0;
3537 if (i
.types
[op
].bitfield
.disp32
3538 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3540 /* If this operand is at most 32 bits, convert
3541 to a signed 32 bit number and don't use 64bit
3543 disp
&= (((offsetT
) 2 << 31) - 1);
3544 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3545 i
.types
[op
].bitfield
.disp64
= 0;
3547 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3549 i
.types
[op
].bitfield
.disp8
= 0;
3550 i
.types
[op
].bitfield
.disp16
= 0;
3551 i
.types
[op
].bitfield
.disp32
= 0;
3552 i
.types
[op
].bitfield
.disp32s
= 0;
3553 i
.types
[op
].bitfield
.disp64
= 0;
3557 else if (flag_code
== CODE_64BIT
)
3559 if (fits_in_signed_long (disp
))
3561 i
.types
[op
].bitfield
.disp64
= 0;
3562 i
.types
[op
].bitfield
.disp32s
= 1;
3564 if (fits_in_unsigned_long (disp
))
3565 i
.types
[op
].bitfield
.disp32
= 1;
3567 if ((i
.types
[op
].bitfield
.disp32
3568 || i
.types
[op
].bitfield
.disp32s
3569 || i
.types
[op
].bitfield
.disp16
)
3570 && fits_in_signed_byte (disp
))
3571 i
.types
[op
].bitfield
.disp8
= 1;
3573 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3574 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3576 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3577 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3578 i
.types
[op
].bitfield
.disp8
= 0;
3579 i
.types
[op
].bitfield
.disp16
= 0;
3580 i
.types
[op
].bitfield
.disp32
= 0;
3581 i
.types
[op
].bitfield
.disp32s
= 0;
3582 i
.types
[op
].bitfield
.disp64
= 0;
3585 /* We only support 64bit displacement on constants. */
3586 i
.types
[op
].bitfield
.disp64
= 0;
3590 static const template *
3591 match_template (void)
3593 /* Points to template once we've found it. */
3595 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3596 i386_operand_type overlap4
;
3597 unsigned int found_reverse_match
;
3598 i386_opcode_modifier suffix_check
;
3599 i386_operand_type operand_types
[MAX_OPERANDS
];
3600 int addr_prefix_disp
;
3602 unsigned int found_cpu_match
;
3603 unsigned int check_register
;
3605 #if MAX_OPERANDS != 5
3606 # error "MAX_OPERANDS must be 5."
3609 found_reverse_match
= 0;
3610 addr_prefix_disp
= -1;
3612 memset (&suffix_check
, 0, sizeof (suffix_check
));
3613 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3614 suffix_check
.no_bsuf
= 1;
3615 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3616 suffix_check
.no_wsuf
= 1;
3617 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3618 suffix_check
.no_ssuf
= 1;
3619 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3620 suffix_check
.no_lsuf
= 1;
3621 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3622 suffix_check
.no_qsuf
= 1;
3623 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3624 suffix_check
.no_ldsuf
= 1;
3626 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3628 addr_prefix_disp
= -1;
3630 /* Must have right number of operands. */
3631 if (i
.operands
!= t
->operands
)
3634 /* Check processor support. */
3635 found_cpu_match
= (cpu_flags_match (t
)
3636 == CPU_FLAGS_PERFECT_MATCH
);
3637 if (!found_cpu_match
)
3640 /* Check old gcc support. */
3641 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3644 /* Check AT&T mnemonic. */
3645 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3648 /* Check AT&T syntax Intel syntax. */
3649 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3650 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3653 /* Check the suffix, except for some instructions in intel mode. */
3654 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3655 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3656 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3657 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3658 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3659 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3660 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3663 if (!operand_size_match (t
))
3666 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3667 operand_types
[j
] = t
->operand_types
[j
];
3669 /* In general, don't allow 64-bit operands in 32-bit mode. */
3670 if (i
.suffix
== QWORD_MNEM_SUFFIX
3671 && flag_code
!= CODE_64BIT
3673 ? (!t
->opcode_modifier
.ignoresize
3674 && !intel_float_operand (t
->name
))
3675 : intel_float_operand (t
->name
) != 2)
3676 && ((!operand_types
[0].bitfield
.regmmx
3677 && !operand_types
[0].bitfield
.regxmm
3678 && !operand_types
[0].bitfield
.regymm
)
3679 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3680 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3681 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3682 && (t
->base_opcode
!= 0x0fc7
3683 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3686 /* In general, don't allow 32-bit operands on pre-386. */
3687 else if (i
.suffix
== LONG_MNEM_SUFFIX
3688 && !cpu_arch_flags
.bitfield
.cpui386
3690 ? (!t
->opcode_modifier
.ignoresize
3691 && !intel_float_operand (t
->name
))
3692 : intel_float_operand (t
->name
) != 2)
3693 && ((!operand_types
[0].bitfield
.regmmx
3694 && !operand_types
[0].bitfield
.regxmm
)
3695 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3696 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3699 /* Do not verify operands when there are none. */
3703 /* We've found a match; break out of loop. */
3707 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3708 into Disp32/Disp16/Disp32 operand. */
3709 if (i
.prefix
[ADDR_PREFIX
] != 0)
3711 /* There should be only one Disp operand. */
3715 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3717 if (operand_types
[j
].bitfield
.disp16
)
3719 addr_prefix_disp
= j
;
3720 operand_types
[j
].bitfield
.disp32
= 1;
3721 operand_types
[j
].bitfield
.disp16
= 0;
3727 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3729 if (operand_types
[j
].bitfield
.disp32
)
3731 addr_prefix_disp
= j
;
3732 operand_types
[j
].bitfield
.disp32
= 0;
3733 operand_types
[j
].bitfield
.disp16
= 1;
3739 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3741 if (operand_types
[j
].bitfield
.disp64
)
3743 addr_prefix_disp
= j
;
3744 operand_types
[j
].bitfield
.disp64
= 0;
3745 operand_types
[j
].bitfield
.disp32
= 1;
3753 /* We check register size only if size of operands can be
3754 encoded the canonical way. */
3755 check_register
= t
->opcode_modifier
.w
;
3756 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3757 switch (t
->operands
)
3760 if (!operand_type_match (overlap0
, i
.types
[0]))
3764 /* xchg %eax, %eax is a special case. It is an aliase for nop
3765 only in 32bit mode and we can use opcode 0x90. In 64bit
3766 mode, we can't use 0x90 for xchg %eax, %eax since it should
3767 zero-extend %eax to %rax. */
3768 if (flag_code
== CODE_64BIT
3769 && t
->base_opcode
== 0x90
3770 && operand_type_equal (&i
.types
[0], &acc32
)
3771 && operand_type_equal (&i
.types
[1], &acc32
))
3775 /* If we swap operand in encoding, we either match
3776 the next one or reverse direction of operands. */
3777 if (t
->opcode_modifier
.s
)
3779 else if (t
->opcode_modifier
.d
)
3784 /* If we swap operand in encoding, we match the next one. */
3785 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3789 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3790 if (!operand_type_match (overlap0
, i
.types
[0])
3791 || !operand_type_match (overlap1
, i
.types
[1])
3793 && !operand_type_register_match (overlap0
, i
.types
[0],
3795 overlap1
, i
.types
[1],
3798 /* Check if other direction is valid ... */
3799 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3803 /* Try reversing direction of operands. */
3804 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3805 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3806 if (!operand_type_match (overlap0
, i
.types
[0])
3807 || !operand_type_match (overlap1
, i
.types
[1])
3809 && !operand_type_register_match (overlap0
,
3816 /* Does not match either direction. */
3819 /* found_reverse_match holds which of D or FloatDR
3821 if (t
->opcode_modifier
.d
)
3822 found_reverse_match
= Opcode_D
;
3823 else if (t
->opcode_modifier
.floatd
)
3824 found_reverse_match
= Opcode_FloatD
;
3826 found_reverse_match
= 0;
3827 if (t
->opcode_modifier
.floatr
)
3828 found_reverse_match
|= Opcode_FloatR
;
3832 /* Found a forward 2 operand match here. */
3833 switch (t
->operands
)
3836 overlap4
= operand_type_and (i
.types
[4],
3839 overlap3
= operand_type_and (i
.types
[3],
3842 overlap2
= operand_type_and (i
.types
[2],
3847 switch (t
->operands
)
3850 if (!operand_type_match (overlap4
, i
.types
[4])
3851 || !operand_type_register_match (overlap3
,
3859 if (!operand_type_match (overlap3
, i
.types
[3])
3861 && !operand_type_register_match (overlap2
,
3869 /* Here we make use of the fact that there are no
3870 reverse match 3 operand instructions, and all 3
3871 operand instructions only need to be checked for
3872 register consistency between operands 2 and 3. */
3873 if (!operand_type_match (overlap2
, i
.types
[2])
3875 && !operand_type_register_match (overlap1
,
3885 /* Found either forward/reverse 2, 3 or 4 operand match here:
3886 slip through to break. */
3888 if (!found_cpu_match
)
3890 found_reverse_match
= 0;
3894 /* We've found a match; break out of loop. */
3898 if (t
== current_templates
->end
)
3900 /* We found no match. */
3902 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3903 current_templates
->start
->name
);
3905 as_bad (_("suffix or operands invalid for `%s'"),
3906 current_templates
->start
->name
);
3910 if (!quiet_warnings
)
3913 && (i
.types
[0].bitfield
.jumpabsolute
3914 != operand_types
[0].bitfield
.jumpabsolute
))
3916 as_warn (_("indirect %s without `*'"), t
->name
);
3919 if (t
->opcode_modifier
.isprefix
3920 && t
->opcode_modifier
.ignoresize
)
3922 /* Warn them that a data or address size prefix doesn't
3923 affect assembly of the next line of code. */
3924 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3928 /* Copy the template we found. */
3931 if (addr_prefix_disp
!= -1)
3932 i
.tm
.operand_types
[addr_prefix_disp
]
3933 = operand_types
[addr_prefix_disp
];
3935 if (found_reverse_match
)
3937 /* If we found a reverse match we must alter the opcode
3938 direction bit. found_reverse_match holds bits to change
3939 (different for int & float insns). */
3941 i
.tm
.base_opcode
^= found_reverse_match
;
3943 i
.tm
.operand_types
[0] = operand_types
[1];
3944 i
.tm
.operand_types
[1] = operand_types
[0];
3953 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3954 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3956 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3958 as_bad (_("`%s' operand %d must use `%ses' segment"),
3964 /* There's only ever one segment override allowed per instruction.
3965 This instruction possibly has a legal segment override on the
3966 second operand, so copy the segment to where non-string
3967 instructions store it, allowing common code. */
3968 i
.seg
[0] = i
.seg
[1];
3970 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3972 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3974 as_bad (_("`%s' operand %d must use `%ses' segment"),
3985 process_suffix (void)
3987 /* If matched instruction specifies an explicit instruction mnemonic
3989 if (i
.tm
.opcode_modifier
.size16
)
3990 i
.suffix
= WORD_MNEM_SUFFIX
;
3991 else if (i
.tm
.opcode_modifier
.size32
)
3992 i
.suffix
= LONG_MNEM_SUFFIX
;
3993 else if (i
.tm
.opcode_modifier
.size64
)
3994 i
.suffix
= QWORD_MNEM_SUFFIX
;
3995 else if (i
.reg_operands
)
3997 /* If there's no instruction mnemonic suffix we try to invent one
3998 based on register operands. */
4001 /* We take i.suffix from the last register operand specified,
4002 Destination register type is more significant than source
4003 register type. crc32 in SSE4.2 prefers source register
4005 if (i
.tm
.base_opcode
== 0xf20f38f1)
4007 if (i
.types
[0].bitfield
.reg16
)
4008 i
.suffix
= WORD_MNEM_SUFFIX
;
4009 else if (i
.types
[0].bitfield
.reg32
)
4010 i
.suffix
= LONG_MNEM_SUFFIX
;
4011 else if (i
.types
[0].bitfield
.reg64
)
4012 i
.suffix
= QWORD_MNEM_SUFFIX
;
4014 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4016 if (i
.types
[0].bitfield
.reg8
)
4017 i
.suffix
= BYTE_MNEM_SUFFIX
;
4024 if (i
.tm
.base_opcode
== 0xf20f38f1
4025 || i
.tm
.base_opcode
== 0xf20f38f0)
4027 /* We have to know the operand size for crc32. */
4028 as_bad (_("ambiguous memory operand size for `%s`"),
4033 for (op
= i
.operands
; --op
>= 0;)
4034 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4036 if (i
.types
[op
].bitfield
.reg8
)
4038 i
.suffix
= BYTE_MNEM_SUFFIX
;
4041 else if (i
.types
[op
].bitfield
.reg16
)
4043 i
.suffix
= WORD_MNEM_SUFFIX
;
4046 else if (i
.types
[op
].bitfield
.reg32
)
4048 i
.suffix
= LONG_MNEM_SUFFIX
;
4051 else if (i
.types
[op
].bitfield
.reg64
)
4053 i
.suffix
= QWORD_MNEM_SUFFIX
;
4059 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4061 if (!check_byte_reg ())
4064 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4066 if (!check_long_reg ())
4069 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4072 && i
.tm
.opcode_modifier
.ignoresize
4073 && i
.tm
.opcode_modifier
.no_qsuf
)
4075 else if (!check_qword_reg ())
4078 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4080 if (!check_word_reg ())
4083 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4084 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4086 /* Skip if the instruction has x/y suffix. match_template
4087 should check if it is a valid suffix. */
4089 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4090 /* Do nothing if the instruction is going to ignore the prefix. */
4095 else if (i
.tm
.opcode_modifier
.defaultsize
4097 /* exclude fldenv/frstor/fsave/fstenv */
4098 && i
.tm
.opcode_modifier
.no_ssuf
)
4100 i
.suffix
= stackop_size
;
4102 else if (intel_syntax
4104 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4105 || i
.tm
.opcode_modifier
.jumpbyte
4106 || i
.tm
.opcode_modifier
.jumpintersegment
4107 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4108 && i
.tm
.extension_opcode
<= 3)))
4113 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4115 i
.suffix
= QWORD_MNEM_SUFFIX
;
4119 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4120 i
.suffix
= LONG_MNEM_SUFFIX
;
4123 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4124 i
.suffix
= WORD_MNEM_SUFFIX
;
4133 if (i
.tm
.opcode_modifier
.w
)
4135 as_bad (_("no instruction mnemonic suffix given and "
4136 "no register operands; can't size instruction"));
4142 unsigned int suffixes
;
4144 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4145 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4147 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4149 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4151 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4153 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4156 /* There are more than suffix matches. */
4157 if (i
.tm
.opcode_modifier
.w
4158 || ((suffixes
& (suffixes
- 1))
4159 && !i
.tm
.opcode_modifier
.defaultsize
4160 && !i
.tm
.opcode_modifier
.ignoresize
))
4162 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4168 /* Change the opcode based on the operand size given by i.suffix;
4169 We don't need to change things for byte insns. */
4172 && i
.suffix
!= BYTE_MNEM_SUFFIX
4173 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4174 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4176 /* It's not a byte, select word/dword operation. */
4177 if (i
.tm
.opcode_modifier
.w
)
4179 if (i
.tm
.opcode_modifier
.shortform
)
4180 i
.tm
.base_opcode
|= 8;
4182 i
.tm
.base_opcode
|= 1;
4185 /* Now select between word & dword operations via the operand
4186 size prefix, except for instructions that will ignore this
4188 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4190 /* The address size override prefix changes the size of the
4192 if ((flag_code
== CODE_32BIT
4193 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4194 || (flag_code
!= CODE_32BIT
4195 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4196 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4199 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4200 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4201 && !i
.tm
.opcode_modifier
.ignoresize
4202 && !i
.tm
.opcode_modifier
.floatmf
4203 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4204 || (flag_code
== CODE_64BIT
4205 && i
.tm
.opcode_modifier
.jumpbyte
)))
4207 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4209 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4210 prefix
= ADDR_PREFIX_OPCODE
;
4212 if (!add_prefix (prefix
))
4216 /* Set mode64 for an operand. */
4217 if (i
.suffix
== QWORD_MNEM_SUFFIX
4218 && flag_code
== CODE_64BIT
4219 && !i
.tm
.opcode_modifier
.norex64
)
4221 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4222 need rex64. cmpxchg8b is also a special case. */
4223 if (! (i
.operands
== 2
4224 && i
.tm
.base_opcode
== 0x90
4225 && i
.tm
.extension_opcode
== None
4226 && operand_type_equal (&i
.types
[0], &acc64
)
4227 && operand_type_equal (&i
.types
[1], &acc64
))
4228 && ! (i
.operands
== 1
4229 && i
.tm
.base_opcode
== 0xfc7
4230 && i
.tm
.extension_opcode
== 1
4231 && !operand_type_check (i
.types
[0], reg
)
4232 && operand_type_check (i
.types
[0], anymem
)))
4236 /* Size floating point instruction. */
4237 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4238 if (i
.tm
.opcode_modifier
.floatmf
)
4239 i
.tm
.base_opcode
^= 4;
4246 check_byte_reg (void)
4250 for (op
= i
.operands
; --op
>= 0;)
4252 /* If this is an eight bit register, it's OK. If it's the 16 or
4253 32 bit version of an eight bit register, we will just use the
4254 low portion, and that's OK too. */
4255 if (i
.types
[op
].bitfield
.reg8
)
4258 /* Don't generate this warning if not needed. */
4259 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4262 /* crc32 doesn't generate this warning. */
4263 if (i
.tm
.base_opcode
== 0xf20f38f0)
4266 if ((i
.types
[op
].bitfield
.reg16
4267 || i
.types
[op
].bitfield
.reg32
4268 || i
.types
[op
].bitfield
.reg64
)
4269 && i
.op
[op
].regs
->reg_num
< 4)
4271 /* Prohibit these changes in the 64bit mode, since the
4272 lowering is more complicated. */
4273 if (flag_code
== CODE_64BIT
4274 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4276 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4277 register_prefix
, i
.op
[op
].regs
->reg_name
,
4281 #if REGISTER_WARNINGS
4283 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4284 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4286 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4287 ? REGNAM_AL
- REGNAM_AX
4288 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4290 i
.op
[op
].regs
->reg_name
,
4295 /* Any other register is bad. */
4296 if (i
.types
[op
].bitfield
.reg16
4297 || i
.types
[op
].bitfield
.reg32
4298 || i
.types
[op
].bitfield
.reg64
4299 || i
.types
[op
].bitfield
.regmmx
4300 || i
.types
[op
].bitfield
.regxmm
4301 || i
.types
[op
].bitfield
.regymm
4302 || i
.types
[op
].bitfield
.sreg2
4303 || i
.types
[op
].bitfield
.sreg3
4304 || i
.types
[op
].bitfield
.control
4305 || i
.types
[op
].bitfield
.debug
4306 || i
.types
[op
].bitfield
.test
4307 || i
.types
[op
].bitfield
.floatreg
4308 || i
.types
[op
].bitfield
.floatacc
)
4310 as_bad (_("`%s%s' not allowed with `%s%c'"),
4312 i
.op
[op
].regs
->reg_name
,
4322 check_long_reg (void)
4326 for (op
= i
.operands
; --op
>= 0;)
4327 /* Reject eight bit registers, except where the template requires
4328 them. (eg. movzb) */
4329 if (i
.types
[op
].bitfield
.reg8
4330 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4331 || i
.tm
.operand_types
[op
].bitfield
.reg32
4332 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4334 as_bad (_("`%s%s' not allowed with `%s%c'"),
4336 i
.op
[op
].regs
->reg_name
,
4341 /* Warn if the e prefix on a general reg is missing. */
4342 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4343 && i
.types
[op
].bitfield
.reg16
4344 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4345 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4347 /* Prohibit these changes in the 64bit mode, since the
4348 lowering is more complicated. */
4349 if (flag_code
== CODE_64BIT
)
4351 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4352 register_prefix
, i
.op
[op
].regs
->reg_name
,
4356 #if REGISTER_WARNINGS
4358 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4360 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4362 i
.op
[op
].regs
->reg_name
,
4366 /* Warn if the r prefix on a general reg is missing. */
4367 else if (i
.types
[op
].bitfield
.reg64
4368 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4369 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4372 && i
.tm
.opcode_modifier
.toqword
4373 && !i
.types
[0].bitfield
.regxmm
)
4375 /* Convert to QWORD. We want REX byte. */
4376 i
.suffix
= QWORD_MNEM_SUFFIX
;
4380 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4381 register_prefix
, i
.op
[op
].regs
->reg_name
,
4390 check_qword_reg (void)
4394 for (op
= i
.operands
; --op
>= 0; )
4395 /* Reject eight bit registers, except where the template requires
4396 them. (eg. movzb) */
4397 if (i
.types
[op
].bitfield
.reg8
4398 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4399 || i
.tm
.operand_types
[op
].bitfield
.reg32
4400 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4402 as_bad (_("`%s%s' not allowed with `%s%c'"),
4404 i
.op
[op
].regs
->reg_name
,
4409 /* Warn if the e prefix on a general reg is missing. */
4410 else if ((i
.types
[op
].bitfield
.reg16
4411 || i
.types
[op
].bitfield
.reg32
)
4412 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4413 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4415 /* Prohibit these changes in the 64bit mode, since the
4416 lowering is more complicated. */
4418 && i
.tm
.opcode_modifier
.todword
4419 && !i
.types
[0].bitfield
.regxmm
)
4421 /* Convert to DWORD. We don't want REX byte. */
4422 i
.suffix
= LONG_MNEM_SUFFIX
;
4426 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4427 register_prefix
, i
.op
[op
].regs
->reg_name
,
4436 check_word_reg (void)
4439 for (op
= i
.operands
; --op
>= 0;)
4440 /* Reject eight bit registers, except where the template requires
4441 them. (eg. movzb) */
4442 if (i
.types
[op
].bitfield
.reg8
4443 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4444 || i
.tm
.operand_types
[op
].bitfield
.reg32
4445 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4447 as_bad (_("`%s%s' not allowed with `%s%c'"),
4449 i
.op
[op
].regs
->reg_name
,
4454 /* Warn if the e prefix on a general reg is present. */
4455 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4456 && i
.types
[op
].bitfield
.reg32
4457 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4458 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4460 /* Prohibit these changes in the 64bit mode, since the
4461 lowering is more complicated. */
4462 if (flag_code
== CODE_64BIT
)
4464 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4465 register_prefix
, i
.op
[op
].regs
->reg_name
,
4470 #if REGISTER_WARNINGS
4471 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4473 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4475 i
.op
[op
].regs
->reg_name
,
4483 update_imm (unsigned int j
)
4485 i386_operand_type overlap
= i
.types
[j
];
4486 if ((overlap
.bitfield
.imm8
4487 || overlap
.bitfield
.imm8s
4488 || overlap
.bitfield
.imm16
4489 || overlap
.bitfield
.imm32
4490 || overlap
.bitfield
.imm32s
4491 || overlap
.bitfield
.imm64
)
4492 && !operand_type_equal (&overlap
, &imm8
)
4493 && !operand_type_equal (&overlap
, &imm8s
)
4494 && !operand_type_equal (&overlap
, &imm16
)
4495 && !operand_type_equal (&overlap
, &imm32
)
4496 && !operand_type_equal (&overlap
, &imm32s
)
4497 && !operand_type_equal (&overlap
, &imm64
))
4501 i386_operand_type temp
;
4503 operand_type_set (&temp
, 0);
4504 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4506 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4507 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4509 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4510 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4511 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4513 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4514 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4517 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4520 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4521 || operand_type_equal (&overlap
, &imm16_32
)
4522 || operand_type_equal (&overlap
, &imm16_32s
))
4524 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4529 if (!operand_type_equal (&overlap
, &imm8
)
4530 && !operand_type_equal (&overlap
, &imm8s
)
4531 && !operand_type_equal (&overlap
, &imm16
)
4532 && !operand_type_equal (&overlap
, &imm32
)
4533 && !operand_type_equal (&overlap
, &imm32s
)
4534 && !operand_type_equal (&overlap
, &imm64
))
4536 as_bad (_("no instruction mnemonic suffix given; "
4537 "can't determine immediate size"));
4541 i
.types
[j
] = overlap
;
4551 /* Update the first 2 immediate operands. */
4552 n
= i
.operands
> 2 ? 2 : i
.operands
;
4555 for (j
= 0; j
< n
; j
++)
4556 if (update_imm (j
) == 0)
4559 /* The 3rd operand can't be immediate operand. */
4560 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4567 bad_implicit_operand (int xmm
)
4569 const char *reg
= xmm
? "xmm0" : "ymm0";
4571 as_bad (_("the last operand of `%s' must be `%s%s'"),
4572 i
.tm
.name
, register_prefix
, reg
);
4574 as_bad (_("the first operand of `%s' must be `%s%s'"),
4575 i
.tm
.name
, register_prefix
, reg
);
4580 process_operands (void)
4582 /* Default segment register this instruction will use for memory
4583 accesses. 0 means unknown. This is only for optimizing out
4584 unnecessary segment overrides. */
4585 const seg_entry
*default_seg
= 0;
4587 if (i
.tm
.opcode_modifier
.sse2avx
4588 && (i
.tm
.opcode_modifier
.vexnds
4589 || i
.tm
.opcode_modifier
.vexndd
))
4591 unsigned int dup
= i
.operands
;
4592 unsigned int dest
= dup
- 1;
4595 /* The destination must be an xmm register. */
4596 gas_assert (i
.reg_operands
4597 && MAX_OPERANDS
> dup
4598 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4600 if (i
.tm
.opcode_modifier
.firstxmm0
)
4602 /* The first operand is implicit and must be xmm0. */
4603 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4604 if (i
.op
[0].regs
->reg_num
!= 0)
4605 return bad_implicit_operand (1);
4607 if (i
.tm
.opcode_modifier
.vex3sources
)
4609 /* Keep xmm0 for instructions with VEX prefix and 3
4615 /* We remove the first xmm0 and keep the number of
4616 operands unchanged, which in fact duplicates the
4618 for (j
= 1; j
< i
.operands
; j
++)
4620 i
.op
[j
- 1] = i
.op
[j
];
4621 i
.types
[j
- 1] = i
.types
[j
];
4622 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4626 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4628 gas_assert ((MAX_OPERANDS
- 1) > dup
4629 && i
.tm
.opcode_modifier
.vex3sources
);
4631 /* Add the implicit xmm0 for instructions with VEX prefix
4633 for (j
= i
.operands
; j
> 0; j
--)
4635 i
.op
[j
] = i
.op
[j
- 1];
4636 i
.types
[j
] = i
.types
[j
- 1];
4637 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4640 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4641 i
.types
[0] = regxmm
;
4642 i
.tm
.operand_types
[0] = regxmm
;
4645 i
.reg_operands
+= 2;
4650 i
.op
[dup
] = i
.op
[dest
];
4651 i
.types
[dup
] = i
.types
[dest
];
4652 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4661 i
.op
[dup
] = i
.op
[dest
];
4662 i
.types
[dup
] = i
.types
[dest
];
4663 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4666 if (i
.tm
.opcode_modifier
.immext
)
4669 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4673 /* The first operand is implicit and must be xmm0/ymm0. */
4674 gas_assert (i
.reg_operands
4675 && (operand_type_equal (&i
.types
[0], ®xmm
)
4676 || operand_type_equal (&i
.types
[0], ®ymm
)));
4677 if (i
.op
[0].regs
->reg_num
!= 0)
4678 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4680 for (j
= 1; j
< i
.operands
; j
++)
4682 i
.op
[j
- 1] = i
.op
[j
];
4683 i
.types
[j
- 1] = i
.types
[j
];
4685 /* We need to adjust fields in i.tm since they are used by
4686 build_modrm_byte. */
4687 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4694 else if (i
.tm
.opcode_modifier
.regkludge
)
4696 /* The imul $imm, %reg instruction is converted into
4697 imul $imm, %reg, %reg, and the clr %reg instruction
4698 is converted into xor %reg, %reg. */
4700 unsigned int first_reg_op
;
4702 if (operand_type_check (i
.types
[0], reg
))
4706 /* Pretend we saw the extra register operand. */
4707 gas_assert (i
.reg_operands
== 1
4708 && i
.op
[first_reg_op
+ 1].regs
== 0);
4709 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4710 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4715 if (i
.tm
.opcode_modifier
.shortform
)
4717 if (i
.types
[0].bitfield
.sreg2
4718 || i
.types
[0].bitfield
.sreg3
)
4720 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4721 && i
.op
[0].regs
->reg_num
== 1)
4723 as_bad (_("you can't `pop %scs'"), register_prefix
);
4726 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4727 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4732 /* The register or float register operand is in operand
4736 if (i
.types
[0].bitfield
.floatreg
4737 || operand_type_check (i
.types
[0], reg
))
4741 /* Register goes in low 3 bits of opcode. */
4742 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4743 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4745 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4747 /* Warn about some common errors, but press on regardless.
4748 The first case can be generated by gcc (<= 2.8.1). */
4749 if (i
.operands
== 2)
4751 /* Reversed arguments on faddp, fsubp, etc. */
4752 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4753 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4754 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4758 /* Extraneous `l' suffix on fp insn. */
4759 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4760 register_prefix
, i
.op
[0].regs
->reg_name
);
4765 else if (i
.tm
.opcode_modifier
.modrm
)
4767 /* The opcode is completed (modulo i.tm.extension_opcode which
4768 must be put into the modrm byte). Now, we make the modrm and
4769 index base bytes based on all the info we've collected. */
4771 default_seg
= build_modrm_byte ();
4773 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4777 else if (i
.tm
.opcode_modifier
.isstring
)
4779 /* For the string instructions that allow a segment override
4780 on one of their operands, the default segment is ds. */
4784 if (i
.tm
.base_opcode
== 0x8d /* lea */
4787 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4789 /* If a segment was explicitly specified, and the specified segment
4790 is not the default, use an opcode prefix to select it. If we
4791 never figured out what the default segment is, then default_seg
4792 will be zero at this point, and the specified segment prefix will
4794 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4796 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4802 static const seg_entry
*
4803 build_modrm_byte (void)
4805 const seg_entry
*default_seg
= 0;
4806 unsigned int source
, dest
;
4809 /* The first operand of instructions with VEX prefix and 3 sources
4810 must be VEX_Imm4. */
4811 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4814 unsigned int nds
, reg
;
4816 if (i
.tm
.opcode_modifier
.veximmext
4817 && i
.tm
.opcode_modifier
.immext
)
4819 dest
= i
.operands
- 2;
4820 gas_assert (dest
== 3);
4823 dest
= i
.operands
- 1;
4826 /* This instruction must have 4 register operands
4827 or 3 register operands plus 1 memory operand.
4828 It must have VexNDS and VexImmExt. */
4829 gas_assert ((i
.reg_operands
== 4
4830 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4831 && i
.tm
.opcode_modifier
.vexnds
4832 && i
.tm
.opcode_modifier
.veximmext
4833 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4834 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4836 /* Generate an 8bit immediate operand to encode the register
4838 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4839 i
.op
[i
.operands
].imms
= exp
;
4840 i
.types
[i
.operands
] = imm8
;
4842 /* If VexW1 is set, the first operand is the source and
4843 the second operand is encoded in the immediate operand. */
4844 if (i
.tm
.opcode_modifier
.vexw1
)
4854 /* FMA4 swaps REG and NDS. */
4855 if (i
.tm
.cpu_flags
.bitfield
.cpufma4
)
4862 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4863 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4865 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4866 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4868 exp
->X_op
= O_constant
;
4870 = ((i
.op
[reg
].regs
->reg_num
4871 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4872 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4877 /* i.reg_operands MUST be the number of real register operands;
4878 implicit registers do not count. If there are 3 register
4879 operands, it must be a instruction with VexNDS. For a
4880 instruction with VexNDD, the destination register is encoded
4881 in VEX prefix. If there are 4 register operands, it must be
4882 a instruction with VEX prefix and 3 sources. */
4883 if (i
.mem_operands
== 0
4884 && ((i
.reg_operands
== 2
4885 && !i
.tm
.opcode_modifier
.vexndd
)
4886 || (i
.reg_operands
== 3
4887 && i
.tm
.opcode_modifier
.vexnds
)
4888 || (i
.reg_operands
== 4 && vex_3_sources
)))
4896 /* When there are 3 operands, one of them may be immediate,
4897 which may be the first or the last operand. Otherwise,
4898 the first operand must be shift count register (cl) or it
4899 is an instruction with VexNDS. */
4900 gas_assert (i
.imm_operands
== 1
4901 || (i
.imm_operands
== 0
4902 && (i
.tm
.opcode_modifier
.vexnds
4903 || i
.types
[0].bitfield
.shiftcount
)));
4904 if (operand_type_check (i
.types
[0], imm
)
4905 || i
.types
[0].bitfield
.shiftcount
)
4911 /* When there are 4 operands, the first two must be 8bit
4912 immediate operands. The source operand will be the 3rd
4915 For instructions with VexNDS, if the first operand
4916 an imm8, the source operand is the 2nd one. If the last
4917 operand is imm8, the source operand is the first one. */
4918 gas_assert ((i
.imm_operands
== 2
4919 && i
.types
[0].bitfield
.imm8
4920 && i
.types
[1].bitfield
.imm8
)
4921 || (i
.tm
.opcode_modifier
.vexnds
4922 && i
.imm_operands
== 1
4923 && (i
.types
[0].bitfield
.imm8
4924 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4925 if (i
.tm
.opcode_modifier
.vexnds
)
4927 if (i
.types
[0].bitfield
.imm8
)
4945 if (i
.tm
.opcode_modifier
.vexnds
)
4947 /* For instructions with VexNDS, the register-only
4948 source operand must be XMM or YMM register. It is
4949 encoded in VEX prefix. We need to clear RegMem bit
4950 before calling operand_type_equal. */
4951 i386_operand_type op
= i
.tm
.operand_types
[dest
];
4952 op
.bitfield
.regmem
= 0;
4953 if ((dest
+ 1) >= i
.operands
4954 || (!operand_type_equal (&op
, ®xmm
)
4955 && !operand_type_equal (&op
, ®ymm
)))
4957 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
4963 /* One of the register operands will be encoded in the i.tm.reg
4964 field, the other in the combined i.tm.mode and i.tm.regmem
4965 fields. If no form of this instruction supports a memory
4966 destination operand, then we assume the source operand may
4967 sometimes be a memory operand and so we need to store the
4968 destination in the i.rm.reg field. */
4969 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4970 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4972 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4973 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4974 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4976 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4981 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4982 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4983 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4985 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4988 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4990 if (!i
.types
[0].bitfield
.control
4991 && !i
.types
[1].bitfield
.control
)
4993 i
.rex
&= ~(REX_R
| REX_B
);
4994 add_prefix (LOCK_PREFIX_OPCODE
);
4998 { /* If it's not 2 reg operands... */
5003 unsigned int fake_zero_displacement
= 0;
5006 for (op
= 0; op
< i
.operands
; op
++)
5007 if (operand_type_check (i
.types
[op
], anymem
))
5009 gas_assert (op
< i
.operands
);
5013 if (i
.base_reg
== 0)
5016 if (!i
.disp_operands
)
5017 fake_zero_displacement
= 1;
5018 if (i
.index_reg
== 0)
5020 /* Operand is just <disp> */
5021 if (flag_code
== CODE_64BIT
)
5023 /* 64bit mode overwrites the 32bit absolute
5024 addressing by RIP relative addressing and
5025 absolute addressing is encoded by one of the
5026 redundant SIB forms. */
5027 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5028 i
.sib
.base
= NO_BASE_REGISTER
;
5029 i
.sib
.index
= NO_INDEX_REGISTER
;
5030 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5031 ? disp32s
: disp32
);
5033 else if ((flag_code
== CODE_16BIT
)
5034 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5036 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5037 i
.types
[op
] = disp16
;
5041 i
.rm
.regmem
= NO_BASE_REGISTER
;
5042 i
.types
[op
] = disp32
;
5045 else /* !i.base_reg && i.index_reg */
5047 if (i
.index_reg
->reg_num
== RegEiz
5048 || i
.index_reg
->reg_num
== RegRiz
)
5049 i
.sib
.index
= NO_INDEX_REGISTER
;
5051 i
.sib
.index
= i
.index_reg
->reg_num
;
5052 i
.sib
.base
= NO_BASE_REGISTER
;
5053 i
.sib
.scale
= i
.log2_scale_factor
;
5054 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5055 i
.types
[op
].bitfield
.disp8
= 0;
5056 i
.types
[op
].bitfield
.disp16
= 0;
5057 i
.types
[op
].bitfield
.disp64
= 0;
5058 if (flag_code
!= CODE_64BIT
)
5060 /* Must be 32 bit */
5061 i
.types
[op
].bitfield
.disp32
= 1;
5062 i
.types
[op
].bitfield
.disp32s
= 0;
5066 i
.types
[op
].bitfield
.disp32
= 0;
5067 i
.types
[op
].bitfield
.disp32s
= 1;
5069 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5073 /* RIP addressing for 64bit mode. */
5074 else if (i
.base_reg
->reg_num
== RegRip
||
5075 i
.base_reg
->reg_num
== RegEip
)
5077 i
.rm
.regmem
= NO_BASE_REGISTER
;
5078 i
.types
[op
].bitfield
.disp8
= 0;
5079 i
.types
[op
].bitfield
.disp16
= 0;
5080 i
.types
[op
].bitfield
.disp32
= 0;
5081 i
.types
[op
].bitfield
.disp32s
= 1;
5082 i
.types
[op
].bitfield
.disp64
= 0;
5083 i
.flags
[op
] |= Operand_PCrel
;
5084 if (! i
.disp_operands
)
5085 fake_zero_displacement
= 1;
5087 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5089 switch (i
.base_reg
->reg_num
)
5092 if (i
.index_reg
== 0)
5094 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5095 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5099 if (i
.index_reg
== 0)
5102 if (operand_type_check (i
.types
[op
], disp
) == 0)
5104 /* fake (%bp) into 0(%bp) */
5105 i
.types
[op
].bitfield
.disp8
= 1;
5106 fake_zero_displacement
= 1;
5109 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5110 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5112 default: /* (%si) -> 4 or (%di) -> 5 */
5113 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5115 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5117 else /* i.base_reg and 32/64 bit mode */
5119 if (flag_code
== CODE_64BIT
5120 && operand_type_check (i
.types
[op
], disp
))
5122 i386_operand_type temp
;
5123 operand_type_set (&temp
, 0);
5124 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5126 if (i
.prefix
[ADDR_PREFIX
] == 0)
5127 i
.types
[op
].bitfield
.disp32s
= 1;
5129 i
.types
[op
].bitfield
.disp32
= 1;
5132 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5133 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5135 i
.sib
.base
= i
.base_reg
->reg_num
;
5136 /* x86-64 ignores REX prefix bit here to avoid decoder
5138 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5141 if (i
.disp_operands
== 0)
5143 fake_zero_displacement
= 1;
5144 i
.types
[op
].bitfield
.disp8
= 1;
5147 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5151 i
.sib
.scale
= i
.log2_scale_factor
;
5152 if (i
.index_reg
== 0)
5154 /* <disp>(%esp) becomes two byte modrm with no index
5155 register. We've already stored the code for esp
5156 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5157 Any base register besides %esp will not use the
5158 extra modrm byte. */
5159 i
.sib
.index
= NO_INDEX_REGISTER
;
5163 if (i
.index_reg
->reg_num
== RegEiz
5164 || i
.index_reg
->reg_num
== RegRiz
)
5165 i
.sib
.index
= NO_INDEX_REGISTER
;
5167 i
.sib
.index
= i
.index_reg
->reg_num
;
5168 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5169 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5174 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5175 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5178 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5181 if (fake_zero_displacement
)
5183 /* Fakes a zero displacement assuming that i.types[op]
5184 holds the correct displacement size. */
5187 gas_assert (i
.op
[op
].disps
== 0);
5188 exp
= &disp_expressions
[i
.disp_operands
++];
5189 i
.op
[op
].disps
= exp
;
5190 exp
->X_op
= O_constant
;
5191 exp
->X_add_number
= 0;
5192 exp
->X_add_symbol
= (symbolS
*) 0;
5193 exp
->X_op_symbol
= (symbolS
*) 0;
5201 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5202 (if any) based on i.tm.extension_opcode. Again, we must be
5203 careful to make sure that segment/control/debug/test/MMX
5204 registers are coded into the i.rm.reg field. */
5208 unsigned int vex_reg
= ~0;
5210 for (op
= 0; op
< i
.operands
; op
++)
5211 if (i
.types
[op
].bitfield
.reg8
5212 || i
.types
[op
].bitfield
.reg16
5213 || i
.types
[op
].bitfield
.reg32
5214 || i
.types
[op
].bitfield
.reg64
5215 || i
.types
[op
].bitfield
.regmmx
5216 || i
.types
[op
].bitfield
.regxmm
5217 || i
.types
[op
].bitfield
.regymm
5218 || i
.types
[op
].bitfield
.sreg2
5219 || i
.types
[op
].bitfield
.sreg3
5220 || i
.types
[op
].bitfield
.control
5221 || i
.types
[op
].bitfield
.debug
5222 || i
.types
[op
].bitfield
.test
)
5227 else if (i
.tm
.opcode_modifier
.vexnds
)
5229 /* For instructions with VexNDS, the register-only
5230 source operand is encoded in VEX prefix. */
5231 gas_assert (mem
!= (unsigned int) ~0);
5236 gas_assert (op
< i
.operands
);
5241 gas_assert (vex_reg
< i
.operands
);
5244 else if (i
.tm
.opcode_modifier
.vexndd
)
5246 /* For instructions with VexNDD, there should be
5247 no memory operand and the register destination
5248 is encoded in VEX prefix. */
5249 gas_assert (i
.mem_operands
== 0
5250 && (op
+ 2) == i
.operands
);
5254 gas_assert (op
< i
.operands
);
5256 if (vex_reg
!= (unsigned int) ~0)
5258 gas_assert (i
.reg_operands
== 2);
5260 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5262 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5265 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5268 /* If there is an extension opcode to put here, the
5269 register number must be put into the regmem field. */
5270 if (i
.tm
.extension_opcode
!= None
)
5272 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5273 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5278 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5279 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5283 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5284 must set it to 3 to indicate this is a register operand
5285 in the regmem field. */
5286 if (!i
.mem_operands
)
5290 /* Fill in i.rm.reg field with extension opcode (if any). */
5291 if (i
.tm
.extension_opcode
!= None
)
5292 i
.rm
.reg
= i
.tm
.extension_opcode
;
5298 output_branch (void)
5303 relax_substateT subtype
;
5308 if (flag_code
== CODE_16BIT
)
5312 if (i
.prefix
[DATA_PREFIX
] != 0)
5318 /* Pentium4 branch hints. */
5319 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5320 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5325 if (i
.prefix
[REX_PREFIX
] != 0)
5331 if (i
.prefixes
!= 0 && !intel_syntax
)
5332 as_warn (_("skipping prefixes on this instruction"));
5334 /* It's always a symbol; End frag & setup for relax.
5335 Make sure there is enough room in this frag for the largest
5336 instruction we may generate in md_convert_frag. This is 2
5337 bytes for the opcode and room for the prefix and largest
5339 frag_grow (prefix
+ 2 + 4);
5340 /* Prefix and 1 opcode byte go in fr_fix. */
5341 p
= frag_more (prefix
+ 1);
5342 if (i
.prefix
[DATA_PREFIX
] != 0)
5343 *p
++ = DATA_PREFIX_OPCODE
;
5344 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5345 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5346 *p
++ = i
.prefix
[SEG_PREFIX
];
5347 if (i
.prefix
[REX_PREFIX
] != 0)
5348 *p
++ = i
.prefix
[REX_PREFIX
];
5349 *p
= i
.tm
.base_opcode
;
5351 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5352 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5353 else if (cpu_arch_flags
.bitfield
.cpui386
)
5354 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5356 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5359 sym
= i
.op
[0].disps
->X_add_symbol
;
5360 off
= i
.op
[0].disps
->X_add_number
;
5362 if (i
.op
[0].disps
->X_op
!= O_constant
5363 && i
.op
[0].disps
->X_op
!= O_symbol
)
5365 /* Handle complex expressions. */
5366 sym
= make_expr_symbol (i
.op
[0].disps
);
5370 /* 1 possible extra opcode + 4 byte displacement go in var part.
5371 Pass reloc in fr_var. */
5372 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5382 if (i
.tm
.opcode_modifier
.jumpbyte
)
5384 /* This is a loop or jecxz type instruction. */
5386 if (i
.prefix
[ADDR_PREFIX
] != 0)
5388 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5391 /* Pentium4 branch hints. */
5392 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5393 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5395 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5404 if (flag_code
== CODE_16BIT
)
5407 if (i
.prefix
[DATA_PREFIX
] != 0)
5409 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5419 if (i
.prefix
[REX_PREFIX
] != 0)
5421 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5425 if (i
.prefixes
!= 0 && !intel_syntax
)
5426 as_warn (_("skipping prefixes on this instruction"));
5428 p
= frag_more (1 + size
);
5429 *p
++ = i
.tm
.base_opcode
;
5431 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5432 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5434 /* All jumps handled here are signed, but don't use a signed limit
5435 check for 32 and 16 bit jumps as we want to allow wrap around at
5436 4G and 64k respectively. */
5438 fixP
->fx_signed
= 1;
5442 output_interseg_jump (void)
5450 if (flag_code
== CODE_16BIT
)
5454 if (i
.prefix
[DATA_PREFIX
] != 0)
5460 if (i
.prefix
[REX_PREFIX
] != 0)
5470 if (i
.prefixes
!= 0 && !intel_syntax
)
5471 as_warn (_("skipping prefixes on this instruction"));
5473 /* 1 opcode; 2 segment; offset */
5474 p
= frag_more (prefix
+ 1 + 2 + size
);
5476 if (i
.prefix
[DATA_PREFIX
] != 0)
5477 *p
++ = DATA_PREFIX_OPCODE
;
5479 if (i
.prefix
[REX_PREFIX
] != 0)
5480 *p
++ = i
.prefix
[REX_PREFIX
];
5482 *p
++ = i
.tm
.base_opcode
;
5483 if (i
.op
[1].imms
->X_op
== O_constant
)
5485 offsetT n
= i
.op
[1].imms
->X_add_number
;
5488 && !fits_in_unsigned_word (n
)
5489 && !fits_in_signed_word (n
))
5491 as_bad (_("16-bit jump out of range"));
5494 md_number_to_chars (p
, n
, size
);
5497 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5498 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5499 if (i
.op
[0].imms
->X_op
!= O_constant
)
5500 as_bad (_("can't handle non absolute segment in `%s'"),
5502 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5508 fragS
*insn_start_frag
;
5509 offsetT insn_start_off
;
5511 /* Tie dwarf2 debug info to the address at the start of the insn.
5512 We can't do this after the insn has been output as the current
5513 frag may have been closed off. eg. by frag_var. */
5514 dwarf2_emit_insn (0);
5516 insn_start_frag
= frag_now
;
5517 insn_start_off
= frag_now_fix ();
5520 if (i
.tm
.opcode_modifier
.jump
)
5522 else if (i
.tm
.opcode_modifier
.jumpbyte
5523 || i
.tm
.opcode_modifier
.jumpdword
)
5525 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5526 output_interseg_jump ();
5529 /* Output normal instructions here. */
5533 unsigned int prefix
;
5535 /* Since the VEX prefix contains the implicit prefix, we don't
5536 need the explicit prefix. */
5537 if (!i
.tm
.opcode_modifier
.vex
)
5539 switch (i
.tm
.opcode_length
)
5542 if (i
.tm
.base_opcode
& 0xff000000)
5544 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5549 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5551 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5552 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5555 if (prefix
!= REPE_PREFIX_OPCODE
5556 || (i
.prefix
[LOCKREP_PREFIX
]
5557 != REPE_PREFIX_OPCODE
))
5558 add_prefix (prefix
);
5561 add_prefix (prefix
);
5570 /* The prefix bytes. */
5571 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5573 FRAG_APPEND_1_CHAR (*q
);
5576 if (i
.tm
.opcode_modifier
.vex
)
5578 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5583 /* REX byte is encoded in VEX prefix. */
5587 FRAG_APPEND_1_CHAR (*q
);
5590 /* There should be no other prefixes for instructions
5595 /* Now the VEX prefix. */
5596 p
= frag_more (i
.vex
.length
);
5597 for (j
= 0; j
< i
.vex
.length
; j
++)
5598 p
[j
] = i
.vex
.bytes
[j
];
5601 /* Now the opcode; be careful about word order here! */
5602 if (i
.tm
.opcode_length
== 1)
5604 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5608 switch (i
.tm
.opcode_length
)
5612 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5622 /* Put out high byte first: can't use md_number_to_chars! */
5623 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5624 *p
= i
.tm
.base_opcode
& 0xff;
5627 /* Now the modrm byte and sib byte (if present). */
5628 if (i
.tm
.opcode_modifier
.modrm
)
5630 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5633 /* If i.rm.regmem == ESP (4)
5634 && i.rm.mode != (Register mode)
5636 ==> need second modrm byte. */
5637 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5639 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5640 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5642 | i
.sib
.scale
<< 6));
5645 if (i
.disp_operands
)
5646 output_disp (insn_start_frag
, insn_start_off
);
5649 output_imm (insn_start_frag
, insn_start_off
);
5655 pi ("" /*line*/, &i
);
5657 #endif /* DEBUG386 */
5660 /* Return the size of the displacement operand N. */
5663 disp_size (unsigned int n
)
5666 if (i
.types
[n
].bitfield
.disp64
)
5668 else if (i
.types
[n
].bitfield
.disp8
)
5670 else if (i
.types
[n
].bitfield
.disp16
)
5675 /* Return the size of the immediate operand N. */
5678 imm_size (unsigned int n
)
5681 if (i
.types
[n
].bitfield
.imm64
)
5683 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5685 else if (i
.types
[n
].bitfield
.imm16
)
5691 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5696 for (n
= 0; n
< i
.operands
; n
++)
5698 if (operand_type_check (i
.types
[n
], disp
))
5700 if (i
.op
[n
].disps
->X_op
== O_constant
)
5702 int size
= disp_size (n
);
5705 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5707 p
= frag_more (size
);
5708 md_number_to_chars (p
, val
, size
);
5712 enum bfd_reloc_code_real reloc_type
;
5713 int size
= disp_size (n
);
5714 int sign
= i
.types
[n
].bitfield
.disp32s
;
5715 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5717 /* We can't have 8 bit displacement here. */
5718 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5720 /* The PC relative address is computed relative
5721 to the instruction boundary, so in case immediate
5722 fields follows, we need to adjust the value. */
5723 if (pcrel
&& i
.imm_operands
)
5728 for (n1
= 0; n1
< i
.operands
; n1
++)
5729 if (operand_type_check (i
.types
[n1
], imm
))
5731 /* Only one immediate is allowed for PC
5732 relative address. */
5733 gas_assert (sz
== 0);
5735 i
.op
[n
].disps
->X_add_number
-= sz
;
5737 /* We should find the immediate. */
5738 gas_assert (sz
!= 0);
5741 p
= frag_more (size
);
5742 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5744 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5745 && (((reloc_type
== BFD_RELOC_32
5746 || reloc_type
== BFD_RELOC_X86_64_32S
5747 || (reloc_type
== BFD_RELOC_64
5749 && (i
.op
[n
].disps
->X_op
== O_symbol
5750 || (i
.op
[n
].disps
->X_op
== O_add
5751 && ((symbol_get_value_expression
5752 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5754 || reloc_type
== BFD_RELOC_32_PCREL
))
5758 if (insn_start_frag
== frag_now
)
5759 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5764 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5765 for (fr
= insn_start_frag
->fr_next
;
5766 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5768 add
+= p
- frag_now
->fr_literal
;
5773 reloc_type
= BFD_RELOC_386_GOTPC
;
5774 i
.op
[n
].imms
->X_add_number
+= add
;
5776 else if (reloc_type
== BFD_RELOC_64
)
5777 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5779 /* Don't do the adjustment for x86-64, as there
5780 the pcrel addressing is relative to the _next_
5781 insn, and that is taken care of in other code. */
5782 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5784 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5785 i
.op
[n
].disps
, pcrel
, reloc_type
);
5792 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5797 for (n
= 0; n
< i
.operands
; n
++)
5799 if (operand_type_check (i
.types
[n
], imm
))
5801 if (i
.op
[n
].imms
->X_op
== O_constant
)
5803 int size
= imm_size (n
);
5806 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5808 p
= frag_more (size
);
5809 md_number_to_chars (p
, val
, size
);
5813 /* Not absolute_section.
5814 Need a 32-bit fixup (don't support 8bit
5815 non-absolute imms). Try to support other
5817 enum bfd_reloc_code_real reloc_type
;
5818 int size
= imm_size (n
);
5821 if (i
.types
[n
].bitfield
.imm32s
5822 && (i
.suffix
== QWORD_MNEM_SUFFIX
5823 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5828 p
= frag_more (size
);
5829 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5831 /* This is tough to explain. We end up with this one if we
5832 * have operands that look like
5833 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5834 * obtain the absolute address of the GOT, and it is strongly
5835 * preferable from a performance point of view to avoid using
5836 * a runtime relocation for this. The actual sequence of
5837 * instructions often look something like:
5842 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5844 * The call and pop essentially return the absolute address
5845 * of the label .L66 and store it in %ebx. The linker itself
5846 * will ultimately change the first operand of the addl so
5847 * that %ebx points to the GOT, but to keep things simple, the
5848 * .o file must have this operand set so that it generates not
5849 * the absolute address of .L66, but the absolute address of
5850 * itself. This allows the linker itself simply treat a GOTPC
5851 * relocation as asking for a pcrel offset to the GOT to be
5852 * added in, and the addend of the relocation is stored in the
5853 * operand field for the instruction itself.
5855 * Our job here is to fix the operand so that it would add
5856 * the correct offset so that %ebx would point to itself. The
5857 * thing that is tricky is that .-.L66 will point to the
5858 * beginning of the instruction, so we need to further modify
5859 * the operand so that it will point to itself. There are
5860 * other cases where you have something like:
5862 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5864 * and here no correction would be required. Internally in
5865 * the assembler we treat operands of this form as not being
5866 * pcrel since the '.' is explicitly mentioned, and I wonder
5867 * whether it would simplify matters to do it this way. Who
5868 * knows. In earlier versions of the PIC patches, the
5869 * pcrel_adjust field was used to store the correction, but
5870 * since the expression is not pcrel, I felt it would be
5871 * confusing to do it this way. */
5873 if ((reloc_type
== BFD_RELOC_32
5874 || reloc_type
== BFD_RELOC_X86_64_32S
5875 || reloc_type
== BFD_RELOC_64
)
5877 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5878 && (i
.op
[n
].imms
->X_op
== O_symbol
5879 || (i
.op
[n
].imms
->X_op
== O_add
5880 && ((symbol_get_value_expression
5881 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5886 if (insn_start_frag
== frag_now
)
5887 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5892 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5893 for (fr
= insn_start_frag
->fr_next
;
5894 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5896 add
+= p
- frag_now
->fr_literal
;
5900 reloc_type
= BFD_RELOC_386_GOTPC
;
5902 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5904 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5905 i
.op
[n
].imms
->X_add_number
+= add
;
5907 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5908 i
.op
[n
].imms
, 0, reloc_type
);
5914 /* x86_cons_fix_new is called via the expression parsing code when a
5915 reloc is needed. We use this hook to get the correct .got reloc. */
5916 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5917 static int cons_sign
= -1;
5920 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5923 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5925 got_reloc
= NO_RELOC
;
5928 if (exp
->X_op
== O_secrel
)
5930 exp
->X_op
= O_symbol
;
5931 r
= BFD_RELOC_32_SECREL
;
5935 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5938 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5939 # define lex_got(reloc, adjust, types) NULL
5941 /* Parse operands of the form
5942 <symbol>@GOTOFF+<nnn>
5943 and similar .plt or .got references.
5945 If we find one, set up the correct relocation in RELOC and copy the
5946 input string, minus the `@GOTOFF' into a malloc'd buffer for
5947 parsing by the calling routine. Return this buffer, and if ADJUST
5948 is non-null set it to the length of the string we removed from the
5949 input line. Otherwise return NULL. */
5951 lex_got (enum bfd_reloc_code_real
*reloc
,
5953 i386_operand_type
*types
)
5955 /* Some of the relocations depend on the size of what field is to
5956 be relocated. But in our callers i386_immediate and i386_displacement
5957 we don't yet know the operand size (this will be set by insn
5958 matching). Hence we record the word32 relocation here,
5959 and adjust the reloc according to the real size in reloc(). */
5960 static const struct {
5962 const enum bfd_reloc_code_real rel
[2];
5963 const i386_operand_type types64
;
5966 BFD_RELOC_X86_64_PLTOFF64
},
5967 OPERAND_TYPE_IMM64
},
5968 { "PLT", { BFD_RELOC_386_PLT32
,
5969 BFD_RELOC_X86_64_PLT32
},
5970 OPERAND_TYPE_IMM32_32S_DISP32
},
5972 BFD_RELOC_X86_64_GOTPLT64
},
5973 OPERAND_TYPE_IMM64_DISP64
},
5974 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5975 BFD_RELOC_X86_64_GOTOFF64
},
5976 OPERAND_TYPE_IMM64_DISP64
},
5978 BFD_RELOC_X86_64_GOTPCREL
},
5979 OPERAND_TYPE_IMM32_32S_DISP32
},
5980 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5981 BFD_RELOC_X86_64_TLSGD
},
5982 OPERAND_TYPE_IMM32_32S_DISP32
},
5983 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5985 OPERAND_TYPE_NONE
},
5987 BFD_RELOC_X86_64_TLSLD
},
5988 OPERAND_TYPE_IMM32_32S_DISP32
},
5989 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5990 BFD_RELOC_X86_64_GOTTPOFF
},
5991 OPERAND_TYPE_IMM32_32S_DISP32
},
5992 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5993 BFD_RELOC_X86_64_TPOFF32
},
5994 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5995 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5997 OPERAND_TYPE_NONE
},
5998 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5999 BFD_RELOC_X86_64_DTPOFF32
},
6001 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6002 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6004 OPERAND_TYPE_NONE
},
6005 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6007 OPERAND_TYPE_NONE
},
6008 { "GOT", { BFD_RELOC_386_GOT32
,
6009 BFD_RELOC_X86_64_GOT32
},
6010 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6011 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6012 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6013 OPERAND_TYPE_IMM32_32S_DISP32
},
6014 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6015 BFD_RELOC_X86_64_TLSDESC_CALL
},
6016 OPERAND_TYPE_IMM32_32S_DISP32
},
6024 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6025 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6028 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6032 len
= strlen (gotrel
[j
].str
);
6033 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6035 if (gotrel
[j
].rel
[object_64bit
] != 0)
6038 char *tmpbuf
, *past_reloc
;
6040 *reloc
= gotrel
[j
].rel
[object_64bit
];
6046 if (flag_code
!= CODE_64BIT
)
6048 types
->bitfield
.imm32
= 1;
6049 types
->bitfield
.disp32
= 1;
6052 *types
= gotrel
[j
].types64
;
6055 if (GOT_symbol
== NULL
)
6056 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6058 /* The length of the first part of our input line. */
6059 first
= cp
- input_line_pointer
;
6061 /* The second part goes from after the reloc token until
6062 (and including) an end_of_line char or comma. */
6063 past_reloc
= cp
+ 1 + len
;
6065 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6067 second
= cp
+ 1 - past_reloc
;
6069 /* Allocate and copy string. The trailing NUL shouldn't
6070 be necessary, but be safe. */
6071 tmpbuf
= xmalloc (first
+ second
+ 2);
6072 memcpy (tmpbuf
, input_line_pointer
, first
);
6073 if (second
!= 0 && *past_reloc
!= ' ')
6074 /* Replace the relocation token with ' ', so that
6075 errors like foo@GOTOFF1 will be detected. */
6076 tmpbuf
[first
++] = ' ';
6077 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6078 tmpbuf
[first
+ second
] = '\0';
6082 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6083 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6088 /* Might be a symbol version string. Don't as_bad here. */
6093 x86_cons (expressionS
*exp
, int size
)
6095 intel_syntax
= -intel_syntax
;
6097 if (size
== 4 || (object_64bit
&& size
== 8))
6099 /* Handle @GOTOFF and the like in an expression. */
6101 char *gotfree_input_line
;
6104 save
= input_line_pointer
;
6105 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6106 if (gotfree_input_line
)
6107 input_line_pointer
= gotfree_input_line
;
6111 if (gotfree_input_line
)
6113 /* expression () has merrily parsed up to the end of line,
6114 or a comma - in the wrong buffer. Transfer how far
6115 input_line_pointer has moved to the right buffer. */
6116 input_line_pointer
= (save
6117 + (input_line_pointer
- gotfree_input_line
)
6119 free (gotfree_input_line
);
6120 if (exp
->X_op
== O_constant
6121 || exp
->X_op
== O_absent
6122 || exp
->X_op
== O_illegal
6123 || exp
->X_op
== O_register
6124 || exp
->X_op
== O_big
)
6126 char c
= *input_line_pointer
;
6127 *input_line_pointer
= 0;
6128 as_bad (_("missing or invalid expression `%s'"), save
);
6129 *input_line_pointer
= c
;
6136 intel_syntax
= -intel_syntax
;
6139 i386_intel_simplify (exp
);
6143 static void signed_cons (int size
)
6145 if (flag_code
== CODE_64BIT
)
6153 pe_directive_secrel (dummy
)
6154 int dummy ATTRIBUTE_UNUSED
;
6161 if (exp
.X_op
== O_symbol
)
6162 exp
.X_op
= O_secrel
;
6164 emit_expr (&exp
, 4);
6166 while (*input_line_pointer
++ == ',');
6168 input_line_pointer
--;
6169 demand_empty_rest_of_line ();
6174 i386_immediate (char *imm_start
)
6176 char *save_input_line_pointer
;
6177 char *gotfree_input_line
;
6180 i386_operand_type types
;
6182 operand_type_set (&types
, ~0);
6184 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6186 as_bad (_("at most %d immediate operands are allowed"),
6187 MAX_IMMEDIATE_OPERANDS
);
6191 exp
= &im_expressions
[i
.imm_operands
++];
6192 i
.op
[this_operand
].imms
= exp
;
6194 if (is_space_char (*imm_start
))
6197 save_input_line_pointer
= input_line_pointer
;
6198 input_line_pointer
= imm_start
;
6200 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6201 if (gotfree_input_line
)
6202 input_line_pointer
= gotfree_input_line
;
6204 exp_seg
= expression (exp
);
6207 if (*input_line_pointer
)
6208 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6210 input_line_pointer
= save_input_line_pointer
;
6211 if (gotfree_input_line
)
6213 free (gotfree_input_line
);
6215 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6216 exp
->X_op
= O_illegal
;
6219 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6223 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6224 i386_operand_type types
, const char *imm_start
)
6226 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6228 as_bad (_("missing or invalid immediate expression `%s'"),
6232 else if (exp
->X_op
== O_constant
)
6234 /* Size it properly later. */
6235 i
.types
[this_operand
].bitfield
.imm64
= 1;
6236 /* If BFD64, sign extend val. */
6237 if (!use_rela_relocations
6238 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6240 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6242 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6243 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6244 && exp_seg
!= absolute_section
6245 && exp_seg
!= text_section
6246 && exp_seg
!= data_section
6247 && exp_seg
!= bss_section
6248 && exp_seg
!= undefined_section
6249 && !bfd_is_com_section (exp_seg
))
6251 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6255 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6257 as_bad (_("illegal immediate register operand %s"), imm_start
);
6262 /* This is an address. The size of the address will be
6263 determined later, depending on destination register,
6264 suffix, or the default for the section. */
6265 i
.types
[this_operand
].bitfield
.imm8
= 1;
6266 i
.types
[this_operand
].bitfield
.imm16
= 1;
6267 i
.types
[this_operand
].bitfield
.imm32
= 1;
6268 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6269 i
.types
[this_operand
].bitfield
.imm64
= 1;
6270 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6278 i386_scale (char *scale
)
6281 char *save
= input_line_pointer
;
6283 input_line_pointer
= scale
;
6284 val
= get_absolute_expression ();
6289 i
.log2_scale_factor
= 0;
6292 i
.log2_scale_factor
= 1;
6295 i
.log2_scale_factor
= 2;
6298 i
.log2_scale_factor
= 3;
6302 char sep
= *input_line_pointer
;
6304 *input_line_pointer
= '\0';
6305 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6307 *input_line_pointer
= sep
;
6308 input_line_pointer
= save
;
6312 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6314 as_warn (_("scale factor of %d without an index register"),
6315 1 << i
.log2_scale_factor
);
6316 i
.log2_scale_factor
= 0;
6318 scale
= input_line_pointer
;
6319 input_line_pointer
= save
;
6324 i386_displacement (char *disp_start
, char *disp_end
)
6328 char *save_input_line_pointer
;
6329 char *gotfree_input_line
;
6331 i386_operand_type bigdisp
, types
= anydisp
;
6334 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6336 as_bad (_("at most %d displacement operands are allowed"),
6337 MAX_MEMORY_OPERANDS
);
6341 operand_type_set (&bigdisp
, 0);
6342 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6343 || (!current_templates
->start
->opcode_modifier
.jump
6344 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6346 bigdisp
.bitfield
.disp32
= 1;
6347 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6348 if (flag_code
== CODE_64BIT
)
6352 bigdisp
.bitfield
.disp32s
= 1;
6353 bigdisp
.bitfield
.disp64
= 1;
6356 else if ((flag_code
== CODE_16BIT
) ^ override
)
6358 bigdisp
.bitfield
.disp32
= 0;
6359 bigdisp
.bitfield
.disp16
= 1;
6364 /* For PC-relative branches, the width of the displacement
6365 is dependent upon data size, not address size. */
6366 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6367 if (flag_code
== CODE_64BIT
)
6369 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6370 bigdisp
.bitfield
.disp16
= 1;
6373 bigdisp
.bitfield
.disp32
= 1;
6374 bigdisp
.bitfield
.disp32s
= 1;
6380 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6382 : LONG_MNEM_SUFFIX
));
6383 bigdisp
.bitfield
.disp32
= 1;
6384 if ((flag_code
== CODE_16BIT
) ^ override
)
6386 bigdisp
.bitfield
.disp32
= 0;
6387 bigdisp
.bitfield
.disp16
= 1;
6391 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6394 exp
= &disp_expressions
[i
.disp_operands
];
6395 i
.op
[this_operand
].disps
= exp
;
6397 save_input_line_pointer
= input_line_pointer
;
6398 input_line_pointer
= disp_start
;
6399 END_STRING_AND_SAVE (disp_end
);
6401 #ifndef GCC_ASM_O_HACK
6402 #define GCC_ASM_O_HACK 0
6405 END_STRING_AND_SAVE (disp_end
+ 1);
6406 if (i
.types
[this_operand
].bitfield
.baseIndex
6407 && displacement_string_end
[-1] == '+')
6409 /* This hack is to avoid a warning when using the "o"
6410 constraint within gcc asm statements.
6413 #define _set_tssldt_desc(n,addr,limit,type) \
6414 __asm__ __volatile__ ( \
6416 "movw %w1,2+%0\n\t" \
6418 "movb %b1,4+%0\n\t" \
6419 "movb %4,5+%0\n\t" \
6420 "movb $0,6+%0\n\t" \
6421 "movb %h1,7+%0\n\t" \
6423 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6425 This works great except that the output assembler ends
6426 up looking a bit weird if it turns out that there is
6427 no offset. You end up producing code that looks like:
6440 So here we provide the missing zero. */
6442 *displacement_string_end
= '0';
6445 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6446 if (gotfree_input_line
)
6447 input_line_pointer
= gotfree_input_line
;
6449 exp_seg
= expression (exp
);
6452 if (*input_line_pointer
)
6453 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6455 RESTORE_END_STRING (disp_end
+ 1);
6457 input_line_pointer
= save_input_line_pointer
;
6458 if (gotfree_input_line
)
6460 free (gotfree_input_line
);
6462 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6463 exp
->X_op
= O_illegal
;
6466 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6468 RESTORE_END_STRING (disp_end
);
6474 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6475 i386_operand_type types
, const char *disp_start
)
6477 i386_operand_type bigdisp
;
6480 /* We do this to make sure that the section symbol is in
6481 the symbol table. We will ultimately change the relocation
6482 to be relative to the beginning of the section. */
6483 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6484 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6485 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6487 if (exp
->X_op
!= O_symbol
)
6490 if (S_IS_LOCAL (exp
->X_add_symbol
)
6491 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6492 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6493 exp
->X_op
= O_subtract
;
6494 exp
->X_op_symbol
= GOT_symbol
;
6495 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6496 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6497 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6498 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6500 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6503 else if (exp
->X_op
== O_absent
6504 || exp
->X_op
== O_illegal
6505 || exp
->X_op
== O_big
)
6508 as_bad (_("missing or invalid displacement expression `%s'"),
6513 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6514 else if (exp
->X_op
!= O_constant
6515 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6516 && exp_seg
!= absolute_section
6517 && exp_seg
!= text_section
6518 && exp_seg
!= data_section
6519 && exp_seg
!= bss_section
6520 && exp_seg
!= undefined_section
6521 && !bfd_is_com_section (exp_seg
))
6523 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6528 /* Check if this is a displacement only operand. */
6529 bigdisp
= i
.types
[this_operand
];
6530 bigdisp
.bitfield
.disp8
= 0;
6531 bigdisp
.bitfield
.disp16
= 0;
6532 bigdisp
.bitfield
.disp32
= 0;
6533 bigdisp
.bitfield
.disp32s
= 0;
6534 bigdisp
.bitfield
.disp64
= 0;
6535 if (operand_type_all_zero (&bigdisp
))
6536 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6542 /* Make sure the memory operand we've been dealt is valid.
6543 Return 1 on success, 0 on a failure. */
6546 i386_index_check (const char *operand_string
)
6549 const char *kind
= "base/index";
6550 #if INFER_ADDR_PREFIX
6556 if (current_templates
->start
->opcode_modifier
.isstring
6557 && !current_templates
->start
->opcode_modifier
.immext
6558 && (current_templates
->end
[-1].opcode_modifier
.isstring
6561 /* Memory operands of string insns are special in that they only allow
6562 a single register (rDI, rSI, or rBX) as their memory address. */
6563 unsigned int expected
;
6565 kind
= "string address";
6567 if (current_templates
->start
->opcode_modifier
.w
)
6569 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6571 if (!type
.bitfield
.baseindex
6572 || ((!i
.mem_operands
!= !intel_syntax
)
6573 && current_templates
->end
[-1].operand_types
[1]
6574 .bitfield
.baseindex
))
6575 type
= current_templates
->end
[-1].operand_types
[1];
6576 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6579 expected
= 3 /* rBX */;
6581 if (!i
.base_reg
|| i
.index_reg
6582 || operand_type_check (i
.types
[this_operand
], disp
))
6584 else if (!(flag_code
== CODE_64BIT
6585 ? i
.prefix
[ADDR_PREFIX
]
6586 ? i
.base_reg
->reg_type
.bitfield
.reg32
6587 : i
.base_reg
->reg_type
.bitfield
.reg64
6588 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6589 ? i
.base_reg
->reg_type
.bitfield
.reg32
6590 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6592 else if (i
.base_reg
->reg_num
!= expected
)
6599 for (j
= 0; j
< i386_regtab_size
; ++j
)
6600 if ((flag_code
== CODE_64BIT
6601 ? i
.prefix
[ADDR_PREFIX
]
6602 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6603 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6604 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6605 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6606 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6607 && i386_regtab
[j
].reg_num
== expected
)
6609 gas_assert (j
< i386_regtab_size
);
6610 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6612 intel_syntax
? '[' : '(',
6614 i386_regtab
[j
].reg_name
,
6615 intel_syntax
? ']' : ')');
6619 else if (flag_code
== CODE_64BIT
)
6622 && ((i
.prefix
[ADDR_PREFIX
] == 0
6623 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6624 || (i
.prefix
[ADDR_PREFIX
]
6625 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6627 || i
.base_reg
->reg_num
!=
6628 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6630 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6631 || (i
.prefix
[ADDR_PREFIX
] == 0
6632 && i
.index_reg
->reg_num
!= RegRiz
6633 && !i
.index_reg
->reg_type
.bitfield
.reg64
6635 || (i
.prefix
[ADDR_PREFIX
]
6636 && i
.index_reg
->reg_num
!= RegEiz
6637 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6642 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6646 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6647 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6649 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6650 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6652 && i
.base_reg
->reg_num
< 6
6653 && i
.index_reg
->reg_num
>= 6
6654 && i
.log2_scale_factor
== 0))))
6661 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6663 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6664 && i
.index_reg
->reg_num
!= RegEiz
)
6665 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6671 #if INFER_ADDR_PREFIX
6672 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6674 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6676 /* Change the size of any displacement too. At most one of
6677 Disp16 or Disp32 is set.
6678 FIXME. There doesn't seem to be any real need for separate
6679 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6680 Removing them would probably clean up the code quite a lot. */
6681 if (flag_code
!= CODE_64BIT
6682 && (i
.types
[this_operand
].bitfield
.disp16
6683 || i
.types
[this_operand
].bitfield
.disp32
))
6684 i
.types
[this_operand
]
6685 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6690 as_bad (_("`%s' is not a valid %s expression"),
6695 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6697 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6698 ? flag_code
== CODE_32BIT
6707 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6711 i386_att_operand (char *operand_string
)
6715 char *op_string
= operand_string
;
6717 if (is_space_char (*op_string
))
6720 /* We check for an absolute prefix (differentiating,
6721 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6722 if (*op_string
== ABSOLUTE_PREFIX
)
6725 if (is_space_char (*op_string
))
6727 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6730 /* Check if operand is a register. */
6731 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6733 i386_operand_type temp
;
6735 /* Check for a segment override by searching for ':' after a
6736 segment register. */
6738 if (is_space_char (*op_string
))
6740 if (*op_string
== ':'
6741 && (r
->reg_type
.bitfield
.sreg2
6742 || r
->reg_type
.bitfield
.sreg3
))
6747 i
.seg
[i
.mem_operands
] = &es
;
6750 i
.seg
[i
.mem_operands
] = &cs
;
6753 i
.seg
[i
.mem_operands
] = &ss
;
6756 i
.seg
[i
.mem_operands
] = &ds
;
6759 i
.seg
[i
.mem_operands
] = &fs
;
6762 i
.seg
[i
.mem_operands
] = &gs
;
6766 /* Skip the ':' and whitespace. */
6768 if (is_space_char (*op_string
))
6771 if (!is_digit_char (*op_string
)
6772 && !is_identifier_char (*op_string
)
6773 && *op_string
!= '('
6774 && *op_string
!= ABSOLUTE_PREFIX
)
6776 as_bad (_("bad memory operand `%s'"), op_string
);
6779 /* Handle case of %es:*foo. */
6780 if (*op_string
== ABSOLUTE_PREFIX
)
6783 if (is_space_char (*op_string
))
6785 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6787 goto do_memory_reference
;
6791 as_bad (_("junk `%s' after register"), op_string
);
6795 temp
.bitfield
.baseindex
= 0;
6796 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6798 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6799 i
.op
[this_operand
].regs
= r
;
6802 else if (*op_string
== REGISTER_PREFIX
)
6804 as_bad (_("bad register name `%s'"), op_string
);
6807 else if (*op_string
== IMMEDIATE_PREFIX
)
6810 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6812 as_bad (_("immediate operand illegal with absolute jump"));
6815 if (!i386_immediate (op_string
))
6818 else if (is_digit_char (*op_string
)
6819 || is_identifier_char (*op_string
)
6820 || *op_string
== '(')
6822 /* This is a memory reference of some sort. */
6825 /* Start and end of displacement string expression (if found). */
6826 char *displacement_string_start
;
6827 char *displacement_string_end
;
6829 do_memory_reference
:
6830 if ((i
.mem_operands
== 1
6831 && !current_templates
->start
->opcode_modifier
.isstring
)
6832 || i
.mem_operands
== 2)
6834 as_bad (_("too many memory references for `%s'"),
6835 current_templates
->start
->name
);
6839 /* Check for base index form. We detect the base index form by
6840 looking for an ')' at the end of the operand, searching
6841 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6843 base_string
= op_string
+ strlen (op_string
);
6846 if (is_space_char (*base_string
))
6849 /* If we only have a displacement, set-up for it to be parsed later. */
6850 displacement_string_start
= op_string
;
6851 displacement_string_end
= base_string
+ 1;
6853 if (*base_string
== ')')
6856 unsigned int parens_balanced
= 1;
6857 /* We've already checked that the number of left & right ()'s are
6858 equal, so this loop will not be infinite. */
6862 if (*base_string
== ')')
6864 if (*base_string
== '(')
6867 while (parens_balanced
);
6869 temp_string
= base_string
;
6871 /* Skip past '(' and whitespace. */
6873 if (is_space_char (*base_string
))
6876 if (*base_string
== ','
6877 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6880 displacement_string_end
= temp_string
;
6882 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6886 base_string
= end_op
;
6887 if (is_space_char (*base_string
))
6891 /* There may be an index reg or scale factor here. */
6892 if (*base_string
== ',')
6895 if (is_space_char (*base_string
))
6898 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6901 base_string
= end_op
;
6902 if (is_space_char (*base_string
))
6904 if (*base_string
== ',')
6907 if (is_space_char (*base_string
))
6910 else if (*base_string
!= ')')
6912 as_bad (_("expecting `,' or `)' "
6913 "after index register in `%s'"),
6918 else if (*base_string
== REGISTER_PREFIX
)
6920 as_bad (_("bad register name `%s'"), base_string
);
6924 /* Check for scale factor. */
6925 if (*base_string
!= ')')
6927 char *end_scale
= i386_scale (base_string
);
6932 base_string
= end_scale
;
6933 if (is_space_char (*base_string
))
6935 if (*base_string
!= ')')
6937 as_bad (_("expecting `)' "
6938 "after scale factor in `%s'"),
6943 else if (!i
.index_reg
)
6945 as_bad (_("expecting index register or scale factor "
6946 "after `,'; got '%c'"),
6951 else if (*base_string
!= ')')
6953 as_bad (_("expecting `,' or `)' "
6954 "after base register in `%s'"),
6959 else if (*base_string
== REGISTER_PREFIX
)
6961 as_bad (_("bad register name `%s'"), base_string
);
6966 /* If there's an expression beginning the operand, parse it,
6967 assuming displacement_string_start and
6968 displacement_string_end are meaningful. */
6969 if (displacement_string_start
!= displacement_string_end
)
6971 if (!i386_displacement (displacement_string_start
,
6972 displacement_string_end
))
6976 /* Special case for (%dx) while doing input/output op. */
6978 && operand_type_equal (&i
.base_reg
->reg_type
,
6979 ®16_inoutportreg
)
6981 && i
.log2_scale_factor
== 0
6982 && i
.seg
[i
.mem_operands
] == 0
6983 && !operand_type_check (i
.types
[this_operand
], disp
))
6985 i
.types
[this_operand
] = inoutportreg
;
6989 if (i386_index_check (operand_string
) == 0)
6991 i
.types
[this_operand
].bitfield
.mem
= 1;
6996 /* It's not a memory operand; argh! */
6997 as_bad (_("invalid char %s beginning operand %d `%s'"),
6998 output_invalid (*op_string
),
7003 return 1; /* Normal return. */
7006 /* md_estimate_size_before_relax()
7008 Called just before relax() for rs_machine_dependent frags. The x86
7009 assembler uses these frags to handle variable size jump
7012 Any symbol that is now undefined will not become defined.
7013 Return the correct fr_subtype in the frag.
7014 Return the initial "guess for variable size of frag" to caller.
7015 The guess is actually the growth beyond the fixed part. Whatever
7016 we do to grow the fixed or variable part contributes to our
7020 md_estimate_size_before_relax (fragP
, segment
)
7024 /* We've already got fragP->fr_subtype right; all we have to do is
7025 check for un-relaxable symbols. On an ELF system, we can't relax
7026 an externally visible symbol, because it may be overridden by a
7028 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7029 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7031 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7032 || S_IS_WEAK (fragP
->fr_symbol
)
7033 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7034 & BSF_GNU_INDIRECT_FUNCTION
))))
7036 #if defined (OBJ_COFF) && defined (TE_PE)
7037 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7038 && S_IS_WEAK (fragP
->fr_symbol
))
7042 /* Symbol is undefined in this segment, or we need to keep a
7043 reloc so that weak symbols can be overridden. */
7044 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7045 enum bfd_reloc_code_real reloc_type
;
7046 unsigned char *opcode
;
7049 if (fragP
->fr_var
!= NO_RELOC
)
7050 reloc_type
= fragP
->fr_var
;
7052 reloc_type
= BFD_RELOC_16_PCREL
;
7054 reloc_type
= BFD_RELOC_32_PCREL
;
7056 old_fr_fix
= fragP
->fr_fix
;
7057 opcode
= (unsigned char *) fragP
->fr_opcode
;
7059 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7062 /* Make jmp (0xeb) a (d)word displacement jump. */
7064 fragP
->fr_fix
+= size
;
7065 fix_new (fragP
, old_fr_fix
, size
,
7067 fragP
->fr_offset
, 1,
7073 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7075 /* Negate the condition, and branch past an
7076 unconditional jump. */
7079 /* Insert an unconditional jump. */
7081 /* We added two extra opcode bytes, and have a two byte
7083 fragP
->fr_fix
+= 2 + 2;
7084 fix_new (fragP
, old_fr_fix
+ 2, 2,
7086 fragP
->fr_offset
, 1,
7093 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7098 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7100 fragP
->fr_offset
, 1,
7102 fixP
->fx_signed
= 1;
7106 /* This changes the byte-displacement jump 0x7N
7107 to the (d)word-displacement jump 0x0f,0x8N. */
7108 opcode
[1] = opcode
[0] + 0x10;
7109 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7110 /* We've added an opcode byte. */
7111 fragP
->fr_fix
+= 1 + size
;
7112 fix_new (fragP
, old_fr_fix
+ 1, size
,
7114 fragP
->fr_offset
, 1,
7119 BAD_CASE (fragP
->fr_subtype
);
7123 return fragP
->fr_fix
- old_fr_fix
;
7126 /* Guess size depending on current relax state. Initially the relax
7127 state will correspond to a short jump and we return 1, because
7128 the variable part of the frag (the branch offset) is one byte
7129 long. However, we can relax a section more than once and in that
7130 case we must either set fr_subtype back to the unrelaxed state,
7131 or return the value for the appropriate branch. */
7132 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7135 /* Called after relax() is finished.
7137 In: Address of frag.
7138 fr_type == rs_machine_dependent.
7139 fr_subtype is what the address relaxed to.
7141 Out: Any fixSs and constants are set up.
7142 Caller will turn frag into a ".space 0". */
7145 md_convert_frag (abfd
, sec
, fragP
)
7146 bfd
*abfd ATTRIBUTE_UNUSED
;
7147 segT sec ATTRIBUTE_UNUSED
;
7150 unsigned char *opcode
;
7151 unsigned char *where_to_put_displacement
= NULL
;
7152 offsetT target_address
;
7153 offsetT opcode_address
;
7154 unsigned int extension
= 0;
7155 offsetT displacement_from_opcode_start
;
7157 opcode
= (unsigned char *) fragP
->fr_opcode
;
7159 /* Address we want to reach in file space. */
7160 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7162 /* Address opcode resides at in file space. */
7163 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7165 /* Displacement from opcode start to fill into instruction. */
7166 displacement_from_opcode_start
= target_address
- opcode_address
;
7168 if ((fragP
->fr_subtype
& BIG
) == 0)
7170 /* Don't have to change opcode. */
7171 extension
= 1; /* 1 opcode + 1 displacement */
7172 where_to_put_displacement
= &opcode
[1];
7176 if (no_cond_jump_promotion
7177 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7178 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7179 _("long jump required"));
7181 switch (fragP
->fr_subtype
)
7183 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7184 extension
= 4; /* 1 opcode + 4 displacement */
7186 where_to_put_displacement
= &opcode
[1];
7189 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7190 extension
= 2; /* 1 opcode + 2 displacement */
7192 where_to_put_displacement
= &opcode
[1];
7195 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7196 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7197 extension
= 5; /* 2 opcode + 4 displacement */
7198 opcode
[1] = opcode
[0] + 0x10;
7199 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7200 where_to_put_displacement
= &opcode
[2];
7203 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7204 extension
= 3; /* 2 opcode + 2 displacement */
7205 opcode
[1] = opcode
[0] + 0x10;
7206 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7207 where_to_put_displacement
= &opcode
[2];
7210 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7215 where_to_put_displacement
= &opcode
[3];
7219 BAD_CASE (fragP
->fr_subtype
);
7224 /* If size if less then four we are sure that the operand fits,
7225 but if it's 4, then it could be that the displacement is larger
7227 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7229 && ((addressT
) (displacement_from_opcode_start
- extension
7230 + ((addressT
) 1 << 31))
7231 > (((addressT
) 2 << 31) - 1)))
7233 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7234 _("jump target out of range"));
7235 /* Make us emit 0. */
7236 displacement_from_opcode_start
= extension
;
7238 /* Now put displacement after opcode. */
7239 md_number_to_chars ((char *) where_to_put_displacement
,
7240 (valueT
) (displacement_from_opcode_start
- extension
),
7241 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7242 fragP
->fr_fix
+= extension
;
7245 /* Apply a fixup (fixS) to segment data, once it has been determined
7246 by our caller that we have all the info we need to fix it up.
7248 On the 386, immediates, displacements, and data pointers are all in
7249 the same (little-endian) format, so we don't need to care about which
7253 md_apply_fix (fixP
, valP
, seg
)
7254 /* The fix we're to put in. */
7256 /* Pointer to the value of the bits. */
7258 /* Segment fix is from. */
7259 segT seg ATTRIBUTE_UNUSED
;
7261 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7262 valueT value
= *valP
;
7264 #if !defined (TE_Mach)
7267 switch (fixP
->fx_r_type
)
7273 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7276 case BFD_RELOC_X86_64_32S
:
7277 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7280 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7283 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7288 if (fixP
->fx_addsy
!= NULL
7289 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7290 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7291 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7292 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7293 && !use_rela_relocations
)
7295 /* This is a hack. There should be a better way to handle this.
7296 This covers for the fact that bfd_install_relocation will
7297 subtract the current location (for partial_inplace, PC relative
7298 relocations); see more below. */
7302 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7305 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7307 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7310 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7313 || (symbol_section_p (fixP
->fx_addsy
)
7314 && sym_seg
!= absolute_section
))
7315 && !TC_FORCE_RELOCATION (fixP
))
7317 /* Yes, we add the values in twice. This is because
7318 bfd_install_relocation subtracts them out again. I think
7319 bfd_install_relocation is broken, but I don't dare change
7321 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7325 #if defined (OBJ_COFF) && defined (TE_PE)
7326 /* For some reason, the PE format does not store a
7327 section address offset for a PC relative symbol. */
7328 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7329 || S_IS_WEAK (fixP
->fx_addsy
))
7330 value
+= md_pcrel_from (fixP
);
7333 #if defined (OBJ_COFF) && defined (TE_PE)
7334 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7336 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7340 /* Fix a few things - the dynamic linker expects certain values here,
7341 and we must not disappoint it. */
7342 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7343 if (IS_ELF
&& fixP
->fx_addsy
)
7344 switch (fixP
->fx_r_type
)
7346 case BFD_RELOC_386_PLT32
:
7347 case BFD_RELOC_X86_64_PLT32
:
7348 /* Make the jump instruction point to the address of the operand. At
7349 runtime we merely add the offset to the actual PLT entry. */
7353 case BFD_RELOC_386_TLS_GD
:
7354 case BFD_RELOC_386_TLS_LDM
:
7355 case BFD_RELOC_386_TLS_IE_32
:
7356 case BFD_RELOC_386_TLS_IE
:
7357 case BFD_RELOC_386_TLS_GOTIE
:
7358 case BFD_RELOC_386_TLS_GOTDESC
:
7359 case BFD_RELOC_X86_64_TLSGD
:
7360 case BFD_RELOC_X86_64_TLSLD
:
7361 case BFD_RELOC_X86_64_GOTTPOFF
:
7362 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7363 value
= 0; /* Fully resolved at runtime. No addend. */
7365 case BFD_RELOC_386_TLS_LE
:
7366 case BFD_RELOC_386_TLS_LDO_32
:
7367 case BFD_RELOC_386_TLS_LE_32
:
7368 case BFD_RELOC_X86_64_DTPOFF32
:
7369 case BFD_RELOC_X86_64_DTPOFF64
:
7370 case BFD_RELOC_X86_64_TPOFF32
:
7371 case BFD_RELOC_X86_64_TPOFF64
:
7372 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7375 case BFD_RELOC_386_TLS_DESC_CALL
:
7376 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7377 value
= 0; /* Fully resolved at runtime. No addend. */
7378 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7382 case BFD_RELOC_386_GOT32
:
7383 case BFD_RELOC_X86_64_GOT32
:
7384 value
= 0; /* Fully resolved at runtime. No addend. */
7387 case BFD_RELOC_VTABLE_INHERIT
:
7388 case BFD_RELOC_VTABLE_ENTRY
:
7395 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7397 #endif /* !defined (TE_Mach) */
7399 /* Are we finished with this relocation now? */
7400 if (fixP
->fx_addsy
== NULL
)
7402 #if defined (OBJ_COFF) && defined (TE_PE)
7403 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7406 /* Remember value for tc_gen_reloc. */
7407 fixP
->fx_addnumber
= value
;
7408 /* Clear out the frag for now. */
7412 else if (use_rela_relocations
)
7414 fixP
->fx_no_overflow
= 1;
7415 /* Remember value for tc_gen_reloc. */
7416 fixP
->fx_addnumber
= value
;
7420 md_number_to_chars (p
, value
, fixP
->fx_size
);
7424 md_atof (int type
, char *litP
, int *sizeP
)
7426 /* This outputs the LITTLENUMs in REVERSE order;
7427 in accord with the bigendian 386. */
7428 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7431 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7434 output_invalid (int c
)
7437 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7440 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7441 "(0x%x)", (unsigned char) c
);
7442 return output_invalid_buf
;
7445 /* REG_STRING starts *before* REGISTER_PREFIX. */
7447 static const reg_entry
*
7448 parse_real_register (char *reg_string
, char **end_op
)
7450 char *s
= reg_string
;
7452 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7455 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7456 if (*s
== REGISTER_PREFIX
)
7459 if (is_space_char (*s
))
7463 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7465 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7466 return (const reg_entry
*) NULL
;
7470 /* For naked regs, make sure that we are not dealing with an identifier.
7471 This prevents confusing an identifier like `eax_var' with register
7473 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7474 return (const reg_entry
*) NULL
;
7478 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7480 /* Handle floating point regs, allowing spaces in the (i) part. */
7481 if (r
== i386_regtab
/* %st is first entry of table */)
7483 if (is_space_char (*s
))
7488 if (is_space_char (*s
))
7490 if (*s
>= '0' && *s
<= '7')
7494 if (is_space_char (*s
))
7499 r
= hash_find (reg_hash
, "st(0)");
7504 /* We have "%st(" then garbage. */
7505 return (const reg_entry
*) NULL
;
7509 if (r
== NULL
|| allow_pseudo_reg
)
7512 if (operand_type_all_zero (&r
->reg_type
))
7513 return (const reg_entry
*) NULL
;
7515 if ((r
->reg_type
.bitfield
.reg32
7516 || r
->reg_type
.bitfield
.sreg3
7517 || r
->reg_type
.bitfield
.control
7518 || r
->reg_type
.bitfield
.debug
7519 || r
->reg_type
.bitfield
.test
)
7520 && !cpu_arch_flags
.bitfield
.cpui386
)
7521 return (const reg_entry
*) NULL
;
7523 if (r
->reg_type
.bitfield
.floatreg
7524 && !cpu_arch_flags
.bitfield
.cpu8087
7525 && !cpu_arch_flags
.bitfield
.cpu287
7526 && !cpu_arch_flags
.bitfield
.cpu387
)
7527 return (const reg_entry
*) NULL
;
7529 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7530 return (const reg_entry
*) NULL
;
7532 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7533 return (const reg_entry
*) NULL
;
7535 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7536 return (const reg_entry
*) NULL
;
7538 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7539 if (!allow_index_reg
7540 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7541 return (const reg_entry
*) NULL
;
7543 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7544 || r
->reg_type
.bitfield
.reg64
)
7545 && (!cpu_arch_flags
.bitfield
.cpulm
7546 || !operand_type_equal (&r
->reg_type
, &control
))
7547 && flag_code
!= CODE_64BIT
)
7548 return (const reg_entry
*) NULL
;
7550 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7551 return (const reg_entry
*) NULL
;
7556 /* REG_STRING starts *before* REGISTER_PREFIX. */
7558 static const reg_entry
*
7559 parse_register (char *reg_string
, char **end_op
)
7563 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7564 r
= parse_real_register (reg_string
, end_op
);
7569 char *save
= input_line_pointer
;
7573 input_line_pointer
= reg_string
;
7574 c
= get_symbol_end ();
7575 symbolP
= symbol_find (reg_string
);
7576 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7578 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7580 know (e
->X_op
== O_register
);
7581 know (e
->X_add_number
>= 0
7582 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7583 r
= i386_regtab
+ e
->X_add_number
;
7584 *end_op
= input_line_pointer
;
7586 *input_line_pointer
= c
;
7587 input_line_pointer
= save
;
7593 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7596 char *end
= input_line_pointer
;
7599 r
= parse_register (name
, &input_line_pointer
);
7600 if (r
&& end
<= input_line_pointer
)
7602 *nextcharP
= *input_line_pointer
;
7603 *input_line_pointer
= 0;
7604 e
->X_op
= O_register
;
7605 e
->X_add_number
= r
- i386_regtab
;
7608 input_line_pointer
= end
;
7610 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7614 md_operand (expressionS
*e
)
7619 switch (*input_line_pointer
)
7621 case REGISTER_PREFIX
:
7622 r
= parse_real_register (input_line_pointer
, &end
);
7625 e
->X_op
= O_register
;
7626 e
->X_add_number
= r
- i386_regtab
;
7627 input_line_pointer
= end
;
7632 gas_assert (intel_syntax
);
7633 end
= input_line_pointer
++;
7635 if (*input_line_pointer
== ']')
7637 ++input_line_pointer
;
7638 e
->X_op_symbol
= make_expr_symbol (e
);
7639 e
->X_add_symbol
= NULL
;
7640 e
->X_add_number
= 0;
7646 input_line_pointer
= end
;
7653 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7654 const char *md_shortopts
= "kVQ:sqn";
7656 const char *md_shortopts
= "qn";
7659 #define OPTION_32 (OPTION_MD_BASE + 0)
7660 #define OPTION_64 (OPTION_MD_BASE + 1)
7661 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7662 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7663 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7664 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7665 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7666 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7667 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7668 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7669 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7670 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7672 struct option md_longopts
[] =
7674 {"32", no_argument
, NULL
, OPTION_32
},
7675 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7676 || defined (TE_PE) || defined (TE_PEP))
7677 {"64", no_argument
, NULL
, OPTION_64
},
7679 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7680 {"march", required_argument
, NULL
, OPTION_MARCH
},
7681 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7682 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7683 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7684 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7685 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7686 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7687 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7688 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7689 {NULL
, no_argument
, NULL
, 0}
7691 size_t md_longopts_size
= sizeof (md_longopts
);
7694 md_parse_option (int c
, char *arg
)
7702 optimize_align_code
= 0;
7709 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7710 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7711 should be emitted or not. FIXME: Not implemented. */
7715 /* -V: SVR4 argument to print version ID. */
7717 print_version_id ();
7720 /* -k: Ignore for FreeBSD compatibility. */
7725 /* -s: On i386 Solaris, this tells the native assembler to use
7726 .stab instead of .stab.excl. We always use .stab anyhow. */
7729 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7730 || defined (TE_PE) || defined (TE_PEP))
7733 const char **list
, **l
;
7735 list
= bfd_target_list ();
7736 for (l
= list
; *l
!= NULL
; l
++)
7737 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7738 || strcmp (*l
, "coff-x86-64") == 0
7739 || strcmp (*l
, "pe-x86-64") == 0
7740 || strcmp (*l
, "pei-x86-64") == 0)
7742 default_arch
= "x86_64";
7746 as_fatal (_("No compiled in support for x86_64"));
7753 default_arch
= "i386";
7757 #ifdef SVR4_COMMENT_CHARS
7762 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7764 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7768 i386_comment_chars
= n
;
7774 arch
= xstrdup (arg
);
7778 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7779 next
= strchr (arch
, '+');
7782 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7784 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7787 cpu_arch_name
= cpu_arch
[i
].name
;
7788 cpu_sub_arch_name
= NULL
;
7789 cpu_arch_flags
= cpu_arch
[i
].flags
;
7790 cpu_arch_isa
= cpu_arch
[i
].type
;
7791 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7792 if (!cpu_arch_tune_set
)
7794 cpu_arch_tune
= cpu_arch_isa
;
7795 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7799 else if (*cpu_arch
[i
].name
== '.'
7800 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7802 /* ISA entension. */
7803 i386_cpu_flags flags
;
7805 if (strncmp (arch
, "no", 2))
7806 flags
= cpu_flags_or (cpu_arch_flags
,
7809 flags
= cpu_flags_and_not (cpu_arch_flags
,
7811 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7813 if (cpu_sub_arch_name
)
7815 char *name
= cpu_sub_arch_name
;
7816 cpu_sub_arch_name
= concat (name
,
7818 (const char *) NULL
);
7822 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7823 cpu_arch_flags
= flags
;
7829 if (i
>= ARRAY_SIZE (cpu_arch
))
7830 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7834 while (next
!= NULL
);
7839 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7840 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7842 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7844 cpu_arch_tune_set
= 1;
7845 cpu_arch_tune
= cpu_arch
[i
].type
;
7846 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7850 if (i
>= ARRAY_SIZE (cpu_arch
))
7851 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7854 case OPTION_MMNEMONIC
:
7855 if (strcasecmp (arg
, "att") == 0)
7857 else if (strcasecmp (arg
, "intel") == 0)
7860 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7863 case OPTION_MSYNTAX
:
7864 if (strcasecmp (arg
, "att") == 0)
7866 else if (strcasecmp (arg
, "intel") == 0)
7869 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7872 case OPTION_MINDEX_REG
:
7873 allow_index_reg
= 1;
7876 case OPTION_MNAKED_REG
:
7877 allow_naked_reg
= 1;
7880 case OPTION_MOLD_GCC
:
7884 case OPTION_MSSE2AVX
:
7888 case OPTION_MSSE_CHECK
:
7889 if (strcasecmp (arg
, "error") == 0)
7890 sse_check
= sse_check_error
;
7891 else if (strcasecmp (arg
, "warning") == 0)
7892 sse_check
= sse_check_warning
;
7893 else if (strcasecmp (arg
, "none") == 0)
7894 sse_check
= sse_check_none
;
7896 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7906 md_show_usage (stream
)
7909 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7910 fprintf (stream
, _("\
7912 -V print assembler version number\n\
7915 fprintf (stream
, _("\
7916 -n Do not optimize code alignment\n\
7917 -q quieten some warnings\n"));
7918 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7919 fprintf (stream
, _("\
7922 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7923 || defined (TE_PE) || defined (TE_PEP))
7924 fprintf (stream
, _("\
7925 --32/--64 generate 32bit/64bit code\n"));
7927 #ifdef SVR4_COMMENT_CHARS
7928 fprintf (stream
, _("\
7929 --divide do not treat `/' as a comment character\n"));
7931 fprintf (stream
, _("\
7932 --divide ignored\n"));
7934 fprintf (stream
, _("\
7935 -march=CPU[,+EXTENSION...]\n\
7936 generate code for CPU and EXTENSION, CPU is one of:\n\
7937 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7938 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7939 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7940 generic32, generic64\n\
7941 EXTENSION is combination of:\n\
7942 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
7943 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
7944 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
7945 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
7946 svme, abm, padlock, fma4\n"));
7947 fprintf (stream
, _("\
7948 -mtune=CPU optimize for CPU, CPU is one of:\n\
7949 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7950 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7951 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7952 generic32, generic64\n"));
7953 fprintf (stream
, _("\
7954 -msse2avx encode SSE instructions with VEX prefix\n"));
7955 fprintf (stream
, _("\
7956 -msse-check=[none|error|warning]\n\
7957 check SSE instructions\n"));
7958 fprintf (stream
, _("\
7959 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7960 fprintf (stream
, _("\
7961 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7962 fprintf (stream
, _("\
7963 -mindex-reg support pseudo index registers\n"));
7964 fprintf (stream
, _("\
7965 -mnaked-reg don't require `%%' prefix for registers\n"));
7966 fprintf (stream
, _("\
7967 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7970 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7971 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7972 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
7974 /* Pick the target format to use. */
7977 i386_target_format (void)
7979 if (!strcmp (default_arch
, "x86_64"))
7981 set_code_flag (CODE_64BIT
);
7982 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
7984 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7985 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7986 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7987 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7988 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7989 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7990 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
7991 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7992 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7993 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7994 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
7996 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
7998 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7999 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8000 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8001 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8002 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8003 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8004 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8005 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8006 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8007 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8010 else if (!strcmp (default_arch
, "i386"))
8012 set_code_flag (CODE_32BIT
);
8013 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8015 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8016 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8017 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8019 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8021 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8022 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8023 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8027 as_fatal (_("Unknown architecture"));
8028 switch (OUTPUT_FLAVOR
)
8030 #if defined (TE_PE) || defined (TE_PEP)
8031 case bfd_target_coff_flavour
:
8032 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8034 #ifdef OBJ_MAYBE_AOUT
8035 case bfd_target_aout_flavour
:
8036 return AOUT_TARGET_FORMAT
;
8038 #ifdef OBJ_MAYBE_COFF
8039 case bfd_target_coff_flavour
:
8042 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8043 case bfd_target_elf_flavour
:
8045 if (flag_code
== CODE_64BIT
)
8048 use_rela_relocations
= 1;
8050 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8053 #if defined (OBJ_MACH_O)
8054 case bfd_target_mach_o_flavour
:
8055 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8063 #endif /* OBJ_MAYBE_ more than one */
8065 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8067 i386_elf_emit_arch_note (void)
8069 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8072 asection
*seg
= now_seg
;
8073 subsegT subseg
= now_subseg
;
8074 Elf_Internal_Note i_note
;
8075 Elf_External_Note e_note
;
8076 asection
*note_secp
;
8079 /* Create the .note section. */
8080 note_secp
= subseg_new (".note", 0);
8081 bfd_set_section_flags (stdoutput
,
8083 SEC_HAS_CONTENTS
| SEC_READONLY
);
8085 /* Process the arch string. */
8086 len
= strlen (cpu_arch_name
);
8088 i_note
.namesz
= len
+ 1;
8090 i_note
.type
= NT_ARCH
;
8091 p
= frag_more (sizeof (e_note
.namesz
));
8092 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8093 p
= frag_more (sizeof (e_note
.descsz
));
8094 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8095 p
= frag_more (sizeof (e_note
.type
));
8096 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8097 p
= frag_more (len
+ 1);
8098 strcpy (p
, cpu_arch_name
);
8100 frag_align (2, 0, 0);
8102 subseg_set (seg
, subseg
);
8108 md_undefined_symbol (name
)
8111 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8112 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8113 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8114 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8118 if (symbol_find (name
))
8119 as_bad (_("GOT already in symbol table"));
8120 GOT_symbol
= symbol_new (name
, undefined_section
,
8121 (valueT
) 0, &zero_address_frag
);
8128 /* Round up a section size to the appropriate boundary. */
8131 md_section_align (segment
, size
)
8132 segT segment ATTRIBUTE_UNUSED
;
8135 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8136 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8138 /* For a.out, force the section size to be aligned. If we don't do
8139 this, BFD will align it for us, but it will not write out the
8140 final bytes of the section. This may be a bug in BFD, but it is
8141 easier to fix it here since that is how the other a.out targets
8145 align
= bfd_get_section_alignment (stdoutput
, segment
);
8146 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8153 /* On the i386, PC-relative offsets are relative to the start of the
8154 next instruction. That is, the address of the offset, plus its
8155 size, since the offset is always the last part of the insn. */
8158 md_pcrel_from (fixS
*fixP
)
8160 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8166 s_bss (int ignore ATTRIBUTE_UNUSED
)
8170 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8172 obj_elf_section_change_hook ();
8174 temp
= get_absolute_expression ();
8175 subseg_set (bss_section
, (subsegT
) temp
);
8176 demand_empty_rest_of_line ();
8182 i386_validate_fix (fixS
*fixp
)
8184 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8186 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8190 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8195 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8197 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8204 tc_gen_reloc (section
, fixp
)
8205 asection
*section ATTRIBUTE_UNUSED
;
8209 bfd_reloc_code_real_type code
;
8211 switch (fixp
->fx_r_type
)
8213 case BFD_RELOC_X86_64_PLT32
:
8214 case BFD_RELOC_X86_64_GOT32
:
8215 case BFD_RELOC_X86_64_GOTPCREL
:
8216 case BFD_RELOC_386_PLT32
:
8217 case BFD_RELOC_386_GOT32
:
8218 case BFD_RELOC_386_GOTOFF
:
8219 case BFD_RELOC_386_GOTPC
:
8220 case BFD_RELOC_386_TLS_GD
:
8221 case BFD_RELOC_386_TLS_LDM
:
8222 case BFD_RELOC_386_TLS_LDO_32
:
8223 case BFD_RELOC_386_TLS_IE_32
:
8224 case BFD_RELOC_386_TLS_IE
:
8225 case BFD_RELOC_386_TLS_GOTIE
:
8226 case BFD_RELOC_386_TLS_LE_32
:
8227 case BFD_RELOC_386_TLS_LE
:
8228 case BFD_RELOC_386_TLS_GOTDESC
:
8229 case BFD_RELOC_386_TLS_DESC_CALL
:
8230 case BFD_RELOC_X86_64_TLSGD
:
8231 case BFD_RELOC_X86_64_TLSLD
:
8232 case BFD_RELOC_X86_64_DTPOFF32
:
8233 case BFD_RELOC_X86_64_DTPOFF64
:
8234 case BFD_RELOC_X86_64_GOTTPOFF
:
8235 case BFD_RELOC_X86_64_TPOFF32
:
8236 case BFD_RELOC_X86_64_TPOFF64
:
8237 case BFD_RELOC_X86_64_GOTOFF64
:
8238 case BFD_RELOC_X86_64_GOTPC32
:
8239 case BFD_RELOC_X86_64_GOT64
:
8240 case BFD_RELOC_X86_64_GOTPCREL64
:
8241 case BFD_RELOC_X86_64_GOTPC64
:
8242 case BFD_RELOC_X86_64_GOTPLT64
:
8243 case BFD_RELOC_X86_64_PLTOFF64
:
8244 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8245 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8247 case BFD_RELOC_VTABLE_ENTRY
:
8248 case BFD_RELOC_VTABLE_INHERIT
:
8250 case BFD_RELOC_32_SECREL
:
8252 code
= fixp
->fx_r_type
;
8254 case BFD_RELOC_X86_64_32S
:
8255 if (!fixp
->fx_pcrel
)
8257 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8258 code
= fixp
->fx_r_type
;
8264 switch (fixp
->fx_size
)
8267 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8268 _("can not do %d byte pc-relative relocation"),
8270 code
= BFD_RELOC_32_PCREL
;
8272 case 1: code
= BFD_RELOC_8_PCREL
; break;
8273 case 2: code
= BFD_RELOC_16_PCREL
; break;
8274 case 4: code
= BFD_RELOC_32_PCREL
; break;
8276 case 8: code
= BFD_RELOC_64_PCREL
; break;
8282 switch (fixp
->fx_size
)
8285 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8286 _("can not do %d byte relocation"),
8288 code
= BFD_RELOC_32
;
8290 case 1: code
= BFD_RELOC_8
; break;
8291 case 2: code
= BFD_RELOC_16
; break;
8292 case 4: code
= BFD_RELOC_32
; break;
8294 case 8: code
= BFD_RELOC_64
; break;
8301 if ((code
== BFD_RELOC_32
8302 || code
== BFD_RELOC_32_PCREL
8303 || code
== BFD_RELOC_X86_64_32S
)
8305 && fixp
->fx_addsy
== GOT_symbol
)
8308 code
= BFD_RELOC_386_GOTPC
;
8310 code
= BFD_RELOC_X86_64_GOTPC32
;
8312 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8314 && fixp
->fx_addsy
== GOT_symbol
)
8316 code
= BFD_RELOC_X86_64_GOTPC64
;
8319 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8320 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8321 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8323 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8325 if (!use_rela_relocations
)
8327 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8328 vtable entry to be used in the relocation's section offset. */
8329 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8330 rel
->address
= fixp
->fx_offset
;
8331 #if defined (OBJ_COFF) && defined (TE_PE)
8332 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8333 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8338 /* Use the rela in 64bit mode. */
8341 if (!fixp
->fx_pcrel
)
8342 rel
->addend
= fixp
->fx_offset
;
8346 case BFD_RELOC_X86_64_PLT32
:
8347 case BFD_RELOC_X86_64_GOT32
:
8348 case BFD_RELOC_X86_64_GOTPCREL
:
8349 case BFD_RELOC_X86_64_TLSGD
:
8350 case BFD_RELOC_X86_64_TLSLD
:
8351 case BFD_RELOC_X86_64_GOTTPOFF
:
8352 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8353 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8354 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8357 rel
->addend
= (section
->vma
8359 + fixp
->fx_addnumber
8360 + md_pcrel_from (fixp
));
8365 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8366 if (rel
->howto
== NULL
)
8368 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8369 _("cannot represent relocation type %s"),
8370 bfd_get_reloc_code_name (code
));
8371 /* Set howto to a garbage value so that we can keep going. */
8372 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8373 gas_assert (rel
->howto
!= NULL
);
8379 #include "tc-i386-intel.c"
8382 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8384 int saved_naked_reg
;
8385 char saved_register_dot
;
8387 saved_naked_reg
= allow_naked_reg
;
8388 allow_naked_reg
= 1;
8389 saved_register_dot
= register_chars
['.'];
8390 register_chars
['.'] = '.';
8391 allow_pseudo_reg
= 1;
8392 expression_and_evaluate (exp
);
8393 allow_pseudo_reg
= 0;
8394 register_chars
['.'] = saved_register_dot
;
8395 allow_naked_reg
= saved_naked_reg
;
8397 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8399 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8401 exp
->X_op
= O_constant
;
8402 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8403 .dw2_regnum
[flag_code
>> 1];
8406 exp
->X_op
= O_illegal
;
8411 tc_x86_frame_initial_instructions (void)
8413 static unsigned int sp_regno
[2];
8415 if (!sp_regno
[flag_code
>> 1])
8417 char *saved_input
= input_line_pointer
;
8418 char sp
[][4] = {"esp", "rsp"};
8421 input_line_pointer
= sp
[flag_code
>> 1];
8422 tc_x86_parse_to_dw2regnum (&exp
);
8423 gas_assert (exp
.X_op
== O_constant
);
8424 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8425 input_line_pointer
= saved_input
;
8428 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8429 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8433 i386_elf_section_type (const char *str
, size_t len
)
8435 if (flag_code
== CODE_64BIT
8436 && len
== sizeof ("unwind") - 1
8437 && strncmp (str
, "unwind", 6) == 0)
8438 return SHT_X86_64_UNWIND
;
8445 i386_solaris_fix_up_eh_frame (segT sec
)
8447 if (flag_code
== CODE_64BIT
)
8448 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8454 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8458 expr
.X_op
= O_secrel
;
8459 expr
.X_add_symbol
= symbol
;
8460 expr
.X_add_number
= 0;
8461 emit_expr (&expr
, size
);
8465 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8466 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8469 x86_64_section_letter (int letter
, char **ptr_msg
)
8471 if (flag_code
== CODE_64BIT
)
8474 return SHF_X86_64_LARGE
;
8476 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8479 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8484 x86_64_section_word (char *str
, size_t len
)
8486 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8487 return SHF_X86_64_LARGE
;
8493 handle_large_common (int small ATTRIBUTE_UNUSED
)
8495 if (flag_code
!= CODE_64BIT
)
8497 s_comm_internal (0, elf_common_parse
);
8498 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8502 static segT lbss_section
;
8503 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8504 asection
*saved_bss_section
= bss_section
;
8506 if (lbss_section
== NULL
)
8508 flagword applicable
;
8510 subsegT subseg
= now_subseg
;
8512 /* The .lbss section is for local .largecomm symbols. */
8513 lbss_section
= subseg_new (".lbss", 0);
8514 applicable
= bfd_applicable_section_flags (stdoutput
);
8515 bfd_set_section_flags (stdoutput
, lbss_section
,
8516 applicable
& SEC_ALLOC
);
8517 seg_info (lbss_section
)->bss
= 1;
8519 subseg_set (seg
, subseg
);
8522 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8523 bss_section
= lbss_section
;
8525 s_comm_internal (0, elf_common_parse
);
8527 elf_com_section_ptr
= saved_com_section_ptr
;
8528 bss_section
= saved_bss_section
;
8531 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */