1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const template *match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "k6", PROCESSOR_K6
,
582 { "k6_2", PROCESSOR_K6
,
584 { "athlon", PROCESSOR_ATHLON
,
586 { "sledgehammer", PROCESSOR_K8
,
588 { "opteron", PROCESSOR_K8
,
590 { "k8", PROCESSOR_K8
,
592 { "amdfam10", PROCESSOR_AMDFAM10
,
593 CPU_AMDFAM10_FLAGS
},
594 { ".mmx", PROCESSOR_UNKNOWN
,
596 { ".sse", PROCESSOR_UNKNOWN
,
598 { ".sse2", PROCESSOR_UNKNOWN
,
600 { ".sse3", PROCESSOR_UNKNOWN
,
602 { ".ssse3", PROCESSOR_UNKNOWN
,
604 { ".sse4.1", PROCESSOR_UNKNOWN
,
606 { ".sse4.2", PROCESSOR_UNKNOWN
,
608 { ".sse4", PROCESSOR_UNKNOWN
,
610 { ".avx", PROCESSOR_UNKNOWN
,
612 { ".vmx", PROCESSOR_UNKNOWN
,
614 { ".smx", PROCESSOR_UNKNOWN
,
616 { ".xsave", PROCESSOR_UNKNOWN
,
618 { ".aes", PROCESSOR_UNKNOWN
,
620 { ".pclmul", PROCESSOR_UNKNOWN
,
622 { ".clmul", PROCESSOR_UNKNOWN
,
624 { ".fma", PROCESSOR_UNKNOWN
,
626 { ".movbe", PROCESSOR_UNKNOWN
,
628 { ".ept", PROCESSOR_UNKNOWN
,
630 { ".clflush", PROCESSOR_UNKNOWN
,
632 { ".syscall", PROCESSOR_UNKNOWN
,
634 { ".rdtscp", PROCESSOR_UNKNOWN
,
636 { ".3dnow", PROCESSOR_UNKNOWN
,
638 { ".3dnowa", PROCESSOR_UNKNOWN
,
640 { ".padlock", PROCESSOR_UNKNOWN
,
642 { ".pacifica", PROCESSOR_UNKNOWN
,
644 { ".svme", PROCESSOR_UNKNOWN
,
646 { ".sse4a", PROCESSOR_UNKNOWN
,
648 { ".abm", PROCESSOR_UNKNOWN
,
653 /* Like s_lcomm_internal in gas/read.c but the alignment string
654 is allowed to be optional. */
657 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
664 && *input_line_pointer
== ',')
666 align
= parse_align (needs_align
- 1);
668 if (align
== (addressT
) -1)
683 bss_alloc (symbolP
, size
, align
);
688 pe_lcomm (int needs_align
)
690 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
694 const pseudo_typeS md_pseudo_table
[] =
696 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
697 {"align", s_align_bytes
, 0},
699 {"align", s_align_ptwo
, 0},
701 {"arch", set_cpu_arch
, 0},
705 {"lcomm", pe_lcomm
, 1},
707 {"ffloat", float_cons
, 'f'},
708 {"dfloat", float_cons
, 'd'},
709 {"tfloat", float_cons
, 'x'},
711 {"slong", signed_cons
, 4},
712 {"noopt", s_ignore
, 0},
713 {"optim", s_ignore
, 0},
714 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
715 {"code16", set_code_flag
, CODE_16BIT
},
716 {"code32", set_code_flag
, CODE_32BIT
},
717 {"code64", set_code_flag
, CODE_64BIT
},
718 {"intel_syntax", set_intel_syntax
, 1},
719 {"att_syntax", set_intel_syntax
, 0},
720 {"intel_mnemonic", set_intel_mnemonic
, 1},
721 {"att_mnemonic", set_intel_mnemonic
, 0},
722 {"allow_index_reg", set_allow_index_reg
, 1},
723 {"disallow_index_reg", set_allow_index_reg
, 0},
724 {"sse_check", set_sse_check
, 0},
725 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
726 {"largecomm", handle_large_common
, 0},
728 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
729 {"loc", dwarf2_directive_loc
, 0},
730 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
733 {"secrel32", pe_directive_secrel
, 0},
738 /* For interface with expression (). */
739 extern char *input_line_pointer
;
741 /* Hash table for instruction mnemonic lookup. */
742 static struct hash_control
*op_hash
;
744 /* Hash table for register lookup. */
745 static struct hash_control
*reg_hash
;
748 i386_align_code (fragS
*fragP
, int count
)
750 /* Various efficient no-op patterns for aligning code labels.
751 Note: Don't try to assemble the instructions in the comments.
752 0L and 0w are not legal. */
753 static const char f32_1
[] =
755 static const char f32_2
[] =
756 {0x66,0x90}; /* xchg %ax,%ax */
757 static const char f32_3
[] =
758 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
759 static const char f32_4
[] =
760 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
761 static const char f32_5
[] =
763 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
764 static const char f32_6
[] =
765 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
766 static const char f32_7
[] =
767 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
768 static const char f32_8
[] =
770 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
771 static const char f32_9
[] =
772 {0x89,0xf6, /* movl %esi,%esi */
773 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
774 static const char f32_10
[] =
775 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
776 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
777 static const char f32_11
[] =
778 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
779 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
780 static const char f32_12
[] =
781 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
782 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
783 static const char f32_13
[] =
784 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
785 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
786 static const char f32_14
[] =
787 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
788 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
789 static const char f16_3
[] =
790 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
791 static const char f16_4
[] =
792 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
793 static const char f16_5
[] =
795 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
796 static const char f16_6
[] =
797 {0x89,0xf6, /* mov %si,%si */
798 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
799 static const char f16_7
[] =
800 {0x8d,0x74,0x00, /* lea 0(%si),%si */
801 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
802 static const char f16_8
[] =
803 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
804 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
805 static const char jump_31
[] =
806 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
807 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
808 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
809 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
810 static const char *const f32_patt
[] = {
811 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
812 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
814 static const char *const f16_patt
[] = {
815 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
818 static const char alt_3
[] =
820 /* nopl 0(%[re]ax) */
821 static const char alt_4
[] =
822 {0x0f,0x1f,0x40,0x00};
823 /* nopl 0(%[re]ax,%[re]ax,1) */
824 static const char alt_5
[] =
825 {0x0f,0x1f,0x44,0x00,0x00};
826 /* nopw 0(%[re]ax,%[re]ax,1) */
827 static const char alt_6
[] =
828 {0x66,0x0f,0x1f,0x44,0x00,0x00};
829 /* nopl 0L(%[re]ax) */
830 static const char alt_7
[] =
831 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
832 /* nopl 0L(%[re]ax,%[re]ax,1) */
833 static const char alt_8
[] =
834 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
835 /* nopw 0L(%[re]ax,%[re]ax,1) */
836 static const char alt_9
[] =
837 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
838 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
839 static const char alt_10
[] =
840 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
842 nopw %cs:0L(%[re]ax,%[re]ax,1) */
843 static const char alt_long_11
[] =
845 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
848 nopw %cs:0L(%[re]ax,%[re]ax,1) */
849 static const char alt_long_12
[] =
852 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
856 nopw %cs:0L(%[re]ax,%[re]ax,1) */
857 static const char alt_long_13
[] =
861 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
866 nopw %cs:0L(%[re]ax,%[re]ax,1) */
867 static const char alt_long_14
[] =
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
878 nopw %cs:0L(%[re]ax,%[re]ax,1) */
879 static const char alt_long_15
[] =
885 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
886 /* nopl 0(%[re]ax,%[re]ax,1)
887 nopw 0(%[re]ax,%[re]ax,1) */
888 static const char alt_short_11
[] =
889 {0x0f,0x1f,0x44,0x00,0x00,
890 0x66,0x0f,0x1f,0x44,0x00,0x00};
891 /* nopw 0(%[re]ax,%[re]ax,1)
892 nopw 0(%[re]ax,%[re]ax,1) */
893 static const char alt_short_12
[] =
894 {0x66,0x0f,0x1f,0x44,0x00,0x00,
895 0x66,0x0f,0x1f,0x44,0x00,0x00};
896 /* nopw 0(%[re]ax,%[re]ax,1)
898 static const char alt_short_13
[] =
899 {0x66,0x0f,0x1f,0x44,0x00,0x00,
900 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
903 static const char alt_short_14
[] =
904 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
905 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
907 nopl 0L(%[re]ax,%[re]ax,1) */
908 static const char alt_short_15
[] =
909 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
910 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 static const char *const alt_short_patt
[] = {
912 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
913 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
914 alt_short_14
, alt_short_15
916 static const char *const alt_long_patt
[] = {
917 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
918 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
919 alt_long_14
, alt_long_15
922 /* Only align for at least a positive non-zero boundary. */
923 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
926 /* We need to decide which NOP sequence to use for 32bit and
927 64bit. When -mtune= is used:
929 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
930 PROCESSOR_GENERIC32, f32_patt will be used.
931 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
932 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
933 PROCESSOR_GENERIC64, alt_long_patt will be used.
934 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
935 PROCESSOR_AMDFAM10, alt_short_patt will be used.
937 When -mtune= isn't used, alt_long_patt will be used if
938 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
941 When -march= or .arch is used, we can't use anything beyond
942 cpu_arch_isa_flags. */
944 if (flag_code
== CODE_16BIT
)
948 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
950 /* Adjust jump offset. */
951 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
954 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
955 f16_patt
[count
- 1], count
);
959 const char *const *patt
= NULL
;
961 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
963 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
964 switch (cpu_arch_tune
)
966 case PROCESSOR_UNKNOWN
:
967 /* We use cpu_arch_isa_flags to check if we SHOULD
968 optimize for Cpu686. */
969 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
970 patt
= alt_long_patt
;
974 case PROCESSOR_PENTIUMPRO
:
975 case PROCESSOR_PENTIUM4
:
976 case PROCESSOR_NOCONA
:
978 case PROCESSOR_CORE2
:
979 case PROCESSOR_COREI7
:
980 case PROCESSOR_GENERIC64
:
981 patt
= alt_long_patt
;
984 case PROCESSOR_ATHLON
:
986 case PROCESSOR_AMDFAM10
:
987 patt
= alt_short_patt
;
991 case PROCESSOR_PENTIUM
:
992 case PROCESSOR_GENERIC32
:
999 switch (fragP
->tc_frag_data
.tune
)
1001 case PROCESSOR_UNKNOWN
:
1002 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1003 PROCESSOR_UNKNOWN. */
1007 case PROCESSOR_I386
:
1008 case PROCESSOR_I486
:
1009 case PROCESSOR_PENTIUM
:
1011 case PROCESSOR_ATHLON
:
1013 case PROCESSOR_AMDFAM10
:
1014 case PROCESSOR_GENERIC32
:
1015 /* We use cpu_arch_isa_flags to check if we CAN optimize
1017 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1018 patt
= alt_short_patt
;
1022 case PROCESSOR_PENTIUMPRO
:
1023 case PROCESSOR_PENTIUM4
:
1024 case PROCESSOR_NOCONA
:
1025 case PROCESSOR_CORE
:
1026 case PROCESSOR_CORE2
:
1027 case PROCESSOR_COREI7
:
1028 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1029 patt
= alt_long_patt
;
1033 case PROCESSOR_GENERIC64
:
1034 patt
= alt_long_patt
;
1039 if (patt
== f32_patt
)
1041 /* If the padding is less than 15 bytes, we use the normal
1042 ones. Otherwise, we use a jump instruction and adjust
1045 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1046 patt
[count
- 1], count
);
1049 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1051 /* Adjust jump offset. */
1052 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1057 /* Maximum length of an instruction is 15 byte. If the
1058 padding is greater than 15 bytes and we don't use jump,
1059 we have to break it into smaller pieces. */
1060 int padding
= count
;
1061 while (padding
> 15)
1064 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1069 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1070 patt
[padding
- 1], padding
);
1073 fragP
->fr_var
= count
;
1077 operand_type_all_zero (const union i386_operand_type
*x
)
1079 switch (ARRAY_SIZE(x
->array
))
1088 return !x
->array
[0];
1095 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1097 switch (ARRAY_SIZE(x
->array
))
1112 operand_type_equal (const union i386_operand_type
*x
,
1113 const union i386_operand_type
*y
)
1115 switch (ARRAY_SIZE(x
->array
))
1118 if (x
->array
[2] != y
->array
[2])
1121 if (x
->array
[1] != y
->array
[1])
1124 return x
->array
[0] == y
->array
[0];
1132 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1134 switch (ARRAY_SIZE(x
->array
))
1143 return !x
->array
[0];
1150 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1152 switch (ARRAY_SIZE(x
->array
))
1167 cpu_flags_equal (const union i386_cpu_flags
*x
,
1168 const union i386_cpu_flags
*y
)
1170 switch (ARRAY_SIZE(x
->array
))
1173 if (x
->array
[2] != y
->array
[2])
1176 if (x
->array
[1] != y
->array
[1])
1179 return x
->array
[0] == y
->array
[0];
1187 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1189 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1190 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1193 static INLINE i386_cpu_flags
1194 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1196 switch (ARRAY_SIZE (x
.array
))
1199 x
.array
[2] &= y
.array
[2];
1201 x
.array
[1] &= y
.array
[1];
1203 x
.array
[0] &= y
.array
[0];
1211 static INLINE i386_cpu_flags
1212 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1214 switch (ARRAY_SIZE (x
.array
))
1217 x
.array
[2] |= y
.array
[2];
1219 x
.array
[1] |= y
.array
[1];
1221 x
.array
[0] |= y
.array
[0];
1229 #define CPU_FLAGS_ARCH_MATCH 0x1
1230 #define CPU_FLAGS_64BIT_MATCH 0x2
1231 #define CPU_FLAGS_AES_MATCH 0x4
1232 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1233 #define CPU_FLAGS_AVX_MATCH 0x10
1235 #define CPU_FLAGS_32BIT_MATCH \
1236 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1237 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1238 #define CPU_FLAGS_PERFECT_MATCH \
1239 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1241 /* Return CPU flags match bits. */
1244 cpu_flags_match (const template *t
)
1246 i386_cpu_flags x
= t
->cpu_flags
;
1247 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1249 x
.bitfield
.cpu64
= 0;
1250 x
.bitfield
.cpuno64
= 0;
1252 if (cpu_flags_all_zero (&x
))
1254 /* This instruction is available on all archs. */
1255 match
|= CPU_FLAGS_32BIT_MATCH
;
1259 /* This instruction is available only on some archs. */
1260 i386_cpu_flags cpu
= cpu_arch_flags
;
1262 cpu
.bitfield
.cpu64
= 0;
1263 cpu
.bitfield
.cpuno64
= 0;
1264 cpu
= cpu_flags_and (x
, cpu
);
1265 if (!cpu_flags_all_zero (&cpu
))
1267 if (x
.bitfield
.cpuavx
)
1269 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1270 if (cpu
.bitfield
.cpuavx
)
1272 /* Check SSE2AVX. */
1273 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1275 match
|= (CPU_FLAGS_ARCH_MATCH
1276 | CPU_FLAGS_AVX_MATCH
);
1278 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1279 match
|= CPU_FLAGS_AES_MATCH
;
1281 if (!x
.bitfield
.cpupclmul
1282 || cpu
.bitfield
.cpupclmul
)
1283 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1287 match
|= CPU_FLAGS_ARCH_MATCH
;
1290 match
|= CPU_FLAGS_32BIT_MATCH
;
1296 static INLINE i386_operand_type
1297 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1299 switch (ARRAY_SIZE (x
.array
))
1302 x
.array
[2] &= y
.array
[2];
1304 x
.array
[1] &= y
.array
[1];
1306 x
.array
[0] &= y
.array
[0];
1314 static INLINE i386_operand_type
1315 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1317 switch (ARRAY_SIZE (x
.array
))
1320 x
.array
[2] |= y
.array
[2];
1322 x
.array
[1] |= y
.array
[1];
1324 x
.array
[0] |= y
.array
[0];
1332 static INLINE i386_operand_type
1333 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1335 switch (ARRAY_SIZE (x
.array
))
1338 x
.array
[2] ^= y
.array
[2];
1340 x
.array
[1] ^= y
.array
[1];
1342 x
.array
[0] ^= y
.array
[0];
1350 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1351 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1352 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1353 static const i386_operand_type inoutportreg
1354 = OPERAND_TYPE_INOUTPORTREG
;
1355 static const i386_operand_type reg16_inoutportreg
1356 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1357 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1358 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1359 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1360 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1361 static const i386_operand_type anydisp
1362 = OPERAND_TYPE_ANYDISP
;
1363 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1364 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1365 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1366 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1367 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1368 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1369 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1370 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1371 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1372 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1373 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1384 operand_type_check (i386_operand_type t
, enum operand_type c
)
1389 return (t
.bitfield
.reg8
1392 || t
.bitfield
.reg64
);
1395 return (t
.bitfield
.imm8
1399 || t
.bitfield
.imm32s
1400 || t
.bitfield
.imm64
);
1403 return (t
.bitfield
.disp8
1404 || t
.bitfield
.disp16
1405 || t
.bitfield
.disp32
1406 || t
.bitfield
.disp32s
1407 || t
.bitfield
.disp64
);
1410 return (t
.bitfield
.disp8
1411 || t
.bitfield
.disp16
1412 || t
.bitfield
.disp32
1413 || t
.bitfield
.disp32s
1414 || t
.bitfield
.disp64
1415 || t
.bitfield
.baseindex
);
1424 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1425 operand J for instruction template T. */
1428 match_reg_size (const template *t
, unsigned int j
)
1430 return !((i
.types
[j
].bitfield
.byte
1431 && !t
->operand_types
[j
].bitfield
.byte
)
1432 || (i
.types
[j
].bitfield
.word
1433 && !t
->operand_types
[j
].bitfield
.word
)
1434 || (i
.types
[j
].bitfield
.dword
1435 && !t
->operand_types
[j
].bitfield
.dword
)
1436 || (i
.types
[j
].bitfield
.qword
1437 && !t
->operand_types
[j
].bitfield
.qword
));
1440 /* Return 1 if there is no conflict in any size on operand J for
1441 instruction template T. */
1444 match_mem_size (const template *t
, unsigned int j
)
1446 return (match_reg_size (t
, j
)
1447 && !((i
.types
[j
].bitfield
.unspecified
1448 && !t
->operand_types
[j
].bitfield
.unspecified
)
1449 || (i
.types
[j
].bitfield
.fword
1450 && !t
->operand_types
[j
].bitfield
.fword
)
1451 || (i
.types
[j
].bitfield
.tbyte
1452 && !t
->operand_types
[j
].bitfield
.tbyte
)
1453 || (i
.types
[j
].bitfield
.xmmword
1454 && !t
->operand_types
[j
].bitfield
.xmmword
)
1455 || (i
.types
[j
].bitfield
.ymmword
1456 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1459 /* Return 1 if there is no size conflict on any operands for
1460 instruction template T. */
1463 operand_size_match (const template *t
)
1468 /* Don't check jump instructions. */
1469 if (t
->opcode_modifier
.jump
1470 || t
->opcode_modifier
.jumpbyte
1471 || t
->opcode_modifier
.jumpdword
1472 || t
->opcode_modifier
.jumpintersegment
)
1475 /* Check memory and accumulator operand size. */
1476 for (j
= 0; j
< i
.operands
; j
++)
1478 if (t
->operand_types
[j
].bitfield
.anysize
)
1481 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1487 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1495 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1498 /* Check reverse. */
1499 gas_assert (i
.operands
== 2);
1502 for (j
= 0; j
< 2; j
++)
1504 if (t
->operand_types
[j
].bitfield
.acc
1505 && !match_reg_size (t
, j
? 0 : 1))
1511 if (i
.types
[j
].bitfield
.mem
1512 && !match_mem_size (t
, j
? 0 : 1))
1523 operand_type_match (i386_operand_type overlap
,
1524 i386_operand_type given
)
1526 i386_operand_type temp
= overlap
;
1528 temp
.bitfield
.jumpabsolute
= 0;
1529 temp
.bitfield
.unspecified
= 0;
1530 temp
.bitfield
.byte
= 0;
1531 temp
.bitfield
.word
= 0;
1532 temp
.bitfield
.dword
= 0;
1533 temp
.bitfield
.fword
= 0;
1534 temp
.bitfield
.qword
= 0;
1535 temp
.bitfield
.tbyte
= 0;
1536 temp
.bitfield
.xmmword
= 0;
1537 temp
.bitfield
.ymmword
= 0;
1538 if (operand_type_all_zero (&temp
))
1541 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1542 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1545 /* If given types g0 and g1 are registers they must be of the same type
1546 unless the expected operand type register overlap is null.
1547 Note that Acc in a template matches every size of reg. */
1550 operand_type_register_match (i386_operand_type m0
,
1551 i386_operand_type g0
,
1552 i386_operand_type t0
,
1553 i386_operand_type m1
,
1554 i386_operand_type g1
,
1555 i386_operand_type t1
)
1557 if (!operand_type_check (g0
, reg
))
1560 if (!operand_type_check (g1
, reg
))
1563 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1564 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1565 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1566 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1569 if (m0
.bitfield
.acc
)
1571 t0
.bitfield
.reg8
= 1;
1572 t0
.bitfield
.reg16
= 1;
1573 t0
.bitfield
.reg32
= 1;
1574 t0
.bitfield
.reg64
= 1;
1577 if (m1
.bitfield
.acc
)
1579 t1
.bitfield
.reg8
= 1;
1580 t1
.bitfield
.reg16
= 1;
1581 t1
.bitfield
.reg32
= 1;
1582 t1
.bitfield
.reg64
= 1;
1585 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1586 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1587 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1588 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1591 static INLINE
unsigned int
1592 mode_from_disp_size (i386_operand_type t
)
1594 if (t
.bitfield
.disp8
)
1596 else if (t
.bitfield
.disp16
1597 || t
.bitfield
.disp32
1598 || t
.bitfield
.disp32s
)
1605 fits_in_signed_byte (offsetT num
)
1607 return (num
>= -128) && (num
<= 127);
1611 fits_in_unsigned_byte (offsetT num
)
1613 return (num
& 0xff) == num
;
1617 fits_in_unsigned_word (offsetT num
)
1619 return (num
& 0xffff) == num
;
1623 fits_in_signed_word (offsetT num
)
1625 return (-32768 <= num
) && (num
<= 32767);
1629 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1634 return (!(((offsetT
) -1 << 31) & num
)
1635 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1637 } /* fits_in_signed_long() */
1640 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1645 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1647 } /* fits_in_unsigned_long() */
1649 static i386_operand_type
1650 smallest_imm_type (offsetT num
)
1652 i386_operand_type t
;
1654 operand_type_set (&t
, 0);
1655 t
.bitfield
.imm64
= 1;
1657 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1659 /* This code is disabled on the 486 because all the Imm1 forms
1660 in the opcode table are slower on the i486. They're the
1661 versions with the implicitly specified single-position
1662 displacement, which has another syntax if you really want to
1664 t
.bitfield
.imm1
= 1;
1665 t
.bitfield
.imm8
= 1;
1666 t
.bitfield
.imm8s
= 1;
1667 t
.bitfield
.imm16
= 1;
1668 t
.bitfield
.imm32
= 1;
1669 t
.bitfield
.imm32s
= 1;
1671 else if (fits_in_signed_byte (num
))
1673 t
.bitfield
.imm8
= 1;
1674 t
.bitfield
.imm8s
= 1;
1675 t
.bitfield
.imm16
= 1;
1676 t
.bitfield
.imm32
= 1;
1677 t
.bitfield
.imm32s
= 1;
1679 else if (fits_in_unsigned_byte (num
))
1681 t
.bitfield
.imm8
= 1;
1682 t
.bitfield
.imm16
= 1;
1683 t
.bitfield
.imm32
= 1;
1684 t
.bitfield
.imm32s
= 1;
1686 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1688 t
.bitfield
.imm16
= 1;
1689 t
.bitfield
.imm32
= 1;
1690 t
.bitfield
.imm32s
= 1;
1692 else if (fits_in_signed_long (num
))
1694 t
.bitfield
.imm32
= 1;
1695 t
.bitfield
.imm32s
= 1;
1697 else if (fits_in_unsigned_long (num
))
1698 t
.bitfield
.imm32
= 1;
1704 offset_in_range (offsetT val
, int size
)
1710 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1711 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1712 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1714 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1719 /* If BFD64, sign extend val. */
1720 if (!use_rela_relocations
)
1721 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1722 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1724 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1726 char buf1
[40], buf2
[40];
1728 sprint_value (buf1
, val
);
1729 sprint_value (buf2
, val
& mask
);
1730 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1735 /* Returns 0 if attempting to add a prefix where one from the same
1736 class already exists, 1 if non rep/repne added, 2 if rep/repne
1739 add_prefix (unsigned int prefix
)
1744 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1745 && flag_code
== CODE_64BIT
)
1747 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1748 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1749 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1760 case CS_PREFIX_OPCODE
:
1761 case DS_PREFIX_OPCODE
:
1762 case ES_PREFIX_OPCODE
:
1763 case FS_PREFIX_OPCODE
:
1764 case GS_PREFIX_OPCODE
:
1765 case SS_PREFIX_OPCODE
:
1769 case REPNE_PREFIX_OPCODE
:
1770 case REPE_PREFIX_OPCODE
:
1773 case LOCK_PREFIX_OPCODE
:
1781 case ADDR_PREFIX_OPCODE
:
1785 case DATA_PREFIX_OPCODE
:
1789 if (i
.prefix
[q
] != 0)
1797 i
.prefix
[q
] |= prefix
;
1800 as_bad (_("same type of prefix used twice"));
1806 set_code_flag (int value
)
1809 if (flag_code
== CODE_64BIT
)
1811 cpu_arch_flags
.bitfield
.cpu64
= 1;
1812 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1816 cpu_arch_flags
.bitfield
.cpu64
= 0;
1817 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1819 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1821 as_bad (_("64bit mode not supported on this CPU."));
1823 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1825 as_bad (_("32bit mode not supported on this CPU."));
1827 stackop_size
= '\0';
1831 set_16bit_gcc_code_flag (int new_code_flag
)
1833 flag_code
= new_code_flag
;
1834 if (flag_code
!= CODE_16BIT
)
1836 cpu_arch_flags
.bitfield
.cpu64
= 0;
1837 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1838 stackop_size
= LONG_MNEM_SUFFIX
;
1842 set_intel_syntax (int syntax_flag
)
1844 /* Find out if register prefixing is specified. */
1845 int ask_naked_reg
= 0;
1848 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1850 char *string
= input_line_pointer
;
1851 int e
= get_symbol_end ();
1853 if (strcmp (string
, "prefix") == 0)
1855 else if (strcmp (string
, "noprefix") == 0)
1858 as_bad (_("bad argument to syntax directive."));
1859 *input_line_pointer
= e
;
1861 demand_empty_rest_of_line ();
1863 intel_syntax
= syntax_flag
;
1865 if (ask_naked_reg
== 0)
1866 allow_naked_reg
= (intel_syntax
1867 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1869 allow_naked_reg
= (ask_naked_reg
< 0);
1871 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1873 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1874 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1875 register_prefix
= allow_naked_reg
? "" : "%";
1879 set_intel_mnemonic (int mnemonic_flag
)
1881 intel_mnemonic
= mnemonic_flag
;
1885 set_allow_index_reg (int flag
)
1887 allow_index_reg
= flag
;
1891 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1895 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1897 char *string
= input_line_pointer
;
1898 int e
= get_symbol_end ();
1900 if (strcmp (string
, "none") == 0)
1901 sse_check
= sse_check_none
;
1902 else if (strcmp (string
, "warning") == 0)
1903 sse_check
= sse_check_warning
;
1904 else if (strcmp (string
, "error") == 0)
1905 sse_check
= sse_check_error
;
1907 as_bad (_("bad argument to sse_check directive."));
1908 *input_line_pointer
= e
;
1911 as_bad (_("missing argument for sse_check directive"));
1913 demand_empty_rest_of_line ();
1917 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1921 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1923 char *string
= input_line_pointer
;
1924 int e
= get_symbol_end ();
1926 i386_cpu_flags flags
;
1928 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1930 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1934 cpu_arch_name
= cpu_arch
[i
].name
;
1935 cpu_sub_arch_name
= NULL
;
1936 cpu_arch_flags
= cpu_arch
[i
].flags
;
1937 if (flag_code
== CODE_64BIT
)
1939 cpu_arch_flags
.bitfield
.cpu64
= 1;
1940 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1944 cpu_arch_flags
.bitfield
.cpu64
= 0;
1945 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1947 cpu_arch_isa
= cpu_arch
[i
].type
;
1948 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1949 if (!cpu_arch_tune_set
)
1951 cpu_arch_tune
= cpu_arch_isa
;
1952 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1957 flags
= cpu_flags_or (cpu_arch_flags
,
1959 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1961 if (cpu_sub_arch_name
)
1963 char *name
= cpu_sub_arch_name
;
1964 cpu_sub_arch_name
= concat (name
,
1966 (const char *) NULL
);
1970 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
1971 cpu_arch_flags
= flags
;
1973 *input_line_pointer
= e
;
1974 demand_empty_rest_of_line ();
1978 if (i
>= ARRAY_SIZE (cpu_arch
))
1979 as_bad (_("no such architecture: `%s'"), string
);
1981 *input_line_pointer
= e
;
1984 as_bad (_("missing cpu architecture"));
1986 no_cond_jump_promotion
= 0;
1987 if (*input_line_pointer
== ','
1988 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
1990 char *string
= ++input_line_pointer
;
1991 int e
= get_symbol_end ();
1993 if (strcmp (string
, "nojumps") == 0)
1994 no_cond_jump_promotion
= 1;
1995 else if (strcmp (string
, "jumps") == 0)
1998 as_bad (_("no such architecture modifier: `%s'"), string
);
2000 *input_line_pointer
= e
;
2003 demand_empty_rest_of_line ();
2009 if (!strcmp (default_arch
, "x86_64"))
2010 return bfd_mach_x86_64
;
2011 else if (!strcmp (default_arch
, "i386"))
2012 return bfd_mach_i386_i386
;
2014 as_fatal (_("Unknown architecture"));
2020 const char *hash_err
;
2022 /* Initialize op_hash hash table. */
2023 op_hash
= hash_new ();
2026 const template *optab
;
2027 templates
*core_optab
;
2029 /* Setup for loop. */
2031 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2032 core_optab
->start
= optab
;
2037 if (optab
->name
== NULL
2038 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2040 /* different name --> ship out current template list;
2041 add to hash table; & begin anew. */
2042 core_optab
->end
= optab
;
2043 hash_err
= hash_insert (op_hash
,
2045 (void *) core_optab
);
2048 as_fatal (_("Internal Error: Can't hash %s: %s"),
2052 if (optab
->name
== NULL
)
2054 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2055 core_optab
->start
= optab
;
2060 /* Initialize reg_hash hash table. */
2061 reg_hash
= hash_new ();
2063 const reg_entry
*regtab
;
2064 unsigned int regtab_size
= i386_regtab_size
;
2066 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2068 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2070 as_fatal (_("Internal Error: Can't hash %s: %s"),
2076 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2081 for (c
= 0; c
< 256; c
++)
2086 mnemonic_chars
[c
] = c
;
2087 register_chars
[c
] = c
;
2088 operand_chars
[c
] = c
;
2090 else if (ISLOWER (c
))
2092 mnemonic_chars
[c
] = c
;
2093 register_chars
[c
] = c
;
2094 operand_chars
[c
] = c
;
2096 else if (ISUPPER (c
))
2098 mnemonic_chars
[c
] = TOLOWER (c
);
2099 register_chars
[c
] = mnemonic_chars
[c
];
2100 operand_chars
[c
] = c
;
2103 if (ISALPHA (c
) || ISDIGIT (c
))
2104 identifier_chars
[c
] = c
;
2107 identifier_chars
[c
] = c
;
2108 operand_chars
[c
] = c
;
2113 identifier_chars
['@'] = '@';
2116 identifier_chars
['?'] = '?';
2117 operand_chars
['?'] = '?';
2119 digit_chars
['-'] = '-';
2120 mnemonic_chars
['_'] = '_';
2121 mnemonic_chars
['-'] = '-';
2122 mnemonic_chars
['.'] = '.';
2123 identifier_chars
['_'] = '_';
2124 identifier_chars
['.'] = '.';
2126 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2127 operand_chars
[(unsigned char) *p
] = *p
;
2130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2133 record_alignment (text_section
, 2);
2134 record_alignment (data_section
, 2);
2135 record_alignment (bss_section
, 2);
2139 if (flag_code
== CODE_64BIT
)
2141 x86_dwarf2_return_column
= 16;
2142 x86_cie_data_alignment
= -8;
2146 x86_dwarf2_return_column
= 8;
2147 x86_cie_data_alignment
= -4;
2152 i386_print_statistics (FILE *file
)
2154 hash_print_statistics (file
, "i386 opcode", op_hash
);
2155 hash_print_statistics (file
, "i386 register", reg_hash
);
2160 /* Debugging routines for md_assemble. */
2161 static void pte (template *);
2162 static void pt (i386_operand_type
);
2163 static void pe (expressionS
*);
2164 static void ps (symbolS
*);
2167 pi (char *line
, i386_insn
*x
)
2171 fprintf (stdout
, "%s: template ", line
);
2173 fprintf (stdout
, " address: base %s index %s scale %x\n",
2174 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2175 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2176 x
->log2_scale_factor
);
2177 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2178 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2179 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2180 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2181 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2182 (x
->rex
& REX_W
) != 0,
2183 (x
->rex
& REX_R
) != 0,
2184 (x
->rex
& REX_X
) != 0,
2185 (x
->rex
& REX_B
) != 0);
2186 for (i
= 0; i
< x
->operands
; i
++)
2188 fprintf (stdout
, " #%d: ", i
+ 1);
2190 fprintf (stdout
, "\n");
2191 if (x
->types
[i
].bitfield
.reg8
2192 || x
->types
[i
].bitfield
.reg16
2193 || x
->types
[i
].bitfield
.reg32
2194 || x
->types
[i
].bitfield
.reg64
2195 || x
->types
[i
].bitfield
.regmmx
2196 || x
->types
[i
].bitfield
.regxmm
2197 || x
->types
[i
].bitfield
.regymm
2198 || x
->types
[i
].bitfield
.sreg2
2199 || x
->types
[i
].bitfield
.sreg3
2200 || x
->types
[i
].bitfield
.control
2201 || x
->types
[i
].bitfield
.debug
2202 || x
->types
[i
].bitfield
.test
)
2203 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2204 if (operand_type_check (x
->types
[i
], imm
))
2206 if (operand_type_check (x
->types
[i
], disp
))
2207 pe (x
->op
[i
].disps
);
2215 fprintf (stdout
, " %d operands ", t
->operands
);
2216 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2217 if (t
->extension_opcode
!= None
)
2218 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2219 if (t
->opcode_modifier
.d
)
2220 fprintf (stdout
, "D");
2221 if (t
->opcode_modifier
.w
)
2222 fprintf (stdout
, "W");
2223 fprintf (stdout
, "\n");
2224 for (i
= 0; i
< t
->operands
; i
++)
2226 fprintf (stdout
, " #%d type ", i
+ 1);
2227 pt (t
->operand_types
[i
]);
2228 fprintf (stdout
, "\n");
2235 fprintf (stdout
, " operation %d\n", e
->X_op
);
2236 fprintf (stdout
, " add_number %ld (%lx)\n",
2237 (long) e
->X_add_number
, (long) e
->X_add_number
);
2238 if (e
->X_add_symbol
)
2240 fprintf (stdout
, " add_symbol ");
2241 ps (e
->X_add_symbol
);
2242 fprintf (stdout
, "\n");
2246 fprintf (stdout
, " op_symbol ");
2247 ps (e
->X_op_symbol
);
2248 fprintf (stdout
, "\n");
2255 fprintf (stdout
, "%s type %s%s",
2257 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2258 segment_name (S_GET_SEGMENT (s
)));
2261 static struct type_name
2263 i386_operand_type mask
;
2266 const type_names
[] =
2268 { OPERAND_TYPE_REG8
, "r8" },
2269 { OPERAND_TYPE_REG16
, "r16" },
2270 { OPERAND_TYPE_REG32
, "r32" },
2271 { OPERAND_TYPE_REG64
, "r64" },
2272 { OPERAND_TYPE_IMM8
, "i8" },
2273 { OPERAND_TYPE_IMM8
, "i8s" },
2274 { OPERAND_TYPE_IMM16
, "i16" },
2275 { OPERAND_TYPE_IMM32
, "i32" },
2276 { OPERAND_TYPE_IMM32S
, "i32s" },
2277 { OPERAND_TYPE_IMM64
, "i64" },
2278 { OPERAND_TYPE_IMM1
, "i1" },
2279 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2280 { OPERAND_TYPE_DISP8
, "d8" },
2281 { OPERAND_TYPE_DISP16
, "d16" },
2282 { OPERAND_TYPE_DISP32
, "d32" },
2283 { OPERAND_TYPE_DISP32S
, "d32s" },
2284 { OPERAND_TYPE_DISP64
, "d64" },
2285 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2286 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2287 { OPERAND_TYPE_CONTROL
, "control reg" },
2288 { OPERAND_TYPE_TEST
, "test reg" },
2289 { OPERAND_TYPE_DEBUG
, "debug reg" },
2290 { OPERAND_TYPE_FLOATREG
, "FReg" },
2291 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2292 { OPERAND_TYPE_SREG2
, "SReg2" },
2293 { OPERAND_TYPE_SREG3
, "SReg3" },
2294 { OPERAND_TYPE_ACC
, "Acc" },
2295 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2296 { OPERAND_TYPE_REGMMX
, "rMMX" },
2297 { OPERAND_TYPE_REGXMM
, "rXMM" },
2298 { OPERAND_TYPE_REGYMM
, "rYMM" },
2299 { OPERAND_TYPE_ESSEG
, "es" },
2303 pt (i386_operand_type t
)
2306 i386_operand_type a
;
2308 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2310 a
= operand_type_and (t
, type_names
[j
].mask
);
2311 if (!operand_type_all_zero (&a
))
2312 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2317 #endif /* DEBUG386 */
2319 static bfd_reloc_code_real_type
2320 reloc (unsigned int size
,
2323 bfd_reloc_code_real_type other
)
2325 if (other
!= NO_RELOC
)
2327 reloc_howto_type
*reloc
;
2332 case BFD_RELOC_X86_64_GOT32
:
2333 return BFD_RELOC_X86_64_GOT64
;
2335 case BFD_RELOC_X86_64_PLTOFF64
:
2336 return BFD_RELOC_X86_64_PLTOFF64
;
2338 case BFD_RELOC_X86_64_GOTPC32
:
2339 other
= BFD_RELOC_X86_64_GOTPC64
;
2341 case BFD_RELOC_X86_64_GOTPCREL
:
2342 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2344 case BFD_RELOC_X86_64_TPOFF32
:
2345 other
= BFD_RELOC_X86_64_TPOFF64
;
2347 case BFD_RELOC_X86_64_DTPOFF32
:
2348 other
= BFD_RELOC_X86_64_DTPOFF64
;
2354 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2355 if (size
== 4 && flag_code
!= CODE_64BIT
)
2358 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2360 as_bad (_("unknown relocation (%u)"), other
);
2361 else if (size
!= bfd_get_reloc_size (reloc
))
2362 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2363 bfd_get_reloc_size (reloc
),
2365 else if (pcrel
&& !reloc
->pc_relative
)
2366 as_bad (_("non-pc-relative relocation for pc-relative field"));
2367 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2369 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2371 as_bad (_("relocated field and relocation type differ in signedness"));
2380 as_bad (_("there are no unsigned pc-relative relocations"));
2383 case 1: return BFD_RELOC_8_PCREL
;
2384 case 2: return BFD_RELOC_16_PCREL
;
2385 case 4: return BFD_RELOC_32_PCREL
;
2386 case 8: return BFD_RELOC_64_PCREL
;
2388 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2395 case 4: return BFD_RELOC_X86_64_32S
;
2400 case 1: return BFD_RELOC_8
;
2401 case 2: return BFD_RELOC_16
;
2402 case 4: return BFD_RELOC_32
;
2403 case 8: return BFD_RELOC_64
;
2405 as_bad (_("cannot do %s %u byte relocation"),
2406 sign
> 0 ? "signed" : "unsigned", size
);
2412 /* Here we decide which fixups can be adjusted to make them relative to
2413 the beginning of the section instead of the symbol. Basically we need
2414 to make sure that the dynamic relocations are done correctly, so in
2415 some cases we force the original symbol to be used. */
2418 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2420 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2424 /* Don't adjust pc-relative references to merge sections in 64-bit
2426 if (use_rela_relocations
2427 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2431 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2432 and changed later by validate_fix. */
2433 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2434 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2437 /* adjust_reloc_syms doesn't know about the GOT. */
2438 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2439 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2440 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2441 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2442 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2443 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2444 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2445 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2446 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2447 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2448 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2449 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2450 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2451 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2452 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2453 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2454 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2455 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2456 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2457 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2458 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2459 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2460 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2461 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2462 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2463 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2464 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2465 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2468 if (fixP
->fx_addsy
!= NULL
2469 && symbol_get_bfdsym (fixP
->fx_addsy
)->flags
& BSF_GNU_INDIRECT_FUNCTION
)
2476 intel_float_operand (const char *mnemonic
)
2478 /* Note that the value returned is meaningful only for opcodes with (memory)
2479 operands, hence the code here is free to improperly handle opcodes that
2480 have no operands (for better performance and smaller code). */
2482 if (mnemonic
[0] != 'f')
2483 return 0; /* non-math */
2485 switch (mnemonic
[1])
2487 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2488 the fs segment override prefix not currently handled because no
2489 call path can make opcodes without operands get here */
2491 return 2 /* integer op */;
2493 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2494 return 3; /* fldcw/fldenv */
2497 if (mnemonic
[2] != 'o' /* fnop */)
2498 return 3; /* non-waiting control op */
2501 if (mnemonic
[2] == 's')
2502 return 3; /* frstor/frstpm */
2505 if (mnemonic
[2] == 'a')
2506 return 3; /* fsave */
2507 if (mnemonic
[2] == 't')
2509 switch (mnemonic
[3])
2511 case 'c': /* fstcw */
2512 case 'd': /* fstdw */
2513 case 'e': /* fstenv */
2514 case 's': /* fsts[gw] */
2520 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2521 return 0; /* fxsave/fxrstor are not really math ops */
2528 /* Build the VEX prefix. */
2531 build_vex_prefix (const template *t
)
2533 unsigned int register_specifier
;
2534 unsigned int implied_prefix
;
2535 unsigned int vector_length
;
2537 /* Check register specifier. */
2538 if (i
.vex
.register_specifier
)
2540 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2541 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2542 register_specifier
+= 8;
2543 register_specifier
= ~register_specifier
& 0xf;
2546 register_specifier
= 0xf;
2548 /* Use 2-byte VEX prefix by swappping destination and source
2551 && i
.operands
== i
.reg_operands
2552 && i
.tm
.opcode_modifier
.vex0f
2553 && i
.tm
.opcode_modifier
.s
2556 unsigned int xchg
= i
.operands
- 1;
2557 union i386_op temp_op
;
2558 i386_operand_type temp_type
;
2560 temp_type
= i
.types
[xchg
];
2561 i
.types
[xchg
] = i
.types
[0];
2562 i
.types
[0] = temp_type
;
2563 temp_op
= i
.op
[xchg
];
2564 i
.op
[xchg
] = i
.op
[0];
2567 gas_assert (i
.rm
.mode
== 3);
2571 i
.rm
.regmem
= i
.rm
.reg
;
2574 /* Use the next insn. */
2578 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2580 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2585 case DATA_PREFIX_OPCODE
:
2588 case REPE_PREFIX_OPCODE
:
2591 case REPNE_PREFIX_OPCODE
:
2598 /* Use 2-byte VEX prefix if possible. */
2599 if (i
.tm
.opcode_modifier
.vex0f
2600 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2602 /* 2-byte VEX prefix. */
2606 i
.vex
.bytes
[0] = 0xc5;
2608 /* Check the REX.R bit. */
2609 r
= (i
.rex
& REX_R
) ? 0 : 1;
2610 i
.vex
.bytes
[1] = (r
<< 7
2611 | register_specifier
<< 3
2612 | vector_length
<< 2
2617 /* 3-byte VEX prefix. */
2620 if (i
.tm
.opcode_modifier
.vex0f
)
2622 else if (i
.tm
.opcode_modifier
.vex0f38
)
2624 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2630 i
.vex
.bytes
[0] = 0xc4;
2632 /* The high 3 bits of the second VEX byte are 1's compliment
2633 of RXB bits from REX. */
2634 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2636 /* Check the REX.W bit. */
2637 w
= (i
.rex
& REX_W
) ? 1 : 0;
2638 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2643 if (i
.tm
.opcode_modifier
.vexw1
)
2647 i
.vex
.bytes
[2] = (w
<< 7
2648 | register_specifier
<< 3
2649 | vector_length
<< 2
2655 process_immext (void)
2659 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2661 /* SSE3 Instructions have the fixed operands with an opcode
2662 suffix which is coded in the same place as an 8-bit immediate
2663 field would be. Here we check those operands and remove them
2667 for (x
= 0; x
< i
.operands
; x
++)
2668 if (i
.op
[x
].regs
->reg_num
!= x
)
2669 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2670 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2676 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2677 which is coded in the same place as an 8-bit immediate field
2678 would be. Here we fake an 8-bit immediate operand from the
2679 opcode suffix stored in tm.extension_opcode.
2681 AVX instructions also use this encoding, for some of
2682 3 argument instructions. */
2684 gas_assert (i
.imm_operands
== 0
2686 || (i
.tm
.opcode_modifier
.vex
2687 && i
.operands
<= 4)));
2689 exp
= &im_expressions
[i
.imm_operands
++];
2690 i
.op
[i
.operands
].imms
= exp
;
2691 i
.types
[i
.operands
] = imm8
;
2693 exp
->X_op
= O_constant
;
2694 exp
->X_add_number
= i
.tm
.extension_opcode
;
2695 i
.tm
.extension_opcode
= None
;
2698 /* This is the guts of the machine-dependent assembler. LINE points to a
2699 machine dependent instruction. This function is supposed to emit
2700 the frags/bytes it assembles to. */
2703 md_assemble (char *line
)
2706 char mnemonic
[MAX_MNEM_SIZE
];
2709 /* Initialize globals. */
2710 memset (&i
, '\0', sizeof (i
));
2711 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2712 i
.reloc
[j
] = NO_RELOC
;
2713 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2714 memset (im_expressions
, '\0', sizeof (im_expressions
));
2715 save_stack_p
= save_stack
;
2717 /* First parse an instruction mnemonic & call i386_operand for the operands.
2718 We assume that the scrubber has arranged it so that line[0] is the valid
2719 start of a (possibly prefixed) mnemonic. */
2721 line
= parse_insn (line
, mnemonic
);
2725 line
= parse_operands (line
, mnemonic
);
2730 /* Now we've parsed the mnemonic into a set of templates, and have the
2731 operands at hand. */
2733 /* All intel opcodes have reversed operands except for "bound" and
2734 "enter". We also don't reverse intersegment "jmp" and "call"
2735 instructions with 2 immediate operands so that the immediate segment
2736 precedes the offset, as it does when in AT&T mode. */
2739 && (strcmp (mnemonic
, "bound") != 0)
2740 && (strcmp (mnemonic
, "invlpga") != 0)
2741 && !(operand_type_check (i
.types
[0], imm
)
2742 && operand_type_check (i
.types
[1], imm
)))
2745 /* The order of the immediates should be reversed
2746 for 2 immediates extrq and insertq instructions */
2747 if (i
.imm_operands
== 2
2748 && (strcmp (mnemonic
, "extrq") == 0
2749 || strcmp (mnemonic
, "insertq") == 0))
2750 swap_2_operands (0, 1);
2755 /* Don't optimize displacement for movabs since it only takes 64bit
2758 && (flag_code
!= CODE_64BIT
2759 || strcmp (mnemonic
, "movabs") != 0))
2762 /* Next, we find a template that matches the given insn,
2763 making sure the overlap of the given operands types is consistent
2764 with the template operand types. */
2766 if (!(t
= match_template ()))
2769 if (sse_check
!= sse_check_none
2770 && !i
.tm
.opcode_modifier
.noavx
2771 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2772 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2773 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2774 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2775 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2776 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2778 (sse_check
== sse_check_warning
2780 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2783 /* Zap movzx and movsx suffix. The suffix has been set from
2784 "word ptr" or "byte ptr" on the source operand in Intel syntax
2785 or extracted from mnemonic in AT&T syntax. But we'll use
2786 the destination register to choose the suffix for encoding. */
2787 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2789 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2790 there is no suffix, the default will be byte extension. */
2791 if (i
.reg_operands
!= 2
2794 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2799 if (i
.tm
.opcode_modifier
.fwait
)
2800 if (!add_prefix (FWAIT_OPCODE
))
2803 /* Check string instruction segment overrides. */
2804 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2806 if (!check_string ())
2808 i
.disp_operands
= 0;
2811 if (!process_suffix ())
2814 /* Make still unresolved immediate matches conform to size of immediate
2815 given in i.suffix. */
2816 if (!finalize_imm ())
2819 if (i
.types
[0].bitfield
.imm1
)
2820 i
.imm_operands
= 0; /* kludge for shift insns. */
2822 for (j
= 0; j
< 3; j
++)
2823 if (i
.types
[j
].bitfield
.inoutportreg
2824 || i
.types
[j
].bitfield
.shiftcount
2825 || i
.types
[j
].bitfield
.acc
2826 || i
.types
[j
].bitfield
.floatacc
)
2829 /* ImmExt should be processed after SSE2AVX. */
2830 if (!i
.tm
.opcode_modifier
.sse2avx
2831 && i
.tm
.opcode_modifier
.immext
)
2834 /* For insns with operands there are more diddles to do to the opcode. */
2837 if (!process_operands ())
2840 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2842 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2843 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2846 if (i
.tm
.opcode_modifier
.vex
)
2847 build_vex_prefix (t
);
2849 /* Handle conversion of 'int $3' --> special int3 insn. */
2850 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2852 i
.tm
.base_opcode
= INT3_OPCODE
;
2856 if ((i
.tm
.opcode_modifier
.jump
2857 || i
.tm
.opcode_modifier
.jumpbyte
2858 || i
.tm
.opcode_modifier
.jumpdword
)
2859 && i
.op
[0].disps
->X_op
== O_constant
)
2861 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2862 the absolute address given by the constant. Since ix86 jumps and
2863 calls are pc relative, we need to generate a reloc. */
2864 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2865 i
.op
[0].disps
->X_op
= O_symbol
;
2868 if (i
.tm
.opcode_modifier
.rex64
)
2871 /* For 8 bit registers we need an empty rex prefix. Also if the
2872 instruction already has a prefix, we need to convert old
2873 registers to new ones. */
2875 if ((i
.types
[0].bitfield
.reg8
2876 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2877 || (i
.types
[1].bitfield
.reg8
2878 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2879 || ((i
.types
[0].bitfield
.reg8
2880 || i
.types
[1].bitfield
.reg8
)
2885 i
.rex
|= REX_OPCODE
;
2886 for (x
= 0; x
< 2; x
++)
2888 /* Look for 8 bit operand that uses old registers. */
2889 if (i
.types
[x
].bitfield
.reg8
2890 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2892 /* In case it is "hi" register, give up. */
2893 if (i
.op
[x
].regs
->reg_num
> 3)
2894 as_bad (_("can't encode register '%s%s' in an "
2895 "instruction requiring REX prefix."),
2896 register_prefix
, i
.op
[x
].regs
->reg_name
);
2898 /* Otherwise it is equivalent to the extended register.
2899 Since the encoding doesn't change this is merely
2900 cosmetic cleanup for debug output. */
2902 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2908 add_prefix (REX_OPCODE
| i
.rex
);
2910 /* We are ready to output the insn. */
2915 parse_insn (char *line
, char *mnemonic
)
2918 char *token_start
= l
;
2924 /* Non-zero if we found a prefix only acceptable with string insns. */
2925 const char *expecting_string_instruction
= NULL
;
2930 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2935 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2937 as_bad (_("no such instruction: `%s'"), token_start
);
2942 if (!is_space_char (*l
)
2943 && *l
!= END_OF_INSN
2945 || (*l
!= PREFIX_SEPARATOR
2948 as_bad (_("invalid character %s in mnemonic"),
2949 output_invalid (*l
));
2952 if (token_start
== l
)
2954 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2955 as_bad (_("expecting prefix; got nothing"));
2957 as_bad (_("expecting mnemonic; got nothing"));
2961 /* Look up instruction (or prefix) via hash table. */
2962 current_templates
= hash_find (op_hash
, mnemonic
);
2964 if (*l
!= END_OF_INSN
2965 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
2966 && current_templates
2967 && current_templates
->start
->opcode_modifier
.isprefix
)
2969 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
2971 as_bad ((flag_code
!= CODE_64BIT
2972 ? _("`%s' is only supported in 64-bit mode")
2973 : _("`%s' is not supported in 64-bit mode")),
2974 current_templates
->start
->name
);
2977 /* If we are in 16-bit mode, do not allow addr16 or data16.
2978 Similarly, in 32-bit mode, do not allow addr32 or data32. */
2979 if ((current_templates
->start
->opcode_modifier
.size16
2980 || current_templates
->start
->opcode_modifier
.size32
)
2981 && flag_code
!= CODE_64BIT
2982 && (current_templates
->start
->opcode_modifier
.size32
2983 ^ (flag_code
== CODE_16BIT
)))
2985 as_bad (_("redundant %s prefix"),
2986 current_templates
->start
->name
);
2989 /* Add prefix, checking for repeated prefixes. */
2990 switch (add_prefix (current_templates
->start
->base_opcode
))
2995 expecting_string_instruction
= current_templates
->start
->name
;
2998 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3005 if (!current_templates
)
3007 /* Check if we should swap operand in encoding. */
3008 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3014 current_templates
= hash_find (op_hash
, mnemonic
);
3017 if (!current_templates
)
3020 /* See if we can get a match by trimming off a suffix. */
3023 case WORD_MNEM_SUFFIX
:
3024 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3025 i
.suffix
= SHORT_MNEM_SUFFIX
;
3027 case BYTE_MNEM_SUFFIX
:
3028 case QWORD_MNEM_SUFFIX
:
3029 i
.suffix
= mnem_p
[-1];
3031 current_templates
= hash_find (op_hash
, mnemonic
);
3033 case SHORT_MNEM_SUFFIX
:
3034 case LONG_MNEM_SUFFIX
:
3037 i
.suffix
= mnem_p
[-1];
3039 current_templates
= hash_find (op_hash
, mnemonic
);
3047 if (intel_float_operand (mnemonic
) == 1)
3048 i
.suffix
= SHORT_MNEM_SUFFIX
;
3050 i
.suffix
= LONG_MNEM_SUFFIX
;
3052 current_templates
= hash_find (op_hash
, mnemonic
);
3056 if (!current_templates
)
3058 as_bad (_("no such instruction: `%s'"), token_start
);
3063 if (current_templates
->start
->opcode_modifier
.jump
3064 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3066 /* Check for a branch hint. We allow ",pt" and ",pn" for
3067 predict taken and predict not taken respectively.
3068 I'm not sure that branch hints actually do anything on loop
3069 and jcxz insns (JumpByte) for current Pentium4 chips. They
3070 may work in the future and it doesn't hurt to accept them
3072 if (l
[0] == ',' && l
[1] == 'p')
3076 if (!add_prefix (DS_PREFIX_OPCODE
))
3080 else if (l
[2] == 'n')
3082 if (!add_prefix (CS_PREFIX_OPCODE
))
3088 /* Any other comma loses. */
3091 as_bad (_("invalid character %s in mnemonic"),
3092 output_invalid (*l
));
3096 /* Check if instruction is supported on specified architecture. */
3098 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3100 supported
|= cpu_flags_match (t
);
3101 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3105 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3107 as_bad (flag_code
== CODE_64BIT
3108 ? _("`%s' is not supported in 64-bit mode")
3109 : _("`%s' is only supported in 64-bit mode"),
3110 current_templates
->start
->name
);
3113 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3115 as_bad (_("`%s' is not supported on `%s%s'"),
3116 current_templates
->start
->name
,
3117 cpu_arch_name
? cpu_arch_name
: default_arch
,
3118 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3123 if (!cpu_arch_flags
.bitfield
.cpui386
3124 && (flag_code
!= CODE_16BIT
))
3126 as_warn (_("use .code16 to ensure correct addressing mode"));
3129 /* Check for rep/repne without a string instruction. */
3130 if (expecting_string_instruction
)
3132 static templates override
;
3134 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3135 if (t
->opcode_modifier
.isstring
)
3137 if (t
>= current_templates
->end
)
3139 as_bad (_("expecting string instruction after `%s'"),
3140 expecting_string_instruction
);
3143 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3144 if (!t
->opcode_modifier
.isstring
)
3147 current_templates
= &override
;
3154 parse_operands (char *l
, const char *mnemonic
)
3158 /* 1 if operand is pending after ','. */
3159 unsigned int expecting_operand
= 0;
3161 /* Non-zero if operand parens not balanced. */
3162 unsigned int paren_not_balanced
;
3164 while (*l
!= END_OF_INSN
)
3166 /* Skip optional white space before operand. */
3167 if (is_space_char (*l
))
3169 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3171 as_bad (_("invalid character %s before operand %d"),
3172 output_invalid (*l
),
3176 token_start
= l
; /* after white space */
3177 paren_not_balanced
= 0;
3178 while (paren_not_balanced
|| *l
!= ',')
3180 if (*l
== END_OF_INSN
)
3182 if (paren_not_balanced
)
3185 as_bad (_("unbalanced parenthesis in operand %d."),
3188 as_bad (_("unbalanced brackets in operand %d."),
3193 break; /* we are done */
3195 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3197 as_bad (_("invalid character %s in operand %d"),
3198 output_invalid (*l
),
3205 ++paren_not_balanced
;
3207 --paren_not_balanced
;
3212 ++paren_not_balanced
;
3214 --paren_not_balanced
;
3218 if (l
!= token_start
)
3219 { /* Yes, we've read in another operand. */
3220 unsigned int operand_ok
;
3221 this_operand
= i
.operands
++;
3222 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3223 if (i
.operands
> MAX_OPERANDS
)
3225 as_bad (_("spurious operands; (%d operands/instruction max)"),
3229 /* Now parse operand adding info to 'i' as we go along. */
3230 END_STRING_AND_SAVE (l
);
3234 i386_intel_operand (token_start
,
3235 intel_float_operand (mnemonic
));
3237 operand_ok
= i386_att_operand (token_start
);
3239 RESTORE_END_STRING (l
);
3245 if (expecting_operand
)
3247 expecting_operand_after_comma
:
3248 as_bad (_("expecting operand after ','; got nothing"));
3253 as_bad (_("expecting operand before ','; got nothing"));
3258 /* Now *l must be either ',' or END_OF_INSN. */
3261 if (*++l
== END_OF_INSN
)
3263 /* Just skip it, if it's \n complain. */
3264 goto expecting_operand_after_comma
;
3266 expecting_operand
= 1;
3273 swap_2_operands (int xchg1
, int xchg2
)
3275 union i386_op temp_op
;
3276 i386_operand_type temp_type
;
3277 enum bfd_reloc_code_real temp_reloc
;
3279 temp_type
= i
.types
[xchg2
];
3280 i
.types
[xchg2
] = i
.types
[xchg1
];
3281 i
.types
[xchg1
] = temp_type
;
3282 temp_op
= i
.op
[xchg2
];
3283 i
.op
[xchg2
] = i
.op
[xchg1
];
3284 i
.op
[xchg1
] = temp_op
;
3285 temp_reloc
= i
.reloc
[xchg2
];
3286 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3287 i
.reloc
[xchg1
] = temp_reloc
;
3291 swap_operands (void)
3297 swap_2_operands (1, i
.operands
- 2);
3300 swap_2_operands (0, i
.operands
- 1);
3306 if (i
.mem_operands
== 2)
3308 const seg_entry
*temp_seg
;
3309 temp_seg
= i
.seg
[0];
3310 i
.seg
[0] = i
.seg
[1];
3311 i
.seg
[1] = temp_seg
;
3315 /* Try to ensure constant immediates are represented in the smallest
3320 char guess_suffix
= 0;
3324 guess_suffix
= i
.suffix
;
3325 else if (i
.reg_operands
)
3327 /* Figure out a suffix from the last register operand specified.
3328 We can't do this properly yet, ie. excluding InOutPortReg,
3329 but the following works for instructions with immediates.
3330 In any case, we can't set i.suffix yet. */
3331 for (op
= i
.operands
; --op
>= 0;)
3332 if (i
.types
[op
].bitfield
.reg8
)
3334 guess_suffix
= BYTE_MNEM_SUFFIX
;
3337 else if (i
.types
[op
].bitfield
.reg16
)
3339 guess_suffix
= WORD_MNEM_SUFFIX
;
3342 else if (i
.types
[op
].bitfield
.reg32
)
3344 guess_suffix
= LONG_MNEM_SUFFIX
;
3347 else if (i
.types
[op
].bitfield
.reg64
)
3349 guess_suffix
= QWORD_MNEM_SUFFIX
;
3353 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3354 guess_suffix
= WORD_MNEM_SUFFIX
;
3356 for (op
= i
.operands
; --op
>= 0;)
3357 if (operand_type_check (i
.types
[op
], imm
))
3359 switch (i
.op
[op
].imms
->X_op
)
3362 /* If a suffix is given, this operand may be shortened. */
3363 switch (guess_suffix
)
3365 case LONG_MNEM_SUFFIX
:
3366 i
.types
[op
].bitfield
.imm32
= 1;
3367 i
.types
[op
].bitfield
.imm64
= 1;
3369 case WORD_MNEM_SUFFIX
:
3370 i
.types
[op
].bitfield
.imm16
= 1;
3371 i
.types
[op
].bitfield
.imm32
= 1;
3372 i
.types
[op
].bitfield
.imm32s
= 1;
3373 i
.types
[op
].bitfield
.imm64
= 1;
3375 case BYTE_MNEM_SUFFIX
:
3376 i
.types
[op
].bitfield
.imm8
= 1;
3377 i
.types
[op
].bitfield
.imm8s
= 1;
3378 i
.types
[op
].bitfield
.imm16
= 1;
3379 i
.types
[op
].bitfield
.imm32
= 1;
3380 i
.types
[op
].bitfield
.imm32s
= 1;
3381 i
.types
[op
].bitfield
.imm64
= 1;
3385 /* If this operand is at most 16 bits, convert it
3386 to a signed 16 bit number before trying to see
3387 whether it will fit in an even smaller size.
3388 This allows a 16-bit operand such as $0xffe0 to
3389 be recognised as within Imm8S range. */
3390 if ((i
.types
[op
].bitfield
.imm16
)
3391 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3393 i
.op
[op
].imms
->X_add_number
=
3394 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3396 if ((i
.types
[op
].bitfield
.imm32
)
3397 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3400 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3401 ^ ((offsetT
) 1 << 31))
3402 - ((offsetT
) 1 << 31));
3405 = operand_type_or (i
.types
[op
],
3406 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3408 /* We must avoid matching of Imm32 templates when 64bit
3409 only immediate is available. */
3410 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3411 i
.types
[op
].bitfield
.imm32
= 0;
3418 /* Symbols and expressions. */
3420 /* Convert symbolic operand to proper sizes for matching, but don't
3421 prevent matching a set of insns that only supports sizes other
3422 than those matching the insn suffix. */
3424 i386_operand_type mask
, allowed
;
3427 operand_type_set (&mask
, 0);
3428 operand_type_set (&allowed
, 0);
3430 for (t
= current_templates
->start
;
3431 t
< current_templates
->end
;
3433 allowed
= operand_type_or (allowed
,
3434 t
->operand_types
[op
]);
3435 switch (guess_suffix
)
3437 case QWORD_MNEM_SUFFIX
:
3438 mask
.bitfield
.imm64
= 1;
3439 mask
.bitfield
.imm32s
= 1;
3441 case LONG_MNEM_SUFFIX
:
3442 mask
.bitfield
.imm32
= 1;
3444 case WORD_MNEM_SUFFIX
:
3445 mask
.bitfield
.imm16
= 1;
3447 case BYTE_MNEM_SUFFIX
:
3448 mask
.bitfield
.imm8
= 1;
3453 allowed
= operand_type_and (mask
, allowed
);
3454 if (!operand_type_all_zero (&allowed
))
3455 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3462 /* Try to use the smallest displacement type too. */
3464 optimize_disp (void)
3468 for (op
= i
.operands
; --op
>= 0;)
3469 if (operand_type_check (i
.types
[op
], disp
))
3471 if (i
.op
[op
].disps
->X_op
== O_constant
)
3473 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3475 if (i
.types
[op
].bitfield
.disp16
3476 && (disp
& ~(offsetT
) 0xffff) == 0)
3478 /* If this operand is at most 16 bits, convert
3479 to a signed 16 bit number and don't use 64bit
3481 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3482 i
.types
[op
].bitfield
.disp64
= 0;
3484 if (i
.types
[op
].bitfield
.disp32
3485 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3487 /* If this operand is at most 32 bits, convert
3488 to a signed 32 bit number and don't use 64bit
3490 disp
&= (((offsetT
) 2 << 31) - 1);
3491 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3492 i
.types
[op
].bitfield
.disp64
= 0;
3494 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3496 i
.types
[op
].bitfield
.disp8
= 0;
3497 i
.types
[op
].bitfield
.disp16
= 0;
3498 i
.types
[op
].bitfield
.disp32
= 0;
3499 i
.types
[op
].bitfield
.disp32s
= 0;
3500 i
.types
[op
].bitfield
.disp64
= 0;
3504 else if (flag_code
== CODE_64BIT
)
3506 if (fits_in_signed_long (disp
))
3508 i
.types
[op
].bitfield
.disp64
= 0;
3509 i
.types
[op
].bitfield
.disp32s
= 1;
3511 if (fits_in_unsigned_long (disp
))
3512 i
.types
[op
].bitfield
.disp32
= 1;
3514 if ((i
.types
[op
].bitfield
.disp32
3515 || i
.types
[op
].bitfield
.disp32s
3516 || i
.types
[op
].bitfield
.disp16
)
3517 && fits_in_signed_byte (disp
))
3518 i
.types
[op
].bitfield
.disp8
= 1;
3520 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3521 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3523 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3524 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3525 i
.types
[op
].bitfield
.disp8
= 0;
3526 i
.types
[op
].bitfield
.disp16
= 0;
3527 i
.types
[op
].bitfield
.disp32
= 0;
3528 i
.types
[op
].bitfield
.disp32s
= 0;
3529 i
.types
[op
].bitfield
.disp64
= 0;
3532 /* We only support 64bit displacement on constants. */
3533 i
.types
[op
].bitfield
.disp64
= 0;
3537 static const template *
3538 match_template (void)
3540 /* Points to template once we've found it. */
3542 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3543 i386_operand_type overlap4
;
3544 unsigned int found_reverse_match
;
3545 i386_opcode_modifier suffix_check
;
3546 i386_operand_type operand_types
[MAX_OPERANDS
];
3547 int addr_prefix_disp
;
3549 unsigned int found_cpu_match
;
3550 unsigned int check_register
;
3552 #if MAX_OPERANDS != 5
3553 # error "MAX_OPERANDS must be 5."
3556 found_reverse_match
= 0;
3557 addr_prefix_disp
= -1;
3559 memset (&suffix_check
, 0, sizeof (suffix_check
));
3560 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3561 suffix_check
.no_bsuf
= 1;
3562 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3563 suffix_check
.no_wsuf
= 1;
3564 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3565 suffix_check
.no_ssuf
= 1;
3566 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3567 suffix_check
.no_lsuf
= 1;
3568 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3569 suffix_check
.no_qsuf
= 1;
3570 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3571 suffix_check
.no_ldsuf
= 1;
3573 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3575 addr_prefix_disp
= -1;
3577 /* Must have right number of operands. */
3578 if (i
.operands
!= t
->operands
)
3581 /* Check processor support. */
3582 found_cpu_match
= (cpu_flags_match (t
)
3583 == CPU_FLAGS_PERFECT_MATCH
);
3584 if (!found_cpu_match
)
3587 /* Check old gcc support. */
3588 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3591 /* Check AT&T mnemonic. */
3592 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3595 /* Check AT&T syntax Intel syntax. */
3596 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3597 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3600 /* Check the suffix, except for some instructions in intel mode. */
3601 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3602 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3603 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3604 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3605 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3606 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3607 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3610 if (!operand_size_match (t
))
3613 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3614 operand_types
[j
] = t
->operand_types
[j
];
3616 /* In general, don't allow 64-bit operands in 32-bit mode. */
3617 if (i
.suffix
== QWORD_MNEM_SUFFIX
3618 && flag_code
!= CODE_64BIT
3620 ? (!t
->opcode_modifier
.ignoresize
3621 && !intel_float_operand (t
->name
))
3622 : intel_float_operand (t
->name
) != 2)
3623 && ((!operand_types
[0].bitfield
.regmmx
3624 && !operand_types
[0].bitfield
.regxmm
3625 && !operand_types
[0].bitfield
.regymm
)
3626 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3627 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3628 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3629 && (t
->base_opcode
!= 0x0fc7
3630 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3633 /* In general, don't allow 32-bit operands on pre-386. */
3634 else if (i
.suffix
== LONG_MNEM_SUFFIX
3635 && !cpu_arch_flags
.bitfield
.cpui386
3637 ? (!t
->opcode_modifier
.ignoresize
3638 && !intel_float_operand (t
->name
))
3639 : intel_float_operand (t
->name
) != 2)
3640 && ((!operand_types
[0].bitfield
.regmmx
3641 && !operand_types
[0].bitfield
.regxmm
)
3642 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3643 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3646 /* Do not verify operands when there are none. */
3650 /* We've found a match; break out of loop. */
3654 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3655 into Disp32/Disp16/Disp32 operand. */
3656 if (i
.prefix
[ADDR_PREFIX
] != 0)
3658 /* There should be only one Disp operand. */
3662 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3664 if (operand_types
[j
].bitfield
.disp16
)
3666 addr_prefix_disp
= j
;
3667 operand_types
[j
].bitfield
.disp32
= 1;
3668 operand_types
[j
].bitfield
.disp16
= 0;
3674 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3676 if (operand_types
[j
].bitfield
.disp32
)
3678 addr_prefix_disp
= j
;
3679 operand_types
[j
].bitfield
.disp32
= 0;
3680 operand_types
[j
].bitfield
.disp16
= 1;
3686 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3688 if (operand_types
[j
].bitfield
.disp64
)
3690 addr_prefix_disp
= j
;
3691 operand_types
[j
].bitfield
.disp64
= 0;
3692 operand_types
[j
].bitfield
.disp32
= 1;
3700 /* We check register size only if size of operands can be
3701 encoded the canonical way. */
3702 check_register
= t
->opcode_modifier
.w
;
3703 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3704 switch (t
->operands
)
3707 if (!operand_type_match (overlap0
, i
.types
[0]))
3711 /* xchg %eax, %eax is a special case. It is an aliase for nop
3712 only in 32bit mode and we can use opcode 0x90. In 64bit
3713 mode, we can't use 0x90 for xchg %eax, %eax since it should
3714 zero-extend %eax to %rax. */
3715 if (flag_code
== CODE_64BIT
3716 && t
->base_opcode
== 0x90
3717 && operand_type_equal (&i
.types
[0], &acc32
)
3718 && operand_type_equal (&i
.types
[1], &acc32
))
3722 /* If we swap operand in encoding, we either match
3723 the next one or reverse direction of operands. */
3724 if (t
->opcode_modifier
.s
)
3726 else if (t
->opcode_modifier
.d
)
3731 /* If we swap operand in encoding, we match the next one. */
3732 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3736 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3737 if (!operand_type_match (overlap0
, i
.types
[0])
3738 || !operand_type_match (overlap1
, i
.types
[1])
3740 && !operand_type_register_match (overlap0
, i
.types
[0],
3742 overlap1
, i
.types
[1],
3745 /* Check if other direction is valid ... */
3746 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3750 /* Try reversing direction of operands. */
3751 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3752 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3753 if (!operand_type_match (overlap0
, i
.types
[0])
3754 || !operand_type_match (overlap1
, i
.types
[1])
3756 && !operand_type_register_match (overlap0
,
3763 /* Does not match either direction. */
3766 /* found_reverse_match holds which of D or FloatDR
3768 if (t
->opcode_modifier
.d
)
3769 found_reverse_match
= Opcode_D
;
3770 else if (t
->opcode_modifier
.floatd
)
3771 found_reverse_match
= Opcode_FloatD
;
3773 found_reverse_match
= 0;
3774 if (t
->opcode_modifier
.floatr
)
3775 found_reverse_match
|= Opcode_FloatR
;
3779 /* Found a forward 2 operand match here. */
3780 switch (t
->operands
)
3783 overlap4
= operand_type_and (i
.types
[4],
3786 overlap3
= operand_type_and (i
.types
[3],
3789 overlap2
= operand_type_and (i
.types
[2],
3794 switch (t
->operands
)
3797 if (!operand_type_match (overlap4
, i
.types
[4])
3798 || !operand_type_register_match (overlap3
,
3806 if (!operand_type_match (overlap3
, i
.types
[3])
3808 && !operand_type_register_match (overlap2
,
3816 /* Here we make use of the fact that there are no
3817 reverse match 3 operand instructions, and all 3
3818 operand instructions only need to be checked for
3819 register consistency between operands 2 and 3. */
3820 if (!operand_type_match (overlap2
, i
.types
[2])
3822 && !operand_type_register_match (overlap1
,
3832 /* Found either forward/reverse 2, 3 or 4 operand match here:
3833 slip through to break. */
3835 if (!found_cpu_match
)
3837 found_reverse_match
= 0;
3841 /* We've found a match; break out of loop. */
3845 if (t
== current_templates
->end
)
3847 /* We found no match. */
3849 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3850 current_templates
->start
->name
);
3852 as_bad (_("suffix or operands invalid for `%s'"),
3853 current_templates
->start
->name
);
3857 if (!quiet_warnings
)
3860 && (i
.types
[0].bitfield
.jumpabsolute
3861 != operand_types
[0].bitfield
.jumpabsolute
))
3863 as_warn (_("indirect %s without `*'"), t
->name
);
3866 if (t
->opcode_modifier
.isprefix
3867 && t
->opcode_modifier
.ignoresize
)
3869 /* Warn them that a data or address size prefix doesn't
3870 affect assembly of the next line of code. */
3871 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3875 /* Copy the template we found. */
3878 if (addr_prefix_disp
!= -1)
3879 i
.tm
.operand_types
[addr_prefix_disp
]
3880 = operand_types
[addr_prefix_disp
];
3882 if (found_reverse_match
)
3884 /* If we found a reverse match we must alter the opcode
3885 direction bit. found_reverse_match holds bits to change
3886 (different for int & float insns). */
3888 i
.tm
.base_opcode
^= found_reverse_match
;
3890 i
.tm
.operand_types
[0] = operand_types
[1];
3891 i
.tm
.operand_types
[1] = operand_types
[0];
3900 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3901 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3903 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3905 as_bad (_("`%s' operand %d must use `%ses' segment"),
3911 /* There's only ever one segment override allowed per instruction.
3912 This instruction possibly has a legal segment override on the
3913 second operand, so copy the segment to where non-string
3914 instructions store it, allowing common code. */
3915 i
.seg
[0] = i
.seg
[1];
3917 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3919 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3921 as_bad (_("`%s' operand %d must use `%ses' segment"),
3932 process_suffix (void)
3934 /* If matched instruction specifies an explicit instruction mnemonic
3936 if (i
.tm
.opcode_modifier
.size16
)
3937 i
.suffix
= WORD_MNEM_SUFFIX
;
3938 else if (i
.tm
.opcode_modifier
.size32
)
3939 i
.suffix
= LONG_MNEM_SUFFIX
;
3940 else if (i
.tm
.opcode_modifier
.size64
)
3941 i
.suffix
= QWORD_MNEM_SUFFIX
;
3942 else if (i
.reg_operands
)
3944 /* If there's no instruction mnemonic suffix we try to invent one
3945 based on register operands. */
3948 /* We take i.suffix from the last register operand specified,
3949 Destination register type is more significant than source
3950 register type. crc32 in SSE4.2 prefers source register
3952 if (i
.tm
.base_opcode
== 0xf20f38f1)
3954 if (i
.types
[0].bitfield
.reg16
)
3955 i
.suffix
= WORD_MNEM_SUFFIX
;
3956 else if (i
.types
[0].bitfield
.reg32
)
3957 i
.suffix
= LONG_MNEM_SUFFIX
;
3958 else if (i
.types
[0].bitfield
.reg64
)
3959 i
.suffix
= QWORD_MNEM_SUFFIX
;
3961 else if (i
.tm
.base_opcode
== 0xf20f38f0)
3963 if (i
.types
[0].bitfield
.reg8
)
3964 i
.suffix
= BYTE_MNEM_SUFFIX
;
3971 if (i
.tm
.base_opcode
== 0xf20f38f1
3972 || i
.tm
.base_opcode
== 0xf20f38f0)
3974 /* We have to know the operand size for crc32. */
3975 as_bad (_("ambiguous memory operand size for `%s`"),
3980 for (op
= i
.operands
; --op
>= 0;)
3981 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
3983 if (i
.types
[op
].bitfield
.reg8
)
3985 i
.suffix
= BYTE_MNEM_SUFFIX
;
3988 else if (i
.types
[op
].bitfield
.reg16
)
3990 i
.suffix
= WORD_MNEM_SUFFIX
;
3993 else if (i
.types
[op
].bitfield
.reg32
)
3995 i
.suffix
= LONG_MNEM_SUFFIX
;
3998 else if (i
.types
[op
].bitfield
.reg64
)
4000 i
.suffix
= QWORD_MNEM_SUFFIX
;
4006 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4008 if (!check_byte_reg ())
4011 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4013 if (!check_long_reg ())
4016 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4019 && i
.tm
.opcode_modifier
.ignoresize
4020 && i
.tm
.opcode_modifier
.no_qsuf
)
4022 else if (!check_qword_reg ())
4025 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4027 if (!check_word_reg ())
4030 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4031 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4033 /* Skip if the instruction has x/y suffix. match_template
4034 should check if it is a valid suffix. */
4036 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4037 /* Do nothing if the instruction is going to ignore the prefix. */
4042 else if (i
.tm
.opcode_modifier
.defaultsize
4044 /* exclude fldenv/frstor/fsave/fstenv */
4045 && i
.tm
.opcode_modifier
.no_ssuf
)
4047 i
.suffix
= stackop_size
;
4049 else if (intel_syntax
4051 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4052 || i
.tm
.opcode_modifier
.jumpbyte
4053 || i
.tm
.opcode_modifier
.jumpintersegment
4054 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4055 && i
.tm
.extension_opcode
<= 3)))
4060 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4062 i
.suffix
= QWORD_MNEM_SUFFIX
;
4066 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4067 i
.suffix
= LONG_MNEM_SUFFIX
;
4070 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4071 i
.suffix
= WORD_MNEM_SUFFIX
;
4080 if (i
.tm
.opcode_modifier
.w
)
4082 as_bad (_("no instruction mnemonic suffix given and "
4083 "no register operands; can't size instruction"));
4089 unsigned int suffixes
;
4091 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4092 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4094 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4096 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4098 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4100 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4103 /* There are more than suffix matches. */
4104 if (i
.tm
.opcode_modifier
.w
4105 || ((suffixes
& (suffixes
- 1))
4106 && !i
.tm
.opcode_modifier
.defaultsize
4107 && !i
.tm
.opcode_modifier
.ignoresize
))
4109 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4115 /* Change the opcode based on the operand size given by i.suffix;
4116 We don't need to change things for byte insns. */
4119 && i
.suffix
!= BYTE_MNEM_SUFFIX
4120 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4121 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4123 /* It's not a byte, select word/dword operation. */
4124 if (i
.tm
.opcode_modifier
.w
)
4126 if (i
.tm
.opcode_modifier
.shortform
)
4127 i
.tm
.base_opcode
|= 8;
4129 i
.tm
.base_opcode
|= 1;
4132 /* Now select between word & dword operations via the operand
4133 size prefix, except for instructions that will ignore this
4135 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4137 /* The address size override prefix changes the size of the
4139 if ((flag_code
== CODE_32BIT
4140 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4141 || (flag_code
!= CODE_32BIT
4142 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4143 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4146 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4147 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4148 && !i
.tm
.opcode_modifier
.ignoresize
4149 && !i
.tm
.opcode_modifier
.floatmf
4150 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4151 || (flag_code
== CODE_64BIT
4152 && i
.tm
.opcode_modifier
.jumpbyte
)))
4154 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4156 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4157 prefix
= ADDR_PREFIX_OPCODE
;
4159 if (!add_prefix (prefix
))
4163 /* Set mode64 for an operand. */
4164 if (i
.suffix
== QWORD_MNEM_SUFFIX
4165 && flag_code
== CODE_64BIT
4166 && !i
.tm
.opcode_modifier
.norex64
)
4168 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4169 need rex64. cmpxchg8b is also a special case. */
4170 if (! (i
.operands
== 2
4171 && i
.tm
.base_opcode
== 0x90
4172 && i
.tm
.extension_opcode
== None
4173 && operand_type_equal (&i
.types
[0], &acc64
)
4174 && operand_type_equal (&i
.types
[1], &acc64
))
4175 && ! (i
.operands
== 1
4176 && i
.tm
.base_opcode
== 0xfc7
4177 && i
.tm
.extension_opcode
== 1
4178 && !operand_type_check (i
.types
[0], reg
)
4179 && operand_type_check (i
.types
[0], anymem
)))
4183 /* Size floating point instruction. */
4184 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4185 if (i
.tm
.opcode_modifier
.floatmf
)
4186 i
.tm
.base_opcode
^= 4;
4193 check_byte_reg (void)
4197 for (op
= i
.operands
; --op
>= 0;)
4199 /* If this is an eight bit register, it's OK. If it's the 16 or
4200 32 bit version of an eight bit register, we will just use the
4201 low portion, and that's OK too. */
4202 if (i
.types
[op
].bitfield
.reg8
)
4205 /* Don't generate this warning if not needed. */
4206 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4209 /* crc32 doesn't generate this warning. */
4210 if (i
.tm
.base_opcode
== 0xf20f38f0)
4213 if ((i
.types
[op
].bitfield
.reg16
4214 || i
.types
[op
].bitfield
.reg32
4215 || i
.types
[op
].bitfield
.reg64
)
4216 && i
.op
[op
].regs
->reg_num
< 4)
4218 /* Prohibit these changes in the 64bit mode, since the
4219 lowering is more complicated. */
4220 if (flag_code
== CODE_64BIT
4221 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4223 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4224 register_prefix
, i
.op
[op
].regs
->reg_name
,
4228 #if REGISTER_WARNINGS
4230 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4231 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4233 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4234 ? REGNAM_AL
- REGNAM_AX
4235 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4237 i
.op
[op
].regs
->reg_name
,
4242 /* Any other register is bad. */
4243 if (i
.types
[op
].bitfield
.reg16
4244 || i
.types
[op
].bitfield
.reg32
4245 || i
.types
[op
].bitfield
.reg64
4246 || i
.types
[op
].bitfield
.regmmx
4247 || i
.types
[op
].bitfield
.regxmm
4248 || i
.types
[op
].bitfield
.regymm
4249 || i
.types
[op
].bitfield
.sreg2
4250 || i
.types
[op
].bitfield
.sreg3
4251 || i
.types
[op
].bitfield
.control
4252 || i
.types
[op
].bitfield
.debug
4253 || i
.types
[op
].bitfield
.test
4254 || i
.types
[op
].bitfield
.floatreg
4255 || i
.types
[op
].bitfield
.floatacc
)
4257 as_bad (_("`%s%s' not allowed with `%s%c'"),
4259 i
.op
[op
].regs
->reg_name
,
4269 check_long_reg (void)
4273 for (op
= i
.operands
; --op
>= 0;)
4274 /* Reject eight bit registers, except where the template requires
4275 them. (eg. movzb) */
4276 if (i
.types
[op
].bitfield
.reg8
4277 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4278 || i
.tm
.operand_types
[op
].bitfield
.reg32
4279 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4281 as_bad (_("`%s%s' not allowed with `%s%c'"),
4283 i
.op
[op
].regs
->reg_name
,
4288 /* Warn if the e prefix on a general reg is missing. */
4289 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4290 && i
.types
[op
].bitfield
.reg16
4291 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4292 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4294 /* Prohibit these changes in the 64bit mode, since the
4295 lowering is more complicated. */
4296 if (flag_code
== CODE_64BIT
)
4298 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4299 register_prefix
, i
.op
[op
].regs
->reg_name
,
4303 #if REGISTER_WARNINGS
4305 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4307 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4309 i
.op
[op
].regs
->reg_name
,
4313 /* Warn if the r prefix on a general reg is missing. */
4314 else if (i
.types
[op
].bitfield
.reg64
4315 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4316 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4319 && i
.tm
.opcode_modifier
.toqword
4320 && !i
.types
[0].bitfield
.regxmm
)
4322 /* Convert to QWORD. We want REX byte. */
4323 i
.suffix
= QWORD_MNEM_SUFFIX
;
4327 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4328 register_prefix
, i
.op
[op
].regs
->reg_name
,
4337 check_qword_reg (void)
4341 for (op
= i
.operands
; --op
>= 0; )
4342 /* Reject eight bit registers, except where the template requires
4343 them. (eg. movzb) */
4344 if (i
.types
[op
].bitfield
.reg8
4345 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4346 || i
.tm
.operand_types
[op
].bitfield
.reg32
4347 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4349 as_bad (_("`%s%s' not allowed with `%s%c'"),
4351 i
.op
[op
].regs
->reg_name
,
4356 /* Warn if the e prefix on a general reg is missing. */
4357 else if ((i
.types
[op
].bitfield
.reg16
4358 || i
.types
[op
].bitfield
.reg32
)
4359 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4360 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4362 /* Prohibit these changes in the 64bit mode, since the
4363 lowering is more complicated. */
4365 && i
.tm
.opcode_modifier
.todword
4366 && !i
.types
[0].bitfield
.regxmm
)
4368 /* Convert to DWORD. We don't want REX byte. */
4369 i
.suffix
= LONG_MNEM_SUFFIX
;
4373 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4374 register_prefix
, i
.op
[op
].regs
->reg_name
,
4383 check_word_reg (void)
4386 for (op
= i
.operands
; --op
>= 0;)
4387 /* Reject eight bit registers, except where the template requires
4388 them. (eg. movzb) */
4389 if (i
.types
[op
].bitfield
.reg8
4390 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4391 || i
.tm
.operand_types
[op
].bitfield
.reg32
4392 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4394 as_bad (_("`%s%s' not allowed with `%s%c'"),
4396 i
.op
[op
].regs
->reg_name
,
4401 /* Warn if the e prefix on a general reg is present. */
4402 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4403 && i
.types
[op
].bitfield
.reg32
4404 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4405 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4407 /* Prohibit these changes in the 64bit mode, since the
4408 lowering is more complicated. */
4409 if (flag_code
== CODE_64BIT
)
4411 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4412 register_prefix
, i
.op
[op
].regs
->reg_name
,
4417 #if REGISTER_WARNINGS
4418 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4420 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4422 i
.op
[op
].regs
->reg_name
,
4430 update_imm (unsigned int j
)
4432 i386_operand_type overlap
;
4434 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4435 if ((overlap
.bitfield
.imm8
4436 || overlap
.bitfield
.imm8s
4437 || overlap
.bitfield
.imm16
4438 || overlap
.bitfield
.imm32
4439 || overlap
.bitfield
.imm32s
4440 || overlap
.bitfield
.imm64
)
4441 && !operand_type_equal (&overlap
, &imm8
)
4442 && !operand_type_equal (&overlap
, &imm8s
)
4443 && !operand_type_equal (&overlap
, &imm16
)
4444 && !operand_type_equal (&overlap
, &imm32
)
4445 && !operand_type_equal (&overlap
, &imm32s
)
4446 && !operand_type_equal (&overlap
, &imm64
))
4450 i386_operand_type temp
;
4452 operand_type_set (&temp
, 0);
4453 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4455 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4456 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4458 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4459 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4460 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4462 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4463 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4466 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4469 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4470 || operand_type_equal (&overlap
, &imm16_32
)
4471 || operand_type_equal (&overlap
, &imm16_32s
))
4473 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4478 if (!operand_type_equal (&overlap
, &imm8
)
4479 && !operand_type_equal (&overlap
, &imm8s
)
4480 && !operand_type_equal (&overlap
, &imm16
)
4481 && !operand_type_equal (&overlap
, &imm32
)
4482 && !operand_type_equal (&overlap
, &imm32s
)
4483 && !operand_type_equal (&overlap
, &imm64
))
4485 as_bad (_("no instruction mnemonic suffix given; "
4486 "can't determine immediate size"));
4490 i
.types
[j
] = overlap
;
4500 for (j
= 0; j
< 2; j
++)
4501 if (update_imm (j
) == 0)
4504 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4505 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4511 bad_implicit_operand (int xmm
)
4513 const char *reg
= xmm
? "xmm0" : "ymm0";
4515 as_bad (_("the last operand of `%s' must be `%s%s'"),
4516 i
.tm
.name
, register_prefix
, reg
);
4518 as_bad (_("the first operand of `%s' must be `%s%s'"),
4519 i
.tm
.name
, register_prefix
, reg
);
4524 process_operands (void)
4526 /* Default segment register this instruction will use for memory
4527 accesses. 0 means unknown. This is only for optimizing out
4528 unnecessary segment overrides. */
4529 const seg_entry
*default_seg
= 0;
4531 if (i
.tm
.opcode_modifier
.sse2avx
4532 && (i
.tm
.opcode_modifier
.vexnds
4533 || i
.tm
.opcode_modifier
.vexndd
))
4535 unsigned int dup
= i
.operands
;
4536 unsigned int dest
= dup
- 1;
4539 /* The destination must be an xmm register. */
4540 gas_assert (i
.reg_operands
4541 && MAX_OPERANDS
> dup
4542 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4544 if (i
.tm
.opcode_modifier
.firstxmm0
)
4546 /* The first operand is implicit and must be xmm0. */
4547 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4548 if (i
.op
[0].regs
->reg_num
!= 0)
4549 return bad_implicit_operand (1);
4551 if (i
.tm
.opcode_modifier
.vex3sources
)
4553 /* Keep xmm0 for instructions with VEX prefix and 3
4559 /* We remove the first xmm0 and keep the number of
4560 operands unchanged, which in fact duplicates the
4562 for (j
= 1; j
< i
.operands
; j
++)
4564 i
.op
[j
- 1] = i
.op
[j
];
4565 i
.types
[j
- 1] = i
.types
[j
];
4566 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4570 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4572 gas_assert ((MAX_OPERANDS
- 1) > dup
4573 && i
.tm
.opcode_modifier
.vex3sources
);
4575 /* Add the implicit xmm0 for instructions with VEX prefix
4577 for (j
= i
.operands
; j
> 0; j
--)
4579 i
.op
[j
] = i
.op
[j
- 1];
4580 i
.types
[j
] = i
.types
[j
- 1];
4581 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4584 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4585 i
.types
[0] = regxmm
;
4586 i
.tm
.operand_types
[0] = regxmm
;
4589 i
.reg_operands
+= 2;
4594 i
.op
[dup
] = i
.op
[dest
];
4595 i
.types
[dup
] = i
.types
[dest
];
4596 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4605 i
.op
[dup
] = i
.op
[dest
];
4606 i
.types
[dup
] = i
.types
[dest
];
4607 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4610 if (i
.tm
.opcode_modifier
.immext
)
4613 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4617 /* The first operand is implicit and must be xmm0/ymm0. */
4618 gas_assert (i
.reg_operands
4619 && (operand_type_equal (&i
.types
[0], ®xmm
)
4620 || operand_type_equal (&i
.types
[0], ®ymm
)));
4621 if (i
.op
[0].regs
->reg_num
!= 0)
4622 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4624 for (j
= 1; j
< i
.operands
; j
++)
4626 i
.op
[j
- 1] = i
.op
[j
];
4627 i
.types
[j
- 1] = i
.types
[j
];
4629 /* We need to adjust fields in i.tm since they are used by
4630 build_modrm_byte. */
4631 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4638 else if (i
.tm
.opcode_modifier
.regkludge
)
4640 /* The imul $imm, %reg instruction is converted into
4641 imul $imm, %reg, %reg, and the clr %reg instruction
4642 is converted into xor %reg, %reg. */
4644 unsigned int first_reg_op
;
4646 if (operand_type_check (i
.types
[0], reg
))
4650 /* Pretend we saw the extra register operand. */
4651 gas_assert (i
.reg_operands
== 1
4652 && i
.op
[first_reg_op
+ 1].regs
== 0);
4653 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4654 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4659 if (i
.tm
.opcode_modifier
.shortform
)
4661 if (i
.types
[0].bitfield
.sreg2
4662 || i
.types
[0].bitfield
.sreg3
)
4664 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4665 && i
.op
[0].regs
->reg_num
== 1)
4667 as_bad (_("you can't `pop %scs'"), register_prefix
);
4670 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4671 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4676 /* The register or float register operand is in operand
4680 if (i
.types
[0].bitfield
.floatreg
4681 || operand_type_check (i
.types
[0], reg
))
4685 /* Register goes in low 3 bits of opcode. */
4686 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4687 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4689 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4691 /* Warn about some common errors, but press on regardless.
4692 The first case can be generated by gcc (<= 2.8.1). */
4693 if (i
.operands
== 2)
4695 /* Reversed arguments on faddp, fsubp, etc. */
4696 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4697 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4698 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4702 /* Extraneous `l' suffix on fp insn. */
4703 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4704 register_prefix
, i
.op
[0].regs
->reg_name
);
4709 else if (i
.tm
.opcode_modifier
.modrm
)
4711 /* The opcode is completed (modulo i.tm.extension_opcode which
4712 must be put into the modrm byte). Now, we make the modrm and
4713 index base bytes based on all the info we've collected. */
4715 default_seg
= build_modrm_byte ();
4717 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4721 else if (i
.tm
.opcode_modifier
.isstring
)
4723 /* For the string instructions that allow a segment override
4724 on one of their operands, the default segment is ds. */
4728 if (i
.tm
.base_opcode
== 0x8d /* lea */
4731 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4733 /* If a segment was explicitly specified, and the specified segment
4734 is not the default, use an opcode prefix to select it. If we
4735 never figured out what the default segment is, then default_seg
4736 will be zero at this point, and the specified segment prefix will
4738 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4740 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4746 static const seg_entry
*
4747 build_modrm_byte (void)
4749 const seg_entry
*default_seg
= 0;
4750 unsigned int source
, dest
;
4753 /* The first operand of instructions with VEX prefix and 3 sources
4754 must be VEX_Imm4. */
4755 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4758 unsigned int nds
, reg
;
4760 dest
= i
.operands
- 1;
4765 /* This instruction must have 4 operands: 4 register operands
4766 or 3 register operands plus 1 memory operand. It must have
4767 VexNDS and VexImmExt. */
4768 gas_assert (i
.operands
== 4
4769 && (i
.reg_operands
== 4
4770 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4771 && i
.tm
.opcode_modifier
.vexnds
4772 && i
.tm
.opcode_modifier
.veximmext
4773 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
4775 || operand_type_equal (&i
.tm
.operand_types
[dest
],
4777 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
4779 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4781 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
4783 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4786 /* Generate an 8bit immediate operand to encode the register
4788 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
4789 i
.op
[i
.operands
].imms
= exp
;
4790 i
.types
[i
.operands
] = imm8
;
4792 exp
->X_op
= O_constant
;
4794 = ((i
.op
[0].regs
->reg_num
4795 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4797 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4802 /* i.reg_operands MUST be the number of real register operands;
4803 implicit registers do not count. If there are 3 register
4804 operands, it must be a instruction with VexNDS. For a
4805 instruction with VexNDD, the destination register is encoded
4806 in VEX prefix. If there are 4 register operands, it must be
4807 a instruction with VEX prefix and 3 sources. */
4808 if (i
.mem_operands
== 0
4809 && ((i
.reg_operands
== 2
4810 && !i
.tm
.opcode_modifier
.vexndd
)
4811 || (i
.reg_operands
== 3
4812 && i
.tm
.opcode_modifier
.vexnds
)
4813 || (i
.reg_operands
== 4 && vex_3_sources
)))
4821 /* When there are 3 operands, one of them may be immediate,
4822 which may be the first or the last operand. Otherwise,
4823 the first operand must be shift count register (cl) or it
4824 is an instruction with VexNDS. */
4825 gas_assert (i
.imm_operands
== 1
4826 || (i
.imm_operands
== 0
4827 && (i
.tm
.opcode_modifier
.vexnds
4828 || i
.types
[0].bitfield
.shiftcount
)));
4829 if (operand_type_check (i
.types
[0], imm
)
4830 || i
.types
[0].bitfield
.shiftcount
)
4836 /* When there are 4 operands, the first two must be 8bit
4837 immediate operands. The source operand will be the 3rd
4840 For instructions with VexNDS, if the first operand
4841 an imm8, the source operand is the 2nd one. If the last
4842 operand is imm8, the source operand is the first one. */
4843 gas_assert ((i
.imm_operands
== 2
4844 && i
.types
[0].bitfield
.imm8
4845 && i
.types
[1].bitfield
.imm8
)
4846 || (i
.tm
.opcode_modifier
.vexnds
4847 && i
.imm_operands
== 1
4848 && (i
.types
[0].bitfield
.imm8
4849 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4850 if (i
.tm
.opcode_modifier
.vexnds
)
4852 if (i
.types
[0].bitfield
.imm8
)
4870 if (i
.tm
.opcode_modifier
.vexnds
)
4872 /* For instructions with VexNDS, the register-only
4873 source operand must be XMM or YMM register. It is
4874 encoded in VEX prefix. We need to clear RegMem bit
4875 before calling operand_type_equal. */
4876 i386_operand_type op
= i
.tm
.operand_types
[dest
];
4877 op
.bitfield
.regmem
= 0;
4878 if ((dest
+ 1) >= i
.operands
4879 || (!operand_type_equal (&op
, ®xmm
)
4880 && !operand_type_equal (&op
, ®ymm
)))
4882 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
4888 /* One of the register operands will be encoded in the i.tm.reg
4889 field, the other in the combined i.tm.mode and i.tm.regmem
4890 fields. If no form of this instruction supports a memory
4891 destination operand, then we assume the source operand may
4892 sometimes be a memory operand and so we need to store the
4893 destination in the i.rm.reg field. */
4894 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
4895 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
4897 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
4898 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
4899 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4901 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4906 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
4907 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
4908 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
4910 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
4913 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
4915 if (!i
.types
[0].bitfield
.control
4916 && !i
.types
[1].bitfield
.control
)
4918 i
.rex
&= ~(REX_R
| REX_B
);
4919 add_prefix (LOCK_PREFIX_OPCODE
);
4923 { /* If it's not 2 reg operands... */
4928 unsigned int fake_zero_displacement
= 0;
4931 for (op
= 0; op
< i
.operands
; op
++)
4932 if (operand_type_check (i
.types
[op
], anymem
))
4935 gas_assert (op
< i
.operands
);
4939 if (i
.base_reg
== 0)
4942 if (!i
.disp_operands
)
4943 fake_zero_displacement
= 1;
4944 if (i
.index_reg
== 0)
4946 /* Operand is just <disp> */
4947 if (flag_code
== CODE_64BIT
)
4949 /* 64bit mode overwrites the 32bit absolute
4950 addressing by RIP relative addressing and
4951 absolute addressing is encoded by one of the
4952 redundant SIB forms. */
4953 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4954 i
.sib
.base
= NO_BASE_REGISTER
;
4955 i
.sib
.index
= NO_INDEX_REGISTER
;
4956 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
4957 ? disp32s
: disp32
);
4959 else if ((flag_code
== CODE_16BIT
)
4960 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
4962 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
4963 i
.types
[op
] = disp16
;
4967 i
.rm
.regmem
= NO_BASE_REGISTER
;
4968 i
.types
[op
] = disp32
;
4971 else /* !i.base_reg && i.index_reg */
4973 if (i
.index_reg
->reg_num
== RegEiz
4974 || i
.index_reg
->reg_num
== RegRiz
)
4975 i
.sib
.index
= NO_INDEX_REGISTER
;
4977 i
.sib
.index
= i
.index_reg
->reg_num
;
4978 i
.sib
.base
= NO_BASE_REGISTER
;
4979 i
.sib
.scale
= i
.log2_scale_factor
;
4980 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
4981 i
.types
[op
].bitfield
.disp8
= 0;
4982 i
.types
[op
].bitfield
.disp16
= 0;
4983 i
.types
[op
].bitfield
.disp64
= 0;
4984 if (flag_code
!= CODE_64BIT
)
4986 /* Must be 32 bit */
4987 i
.types
[op
].bitfield
.disp32
= 1;
4988 i
.types
[op
].bitfield
.disp32s
= 0;
4992 i
.types
[op
].bitfield
.disp32
= 0;
4993 i
.types
[op
].bitfield
.disp32s
= 1;
4995 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
4999 /* RIP addressing for 64bit mode. */
5000 else if (i
.base_reg
->reg_num
== RegRip
||
5001 i
.base_reg
->reg_num
== RegEip
)
5003 i
.rm
.regmem
= NO_BASE_REGISTER
;
5004 i
.types
[op
].bitfield
.disp8
= 0;
5005 i
.types
[op
].bitfield
.disp16
= 0;
5006 i
.types
[op
].bitfield
.disp32
= 0;
5007 i
.types
[op
].bitfield
.disp32s
= 1;
5008 i
.types
[op
].bitfield
.disp64
= 0;
5009 i
.flags
[op
] |= Operand_PCrel
;
5010 if (! i
.disp_operands
)
5011 fake_zero_displacement
= 1;
5013 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5015 switch (i
.base_reg
->reg_num
)
5018 if (i
.index_reg
== 0)
5020 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5021 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5025 if (i
.index_reg
== 0)
5028 if (operand_type_check (i
.types
[op
], disp
) == 0)
5030 /* fake (%bp) into 0(%bp) */
5031 i
.types
[op
].bitfield
.disp8
= 1;
5032 fake_zero_displacement
= 1;
5035 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5036 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5038 default: /* (%si) -> 4 or (%di) -> 5 */
5039 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5041 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5043 else /* i.base_reg and 32/64 bit mode */
5045 if (flag_code
== CODE_64BIT
5046 && operand_type_check (i
.types
[op
], disp
))
5048 i386_operand_type temp
;
5049 operand_type_set (&temp
, 0);
5050 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5052 if (i
.prefix
[ADDR_PREFIX
] == 0)
5053 i
.types
[op
].bitfield
.disp32s
= 1;
5055 i
.types
[op
].bitfield
.disp32
= 1;
5058 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5059 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5061 i
.sib
.base
= i
.base_reg
->reg_num
;
5062 /* x86-64 ignores REX prefix bit here to avoid decoder
5064 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5067 if (i
.disp_operands
== 0)
5069 fake_zero_displacement
= 1;
5070 i
.types
[op
].bitfield
.disp8
= 1;
5073 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5077 i
.sib
.scale
= i
.log2_scale_factor
;
5078 if (i
.index_reg
== 0)
5080 /* <disp>(%esp) becomes two byte modrm with no index
5081 register. We've already stored the code for esp
5082 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5083 Any base register besides %esp will not use the
5084 extra modrm byte. */
5085 i
.sib
.index
= NO_INDEX_REGISTER
;
5089 if (i
.index_reg
->reg_num
== RegEiz
5090 || i
.index_reg
->reg_num
== RegRiz
)
5091 i
.sib
.index
= NO_INDEX_REGISTER
;
5093 i
.sib
.index
= i
.index_reg
->reg_num
;
5094 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5095 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5100 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5101 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5104 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5107 if (fake_zero_displacement
)
5109 /* Fakes a zero displacement assuming that i.types[op]
5110 holds the correct displacement size. */
5113 gas_assert (i
.op
[op
].disps
== 0);
5114 exp
= &disp_expressions
[i
.disp_operands
++];
5115 i
.op
[op
].disps
= exp
;
5116 exp
->X_op
= O_constant
;
5117 exp
->X_add_number
= 0;
5118 exp
->X_add_symbol
= (symbolS
*) 0;
5119 exp
->X_op_symbol
= (symbolS
*) 0;
5127 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5128 (if any) based on i.tm.extension_opcode. Again, we must be
5129 careful to make sure that segment/control/debug/test/MMX
5130 registers are coded into the i.rm.reg field. */
5134 unsigned int vex_reg
= ~0;
5136 for (op
= 0; op
< i
.operands
; op
++)
5137 if (i
.types
[op
].bitfield
.reg8
5138 || i
.types
[op
].bitfield
.reg16
5139 || i
.types
[op
].bitfield
.reg32
5140 || i
.types
[op
].bitfield
.reg64
5141 || i
.types
[op
].bitfield
.regmmx
5142 || i
.types
[op
].bitfield
.regxmm
5143 || i
.types
[op
].bitfield
.regymm
5144 || i
.types
[op
].bitfield
.sreg2
5145 || i
.types
[op
].bitfield
.sreg3
5146 || i
.types
[op
].bitfield
.control
5147 || i
.types
[op
].bitfield
.debug
5148 || i
.types
[op
].bitfield
.test
)
5153 else if (i
.tm
.opcode_modifier
.vexnds
)
5155 /* For instructions with VexNDS, the register-only
5156 source operand is encoded in VEX prefix. */
5157 gas_assert (mem
!= (unsigned int) ~0);
5162 gas_assert (op
< i
.operands
);
5167 gas_assert (vex_reg
< i
.operands
);
5170 else if (i
.tm
.opcode_modifier
.vexndd
)
5172 /* For instructions with VexNDD, there should be
5173 no memory operand and the register destination
5174 is encoded in VEX prefix. */
5175 gas_assert (i
.mem_operands
== 0
5176 && (op
+ 2) == i
.operands
);
5180 gas_assert (op
< i
.operands
);
5182 if (vex_reg
!= (unsigned int) ~0)
5184 gas_assert (i
.reg_operands
== 2);
5186 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5188 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5191 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5194 /* If there is an extension opcode to put here, the
5195 register number must be put into the regmem field. */
5196 if (i
.tm
.extension_opcode
!= None
)
5198 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5199 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5204 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5205 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5209 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5210 must set it to 3 to indicate this is a register operand
5211 in the regmem field. */
5212 if (!i
.mem_operands
)
5216 /* Fill in i.rm.reg field with extension opcode (if any). */
5217 if (i
.tm
.extension_opcode
!= None
)
5218 i
.rm
.reg
= i
.tm
.extension_opcode
;
5224 output_branch (void)
5229 relax_substateT subtype
;
5234 if (flag_code
== CODE_16BIT
)
5238 if (i
.prefix
[DATA_PREFIX
] != 0)
5244 /* Pentium4 branch hints. */
5245 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5246 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5251 if (i
.prefix
[REX_PREFIX
] != 0)
5257 if (i
.prefixes
!= 0 && !intel_syntax
)
5258 as_warn (_("skipping prefixes on this instruction"));
5260 /* It's always a symbol; End frag & setup for relax.
5261 Make sure there is enough room in this frag for the largest
5262 instruction we may generate in md_convert_frag. This is 2
5263 bytes for the opcode and room for the prefix and largest
5265 frag_grow (prefix
+ 2 + 4);
5266 /* Prefix and 1 opcode byte go in fr_fix. */
5267 p
= frag_more (prefix
+ 1);
5268 if (i
.prefix
[DATA_PREFIX
] != 0)
5269 *p
++ = DATA_PREFIX_OPCODE
;
5270 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5271 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5272 *p
++ = i
.prefix
[SEG_PREFIX
];
5273 if (i
.prefix
[REX_PREFIX
] != 0)
5274 *p
++ = i
.prefix
[REX_PREFIX
];
5275 *p
= i
.tm
.base_opcode
;
5277 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5278 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5279 else if (cpu_arch_flags
.bitfield
.cpui386
)
5280 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5282 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5285 sym
= i
.op
[0].disps
->X_add_symbol
;
5286 off
= i
.op
[0].disps
->X_add_number
;
5288 if (i
.op
[0].disps
->X_op
!= O_constant
5289 && i
.op
[0].disps
->X_op
!= O_symbol
)
5291 /* Handle complex expressions. */
5292 sym
= make_expr_symbol (i
.op
[0].disps
);
5296 /* 1 possible extra opcode + 4 byte displacement go in var part.
5297 Pass reloc in fr_var. */
5298 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5308 if (i
.tm
.opcode_modifier
.jumpbyte
)
5310 /* This is a loop or jecxz type instruction. */
5312 if (i
.prefix
[ADDR_PREFIX
] != 0)
5314 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5317 /* Pentium4 branch hints. */
5318 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5319 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5321 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5330 if (flag_code
== CODE_16BIT
)
5333 if (i
.prefix
[DATA_PREFIX
] != 0)
5335 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5345 if (i
.prefix
[REX_PREFIX
] != 0)
5347 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5351 if (i
.prefixes
!= 0 && !intel_syntax
)
5352 as_warn (_("skipping prefixes on this instruction"));
5354 p
= frag_more (1 + size
);
5355 *p
++ = i
.tm
.base_opcode
;
5357 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5358 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5360 /* All jumps handled here are signed, but don't use a signed limit
5361 check for 32 and 16 bit jumps as we want to allow wrap around at
5362 4G and 64k respectively. */
5364 fixP
->fx_signed
= 1;
5368 output_interseg_jump (void)
5376 if (flag_code
== CODE_16BIT
)
5380 if (i
.prefix
[DATA_PREFIX
] != 0)
5386 if (i
.prefix
[REX_PREFIX
] != 0)
5396 if (i
.prefixes
!= 0 && !intel_syntax
)
5397 as_warn (_("skipping prefixes on this instruction"));
5399 /* 1 opcode; 2 segment; offset */
5400 p
= frag_more (prefix
+ 1 + 2 + size
);
5402 if (i
.prefix
[DATA_PREFIX
] != 0)
5403 *p
++ = DATA_PREFIX_OPCODE
;
5405 if (i
.prefix
[REX_PREFIX
] != 0)
5406 *p
++ = i
.prefix
[REX_PREFIX
];
5408 *p
++ = i
.tm
.base_opcode
;
5409 if (i
.op
[1].imms
->X_op
== O_constant
)
5411 offsetT n
= i
.op
[1].imms
->X_add_number
;
5414 && !fits_in_unsigned_word (n
)
5415 && !fits_in_signed_word (n
))
5417 as_bad (_("16-bit jump out of range"));
5420 md_number_to_chars (p
, n
, size
);
5423 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5424 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5425 if (i
.op
[0].imms
->X_op
!= O_constant
)
5426 as_bad (_("can't handle non absolute segment in `%s'"),
5428 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5434 fragS
*insn_start_frag
;
5435 offsetT insn_start_off
;
5437 /* Tie dwarf2 debug info to the address at the start of the insn.
5438 We can't do this after the insn has been output as the current
5439 frag may have been closed off. eg. by frag_var. */
5440 dwarf2_emit_insn (0);
5442 insn_start_frag
= frag_now
;
5443 insn_start_off
= frag_now_fix ();
5446 if (i
.tm
.opcode_modifier
.jump
)
5448 else if (i
.tm
.opcode_modifier
.jumpbyte
5449 || i
.tm
.opcode_modifier
.jumpdword
)
5451 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5452 output_interseg_jump ();
5455 /* Output normal instructions here. */
5459 unsigned int prefix
;
5461 /* Since the VEX prefix contains the implicit prefix, we don't
5462 need the explicit prefix. */
5463 if (!i
.tm
.opcode_modifier
.vex
)
5465 switch (i
.tm
.opcode_length
)
5468 if (i
.tm
.base_opcode
& 0xff000000)
5470 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5475 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5477 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5478 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5481 if (prefix
!= REPE_PREFIX_OPCODE
5482 || (i
.prefix
[LOCKREP_PREFIX
]
5483 != REPE_PREFIX_OPCODE
))
5484 add_prefix (prefix
);
5487 add_prefix (prefix
);
5496 /* The prefix bytes. */
5497 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5499 FRAG_APPEND_1_CHAR (*q
);
5502 if (i
.tm
.opcode_modifier
.vex
)
5504 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5509 /* REX byte is encoded in VEX prefix. */
5513 FRAG_APPEND_1_CHAR (*q
);
5516 /* There should be no other prefixes for instructions
5521 /* Now the VEX prefix. */
5522 p
= frag_more (i
.vex
.length
);
5523 for (j
= 0; j
< i
.vex
.length
; j
++)
5524 p
[j
] = i
.vex
.bytes
[j
];
5527 /* Now the opcode; be careful about word order here! */
5528 if (i
.tm
.opcode_length
== 1)
5530 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5534 switch (i
.tm
.opcode_length
)
5538 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5548 /* Put out high byte first: can't use md_number_to_chars! */
5549 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5550 *p
= i
.tm
.base_opcode
& 0xff;
5553 /* Now the modrm byte and sib byte (if present). */
5554 if (i
.tm
.opcode_modifier
.modrm
)
5556 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5559 /* If i.rm.regmem == ESP (4)
5560 && i.rm.mode != (Register mode)
5562 ==> need second modrm byte. */
5563 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5565 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5566 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5568 | i
.sib
.scale
<< 6));
5571 if (i
.disp_operands
)
5572 output_disp (insn_start_frag
, insn_start_off
);
5575 output_imm (insn_start_frag
, insn_start_off
);
5581 pi ("" /*line*/, &i
);
5583 #endif /* DEBUG386 */
5586 /* Return the size of the displacement operand N. */
5589 disp_size (unsigned int n
)
5592 if (i
.types
[n
].bitfield
.disp64
)
5594 else if (i
.types
[n
].bitfield
.disp8
)
5596 else if (i
.types
[n
].bitfield
.disp16
)
5601 /* Return the size of the immediate operand N. */
5604 imm_size (unsigned int n
)
5607 if (i
.types
[n
].bitfield
.imm64
)
5609 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5611 else if (i
.types
[n
].bitfield
.imm16
)
5617 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5622 for (n
= 0; n
< i
.operands
; n
++)
5624 if (operand_type_check (i
.types
[n
], disp
))
5626 if (i
.op
[n
].disps
->X_op
== O_constant
)
5628 int size
= disp_size (n
);
5631 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5633 p
= frag_more (size
);
5634 md_number_to_chars (p
, val
, size
);
5638 enum bfd_reloc_code_real reloc_type
;
5639 int size
= disp_size (n
);
5640 int sign
= i
.types
[n
].bitfield
.disp32s
;
5641 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5643 /* We can't have 8 bit displacement here. */
5644 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5646 /* The PC relative address is computed relative
5647 to the instruction boundary, so in case immediate
5648 fields follows, we need to adjust the value. */
5649 if (pcrel
&& i
.imm_operands
)
5654 for (n1
= 0; n1
< i
.operands
; n1
++)
5655 if (operand_type_check (i
.types
[n1
], imm
))
5657 /* Only one immediate is allowed for PC
5658 relative address. */
5659 gas_assert (sz
== 0);
5661 i
.op
[n
].disps
->X_add_number
-= sz
;
5663 /* We should find the immediate. */
5664 gas_assert (sz
!= 0);
5667 p
= frag_more (size
);
5668 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5670 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5671 && (((reloc_type
== BFD_RELOC_32
5672 || reloc_type
== BFD_RELOC_X86_64_32S
5673 || (reloc_type
== BFD_RELOC_64
5675 && (i
.op
[n
].disps
->X_op
== O_symbol
5676 || (i
.op
[n
].disps
->X_op
== O_add
5677 && ((symbol_get_value_expression
5678 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5680 || reloc_type
== BFD_RELOC_32_PCREL
))
5684 if (insn_start_frag
== frag_now
)
5685 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5690 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5691 for (fr
= insn_start_frag
->fr_next
;
5692 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5694 add
+= p
- frag_now
->fr_literal
;
5699 reloc_type
= BFD_RELOC_386_GOTPC
;
5700 i
.op
[n
].imms
->X_add_number
+= add
;
5702 else if (reloc_type
== BFD_RELOC_64
)
5703 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5705 /* Don't do the adjustment for x86-64, as there
5706 the pcrel addressing is relative to the _next_
5707 insn, and that is taken care of in other code. */
5708 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5710 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5711 i
.op
[n
].disps
, pcrel
, reloc_type
);
5718 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5723 for (n
= 0; n
< i
.operands
; n
++)
5725 if (operand_type_check (i
.types
[n
], imm
))
5727 if (i
.op
[n
].imms
->X_op
== O_constant
)
5729 int size
= imm_size (n
);
5732 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5734 p
= frag_more (size
);
5735 md_number_to_chars (p
, val
, size
);
5739 /* Not absolute_section.
5740 Need a 32-bit fixup (don't support 8bit
5741 non-absolute imms). Try to support other
5743 enum bfd_reloc_code_real reloc_type
;
5744 int size
= imm_size (n
);
5747 if (i
.types
[n
].bitfield
.imm32s
5748 && (i
.suffix
== QWORD_MNEM_SUFFIX
5749 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5754 p
= frag_more (size
);
5755 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5757 /* This is tough to explain. We end up with this one if we
5758 * have operands that look like
5759 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5760 * obtain the absolute address of the GOT, and it is strongly
5761 * preferable from a performance point of view to avoid using
5762 * a runtime relocation for this. The actual sequence of
5763 * instructions often look something like:
5768 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5770 * The call and pop essentially return the absolute address
5771 * of the label .L66 and store it in %ebx. The linker itself
5772 * will ultimately change the first operand of the addl so
5773 * that %ebx points to the GOT, but to keep things simple, the
5774 * .o file must have this operand set so that it generates not
5775 * the absolute address of .L66, but the absolute address of
5776 * itself. This allows the linker itself simply treat a GOTPC
5777 * relocation as asking for a pcrel offset to the GOT to be
5778 * added in, and the addend of the relocation is stored in the
5779 * operand field for the instruction itself.
5781 * Our job here is to fix the operand so that it would add
5782 * the correct offset so that %ebx would point to itself. The
5783 * thing that is tricky is that .-.L66 will point to the
5784 * beginning of the instruction, so we need to further modify
5785 * the operand so that it will point to itself. There are
5786 * other cases where you have something like:
5788 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5790 * and here no correction would be required. Internally in
5791 * the assembler we treat operands of this form as not being
5792 * pcrel since the '.' is explicitly mentioned, and I wonder
5793 * whether it would simplify matters to do it this way. Who
5794 * knows. In earlier versions of the PIC patches, the
5795 * pcrel_adjust field was used to store the correction, but
5796 * since the expression is not pcrel, I felt it would be
5797 * confusing to do it this way. */
5799 if ((reloc_type
== BFD_RELOC_32
5800 || reloc_type
== BFD_RELOC_X86_64_32S
5801 || reloc_type
== BFD_RELOC_64
)
5803 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5804 && (i
.op
[n
].imms
->X_op
== O_symbol
5805 || (i
.op
[n
].imms
->X_op
== O_add
5806 && ((symbol_get_value_expression
5807 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5812 if (insn_start_frag
== frag_now
)
5813 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5818 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5819 for (fr
= insn_start_frag
->fr_next
;
5820 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5822 add
+= p
- frag_now
->fr_literal
;
5826 reloc_type
= BFD_RELOC_386_GOTPC
;
5828 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5830 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5831 i
.op
[n
].imms
->X_add_number
+= add
;
5833 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5834 i
.op
[n
].imms
, 0, reloc_type
);
5840 /* x86_cons_fix_new is called via the expression parsing code when a
5841 reloc is needed. We use this hook to get the correct .got reloc. */
5842 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5843 static int cons_sign
= -1;
5846 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
5849 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
5851 got_reloc
= NO_RELOC
;
5854 if (exp
->X_op
== O_secrel
)
5856 exp
->X_op
= O_symbol
;
5857 r
= BFD_RELOC_32_SECREL
;
5861 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
5864 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
5865 # define lex_got(reloc, adjust, types) NULL
5867 /* Parse operands of the form
5868 <symbol>@GOTOFF+<nnn>
5869 and similar .plt or .got references.
5871 If we find one, set up the correct relocation in RELOC and copy the
5872 input string, minus the `@GOTOFF' into a malloc'd buffer for
5873 parsing by the calling routine. Return this buffer, and if ADJUST
5874 is non-null set it to the length of the string we removed from the
5875 input line. Otherwise return NULL. */
5877 lex_got (enum bfd_reloc_code_real
*reloc
,
5879 i386_operand_type
*types
)
5881 /* Some of the relocations depend on the size of what field is to
5882 be relocated. But in our callers i386_immediate and i386_displacement
5883 we don't yet know the operand size (this will be set by insn
5884 matching). Hence we record the word32 relocation here,
5885 and adjust the reloc according to the real size in reloc(). */
5886 static const struct {
5888 const enum bfd_reloc_code_real rel
[2];
5889 const i386_operand_type types64
;
5892 BFD_RELOC_X86_64_PLTOFF64
},
5893 OPERAND_TYPE_IMM64
},
5894 { "PLT", { BFD_RELOC_386_PLT32
,
5895 BFD_RELOC_X86_64_PLT32
},
5896 OPERAND_TYPE_IMM32_32S_DISP32
},
5898 BFD_RELOC_X86_64_GOTPLT64
},
5899 OPERAND_TYPE_IMM64_DISP64
},
5900 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
5901 BFD_RELOC_X86_64_GOTOFF64
},
5902 OPERAND_TYPE_IMM64_DISP64
},
5904 BFD_RELOC_X86_64_GOTPCREL
},
5905 OPERAND_TYPE_IMM32_32S_DISP32
},
5906 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
5907 BFD_RELOC_X86_64_TLSGD
},
5908 OPERAND_TYPE_IMM32_32S_DISP32
},
5909 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
5911 OPERAND_TYPE_NONE
},
5913 BFD_RELOC_X86_64_TLSLD
},
5914 OPERAND_TYPE_IMM32_32S_DISP32
},
5915 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
5916 BFD_RELOC_X86_64_GOTTPOFF
},
5917 OPERAND_TYPE_IMM32_32S_DISP32
},
5918 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
5919 BFD_RELOC_X86_64_TPOFF32
},
5920 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5921 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
5923 OPERAND_TYPE_NONE
},
5924 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
5925 BFD_RELOC_X86_64_DTPOFF32
},
5927 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
5928 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
5930 OPERAND_TYPE_NONE
},
5931 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
5933 OPERAND_TYPE_NONE
},
5934 { "GOT", { BFD_RELOC_386_GOT32
,
5935 BFD_RELOC_X86_64_GOT32
},
5936 OPERAND_TYPE_IMM32_32S_64_DISP32
},
5937 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
5938 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
5939 OPERAND_TYPE_IMM32_32S_DISP32
},
5940 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
5941 BFD_RELOC_X86_64_TLSDESC_CALL
},
5942 OPERAND_TYPE_IMM32_32S_DISP32
},
5950 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
5951 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
5954 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
5958 len
= strlen (gotrel
[j
].str
);
5959 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
5961 if (gotrel
[j
].rel
[object_64bit
] != 0)
5964 char *tmpbuf
, *past_reloc
;
5966 *reloc
= gotrel
[j
].rel
[object_64bit
];
5972 if (flag_code
!= CODE_64BIT
)
5974 types
->bitfield
.imm32
= 1;
5975 types
->bitfield
.disp32
= 1;
5978 *types
= gotrel
[j
].types64
;
5981 if (GOT_symbol
== NULL
)
5982 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
5984 /* The length of the first part of our input line. */
5985 first
= cp
- input_line_pointer
;
5987 /* The second part goes from after the reloc token until
5988 (and including) an end_of_line char or comma. */
5989 past_reloc
= cp
+ 1 + len
;
5991 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
5993 second
= cp
+ 1 - past_reloc
;
5995 /* Allocate and copy string. The trailing NUL shouldn't
5996 be necessary, but be safe. */
5997 tmpbuf
= xmalloc (first
+ second
+ 2);
5998 memcpy (tmpbuf
, input_line_pointer
, first
);
5999 if (second
!= 0 && *past_reloc
!= ' ')
6000 /* Replace the relocation token with ' ', so that
6001 errors like foo@GOTOFF1 will be detected. */
6002 tmpbuf
[first
++] = ' ';
6003 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6004 tmpbuf
[first
+ second
] = '\0';
6008 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6009 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6014 /* Might be a symbol version string. Don't as_bad here. */
6019 x86_cons (expressionS
*exp
, int size
)
6021 intel_syntax
= -intel_syntax
;
6023 if (size
== 4 || (object_64bit
&& size
== 8))
6025 /* Handle @GOTOFF and the like in an expression. */
6027 char *gotfree_input_line
;
6030 save
= input_line_pointer
;
6031 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6032 if (gotfree_input_line
)
6033 input_line_pointer
= gotfree_input_line
;
6037 if (gotfree_input_line
)
6039 /* expression () has merrily parsed up to the end of line,
6040 or a comma - in the wrong buffer. Transfer how far
6041 input_line_pointer has moved to the right buffer. */
6042 input_line_pointer
= (save
6043 + (input_line_pointer
- gotfree_input_line
)
6045 free (gotfree_input_line
);
6046 if (exp
->X_op
== O_constant
6047 || exp
->X_op
== O_absent
6048 || exp
->X_op
== O_illegal
6049 || exp
->X_op
== O_register
6050 || exp
->X_op
== O_big
)
6052 char c
= *input_line_pointer
;
6053 *input_line_pointer
= 0;
6054 as_bad (_("missing or invalid expression `%s'"), save
);
6055 *input_line_pointer
= c
;
6062 intel_syntax
= -intel_syntax
;
6065 i386_intel_simplify (exp
);
6069 static void signed_cons (int size
)
6071 if (flag_code
== CODE_64BIT
)
6079 pe_directive_secrel (dummy
)
6080 int dummy ATTRIBUTE_UNUSED
;
6087 if (exp
.X_op
== O_symbol
)
6088 exp
.X_op
= O_secrel
;
6090 emit_expr (&exp
, 4);
6092 while (*input_line_pointer
++ == ',');
6094 input_line_pointer
--;
6095 demand_empty_rest_of_line ();
6100 i386_immediate (char *imm_start
)
6102 char *save_input_line_pointer
;
6103 char *gotfree_input_line
;
6106 i386_operand_type types
;
6108 operand_type_set (&types
, ~0);
6110 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6112 as_bad (_("at most %d immediate operands are allowed"),
6113 MAX_IMMEDIATE_OPERANDS
);
6117 exp
= &im_expressions
[i
.imm_operands
++];
6118 i
.op
[this_operand
].imms
= exp
;
6120 if (is_space_char (*imm_start
))
6123 save_input_line_pointer
= input_line_pointer
;
6124 input_line_pointer
= imm_start
;
6126 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6127 if (gotfree_input_line
)
6128 input_line_pointer
= gotfree_input_line
;
6130 exp_seg
= expression (exp
);
6133 if (*input_line_pointer
)
6134 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6136 input_line_pointer
= save_input_line_pointer
;
6137 if (gotfree_input_line
)
6139 free (gotfree_input_line
);
6141 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6142 exp
->X_op
= O_illegal
;
6145 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6149 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6150 i386_operand_type types
, const char *imm_start
)
6152 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6154 as_bad (_("missing or invalid immediate expression `%s'"),
6158 else if (exp
->X_op
== O_constant
)
6160 /* Size it properly later. */
6161 i
.types
[this_operand
].bitfield
.imm64
= 1;
6162 /* If BFD64, sign extend val. */
6163 if (!use_rela_relocations
6164 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6166 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6168 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6169 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6170 && exp_seg
!= absolute_section
6171 && exp_seg
!= text_section
6172 && exp_seg
!= data_section
6173 && exp_seg
!= bss_section
6174 && exp_seg
!= undefined_section
6175 && !bfd_is_com_section (exp_seg
))
6177 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6181 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6183 as_bad (_("illegal immediate register operand %s"), imm_start
);
6188 /* This is an address. The size of the address will be
6189 determined later, depending on destination register,
6190 suffix, or the default for the section. */
6191 i
.types
[this_operand
].bitfield
.imm8
= 1;
6192 i
.types
[this_operand
].bitfield
.imm16
= 1;
6193 i
.types
[this_operand
].bitfield
.imm32
= 1;
6194 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6195 i
.types
[this_operand
].bitfield
.imm64
= 1;
6196 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6204 i386_scale (char *scale
)
6207 char *save
= input_line_pointer
;
6209 input_line_pointer
= scale
;
6210 val
= get_absolute_expression ();
6215 i
.log2_scale_factor
= 0;
6218 i
.log2_scale_factor
= 1;
6221 i
.log2_scale_factor
= 2;
6224 i
.log2_scale_factor
= 3;
6228 char sep
= *input_line_pointer
;
6230 *input_line_pointer
= '\0';
6231 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6233 *input_line_pointer
= sep
;
6234 input_line_pointer
= save
;
6238 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6240 as_warn (_("scale factor of %d without an index register"),
6241 1 << i
.log2_scale_factor
);
6242 i
.log2_scale_factor
= 0;
6244 scale
= input_line_pointer
;
6245 input_line_pointer
= save
;
6250 i386_displacement (char *disp_start
, char *disp_end
)
6254 char *save_input_line_pointer
;
6255 char *gotfree_input_line
;
6257 i386_operand_type bigdisp
, types
= anydisp
;
6260 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6262 as_bad (_("at most %d displacement operands are allowed"),
6263 MAX_MEMORY_OPERANDS
);
6267 operand_type_set (&bigdisp
, 0);
6268 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6269 || (!current_templates
->start
->opcode_modifier
.jump
6270 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6272 bigdisp
.bitfield
.disp32
= 1;
6273 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6274 if (flag_code
== CODE_64BIT
)
6278 bigdisp
.bitfield
.disp32s
= 1;
6279 bigdisp
.bitfield
.disp64
= 1;
6282 else if ((flag_code
== CODE_16BIT
) ^ override
)
6284 bigdisp
.bitfield
.disp32
= 0;
6285 bigdisp
.bitfield
.disp16
= 1;
6290 /* For PC-relative branches, the width of the displacement
6291 is dependent upon data size, not address size. */
6292 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6293 if (flag_code
== CODE_64BIT
)
6295 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6296 bigdisp
.bitfield
.disp16
= 1;
6299 bigdisp
.bitfield
.disp32
= 1;
6300 bigdisp
.bitfield
.disp32s
= 1;
6306 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6308 : LONG_MNEM_SUFFIX
));
6309 bigdisp
.bitfield
.disp32
= 1;
6310 if ((flag_code
== CODE_16BIT
) ^ override
)
6312 bigdisp
.bitfield
.disp32
= 0;
6313 bigdisp
.bitfield
.disp16
= 1;
6317 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6320 exp
= &disp_expressions
[i
.disp_operands
];
6321 i
.op
[this_operand
].disps
= exp
;
6323 save_input_line_pointer
= input_line_pointer
;
6324 input_line_pointer
= disp_start
;
6325 END_STRING_AND_SAVE (disp_end
);
6327 #ifndef GCC_ASM_O_HACK
6328 #define GCC_ASM_O_HACK 0
6331 END_STRING_AND_SAVE (disp_end
+ 1);
6332 if (i
.types
[this_operand
].bitfield
.baseIndex
6333 && displacement_string_end
[-1] == '+')
6335 /* This hack is to avoid a warning when using the "o"
6336 constraint within gcc asm statements.
6339 #define _set_tssldt_desc(n,addr,limit,type) \
6340 __asm__ __volatile__ ( \
6342 "movw %w1,2+%0\n\t" \
6344 "movb %b1,4+%0\n\t" \
6345 "movb %4,5+%0\n\t" \
6346 "movb $0,6+%0\n\t" \
6347 "movb %h1,7+%0\n\t" \
6349 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6351 This works great except that the output assembler ends
6352 up looking a bit weird if it turns out that there is
6353 no offset. You end up producing code that looks like:
6366 So here we provide the missing zero. */
6368 *displacement_string_end
= '0';
6371 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6372 if (gotfree_input_line
)
6373 input_line_pointer
= gotfree_input_line
;
6375 exp_seg
= expression (exp
);
6378 if (*input_line_pointer
)
6379 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6381 RESTORE_END_STRING (disp_end
+ 1);
6383 input_line_pointer
= save_input_line_pointer
;
6384 if (gotfree_input_line
)
6386 free (gotfree_input_line
);
6388 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6389 exp
->X_op
= O_illegal
;
6392 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6394 RESTORE_END_STRING (disp_end
);
6400 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6401 i386_operand_type types
, const char *disp_start
)
6403 i386_operand_type bigdisp
;
6406 /* We do this to make sure that the section symbol is in
6407 the symbol table. We will ultimately change the relocation
6408 to be relative to the beginning of the section. */
6409 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6410 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6411 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6413 if (exp
->X_op
!= O_symbol
)
6416 if (S_IS_LOCAL (exp
->X_add_symbol
)
6417 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6418 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6419 exp
->X_op
= O_subtract
;
6420 exp
->X_op_symbol
= GOT_symbol
;
6421 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6422 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6423 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6424 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6426 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6429 else if (exp
->X_op
== O_absent
6430 || exp
->X_op
== O_illegal
6431 || exp
->X_op
== O_big
)
6434 as_bad (_("missing or invalid displacement expression `%s'"),
6439 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6440 else if (exp
->X_op
!= O_constant
6441 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6442 && exp_seg
!= absolute_section
6443 && exp_seg
!= text_section
6444 && exp_seg
!= data_section
6445 && exp_seg
!= bss_section
6446 && exp_seg
!= undefined_section
6447 && !bfd_is_com_section (exp_seg
))
6449 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6454 /* Check if this is a displacement only operand. */
6455 bigdisp
= i
.types
[this_operand
];
6456 bigdisp
.bitfield
.disp8
= 0;
6457 bigdisp
.bitfield
.disp16
= 0;
6458 bigdisp
.bitfield
.disp32
= 0;
6459 bigdisp
.bitfield
.disp32s
= 0;
6460 bigdisp
.bitfield
.disp64
= 0;
6461 if (operand_type_all_zero (&bigdisp
))
6462 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6468 /* Make sure the memory operand we've been dealt is valid.
6469 Return 1 on success, 0 on a failure. */
6472 i386_index_check (const char *operand_string
)
6475 const char *kind
= "base/index";
6476 #if INFER_ADDR_PREFIX
6482 if (current_templates
->start
->opcode_modifier
.isstring
6483 && !current_templates
->start
->opcode_modifier
.immext
6484 && (current_templates
->end
[-1].opcode_modifier
.isstring
6487 /* Memory operands of string insns are special in that they only allow
6488 a single register (rDI, rSI, or rBX) as their memory address. */
6489 unsigned int expected
;
6491 kind
= "string address";
6493 if (current_templates
->start
->opcode_modifier
.w
)
6495 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6497 if (!type
.bitfield
.baseindex
6498 || ((!i
.mem_operands
!= !intel_syntax
)
6499 && current_templates
->end
[-1].operand_types
[1]
6500 .bitfield
.baseindex
))
6501 type
= current_templates
->end
[-1].operand_types
[1];
6502 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6505 expected
= 3 /* rBX */;
6507 if (!i
.base_reg
|| i
.index_reg
6508 || operand_type_check (i
.types
[this_operand
], disp
))
6510 else if (!(flag_code
== CODE_64BIT
6511 ? i
.prefix
[ADDR_PREFIX
]
6512 ? i
.base_reg
->reg_type
.bitfield
.reg32
6513 : i
.base_reg
->reg_type
.bitfield
.reg64
6514 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6515 ? i
.base_reg
->reg_type
.bitfield
.reg32
6516 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6518 else if (i
.base_reg
->reg_num
!= expected
)
6525 for (j
= 0; j
< i386_regtab_size
; ++j
)
6526 if ((flag_code
== CODE_64BIT
6527 ? i
.prefix
[ADDR_PREFIX
]
6528 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6529 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6530 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6531 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6532 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6533 && i386_regtab
[j
].reg_num
== expected
)
6535 gas_assert (j
< i386_regtab_size
);
6536 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6538 intel_syntax
? '[' : '(',
6540 i386_regtab
[j
].reg_name
,
6541 intel_syntax
? ']' : ')');
6545 else if (flag_code
== CODE_64BIT
)
6548 && ((i
.prefix
[ADDR_PREFIX
] == 0
6549 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6550 || (i
.prefix
[ADDR_PREFIX
]
6551 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6553 || i
.base_reg
->reg_num
!=
6554 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6556 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6557 || (i
.prefix
[ADDR_PREFIX
] == 0
6558 && i
.index_reg
->reg_num
!= RegRiz
6559 && !i
.index_reg
->reg_type
.bitfield
.reg64
6561 || (i
.prefix
[ADDR_PREFIX
]
6562 && i
.index_reg
->reg_num
!= RegEiz
6563 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6568 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6572 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6573 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6575 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6576 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6578 && i
.base_reg
->reg_num
< 6
6579 && i
.index_reg
->reg_num
>= 6
6580 && i
.log2_scale_factor
== 0))))
6587 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6589 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6590 && i
.index_reg
->reg_num
!= RegEiz
)
6591 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6597 #if INFER_ADDR_PREFIX
6598 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6600 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6602 /* Change the size of any displacement too. At most one of
6603 Disp16 or Disp32 is set.
6604 FIXME. There doesn't seem to be any real need for separate
6605 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6606 Removing them would probably clean up the code quite a lot. */
6607 if (flag_code
!= CODE_64BIT
6608 && (i
.types
[this_operand
].bitfield
.disp16
6609 || i
.types
[this_operand
].bitfield
.disp32
))
6610 i
.types
[this_operand
]
6611 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6616 as_bad (_("`%s' is not a valid %s expression"),
6621 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6623 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6624 ? flag_code
== CODE_32BIT
6633 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6637 i386_att_operand (char *operand_string
)
6641 char *op_string
= operand_string
;
6643 if (is_space_char (*op_string
))
6646 /* We check for an absolute prefix (differentiating,
6647 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6648 if (*op_string
== ABSOLUTE_PREFIX
)
6651 if (is_space_char (*op_string
))
6653 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6656 /* Check if operand is a register. */
6657 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6659 i386_operand_type temp
;
6661 /* Check for a segment override by searching for ':' after a
6662 segment register. */
6664 if (is_space_char (*op_string
))
6666 if (*op_string
== ':'
6667 && (r
->reg_type
.bitfield
.sreg2
6668 || r
->reg_type
.bitfield
.sreg3
))
6673 i
.seg
[i
.mem_operands
] = &es
;
6676 i
.seg
[i
.mem_operands
] = &cs
;
6679 i
.seg
[i
.mem_operands
] = &ss
;
6682 i
.seg
[i
.mem_operands
] = &ds
;
6685 i
.seg
[i
.mem_operands
] = &fs
;
6688 i
.seg
[i
.mem_operands
] = &gs
;
6692 /* Skip the ':' and whitespace. */
6694 if (is_space_char (*op_string
))
6697 if (!is_digit_char (*op_string
)
6698 && !is_identifier_char (*op_string
)
6699 && *op_string
!= '('
6700 && *op_string
!= ABSOLUTE_PREFIX
)
6702 as_bad (_("bad memory operand `%s'"), op_string
);
6705 /* Handle case of %es:*foo. */
6706 if (*op_string
== ABSOLUTE_PREFIX
)
6709 if (is_space_char (*op_string
))
6711 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6713 goto do_memory_reference
;
6717 as_bad (_("junk `%s' after register"), op_string
);
6721 temp
.bitfield
.baseindex
= 0;
6722 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6724 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6725 i
.op
[this_operand
].regs
= r
;
6728 else if (*op_string
== REGISTER_PREFIX
)
6730 as_bad (_("bad register name `%s'"), op_string
);
6733 else if (*op_string
== IMMEDIATE_PREFIX
)
6736 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6738 as_bad (_("immediate operand illegal with absolute jump"));
6741 if (!i386_immediate (op_string
))
6744 else if (is_digit_char (*op_string
)
6745 || is_identifier_char (*op_string
)
6746 || *op_string
== '(')
6748 /* This is a memory reference of some sort. */
6751 /* Start and end of displacement string expression (if found). */
6752 char *displacement_string_start
;
6753 char *displacement_string_end
;
6755 do_memory_reference
:
6756 if ((i
.mem_operands
== 1
6757 && !current_templates
->start
->opcode_modifier
.isstring
)
6758 || i
.mem_operands
== 2)
6760 as_bad (_("too many memory references for `%s'"),
6761 current_templates
->start
->name
);
6765 /* Check for base index form. We detect the base index form by
6766 looking for an ')' at the end of the operand, searching
6767 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6769 base_string
= op_string
+ strlen (op_string
);
6772 if (is_space_char (*base_string
))
6775 /* If we only have a displacement, set-up for it to be parsed later. */
6776 displacement_string_start
= op_string
;
6777 displacement_string_end
= base_string
+ 1;
6779 if (*base_string
== ')')
6782 unsigned int parens_balanced
= 1;
6783 /* We've already checked that the number of left & right ()'s are
6784 equal, so this loop will not be infinite. */
6788 if (*base_string
== ')')
6790 if (*base_string
== '(')
6793 while (parens_balanced
);
6795 temp_string
= base_string
;
6797 /* Skip past '(' and whitespace. */
6799 if (is_space_char (*base_string
))
6802 if (*base_string
== ','
6803 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6806 displacement_string_end
= temp_string
;
6808 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6812 base_string
= end_op
;
6813 if (is_space_char (*base_string
))
6817 /* There may be an index reg or scale factor here. */
6818 if (*base_string
== ',')
6821 if (is_space_char (*base_string
))
6824 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
6827 base_string
= end_op
;
6828 if (is_space_char (*base_string
))
6830 if (*base_string
== ',')
6833 if (is_space_char (*base_string
))
6836 else if (*base_string
!= ')')
6838 as_bad (_("expecting `,' or `)' "
6839 "after index register in `%s'"),
6844 else if (*base_string
== REGISTER_PREFIX
)
6846 as_bad (_("bad register name `%s'"), base_string
);
6850 /* Check for scale factor. */
6851 if (*base_string
!= ')')
6853 char *end_scale
= i386_scale (base_string
);
6858 base_string
= end_scale
;
6859 if (is_space_char (*base_string
))
6861 if (*base_string
!= ')')
6863 as_bad (_("expecting `)' "
6864 "after scale factor in `%s'"),
6869 else if (!i
.index_reg
)
6871 as_bad (_("expecting index register or scale factor "
6872 "after `,'; got '%c'"),
6877 else if (*base_string
!= ')')
6879 as_bad (_("expecting `,' or `)' "
6880 "after base register in `%s'"),
6885 else if (*base_string
== REGISTER_PREFIX
)
6887 as_bad (_("bad register name `%s'"), base_string
);
6892 /* If there's an expression beginning the operand, parse it,
6893 assuming displacement_string_start and
6894 displacement_string_end are meaningful. */
6895 if (displacement_string_start
!= displacement_string_end
)
6897 if (!i386_displacement (displacement_string_start
,
6898 displacement_string_end
))
6902 /* Special case for (%dx) while doing input/output op. */
6904 && operand_type_equal (&i
.base_reg
->reg_type
,
6905 ®16_inoutportreg
)
6907 && i
.log2_scale_factor
== 0
6908 && i
.seg
[i
.mem_operands
] == 0
6909 && !operand_type_check (i
.types
[this_operand
], disp
))
6911 i
.types
[this_operand
] = inoutportreg
;
6915 if (i386_index_check (operand_string
) == 0)
6917 i
.types
[this_operand
].bitfield
.mem
= 1;
6922 /* It's not a memory operand; argh! */
6923 as_bad (_("invalid char %s beginning operand %d `%s'"),
6924 output_invalid (*op_string
),
6929 return 1; /* Normal return. */
6932 /* md_estimate_size_before_relax()
6934 Called just before relax() for rs_machine_dependent frags. The x86
6935 assembler uses these frags to handle variable size jump
6938 Any symbol that is now undefined will not become defined.
6939 Return the correct fr_subtype in the frag.
6940 Return the initial "guess for variable size of frag" to caller.
6941 The guess is actually the growth beyond the fixed part. Whatever
6942 we do to grow the fixed or variable part contributes to our
6946 md_estimate_size_before_relax (fragP
, segment
)
6950 /* We've already got fragP->fr_subtype right; all we have to do is
6951 check for un-relaxable symbols. On an ELF system, we can't relax
6952 an externally visible symbol, because it may be overridden by a
6954 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
6955 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
6957 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
6958 || S_IS_WEAK (fragP
->fr_symbol
)))
6960 #if defined (OBJ_COFF) && defined (TE_PE)
6961 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
6962 && S_IS_WEAK (fragP
->fr_symbol
))
6966 /* Symbol is undefined in this segment, or we need to keep a
6967 reloc so that weak symbols can be overridden. */
6968 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
6969 enum bfd_reloc_code_real reloc_type
;
6970 unsigned char *opcode
;
6973 if (fragP
->fr_var
!= NO_RELOC
)
6974 reloc_type
= fragP
->fr_var
;
6976 reloc_type
= BFD_RELOC_16_PCREL
;
6978 reloc_type
= BFD_RELOC_32_PCREL
;
6980 old_fr_fix
= fragP
->fr_fix
;
6981 opcode
= (unsigned char *) fragP
->fr_opcode
;
6983 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
6986 /* Make jmp (0xeb) a (d)word displacement jump. */
6988 fragP
->fr_fix
+= size
;
6989 fix_new (fragP
, old_fr_fix
, size
,
6991 fragP
->fr_offset
, 1,
6997 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
6999 /* Negate the condition, and branch past an
7000 unconditional jump. */
7003 /* Insert an unconditional jump. */
7005 /* We added two extra opcode bytes, and have a two byte
7007 fragP
->fr_fix
+= 2 + 2;
7008 fix_new (fragP
, old_fr_fix
+ 2, 2,
7010 fragP
->fr_offset
, 1,
7017 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7022 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7024 fragP
->fr_offset
, 1,
7026 fixP
->fx_signed
= 1;
7030 /* This changes the byte-displacement jump 0x7N
7031 to the (d)word-displacement jump 0x0f,0x8N. */
7032 opcode
[1] = opcode
[0] + 0x10;
7033 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7034 /* We've added an opcode byte. */
7035 fragP
->fr_fix
+= 1 + size
;
7036 fix_new (fragP
, old_fr_fix
+ 1, size
,
7038 fragP
->fr_offset
, 1,
7043 BAD_CASE (fragP
->fr_subtype
);
7047 return fragP
->fr_fix
- old_fr_fix
;
7050 /* Guess size depending on current relax state. Initially the relax
7051 state will correspond to a short jump and we return 1, because
7052 the variable part of the frag (the branch offset) is one byte
7053 long. However, we can relax a section more than once and in that
7054 case we must either set fr_subtype back to the unrelaxed state,
7055 or return the value for the appropriate branch. */
7056 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7059 /* Called after relax() is finished.
7061 In: Address of frag.
7062 fr_type == rs_machine_dependent.
7063 fr_subtype is what the address relaxed to.
7065 Out: Any fixSs and constants are set up.
7066 Caller will turn frag into a ".space 0". */
7069 md_convert_frag (abfd
, sec
, fragP
)
7070 bfd
*abfd ATTRIBUTE_UNUSED
;
7071 segT sec ATTRIBUTE_UNUSED
;
7074 unsigned char *opcode
;
7075 unsigned char *where_to_put_displacement
= NULL
;
7076 offsetT target_address
;
7077 offsetT opcode_address
;
7078 unsigned int extension
= 0;
7079 offsetT displacement_from_opcode_start
;
7081 opcode
= (unsigned char *) fragP
->fr_opcode
;
7083 /* Address we want to reach in file space. */
7084 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7086 /* Address opcode resides at in file space. */
7087 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7089 /* Displacement from opcode start to fill into instruction. */
7090 displacement_from_opcode_start
= target_address
- opcode_address
;
7092 if ((fragP
->fr_subtype
& BIG
) == 0)
7094 /* Don't have to change opcode. */
7095 extension
= 1; /* 1 opcode + 1 displacement */
7096 where_to_put_displacement
= &opcode
[1];
7100 if (no_cond_jump_promotion
7101 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7102 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7103 _("long jump required"));
7105 switch (fragP
->fr_subtype
)
7107 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7108 extension
= 4; /* 1 opcode + 4 displacement */
7110 where_to_put_displacement
= &opcode
[1];
7113 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7114 extension
= 2; /* 1 opcode + 2 displacement */
7116 where_to_put_displacement
= &opcode
[1];
7119 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7120 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7121 extension
= 5; /* 2 opcode + 4 displacement */
7122 opcode
[1] = opcode
[0] + 0x10;
7123 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7124 where_to_put_displacement
= &opcode
[2];
7127 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7128 extension
= 3; /* 2 opcode + 2 displacement */
7129 opcode
[1] = opcode
[0] + 0x10;
7130 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7131 where_to_put_displacement
= &opcode
[2];
7134 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7139 where_to_put_displacement
= &opcode
[3];
7143 BAD_CASE (fragP
->fr_subtype
);
7148 /* If size if less then four we are sure that the operand fits,
7149 but if it's 4, then it could be that the displacement is larger
7151 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7153 && ((addressT
) (displacement_from_opcode_start
- extension
7154 + ((addressT
) 1 << 31))
7155 > (((addressT
) 2 << 31) - 1)))
7157 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7158 _("jump target out of range"));
7159 /* Make us emit 0. */
7160 displacement_from_opcode_start
= extension
;
7162 /* Now put displacement after opcode. */
7163 md_number_to_chars ((char *) where_to_put_displacement
,
7164 (valueT
) (displacement_from_opcode_start
- extension
),
7165 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7166 fragP
->fr_fix
+= extension
;
7169 /* Apply a fixup (fixS) to segment data, once it has been determined
7170 by our caller that we have all the info we need to fix it up.
7172 On the 386, immediates, displacements, and data pointers are all in
7173 the same (little-endian) format, so we don't need to care about which
7177 md_apply_fix (fixP
, valP
, seg
)
7178 /* The fix we're to put in. */
7180 /* Pointer to the value of the bits. */
7182 /* Segment fix is from. */
7183 segT seg ATTRIBUTE_UNUSED
;
7185 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7186 valueT value
= *valP
;
7188 #if !defined (TE_Mach)
7191 switch (fixP
->fx_r_type
)
7197 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7200 case BFD_RELOC_X86_64_32S
:
7201 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7204 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7207 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7212 if (fixP
->fx_addsy
!= NULL
7213 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7214 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7215 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7216 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7217 && !use_rela_relocations
)
7219 /* This is a hack. There should be a better way to handle this.
7220 This covers for the fact that bfd_install_relocation will
7221 subtract the current location (for partial_inplace, PC relative
7222 relocations); see more below. */
7226 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7229 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7231 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7234 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7237 || (symbol_section_p (fixP
->fx_addsy
)
7238 && sym_seg
!= absolute_section
))
7239 && !TC_FORCE_RELOCATION (fixP
))
7241 /* Yes, we add the values in twice. This is because
7242 bfd_install_relocation subtracts them out again. I think
7243 bfd_install_relocation is broken, but I don't dare change
7245 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7249 #if defined (OBJ_COFF) && defined (TE_PE)
7250 /* For some reason, the PE format does not store a
7251 section address offset for a PC relative symbol. */
7252 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7253 || S_IS_WEAK (fixP
->fx_addsy
))
7254 value
+= md_pcrel_from (fixP
);
7257 #if defined (OBJ_COFF) && defined (TE_PE)
7258 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7260 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7264 /* Fix a few things - the dynamic linker expects certain values here,
7265 and we must not disappoint it. */
7266 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7267 if (IS_ELF
&& fixP
->fx_addsy
)
7268 switch (fixP
->fx_r_type
)
7270 case BFD_RELOC_386_PLT32
:
7271 case BFD_RELOC_X86_64_PLT32
:
7272 /* Make the jump instruction point to the address of the operand. At
7273 runtime we merely add the offset to the actual PLT entry. */
7277 case BFD_RELOC_386_TLS_GD
:
7278 case BFD_RELOC_386_TLS_LDM
:
7279 case BFD_RELOC_386_TLS_IE_32
:
7280 case BFD_RELOC_386_TLS_IE
:
7281 case BFD_RELOC_386_TLS_GOTIE
:
7282 case BFD_RELOC_386_TLS_GOTDESC
:
7283 case BFD_RELOC_X86_64_TLSGD
:
7284 case BFD_RELOC_X86_64_TLSLD
:
7285 case BFD_RELOC_X86_64_GOTTPOFF
:
7286 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7287 value
= 0; /* Fully resolved at runtime. No addend. */
7289 case BFD_RELOC_386_TLS_LE
:
7290 case BFD_RELOC_386_TLS_LDO_32
:
7291 case BFD_RELOC_386_TLS_LE_32
:
7292 case BFD_RELOC_X86_64_DTPOFF32
:
7293 case BFD_RELOC_X86_64_DTPOFF64
:
7294 case BFD_RELOC_X86_64_TPOFF32
:
7295 case BFD_RELOC_X86_64_TPOFF64
:
7296 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7299 case BFD_RELOC_386_TLS_DESC_CALL
:
7300 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7301 value
= 0; /* Fully resolved at runtime. No addend. */
7302 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7306 case BFD_RELOC_386_GOT32
:
7307 case BFD_RELOC_X86_64_GOT32
:
7308 value
= 0; /* Fully resolved at runtime. No addend. */
7311 case BFD_RELOC_VTABLE_INHERIT
:
7312 case BFD_RELOC_VTABLE_ENTRY
:
7319 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7321 #endif /* !defined (TE_Mach) */
7323 /* Are we finished with this relocation now? */
7324 if (fixP
->fx_addsy
== NULL
)
7326 #if defined (OBJ_COFF) && defined (TE_PE)
7327 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7330 /* Remember value for tc_gen_reloc. */
7331 fixP
->fx_addnumber
= value
;
7332 /* Clear out the frag for now. */
7336 else if (use_rela_relocations
)
7338 fixP
->fx_no_overflow
= 1;
7339 /* Remember value for tc_gen_reloc. */
7340 fixP
->fx_addnumber
= value
;
7344 md_number_to_chars (p
, value
, fixP
->fx_size
);
7348 md_atof (int type
, char *litP
, int *sizeP
)
7350 /* This outputs the LITTLENUMs in REVERSE order;
7351 in accord with the bigendian 386. */
7352 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7355 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7358 output_invalid (int c
)
7361 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7364 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7365 "(0x%x)", (unsigned char) c
);
7366 return output_invalid_buf
;
7369 /* REG_STRING starts *before* REGISTER_PREFIX. */
7371 static const reg_entry
*
7372 parse_real_register (char *reg_string
, char **end_op
)
7374 char *s
= reg_string
;
7376 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7379 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7380 if (*s
== REGISTER_PREFIX
)
7383 if (is_space_char (*s
))
7387 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7389 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7390 return (const reg_entry
*) NULL
;
7394 /* For naked regs, make sure that we are not dealing with an identifier.
7395 This prevents confusing an identifier like `eax_var' with register
7397 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7398 return (const reg_entry
*) NULL
;
7402 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7404 /* Handle floating point regs, allowing spaces in the (i) part. */
7405 if (r
== i386_regtab
/* %st is first entry of table */)
7407 if (is_space_char (*s
))
7412 if (is_space_char (*s
))
7414 if (*s
>= '0' && *s
<= '7')
7418 if (is_space_char (*s
))
7423 r
= hash_find (reg_hash
, "st(0)");
7428 /* We have "%st(" then garbage. */
7429 return (const reg_entry
*) NULL
;
7433 if (r
== NULL
|| allow_pseudo_reg
)
7436 if (operand_type_all_zero (&r
->reg_type
))
7437 return (const reg_entry
*) NULL
;
7439 if ((r
->reg_type
.bitfield
.reg32
7440 || r
->reg_type
.bitfield
.sreg3
7441 || r
->reg_type
.bitfield
.control
7442 || r
->reg_type
.bitfield
.debug
7443 || r
->reg_type
.bitfield
.test
)
7444 && !cpu_arch_flags
.bitfield
.cpui386
)
7445 return (const reg_entry
*) NULL
;
7447 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7448 return (const reg_entry
*) NULL
;
7450 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7451 return (const reg_entry
*) NULL
;
7453 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7454 return (const reg_entry
*) NULL
;
7456 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7457 if (!allow_index_reg
7458 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7459 return (const reg_entry
*) NULL
;
7461 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7462 || r
->reg_type
.bitfield
.reg64
)
7463 && (!cpu_arch_flags
.bitfield
.cpulm
7464 || !operand_type_equal (&r
->reg_type
, &control
))
7465 && flag_code
!= CODE_64BIT
)
7466 return (const reg_entry
*) NULL
;
7468 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7469 return (const reg_entry
*) NULL
;
7474 /* REG_STRING starts *before* REGISTER_PREFIX. */
7476 static const reg_entry
*
7477 parse_register (char *reg_string
, char **end_op
)
7481 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7482 r
= parse_real_register (reg_string
, end_op
);
7487 char *save
= input_line_pointer
;
7491 input_line_pointer
= reg_string
;
7492 c
= get_symbol_end ();
7493 symbolP
= symbol_find (reg_string
);
7494 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7496 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7498 know (e
->X_op
== O_register
);
7499 know (e
->X_add_number
>= 0
7500 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7501 r
= i386_regtab
+ e
->X_add_number
;
7502 *end_op
= input_line_pointer
;
7504 *input_line_pointer
= c
;
7505 input_line_pointer
= save
;
7511 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7514 char *end
= input_line_pointer
;
7517 r
= parse_register (name
, &input_line_pointer
);
7518 if (r
&& end
<= input_line_pointer
)
7520 *nextcharP
= *input_line_pointer
;
7521 *input_line_pointer
= 0;
7522 e
->X_op
= O_register
;
7523 e
->X_add_number
= r
- i386_regtab
;
7526 input_line_pointer
= end
;
7528 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7532 md_operand (expressionS
*e
)
7537 switch (*input_line_pointer
)
7539 case REGISTER_PREFIX
:
7540 r
= parse_real_register (input_line_pointer
, &end
);
7543 e
->X_op
= O_register
;
7544 e
->X_add_number
= r
- i386_regtab
;
7545 input_line_pointer
= end
;
7550 gas_assert (intel_syntax
);
7551 end
= input_line_pointer
++;
7553 if (*input_line_pointer
== ']')
7555 ++input_line_pointer
;
7556 e
->X_op_symbol
= make_expr_symbol (e
);
7557 e
->X_add_symbol
= NULL
;
7558 e
->X_add_number
= 0;
7564 input_line_pointer
= end
;
7571 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7572 const char *md_shortopts
= "kVQ:sqn";
7574 const char *md_shortopts
= "qn";
7577 #define OPTION_32 (OPTION_MD_BASE + 0)
7578 #define OPTION_64 (OPTION_MD_BASE + 1)
7579 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7580 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7581 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7582 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7583 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7584 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7585 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7586 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7587 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7588 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7590 struct option md_longopts
[] =
7592 {"32", no_argument
, NULL
, OPTION_32
},
7593 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7594 || defined (TE_PE) || defined (TE_PEP))
7595 {"64", no_argument
, NULL
, OPTION_64
},
7597 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7598 {"march", required_argument
, NULL
, OPTION_MARCH
},
7599 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7600 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7601 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7602 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7603 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7604 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7605 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7606 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7607 {NULL
, no_argument
, NULL
, 0}
7609 size_t md_longopts_size
= sizeof (md_longopts
);
7612 md_parse_option (int c
, char *arg
)
7620 optimize_align_code
= 0;
7627 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7628 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7629 should be emitted or not. FIXME: Not implemented. */
7633 /* -V: SVR4 argument to print version ID. */
7635 print_version_id ();
7638 /* -k: Ignore for FreeBSD compatibility. */
7643 /* -s: On i386 Solaris, this tells the native assembler to use
7644 .stab instead of .stab.excl. We always use .stab anyhow. */
7647 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7648 || defined (TE_PE) || defined (TE_PEP))
7651 const char **list
, **l
;
7653 list
= bfd_target_list ();
7654 for (l
= list
; *l
!= NULL
; l
++)
7655 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7656 || strcmp (*l
, "coff-x86-64") == 0
7657 || strcmp (*l
, "pe-x86-64") == 0
7658 || strcmp (*l
, "pei-x86-64") == 0)
7660 default_arch
= "x86_64";
7664 as_fatal (_("No compiled in support for x86_64"));
7671 default_arch
= "i386";
7675 #ifdef SVR4_COMMENT_CHARS
7680 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7682 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7686 i386_comment_chars
= n
;
7692 arch
= xstrdup (arg
);
7696 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7697 next
= strchr (arch
, '+');
7700 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7702 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7705 cpu_arch_name
= cpu_arch
[i
].name
;
7706 cpu_sub_arch_name
= NULL
;
7707 cpu_arch_flags
= cpu_arch
[i
].flags
;
7708 cpu_arch_isa
= cpu_arch
[i
].type
;
7709 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7710 if (!cpu_arch_tune_set
)
7712 cpu_arch_tune
= cpu_arch_isa
;
7713 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7717 else if (*cpu_arch
[i
].name
== '.'
7718 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7720 /* ISA entension. */
7721 i386_cpu_flags flags
;
7722 flags
= cpu_flags_or (cpu_arch_flags
,
7724 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7726 if (cpu_sub_arch_name
)
7728 char *name
= cpu_sub_arch_name
;
7729 cpu_sub_arch_name
= concat (name
,
7731 (const char *) NULL
);
7735 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7736 cpu_arch_flags
= flags
;
7742 if (i
>= ARRAY_SIZE (cpu_arch
))
7743 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7747 while (next
!= NULL
);
7752 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7753 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7755 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7757 cpu_arch_tune_set
= 1;
7758 cpu_arch_tune
= cpu_arch
[i
].type
;
7759 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7763 if (i
>= ARRAY_SIZE (cpu_arch
))
7764 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7767 case OPTION_MMNEMONIC
:
7768 if (strcasecmp (arg
, "att") == 0)
7770 else if (strcasecmp (arg
, "intel") == 0)
7773 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7776 case OPTION_MSYNTAX
:
7777 if (strcasecmp (arg
, "att") == 0)
7779 else if (strcasecmp (arg
, "intel") == 0)
7782 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7785 case OPTION_MINDEX_REG
:
7786 allow_index_reg
= 1;
7789 case OPTION_MNAKED_REG
:
7790 allow_naked_reg
= 1;
7793 case OPTION_MOLD_GCC
:
7797 case OPTION_MSSE2AVX
:
7801 case OPTION_MSSE_CHECK
:
7802 if (strcasecmp (arg
, "error") == 0)
7803 sse_check
= sse_check_error
;
7804 else if (strcasecmp (arg
, "warning") == 0)
7805 sse_check
= sse_check_warning
;
7806 else if (strcasecmp (arg
, "none") == 0)
7807 sse_check
= sse_check_none
;
7809 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
7819 md_show_usage (stream
)
7822 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7823 fprintf (stream
, _("\
7825 -V print assembler version number\n\
7828 fprintf (stream
, _("\
7829 -n Do not optimize code alignment\n\
7830 -q quieten some warnings\n"));
7831 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7832 fprintf (stream
, _("\
7835 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7836 || defined (TE_PE) || defined (TE_PEP))
7837 fprintf (stream
, _("\
7838 --32/--64 generate 32bit/64bit code\n"));
7840 #ifdef SVR4_COMMENT_CHARS
7841 fprintf (stream
, _("\
7842 --divide do not treat `/' as a comment character\n"));
7844 fprintf (stream
, _("\
7845 --divide ignored\n"));
7847 fprintf (stream
, _("\
7848 -march=CPU[,+EXTENSION...]\n\
7849 generate code for CPU and EXTENSION, CPU is one of:\n\
7850 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7851 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7852 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7853 generic32, generic64\n\
7854 EXTENSION is combination of:\n\
7855 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
7856 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
7857 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
7858 svme, abm, padlock\n"));
7859 fprintf (stream
, _("\
7860 -mtune=CPU optimize for CPU, CPU is one of:\n\
7861 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
7862 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
7863 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
7864 generic32, generic64\n"));
7865 fprintf (stream
, _("\
7866 -msse2avx encode SSE instructions with VEX prefix\n"));
7867 fprintf (stream
, _("\
7868 -msse-check=[none|error|warning]\n\
7869 check SSE instructions\n"));
7870 fprintf (stream
, _("\
7871 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
7872 fprintf (stream
, _("\
7873 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
7874 fprintf (stream
, _("\
7875 -mindex-reg support pseudo index registers\n"));
7876 fprintf (stream
, _("\
7877 -mnaked-reg don't require `%%' prefix for registers\n"));
7878 fprintf (stream
, _("\
7879 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
7882 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
7883 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7884 || defined (TE_PE) || defined (TE_PEP))
7886 /* Pick the target format to use. */
7889 i386_target_format (void)
7891 if (!strcmp (default_arch
, "x86_64"))
7893 set_code_flag (CODE_64BIT
);
7894 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
7896 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7897 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7898 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7899 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
7900 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
7901 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
7902 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
7903 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
7904 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
7905 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
7907 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
7909 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7910 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7911 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7912 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
7913 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
7914 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
7915 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
7916 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
7917 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
7918 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
7921 else if (!strcmp (default_arch
, "i386"))
7923 set_code_flag (CODE_32BIT
);
7924 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
7926 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
7927 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
7928 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
7930 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
7932 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
7933 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
7934 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
7938 as_fatal (_("Unknown architecture"));
7939 switch (OUTPUT_FLAVOR
)
7941 #if defined (TE_PE) || defined (TE_PEP)
7942 case bfd_target_coff_flavour
:
7943 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
7945 #ifdef OBJ_MAYBE_AOUT
7946 case bfd_target_aout_flavour
:
7947 return AOUT_TARGET_FORMAT
;
7949 #ifdef OBJ_MAYBE_COFF
7950 case bfd_target_coff_flavour
:
7953 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
7954 case bfd_target_elf_flavour
:
7956 if (flag_code
== CODE_64BIT
)
7959 use_rela_relocations
= 1;
7961 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
7970 #endif /* OBJ_MAYBE_ more than one */
7972 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
7974 i386_elf_emit_arch_note (void)
7976 if (IS_ELF
&& cpu_arch_name
!= NULL
)
7979 asection
*seg
= now_seg
;
7980 subsegT subseg
= now_subseg
;
7981 Elf_Internal_Note i_note
;
7982 Elf_External_Note e_note
;
7983 asection
*note_secp
;
7986 /* Create the .note section. */
7987 note_secp
= subseg_new (".note", 0);
7988 bfd_set_section_flags (stdoutput
,
7990 SEC_HAS_CONTENTS
| SEC_READONLY
);
7992 /* Process the arch string. */
7993 len
= strlen (cpu_arch_name
);
7995 i_note
.namesz
= len
+ 1;
7997 i_note
.type
= NT_ARCH
;
7998 p
= frag_more (sizeof (e_note
.namesz
));
7999 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8000 p
= frag_more (sizeof (e_note
.descsz
));
8001 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8002 p
= frag_more (sizeof (e_note
.type
));
8003 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8004 p
= frag_more (len
+ 1);
8005 strcpy (p
, cpu_arch_name
);
8007 frag_align (2, 0, 0);
8009 subseg_set (seg
, subseg
);
8015 md_undefined_symbol (name
)
8018 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8019 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8020 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8021 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8025 if (symbol_find (name
))
8026 as_bad (_("GOT already in symbol table"));
8027 GOT_symbol
= symbol_new (name
, undefined_section
,
8028 (valueT
) 0, &zero_address_frag
);
8035 /* Round up a section size to the appropriate boundary. */
8038 md_section_align (segment
, size
)
8039 segT segment ATTRIBUTE_UNUSED
;
8042 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8043 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8045 /* For a.out, force the section size to be aligned. If we don't do
8046 this, BFD will align it for us, but it will not write out the
8047 final bytes of the section. This may be a bug in BFD, but it is
8048 easier to fix it here since that is how the other a.out targets
8052 align
= bfd_get_section_alignment (stdoutput
, segment
);
8053 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8060 /* On the i386, PC-relative offsets are relative to the start of the
8061 next instruction. That is, the address of the offset, plus its
8062 size, since the offset is always the last part of the insn. */
8065 md_pcrel_from (fixS
*fixP
)
8067 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8073 s_bss (int ignore ATTRIBUTE_UNUSED
)
8077 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8079 obj_elf_section_change_hook ();
8081 temp
= get_absolute_expression ();
8082 subseg_set (bss_section
, (subsegT
) temp
);
8083 demand_empty_rest_of_line ();
8089 i386_validate_fix (fixS
*fixp
)
8091 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8093 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8097 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8102 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8104 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8111 tc_gen_reloc (section
, fixp
)
8112 asection
*section ATTRIBUTE_UNUSED
;
8116 bfd_reloc_code_real_type code
;
8118 switch (fixp
->fx_r_type
)
8120 case BFD_RELOC_X86_64_PLT32
:
8121 case BFD_RELOC_X86_64_GOT32
:
8122 case BFD_RELOC_X86_64_GOTPCREL
:
8123 case BFD_RELOC_386_PLT32
:
8124 case BFD_RELOC_386_GOT32
:
8125 case BFD_RELOC_386_GOTOFF
:
8126 case BFD_RELOC_386_GOTPC
:
8127 case BFD_RELOC_386_TLS_GD
:
8128 case BFD_RELOC_386_TLS_LDM
:
8129 case BFD_RELOC_386_TLS_LDO_32
:
8130 case BFD_RELOC_386_TLS_IE_32
:
8131 case BFD_RELOC_386_TLS_IE
:
8132 case BFD_RELOC_386_TLS_GOTIE
:
8133 case BFD_RELOC_386_TLS_LE_32
:
8134 case BFD_RELOC_386_TLS_LE
:
8135 case BFD_RELOC_386_TLS_GOTDESC
:
8136 case BFD_RELOC_386_TLS_DESC_CALL
:
8137 case BFD_RELOC_X86_64_TLSGD
:
8138 case BFD_RELOC_X86_64_TLSLD
:
8139 case BFD_RELOC_X86_64_DTPOFF32
:
8140 case BFD_RELOC_X86_64_DTPOFF64
:
8141 case BFD_RELOC_X86_64_GOTTPOFF
:
8142 case BFD_RELOC_X86_64_TPOFF32
:
8143 case BFD_RELOC_X86_64_TPOFF64
:
8144 case BFD_RELOC_X86_64_GOTOFF64
:
8145 case BFD_RELOC_X86_64_GOTPC32
:
8146 case BFD_RELOC_X86_64_GOT64
:
8147 case BFD_RELOC_X86_64_GOTPCREL64
:
8148 case BFD_RELOC_X86_64_GOTPC64
:
8149 case BFD_RELOC_X86_64_GOTPLT64
:
8150 case BFD_RELOC_X86_64_PLTOFF64
:
8151 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8152 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8154 case BFD_RELOC_VTABLE_ENTRY
:
8155 case BFD_RELOC_VTABLE_INHERIT
:
8157 case BFD_RELOC_32_SECREL
:
8159 code
= fixp
->fx_r_type
;
8161 case BFD_RELOC_X86_64_32S
:
8162 if (!fixp
->fx_pcrel
)
8164 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8165 code
= fixp
->fx_r_type
;
8171 switch (fixp
->fx_size
)
8174 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8175 _("can not do %d byte pc-relative relocation"),
8177 code
= BFD_RELOC_32_PCREL
;
8179 case 1: code
= BFD_RELOC_8_PCREL
; break;
8180 case 2: code
= BFD_RELOC_16_PCREL
; break;
8181 case 4: code
= BFD_RELOC_32_PCREL
; break;
8183 case 8: code
= BFD_RELOC_64_PCREL
; break;
8189 switch (fixp
->fx_size
)
8192 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8193 _("can not do %d byte relocation"),
8195 code
= BFD_RELOC_32
;
8197 case 1: code
= BFD_RELOC_8
; break;
8198 case 2: code
= BFD_RELOC_16
; break;
8199 case 4: code
= BFD_RELOC_32
; break;
8201 case 8: code
= BFD_RELOC_64
; break;
8208 if ((code
== BFD_RELOC_32
8209 || code
== BFD_RELOC_32_PCREL
8210 || code
== BFD_RELOC_X86_64_32S
)
8212 && fixp
->fx_addsy
== GOT_symbol
)
8215 code
= BFD_RELOC_386_GOTPC
;
8217 code
= BFD_RELOC_X86_64_GOTPC32
;
8219 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8221 && fixp
->fx_addsy
== GOT_symbol
)
8223 code
= BFD_RELOC_X86_64_GOTPC64
;
8226 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8227 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8228 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8230 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8232 if (!use_rela_relocations
)
8234 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8235 vtable entry to be used in the relocation's section offset. */
8236 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8237 rel
->address
= fixp
->fx_offset
;
8238 #if defined (OBJ_COFF) && defined (TE_PE)
8239 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8240 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8245 /* Use the rela in 64bit mode. */
8248 if (!fixp
->fx_pcrel
)
8249 rel
->addend
= fixp
->fx_offset
;
8253 case BFD_RELOC_X86_64_PLT32
:
8254 case BFD_RELOC_X86_64_GOT32
:
8255 case BFD_RELOC_X86_64_GOTPCREL
:
8256 case BFD_RELOC_X86_64_TLSGD
:
8257 case BFD_RELOC_X86_64_TLSLD
:
8258 case BFD_RELOC_X86_64_GOTTPOFF
:
8259 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8260 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8261 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8264 rel
->addend
= (section
->vma
8266 + fixp
->fx_addnumber
8267 + md_pcrel_from (fixp
));
8272 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8273 if (rel
->howto
== NULL
)
8275 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8276 _("cannot represent relocation type %s"),
8277 bfd_get_reloc_code_name (code
));
8278 /* Set howto to a garbage value so that we can keep going. */
8279 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8280 gas_assert (rel
->howto
!= NULL
);
8286 #include "tc-i386-intel.c"
8289 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8291 int saved_naked_reg
;
8292 char saved_register_dot
;
8294 saved_naked_reg
= allow_naked_reg
;
8295 allow_naked_reg
= 1;
8296 saved_register_dot
= register_chars
['.'];
8297 register_chars
['.'] = '.';
8298 allow_pseudo_reg
= 1;
8299 expression_and_evaluate (exp
);
8300 allow_pseudo_reg
= 0;
8301 register_chars
['.'] = saved_register_dot
;
8302 allow_naked_reg
= saved_naked_reg
;
8304 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8306 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8308 exp
->X_op
= O_constant
;
8309 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8310 .dw2_regnum
[flag_code
>> 1];
8313 exp
->X_op
= O_illegal
;
8318 tc_x86_frame_initial_instructions (void)
8320 static unsigned int sp_regno
[2];
8322 if (!sp_regno
[flag_code
>> 1])
8324 char *saved_input
= input_line_pointer
;
8325 char sp
[][4] = {"esp", "rsp"};
8328 input_line_pointer
= sp
[flag_code
>> 1];
8329 tc_x86_parse_to_dw2regnum (&exp
);
8330 gas_assert (exp
.X_op
== O_constant
);
8331 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8332 input_line_pointer
= saved_input
;
8335 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8336 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8340 i386_elf_section_type (const char *str
, size_t len
)
8342 if (flag_code
== CODE_64BIT
8343 && len
== sizeof ("unwind") - 1
8344 && strncmp (str
, "unwind", 6) == 0)
8345 return SHT_X86_64_UNWIND
;
8352 i386_solaris_fix_up_eh_frame (segT sec
)
8354 if (flag_code
== CODE_64BIT
)
8355 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8361 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8365 expr
.X_op
= O_secrel
;
8366 expr
.X_add_symbol
= symbol
;
8367 expr
.X_add_number
= 0;
8368 emit_expr (&expr
, size
);
8372 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8373 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8376 x86_64_section_letter (int letter
, char **ptr_msg
)
8378 if (flag_code
== CODE_64BIT
)
8381 return SHF_X86_64_LARGE
;
8383 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8386 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8391 x86_64_section_word (char *str
, size_t len
)
8393 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8394 return SHF_X86_64_LARGE
;
8400 handle_large_common (int small ATTRIBUTE_UNUSED
)
8402 if (flag_code
!= CODE_64BIT
)
8404 s_comm_internal (0, elf_common_parse
);
8405 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8409 static segT lbss_section
;
8410 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8411 asection
*saved_bss_section
= bss_section
;
8413 if (lbss_section
== NULL
)
8415 flagword applicable
;
8417 subsegT subseg
= now_subseg
;
8419 /* The .lbss section is for local .largecomm symbols. */
8420 lbss_section
= subseg_new (".lbss", 0);
8421 applicable
= bfd_applicable_section_flags (stdoutput
);
8422 bfd_set_section_flags (stdoutput
, lbss_section
,
8423 applicable
& SEC_ALLOC
);
8424 seg_info (lbss_section
)->bss
= 1;
8426 subseg_set (seg
, subseg
);
8429 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8430 bss_section
= lbss_section
;
8432 s_comm_internal (0, elf_common_parse
);
8434 elf_com_section_ptr
= saved_com_section_ptr
;
8435 bss_section
= saved_bss_section
;
8438 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */