1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const template *start
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* The SSE5 instructions have a two bit instruction modifier (OC) that
118 is stored in two separate bytes in the instruction. Pick apart OC
119 into the 2 separate bits for instruction. */
120 #define DREX_OC0(x) (((x) & 1) != 0)
121 #define DREX_OC1(x) (((x) & 2) != 0)
123 #define DREX_OC0_MASK (1 << 3) /* set OC0 in byte 4 */
124 #define DREX_OC1_MASK (1 << 2) /* set OC1 in byte 3 */
127 #define DREX_XMEM_X1_X2_X2 0 /* 4 op insn, dest = src3, src1 = reg/mem */
128 #define DREX_X1_XMEM_X2_X2 1 /* 4 op insn, dest = src3, src2 = reg/mem */
129 #define DREX_X1_XMEM_X2_X1 2 /* 4 op insn, dest = src1, src2 = reg/mem */
130 #define DREX_X1_X2_XMEM_X1 3 /* 4 op insn, dest = src1, src3 = reg/mem */
132 #define DREX_XMEM_X1_X2 0 /* 3 op insn, src1 = reg/mem */
133 #define DREX_X1_XMEM_X2 1 /* 3 op insn, src1 = reg/mem */
135 /* Information needed to create the DREX byte in SSE5 instructions. */
138 unsigned int reg
; /* register */
139 unsigned int rex
; /* REX flags */
140 unsigned int modrm_reg
; /* which arg goes in the modrm.reg field */
141 unsigned int modrm_regmem
; /* which arg goes in the modrm.regmem field */
144 /* 386 opcode byte to code indirect addressing. */
153 /* x86 arch names, types and features */
156 const char *name
; /* arch name */
157 enum processor_type type
; /* arch type */
158 i386_cpu_flags flags
; /* cpu feature flags */
162 static void set_code_flag (int);
163 static void set_16bit_gcc_code_flag (int);
164 static void set_intel_syntax (int);
165 static void set_intel_mnemonic (int);
166 static void set_allow_index_reg (int);
167 static void set_sse_check (int);
168 static void set_cpu_arch (int);
170 static void pe_directive_secrel (int);
172 static void signed_cons (int);
173 static char *output_invalid (int c
);
174 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
176 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
178 static int i386_att_operand (char *);
179 static int i386_intel_operand (char *, int);
180 static int i386_intel_simplify (expressionS
*);
181 static int i386_intel_parse_name (const char *, expressionS
*);
182 static const reg_entry
*parse_register (char *, char **);
183 static char *parse_insn (char *, char *);
184 static char *parse_operands (char *, const char *);
185 static void swap_operands (void);
186 static void swap_2_operands (int, int);
187 static void optimize_imm (void);
188 static void optimize_disp (void);
189 static const template *match_template (void);
190 static int check_string (void);
191 static int process_suffix (void);
192 static int check_byte_reg (void);
193 static int check_long_reg (void);
194 static int check_qword_reg (void);
195 static int check_word_reg (void);
196 static int finalize_imm (void);
197 static void process_drex (void);
198 static int process_operands (void);
199 static const seg_entry
*build_modrm_byte (void);
200 static void output_insn (void);
201 static void output_imm (fragS
*, offsetT
);
202 static void output_disp (fragS
*, offsetT
);
204 static void s_bss (int);
206 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
207 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
210 static const char *default_arch
= DEFAULT_ARCH
;
215 /* VEX prefix is either 2 byte or 3 byte. */
216 unsigned char bytes
[3];
218 /* Destination or source register specifier. */
219 const reg_entry
*register_specifier
;
222 /* 'md_assemble ()' gathers together information and puts it into a
229 const reg_entry
*regs
;
234 /* TM holds the template for the insn were currently assembling. */
237 /* SUFFIX holds the instruction size suffix for byte, word, dword
238 or qword, if given. */
241 /* OPERANDS gives the number of given operands. */
242 unsigned int operands
;
244 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
245 of given register, displacement, memory operands and immediate
247 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
249 /* TYPES [i] is the type (see above #defines) which tells us how to
250 use OP[i] for the corresponding operand. */
251 i386_operand_type types
[MAX_OPERANDS
];
253 /* Displacement expression, immediate expression, or register for each
255 union i386_op op
[MAX_OPERANDS
];
257 /* Flags for operands. */
258 unsigned int flags
[MAX_OPERANDS
];
259 #define Operand_PCrel 1
261 /* Relocation type for operand */
262 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
264 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
265 the base index byte below. */
266 const reg_entry
*base_reg
;
267 const reg_entry
*index_reg
;
268 unsigned int log2_scale_factor
;
270 /* SEG gives the seg_entries of this insn. They are zero unless
271 explicit segment overrides are given. */
272 const seg_entry
*seg
[2];
274 /* PREFIX holds all the given prefix opcodes (usually null).
275 PREFIXES is the number of prefix opcodes. */
276 unsigned int prefixes
;
277 unsigned char prefix
[MAX_PREFIXES
];
279 /* RM and SIB are the modrm byte and the sib byte where the
280 addressing modes of this insn are encoded. DREX is the byte
281 added by the SSE5 instructions. */
289 /* Swap operand in encoding. */
290 unsigned int swap_operand
: 1;
293 typedef struct _i386_insn i386_insn
;
295 /* List of chars besides those in app.c:symbol_chars that can start an
296 operand. Used to prevent the scrubber eating vital white-space. */
297 const char extra_symbol_chars
[] = "*%-(["
306 #if (defined (TE_I386AIX) \
307 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
308 && !defined (TE_GNU) \
309 && !defined (TE_LINUX) \
310 && !defined (TE_NETWARE) \
311 && !defined (TE_FreeBSD) \
312 && !defined (TE_NetBSD)))
313 /* This array holds the chars that always start a comment. If the
314 pre-processor is disabled, these aren't very useful. The option
315 --divide will remove '/' from this list. */
316 const char *i386_comment_chars
= "#/";
317 #define SVR4_COMMENT_CHARS 1
318 #define PREFIX_SEPARATOR '\\'
321 const char *i386_comment_chars
= "#";
322 #define PREFIX_SEPARATOR '/'
325 /* This array holds the chars that only start a comment at the beginning of
326 a line. If the line seems to have the form '# 123 filename'
327 .line and .file directives will appear in the pre-processed output.
328 Note that input_file.c hand checks for '#' at the beginning of the
329 first line of the input file. This is because the compiler outputs
330 #NO_APP at the beginning of its output.
331 Also note that comments started like this one will always work if
332 '/' isn't otherwise defined. */
333 const char line_comment_chars
[] = "#/";
335 const char line_separator_chars
[] = ";";
337 /* Chars that can be used to separate mant from exp in floating point
339 const char EXP_CHARS
[] = "eE";
341 /* Chars that mean this number is a floating point constant
344 const char FLT_CHARS
[] = "fFdDxX";
346 /* Tables for lexical analysis. */
347 static char mnemonic_chars
[256];
348 static char register_chars
[256];
349 static char operand_chars
[256];
350 static char identifier_chars
[256];
351 static char digit_chars
[256];
353 /* Lexical macros. */
354 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
355 #define is_operand_char(x) (operand_chars[(unsigned char) x])
356 #define is_register_char(x) (register_chars[(unsigned char) x])
357 #define is_space_char(x) ((x) == ' ')
358 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
359 #define is_digit_char(x) (digit_chars[(unsigned char) x])
361 /* All non-digit non-letter characters that may occur in an operand. */
362 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
364 /* md_assemble() always leaves the strings it's passed unaltered. To
365 effect this we maintain a stack of saved characters that we've smashed
366 with '\0's (indicating end of strings for various sub-fields of the
367 assembler instruction). */
368 static char save_stack
[32];
369 static char *save_stack_p
;
370 #define END_STRING_AND_SAVE(s) \
371 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
372 #define RESTORE_END_STRING(s) \
373 do { *(s) = *--save_stack_p; } while (0)
375 /* The instruction we're assembling. */
378 /* Possible templates for current insn. */
379 static const templates
*current_templates
;
381 /* Per instruction expressionS buffers: max displacements & immediates. */
382 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
383 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
385 /* Current operand we are working on. */
386 static int this_operand
= -1;
388 /* We support four different modes. FLAG_CODE variable is used to distinguish
396 static enum flag_code flag_code
;
397 static unsigned int object_64bit
;
398 static int use_rela_relocations
= 0;
400 /* The names used to print error messages. */
401 static const char *flag_code_names
[] =
408 /* 1 for intel syntax,
410 static int intel_syntax
= 0;
412 /* 1 for intel mnemonic,
413 0 if att mnemonic. */
414 static int intel_mnemonic
= !SYSV386_COMPAT
;
416 /* 1 if support old (<= 2.8.1) versions of gcc. */
417 static int old_gcc
= OLDGCC_COMPAT
;
419 /* 1 if pseudo registers are permitted. */
420 static int allow_pseudo_reg
= 0;
422 /* 1 if register prefix % not required. */
423 static int allow_naked_reg
= 0;
425 /* 1 if pseudo index register, eiz/riz, is allowed . */
426 static int allow_index_reg
= 0;
436 /* Register prefix used for error message. */
437 static const char *register_prefix
= "%";
439 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
440 leave, push, and pop instructions so that gcc has the same stack
441 frame as in 32 bit mode. */
442 static char stackop_size
= '\0';
444 /* Non-zero to optimize code alignment. */
445 int optimize_align_code
= 1;
447 /* Non-zero to quieten some warnings. */
448 static int quiet_warnings
= 0;
451 static const char *cpu_arch_name
= NULL
;
452 static char *cpu_sub_arch_name
= NULL
;
454 /* CPU feature flags. */
455 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
457 /* If we have selected a cpu we are generating instructions for. */
458 static int cpu_arch_tune_set
= 0;
460 /* Cpu we are generating instructions for. */
461 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
463 /* CPU feature flags of cpu we are generating instructions for. */
464 static i386_cpu_flags cpu_arch_tune_flags
;
466 /* CPU instruction set architecture used. */
467 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
469 /* CPU feature flags of instruction set architecture used. */
470 i386_cpu_flags cpu_arch_isa_flags
;
472 /* If set, conditional jumps are not automatically promoted to handle
473 larger than a byte offset. */
474 static unsigned int no_cond_jump_promotion
= 0;
476 /* Encode SSE instructions with VEX prefix. */
477 static unsigned int sse2avx
;
479 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
480 static symbolS
*GOT_symbol
;
482 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
483 unsigned int x86_dwarf2_return_column
;
485 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
486 int x86_cie_data_alignment
;
488 /* Interface to relax_segment.
489 There are 3 major relax states for 386 jump insns because the
490 different types of jumps add different sizes to frags when we're
491 figuring out what sort of jump to choose to reach a given label. */
494 #define UNCOND_JUMP 0
496 #define COND_JUMP86 2
501 #define SMALL16 (SMALL | CODE16)
503 #define BIG16 (BIG | CODE16)
507 #define INLINE __inline__
513 #define ENCODE_RELAX_STATE(type, size) \
514 ((relax_substateT) (((type) << 2) | (size)))
515 #define TYPE_FROM_RELAX_STATE(s) \
517 #define DISP_SIZE_FROM_RELAX_STATE(s) \
518 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
520 /* This table is used by relax_frag to promote short jumps to long
521 ones where necessary. SMALL (short) jumps may be promoted to BIG
522 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
523 don't allow a short jump in a 32 bit code segment to be promoted to
524 a 16 bit offset jump because it's slower (requires data size
525 prefix), and doesn't work, unless the destination is in the bottom
526 64k of the code segment (The top 16 bits of eip are zeroed). */
528 const relax_typeS md_relax_table
[] =
531 1) most positive reach of this state,
532 2) most negative reach of this state,
533 3) how many bytes this mode will have in the variable part of the frag
534 4) which index into the table to try if we can't fit into this one. */
536 /* UNCOND_JUMP states. */
537 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
538 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
539 /* dword jmp adds 4 bytes to frag:
540 0 extra opcode bytes, 4 displacement bytes. */
542 /* word jmp adds 2 byte2 to frag:
543 0 extra opcode bytes, 2 displacement bytes. */
546 /* COND_JUMP states. */
547 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
549 /* dword conditionals adds 5 bytes to frag:
550 1 extra opcode byte, 4 displacement bytes. */
552 /* word conditionals add 3 bytes to frag:
553 1 extra opcode byte, 2 displacement bytes. */
556 /* COND_JUMP86 states. */
557 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
559 /* dword conditionals adds 5 bytes to frag:
560 1 extra opcode byte, 4 displacement bytes. */
562 /* word conditionals add 4 bytes to frag:
563 1 displacement byte and a 3 byte long branch insn. */
567 static const arch_entry cpu_arch
[] =
569 { "generic32", PROCESSOR_GENERIC32
,
570 CPU_GENERIC32_FLAGS
},
571 { "generic64", PROCESSOR_GENERIC64
,
572 CPU_GENERIC64_FLAGS
},
573 { "i8086", PROCESSOR_UNKNOWN
,
575 { "i186", PROCESSOR_UNKNOWN
,
577 { "i286", PROCESSOR_UNKNOWN
,
579 { "i386", PROCESSOR_I386
,
581 { "i486", PROCESSOR_I486
,
583 { "i586", PROCESSOR_PENTIUM
,
585 { "i686", PROCESSOR_PENTIUMPRO
,
587 { "pentium", PROCESSOR_PENTIUM
,
589 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
591 { "pentiumii", PROCESSOR_PENTIUMPRO
,
593 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
595 { "pentium4", PROCESSOR_PENTIUM4
,
597 { "prescott", PROCESSOR_NOCONA
,
599 { "nocona", PROCESSOR_NOCONA
,
601 { "yonah", PROCESSOR_CORE
,
603 { "core", PROCESSOR_CORE
,
605 { "merom", PROCESSOR_CORE2
,
607 { "core2", PROCESSOR_CORE2
,
609 { "corei7", PROCESSOR_COREI7
,
611 { "k6", PROCESSOR_K6
,
613 { "k6_2", PROCESSOR_K6
,
615 { "athlon", PROCESSOR_ATHLON
,
617 { "sledgehammer", PROCESSOR_K8
,
619 { "opteron", PROCESSOR_K8
,
621 { "k8", PROCESSOR_K8
,
623 { "amdfam10", PROCESSOR_AMDFAM10
,
624 CPU_AMDFAM10_FLAGS
},
625 { ".mmx", PROCESSOR_UNKNOWN
,
627 { ".sse", PROCESSOR_UNKNOWN
,
629 { ".sse2", PROCESSOR_UNKNOWN
,
631 { ".sse3", PROCESSOR_UNKNOWN
,
633 { ".ssse3", PROCESSOR_UNKNOWN
,
635 { ".sse4.1", PROCESSOR_UNKNOWN
,
637 { ".sse4.2", PROCESSOR_UNKNOWN
,
639 { ".sse4", PROCESSOR_UNKNOWN
,
641 { ".avx", PROCESSOR_UNKNOWN
,
643 { ".vmx", PROCESSOR_UNKNOWN
,
645 { ".smx", PROCESSOR_UNKNOWN
,
647 { ".xsave", PROCESSOR_UNKNOWN
,
649 { ".aes", PROCESSOR_UNKNOWN
,
651 { ".pclmul", PROCESSOR_UNKNOWN
,
653 { ".clmul", PROCESSOR_UNKNOWN
,
655 { ".fma", PROCESSOR_UNKNOWN
,
657 { ".movbe", PROCESSOR_UNKNOWN
,
659 { ".ept", PROCESSOR_UNKNOWN
,
661 { ".clflush", PROCESSOR_UNKNOWN
,
663 { ".syscall", PROCESSOR_UNKNOWN
,
665 { ".rdtscp", PROCESSOR_UNKNOWN
,
667 { ".3dnow", PROCESSOR_UNKNOWN
,
669 { ".3dnowa", PROCESSOR_UNKNOWN
,
671 { ".padlock", PROCESSOR_UNKNOWN
,
673 { ".pacifica", PROCESSOR_UNKNOWN
,
675 { ".svme", PROCESSOR_UNKNOWN
,
677 { ".sse4a", PROCESSOR_UNKNOWN
,
679 { ".abm", PROCESSOR_UNKNOWN
,
681 { ".sse5", PROCESSOR_UNKNOWN
,
686 /* Like s_lcomm_internal in gas/read.c but the alignment string
687 is allowed to be optional. */
690 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
697 && *input_line_pointer
== ',')
699 align
= parse_align (needs_align
- 1);
701 if (align
== (addressT
) -1)
716 bss_alloc (symbolP
, size
, align
);
721 pe_lcomm (int needs_align
)
723 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
727 const pseudo_typeS md_pseudo_table
[] =
729 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
730 {"align", s_align_bytes
, 0},
732 {"align", s_align_ptwo
, 0},
734 {"arch", set_cpu_arch
, 0},
738 {"lcomm", pe_lcomm
, 1},
740 {"ffloat", float_cons
, 'f'},
741 {"dfloat", float_cons
, 'd'},
742 {"tfloat", float_cons
, 'x'},
744 {"slong", signed_cons
, 4},
745 {"noopt", s_ignore
, 0},
746 {"optim", s_ignore
, 0},
747 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
748 {"code16", set_code_flag
, CODE_16BIT
},
749 {"code32", set_code_flag
, CODE_32BIT
},
750 {"code64", set_code_flag
, CODE_64BIT
},
751 {"intel_syntax", set_intel_syntax
, 1},
752 {"att_syntax", set_intel_syntax
, 0},
753 {"intel_mnemonic", set_intel_mnemonic
, 1},
754 {"att_mnemonic", set_intel_mnemonic
, 0},
755 {"allow_index_reg", set_allow_index_reg
, 1},
756 {"disallow_index_reg", set_allow_index_reg
, 0},
757 {"sse_check", set_sse_check
, 0},
758 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
759 {"largecomm", handle_large_common
, 0},
761 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
762 {"loc", dwarf2_directive_loc
, 0},
763 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
766 {"secrel32", pe_directive_secrel
, 0},
771 /* For interface with expression (). */
772 extern char *input_line_pointer
;
774 /* Hash table for instruction mnemonic lookup. */
775 static struct hash_control
*op_hash
;
777 /* Hash table for register lookup. */
778 static struct hash_control
*reg_hash
;
781 i386_align_code (fragS
*fragP
, int count
)
783 /* Various efficient no-op patterns for aligning code labels.
784 Note: Don't try to assemble the instructions in the comments.
785 0L and 0w are not legal. */
786 static const char f32_1
[] =
788 static const char f32_2
[] =
789 {0x66,0x90}; /* xchg %ax,%ax */
790 static const char f32_3
[] =
791 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
792 static const char f32_4
[] =
793 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
794 static const char f32_5
[] =
796 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
797 static const char f32_6
[] =
798 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
799 static const char f32_7
[] =
800 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
801 static const char f32_8
[] =
803 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
804 static const char f32_9
[] =
805 {0x89,0xf6, /* movl %esi,%esi */
806 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
807 static const char f32_10
[] =
808 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
809 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
810 static const char f32_11
[] =
811 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
812 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
813 static const char f32_12
[] =
814 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
815 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
816 static const char f32_13
[] =
817 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
818 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
819 static const char f32_14
[] =
820 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
821 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
822 static const char f16_3
[] =
823 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
824 static const char f16_4
[] =
825 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
826 static const char f16_5
[] =
828 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
829 static const char f16_6
[] =
830 {0x89,0xf6, /* mov %si,%si */
831 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
832 static const char f16_7
[] =
833 {0x8d,0x74,0x00, /* lea 0(%si),%si */
834 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
835 static const char f16_8
[] =
836 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
837 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
838 static const char jump_31
[] =
839 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
840 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
841 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
842 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
843 static const char *const f32_patt
[] = {
844 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
845 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
847 static const char *const f16_patt
[] = {
848 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
851 static const char alt_3
[] =
853 /* nopl 0(%[re]ax) */
854 static const char alt_4
[] =
855 {0x0f,0x1f,0x40,0x00};
856 /* nopl 0(%[re]ax,%[re]ax,1) */
857 static const char alt_5
[] =
858 {0x0f,0x1f,0x44,0x00,0x00};
859 /* nopw 0(%[re]ax,%[re]ax,1) */
860 static const char alt_6
[] =
861 {0x66,0x0f,0x1f,0x44,0x00,0x00};
862 /* nopl 0L(%[re]ax) */
863 static const char alt_7
[] =
864 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
865 /* nopl 0L(%[re]ax,%[re]ax,1) */
866 static const char alt_8
[] =
867 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 /* nopw 0L(%[re]ax,%[re]ax,1) */
869 static const char alt_9
[] =
870 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
871 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
872 static const char alt_10
[] =
873 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_long_11
[] =
878 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
881 nopw %cs:0L(%[re]ax,%[re]ax,1) */
882 static const char alt_long_12
[] =
885 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
889 nopw %cs:0L(%[re]ax,%[re]ax,1) */
890 static const char alt_long_13
[] =
894 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
899 nopw %cs:0L(%[re]ax,%[re]ax,1) */
900 static const char alt_long_14
[] =
905 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
911 nopw %cs:0L(%[re]ax,%[re]ax,1) */
912 static const char alt_long_15
[] =
918 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
919 /* nopl 0(%[re]ax,%[re]ax,1)
920 nopw 0(%[re]ax,%[re]ax,1) */
921 static const char alt_short_11
[] =
922 {0x0f,0x1f,0x44,0x00,0x00,
923 0x66,0x0f,0x1f,0x44,0x00,0x00};
924 /* nopw 0(%[re]ax,%[re]ax,1)
925 nopw 0(%[re]ax,%[re]ax,1) */
926 static const char alt_short_12
[] =
927 {0x66,0x0f,0x1f,0x44,0x00,0x00,
928 0x66,0x0f,0x1f,0x44,0x00,0x00};
929 /* nopw 0(%[re]ax,%[re]ax,1)
931 static const char alt_short_13
[] =
932 {0x66,0x0f,0x1f,0x44,0x00,0x00,
933 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
936 static const char alt_short_14
[] =
937 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
938 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
940 nopl 0L(%[re]ax,%[re]ax,1) */
941 static const char alt_short_15
[] =
942 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
943 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
944 static const char *const alt_short_patt
[] = {
945 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
946 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
947 alt_short_14
, alt_short_15
949 static const char *const alt_long_patt
[] = {
950 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
951 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
952 alt_long_14
, alt_long_15
955 /* Only align for at least a positive non-zero boundary. */
956 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
959 /* We need to decide which NOP sequence to use for 32bit and
960 64bit. When -mtune= is used:
962 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
963 PROCESSOR_GENERIC32, f32_patt will be used.
964 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
965 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
966 PROCESSOR_GENERIC64, alt_long_patt will be used.
967 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
968 PROCESSOR_AMDFAM10, alt_short_patt will be used.
970 When -mtune= isn't used, alt_long_patt will be used if
971 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
974 When -march= or .arch is used, we can't use anything beyond
975 cpu_arch_isa_flags. */
977 if (flag_code
== CODE_16BIT
)
981 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
983 /* Adjust jump offset. */
984 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
987 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
988 f16_patt
[count
- 1], count
);
992 const char *const *patt
= NULL
;
994 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
996 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
997 switch (cpu_arch_tune
)
999 case PROCESSOR_UNKNOWN
:
1000 /* We use cpu_arch_isa_flags to check if we SHOULD
1001 optimize for Cpu686. */
1002 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1003 patt
= alt_long_patt
;
1007 case PROCESSOR_PENTIUMPRO
:
1008 case PROCESSOR_PENTIUM4
:
1009 case PROCESSOR_NOCONA
:
1010 case PROCESSOR_CORE
:
1011 case PROCESSOR_CORE2
:
1012 case PROCESSOR_COREI7
:
1013 case PROCESSOR_GENERIC64
:
1014 patt
= alt_long_patt
;
1017 case PROCESSOR_ATHLON
:
1019 case PROCESSOR_AMDFAM10
:
1020 patt
= alt_short_patt
;
1022 case PROCESSOR_I386
:
1023 case PROCESSOR_I486
:
1024 case PROCESSOR_PENTIUM
:
1025 case PROCESSOR_GENERIC32
:
1032 switch (fragP
->tc_frag_data
.tune
)
1034 case PROCESSOR_UNKNOWN
:
1035 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1036 PROCESSOR_UNKNOWN. */
1040 case PROCESSOR_I386
:
1041 case PROCESSOR_I486
:
1042 case PROCESSOR_PENTIUM
:
1044 case PROCESSOR_ATHLON
:
1046 case PROCESSOR_AMDFAM10
:
1047 case PROCESSOR_GENERIC32
:
1048 /* We use cpu_arch_isa_flags to check if we CAN optimize
1050 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1051 patt
= alt_short_patt
;
1055 case PROCESSOR_PENTIUMPRO
:
1056 case PROCESSOR_PENTIUM4
:
1057 case PROCESSOR_NOCONA
:
1058 case PROCESSOR_CORE
:
1059 case PROCESSOR_CORE2
:
1060 case PROCESSOR_COREI7
:
1061 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1062 patt
= alt_long_patt
;
1066 case PROCESSOR_GENERIC64
:
1067 patt
= alt_long_patt
;
1072 if (patt
== f32_patt
)
1074 /* If the padding is less than 15 bytes, we use the normal
1075 ones. Otherwise, we use a jump instruction and adjust
1078 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1079 patt
[count
- 1], count
);
1082 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1084 /* Adjust jump offset. */
1085 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1090 /* Maximum length of an instruction is 15 byte. If the
1091 padding is greater than 15 bytes and we don't use jump,
1092 we have to break it into smaller pieces. */
1093 int padding
= count
;
1094 while (padding
> 15)
1097 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1102 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1103 patt
[padding
- 1], padding
);
1106 fragP
->fr_var
= count
;
1110 operand_type_all_zero (const union i386_operand_type
*x
)
1112 switch (ARRAY_SIZE(x
->array
))
1121 return !x
->array
[0];
1128 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1130 switch (ARRAY_SIZE(x
->array
))
1145 operand_type_equal (const union i386_operand_type
*x
,
1146 const union i386_operand_type
*y
)
1148 switch (ARRAY_SIZE(x
->array
))
1151 if (x
->array
[2] != y
->array
[2])
1154 if (x
->array
[1] != y
->array
[1])
1157 return x
->array
[0] == y
->array
[0];
1165 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1167 switch (ARRAY_SIZE(x
->array
))
1176 return !x
->array
[0];
1183 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1185 switch (ARRAY_SIZE(x
->array
))
1200 cpu_flags_equal (const union i386_cpu_flags
*x
,
1201 const union i386_cpu_flags
*y
)
1203 switch (ARRAY_SIZE(x
->array
))
1206 if (x
->array
[2] != y
->array
[2])
1209 if (x
->array
[1] != y
->array
[1])
1212 return x
->array
[0] == y
->array
[0];
1220 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1222 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1223 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1226 static INLINE i386_cpu_flags
1227 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1229 switch (ARRAY_SIZE (x
.array
))
1232 x
.array
[2] &= y
.array
[2];
1234 x
.array
[1] &= y
.array
[1];
1236 x
.array
[0] &= y
.array
[0];
1244 static INLINE i386_cpu_flags
1245 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1247 switch (ARRAY_SIZE (x
.array
))
1250 x
.array
[2] |= y
.array
[2];
1252 x
.array
[1] |= y
.array
[1];
1254 x
.array
[0] |= y
.array
[0];
1262 #define CPU_FLAGS_ARCH_MATCH 0x1
1263 #define CPU_FLAGS_64BIT_MATCH 0x2
1264 #define CPU_FLAGS_AES_MATCH 0x4
1265 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1266 #define CPU_FLAGS_AVX_MATCH 0x10
1268 #define CPU_FLAGS_32BIT_MATCH \
1269 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1270 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1271 #define CPU_FLAGS_PERFECT_MATCH \
1272 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1274 /* Return CPU flags match bits. */
1277 cpu_flags_match (const template *t
)
1279 i386_cpu_flags x
= t
->cpu_flags
;
1280 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1282 x
.bitfield
.cpu64
= 0;
1283 x
.bitfield
.cpuno64
= 0;
1285 if (cpu_flags_all_zero (&x
))
1287 /* This instruction is available on all archs. */
1288 match
|= CPU_FLAGS_32BIT_MATCH
;
1292 /* This instruction is available only on some archs. */
1293 i386_cpu_flags cpu
= cpu_arch_flags
;
1295 cpu
.bitfield
.cpu64
= 0;
1296 cpu
.bitfield
.cpuno64
= 0;
1297 cpu
= cpu_flags_and (x
, cpu
);
1298 if (!cpu_flags_all_zero (&cpu
))
1300 if (x
.bitfield
.cpuavx
)
1302 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1303 if (cpu
.bitfield
.cpuavx
)
1305 /* Check SSE2AVX. */
1306 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1308 match
|= (CPU_FLAGS_ARCH_MATCH
1309 | CPU_FLAGS_AVX_MATCH
);
1311 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1312 match
|= CPU_FLAGS_AES_MATCH
;
1314 if (!x
.bitfield
.cpupclmul
1315 || cpu
.bitfield
.cpupclmul
)
1316 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1320 match
|= CPU_FLAGS_ARCH_MATCH
;
1323 match
|= CPU_FLAGS_32BIT_MATCH
;
1329 static INLINE i386_operand_type
1330 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1332 switch (ARRAY_SIZE (x
.array
))
1335 x
.array
[2] &= y
.array
[2];
1337 x
.array
[1] &= y
.array
[1];
1339 x
.array
[0] &= y
.array
[0];
1347 static INLINE i386_operand_type
1348 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1350 switch (ARRAY_SIZE (x
.array
))
1353 x
.array
[2] |= y
.array
[2];
1355 x
.array
[1] |= y
.array
[1];
1357 x
.array
[0] |= y
.array
[0];
1365 static INLINE i386_operand_type
1366 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1368 switch (ARRAY_SIZE (x
.array
))
1371 x
.array
[2] ^= y
.array
[2];
1373 x
.array
[1] ^= y
.array
[1];
1375 x
.array
[0] ^= y
.array
[0];
1383 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1384 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1385 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1386 static const i386_operand_type inoutportreg
1387 = OPERAND_TYPE_INOUTPORTREG
;
1388 static const i386_operand_type reg16_inoutportreg
1389 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1390 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1391 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1392 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1393 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1394 static const i386_operand_type anydisp
1395 = OPERAND_TYPE_ANYDISP
;
1396 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1397 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1398 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1399 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1400 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1401 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1402 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1403 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1404 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1405 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1406 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1417 operand_type_check (i386_operand_type t
, enum operand_type c
)
1422 return (t
.bitfield
.reg8
1425 || t
.bitfield
.reg64
);
1428 return (t
.bitfield
.imm8
1432 || t
.bitfield
.imm32s
1433 || t
.bitfield
.imm64
);
1436 return (t
.bitfield
.disp8
1437 || t
.bitfield
.disp16
1438 || t
.bitfield
.disp32
1439 || t
.bitfield
.disp32s
1440 || t
.bitfield
.disp64
);
1443 return (t
.bitfield
.disp8
1444 || t
.bitfield
.disp16
1445 || t
.bitfield
.disp32
1446 || t
.bitfield
.disp32s
1447 || t
.bitfield
.disp64
1448 || t
.bitfield
.baseindex
);
1457 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1458 operand J for instruction template T. */
1461 match_reg_size (const template *t
, unsigned int j
)
1463 return !((i
.types
[j
].bitfield
.byte
1464 && !t
->operand_types
[j
].bitfield
.byte
)
1465 || (i
.types
[j
].bitfield
.word
1466 && !t
->operand_types
[j
].bitfield
.word
)
1467 || (i
.types
[j
].bitfield
.dword
1468 && !t
->operand_types
[j
].bitfield
.dword
)
1469 || (i
.types
[j
].bitfield
.qword
1470 && !t
->operand_types
[j
].bitfield
.qword
));
1473 /* Return 1 if there is no conflict in any size on operand J for
1474 instruction template T. */
1477 match_mem_size (const template *t
, unsigned int j
)
1479 return (match_reg_size (t
, j
)
1480 && !((i
.types
[j
].bitfield
.unspecified
1481 && !t
->operand_types
[j
].bitfield
.unspecified
)
1482 || (i
.types
[j
].bitfield
.fword
1483 && !t
->operand_types
[j
].bitfield
.fword
)
1484 || (i
.types
[j
].bitfield
.tbyte
1485 && !t
->operand_types
[j
].bitfield
.tbyte
)
1486 || (i
.types
[j
].bitfield
.xmmword
1487 && !t
->operand_types
[j
].bitfield
.xmmword
)
1488 || (i
.types
[j
].bitfield
.ymmword
1489 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1492 /* Return 1 if there is no size conflict on any operands for
1493 instruction template T. */
1496 operand_size_match (const template *t
)
1501 /* Don't check jump instructions. */
1502 if (t
->opcode_modifier
.jump
1503 || t
->opcode_modifier
.jumpbyte
1504 || t
->opcode_modifier
.jumpdword
1505 || t
->opcode_modifier
.jumpintersegment
)
1508 /* Check memory and accumulator operand size. */
1509 for (j
= 0; j
< i
.operands
; j
++)
1511 if (t
->operand_types
[j
].bitfield
.anysize
)
1514 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1520 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1528 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1531 /* Check reverse. */
1532 assert (i
.operands
== 2);
1535 for (j
= 0; j
< 2; j
++)
1537 if (t
->operand_types
[j
].bitfield
.acc
1538 && !match_reg_size (t
, j
? 0 : 1))
1544 if (i
.types
[j
].bitfield
.mem
1545 && !match_mem_size (t
, j
? 0 : 1))
1556 operand_type_match (i386_operand_type overlap
,
1557 i386_operand_type given
)
1559 i386_operand_type temp
= overlap
;
1561 temp
.bitfield
.jumpabsolute
= 0;
1562 temp
.bitfield
.unspecified
= 0;
1563 temp
.bitfield
.byte
= 0;
1564 temp
.bitfield
.word
= 0;
1565 temp
.bitfield
.dword
= 0;
1566 temp
.bitfield
.fword
= 0;
1567 temp
.bitfield
.qword
= 0;
1568 temp
.bitfield
.tbyte
= 0;
1569 temp
.bitfield
.xmmword
= 0;
1570 temp
.bitfield
.ymmword
= 0;
1571 if (operand_type_all_zero (&temp
))
1574 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1575 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1578 /* If given types g0 and g1 are registers they must be of the same type
1579 unless the expected operand type register overlap is null.
1580 Note that Acc in a template matches every size of reg. */
1583 operand_type_register_match (i386_operand_type m0
,
1584 i386_operand_type g0
,
1585 i386_operand_type t0
,
1586 i386_operand_type m1
,
1587 i386_operand_type g1
,
1588 i386_operand_type t1
)
1590 if (!operand_type_check (g0
, reg
))
1593 if (!operand_type_check (g1
, reg
))
1596 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1597 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1598 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1599 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1602 if (m0
.bitfield
.acc
)
1604 t0
.bitfield
.reg8
= 1;
1605 t0
.bitfield
.reg16
= 1;
1606 t0
.bitfield
.reg32
= 1;
1607 t0
.bitfield
.reg64
= 1;
1610 if (m1
.bitfield
.acc
)
1612 t1
.bitfield
.reg8
= 1;
1613 t1
.bitfield
.reg16
= 1;
1614 t1
.bitfield
.reg32
= 1;
1615 t1
.bitfield
.reg64
= 1;
1618 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1619 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1620 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1621 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1624 static INLINE
unsigned int
1625 mode_from_disp_size (i386_operand_type t
)
1627 if (t
.bitfield
.disp8
)
1629 else if (t
.bitfield
.disp16
1630 || t
.bitfield
.disp32
1631 || t
.bitfield
.disp32s
)
1638 fits_in_signed_byte (offsetT num
)
1640 return (num
>= -128) && (num
<= 127);
1644 fits_in_unsigned_byte (offsetT num
)
1646 return (num
& 0xff) == num
;
1650 fits_in_unsigned_word (offsetT num
)
1652 return (num
& 0xffff) == num
;
1656 fits_in_signed_word (offsetT num
)
1658 return (-32768 <= num
) && (num
<= 32767);
1662 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1667 return (!(((offsetT
) -1 << 31) & num
)
1668 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1670 } /* fits_in_signed_long() */
1673 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1678 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1680 } /* fits_in_unsigned_long() */
1682 static i386_operand_type
1683 smallest_imm_type (offsetT num
)
1685 i386_operand_type t
;
1687 operand_type_set (&t
, 0);
1688 t
.bitfield
.imm64
= 1;
1690 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1692 /* This code is disabled on the 486 because all the Imm1 forms
1693 in the opcode table are slower on the i486. They're the
1694 versions with the implicitly specified single-position
1695 displacement, which has another syntax if you really want to
1697 t
.bitfield
.imm1
= 1;
1698 t
.bitfield
.imm8
= 1;
1699 t
.bitfield
.imm8s
= 1;
1700 t
.bitfield
.imm16
= 1;
1701 t
.bitfield
.imm32
= 1;
1702 t
.bitfield
.imm32s
= 1;
1704 else if (fits_in_signed_byte (num
))
1706 t
.bitfield
.imm8
= 1;
1707 t
.bitfield
.imm8s
= 1;
1708 t
.bitfield
.imm16
= 1;
1709 t
.bitfield
.imm32
= 1;
1710 t
.bitfield
.imm32s
= 1;
1712 else if (fits_in_unsigned_byte (num
))
1714 t
.bitfield
.imm8
= 1;
1715 t
.bitfield
.imm16
= 1;
1716 t
.bitfield
.imm32
= 1;
1717 t
.bitfield
.imm32s
= 1;
1719 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1721 t
.bitfield
.imm16
= 1;
1722 t
.bitfield
.imm32
= 1;
1723 t
.bitfield
.imm32s
= 1;
1725 else if (fits_in_signed_long (num
))
1727 t
.bitfield
.imm32
= 1;
1728 t
.bitfield
.imm32s
= 1;
1730 else if (fits_in_unsigned_long (num
))
1731 t
.bitfield
.imm32
= 1;
1737 offset_in_range (offsetT val
, int size
)
1743 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1744 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1745 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1747 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1752 /* If BFD64, sign extend val. */
1753 if (!use_rela_relocations
)
1754 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1755 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1757 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1759 char buf1
[40], buf2
[40];
1761 sprint_value (buf1
, val
);
1762 sprint_value (buf2
, val
& mask
);
1763 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1768 /* Returns 0 if attempting to add a prefix where one from the same
1769 class already exists, 1 if non rep/repne added, 2 if rep/repne
1772 add_prefix (unsigned int prefix
)
1777 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1778 && flag_code
== CODE_64BIT
)
1780 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1781 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1782 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1793 case CS_PREFIX_OPCODE
:
1794 case DS_PREFIX_OPCODE
:
1795 case ES_PREFIX_OPCODE
:
1796 case FS_PREFIX_OPCODE
:
1797 case GS_PREFIX_OPCODE
:
1798 case SS_PREFIX_OPCODE
:
1802 case REPNE_PREFIX_OPCODE
:
1803 case REPE_PREFIX_OPCODE
:
1806 case LOCK_PREFIX_OPCODE
:
1814 case ADDR_PREFIX_OPCODE
:
1818 case DATA_PREFIX_OPCODE
:
1822 if (i
.prefix
[q
] != 0)
1830 i
.prefix
[q
] |= prefix
;
1833 as_bad (_("same type of prefix used twice"));
1839 set_code_flag (int value
)
1842 if (flag_code
== CODE_64BIT
)
1844 cpu_arch_flags
.bitfield
.cpu64
= 1;
1845 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1849 cpu_arch_flags
.bitfield
.cpu64
= 0;
1850 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1852 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1854 as_bad (_("64bit mode not supported on this CPU."));
1856 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1858 as_bad (_("32bit mode not supported on this CPU."));
1860 stackop_size
= '\0';
1864 set_16bit_gcc_code_flag (int new_code_flag
)
1866 flag_code
= new_code_flag
;
1867 if (flag_code
!= CODE_16BIT
)
1869 cpu_arch_flags
.bitfield
.cpu64
= 0;
1870 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1871 stackop_size
= LONG_MNEM_SUFFIX
;
1875 set_intel_syntax (int syntax_flag
)
1877 /* Find out if register prefixing is specified. */
1878 int ask_naked_reg
= 0;
1881 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1883 char *string
= input_line_pointer
;
1884 int e
= get_symbol_end ();
1886 if (strcmp (string
, "prefix") == 0)
1888 else if (strcmp (string
, "noprefix") == 0)
1891 as_bad (_("bad argument to syntax directive."));
1892 *input_line_pointer
= e
;
1894 demand_empty_rest_of_line ();
1896 intel_syntax
= syntax_flag
;
1898 if (ask_naked_reg
== 0)
1899 allow_naked_reg
= (intel_syntax
1900 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1902 allow_naked_reg
= (ask_naked_reg
< 0);
1904 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1906 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1907 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1908 register_prefix
= allow_naked_reg
? "" : "%";
1912 set_intel_mnemonic (int mnemonic_flag
)
1914 intel_mnemonic
= mnemonic_flag
;
1918 set_allow_index_reg (int flag
)
1920 allow_index_reg
= flag
;
1924 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1928 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1930 char *string
= input_line_pointer
;
1931 int e
= get_symbol_end ();
1933 if (strcmp (string
, "none") == 0)
1934 sse_check
= sse_check_none
;
1935 else if (strcmp (string
, "warning") == 0)
1936 sse_check
= sse_check_warning
;
1937 else if (strcmp (string
, "error") == 0)
1938 sse_check
= sse_check_error
;
1940 as_bad (_("bad argument to sse_check directive."));
1941 *input_line_pointer
= e
;
1944 as_bad (_("missing argument for sse_check directive"));
1946 demand_empty_rest_of_line ();
1950 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
1954 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1956 char *string
= input_line_pointer
;
1957 int e
= get_symbol_end ();
1959 i386_cpu_flags flags
;
1961 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
1963 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
1967 cpu_arch_name
= cpu_arch
[i
].name
;
1968 cpu_sub_arch_name
= NULL
;
1969 cpu_arch_flags
= cpu_arch
[i
].flags
;
1970 if (flag_code
== CODE_64BIT
)
1972 cpu_arch_flags
.bitfield
.cpu64
= 1;
1973 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1977 cpu_arch_flags
.bitfield
.cpu64
= 0;
1978 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1980 cpu_arch_isa
= cpu_arch
[i
].type
;
1981 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
1982 if (!cpu_arch_tune_set
)
1984 cpu_arch_tune
= cpu_arch_isa
;
1985 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
1990 flags
= cpu_flags_or (cpu_arch_flags
,
1992 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
1994 if (cpu_sub_arch_name
)
1996 char *name
= cpu_sub_arch_name
;
1997 cpu_sub_arch_name
= concat (name
,
1999 (const char *) NULL
);
2003 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2004 cpu_arch_flags
= flags
;
2006 *input_line_pointer
= e
;
2007 demand_empty_rest_of_line ();
2011 if (i
>= ARRAY_SIZE (cpu_arch
))
2012 as_bad (_("no such architecture: `%s'"), string
);
2014 *input_line_pointer
= e
;
2017 as_bad (_("missing cpu architecture"));
2019 no_cond_jump_promotion
= 0;
2020 if (*input_line_pointer
== ','
2021 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2023 char *string
= ++input_line_pointer
;
2024 int e
= get_symbol_end ();
2026 if (strcmp (string
, "nojumps") == 0)
2027 no_cond_jump_promotion
= 1;
2028 else if (strcmp (string
, "jumps") == 0)
2031 as_bad (_("no such architecture modifier: `%s'"), string
);
2033 *input_line_pointer
= e
;
2036 demand_empty_rest_of_line ();
2042 if (!strcmp (default_arch
, "x86_64"))
2043 return bfd_mach_x86_64
;
2044 else if (!strcmp (default_arch
, "i386"))
2045 return bfd_mach_i386_i386
;
2047 as_fatal (_("Unknown architecture"));
2053 const char *hash_err
;
2055 /* Initialize op_hash hash table. */
2056 op_hash
= hash_new ();
2059 const template *optab
;
2060 templates
*core_optab
;
2062 /* Setup for loop. */
2064 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2065 core_optab
->start
= optab
;
2070 if (optab
->name
== NULL
2071 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2073 /* different name --> ship out current template list;
2074 add to hash table; & begin anew. */
2075 core_optab
->end
= optab
;
2076 hash_err
= hash_insert (op_hash
,
2078 (void *) core_optab
);
2081 as_fatal (_("Internal Error: Can't hash %s: %s"),
2085 if (optab
->name
== NULL
)
2087 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2088 core_optab
->start
= optab
;
2093 /* Initialize reg_hash hash table. */
2094 reg_hash
= hash_new ();
2096 const reg_entry
*regtab
;
2097 unsigned int regtab_size
= i386_regtab_size
;
2099 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2101 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2103 as_fatal (_("Internal Error: Can't hash %s: %s"),
2109 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2114 for (c
= 0; c
< 256; c
++)
2119 mnemonic_chars
[c
] = c
;
2120 register_chars
[c
] = c
;
2121 operand_chars
[c
] = c
;
2123 else if (ISLOWER (c
))
2125 mnemonic_chars
[c
] = c
;
2126 register_chars
[c
] = c
;
2127 operand_chars
[c
] = c
;
2129 else if (ISUPPER (c
))
2131 mnemonic_chars
[c
] = TOLOWER (c
);
2132 register_chars
[c
] = mnemonic_chars
[c
];
2133 operand_chars
[c
] = c
;
2136 if (ISALPHA (c
) || ISDIGIT (c
))
2137 identifier_chars
[c
] = c
;
2140 identifier_chars
[c
] = c
;
2141 operand_chars
[c
] = c
;
2146 identifier_chars
['@'] = '@';
2149 identifier_chars
['?'] = '?';
2150 operand_chars
['?'] = '?';
2152 digit_chars
['-'] = '-';
2153 mnemonic_chars
['_'] = '_';
2154 mnemonic_chars
['-'] = '-';
2155 mnemonic_chars
['.'] = '.';
2156 identifier_chars
['_'] = '_';
2157 identifier_chars
['.'] = '.';
2159 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2160 operand_chars
[(unsigned char) *p
] = *p
;
2163 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2166 record_alignment (text_section
, 2);
2167 record_alignment (data_section
, 2);
2168 record_alignment (bss_section
, 2);
2172 if (flag_code
== CODE_64BIT
)
2174 x86_dwarf2_return_column
= 16;
2175 x86_cie_data_alignment
= -8;
2179 x86_dwarf2_return_column
= 8;
2180 x86_cie_data_alignment
= -4;
2185 i386_print_statistics (FILE *file
)
2187 hash_print_statistics (file
, "i386 opcode", op_hash
);
2188 hash_print_statistics (file
, "i386 register", reg_hash
);
2193 /* Debugging routines for md_assemble. */
2194 static void pte (template *);
2195 static void pt (i386_operand_type
);
2196 static void pe (expressionS
*);
2197 static void ps (symbolS
*);
2200 pi (char *line
, i386_insn
*x
)
2204 fprintf (stdout
, "%s: template ", line
);
2206 fprintf (stdout
, " address: base %s index %s scale %x\n",
2207 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2208 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2209 x
->log2_scale_factor
);
2210 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2211 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2212 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2213 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2214 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2215 (x
->rex
& REX_W
) != 0,
2216 (x
->rex
& REX_R
) != 0,
2217 (x
->rex
& REX_X
) != 0,
2218 (x
->rex
& REX_B
) != 0);
2219 fprintf (stdout
, " drex: reg %d rex 0x%x\n",
2220 x
->drex
.reg
, x
->drex
.rex
);
2221 for (i
= 0; i
< x
->operands
; i
++)
2223 fprintf (stdout
, " #%d: ", i
+ 1);
2225 fprintf (stdout
, "\n");
2226 if (x
->types
[i
].bitfield
.reg8
2227 || x
->types
[i
].bitfield
.reg16
2228 || x
->types
[i
].bitfield
.reg32
2229 || x
->types
[i
].bitfield
.reg64
2230 || x
->types
[i
].bitfield
.regmmx
2231 || x
->types
[i
].bitfield
.regxmm
2232 || x
->types
[i
].bitfield
.regymm
2233 || x
->types
[i
].bitfield
.sreg2
2234 || x
->types
[i
].bitfield
.sreg3
2235 || x
->types
[i
].bitfield
.control
2236 || x
->types
[i
].bitfield
.debug
2237 || x
->types
[i
].bitfield
.test
)
2238 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2239 if (operand_type_check (x
->types
[i
], imm
))
2241 if (operand_type_check (x
->types
[i
], disp
))
2242 pe (x
->op
[i
].disps
);
2250 fprintf (stdout
, " %d operands ", t
->operands
);
2251 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2252 if (t
->extension_opcode
!= None
)
2253 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2254 if (t
->opcode_modifier
.d
)
2255 fprintf (stdout
, "D");
2256 if (t
->opcode_modifier
.w
)
2257 fprintf (stdout
, "W");
2258 fprintf (stdout
, "\n");
2259 for (i
= 0; i
< t
->operands
; i
++)
2261 fprintf (stdout
, " #%d type ", i
+ 1);
2262 pt (t
->operand_types
[i
]);
2263 fprintf (stdout
, "\n");
2270 fprintf (stdout
, " operation %d\n", e
->X_op
);
2271 fprintf (stdout
, " add_number %ld (%lx)\n",
2272 (long) e
->X_add_number
, (long) e
->X_add_number
);
2273 if (e
->X_add_symbol
)
2275 fprintf (stdout
, " add_symbol ");
2276 ps (e
->X_add_symbol
);
2277 fprintf (stdout
, "\n");
2281 fprintf (stdout
, " op_symbol ");
2282 ps (e
->X_op_symbol
);
2283 fprintf (stdout
, "\n");
2290 fprintf (stdout
, "%s type %s%s",
2292 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2293 segment_name (S_GET_SEGMENT (s
)));
2296 static struct type_name
2298 i386_operand_type mask
;
2301 const type_names
[] =
2303 { OPERAND_TYPE_REG8
, "r8" },
2304 { OPERAND_TYPE_REG16
, "r16" },
2305 { OPERAND_TYPE_REG32
, "r32" },
2306 { OPERAND_TYPE_REG64
, "r64" },
2307 { OPERAND_TYPE_IMM8
, "i8" },
2308 { OPERAND_TYPE_IMM8
, "i8s" },
2309 { OPERAND_TYPE_IMM16
, "i16" },
2310 { OPERAND_TYPE_IMM32
, "i32" },
2311 { OPERAND_TYPE_IMM32S
, "i32s" },
2312 { OPERAND_TYPE_IMM64
, "i64" },
2313 { OPERAND_TYPE_IMM1
, "i1" },
2314 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2315 { OPERAND_TYPE_DISP8
, "d8" },
2316 { OPERAND_TYPE_DISP16
, "d16" },
2317 { OPERAND_TYPE_DISP32
, "d32" },
2318 { OPERAND_TYPE_DISP32S
, "d32s" },
2319 { OPERAND_TYPE_DISP64
, "d64" },
2320 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2321 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2322 { OPERAND_TYPE_CONTROL
, "control reg" },
2323 { OPERAND_TYPE_TEST
, "test reg" },
2324 { OPERAND_TYPE_DEBUG
, "debug reg" },
2325 { OPERAND_TYPE_FLOATREG
, "FReg" },
2326 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2327 { OPERAND_TYPE_SREG2
, "SReg2" },
2328 { OPERAND_TYPE_SREG3
, "SReg3" },
2329 { OPERAND_TYPE_ACC
, "Acc" },
2330 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2331 { OPERAND_TYPE_REGMMX
, "rMMX" },
2332 { OPERAND_TYPE_REGXMM
, "rXMM" },
2333 { OPERAND_TYPE_REGYMM
, "rYMM" },
2334 { OPERAND_TYPE_ESSEG
, "es" },
2338 pt (i386_operand_type t
)
2341 i386_operand_type a
;
2343 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2345 a
= operand_type_and (t
, type_names
[j
].mask
);
2346 if (!operand_type_all_zero (&a
))
2347 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2352 #endif /* DEBUG386 */
2354 static bfd_reloc_code_real_type
2355 reloc (unsigned int size
,
2358 bfd_reloc_code_real_type other
)
2360 if (other
!= NO_RELOC
)
2362 reloc_howto_type
*reloc
;
2367 case BFD_RELOC_X86_64_GOT32
:
2368 return BFD_RELOC_X86_64_GOT64
;
2370 case BFD_RELOC_X86_64_PLTOFF64
:
2371 return BFD_RELOC_X86_64_PLTOFF64
;
2373 case BFD_RELOC_X86_64_GOTPC32
:
2374 other
= BFD_RELOC_X86_64_GOTPC64
;
2376 case BFD_RELOC_X86_64_GOTPCREL
:
2377 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2379 case BFD_RELOC_X86_64_TPOFF32
:
2380 other
= BFD_RELOC_X86_64_TPOFF64
;
2382 case BFD_RELOC_X86_64_DTPOFF32
:
2383 other
= BFD_RELOC_X86_64_DTPOFF64
;
2389 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2390 if (size
== 4 && flag_code
!= CODE_64BIT
)
2393 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2395 as_bad (_("unknown relocation (%u)"), other
);
2396 else if (size
!= bfd_get_reloc_size (reloc
))
2397 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2398 bfd_get_reloc_size (reloc
),
2400 else if (pcrel
&& !reloc
->pc_relative
)
2401 as_bad (_("non-pc-relative relocation for pc-relative field"));
2402 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2404 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2406 as_bad (_("relocated field and relocation type differ in signedness"));
2415 as_bad (_("there are no unsigned pc-relative relocations"));
2418 case 1: return BFD_RELOC_8_PCREL
;
2419 case 2: return BFD_RELOC_16_PCREL
;
2420 case 4: return BFD_RELOC_32_PCREL
;
2421 case 8: return BFD_RELOC_64_PCREL
;
2423 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2430 case 4: return BFD_RELOC_X86_64_32S
;
2435 case 1: return BFD_RELOC_8
;
2436 case 2: return BFD_RELOC_16
;
2437 case 4: return BFD_RELOC_32
;
2438 case 8: return BFD_RELOC_64
;
2440 as_bad (_("cannot do %s %u byte relocation"),
2441 sign
> 0 ? "signed" : "unsigned", size
);
2447 /* Here we decide which fixups can be adjusted to make them relative to
2448 the beginning of the section instead of the symbol. Basically we need
2449 to make sure that the dynamic relocations are done correctly, so in
2450 some cases we force the original symbol to be used. */
2453 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2455 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2459 /* Don't adjust pc-relative references to merge sections in 64-bit
2461 if (use_rela_relocations
2462 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2466 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2467 and changed later by validate_fix. */
2468 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2469 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2472 /* adjust_reloc_syms doesn't know about the GOT. */
2473 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2474 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2475 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2476 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2477 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2478 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2479 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2480 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2481 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2482 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2483 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2484 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2485 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2486 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2487 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2488 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2489 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2490 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2491 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2492 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2493 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2494 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2495 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2496 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2497 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2498 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2499 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2500 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2507 intel_float_operand (const char *mnemonic
)
2509 /* Note that the value returned is meaningful only for opcodes with (memory)
2510 operands, hence the code here is free to improperly handle opcodes that
2511 have no operands (for better performance and smaller code). */
2513 if (mnemonic
[0] != 'f')
2514 return 0; /* non-math */
2516 switch (mnemonic
[1])
2518 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2519 the fs segment override prefix not currently handled because no
2520 call path can make opcodes without operands get here */
2522 return 2 /* integer op */;
2524 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2525 return 3; /* fldcw/fldenv */
2528 if (mnemonic
[2] != 'o' /* fnop */)
2529 return 3; /* non-waiting control op */
2532 if (mnemonic
[2] == 's')
2533 return 3; /* frstor/frstpm */
2536 if (mnemonic
[2] == 'a')
2537 return 3; /* fsave */
2538 if (mnemonic
[2] == 't')
2540 switch (mnemonic
[3])
2542 case 'c': /* fstcw */
2543 case 'd': /* fstdw */
2544 case 'e': /* fstenv */
2545 case 's': /* fsts[gw] */
2551 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2552 return 0; /* fxsave/fxrstor are not really math ops */
2559 /* Build the VEX prefix. */
2562 build_vex_prefix (const template *t
)
2564 unsigned int register_specifier
;
2565 unsigned int implied_prefix
;
2566 unsigned int vector_length
;
2568 /* Check register specifier. */
2569 if (i
.vex
.register_specifier
)
2571 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2572 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2573 register_specifier
+= 8;
2574 register_specifier
= ~register_specifier
& 0xf;
2577 register_specifier
= 0xf;
2579 /* Use 2-byte VEX prefix by swappping destination and source
2582 && i
.operands
== i
.reg_operands
2583 && i
.tm
.opcode_modifier
.vex0f
2584 && i
.tm
.opcode_modifier
.s
2587 unsigned int xchg
= i
.operands
- 1;
2588 union i386_op temp_op
;
2589 i386_operand_type temp_type
;
2591 temp_type
= i
.types
[xchg
];
2592 i
.types
[xchg
] = i
.types
[0];
2593 i
.types
[0] = temp_type
;
2594 temp_op
= i
.op
[xchg
];
2595 i
.op
[xchg
] = i
.op
[0];
2598 assert (i
.rm
.mode
== 3);
2602 i
.rm
.regmem
= i
.rm
.reg
;
2605 /* Use the next insn. */
2609 vector_length
= i
.tm
.opcode_modifier
.vex256
? 1 : 0;
2611 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2616 case DATA_PREFIX_OPCODE
:
2619 case REPE_PREFIX_OPCODE
:
2622 case REPNE_PREFIX_OPCODE
:
2629 /* Use 2-byte VEX prefix if possible. */
2630 if (i
.tm
.opcode_modifier
.vex0f
2631 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2633 /* 2-byte VEX prefix. */
2637 i
.vex
.bytes
[0] = 0xc5;
2639 /* Check the REX.R bit. */
2640 r
= (i
.rex
& REX_R
) ? 0 : 1;
2641 i
.vex
.bytes
[1] = (r
<< 7
2642 | register_specifier
<< 3
2643 | vector_length
<< 2
2648 /* 3-byte VEX prefix. */
2651 if (i
.tm
.opcode_modifier
.vex0f
)
2653 else if (i
.tm
.opcode_modifier
.vex0f38
)
2655 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2661 i
.vex
.bytes
[0] = 0xc4;
2663 /* The high 3 bits of the second VEX byte are 1's compliment
2664 of RXB bits from REX. */
2665 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2667 /* Check the REX.W bit. */
2668 w
= (i
.rex
& REX_W
) ? 1 : 0;
2669 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2674 if (i
.tm
.opcode_modifier
.vexw1
)
2678 i
.vex
.bytes
[2] = (w
<< 7
2679 | register_specifier
<< 3
2680 | vector_length
<< 2
2686 process_immext (void)
2690 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2692 /* SSE3 Instructions have the fixed operands with an opcode
2693 suffix which is coded in the same place as an 8-bit immediate
2694 field would be. Here we check those operands and remove them
2698 for (x
= 0; x
< i
.operands
; x
++)
2699 if (i
.op
[x
].regs
->reg_num
!= x
)
2700 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2701 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2707 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2708 which is coded in the same place as an 8-bit immediate field
2709 would be. Here we fake an 8-bit immediate operand from the
2710 opcode suffix stored in tm.extension_opcode.
2712 SSE5 and AVX instructions also use this encoding, for some of
2713 3 argument instructions. */
2715 assert (i
.imm_operands
== 0
2717 || (i
.tm
.cpu_flags
.bitfield
.cpusse5
2719 || (i
.tm
.opcode_modifier
.vex
2720 && i
.operands
<= 4)));
2722 exp
= &im_expressions
[i
.imm_operands
++];
2723 i
.op
[i
.operands
].imms
= exp
;
2724 i
.types
[i
.operands
] = imm8
;
2726 exp
->X_op
= O_constant
;
2727 exp
->X_add_number
= i
.tm
.extension_opcode
;
2728 i
.tm
.extension_opcode
= None
;
2731 /* This is the guts of the machine-dependent assembler. LINE points to a
2732 machine dependent instruction. This function is supposed to emit
2733 the frags/bytes it assembles to. */
2736 md_assemble (char *line
)
2739 char mnemonic
[MAX_MNEM_SIZE
];
2742 /* Initialize globals. */
2743 memset (&i
, '\0', sizeof (i
));
2744 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2745 i
.reloc
[j
] = NO_RELOC
;
2746 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2747 memset (im_expressions
, '\0', sizeof (im_expressions
));
2748 save_stack_p
= save_stack
;
2750 /* First parse an instruction mnemonic & call i386_operand for the operands.
2751 We assume that the scrubber has arranged it so that line[0] is the valid
2752 start of a (possibly prefixed) mnemonic. */
2754 line
= parse_insn (line
, mnemonic
);
2758 line
= parse_operands (line
, mnemonic
);
2763 /* Now we've parsed the mnemonic into a set of templates, and have the
2764 operands at hand. */
2766 /* All intel opcodes have reversed operands except for "bound" and
2767 "enter". We also don't reverse intersegment "jmp" and "call"
2768 instructions with 2 immediate operands so that the immediate segment
2769 precedes the offset, as it does when in AT&T mode. */
2772 && (strcmp (mnemonic
, "bound") != 0)
2773 && (strcmp (mnemonic
, "invlpga") != 0)
2774 && !(operand_type_check (i
.types
[0], imm
)
2775 && operand_type_check (i
.types
[1], imm
)))
2778 /* The order of the immediates should be reversed
2779 for 2 immediates extrq and insertq instructions */
2780 if (i
.imm_operands
== 2
2781 && (strcmp (mnemonic
, "extrq") == 0
2782 || strcmp (mnemonic
, "insertq") == 0))
2783 swap_2_operands (0, 1);
2788 /* Don't optimize displacement for movabs since it only takes 64bit
2791 && (flag_code
!= CODE_64BIT
2792 || strcmp (mnemonic
, "movabs") != 0))
2795 /* Next, we find a template that matches the given insn,
2796 making sure the overlap of the given operands types is consistent
2797 with the template operand types. */
2799 if (!(t
= match_template ()))
2802 if (sse_check
!= sse_check_none
2803 && !i
.tm
.opcode_modifier
.noavx
2804 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2805 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2806 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2807 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2808 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2809 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2811 (sse_check
== sse_check_warning
2813 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2816 /* Zap movzx and movsx suffix. The suffix has been set from
2817 "word ptr" or "byte ptr" on the source operand in Intel syntax
2818 or extracted from mnemonic in AT&T syntax. But we'll use
2819 the destination register to choose the suffix for encoding. */
2820 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2822 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2823 there is no suffix, the default will be byte extension. */
2824 if (i
.reg_operands
!= 2
2827 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2832 if (i
.tm
.opcode_modifier
.fwait
)
2833 if (!add_prefix (FWAIT_OPCODE
))
2836 /* Check string instruction segment overrides. */
2837 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2839 if (!check_string ())
2841 i
.disp_operands
= 0;
2844 if (!process_suffix ())
2847 /* Make still unresolved immediate matches conform to size of immediate
2848 given in i.suffix. */
2849 if (!finalize_imm ())
2852 if (i
.types
[0].bitfield
.imm1
)
2853 i
.imm_operands
= 0; /* kludge for shift insns. */
2855 for (j
= 0; j
< 3; j
++)
2856 if (i
.types
[j
].bitfield
.inoutportreg
2857 || i
.types
[j
].bitfield
.shiftcount
2858 || i
.types
[j
].bitfield
.acc
2859 || i
.types
[j
].bitfield
.floatacc
)
2862 /* ImmExt should be processed after SSE2AVX. */
2863 if (!i
.tm
.opcode_modifier
.sse2avx
2864 && i
.tm
.opcode_modifier
.immext
)
2867 /* For insns with operands there are more diddles to do to the opcode. */
2870 if (!process_operands ())
2873 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2875 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2876 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2879 if (i
.tm
.opcode_modifier
.vex
)
2880 build_vex_prefix (t
);
2882 /* Handle conversion of 'int $3' --> special int3 insn. */
2883 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2885 i
.tm
.base_opcode
= INT3_OPCODE
;
2889 if ((i
.tm
.opcode_modifier
.jump
2890 || i
.tm
.opcode_modifier
.jumpbyte
2891 || i
.tm
.opcode_modifier
.jumpdword
)
2892 && i
.op
[0].disps
->X_op
== O_constant
)
2894 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2895 the absolute address given by the constant. Since ix86 jumps and
2896 calls are pc relative, we need to generate a reloc. */
2897 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2898 i
.op
[0].disps
->X_op
= O_symbol
;
2901 if (i
.tm
.opcode_modifier
.rex64
)
2904 /* For 8 bit registers we need an empty rex prefix. Also if the
2905 instruction already has a prefix, we need to convert old
2906 registers to new ones. */
2908 if ((i
.types
[0].bitfield
.reg8
2909 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2910 || (i
.types
[1].bitfield
.reg8
2911 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
2912 || ((i
.types
[0].bitfield
.reg8
2913 || i
.types
[1].bitfield
.reg8
)
2918 i
.rex
|= REX_OPCODE
;
2919 for (x
= 0; x
< 2; x
++)
2921 /* Look for 8 bit operand that uses old registers. */
2922 if (i
.types
[x
].bitfield
.reg8
2923 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
2925 /* In case it is "hi" register, give up. */
2926 if (i
.op
[x
].regs
->reg_num
> 3)
2927 as_bad (_("can't encode register '%s%s' in an "
2928 "instruction requiring REX prefix."),
2929 register_prefix
, i
.op
[x
].regs
->reg_name
);
2931 /* Otherwise it is equivalent to the extended register.
2932 Since the encoding doesn't change this is merely
2933 cosmetic cleanup for debug output. */
2935 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
2940 /* If the instruction has the DREX attribute (aka SSE5), don't emit a
2942 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
2947 else if (i
.rex
!= 0)
2948 add_prefix (REX_OPCODE
| i
.rex
);
2950 /* We are ready to output the insn. */
2955 parse_insn (char *line
, char *mnemonic
)
2958 char *token_start
= l
;
2964 /* Non-zero if we found a prefix only acceptable with string insns. */
2965 const char *expecting_string_instruction
= NULL
;
2970 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
2975 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
2977 as_bad (_("no such instruction: `%s'"), token_start
);
2982 if (!is_space_char (*l
)
2983 && *l
!= END_OF_INSN
2985 || (*l
!= PREFIX_SEPARATOR
2988 as_bad (_("invalid character %s in mnemonic"),
2989 output_invalid (*l
));
2992 if (token_start
== l
)
2994 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
2995 as_bad (_("expecting prefix; got nothing"));
2997 as_bad (_("expecting mnemonic; got nothing"));
3001 /* Look up instruction (or prefix) via hash table. */
3002 current_templates
= hash_find (op_hash
, mnemonic
);
3004 if (*l
!= END_OF_INSN
3005 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3006 && current_templates
3007 && current_templates
->start
->opcode_modifier
.isprefix
)
3009 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3011 as_bad ((flag_code
!= CODE_64BIT
3012 ? _("`%s' is only supported in 64-bit mode")
3013 : _("`%s' is not supported in 64-bit mode")),
3014 current_templates
->start
->name
);
3017 /* If we are in 16-bit mode, do not allow addr16 or data16.
3018 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3019 if ((current_templates
->start
->opcode_modifier
.size16
3020 || current_templates
->start
->opcode_modifier
.size32
)
3021 && flag_code
!= CODE_64BIT
3022 && (current_templates
->start
->opcode_modifier
.size32
3023 ^ (flag_code
== CODE_16BIT
)))
3025 as_bad (_("redundant %s prefix"),
3026 current_templates
->start
->name
);
3029 /* Add prefix, checking for repeated prefixes. */
3030 switch (add_prefix (current_templates
->start
->base_opcode
))
3035 expecting_string_instruction
= current_templates
->start
->name
;
3038 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3045 if (!current_templates
)
3047 /* Check if we should swap operand in encoding. */
3048 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3054 current_templates
= hash_find (op_hash
, mnemonic
);
3057 if (!current_templates
)
3060 /* See if we can get a match by trimming off a suffix. */
3063 case WORD_MNEM_SUFFIX
:
3064 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3065 i
.suffix
= SHORT_MNEM_SUFFIX
;
3067 case BYTE_MNEM_SUFFIX
:
3068 case QWORD_MNEM_SUFFIX
:
3069 i
.suffix
= mnem_p
[-1];
3071 current_templates
= hash_find (op_hash
, mnemonic
);
3073 case SHORT_MNEM_SUFFIX
:
3074 case LONG_MNEM_SUFFIX
:
3077 i
.suffix
= mnem_p
[-1];
3079 current_templates
= hash_find (op_hash
, mnemonic
);
3087 if (intel_float_operand (mnemonic
) == 1)
3088 i
.suffix
= SHORT_MNEM_SUFFIX
;
3090 i
.suffix
= LONG_MNEM_SUFFIX
;
3092 current_templates
= hash_find (op_hash
, mnemonic
);
3096 if (!current_templates
)
3098 as_bad (_("no such instruction: `%s'"), token_start
);
3103 if (current_templates
->start
->opcode_modifier
.jump
3104 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3106 /* Check for a branch hint. We allow ",pt" and ",pn" for
3107 predict taken and predict not taken respectively.
3108 I'm not sure that branch hints actually do anything on loop
3109 and jcxz insns (JumpByte) for current Pentium4 chips. They
3110 may work in the future and it doesn't hurt to accept them
3112 if (l
[0] == ',' && l
[1] == 'p')
3116 if (!add_prefix (DS_PREFIX_OPCODE
))
3120 else if (l
[2] == 'n')
3122 if (!add_prefix (CS_PREFIX_OPCODE
))
3128 /* Any other comma loses. */
3131 as_bad (_("invalid character %s in mnemonic"),
3132 output_invalid (*l
));
3136 /* Check if instruction is supported on specified architecture. */
3138 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3140 supported
|= cpu_flags_match (t
);
3141 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3145 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3147 as_bad (flag_code
== CODE_64BIT
3148 ? _("`%s' is not supported in 64-bit mode")
3149 : _("`%s' is only supported in 64-bit mode"),
3150 current_templates
->start
->name
);
3153 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3155 as_bad (_("`%s' is not supported on `%s%s'"),
3156 current_templates
->start
->name
,
3157 cpu_arch_name
? cpu_arch_name
: default_arch
,
3158 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3163 if (!cpu_arch_flags
.bitfield
.cpui386
3164 && (flag_code
!= CODE_16BIT
))
3166 as_warn (_("use .code16 to ensure correct addressing mode"));
3169 /* Check for rep/repne without a string instruction. */
3170 if (expecting_string_instruction
)
3172 static templates override
;
3174 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3175 if (t
->opcode_modifier
.isstring
)
3177 if (t
>= current_templates
->end
)
3179 as_bad (_("expecting string instruction after `%s'"),
3180 expecting_string_instruction
);
3183 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3184 if (!t
->opcode_modifier
.isstring
)
3187 current_templates
= &override
;
3194 parse_operands (char *l
, const char *mnemonic
)
3198 /* 1 if operand is pending after ','. */
3199 unsigned int expecting_operand
= 0;
3201 /* Non-zero if operand parens not balanced. */
3202 unsigned int paren_not_balanced
;
3204 while (*l
!= END_OF_INSN
)
3206 /* Skip optional white space before operand. */
3207 if (is_space_char (*l
))
3209 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3211 as_bad (_("invalid character %s before operand %d"),
3212 output_invalid (*l
),
3216 token_start
= l
; /* after white space */
3217 paren_not_balanced
= 0;
3218 while (paren_not_balanced
|| *l
!= ',')
3220 if (*l
== END_OF_INSN
)
3222 if (paren_not_balanced
)
3225 as_bad (_("unbalanced parenthesis in operand %d."),
3228 as_bad (_("unbalanced brackets in operand %d."),
3233 break; /* we are done */
3235 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3237 as_bad (_("invalid character %s in operand %d"),
3238 output_invalid (*l
),
3245 ++paren_not_balanced
;
3247 --paren_not_balanced
;
3252 ++paren_not_balanced
;
3254 --paren_not_balanced
;
3258 if (l
!= token_start
)
3259 { /* Yes, we've read in another operand. */
3260 unsigned int operand_ok
;
3261 this_operand
= i
.operands
++;
3262 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3263 if (i
.operands
> MAX_OPERANDS
)
3265 as_bad (_("spurious operands; (%d operands/instruction max)"),
3269 /* Now parse operand adding info to 'i' as we go along. */
3270 END_STRING_AND_SAVE (l
);
3274 i386_intel_operand (token_start
,
3275 intel_float_operand (mnemonic
));
3277 operand_ok
= i386_att_operand (token_start
);
3279 RESTORE_END_STRING (l
);
3285 if (expecting_operand
)
3287 expecting_operand_after_comma
:
3288 as_bad (_("expecting operand after ','; got nothing"));
3293 as_bad (_("expecting operand before ','; got nothing"));
3298 /* Now *l must be either ',' or END_OF_INSN. */
3301 if (*++l
== END_OF_INSN
)
3303 /* Just skip it, if it's \n complain. */
3304 goto expecting_operand_after_comma
;
3306 expecting_operand
= 1;
3313 swap_2_operands (int xchg1
, int xchg2
)
3315 union i386_op temp_op
;
3316 i386_operand_type temp_type
;
3317 enum bfd_reloc_code_real temp_reloc
;
3319 temp_type
= i
.types
[xchg2
];
3320 i
.types
[xchg2
] = i
.types
[xchg1
];
3321 i
.types
[xchg1
] = temp_type
;
3322 temp_op
= i
.op
[xchg2
];
3323 i
.op
[xchg2
] = i
.op
[xchg1
];
3324 i
.op
[xchg1
] = temp_op
;
3325 temp_reloc
= i
.reloc
[xchg2
];
3326 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3327 i
.reloc
[xchg1
] = temp_reloc
;
3331 swap_operands (void)
3337 swap_2_operands (1, i
.operands
- 2);
3340 swap_2_operands (0, i
.operands
- 1);
3346 if (i
.mem_operands
== 2)
3348 const seg_entry
*temp_seg
;
3349 temp_seg
= i
.seg
[0];
3350 i
.seg
[0] = i
.seg
[1];
3351 i
.seg
[1] = temp_seg
;
3355 /* Try to ensure constant immediates are represented in the smallest
3360 char guess_suffix
= 0;
3364 guess_suffix
= i
.suffix
;
3365 else if (i
.reg_operands
)
3367 /* Figure out a suffix from the last register operand specified.
3368 We can't do this properly yet, ie. excluding InOutPortReg,
3369 but the following works for instructions with immediates.
3370 In any case, we can't set i.suffix yet. */
3371 for (op
= i
.operands
; --op
>= 0;)
3372 if (i
.types
[op
].bitfield
.reg8
)
3374 guess_suffix
= BYTE_MNEM_SUFFIX
;
3377 else if (i
.types
[op
].bitfield
.reg16
)
3379 guess_suffix
= WORD_MNEM_SUFFIX
;
3382 else if (i
.types
[op
].bitfield
.reg32
)
3384 guess_suffix
= LONG_MNEM_SUFFIX
;
3387 else if (i
.types
[op
].bitfield
.reg64
)
3389 guess_suffix
= QWORD_MNEM_SUFFIX
;
3393 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3394 guess_suffix
= WORD_MNEM_SUFFIX
;
3396 for (op
= i
.operands
; --op
>= 0;)
3397 if (operand_type_check (i
.types
[op
], imm
))
3399 switch (i
.op
[op
].imms
->X_op
)
3402 /* If a suffix is given, this operand may be shortened. */
3403 switch (guess_suffix
)
3405 case LONG_MNEM_SUFFIX
:
3406 i
.types
[op
].bitfield
.imm32
= 1;
3407 i
.types
[op
].bitfield
.imm64
= 1;
3409 case WORD_MNEM_SUFFIX
:
3410 i
.types
[op
].bitfield
.imm16
= 1;
3411 i
.types
[op
].bitfield
.imm32
= 1;
3412 i
.types
[op
].bitfield
.imm32s
= 1;
3413 i
.types
[op
].bitfield
.imm64
= 1;
3415 case BYTE_MNEM_SUFFIX
:
3416 i
.types
[op
].bitfield
.imm8
= 1;
3417 i
.types
[op
].bitfield
.imm8s
= 1;
3418 i
.types
[op
].bitfield
.imm16
= 1;
3419 i
.types
[op
].bitfield
.imm32
= 1;
3420 i
.types
[op
].bitfield
.imm32s
= 1;
3421 i
.types
[op
].bitfield
.imm64
= 1;
3425 /* If this operand is at most 16 bits, convert it
3426 to a signed 16 bit number before trying to see
3427 whether it will fit in an even smaller size.
3428 This allows a 16-bit operand such as $0xffe0 to
3429 be recognised as within Imm8S range. */
3430 if ((i
.types
[op
].bitfield
.imm16
)
3431 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3433 i
.op
[op
].imms
->X_add_number
=
3434 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3436 if ((i
.types
[op
].bitfield
.imm32
)
3437 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3440 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3441 ^ ((offsetT
) 1 << 31))
3442 - ((offsetT
) 1 << 31));
3445 = operand_type_or (i
.types
[op
],
3446 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3448 /* We must avoid matching of Imm32 templates when 64bit
3449 only immediate is available. */
3450 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3451 i
.types
[op
].bitfield
.imm32
= 0;
3458 /* Symbols and expressions. */
3460 /* Convert symbolic operand to proper sizes for matching, but don't
3461 prevent matching a set of insns that only supports sizes other
3462 than those matching the insn suffix. */
3464 i386_operand_type mask
, allowed
;
3467 operand_type_set (&mask
, 0);
3468 operand_type_set (&allowed
, 0);
3470 for (t
= current_templates
->start
;
3471 t
< current_templates
->end
;
3473 allowed
= operand_type_or (allowed
,
3474 t
->operand_types
[op
]);
3475 switch (guess_suffix
)
3477 case QWORD_MNEM_SUFFIX
:
3478 mask
.bitfield
.imm64
= 1;
3479 mask
.bitfield
.imm32s
= 1;
3481 case LONG_MNEM_SUFFIX
:
3482 mask
.bitfield
.imm32
= 1;
3484 case WORD_MNEM_SUFFIX
:
3485 mask
.bitfield
.imm16
= 1;
3487 case BYTE_MNEM_SUFFIX
:
3488 mask
.bitfield
.imm8
= 1;
3493 allowed
= operand_type_and (mask
, allowed
);
3494 if (!operand_type_all_zero (&allowed
))
3495 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3502 /* Try to use the smallest displacement type too. */
3504 optimize_disp (void)
3508 for (op
= i
.operands
; --op
>= 0;)
3509 if (operand_type_check (i
.types
[op
], disp
))
3511 if (i
.op
[op
].disps
->X_op
== O_constant
)
3513 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3515 if (i
.types
[op
].bitfield
.disp16
3516 && (disp
& ~(offsetT
) 0xffff) == 0)
3518 /* If this operand is at most 16 bits, convert
3519 to a signed 16 bit number and don't use 64bit
3521 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3522 i
.types
[op
].bitfield
.disp64
= 0;
3524 if (i
.types
[op
].bitfield
.disp32
3525 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3527 /* If this operand is at most 32 bits, convert
3528 to a signed 32 bit number and don't use 64bit
3530 disp
&= (((offsetT
) 2 << 31) - 1);
3531 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3532 i
.types
[op
].bitfield
.disp64
= 0;
3534 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3536 i
.types
[op
].bitfield
.disp8
= 0;
3537 i
.types
[op
].bitfield
.disp16
= 0;
3538 i
.types
[op
].bitfield
.disp32
= 0;
3539 i
.types
[op
].bitfield
.disp32s
= 0;
3540 i
.types
[op
].bitfield
.disp64
= 0;
3544 else if (flag_code
== CODE_64BIT
)
3546 if (fits_in_signed_long (disp
))
3548 i
.types
[op
].bitfield
.disp64
= 0;
3549 i
.types
[op
].bitfield
.disp32s
= 1;
3551 if (fits_in_unsigned_long (disp
))
3552 i
.types
[op
].bitfield
.disp32
= 1;
3554 if ((i
.types
[op
].bitfield
.disp32
3555 || i
.types
[op
].bitfield
.disp32s
3556 || i
.types
[op
].bitfield
.disp16
)
3557 && fits_in_signed_byte (disp
))
3558 i
.types
[op
].bitfield
.disp8
= 1;
3560 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3561 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3563 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3564 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3565 i
.types
[op
].bitfield
.disp8
= 0;
3566 i
.types
[op
].bitfield
.disp16
= 0;
3567 i
.types
[op
].bitfield
.disp32
= 0;
3568 i
.types
[op
].bitfield
.disp32s
= 0;
3569 i
.types
[op
].bitfield
.disp64
= 0;
3572 /* We only support 64bit displacement on constants. */
3573 i
.types
[op
].bitfield
.disp64
= 0;
3577 static const template *
3578 match_template (void)
3580 /* Points to template once we've found it. */
3582 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3583 i386_operand_type overlap4
;
3584 unsigned int found_reverse_match
;
3585 i386_opcode_modifier suffix_check
;
3586 i386_operand_type operand_types
[MAX_OPERANDS
];
3587 int addr_prefix_disp
;
3589 unsigned int found_cpu_match
;
3590 unsigned int check_register
;
3592 #if MAX_OPERANDS != 5
3593 # error "MAX_OPERANDS must be 5."
3596 found_reverse_match
= 0;
3597 addr_prefix_disp
= -1;
3599 memset (&suffix_check
, 0, sizeof (suffix_check
));
3600 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3601 suffix_check
.no_bsuf
= 1;
3602 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3603 suffix_check
.no_wsuf
= 1;
3604 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3605 suffix_check
.no_ssuf
= 1;
3606 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3607 suffix_check
.no_lsuf
= 1;
3608 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3609 suffix_check
.no_qsuf
= 1;
3610 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3611 suffix_check
.no_ldsuf
= 1;
3613 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3615 addr_prefix_disp
= -1;
3617 /* Must have right number of operands. */
3618 if (i
.operands
!= t
->operands
)
3621 /* Check processor support. */
3622 found_cpu_match
= (cpu_flags_match (t
)
3623 == CPU_FLAGS_PERFECT_MATCH
);
3624 if (!found_cpu_match
)
3627 /* Check old gcc support. */
3628 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3631 /* Check AT&T mnemonic. */
3632 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3635 /* Check AT&T syntax Intel syntax. */
3636 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3637 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3640 /* Check the suffix, except for some instructions in intel mode. */
3641 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3642 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3643 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3644 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3645 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3646 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3647 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3650 if (!operand_size_match (t
))
3653 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3654 operand_types
[j
] = t
->operand_types
[j
];
3656 /* In general, don't allow 64-bit operands in 32-bit mode. */
3657 if (i
.suffix
== QWORD_MNEM_SUFFIX
3658 && flag_code
!= CODE_64BIT
3660 ? (!t
->opcode_modifier
.ignoresize
3661 && !intel_float_operand (t
->name
))
3662 : intel_float_operand (t
->name
) != 2)
3663 && ((!operand_types
[0].bitfield
.regmmx
3664 && !operand_types
[0].bitfield
.regxmm
3665 && !operand_types
[0].bitfield
.regymm
)
3666 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3667 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3668 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3669 && (t
->base_opcode
!= 0x0fc7
3670 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3673 /* In general, don't allow 32-bit operands on pre-386. */
3674 else if (i
.suffix
== LONG_MNEM_SUFFIX
3675 && !cpu_arch_flags
.bitfield
.cpui386
3677 ? (!t
->opcode_modifier
.ignoresize
3678 && !intel_float_operand (t
->name
))
3679 : intel_float_operand (t
->name
) != 2)
3680 && ((!operand_types
[0].bitfield
.regmmx
3681 && !operand_types
[0].bitfield
.regxmm
)
3682 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3683 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3686 /* Do not verify operands when there are none. */
3690 /* We've found a match; break out of loop. */
3694 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3695 into Disp32/Disp16/Disp32 operand. */
3696 if (i
.prefix
[ADDR_PREFIX
] != 0)
3698 /* There should be only one Disp operand. */
3702 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3704 if (operand_types
[j
].bitfield
.disp16
)
3706 addr_prefix_disp
= j
;
3707 operand_types
[j
].bitfield
.disp32
= 1;
3708 operand_types
[j
].bitfield
.disp16
= 0;
3714 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3716 if (operand_types
[j
].bitfield
.disp32
)
3718 addr_prefix_disp
= j
;
3719 operand_types
[j
].bitfield
.disp32
= 0;
3720 operand_types
[j
].bitfield
.disp16
= 1;
3726 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3728 if (operand_types
[j
].bitfield
.disp64
)
3730 addr_prefix_disp
= j
;
3731 operand_types
[j
].bitfield
.disp64
= 0;
3732 operand_types
[j
].bitfield
.disp32
= 1;
3740 /* We check register size only if size of operands can be
3741 encoded the canonical way. */
3742 check_register
= t
->opcode_modifier
.w
;
3743 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3744 switch (t
->operands
)
3747 if (!operand_type_match (overlap0
, i
.types
[0]))
3751 /* xchg %eax, %eax is a special case. It is an aliase for nop
3752 only in 32bit mode and we can use opcode 0x90. In 64bit
3753 mode, we can't use 0x90 for xchg %eax, %eax since it should
3754 zero-extend %eax to %rax. */
3755 if (flag_code
== CODE_64BIT
3756 && t
->base_opcode
== 0x90
3757 && operand_type_equal (&i
.types
[0], &acc32
)
3758 && operand_type_equal (&i
.types
[1], &acc32
))
3762 /* If we swap operand in encoding, we either match
3763 the next one or reverse direction of operands. */
3764 if (t
->opcode_modifier
.s
)
3766 else if (t
->opcode_modifier
.d
)
3771 /* If we swap operand in encoding, we match the next one. */
3772 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3776 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3777 if (!operand_type_match (overlap0
, i
.types
[0])
3778 || !operand_type_match (overlap1
, i
.types
[1])
3780 && !operand_type_register_match (overlap0
, i
.types
[0],
3782 overlap1
, i
.types
[1],
3785 /* Check if other direction is valid ... */
3786 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3790 /* Try reversing direction of operands. */
3791 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3792 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3793 if (!operand_type_match (overlap0
, i
.types
[0])
3794 || !operand_type_match (overlap1
, i
.types
[1])
3796 && !operand_type_register_match (overlap0
,
3803 /* Does not match either direction. */
3806 /* found_reverse_match holds which of D or FloatDR
3808 if (t
->opcode_modifier
.d
)
3809 found_reverse_match
= Opcode_D
;
3810 else if (t
->opcode_modifier
.floatd
)
3811 found_reverse_match
= Opcode_FloatD
;
3813 found_reverse_match
= 0;
3814 if (t
->opcode_modifier
.floatr
)
3815 found_reverse_match
|= Opcode_FloatR
;
3819 /* Found a forward 2 operand match here. */
3820 switch (t
->operands
)
3823 overlap4
= operand_type_and (i
.types
[4],
3826 overlap3
= operand_type_and (i
.types
[3],
3829 overlap2
= operand_type_and (i
.types
[2],
3834 switch (t
->operands
)
3837 if (!operand_type_match (overlap4
, i
.types
[4])
3838 || !operand_type_register_match (overlap3
,
3846 if (!operand_type_match (overlap3
, i
.types
[3])
3848 && !operand_type_register_match (overlap2
,
3856 /* Here we make use of the fact that there are no
3857 reverse match 3 operand instructions, and all 3
3858 operand instructions only need to be checked for
3859 register consistency between operands 2 and 3. */
3860 if (!operand_type_match (overlap2
, i
.types
[2])
3862 && !operand_type_register_match (overlap1
,
3872 /* Found either forward/reverse 2, 3 or 4 operand match here:
3873 slip through to break. */
3875 if (!found_cpu_match
)
3877 found_reverse_match
= 0;
3881 /* We've found a match; break out of loop. */
3885 if (t
== current_templates
->end
)
3887 /* We found no match. */
3889 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3890 current_templates
->start
->name
);
3892 as_bad (_("suffix or operands invalid for `%s'"),
3893 current_templates
->start
->name
);
3897 if (!quiet_warnings
)
3900 && (i
.types
[0].bitfield
.jumpabsolute
3901 != operand_types
[0].bitfield
.jumpabsolute
))
3903 as_warn (_("indirect %s without `*'"), t
->name
);
3906 if (t
->opcode_modifier
.isprefix
3907 && t
->opcode_modifier
.ignoresize
)
3909 /* Warn them that a data or address size prefix doesn't
3910 affect assembly of the next line of code. */
3911 as_warn (_("stand-alone `%s' prefix"), t
->name
);
3915 /* Copy the template we found. */
3918 if (addr_prefix_disp
!= -1)
3919 i
.tm
.operand_types
[addr_prefix_disp
]
3920 = operand_types
[addr_prefix_disp
];
3922 if (found_reverse_match
)
3924 /* If we found a reverse match we must alter the opcode
3925 direction bit. found_reverse_match holds bits to change
3926 (different for int & float insns). */
3928 i
.tm
.base_opcode
^= found_reverse_match
;
3930 i
.tm
.operand_types
[0] = operand_types
[1];
3931 i
.tm
.operand_types
[1] = operand_types
[0];
3940 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
3941 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
3943 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
3945 as_bad (_("`%s' operand %d must use `%ses' segment"),
3951 /* There's only ever one segment override allowed per instruction.
3952 This instruction possibly has a legal segment override on the
3953 second operand, so copy the segment to where non-string
3954 instructions store it, allowing common code. */
3955 i
.seg
[0] = i
.seg
[1];
3957 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
3959 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
3961 as_bad (_("`%s' operand %d must use `%ses' segment"),
3972 process_suffix (void)
3974 /* If matched instruction specifies an explicit instruction mnemonic
3976 if (i
.tm
.opcode_modifier
.size16
)
3977 i
.suffix
= WORD_MNEM_SUFFIX
;
3978 else if (i
.tm
.opcode_modifier
.size32
)
3979 i
.suffix
= LONG_MNEM_SUFFIX
;
3980 else if (i
.tm
.opcode_modifier
.size64
)
3981 i
.suffix
= QWORD_MNEM_SUFFIX
;
3982 else if (i
.reg_operands
)
3984 /* If there's no instruction mnemonic suffix we try to invent one
3985 based on register operands. */
3988 /* We take i.suffix from the last register operand specified,
3989 Destination register type is more significant than source
3990 register type. crc32 in SSE4.2 prefers source register
3992 if (i
.tm
.base_opcode
== 0xf20f38f1)
3994 if (i
.types
[0].bitfield
.reg16
)
3995 i
.suffix
= WORD_MNEM_SUFFIX
;
3996 else if (i
.types
[0].bitfield
.reg32
)
3997 i
.suffix
= LONG_MNEM_SUFFIX
;
3998 else if (i
.types
[0].bitfield
.reg64
)
3999 i
.suffix
= QWORD_MNEM_SUFFIX
;
4001 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4003 if (i
.types
[0].bitfield
.reg8
)
4004 i
.suffix
= BYTE_MNEM_SUFFIX
;
4011 if (i
.tm
.base_opcode
== 0xf20f38f1
4012 || i
.tm
.base_opcode
== 0xf20f38f0)
4014 /* We have to know the operand size for crc32. */
4015 as_bad (_("ambiguous memory operand size for `%s`"),
4020 for (op
= i
.operands
; --op
>= 0;)
4021 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4023 if (i
.types
[op
].bitfield
.reg8
)
4025 i
.suffix
= BYTE_MNEM_SUFFIX
;
4028 else if (i
.types
[op
].bitfield
.reg16
)
4030 i
.suffix
= WORD_MNEM_SUFFIX
;
4033 else if (i
.types
[op
].bitfield
.reg32
)
4035 i
.suffix
= LONG_MNEM_SUFFIX
;
4038 else if (i
.types
[op
].bitfield
.reg64
)
4040 i
.suffix
= QWORD_MNEM_SUFFIX
;
4046 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4048 if (!check_byte_reg ())
4051 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4053 if (!check_long_reg ())
4056 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4059 && i
.tm
.opcode_modifier
.ignoresize
4060 && i
.tm
.opcode_modifier
.no_qsuf
)
4062 else if (!check_qword_reg ())
4065 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4067 if (!check_word_reg ())
4070 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4071 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4073 /* Skip if the instruction has x/y suffix. match_template
4074 should check if it is a valid suffix. */
4076 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4077 /* Do nothing if the instruction is going to ignore the prefix. */
4082 else if (i
.tm
.opcode_modifier
.defaultsize
4084 /* exclude fldenv/frstor/fsave/fstenv */
4085 && i
.tm
.opcode_modifier
.no_ssuf
)
4087 i
.suffix
= stackop_size
;
4089 else if (intel_syntax
4091 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4092 || i
.tm
.opcode_modifier
.jumpbyte
4093 || i
.tm
.opcode_modifier
.jumpintersegment
4094 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4095 && i
.tm
.extension_opcode
<= 3)))
4100 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4102 i
.suffix
= QWORD_MNEM_SUFFIX
;
4106 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4107 i
.suffix
= LONG_MNEM_SUFFIX
;
4110 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4111 i
.suffix
= WORD_MNEM_SUFFIX
;
4120 if (i
.tm
.opcode_modifier
.w
)
4122 as_bad (_("no instruction mnemonic suffix given and "
4123 "no register operands; can't size instruction"));
4129 unsigned int suffixes
;
4131 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4132 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4134 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4136 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4138 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4140 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4143 /* There are more than suffix matches. */
4144 if (i
.tm
.opcode_modifier
.w
4145 || ((suffixes
& (suffixes
- 1))
4146 && !i
.tm
.opcode_modifier
.defaultsize
4147 && !i
.tm
.opcode_modifier
.ignoresize
))
4149 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4155 /* Change the opcode based on the operand size given by i.suffix;
4156 We don't need to change things for byte insns. */
4159 && i
.suffix
!= BYTE_MNEM_SUFFIX
4160 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4161 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4163 /* It's not a byte, select word/dword operation. */
4164 if (i
.tm
.opcode_modifier
.w
)
4166 if (i
.tm
.opcode_modifier
.shortform
)
4167 i
.tm
.base_opcode
|= 8;
4169 i
.tm
.base_opcode
|= 1;
4172 /* Now select between word & dword operations via the operand
4173 size prefix, except for instructions that will ignore this
4175 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4177 /* The address size override prefix changes the size of the
4179 if ((flag_code
== CODE_32BIT
4180 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4181 || (flag_code
!= CODE_32BIT
4182 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4183 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4186 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4187 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4188 && !i
.tm
.opcode_modifier
.ignoresize
4189 && !i
.tm
.opcode_modifier
.floatmf
4190 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4191 || (flag_code
== CODE_64BIT
4192 && i
.tm
.opcode_modifier
.jumpbyte
)))
4194 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4196 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4197 prefix
= ADDR_PREFIX_OPCODE
;
4199 if (!add_prefix (prefix
))
4203 /* Set mode64 for an operand. */
4204 if (i
.suffix
== QWORD_MNEM_SUFFIX
4205 && flag_code
== CODE_64BIT
4206 && !i
.tm
.opcode_modifier
.norex64
)
4208 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4209 need rex64. cmpxchg8b is also a special case. */
4210 if (! (i
.operands
== 2
4211 && i
.tm
.base_opcode
== 0x90
4212 && i
.tm
.extension_opcode
== None
4213 && operand_type_equal (&i
.types
[0], &acc64
)
4214 && operand_type_equal (&i
.types
[1], &acc64
))
4215 && ! (i
.operands
== 1
4216 && i
.tm
.base_opcode
== 0xfc7
4217 && i
.tm
.extension_opcode
== 1
4218 && !operand_type_check (i
.types
[0], reg
)
4219 && operand_type_check (i
.types
[0], anymem
)))
4223 /* Size floating point instruction. */
4224 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4225 if (i
.tm
.opcode_modifier
.floatmf
)
4226 i
.tm
.base_opcode
^= 4;
4233 check_byte_reg (void)
4237 for (op
= i
.operands
; --op
>= 0;)
4239 /* If this is an eight bit register, it's OK. If it's the 16 or
4240 32 bit version of an eight bit register, we will just use the
4241 low portion, and that's OK too. */
4242 if (i
.types
[op
].bitfield
.reg8
)
4245 /* Don't generate this warning if not needed. */
4246 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4249 /* crc32 doesn't generate this warning. */
4250 if (i
.tm
.base_opcode
== 0xf20f38f0)
4253 if ((i
.types
[op
].bitfield
.reg16
4254 || i
.types
[op
].bitfield
.reg32
4255 || i
.types
[op
].bitfield
.reg64
)
4256 && i
.op
[op
].regs
->reg_num
< 4)
4258 /* Prohibit these changes in the 64bit mode, since the
4259 lowering is more complicated. */
4260 if (flag_code
== CODE_64BIT
4261 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4263 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4264 register_prefix
, i
.op
[op
].regs
->reg_name
,
4268 #if REGISTER_WARNINGS
4270 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4271 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4273 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4274 ? REGNAM_AL
- REGNAM_AX
4275 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4277 i
.op
[op
].regs
->reg_name
,
4282 /* Any other register is bad. */
4283 if (i
.types
[op
].bitfield
.reg16
4284 || i
.types
[op
].bitfield
.reg32
4285 || i
.types
[op
].bitfield
.reg64
4286 || i
.types
[op
].bitfield
.regmmx
4287 || i
.types
[op
].bitfield
.regxmm
4288 || i
.types
[op
].bitfield
.regymm
4289 || i
.types
[op
].bitfield
.sreg2
4290 || i
.types
[op
].bitfield
.sreg3
4291 || i
.types
[op
].bitfield
.control
4292 || i
.types
[op
].bitfield
.debug
4293 || i
.types
[op
].bitfield
.test
4294 || i
.types
[op
].bitfield
.floatreg
4295 || i
.types
[op
].bitfield
.floatacc
)
4297 as_bad (_("`%s%s' not allowed with `%s%c'"),
4299 i
.op
[op
].regs
->reg_name
,
4309 check_long_reg (void)
4313 for (op
= i
.operands
; --op
>= 0;)
4314 /* Reject eight bit registers, except where the template requires
4315 them. (eg. movzb) */
4316 if (i
.types
[op
].bitfield
.reg8
4317 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4318 || i
.tm
.operand_types
[op
].bitfield
.reg32
4319 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4321 as_bad (_("`%s%s' not allowed with `%s%c'"),
4323 i
.op
[op
].regs
->reg_name
,
4328 /* Warn if the e prefix on a general reg is missing. */
4329 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4330 && i
.types
[op
].bitfield
.reg16
4331 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4332 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4334 /* Prohibit these changes in the 64bit mode, since the
4335 lowering is more complicated. */
4336 if (flag_code
== CODE_64BIT
)
4338 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4339 register_prefix
, i
.op
[op
].regs
->reg_name
,
4343 #if REGISTER_WARNINGS
4345 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4347 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4349 i
.op
[op
].regs
->reg_name
,
4353 /* Warn if the r prefix on a general reg is missing. */
4354 else if (i
.types
[op
].bitfield
.reg64
4355 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4356 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4359 && i
.tm
.opcode_modifier
.toqword
4360 && !i
.types
[0].bitfield
.regxmm
)
4362 /* Convert to QWORD. We want REX byte. */
4363 i
.suffix
= QWORD_MNEM_SUFFIX
;
4367 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4368 register_prefix
, i
.op
[op
].regs
->reg_name
,
4377 check_qword_reg (void)
4381 for (op
= i
.operands
; --op
>= 0; )
4382 /* Reject eight bit registers, except where the template requires
4383 them. (eg. movzb) */
4384 if (i
.types
[op
].bitfield
.reg8
4385 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4386 || i
.tm
.operand_types
[op
].bitfield
.reg32
4387 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4389 as_bad (_("`%s%s' not allowed with `%s%c'"),
4391 i
.op
[op
].regs
->reg_name
,
4396 /* Warn if the e prefix on a general reg is missing. */
4397 else if ((i
.types
[op
].bitfield
.reg16
4398 || i
.types
[op
].bitfield
.reg32
)
4399 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4400 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4402 /* Prohibit these changes in the 64bit mode, since the
4403 lowering is more complicated. */
4405 && i
.tm
.opcode_modifier
.todword
4406 && !i
.types
[0].bitfield
.regxmm
)
4408 /* Convert to DWORD. We don't want REX byte. */
4409 i
.suffix
= LONG_MNEM_SUFFIX
;
4413 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4414 register_prefix
, i
.op
[op
].regs
->reg_name
,
4423 check_word_reg (void)
4426 for (op
= i
.operands
; --op
>= 0;)
4427 /* Reject eight bit registers, except where the template requires
4428 them. (eg. movzb) */
4429 if (i
.types
[op
].bitfield
.reg8
4430 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4431 || i
.tm
.operand_types
[op
].bitfield
.reg32
4432 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4434 as_bad (_("`%s%s' not allowed with `%s%c'"),
4436 i
.op
[op
].regs
->reg_name
,
4441 /* Warn if the e prefix on a general reg is present. */
4442 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4443 && i
.types
[op
].bitfield
.reg32
4444 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4445 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4447 /* Prohibit these changes in the 64bit mode, since the
4448 lowering is more complicated. */
4449 if (flag_code
== CODE_64BIT
)
4451 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4452 register_prefix
, i
.op
[op
].regs
->reg_name
,
4457 #if REGISTER_WARNINGS
4458 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4460 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4462 i
.op
[op
].regs
->reg_name
,
4470 update_imm (unsigned int j
)
4472 i386_operand_type overlap
;
4474 overlap
= operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
4475 if ((overlap
.bitfield
.imm8
4476 || overlap
.bitfield
.imm8s
4477 || overlap
.bitfield
.imm16
4478 || overlap
.bitfield
.imm32
4479 || overlap
.bitfield
.imm32s
4480 || overlap
.bitfield
.imm64
)
4481 && !operand_type_equal (&overlap
, &imm8
)
4482 && !operand_type_equal (&overlap
, &imm8s
)
4483 && !operand_type_equal (&overlap
, &imm16
)
4484 && !operand_type_equal (&overlap
, &imm32
)
4485 && !operand_type_equal (&overlap
, &imm32s
)
4486 && !operand_type_equal (&overlap
, &imm64
))
4490 i386_operand_type temp
;
4492 operand_type_set (&temp
, 0);
4493 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4495 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4496 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4498 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4499 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4500 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4502 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4503 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4506 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4509 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4510 || operand_type_equal (&overlap
, &imm16_32
)
4511 || operand_type_equal (&overlap
, &imm16_32s
))
4513 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4518 if (!operand_type_equal (&overlap
, &imm8
)
4519 && !operand_type_equal (&overlap
, &imm8s
)
4520 && !operand_type_equal (&overlap
, &imm16
)
4521 && !operand_type_equal (&overlap
, &imm32
)
4522 && !operand_type_equal (&overlap
, &imm32s
)
4523 && !operand_type_equal (&overlap
, &imm64
))
4525 as_bad (_("no instruction mnemonic suffix given; "
4526 "can't determine immediate size"));
4530 i
.types
[j
] = overlap
;
4540 for (j
= 0; j
< 2; j
++)
4541 if (update_imm (j
) == 0)
4544 i
.types
[2] = operand_type_and (i
.types
[2], i
.tm
.operand_types
[2]);
4545 assert (operand_type_check (i
.types
[2], imm
) == 0);
4553 i
.drex
.modrm_reg
= 0;
4554 i
.drex
.modrm_regmem
= 0;
4556 /* SSE5 4 operand instructions must have the destination the same as
4557 one of the inputs. Figure out the destination register and cache
4558 it away in the drex field, and remember which fields to use for
4560 if (i
.tm
.opcode_modifier
.drex
4561 && i
.tm
.opcode_modifier
.drexv
4564 i
.tm
.extension_opcode
= None
;
4566 /* Case 1: 4 operand insn, dest = src1, src3 = register. */
4567 if (i
.types
[0].bitfield
.regxmm
!= 0
4568 && i
.types
[1].bitfield
.regxmm
!= 0
4569 && i
.types
[2].bitfield
.regxmm
!= 0
4570 && i
.types
[3].bitfield
.regxmm
!= 0
4571 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4572 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4574 /* Clear the arguments that are stored in drex. */
4575 operand_type_set (&i
.types
[0], 0);
4576 operand_type_set (&i
.types
[3], 0);
4577 i
.reg_operands
-= 2;
4579 /* There are two different ways to encode a 4 operand
4580 instruction with all registers that uses OC1 set to
4581 0 or 1. Favor setting OC1 to 0 since this mimics the
4582 actions of other SSE5 assemblers. Use modrm encoding 2
4583 for register/register. Include the high order bit that
4584 is normally stored in the REX byte in the register
4586 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4587 i
.drex
.modrm_reg
= 2;
4588 i
.drex
.modrm_regmem
= 1;
4589 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4590 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4593 /* Case 2: 4 operand insn, dest = src1, src3 = memory. */
4594 else if (i
.types
[0].bitfield
.regxmm
!= 0
4595 && i
.types
[1].bitfield
.regxmm
!= 0
4596 && (i
.types
[2].bitfield
.regxmm
4597 || operand_type_check (i
.types
[2], anymem
))
4598 && i
.types
[3].bitfield
.regxmm
!= 0
4599 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4600 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4602 /* clear the arguments that are stored in drex */
4603 operand_type_set (&i
.types
[0], 0);
4604 operand_type_set (&i
.types
[3], 0);
4605 i
.reg_operands
-= 2;
4607 /* Specify the modrm encoding for memory addressing. Include
4608 the high order bit that is normally stored in the REX byte
4609 in the register field. */
4610 i
.tm
.extension_opcode
= DREX_X1_X2_XMEM_X1
;
4611 i
.drex
.modrm_reg
= 1;
4612 i
.drex
.modrm_regmem
= 2;
4613 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4614 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4617 /* Case 3: 4 operand insn, dest = src1, src2 = memory. */
4618 else if (i
.types
[0].bitfield
.regxmm
!= 0
4619 && operand_type_check (i
.types
[1], anymem
) != 0
4620 && i
.types
[2].bitfield
.regxmm
!= 0
4621 && i
.types
[3].bitfield
.regxmm
!= 0
4622 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4623 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4625 /* Clear the arguments that are stored in drex. */
4626 operand_type_set (&i
.types
[0], 0);
4627 operand_type_set (&i
.types
[3], 0);
4628 i
.reg_operands
-= 2;
4630 /* Specify the modrm encoding for memory addressing. Include
4631 the high order bit that is normally stored in the REX byte
4632 in the register field. */
4633 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X1
;
4634 i
.drex
.modrm_reg
= 2;
4635 i
.drex
.modrm_regmem
= 1;
4636 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4637 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4640 /* Case 4: 4 operand insn, dest = src3, src2 = register. */
4641 else if (i
.types
[0].bitfield
.regxmm
!= 0
4642 && i
.types
[1].bitfield
.regxmm
!= 0
4643 && i
.types
[2].bitfield
.regxmm
!= 0
4644 && i
.types
[3].bitfield
.regxmm
!= 0
4645 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4646 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4648 /* clear the arguments that are stored in drex */
4649 operand_type_set (&i
.types
[2], 0);
4650 operand_type_set (&i
.types
[3], 0);
4651 i
.reg_operands
-= 2;
4653 /* There are two different ways to encode a 4 operand
4654 instruction with all registers that uses OC1 set to
4655 0 or 1. Favor setting OC1 to 0 since this mimics the
4656 actions of other SSE5 assemblers. Use modrm encoding
4657 2 for register/register. Include the high order bit that
4658 is normally stored in the REX byte in the register
4660 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4661 i
.drex
.modrm_reg
= 1;
4662 i
.drex
.modrm_regmem
= 0;
4664 /* Remember the register, including the upper bits */
4665 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4666 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4669 /* Case 5: 4 operand insn, dest = src3, src2 = memory. */
4670 else if (i
.types
[0].bitfield
.regxmm
!= 0
4671 && (i
.types
[1].bitfield
.regxmm
4672 || operand_type_check (i
.types
[1], anymem
))
4673 && i
.types
[2].bitfield
.regxmm
!= 0
4674 && i
.types
[3].bitfield
.regxmm
!= 0
4675 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4676 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4678 /* Clear the arguments that are stored in drex. */
4679 operand_type_set (&i
.types
[2], 0);
4680 operand_type_set (&i
.types
[3], 0);
4681 i
.reg_operands
-= 2;
4683 /* Specify the modrm encoding and remember the register
4684 including the bits normally stored in the REX byte. */
4685 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2_X2
;
4686 i
.drex
.modrm_reg
= 0;
4687 i
.drex
.modrm_regmem
= 1;
4688 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4689 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4692 /* Case 6: 4 operand insn, dest = src3, src1 = memory. */
4693 else if (operand_type_check (i
.types
[0], anymem
) != 0
4694 && i
.types
[1].bitfield
.regxmm
!= 0
4695 && i
.types
[2].bitfield
.regxmm
!= 0
4696 && i
.types
[3].bitfield
.regxmm
!= 0
4697 && i
.op
[2].regs
->reg_num
== i
.op
[3].regs
->reg_num
4698 && i
.op
[2].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4700 /* clear the arguments that are stored in drex */
4701 operand_type_set (&i
.types
[2], 0);
4702 operand_type_set (&i
.types
[3], 0);
4703 i
.reg_operands
-= 2;
4705 /* Specify the modrm encoding and remember the register
4706 including the bits normally stored in the REX byte. */
4707 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2_X2
;
4708 i
.drex
.modrm_reg
= 1;
4709 i
.drex
.modrm_regmem
= 0;
4710 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4711 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4715 as_bad (_("Incorrect operands for the '%s' instruction"),
4719 /* SSE5 instructions with the DREX byte where the only memory operand
4720 is in the 2nd argument, and the first and last xmm register must
4721 match, and is encoded in the DREX byte. */
4722 else if (i
.tm
.opcode_modifier
.drex
4723 && !i
.tm
.opcode_modifier
.drexv
4726 /* Case 1: 4 operand insn, dest = src1, src3 = reg/mem. */
4727 if (i
.types
[0].bitfield
.regxmm
!= 0
4728 && (i
.types
[1].bitfield
.regxmm
4729 || operand_type_check(i
.types
[1], anymem
))
4730 && i
.types
[2].bitfield
.regxmm
!= 0
4731 && i
.types
[3].bitfield
.regxmm
!= 0
4732 && i
.op
[0].regs
->reg_num
== i
.op
[3].regs
->reg_num
4733 && i
.op
[0].regs
->reg_flags
== i
.op
[3].regs
->reg_flags
)
4735 /* clear the arguments that are stored in drex */
4736 operand_type_set (&i
.types
[0], 0);
4737 operand_type_set (&i
.types
[3], 0);
4738 i
.reg_operands
-= 2;
4740 /* Specify the modrm encoding and remember the register
4741 including the high bit normally stored in the REX
4743 i
.drex
.modrm_reg
= 2;
4744 i
.drex
.modrm_regmem
= 1;
4745 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4746 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4750 as_bad (_("Incorrect operands for the '%s' instruction"),
4754 /* SSE5 3 operand instructions that the result is a register, being
4755 either operand can be a memory operand, using OC0 to note which
4756 one is the memory. */
4757 else if (i
.tm
.opcode_modifier
.drex
4758 && i
.tm
.opcode_modifier
.drexv
4761 i
.tm
.extension_opcode
= None
;
4763 /* Case 1: 3 operand insn, src1 = register. */
4764 if (i
.types
[0].bitfield
.regxmm
!= 0
4765 && i
.types
[1].bitfield
.regxmm
!= 0
4766 && i
.types
[2].bitfield
.regxmm
!= 0)
4768 /* Clear the arguments that are stored in drex. */
4769 operand_type_set (&i
.types
[2], 0);
4772 /* Specify the modrm encoding and remember the register
4773 including the high bit normally stored in the REX byte. */
4774 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4775 i
.drex
.modrm_reg
= 1;
4776 i
.drex
.modrm_regmem
= 0;
4777 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4778 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4781 /* Case 2: 3 operand insn, src1 = memory. */
4782 else if (operand_type_check (i
.types
[0], anymem
) != 0
4783 && i
.types
[1].bitfield
.regxmm
!= 0
4784 && i
.types
[2].bitfield
.regxmm
!= 0)
4786 /* Clear the arguments that are stored in drex. */
4787 operand_type_set (&i
.types
[2], 0);
4790 /* Specify the modrm encoding and remember the register
4791 including the high bit normally stored in the REX
4793 i
.tm
.extension_opcode
= DREX_XMEM_X1_X2
;
4794 i
.drex
.modrm_reg
= 1;
4795 i
.drex
.modrm_regmem
= 0;
4796 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4797 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4800 /* Case 3: 3 operand insn, src2 = memory. */
4801 else if (i
.types
[0].bitfield
.regxmm
!= 0
4802 && operand_type_check (i
.types
[1], anymem
) != 0
4803 && i
.types
[2].bitfield
.regxmm
!= 0)
4805 /* Clear the arguments that are stored in drex. */
4806 operand_type_set (&i
.types
[2], 0);
4809 /* Specify the modrm encoding and remember the register
4810 including the high bit normally stored in the REX byte. */
4811 i
.tm
.extension_opcode
= DREX_X1_XMEM_X2
;
4812 i
.drex
.modrm_reg
= 0;
4813 i
.drex
.modrm_regmem
= 1;
4814 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4815 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4819 as_bad (_("Incorrect operands for the '%s' instruction"),
4823 /* SSE5 4 operand instructions that are the comparison instructions
4824 where the first operand is the immediate value of the comparison
4826 else if (i
.tm
.opcode_modifier
.drexc
!= 0 && i
.operands
== 4)
4828 /* Case 1: 4 operand insn, src1 = reg/memory. */
4829 if (operand_type_check (i
.types
[0], imm
) != 0
4830 && (i
.types
[1].bitfield
.regxmm
4831 || operand_type_check (i
.types
[1], anymem
))
4832 && i
.types
[2].bitfield
.regxmm
!= 0
4833 && i
.types
[3].bitfield
.regxmm
!= 0)
4835 /* clear the arguments that are stored in drex */
4836 operand_type_set (&i
.types
[3], 0);
4839 /* Specify the modrm encoding and remember the register
4840 including the high bit normally stored in the REX byte. */
4841 i
.drex
.modrm_reg
= 2;
4842 i
.drex
.modrm_regmem
= 1;
4843 i
.drex
.reg
= (i
.op
[3].regs
->reg_num
4844 + ((i
.op
[3].regs
->reg_flags
& RegRex
) ? 8 : 0));
4847 /* Case 2: 3 operand insn with ImmExt that places the
4848 opcode_extension as an immediate argument. This is used for
4849 all of the varients of comparison that supplies the appropriate
4850 value as part of the instruction. */
4851 else if ((i
.types
[0].bitfield
.regxmm
4852 || operand_type_check (i
.types
[0], anymem
))
4853 && i
.types
[1].bitfield
.regxmm
!= 0
4854 && i
.types
[2].bitfield
.regxmm
!= 0
4855 && operand_type_check (i
.types
[3], imm
) != 0)
4857 /* clear the arguments that are stored in drex */
4858 operand_type_set (&i
.types
[2], 0);
4861 /* Specify the modrm encoding and remember the register
4862 including the high bit normally stored in the REX byte. */
4863 i
.drex
.modrm_reg
= 1;
4864 i
.drex
.modrm_regmem
= 0;
4865 i
.drex
.reg
= (i
.op
[2].regs
->reg_num
4866 + ((i
.op
[2].regs
->reg_flags
& RegRex
) ? 8 : 0));
4870 as_bad (_("Incorrect operands for the '%s' instruction"),
4874 else if (i
.tm
.opcode_modifier
.drex
4875 || i
.tm
.opcode_modifier
.drexv
4876 || i
.tm
.opcode_modifier
.drexc
)
4877 as_bad (_("Internal error for the '%s' instruction"), i
.tm
.name
);
4881 bad_implicit_operand (int xmm
)
4883 const char *reg
= xmm
? "xmm0" : "ymm0";
4885 as_bad (_("the last operand of `%s' must be `%s%s'"),
4886 i
.tm
.name
, register_prefix
, reg
);
4888 as_bad (_("the first operand of `%s' must be `%s%s'"),
4889 i
.tm
.name
, register_prefix
, reg
);
4894 process_operands (void)
4896 /* Default segment register this instruction will use for memory
4897 accesses. 0 means unknown. This is only for optimizing out
4898 unnecessary segment overrides. */
4899 const seg_entry
*default_seg
= 0;
4901 /* Handle all of the DREX munging that SSE5 needs. */
4902 if (i
.tm
.opcode_modifier
.drex
4903 || i
.tm
.opcode_modifier
.drexv
4904 || i
.tm
.opcode_modifier
.drexc
)
4907 if (i
.tm
.opcode_modifier
.sse2avx
4908 && (i
.tm
.opcode_modifier
.vexnds
4909 || i
.tm
.opcode_modifier
.vexndd
))
4911 unsigned int dup
= i
.operands
;
4912 unsigned int dest
= dup
- 1;
4915 /* The destination must be an xmm register. */
4916 assert (i
.reg_operands
4917 && MAX_OPERANDS
> dup
4918 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4920 if (i
.tm
.opcode_modifier
.firstxmm0
)
4922 /* The first operand is implicit and must be xmm0. */
4923 assert (operand_type_equal (&i
.types
[0], ®xmm
));
4924 if (i
.op
[0].regs
->reg_num
!= 0)
4925 return bad_implicit_operand (1);
4927 if (i
.tm
.opcode_modifier
.vex3sources
)
4929 /* Keep xmm0 for instructions with VEX prefix and 3
4935 /* We remove the first xmm0 and keep the number of
4936 operands unchanged, which in fact duplicates the
4938 for (j
= 1; j
< i
.operands
; j
++)
4940 i
.op
[j
- 1] = i
.op
[j
];
4941 i
.types
[j
- 1] = i
.types
[j
];
4942 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4946 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4948 assert ((MAX_OPERANDS
- 1) > dup
4949 && i
.tm
.opcode_modifier
.vex3sources
);
4951 /* Add the implicit xmm0 for instructions with VEX prefix
4953 for (j
= i
.operands
; j
> 0; j
--)
4955 i
.op
[j
] = i
.op
[j
- 1];
4956 i
.types
[j
] = i
.types
[j
- 1];
4957 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4960 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4961 i
.types
[0] = regxmm
;
4962 i
.tm
.operand_types
[0] = regxmm
;
4965 i
.reg_operands
+= 2;
4970 i
.op
[dup
] = i
.op
[dest
];
4971 i
.types
[dup
] = i
.types
[dest
];
4972 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4981 i
.op
[dup
] = i
.op
[dest
];
4982 i
.types
[dup
] = i
.types
[dest
];
4983 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4986 if (i
.tm
.opcode_modifier
.immext
)
4989 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4993 /* The first operand is implicit and must be xmm0/ymm0. */
4994 assert (i
.reg_operands
4995 && (operand_type_equal (&i
.types
[0], ®xmm
)
4996 || operand_type_equal (&i
.types
[0], ®ymm
)));
4997 if (i
.op
[0].regs
->reg_num
!= 0)
4998 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
5000 for (j
= 1; j
< i
.operands
; j
++)
5002 i
.op
[j
- 1] = i
.op
[j
];
5003 i
.types
[j
- 1] = i
.types
[j
];
5005 /* We need to adjust fields in i.tm since they are used by
5006 build_modrm_byte. */
5007 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
5014 else if (i
.tm
.opcode_modifier
.regkludge
)
5016 /* The imul $imm, %reg instruction is converted into
5017 imul $imm, %reg, %reg, and the clr %reg instruction
5018 is converted into xor %reg, %reg. */
5020 unsigned int first_reg_op
;
5022 if (operand_type_check (i
.types
[0], reg
))
5026 /* Pretend we saw the extra register operand. */
5027 assert (i
.reg_operands
== 1
5028 && i
.op
[first_reg_op
+ 1].regs
== 0);
5029 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5030 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5035 if (i
.tm
.opcode_modifier
.shortform
)
5037 if (i
.types
[0].bitfield
.sreg2
5038 || i
.types
[0].bitfield
.sreg3
)
5040 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5041 && i
.op
[0].regs
->reg_num
== 1)
5043 as_bad (_("you can't `pop %scs'"), register_prefix
);
5046 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5047 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5052 /* The register or float register operand is in operand
5056 if (i
.types
[0].bitfield
.floatreg
5057 || operand_type_check (i
.types
[0], reg
))
5061 /* Register goes in low 3 bits of opcode. */
5062 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5063 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5065 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5067 /* Warn about some common errors, but press on regardless.
5068 The first case can be generated by gcc (<= 2.8.1). */
5069 if (i
.operands
== 2)
5071 /* Reversed arguments on faddp, fsubp, etc. */
5072 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5073 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5074 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5078 /* Extraneous `l' suffix on fp insn. */
5079 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5080 register_prefix
, i
.op
[0].regs
->reg_name
);
5085 else if (i
.tm
.opcode_modifier
.modrm
)
5087 /* The opcode is completed (modulo i.tm.extension_opcode which
5088 must be put into the modrm byte). Now, we make the modrm and
5089 index base bytes based on all the info we've collected. */
5091 default_seg
= build_modrm_byte ();
5093 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5097 else if (i
.tm
.opcode_modifier
.isstring
)
5099 /* For the string instructions that allow a segment override
5100 on one of their operands, the default segment is ds. */
5104 if (i
.tm
.base_opcode
== 0x8d /* lea */
5107 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5109 /* If a segment was explicitly specified, and the specified segment
5110 is not the default, use an opcode prefix to select it. If we
5111 never figured out what the default segment is, then default_seg
5112 will be zero at this point, and the specified segment prefix will
5114 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5116 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5122 static const seg_entry
*
5123 build_modrm_byte (void)
5125 const seg_entry
*default_seg
= 0;
5126 unsigned int source
, dest
;
5129 /* The first operand of instructions with VEX prefix and 3 sources
5130 must be VEX_Imm4. */
5131 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
5134 unsigned int nds
, reg
;
5136 dest
= i
.operands
- 1;
5141 /* This instruction must have 4 operands: 4 register operands
5142 or 3 register operands plus 1 memory operand. It must have
5143 VexNDS and VexImmExt. */
5144 assert (i
.operands
== 4
5145 && (i
.reg_operands
== 4
5146 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5147 && i
.tm
.opcode_modifier
.vexnds
5148 && i
.tm
.opcode_modifier
.veximmext
5149 && (operand_type_equal (&i
.tm
.operand_types
[dest
],
5151 || operand_type_equal (&i
.tm
.operand_types
[dest
],
5153 && (operand_type_equal (&i
.tm
.operand_types
[nds
],
5155 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5157 && (operand_type_equal (&i
.tm
.operand_types
[reg
],
5159 || operand_type_equal (&i
.tm
.operand_types
[reg
],
5162 /* Generate an 8bit immediate operand to encode the register
5164 expressionS
*exp
= &im_expressions
[i
.imm_operands
++];
5165 i
.op
[i
.operands
].imms
= exp
;
5166 i
.types
[i
.operands
] = imm8
;
5168 exp
->X_op
= O_constant
;
5170 = ((i
.op
[0].regs
->reg_num
5171 + ((i
.op
[0].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
5173 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5178 /* SSE5 4 operand instructions are encoded in such a way that one of
5179 the inputs must match the destination register. Process_drex hides
5180 the 3rd argument in the drex field, so that by the time we get
5181 here, it looks to GAS as if this is a 2 operand instruction. */
5182 if ((i
.tm
.opcode_modifier
.drex
5183 || i
.tm
.opcode_modifier
.drexv
5184 || i
.tm
.opcode_modifier
.drexc
)
5185 && i
.reg_operands
== 2)
5187 const reg_entry
*reg
= i
.op
[i
.drex
.modrm_reg
].regs
;
5188 const reg_entry
*regmem
= i
.op
[i
.drex
.modrm_regmem
].regs
;
5190 i
.rm
.reg
= reg
->reg_num
;
5191 i
.rm
.regmem
= regmem
->reg_num
;
5193 if ((reg
->reg_flags
& RegRex
) != 0)
5195 if ((regmem
->reg_flags
& RegRex
) != 0)
5199 /* i.reg_operands MUST be the number of real register operands;
5200 implicit registers do not count. If there are 3 register
5201 operands, it must be a instruction with VexNDS. For a
5202 instruction with VexNDD, the destination register is encoded
5203 in VEX prefix. If there are 4 register operands, it must be
5204 a instruction with VEX prefix and 3 sources. */
5205 else if (i
.mem_operands
== 0
5206 && ((i
.reg_operands
== 2
5207 && !i
.tm
.opcode_modifier
.vexndd
)
5208 || (i
.reg_operands
== 3
5209 && i
.tm
.opcode_modifier
.vexnds
)
5210 || (i
.reg_operands
== 4 && vex_3_sources
)))
5218 /* When there are 3 operands, one of them may be immediate,
5219 which may be the first or the last operand. Otherwise,
5220 the first operand must be shift count register (cl) or it
5221 is an instruction with VexNDS. */
5222 assert (i
.imm_operands
== 1
5223 || (i
.imm_operands
== 0
5224 && (i
.tm
.opcode_modifier
.vexnds
5225 || i
.types
[0].bitfield
.shiftcount
)));
5226 if (operand_type_check (i
.types
[0], imm
)
5227 || i
.types
[0].bitfield
.shiftcount
)
5233 /* When there are 4 operands, the first two must be 8bit
5234 immediate operands. The source operand will be the 3rd
5237 For instructions with VexNDS, if the first operand
5238 an imm8, the source operand is the 2nd one. If the last
5239 operand is imm8, the source operand is the first one. */
5240 assert ((i
.imm_operands
== 2
5241 && i
.types
[0].bitfield
.imm8
5242 && i
.types
[1].bitfield
.imm8
)
5243 || (i
.tm
.opcode_modifier
.vexnds
5244 && i
.imm_operands
== 1
5245 && (i
.types
[0].bitfield
.imm8
5246 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5247 if (i
.tm
.opcode_modifier
.vexnds
)
5249 if (i
.types
[0].bitfield
.imm8
)
5267 if (i
.tm
.opcode_modifier
.vexnds
)
5269 /* For instructions with VexNDS, the register-only
5270 source operand must be XMM or YMM register. It is
5271 encoded in VEX prefix. We need to clear RegMem bit
5272 before calling operand_type_equal. */
5273 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5274 op
.bitfield
.regmem
= 0;
5275 if ((dest
+ 1) >= i
.operands
5276 || (!operand_type_equal (&op
, ®xmm
)
5277 && !operand_type_equal (&op
, ®ymm
)))
5279 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5285 /* One of the register operands will be encoded in the i.tm.reg
5286 field, the other in the combined i.tm.mode and i.tm.regmem
5287 fields. If no form of this instruction supports a memory
5288 destination operand, then we assume the source operand may
5289 sometimes be a memory operand and so we need to store the
5290 destination in the i.rm.reg field. */
5291 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5292 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5294 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5295 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5296 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5298 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5303 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5304 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5305 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5307 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5310 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5312 if (!i
.types
[0].bitfield
.control
5313 && !i
.types
[1].bitfield
.control
)
5315 i
.rex
&= ~(REX_R
| REX_B
);
5316 add_prefix (LOCK_PREFIX_OPCODE
);
5320 { /* If it's not 2 reg operands... */
5325 unsigned int fake_zero_displacement
= 0;
5328 /* This has been precalculated for SSE5 instructions
5329 that have a DREX field earlier in process_drex. */
5330 if (i
.tm
.opcode_modifier
.drex
5331 || i
.tm
.opcode_modifier
.drexv
5332 || i
.tm
.opcode_modifier
.drexc
)
5333 op
= i
.drex
.modrm_regmem
;
5336 for (op
= 0; op
< i
.operands
; op
++)
5337 if (operand_type_check (i
.types
[op
], anymem
))
5339 assert (op
< i
.operands
);
5344 if (i
.base_reg
== 0)
5347 if (!i
.disp_operands
)
5348 fake_zero_displacement
= 1;
5349 if (i
.index_reg
== 0)
5351 /* Operand is just <disp> */
5352 if (flag_code
== CODE_64BIT
)
5354 /* 64bit mode overwrites the 32bit absolute
5355 addressing by RIP relative addressing and
5356 absolute addressing is encoded by one of the
5357 redundant SIB forms. */
5358 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5359 i
.sib
.base
= NO_BASE_REGISTER
;
5360 i
.sib
.index
= NO_INDEX_REGISTER
;
5361 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5362 ? disp32s
: disp32
);
5364 else if ((flag_code
== CODE_16BIT
)
5365 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5367 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5368 i
.types
[op
] = disp16
;
5372 i
.rm
.regmem
= NO_BASE_REGISTER
;
5373 i
.types
[op
] = disp32
;
5376 else /* !i.base_reg && i.index_reg */
5378 if (i
.index_reg
->reg_num
== RegEiz
5379 || i
.index_reg
->reg_num
== RegRiz
)
5380 i
.sib
.index
= NO_INDEX_REGISTER
;
5382 i
.sib
.index
= i
.index_reg
->reg_num
;
5383 i
.sib
.base
= NO_BASE_REGISTER
;
5384 i
.sib
.scale
= i
.log2_scale_factor
;
5385 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5386 i
.types
[op
].bitfield
.disp8
= 0;
5387 i
.types
[op
].bitfield
.disp16
= 0;
5388 i
.types
[op
].bitfield
.disp64
= 0;
5389 if (flag_code
!= CODE_64BIT
)
5391 /* Must be 32 bit */
5392 i
.types
[op
].bitfield
.disp32
= 1;
5393 i
.types
[op
].bitfield
.disp32s
= 0;
5397 i
.types
[op
].bitfield
.disp32
= 0;
5398 i
.types
[op
].bitfield
.disp32s
= 1;
5400 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5404 /* RIP addressing for 64bit mode. */
5405 else if (i
.base_reg
->reg_num
== RegRip
||
5406 i
.base_reg
->reg_num
== RegEip
)
5408 i
.rm
.regmem
= NO_BASE_REGISTER
;
5409 i
.types
[op
].bitfield
.disp8
= 0;
5410 i
.types
[op
].bitfield
.disp16
= 0;
5411 i
.types
[op
].bitfield
.disp32
= 0;
5412 i
.types
[op
].bitfield
.disp32s
= 1;
5413 i
.types
[op
].bitfield
.disp64
= 0;
5414 i
.flags
[op
] |= Operand_PCrel
;
5415 if (! i
.disp_operands
)
5416 fake_zero_displacement
= 1;
5418 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5420 switch (i
.base_reg
->reg_num
)
5423 if (i
.index_reg
== 0)
5425 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5426 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5430 if (i
.index_reg
== 0)
5433 if (operand_type_check (i
.types
[op
], disp
) == 0)
5435 /* fake (%bp) into 0(%bp) */
5436 i
.types
[op
].bitfield
.disp8
= 1;
5437 fake_zero_displacement
= 1;
5440 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5441 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5443 default: /* (%si) -> 4 or (%di) -> 5 */
5444 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5446 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5448 else /* i.base_reg and 32/64 bit mode */
5450 if (flag_code
== CODE_64BIT
5451 && operand_type_check (i
.types
[op
], disp
))
5453 i386_operand_type temp
;
5454 operand_type_set (&temp
, 0);
5455 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5457 if (i
.prefix
[ADDR_PREFIX
] == 0)
5458 i
.types
[op
].bitfield
.disp32s
= 1;
5460 i
.types
[op
].bitfield
.disp32
= 1;
5463 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5464 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5466 i
.sib
.base
= i
.base_reg
->reg_num
;
5467 /* x86-64 ignores REX prefix bit here to avoid decoder
5469 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5472 if (i
.disp_operands
== 0)
5474 fake_zero_displacement
= 1;
5475 i
.types
[op
].bitfield
.disp8
= 1;
5478 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5482 i
.sib
.scale
= i
.log2_scale_factor
;
5483 if (i
.index_reg
== 0)
5485 /* <disp>(%esp) becomes two byte modrm with no index
5486 register. We've already stored the code for esp
5487 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5488 Any base register besides %esp will not use the
5489 extra modrm byte. */
5490 i
.sib
.index
= NO_INDEX_REGISTER
;
5494 if (i
.index_reg
->reg_num
== RegEiz
5495 || i
.index_reg
->reg_num
== RegRiz
)
5496 i
.sib
.index
= NO_INDEX_REGISTER
;
5498 i
.sib
.index
= i
.index_reg
->reg_num
;
5499 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5500 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5505 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5506 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5509 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5512 if (fake_zero_displacement
)
5514 /* Fakes a zero displacement assuming that i.types[op]
5515 holds the correct displacement size. */
5518 assert (i
.op
[op
].disps
== 0);
5519 exp
= &disp_expressions
[i
.disp_operands
++];
5520 i
.op
[op
].disps
= exp
;
5521 exp
->X_op
= O_constant
;
5522 exp
->X_add_number
= 0;
5523 exp
->X_add_symbol
= (symbolS
*) 0;
5524 exp
->X_op_symbol
= (symbolS
*) 0;
5532 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5533 (if any) based on i.tm.extension_opcode. Again, we must be
5534 careful to make sure that segment/control/debug/test/MMX
5535 registers are coded into the i.rm.reg field. */
5540 /* This has been precalculated for SSE5 instructions
5541 that have a DREX field earlier in process_drex. */
5542 if (i
.tm
.opcode_modifier
.drex
5543 || i
.tm
.opcode_modifier
.drexv
5544 || i
.tm
.opcode_modifier
.drexc
)
5546 op
= i
.drex
.modrm_reg
;
5547 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5548 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5553 unsigned int vex_reg
= ~0;
5555 for (op
= 0; op
< i
.operands
; op
++)
5556 if (i
.types
[op
].bitfield
.reg8
5557 || i
.types
[op
].bitfield
.reg16
5558 || i
.types
[op
].bitfield
.reg32
5559 || i
.types
[op
].bitfield
.reg64
5560 || i
.types
[op
].bitfield
.regmmx
5561 || i
.types
[op
].bitfield
.regxmm
5562 || i
.types
[op
].bitfield
.regymm
5563 || i
.types
[op
].bitfield
.sreg2
5564 || i
.types
[op
].bitfield
.sreg3
5565 || i
.types
[op
].bitfield
.control
5566 || i
.types
[op
].bitfield
.debug
5567 || i
.types
[op
].bitfield
.test
)
5572 else if (i
.tm
.opcode_modifier
.vexnds
)
5574 /* For instructions with VexNDS, the register-only
5575 source operand is encoded in VEX prefix. */
5576 assert (mem
!= (unsigned int) ~0);
5581 assert (op
< i
.operands
);
5586 assert (vex_reg
< i
.operands
);
5589 else if (i
.tm
.opcode_modifier
.vexndd
)
5591 /* For instructions with VexNDD, there should be
5592 no memory operand and the register destination
5593 is encoded in VEX prefix. */
5594 assert (i
.mem_operands
== 0
5595 && (op
+ 2) == i
.operands
);
5599 assert (op
< i
.operands
);
5601 if (vex_reg
!= (unsigned int) ~0)
5603 assert (i
.reg_operands
== 2);
5605 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5607 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5610 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5613 /* If there is an extension opcode to put here, the
5614 register number must be put into the regmem field. */
5615 if (i
.tm
.extension_opcode
!= None
)
5617 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5618 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5623 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5624 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5629 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5630 must set it to 3 to indicate this is a register operand
5631 in the regmem field. */
5632 if (!i
.mem_operands
)
5636 /* Fill in i.rm.reg field with extension opcode (if any). */
5637 if (i
.tm
.extension_opcode
!= None
5638 && !(i
.tm
.opcode_modifier
.drex
5639 || i
.tm
.opcode_modifier
.drexv
5640 || i
.tm
.opcode_modifier
.drexc
))
5641 i
.rm
.reg
= i
.tm
.extension_opcode
;
5647 output_branch (void)
5652 relax_substateT subtype
;
5657 if (flag_code
== CODE_16BIT
)
5661 if (i
.prefix
[DATA_PREFIX
] != 0)
5667 /* Pentium4 branch hints. */
5668 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5669 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5674 if (i
.prefix
[REX_PREFIX
] != 0)
5680 if (i
.prefixes
!= 0 && !intel_syntax
)
5681 as_warn (_("skipping prefixes on this instruction"));
5683 /* It's always a symbol; End frag & setup for relax.
5684 Make sure there is enough room in this frag for the largest
5685 instruction we may generate in md_convert_frag. This is 2
5686 bytes for the opcode and room for the prefix and largest
5688 frag_grow (prefix
+ 2 + 4);
5689 /* Prefix and 1 opcode byte go in fr_fix. */
5690 p
= frag_more (prefix
+ 1);
5691 if (i
.prefix
[DATA_PREFIX
] != 0)
5692 *p
++ = DATA_PREFIX_OPCODE
;
5693 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5694 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5695 *p
++ = i
.prefix
[SEG_PREFIX
];
5696 if (i
.prefix
[REX_PREFIX
] != 0)
5697 *p
++ = i
.prefix
[REX_PREFIX
];
5698 *p
= i
.tm
.base_opcode
;
5700 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5701 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5702 else if (cpu_arch_flags
.bitfield
.cpui386
)
5703 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5705 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5708 sym
= i
.op
[0].disps
->X_add_symbol
;
5709 off
= i
.op
[0].disps
->X_add_number
;
5711 if (i
.op
[0].disps
->X_op
!= O_constant
5712 && i
.op
[0].disps
->X_op
!= O_symbol
)
5714 /* Handle complex expressions. */
5715 sym
= make_expr_symbol (i
.op
[0].disps
);
5719 /* 1 possible extra opcode + 4 byte displacement go in var part.
5720 Pass reloc in fr_var. */
5721 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5731 if (i
.tm
.opcode_modifier
.jumpbyte
)
5733 /* This is a loop or jecxz type instruction. */
5735 if (i
.prefix
[ADDR_PREFIX
] != 0)
5737 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5740 /* Pentium4 branch hints. */
5741 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5742 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5744 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5753 if (flag_code
== CODE_16BIT
)
5756 if (i
.prefix
[DATA_PREFIX
] != 0)
5758 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5768 if (i
.prefix
[REX_PREFIX
] != 0)
5770 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5774 if (i
.prefixes
!= 0 && !intel_syntax
)
5775 as_warn (_("skipping prefixes on this instruction"));
5777 p
= frag_more (1 + size
);
5778 *p
++ = i
.tm
.base_opcode
;
5780 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5781 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5783 /* All jumps handled here are signed, but don't use a signed limit
5784 check for 32 and 16 bit jumps as we want to allow wrap around at
5785 4G and 64k respectively. */
5787 fixP
->fx_signed
= 1;
5791 output_interseg_jump (void)
5799 if (flag_code
== CODE_16BIT
)
5803 if (i
.prefix
[DATA_PREFIX
] != 0)
5809 if (i
.prefix
[REX_PREFIX
] != 0)
5819 if (i
.prefixes
!= 0 && !intel_syntax
)
5820 as_warn (_("skipping prefixes on this instruction"));
5822 /* 1 opcode; 2 segment; offset */
5823 p
= frag_more (prefix
+ 1 + 2 + size
);
5825 if (i
.prefix
[DATA_PREFIX
] != 0)
5826 *p
++ = DATA_PREFIX_OPCODE
;
5828 if (i
.prefix
[REX_PREFIX
] != 0)
5829 *p
++ = i
.prefix
[REX_PREFIX
];
5831 *p
++ = i
.tm
.base_opcode
;
5832 if (i
.op
[1].imms
->X_op
== O_constant
)
5834 offsetT n
= i
.op
[1].imms
->X_add_number
;
5837 && !fits_in_unsigned_word (n
)
5838 && !fits_in_signed_word (n
))
5840 as_bad (_("16-bit jump out of range"));
5843 md_number_to_chars (p
, n
, size
);
5846 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5847 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5848 if (i
.op
[0].imms
->X_op
!= O_constant
)
5849 as_bad (_("can't handle non absolute segment in `%s'"),
5851 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5857 fragS
*insn_start_frag
;
5858 offsetT insn_start_off
;
5860 /* Tie dwarf2 debug info to the address at the start of the insn.
5861 We can't do this after the insn has been output as the current
5862 frag may have been closed off. eg. by frag_var. */
5863 dwarf2_emit_insn (0);
5865 insn_start_frag
= frag_now
;
5866 insn_start_off
= frag_now_fix ();
5869 if (i
.tm
.opcode_modifier
.jump
)
5871 else if (i
.tm
.opcode_modifier
.jumpbyte
5872 || i
.tm
.opcode_modifier
.jumpdword
)
5874 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5875 output_interseg_jump ();
5878 /* Output normal instructions here. */
5882 unsigned int prefix
;
5884 /* Since the VEX prefix contains the implicit prefix, we don't
5885 need the explicit prefix. */
5886 if (!i
.tm
.opcode_modifier
.vex
)
5888 switch (i
.tm
.opcode_length
)
5891 if (i
.tm
.base_opcode
& 0xff000000)
5893 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5898 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5900 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5901 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5904 if (prefix
!= REPE_PREFIX_OPCODE
5905 || (i
.prefix
[LOCKREP_PREFIX
]
5906 != REPE_PREFIX_OPCODE
))
5907 add_prefix (prefix
);
5910 add_prefix (prefix
);
5919 /* The prefix bytes. */
5920 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5922 FRAG_APPEND_1_CHAR (*q
);
5925 if (i
.tm
.opcode_modifier
.vex
)
5927 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5932 /* REX byte is encoded in VEX prefix. */
5936 FRAG_APPEND_1_CHAR (*q
);
5939 /* There should be no other prefixes for instructions
5944 /* Now the VEX prefix. */
5945 p
= frag_more (i
.vex
.length
);
5946 for (j
= 0; j
< i
.vex
.length
; j
++)
5947 p
[j
] = i
.vex
.bytes
[j
];
5950 /* Now the opcode; be careful about word order here! */
5951 if (i
.tm
.opcode_length
== 1)
5953 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5957 switch (i
.tm
.opcode_length
)
5961 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5971 /* Put out high byte first: can't use md_number_to_chars! */
5972 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5973 *p
= i
.tm
.base_opcode
& 0xff;
5975 /* On SSE5, encode the OC1 bit in the DREX field if this
5976 encoding has multiple formats. */
5977 if (i
.tm
.opcode_modifier
.drex
5978 && i
.tm
.opcode_modifier
.drexv
5979 && DREX_OC1 (i
.tm
.extension_opcode
))
5980 *p
|= DREX_OC1_MASK
;
5983 /* Now the modrm byte and sib byte (if present). */
5984 if (i
.tm
.opcode_modifier
.modrm
)
5986 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5989 /* If i.rm.regmem == ESP (4)
5990 && i.rm.mode != (Register mode)
5992 ==> need second modrm byte. */
5993 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5995 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5996 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5998 | i
.sib
.scale
<< 6));
6001 /* Write the DREX byte if needed. */
6002 if (i
.tm
.opcode_modifier
.drex
|| i
.tm
.opcode_modifier
.drexc
)
6005 *p
= (((i
.drex
.reg
& 0xf) << 4) | (i
.drex
.rex
& 0x7));
6007 /* Encode the OC0 bit if this encoding has multiple
6009 if ((i
.tm
.opcode_modifier
.drex
6010 || i
.tm
.opcode_modifier
.drexv
)
6011 && DREX_OC0 (i
.tm
.extension_opcode
))
6012 *p
|= DREX_OC0_MASK
;
6015 if (i
.disp_operands
)
6016 output_disp (insn_start_frag
, insn_start_off
);
6019 output_imm (insn_start_frag
, insn_start_off
);
6025 pi ("" /*line*/, &i
);
6027 #endif /* DEBUG386 */
6030 /* Return the size of the displacement operand N. */
6033 disp_size (unsigned int n
)
6036 if (i
.types
[n
].bitfield
.disp64
)
6038 else if (i
.types
[n
].bitfield
.disp8
)
6040 else if (i
.types
[n
].bitfield
.disp16
)
6045 /* Return the size of the immediate operand N. */
6048 imm_size (unsigned int n
)
6051 if (i
.types
[n
].bitfield
.imm64
)
6053 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6055 else if (i
.types
[n
].bitfield
.imm16
)
6061 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6066 for (n
= 0; n
< i
.operands
; n
++)
6068 if (operand_type_check (i
.types
[n
], disp
))
6070 if (i
.op
[n
].disps
->X_op
== O_constant
)
6072 int size
= disp_size (n
);
6075 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6077 p
= frag_more (size
);
6078 md_number_to_chars (p
, val
, size
);
6082 enum bfd_reloc_code_real reloc_type
;
6083 int size
= disp_size (n
);
6084 int sign
= i
.types
[n
].bitfield
.disp32s
;
6085 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6087 /* We can't have 8 bit displacement here. */
6088 assert (!i
.types
[n
].bitfield
.disp8
);
6090 /* The PC relative address is computed relative
6091 to the instruction boundary, so in case immediate
6092 fields follows, we need to adjust the value. */
6093 if (pcrel
&& i
.imm_operands
)
6098 for (n1
= 0; n1
< i
.operands
; n1
++)
6099 if (operand_type_check (i
.types
[n1
], imm
))
6101 /* Only one immediate is allowed for PC
6102 relative address. */
6105 i
.op
[n
].disps
->X_add_number
-= sz
;
6107 /* We should find the immediate. */
6111 p
= frag_more (size
);
6112 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6114 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6115 && (((reloc_type
== BFD_RELOC_32
6116 || reloc_type
== BFD_RELOC_X86_64_32S
6117 || (reloc_type
== BFD_RELOC_64
6119 && (i
.op
[n
].disps
->X_op
== O_symbol
6120 || (i
.op
[n
].disps
->X_op
== O_add
6121 && ((symbol_get_value_expression
6122 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6124 || reloc_type
== BFD_RELOC_32_PCREL
))
6128 if (insn_start_frag
== frag_now
)
6129 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6134 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6135 for (fr
= insn_start_frag
->fr_next
;
6136 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6138 add
+= p
- frag_now
->fr_literal
;
6143 reloc_type
= BFD_RELOC_386_GOTPC
;
6144 i
.op
[n
].imms
->X_add_number
+= add
;
6146 else if (reloc_type
== BFD_RELOC_64
)
6147 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6149 /* Don't do the adjustment for x86-64, as there
6150 the pcrel addressing is relative to the _next_
6151 insn, and that is taken care of in other code. */
6152 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6154 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6155 i
.op
[n
].disps
, pcrel
, reloc_type
);
6162 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6167 for (n
= 0; n
< i
.operands
; n
++)
6169 if (operand_type_check (i
.types
[n
], imm
))
6171 if (i
.op
[n
].imms
->X_op
== O_constant
)
6173 int size
= imm_size (n
);
6176 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6178 p
= frag_more (size
);
6179 md_number_to_chars (p
, val
, size
);
6183 /* Not absolute_section.
6184 Need a 32-bit fixup (don't support 8bit
6185 non-absolute imms). Try to support other
6187 enum bfd_reloc_code_real reloc_type
;
6188 int size
= imm_size (n
);
6191 if (i
.types
[n
].bitfield
.imm32s
6192 && (i
.suffix
== QWORD_MNEM_SUFFIX
6193 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6198 p
= frag_more (size
);
6199 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6201 /* This is tough to explain. We end up with this one if we
6202 * have operands that look like
6203 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6204 * obtain the absolute address of the GOT, and it is strongly
6205 * preferable from a performance point of view to avoid using
6206 * a runtime relocation for this. The actual sequence of
6207 * instructions often look something like:
6212 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6214 * The call and pop essentially return the absolute address
6215 * of the label .L66 and store it in %ebx. The linker itself
6216 * will ultimately change the first operand of the addl so
6217 * that %ebx points to the GOT, but to keep things simple, the
6218 * .o file must have this operand set so that it generates not
6219 * the absolute address of .L66, but the absolute address of
6220 * itself. This allows the linker itself simply treat a GOTPC
6221 * relocation as asking for a pcrel offset to the GOT to be
6222 * added in, and the addend of the relocation is stored in the
6223 * operand field for the instruction itself.
6225 * Our job here is to fix the operand so that it would add
6226 * the correct offset so that %ebx would point to itself. The
6227 * thing that is tricky is that .-.L66 will point to the
6228 * beginning of the instruction, so we need to further modify
6229 * the operand so that it will point to itself. There are
6230 * other cases where you have something like:
6232 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6234 * and here no correction would be required. Internally in
6235 * the assembler we treat operands of this form as not being
6236 * pcrel since the '.' is explicitly mentioned, and I wonder
6237 * whether it would simplify matters to do it this way. Who
6238 * knows. In earlier versions of the PIC patches, the
6239 * pcrel_adjust field was used to store the correction, but
6240 * since the expression is not pcrel, I felt it would be
6241 * confusing to do it this way. */
6243 if ((reloc_type
== BFD_RELOC_32
6244 || reloc_type
== BFD_RELOC_X86_64_32S
6245 || reloc_type
== BFD_RELOC_64
)
6247 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6248 && (i
.op
[n
].imms
->X_op
== O_symbol
6249 || (i
.op
[n
].imms
->X_op
== O_add
6250 && ((symbol_get_value_expression
6251 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6256 if (insn_start_frag
== frag_now
)
6257 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6262 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6263 for (fr
= insn_start_frag
->fr_next
;
6264 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6266 add
+= p
- frag_now
->fr_literal
;
6270 reloc_type
= BFD_RELOC_386_GOTPC
;
6272 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6274 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6275 i
.op
[n
].imms
->X_add_number
+= add
;
6277 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6278 i
.op
[n
].imms
, 0, reloc_type
);
6284 /* x86_cons_fix_new is called via the expression parsing code when a
6285 reloc is needed. We use this hook to get the correct .got reloc. */
6286 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6287 static int cons_sign
= -1;
6290 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6293 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6295 got_reloc
= NO_RELOC
;
6298 if (exp
->X_op
== O_secrel
)
6300 exp
->X_op
= O_symbol
;
6301 r
= BFD_RELOC_32_SECREL
;
6305 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6308 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6309 # define lex_got(reloc, adjust, types) NULL
6311 /* Parse operands of the form
6312 <symbol>@GOTOFF+<nnn>
6313 and similar .plt or .got references.
6315 If we find one, set up the correct relocation in RELOC and copy the
6316 input string, minus the `@GOTOFF' into a malloc'd buffer for
6317 parsing by the calling routine. Return this buffer, and if ADJUST
6318 is non-null set it to the length of the string we removed from the
6319 input line. Otherwise return NULL. */
6321 lex_got (enum bfd_reloc_code_real
*reloc
,
6323 i386_operand_type
*types
)
6325 /* Some of the relocations depend on the size of what field is to
6326 be relocated. But in our callers i386_immediate and i386_displacement
6327 we don't yet know the operand size (this will be set by insn
6328 matching). Hence we record the word32 relocation here,
6329 and adjust the reloc according to the real size in reloc(). */
6330 static const struct {
6332 const enum bfd_reloc_code_real rel
[2];
6333 const i386_operand_type types64
;
6336 BFD_RELOC_X86_64_PLTOFF64
},
6337 OPERAND_TYPE_IMM64
},
6338 { "PLT", { BFD_RELOC_386_PLT32
,
6339 BFD_RELOC_X86_64_PLT32
},
6340 OPERAND_TYPE_IMM32_32S_DISP32
},
6342 BFD_RELOC_X86_64_GOTPLT64
},
6343 OPERAND_TYPE_IMM64_DISP64
},
6344 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6345 BFD_RELOC_X86_64_GOTOFF64
},
6346 OPERAND_TYPE_IMM64_DISP64
},
6348 BFD_RELOC_X86_64_GOTPCREL
},
6349 OPERAND_TYPE_IMM32_32S_DISP32
},
6350 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6351 BFD_RELOC_X86_64_TLSGD
},
6352 OPERAND_TYPE_IMM32_32S_DISP32
},
6353 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6355 OPERAND_TYPE_NONE
},
6357 BFD_RELOC_X86_64_TLSLD
},
6358 OPERAND_TYPE_IMM32_32S_DISP32
},
6359 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6360 BFD_RELOC_X86_64_GOTTPOFF
},
6361 OPERAND_TYPE_IMM32_32S_DISP32
},
6362 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6363 BFD_RELOC_X86_64_TPOFF32
},
6364 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6365 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6367 OPERAND_TYPE_NONE
},
6368 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6369 BFD_RELOC_X86_64_DTPOFF32
},
6371 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6372 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6374 OPERAND_TYPE_NONE
},
6375 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6377 OPERAND_TYPE_NONE
},
6378 { "GOT", { BFD_RELOC_386_GOT32
,
6379 BFD_RELOC_X86_64_GOT32
},
6380 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6381 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6382 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6383 OPERAND_TYPE_IMM32_32S_DISP32
},
6384 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6385 BFD_RELOC_X86_64_TLSDESC_CALL
},
6386 OPERAND_TYPE_IMM32_32S_DISP32
},
6394 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6395 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6398 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6402 len
= strlen (gotrel
[j
].str
);
6403 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6405 if (gotrel
[j
].rel
[object_64bit
] != 0)
6408 char *tmpbuf
, *past_reloc
;
6410 *reloc
= gotrel
[j
].rel
[object_64bit
];
6416 if (flag_code
!= CODE_64BIT
)
6418 types
->bitfield
.imm32
= 1;
6419 types
->bitfield
.disp32
= 1;
6422 *types
= gotrel
[j
].types64
;
6425 if (GOT_symbol
== NULL
)
6426 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6428 /* The length of the first part of our input line. */
6429 first
= cp
- input_line_pointer
;
6431 /* The second part goes from after the reloc token until
6432 (and including) an end_of_line char or comma. */
6433 past_reloc
= cp
+ 1 + len
;
6435 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6437 second
= cp
+ 1 - past_reloc
;
6439 /* Allocate and copy string. The trailing NUL shouldn't
6440 be necessary, but be safe. */
6441 tmpbuf
= xmalloc (first
+ second
+ 2);
6442 memcpy (tmpbuf
, input_line_pointer
, first
);
6443 if (second
!= 0 && *past_reloc
!= ' ')
6444 /* Replace the relocation token with ' ', so that
6445 errors like foo@GOTOFF1 will be detected. */
6446 tmpbuf
[first
++] = ' ';
6447 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6448 tmpbuf
[first
+ second
] = '\0';
6452 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6453 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6458 /* Might be a symbol version string. Don't as_bad here. */
6463 x86_cons (expressionS
*exp
, int size
)
6465 intel_syntax
= -intel_syntax
;
6467 if (size
== 4 || (object_64bit
&& size
== 8))
6469 /* Handle @GOTOFF and the like in an expression. */
6471 char *gotfree_input_line
;
6474 save
= input_line_pointer
;
6475 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6476 if (gotfree_input_line
)
6477 input_line_pointer
= gotfree_input_line
;
6481 if (gotfree_input_line
)
6483 /* expression () has merrily parsed up to the end of line,
6484 or a comma - in the wrong buffer. Transfer how far
6485 input_line_pointer has moved to the right buffer. */
6486 input_line_pointer
= (save
6487 + (input_line_pointer
- gotfree_input_line
)
6489 free (gotfree_input_line
);
6490 if (exp
->X_op
== O_constant
6491 || exp
->X_op
== O_absent
6492 || exp
->X_op
== O_illegal
6493 || exp
->X_op
== O_register
6494 || exp
->X_op
== O_big
)
6496 char c
= *input_line_pointer
;
6497 *input_line_pointer
= 0;
6498 as_bad (_("missing or invalid expression `%s'"), save
);
6499 *input_line_pointer
= c
;
6506 intel_syntax
= -intel_syntax
;
6509 i386_intel_simplify (exp
);
6513 static void signed_cons (int size
)
6515 if (flag_code
== CODE_64BIT
)
6523 pe_directive_secrel (dummy
)
6524 int dummy ATTRIBUTE_UNUSED
;
6531 if (exp
.X_op
== O_symbol
)
6532 exp
.X_op
= O_secrel
;
6534 emit_expr (&exp
, 4);
6536 while (*input_line_pointer
++ == ',');
6538 input_line_pointer
--;
6539 demand_empty_rest_of_line ();
6544 i386_immediate (char *imm_start
)
6546 char *save_input_line_pointer
;
6547 char *gotfree_input_line
;
6550 i386_operand_type types
;
6552 operand_type_set (&types
, ~0);
6554 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6556 as_bad (_("at most %d immediate operands are allowed"),
6557 MAX_IMMEDIATE_OPERANDS
);
6561 exp
= &im_expressions
[i
.imm_operands
++];
6562 i
.op
[this_operand
].imms
= exp
;
6564 if (is_space_char (*imm_start
))
6567 save_input_line_pointer
= input_line_pointer
;
6568 input_line_pointer
= imm_start
;
6570 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6571 if (gotfree_input_line
)
6572 input_line_pointer
= gotfree_input_line
;
6574 exp_seg
= expression (exp
);
6577 if (*input_line_pointer
)
6578 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6580 input_line_pointer
= save_input_line_pointer
;
6581 if (gotfree_input_line
)
6583 free (gotfree_input_line
);
6585 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6586 exp
->X_op
= O_illegal
;
6589 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6593 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6594 i386_operand_type types
, const char *imm_start
)
6596 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6598 as_bad (_("missing or invalid immediate expression `%s'"),
6602 else if (exp
->X_op
== O_constant
)
6604 /* Size it properly later. */
6605 i
.types
[this_operand
].bitfield
.imm64
= 1;
6606 /* If BFD64, sign extend val. */
6607 if (!use_rela_relocations
6608 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6610 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6612 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6613 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6614 && exp_seg
!= absolute_section
6615 && exp_seg
!= text_section
6616 && exp_seg
!= data_section
6617 && exp_seg
!= bss_section
6618 && exp_seg
!= undefined_section
6619 && !bfd_is_com_section (exp_seg
))
6621 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6625 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6627 as_bad (_("illegal immediate register operand %s"), imm_start
);
6632 /* This is an address. The size of the address will be
6633 determined later, depending on destination register,
6634 suffix, or the default for the section. */
6635 i
.types
[this_operand
].bitfield
.imm8
= 1;
6636 i
.types
[this_operand
].bitfield
.imm16
= 1;
6637 i
.types
[this_operand
].bitfield
.imm32
= 1;
6638 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6639 i
.types
[this_operand
].bitfield
.imm64
= 1;
6640 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6648 i386_scale (char *scale
)
6651 char *save
= input_line_pointer
;
6653 input_line_pointer
= scale
;
6654 val
= get_absolute_expression ();
6659 i
.log2_scale_factor
= 0;
6662 i
.log2_scale_factor
= 1;
6665 i
.log2_scale_factor
= 2;
6668 i
.log2_scale_factor
= 3;
6672 char sep
= *input_line_pointer
;
6674 *input_line_pointer
= '\0';
6675 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6677 *input_line_pointer
= sep
;
6678 input_line_pointer
= save
;
6682 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6684 as_warn (_("scale factor of %d without an index register"),
6685 1 << i
.log2_scale_factor
);
6686 i
.log2_scale_factor
= 0;
6688 scale
= input_line_pointer
;
6689 input_line_pointer
= save
;
6694 i386_displacement (char *disp_start
, char *disp_end
)
6698 char *save_input_line_pointer
;
6699 char *gotfree_input_line
;
6701 i386_operand_type bigdisp
, types
= anydisp
;
6704 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6706 as_bad (_("at most %d displacement operands are allowed"),
6707 MAX_MEMORY_OPERANDS
);
6711 operand_type_set (&bigdisp
, 0);
6712 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6713 || (!current_templates
->start
->opcode_modifier
.jump
6714 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6716 bigdisp
.bitfield
.disp32
= 1;
6717 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6718 if (flag_code
== CODE_64BIT
)
6722 bigdisp
.bitfield
.disp32s
= 1;
6723 bigdisp
.bitfield
.disp64
= 1;
6726 else if ((flag_code
== CODE_16BIT
) ^ override
)
6728 bigdisp
.bitfield
.disp32
= 0;
6729 bigdisp
.bitfield
.disp16
= 1;
6734 /* For PC-relative branches, the width of the displacement
6735 is dependent upon data size, not address size. */
6736 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6737 if (flag_code
== CODE_64BIT
)
6739 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6740 bigdisp
.bitfield
.disp16
= 1;
6743 bigdisp
.bitfield
.disp32
= 1;
6744 bigdisp
.bitfield
.disp32s
= 1;
6750 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6752 : LONG_MNEM_SUFFIX
));
6753 bigdisp
.bitfield
.disp32
= 1;
6754 if ((flag_code
== CODE_16BIT
) ^ override
)
6756 bigdisp
.bitfield
.disp32
= 0;
6757 bigdisp
.bitfield
.disp16
= 1;
6761 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6764 exp
= &disp_expressions
[i
.disp_operands
];
6765 i
.op
[this_operand
].disps
= exp
;
6767 save_input_line_pointer
= input_line_pointer
;
6768 input_line_pointer
= disp_start
;
6769 END_STRING_AND_SAVE (disp_end
);
6771 #ifndef GCC_ASM_O_HACK
6772 #define GCC_ASM_O_HACK 0
6775 END_STRING_AND_SAVE (disp_end
+ 1);
6776 if (i
.types
[this_operand
].bitfield
.baseIndex
6777 && displacement_string_end
[-1] == '+')
6779 /* This hack is to avoid a warning when using the "o"
6780 constraint within gcc asm statements.
6783 #define _set_tssldt_desc(n,addr,limit,type) \
6784 __asm__ __volatile__ ( \
6786 "movw %w1,2+%0\n\t" \
6788 "movb %b1,4+%0\n\t" \
6789 "movb %4,5+%0\n\t" \
6790 "movb $0,6+%0\n\t" \
6791 "movb %h1,7+%0\n\t" \
6793 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6795 This works great except that the output assembler ends
6796 up looking a bit weird if it turns out that there is
6797 no offset. You end up producing code that looks like:
6810 So here we provide the missing zero. */
6812 *displacement_string_end
= '0';
6815 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6816 if (gotfree_input_line
)
6817 input_line_pointer
= gotfree_input_line
;
6819 exp_seg
= expression (exp
);
6822 if (*input_line_pointer
)
6823 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6825 RESTORE_END_STRING (disp_end
+ 1);
6827 input_line_pointer
= save_input_line_pointer
;
6828 if (gotfree_input_line
)
6830 free (gotfree_input_line
);
6832 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6833 exp
->X_op
= O_illegal
;
6836 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6838 RESTORE_END_STRING (disp_end
);
6844 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6845 i386_operand_type types
, const char *disp_start
)
6847 i386_operand_type bigdisp
;
6850 /* We do this to make sure that the section symbol is in
6851 the symbol table. We will ultimately change the relocation
6852 to be relative to the beginning of the section. */
6853 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6854 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6855 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6857 if (exp
->X_op
!= O_symbol
)
6860 if (S_IS_LOCAL (exp
->X_add_symbol
)
6861 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6862 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6863 exp
->X_op
= O_subtract
;
6864 exp
->X_op_symbol
= GOT_symbol
;
6865 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6866 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6867 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6868 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6870 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6873 else if (exp
->X_op
== O_absent
6874 || exp
->X_op
== O_illegal
6875 || exp
->X_op
== O_big
)
6878 as_bad (_("missing or invalid displacement expression `%s'"),
6883 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6884 else if (exp
->X_op
!= O_constant
6885 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6886 && exp_seg
!= absolute_section
6887 && exp_seg
!= text_section
6888 && exp_seg
!= data_section
6889 && exp_seg
!= bss_section
6890 && exp_seg
!= undefined_section
6891 && !bfd_is_com_section (exp_seg
))
6893 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6898 /* Check if this is a displacement only operand. */
6899 bigdisp
= i
.types
[this_operand
];
6900 bigdisp
.bitfield
.disp8
= 0;
6901 bigdisp
.bitfield
.disp16
= 0;
6902 bigdisp
.bitfield
.disp32
= 0;
6903 bigdisp
.bitfield
.disp32s
= 0;
6904 bigdisp
.bitfield
.disp64
= 0;
6905 if (operand_type_all_zero (&bigdisp
))
6906 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6912 /* Make sure the memory operand we've been dealt is valid.
6913 Return 1 on success, 0 on a failure. */
6916 i386_index_check (const char *operand_string
)
6919 const char *kind
= "base/index";
6920 #if INFER_ADDR_PREFIX
6926 if (current_templates
->start
->opcode_modifier
.isstring
6927 && !current_templates
->start
->opcode_modifier
.immext
6928 && (current_templates
->end
[-1].opcode_modifier
.isstring
6931 /* Memory operands of string insns are special in that they only allow
6932 a single register (rDI, rSI, or rBX) as their memory address. */
6933 unsigned int expected
;
6935 kind
= "string address";
6937 if (current_templates
->start
->opcode_modifier
.w
)
6939 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6941 if (!type
.bitfield
.baseindex
6942 || ((!i
.mem_operands
!= !intel_syntax
)
6943 && current_templates
->end
[-1].operand_types
[1]
6944 .bitfield
.baseindex
))
6945 type
= current_templates
->end
[-1].operand_types
[1];
6946 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6949 expected
= 3 /* rBX */;
6951 if (!i
.base_reg
|| i
.index_reg
6952 || operand_type_check (i
.types
[this_operand
], disp
))
6954 else if (!(flag_code
== CODE_64BIT
6955 ? i
.prefix
[ADDR_PREFIX
]
6956 ? i
.base_reg
->reg_type
.bitfield
.reg32
6957 : i
.base_reg
->reg_type
.bitfield
.reg64
6958 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6959 ? i
.base_reg
->reg_type
.bitfield
.reg32
6960 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6962 else if (i
.base_reg
->reg_num
!= expected
)
6969 for (j
= 0; j
< i386_regtab_size
; ++j
)
6970 if ((flag_code
== CODE_64BIT
6971 ? i
.prefix
[ADDR_PREFIX
]
6972 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6973 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6974 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6975 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6976 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6977 && i386_regtab
[j
].reg_num
== expected
)
6979 assert (j
< i386_regtab_size
);
6980 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6982 intel_syntax
? '[' : '(',
6984 i386_regtab
[j
].reg_name
,
6985 intel_syntax
? ']' : ')');
6989 else if (flag_code
== CODE_64BIT
)
6992 && ((i
.prefix
[ADDR_PREFIX
] == 0
6993 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6994 || (i
.prefix
[ADDR_PREFIX
]
6995 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6997 || i
.base_reg
->reg_num
!=
6998 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7000 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7001 || (i
.prefix
[ADDR_PREFIX
] == 0
7002 && i
.index_reg
->reg_num
!= RegRiz
7003 && !i
.index_reg
->reg_type
.bitfield
.reg64
7005 || (i
.prefix
[ADDR_PREFIX
]
7006 && i
.index_reg
->reg_num
!= RegEiz
7007 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7012 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7016 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7017 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7019 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7020 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7022 && i
.base_reg
->reg_num
< 6
7023 && i
.index_reg
->reg_num
>= 6
7024 && i
.log2_scale_factor
== 0))))
7031 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7033 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7034 && i
.index_reg
->reg_num
!= RegEiz
)
7035 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7041 #if INFER_ADDR_PREFIX
7042 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7044 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7046 /* Change the size of any displacement too. At most one of
7047 Disp16 or Disp32 is set.
7048 FIXME. There doesn't seem to be any real need for separate
7049 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7050 Removing them would probably clean up the code quite a lot. */
7051 if (flag_code
!= CODE_64BIT
7052 && (i
.types
[this_operand
].bitfield
.disp16
7053 || i
.types
[this_operand
].bitfield
.disp32
))
7054 i
.types
[this_operand
]
7055 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7060 as_bad (_("`%s' is not a valid %s expression"),
7065 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7067 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7068 ? flag_code
== CODE_32BIT
7077 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7081 i386_att_operand (char *operand_string
)
7085 char *op_string
= operand_string
;
7087 if (is_space_char (*op_string
))
7090 /* We check for an absolute prefix (differentiating,
7091 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7092 if (*op_string
== ABSOLUTE_PREFIX
)
7095 if (is_space_char (*op_string
))
7097 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7100 /* Check if operand is a register. */
7101 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7103 i386_operand_type temp
;
7105 /* Check for a segment override by searching for ':' after a
7106 segment register. */
7108 if (is_space_char (*op_string
))
7110 if (*op_string
== ':'
7111 && (r
->reg_type
.bitfield
.sreg2
7112 || r
->reg_type
.bitfield
.sreg3
))
7117 i
.seg
[i
.mem_operands
] = &es
;
7120 i
.seg
[i
.mem_operands
] = &cs
;
7123 i
.seg
[i
.mem_operands
] = &ss
;
7126 i
.seg
[i
.mem_operands
] = &ds
;
7129 i
.seg
[i
.mem_operands
] = &fs
;
7132 i
.seg
[i
.mem_operands
] = &gs
;
7136 /* Skip the ':' and whitespace. */
7138 if (is_space_char (*op_string
))
7141 if (!is_digit_char (*op_string
)
7142 && !is_identifier_char (*op_string
)
7143 && *op_string
!= '('
7144 && *op_string
!= ABSOLUTE_PREFIX
)
7146 as_bad (_("bad memory operand `%s'"), op_string
);
7149 /* Handle case of %es:*foo. */
7150 if (*op_string
== ABSOLUTE_PREFIX
)
7153 if (is_space_char (*op_string
))
7155 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7157 goto do_memory_reference
;
7161 as_bad (_("junk `%s' after register"), op_string
);
7165 temp
.bitfield
.baseindex
= 0;
7166 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7168 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7169 i
.op
[this_operand
].regs
= r
;
7172 else if (*op_string
== REGISTER_PREFIX
)
7174 as_bad (_("bad register name `%s'"), op_string
);
7177 else if (*op_string
== IMMEDIATE_PREFIX
)
7180 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7182 as_bad (_("immediate operand illegal with absolute jump"));
7185 if (!i386_immediate (op_string
))
7188 else if (is_digit_char (*op_string
)
7189 || is_identifier_char (*op_string
)
7190 || *op_string
== '(')
7192 /* This is a memory reference of some sort. */
7195 /* Start and end of displacement string expression (if found). */
7196 char *displacement_string_start
;
7197 char *displacement_string_end
;
7199 do_memory_reference
:
7200 if ((i
.mem_operands
== 1
7201 && !current_templates
->start
->opcode_modifier
.isstring
)
7202 || i
.mem_operands
== 2)
7204 as_bad (_("too many memory references for `%s'"),
7205 current_templates
->start
->name
);
7209 /* Check for base index form. We detect the base index form by
7210 looking for an ')' at the end of the operand, searching
7211 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7213 base_string
= op_string
+ strlen (op_string
);
7216 if (is_space_char (*base_string
))
7219 /* If we only have a displacement, set-up for it to be parsed later. */
7220 displacement_string_start
= op_string
;
7221 displacement_string_end
= base_string
+ 1;
7223 if (*base_string
== ')')
7226 unsigned int parens_balanced
= 1;
7227 /* We've already checked that the number of left & right ()'s are
7228 equal, so this loop will not be infinite. */
7232 if (*base_string
== ')')
7234 if (*base_string
== '(')
7237 while (parens_balanced
);
7239 temp_string
= base_string
;
7241 /* Skip past '(' and whitespace. */
7243 if (is_space_char (*base_string
))
7246 if (*base_string
== ','
7247 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7250 displacement_string_end
= temp_string
;
7252 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7256 base_string
= end_op
;
7257 if (is_space_char (*base_string
))
7261 /* There may be an index reg or scale factor here. */
7262 if (*base_string
== ',')
7265 if (is_space_char (*base_string
))
7268 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7271 base_string
= end_op
;
7272 if (is_space_char (*base_string
))
7274 if (*base_string
== ',')
7277 if (is_space_char (*base_string
))
7280 else if (*base_string
!= ')')
7282 as_bad (_("expecting `,' or `)' "
7283 "after index register in `%s'"),
7288 else if (*base_string
== REGISTER_PREFIX
)
7290 as_bad (_("bad register name `%s'"), base_string
);
7294 /* Check for scale factor. */
7295 if (*base_string
!= ')')
7297 char *end_scale
= i386_scale (base_string
);
7302 base_string
= end_scale
;
7303 if (is_space_char (*base_string
))
7305 if (*base_string
!= ')')
7307 as_bad (_("expecting `)' "
7308 "after scale factor in `%s'"),
7313 else if (!i
.index_reg
)
7315 as_bad (_("expecting index register or scale factor "
7316 "after `,'; got '%c'"),
7321 else if (*base_string
!= ')')
7323 as_bad (_("expecting `,' or `)' "
7324 "after base register in `%s'"),
7329 else if (*base_string
== REGISTER_PREFIX
)
7331 as_bad (_("bad register name `%s'"), base_string
);
7336 /* If there's an expression beginning the operand, parse it,
7337 assuming displacement_string_start and
7338 displacement_string_end are meaningful. */
7339 if (displacement_string_start
!= displacement_string_end
)
7341 if (!i386_displacement (displacement_string_start
,
7342 displacement_string_end
))
7346 /* Special case for (%dx) while doing input/output op. */
7348 && operand_type_equal (&i
.base_reg
->reg_type
,
7349 ®16_inoutportreg
)
7351 && i
.log2_scale_factor
== 0
7352 && i
.seg
[i
.mem_operands
] == 0
7353 && !operand_type_check (i
.types
[this_operand
], disp
))
7355 i
.types
[this_operand
] = inoutportreg
;
7359 if (i386_index_check (operand_string
) == 0)
7361 i
.types
[this_operand
].bitfield
.mem
= 1;
7366 /* It's not a memory operand; argh! */
7367 as_bad (_("invalid char %s beginning operand %d `%s'"),
7368 output_invalid (*op_string
),
7373 return 1; /* Normal return. */
7376 /* md_estimate_size_before_relax()
7378 Called just before relax() for rs_machine_dependent frags. The x86
7379 assembler uses these frags to handle variable size jump
7382 Any symbol that is now undefined will not become defined.
7383 Return the correct fr_subtype in the frag.
7384 Return the initial "guess for variable size of frag" to caller.
7385 The guess is actually the growth beyond the fixed part. Whatever
7386 we do to grow the fixed or variable part contributes to our
7390 md_estimate_size_before_relax (fragP
, segment
)
7394 /* We've already got fragP->fr_subtype right; all we have to do is
7395 check for un-relaxable symbols. On an ELF system, we can't relax
7396 an externally visible symbol, because it may be overridden by a
7398 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7399 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7401 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7402 || S_IS_WEAK (fragP
->fr_symbol
)))
7406 /* Symbol is undefined in this segment, or we need to keep a
7407 reloc so that weak symbols can be overridden. */
7408 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7409 enum bfd_reloc_code_real reloc_type
;
7410 unsigned char *opcode
;
7413 if (fragP
->fr_var
!= NO_RELOC
)
7414 reloc_type
= fragP
->fr_var
;
7416 reloc_type
= BFD_RELOC_16_PCREL
;
7418 reloc_type
= BFD_RELOC_32_PCREL
;
7420 old_fr_fix
= fragP
->fr_fix
;
7421 opcode
= (unsigned char *) fragP
->fr_opcode
;
7423 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7426 /* Make jmp (0xeb) a (d)word displacement jump. */
7428 fragP
->fr_fix
+= size
;
7429 fix_new (fragP
, old_fr_fix
, size
,
7431 fragP
->fr_offset
, 1,
7437 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7439 /* Negate the condition, and branch past an
7440 unconditional jump. */
7443 /* Insert an unconditional jump. */
7445 /* We added two extra opcode bytes, and have a two byte
7447 fragP
->fr_fix
+= 2 + 2;
7448 fix_new (fragP
, old_fr_fix
+ 2, 2,
7450 fragP
->fr_offset
, 1,
7457 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7462 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7464 fragP
->fr_offset
, 1,
7466 fixP
->fx_signed
= 1;
7470 /* This changes the byte-displacement jump 0x7N
7471 to the (d)word-displacement jump 0x0f,0x8N. */
7472 opcode
[1] = opcode
[0] + 0x10;
7473 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7474 /* We've added an opcode byte. */
7475 fragP
->fr_fix
+= 1 + size
;
7476 fix_new (fragP
, old_fr_fix
+ 1, size
,
7478 fragP
->fr_offset
, 1,
7483 BAD_CASE (fragP
->fr_subtype
);
7487 return fragP
->fr_fix
- old_fr_fix
;
7490 /* Guess size depending on current relax state. Initially the relax
7491 state will correspond to a short jump and we return 1, because
7492 the variable part of the frag (the branch offset) is one byte
7493 long. However, we can relax a section more than once and in that
7494 case we must either set fr_subtype back to the unrelaxed state,
7495 or return the value for the appropriate branch. */
7496 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7499 /* Called after relax() is finished.
7501 In: Address of frag.
7502 fr_type == rs_machine_dependent.
7503 fr_subtype is what the address relaxed to.
7505 Out: Any fixSs and constants are set up.
7506 Caller will turn frag into a ".space 0". */
7509 md_convert_frag (abfd
, sec
, fragP
)
7510 bfd
*abfd ATTRIBUTE_UNUSED
;
7511 segT sec ATTRIBUTE_UNUSED
;
7514 unsigned char *opcode
;
7515 unsigned char *where_to_put_displacement
= NULL
;
7516 offsetT target_address
;
7517 offsetT opcode_address
;
7518 unsigned int extension
= 0;
7519 offsetT displacement_from_opcode_start
;
7521 opcode
= (unsigned char *) fragP
->fr_opcode
;
7523 /* Address we want to reach in file space. */
7524 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7526 /* Address opcode resides at in file space. */
7527 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7529 /* Displacement from opcode start to fill into instruction. */
7530 displacement_from_opcode_start
= target_address
- opcode_address
;
7532 if ((fragP
->fr_subtype
& BIG
) == 0)
7534 /* Don't have to change opcode. */
7535 extension
= 1; /* 1 opcode + 1 displacement */
7536 where_to_put_displacement
= &opcode
[1];
7540 if (no_cond_jump_promotion
7541 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7542 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7543 _("long jump required"));
7545 switch (fragP
->fr_subtype
)
7547 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7548 extension
= 4; /* 1 opcode + 4 displacement */
7550 where_to_put_displacement
= &opcode
[1];
7553 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7554 extension
= 2; /* 1 opcode + 2 displacement */
7556 where_to_put_displacement
= &opcode
[1];
7559 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7560 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7561 extension
= 5; /* 2 opcode + 4 displacement */
7562 opcode
[1] = opcode
[0] + 0x10;
7563 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7564 where_to_put_displacement
= &opcode
[2];
7567 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7568 extension
= 3; /* 2 opcode + 2 displacement */
7569 opcode
[1] = opcode
[0] + 0x10;
7570 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7571 where_to_put_displacement
= &opcode
[2];
7574 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7579 where_to_put_displacement
= &opcode
[3];
7583 BAD_CASE (fragP
->fr_subtype
);
7588 /* If size if less then four we are sure that the operand fits,
7589 but if it's 4, then it could be that the displacement is larger
7591 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7593 && ((addressT
) (displacement_from_opcode_start
- extension
7594 + ((addressT
) 1 << 31))
7595 > (((addressT
) 2 << 31) - 1)))
7597 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7598 _("jump target out of range"));
7599 /* Make us emit 0. */
7600 displacement_from_opcode_start
= extension
;
7602 /* Now put displacement after opcode. */
7603 md_number_to_chars ((char *) where_to_put_displacement
,
7604 (valueT
) (displacement_from_opcode_start
- extension
),
7605 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7606 fragP
->fr_fix
+= extension
;
7609 /* Apply a fixup (fixS) to segment data, once it has been determined
7610 by our caller that we have all the info we need to fix it up.
7612 On the 386, immediates, displacements, and data pointers are all in
7613 the same (little-endian) format, so we don't need to care about which
7617 md_apply_fix (fixP
, valP
, seg
)
7618 /* The fix we're to put in. */
7620 /* Pointer to the value of the bits. */
7622 /* Segment fix is from. */
7623 segT seg ATTRIBUTE_UNUSED
;
7625 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7626 valueT value
= *valP
;
7628 #if !defined (TE_Mach)
7631 switch (fixP
->fx_r_type
)
7637 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7640 case BFD_RELOC_X86_64_32S
:
7641 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7644 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7647 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7652 if (fixP
->fx_addsy
!= NULL
7653 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7654 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7655 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7656 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7657 && !use_rela_relocations
)
7659 /* This is a hack. There should be a better way to handle this.
7660 This covers for the fact that bfd_install_relocation will
7661 subtract the current location (for partial_inplace, PC relative
7662 relocations); see more below. */
7666 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7669 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7671 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7674 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7677 || (symbol_section_p (fixP
->fx_addsy
)
7678 && sym_seg
!= absolute_section
))
7679 && !generic_force_reloc (fixP
))
7681 /* Yes, we add the values in twice. This is because
7682 bfd_install_relocation subtracts them out again. I think
7683 bfd_install_relocation is broken, but I don't dare change
7685 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7689 #if defined (OBJ_COFF) && defined (TE_PE)
7690 /* For some reason, the PE format does not store a
7691 section address offset for a PC relative symbol. */
7692 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7693 || S_IS_WEAK (fixP
->fx_addsy
))
7694 value
+= md_pcrel_from (fixP
);
7698 /* Fix a few things - the dynamic linker expects certain values here,
7699 and we must not disappoint it. */
7700 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7701 if (IS_ELF
&& fixP
->fx_addsy
)
7702 switch (fixP
->fx_r_type
)
7704 case BFD_RELOC_386_PLT32
:
7705 case BFD_RELOC_X86_64_PLT32
:
7706 /* Make the jump instruction point to the address of the operand. At
7707 runtime we merely add the offset to the actual PLT entry. */
7711 case BFD_RELOC_386_TLS_GD
:
7712 case BFD_RELOC_386_TLS_LDM
:
7713 case BFD_RELOC_386_TLS_IE_32
:
7714 case BFD_RELOC_386_TLS_IE
:
7715 case BFD_RELOC_386_TLS_GOTIE
:
7716 case BFD_RELOC_386_TLS_GOTDESC
:
7717 case BFD_RELOC_X86_64_TLSGD
:
7718 case BFD_RELOC_X86_64_TLSLD
:
7719 case BFD_RELOC_X86_64_GOTTPOFF
:
7720 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7721 value
= 0; /* Fully resolved at runtime. No addend. */
7723 case BFD_RELOC_386_TLS_LE
:
7724 case BFD_RELOC_386_TLS_LDO_32
:
7725 case BFD_RELOC_386_TLS_LE_32
:
7726 case BFD_RELOC_X86_64_DTPOFF32
:
7727 case BFD_RELOC_X86_64_DTPOFF64
:
7728 case BFD_RELOC_X86_64_TPOFF32
:
7729 case BFD_RELOC_X86_64_TPOFF64
:
7730 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7733 case BFD_RELOC_386_TLS_DESC_CALL
:
7734 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7735 value
= 0; /* Fully resolved at runtime. No addend. */
7736 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7740 case BFD_RELOC_386_GOT32
:
7741 case BFD_RELOC_X86_64_GOT32
:
7742 value
= 0; /* Fully resolved at runtime. No addend. */
7745 case BFD_RELOC_VTABLE_INHERIT
:
7746 case BFD_RELOC_VTABLE_ENTRY
:
7753 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7755 #endif /* !defined (TE_Mach) */
7757 /* Are we finished with this relocation now? */
7758 if (fixP
->fx_addsy
== NULL
)
7760 else if (use_rela_relocations
)
7762 fixP
->fx_no_overflow
= 1;
7763 /* Remember value for tc_gen_reloc. */
7764 fixP
->fx_addnumber
= value
;
7768 md_number_to_chars (p
, value
, fixP
->fx_size
);
7772 md_atof (int type
, char *litP
, int *sizeP
)
7774 /* This outputs the LITTLENUMs in REVERSE order;
7775 in accord with the bigendian 386. */
7776 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7779 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7782 output_invalid (int c
)
7785 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7788 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7789 "(0x%x)", (unsigned char) c
);
7790 return output_invalid_buf
;
7793 /* REG_STRING starts *before* REGISTER_PREFIX. */
7795 static const reg_entry
*
7796 parse_real_register (char *reg_string
, char **end_op
)
7798 char *s
= reg_string
;
7800 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7803 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7804 if (*s
== REGISTER_PREFIX
)
7807 if (is_space_char (*s
))
7811 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7813 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7814 return (const reg_entry
*) NULL
;
7818 /* For naked regs, make sure that we are not dealing with an identifier.
7819 This prevents confusing an identifier like `eax_var' with register
7821 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7822 return (const reg_entry
*) NULL
;
7826 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7828 /* Handle floating point regs, allowing spaces in the (i) part. */
7829 if (r
== i386_regtab
/* %st is first entry of table */)
7831 if (is_space_char (*s
))
7836 if (is_space_char (*s
))
7838 if (*s
>= '0' && *s
<= '7')
7842 if (is_space_char (*s
))
7847 r
= hash_find (reg_hash
, "st(0)");
7852 /* We have "%st(" then garbage. */
7853 return (const reg_entry
*) NULL
;
7857 if (r
== NULL
|| allow_pseudo_reg
)
7860 if (operand_type_all_zero (&r
->reg_type
))
7861 return (const reg_entry
*) NULL
;
7863 if ((r
->reg_type
.bitfield
.reg32
7864 || r
->reg_type
.bitfield
.sreg3
7865 || r
->reg_type
.bitfield
.control
7866 || r
->reg_type
.bitfield
.debug
7867 || r
->reg_type
.bitfield
.test
)
7868 && !cpu_arch_flags
.bitfield
.cpui386
)
7869 return (const reg_entry
*) NULL
;
7871 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7872 return (const reg_entry
*) NULL
;
7874 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7875 return (const reg_entry
*) NULL
;
7877 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7878 return (const reg_entry
*) NULL
;
7880 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7881 if (!allow_index_reg
7882 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7883 return (const reg_entry
*) NULL
;
7885 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7886 || r
->reg_type
.bitfield
.reg64
)
7887 && (!cpu_arch_flags
.bitfield
.cpulm
7888 || !operand_type_equal (&r
->reg_type
, &control
))
7889 && flag_code
!= CODE_64BIT
)
7890 return (const reg_entry
*) NULL
;
7892 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7893 return (const reg_entry
*) NULL
;
7898 /* REG_STRING starts *before* REGISTER_PREFIX. */
7900 static const reg_entry
*
7901 parse_register (char *reg_string
, char **end_op
)
7905 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7906 r
= parse_real_register (reg_string
, end_op
);
7911 char *save
= input_line_pointer
;
7915 input_line_pointer
= reg_string
;
7916 c
= get_symbol_end ();
7917 symbolP
= symbol_find (reg_string
);
7918 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7920 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7922 know (e
->X_op
== O_register
);
7923 know (e
->X_add_number
>= 0
7924 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7925 r
= i386_regtab
+ e
->X_add_number
;
7926 *end_op
= input_line_pointer
;
7928 *input_line_pointer
= c
;
7929 input_line_pointer
= save
;
7935 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7938 char *end
= input_line_pointer
;
7941 r
= parse_register (name
, &input_line_pointer
);
7942 if (r
&& end
<= input_line_pointer
)
7944 *nextcharP
= *input_line_pointer
;
7945 *input_line_pointer
= 0;
7946 e
->X_op
= O_register
;
7947 e
->X_add_number
= r
- i386_regtab
;
7950 input_line_pointer
= end
;
7952 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7956 md_operand (expressionS
*e
)
7961 switch (*input_line_pointer
)
7963 case REGISTER_PREFIX
:
7964 r
= parse_real_register (input_line_pointer
, &end
);
7967 e
->X_op
= O_register
;
7968 e
->X_add_number
= r
- i386_regtab
;
7969 input_line_pointer
= end
;
7974 assert (intel_syntax
);
7975 end
= input_line_pointer
++;
7977 if (*input_line_pointer
== ']')
7979 ++input_line_pointer
;
7980 e
->X_op_symbol
= make_expr_symbol (e
);
7981 e
->X_add_symbol
= NULL
;
7982 e
->X_add_number
= 0;
7988 input_line_pointer
= end
;
7995 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7996 const char *md_shortopts
= "kVQ:sqn";
7998 const char *md_shortopts
= "qn";
8001 #define OPTION_32 (OPTION_MD_BASE + 0)
8002 #define OPTION_64 (OPTION_MD_BASE + 1)
8003 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8004 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8005 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8006 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8007 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8008 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8009 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8010 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8011 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8012 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8014 struct option md_longopts
[] =
8016 {"32", no_argument
, NULL
, OPTION_32
},
8017 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8018 {"64", no_argument
, NULL
, OPTION_64
},
8020 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8021 {"march", required_argument
, NULL
, OPTION_MARCH
},
8022 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8023 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8024 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8025 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8026 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8027 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8028 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8029 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8030 {NULL
, no_argument
, NULL
, 0}
8032 size_t md_longopts_size
= sizeof (md_longopts
);
8035 md_parse_option (int c
, char *arg
)
8043 optimize_align_code
= 0;
8050 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8051 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8052 should be emitted or not. FIXME: Not implemented. */
8056 /* -V: SVR4 argument to print version ID. */
8058 print_version_id ();
8061 /* -k: Ignore for FreeBSD compatibility. */
8066 /* -s: On i386 Solaris, this tells the native assembler to use
8067 .stab instead of .stab.excl. We always use .stab anyhow. */
8070 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8073 const char **list
, **l
;
8075 list
= bfd_target_list ();
8076 for (l
= list
; *l
!= NULL
; l
++)
8077 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8078 || strcmp (*l
, "coff-x86-64") == 0
8079 || strcmp (*l
, "pe-x86-64") == 0
8080 || strcmp (*l
, "pei-x86-64") == 0)
8082 default_arch
= "x86_64";
8086 as_fatal (_("No compiled in support for x86_64"));
8093 default_arch
= "i386";
8097 #ifdef SVR4_COMMENT_CHARS
8102 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8104 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8108 i386_comment_chars
= n
;
8114 arch
= xstrdup (arg
);
8118 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8119 next
= strchr (arch
, '+');
8122 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8124 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
8127 cpu_arch_name
= cpu_arch
[i
].name
;
8128 cpu_sub_arch_name
= NULL
;
8129 cpu_arch_flags
= cpu_arch
[i
].flags
;
8130 cpu_arch_isa
= cpu_arch
[i
].type
;
8131 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
8132 if (!cpu_arch_tune_set
)
8134 cpu_arch_tune
= cpu_arch_isa
;
8135 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8139 else if (*cpu_arch
[i
].name
== '.'
8140 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
8142 /* ISA entension. */
8143 i386_cpu_flags flags
;
8144 flags
= cpu_flags_or (cpu_arch_flags
,
8146 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8148 if (cpu_sub_arch_name
)
8150 char *name
= cpu_sub_arch_name
;
8151 cpu_sub_arch_name
= concat (name
,
8153 (const char *) NULL
);
8157 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
8158 cpu_arch_flags
= flags
;
8164 if (i
>= ARRAY_SIZE (cpu_arch
))
8165 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8169 while (next
!= NULL
);
8174 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8175 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
8177 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
8179 cpu_arch_tune_set
= 1;
8180 cpu_arch_tune
= cpu_arch
[i
].type
;
8181 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
8185 if (i
>= ARRAY_SIZE (cpu_arch
))
8186 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8189 case OPTION_MMNEMONIC
:
8190 if (strcasecmp (arg
, "att") == 0)
8192 else if (strcasecmp (arg
, "intel") == 0)
8195 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8198 case OPTION_MSYNTAX
:
8199 if (strcasecmp (arg
, "att") == 0)
8201 else if (strcasecmp (arg
, "intel") == 0)
8204 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8207 case OPTION_MINDEX_REG
:
8208 allow_index_reg
= 1;
8211 case OPTION_MNAKED_REG
:
8212 allow_naked_reg
= 1;
8215 case OPTION_MOLD_GCC
:
8219 case OPTION_MSSE2AVX
:
8223 case OPTION_MSSE_CHECK
:
8224 if (strcasecmp (arg
, "error") == 0)
8225 sse_check
= sse_check_error
;
8226 else if (strcasecmp (arg
, "warning") == 0)
8227 sse_check
= sse_check_warning
;
8228 else if (strcasecmp (arg
, "none") == 0)
8229 sse_check
= sse_check_none
;
8231 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8241 md_show_usage (stream
)
8244 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8245 fprintf (stream
, _("\
8247 -V print assembler version number\n\
8250 fprintf (stream
, _("\
8251 -n Do not optimize code alignment\n\
8252 -q quieten some warnings\n"));
8253 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8254 fprintf (stream
, _("\
8257 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined(TE_PEP)
8258 fprintf (stream
, _("\
8259 --32/--64 generate 32bit/64bit code\n"));
8261 #ifdef SVR4_COMMENT_CHARS
8262 fprintf (stream
, _("\
8263 --divide do not treat `/' as a comment character\n"));
8265 fprintf (stream
, _("\
8266 --divide ignored\n"));
8268 fprintf (stream
, _("\
8269 -march=CPU[,+EXTENSION...]\n\
8270 generate code for CPU and EXTENSION, CPU is one of:\n\
8271 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8272 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8273 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8274 generic32, generic64\n\
8275 EXTENSION is combination of:\n\
8276 mmx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4,\n\
8277 avx, vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8278 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8279 sse5, svme, abm, padlock\n"));
8280 fprintf (stream
, _("\
8281 -mtune=CPU optimize for CPU, CPU is one of:\n\
8282 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8283 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8284 core, core2, corei7, k6, k6_2, athlon, k8, amdfam10,\n\
8285 generic32, generic64\n"));
8286 fprintf (stream
, _("\
8287 -msse2avx encode SSE instructions with VEX prefix\n"));
8288 fprintf (stream
, _("\
8289 -msse-check=[none|error|warning]\n\
8290 check SSE instructions\n"));
8291 fprintf (stream
, _("\
8292 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8293 fprintf (stream
, _("\
8294 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8295 fprintf (stream
, _("\
8296 -mindex-reg support pseudo index registers\n"));
8297 fprintf (stream
, _("\
8298 -mnaked-reg don't require `%%' prefix for registers\n"));
8299 fprintf (stream
, _("\
8300 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8303 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8304 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) || defined (TE_PEP))
8306 /* Pick the target format to use. */
8309 i386_target_format (void)
8311 if (!strcmp (default_arch
, "x86_64"))
8313 set_code_flag (CODE_64BIT
);
8314 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8316 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8317 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8318 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8319 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8320 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8321 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8322 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8323 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8324 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8325 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8327 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8329 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8330 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8331 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8332 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8333 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8334 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8335 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8336 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8337 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8338 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8341 else if (!strcmp (default_arch
, "i386"))
8343 set_code_flag (CODE_32BIT
);
8344 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8346 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8347 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8348 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8350 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8352 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8353 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8354 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8358 as_fatal (_("Unknown architecture"));
8359 switch (OUTPUT_FLAVOR
)
8362 case bfd_target_coff_flavour
:
8363 return flag_code
== CODE_64BIT
? COFF_TARGET_FORMAT
: "pe-i386";
8366 #ifdef OBJ_MAYBE_AOUT
8367 case bfd_target_aout_flavour
:
8368 return AOUT_TARGET_FORMAT
;
8370 #ifdef OBJ_MAYBE_COFF
8371 case bfd_target_coff_flavour
:
8374 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8375 case bfd_target_elf_flavour
:
8377 if (flag_code
== CODE_64BIT
)
8380 use_rela_relocations
= 1;
8382 return flag_code
== CODE_64BIT
? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
;
8391 #endif /* OBJ_MAYBE_ more than one */
8393 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8395 i386_elf_emit_arch_note (void)
8397 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8400 asection
*seg
= now_seg
;
8401 subsegT subseg
= now_subseg
;
8402 Elf_Internal_Note i_note
;
8403 Elf_External_Note e_note
;
8404 asection
*note_secp
;
8407 /* Create the .note section. */
8408 note_secp
= subseg_new (".note", 0);
8409 bfd_set_section_flags (stdoutput
,
8411 SEC_HAS_CONTENTS
| SEC_READONLY
);
8413 /* Process the arch string. */
8414 len
= strlen (cpu_arch_name
);
8416 i_note
.namesz
= len
+ 1;
8418 i_note
.type
= NT_ARCH
;
8419 p
= frag_more (sizeof (e_note
.namesz
));
8420 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8421 p
= frag_more (sizeof (e_note
.descsz
));
8422 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8423 p
= frag_more (sizeof (e_note
.type
));
8424 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8425 p
= frag_more (len
+ 1);
8426 strcpy (p
, cpu_arch_name
);
8428 frag_align (2, 0, 0);
8430 subseg_set (seg
, subseg
);
8436 md_undefined_symbol (name
)
8439 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8440 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8441 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8442 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8446 if (symbol_find (name
))
8447 as_bad (_("GOT already in symbol table"));
8448 GOT_symbol
= symbol_new (name
, undefined_section
,
8449 (valueT
) 0, &zero_address_frag
);
8456 /* Round up a section size to the appropriate boundary. */
8459 md_section_align (segment
, size
)
8460 segT segment ATTRIBUTE_UNUSED
;
8463 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8464 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8466 /* For a.out, force the section size to be aligned. If we don't do
8467 this, BFD will align it for us, but it will not write out the
8468 final bytes of the section. This may be a bug in BFD, but it is
8469 easier to fix it here since that is how the other a.out targets
8473 align
= bfd_get_section_alignment (stdoutput
, segment
);
8474 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8481 /* On the i386, PC-relative offsets are relative to the start of the
8482 next instruction. That is, the address of the offset, plus its
8483 size, since the offset is always the last part of the insn. */
8486 md_pcrel_from (fixS
*fixP
)
8488 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8494 s_bss (int ignore ATTRIBUTE_UNUSED
)
8498 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8500 obj_elf_section_change_hook ();
8502 temp
= get_absolute_expression ();
8503 subseg_set (bss_section
, (subsegT
) temp
);
8504 demand_empty_rest_of_line ();
8510 i386_validate_fix (fixS
*fixp
)
8512 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8514 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8518 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8523 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8525 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8532 tc_gen_reloc (section
, fixp
)
8533 asection
*section ATTRIBUTE_UNUSED
;
8537 bfd_reloc_code_real_type code
;
8539 switch (fixp
->fx_r_type
)
8541 case BFD_RELOC_X86_64_PLT32
:
8542 case BFD_RELOC_X86_64_GOT32
:
8543 case BFD_RELOC_X86_64_GOTPCREL
:
8544 case BFD_RELOC_386_PLT32
:
8545 case BFD_RELOC_386_GOT32
:
8546 case BFD_RELOC_386_GOTOFF
:
8547 case BFD_RELOC_386_GOTPC
:
8548 case BFD_RELOC_386_TLS_GD
:
8549 case BFD_RELOC_386_TLS_LDM
:
8550 case BFD_RELOC_386_TLS_LDO_32
:
8551 case BFD_RELOC_386_TLS_IE_32
:
8552 case BFD_RELOC_386_TLS_IE
:
8553 case BFD_RELOC_386_TLS_GOTIE
:
8554 case BFD_RELOC_386_TLS_LE_32
:
8555 case BFD_RELOC_386_TLS_LE
:
8556 case BFD_RELOC_386_TLS_GOTDESC
:
8557 case BFD_RELOC_386_TLS_DESC_CALL
:
8558 case BFD_RELOC_X86_64_TLSGD
:
8559 case BFD_RELOC_X86_64_TLSLD
:
8560 case BFD_RELOC_X86_64_DTPOFF32
:
8561 case BFD_RELOC_X86_64_DTPOFF64
:
8562 case BFD_RELOC_X86_64_GOTTPOFF
:
8563 case BFD_RELOC_X86_64_TPOFF32
:
8564 case BFD_RELOC_X86_64_TPOFF64
:
8565 case BFD_RELOC_X86_64_GOTOFF64
:
8566 case BFD_RELOC_X86_64_GOTPC32
:
8567 case BFD_RELOC_X86_64_GOT64
:
8568 case BFD_RELOC_X86_64_GOTPCREL64
:
8569 case BFD_RELOC_X86_64_GOTPC64
:
8570 case BFD_RELOC_X86_64_GOTPLT64
:
8571 case BFD_RELOC_X86_64_PLTOFF64
:
8572 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8573 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8575 case BFD_RELOC_VTABLE_ENTRY
:
8576 case BFD_RELOC_VTABLE_INHERIT
:
8578 case BFD_RELOC_32_SECREL
:
8580 code
= fixp
->fx_r_type
;
8582 case BFD_RELOC_X86_64_32S
:
8583 if (!fixp
->fx_pcrel
)
8585 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8586 code
= fixp
->fx_r_type
;
8592 switch (fixp
->fx_size
)
8595 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8596 _("can not do %d byte pc-relative relocation"),
8598 code
= BFD_RELOC_32_PCREL
;
8600 case 1: code
= BFD_RELOC_8_PCREL
; break;
8601 case 2: code
= BFD_RELOC_16_PCREL
; break;
8602 case 4: code
= BFD_RELOC_32_PCREL
; break;
8604 case 8: code
= BFD_RELOC_64_PCREL
; break;
8610 switch (fixp
->fx_size
)
8613 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8614 _("can not do %d byte relocation"),
8616 code
= BFD_RELOC_32
;
8618 case 1: code
= BFD_RELOC_8
; break;
8619 case 2: code
= BFD_RELOC_16
; break;
8620 case 4: code
= BFD_RELOC_32
; break;
8622 case 8: code
= BFD_RELOC_64
; break;
8629 if ((code
== BFD_RELOC_32
8630 || code
== BFD_RELOC_32_PCREL
8631 || code
== BFD_RELOC_X86_64_32S
)
8633 && fixp
->fx_addsy
== GOT_symbol
)
8636 code
= BFD_RELOC_386_GOTPC
;
8638 code
= BFD_RELOC_X86_64_GOTPC32
;
8640 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8642 && fixp
->fx_addsy
== GOT_symbol
)
8644 code
= BFD_RELOC_X86_64_GOTPC64
;
8647 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8648 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8649 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8651 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8653 if (!use_rela_relocations
)
8655 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8656 vtable entry to be used in the relocation's section offset. */
8657 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8658 rel
->address
= fixp
->fx_offset
;
8662 /* Use the rela in 64bit mode. */
8665 if (!fixp
->fx_pcrel
)
8666 rel
->addend
= fixp
->fx_offset
;
8670 case BFD_RELOC_X86_64_PLT32
:
8671 case BFD_RELOC_X86_64_GOT32
:
8672 case BFD_RELOC_X86_64_GOTPCREL
:
8673 case BFD_RELOC_X86_64_TLSGD
:
8674 case BFD_RELOC_X86_64_TLSLD
:
8675 case BFD_RELOC_X86_64_GOTTPOFF
:
8676 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8677 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8678 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8681 rel
->addend
= (section
->vma
8683 + fixp
->fx_addnumber
8684 + md_pcrel_from (fixp
));
8689 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8690 if (rel
->howto
== NULL
)
8692 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8693 _("cannot represent relocation type %s"),
8694 bfd_get_reloc_code_name (code
));
8695 /* Set howto to a garbage value so that we can keep going. */
8696 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8697 assert (rel
->howto
!= NULL
);
8703 #include "tc-i386-intel.c"
8706 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8708 int saved_naked_reg
;
8709 char saved_register_dot
;
8711 saved_naked_reg
= allow_naked_reg
;
8712 allow_naked_reg
= 1;
8713 saved_register_dot
= register_chars
['.'];
8714 register_chars
['.'] = '.';
8715 allow_pseudo_reg
= 1;
8716 expression_and_evaluate (exp
);
8717 allow_pseudo_reg
= 0;
8718 register_chars
['.'] = saved_register_dot
;
8719 allow_naked_reg
= saved_naked_reg
;
8721 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8723 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8725 exp
->X_op
= O_constant
;
8726 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8727 .dw2_regnum
[flag_code
>> 1];
8730 exp
->X_op
= O_illegal
;
8735 tc_x86_frame_initial_instructions (void)
8737 static unsigned int sp_regno
[2];
8739 if (!sp_regno
[flag_code
>> 1])
8741 char *saved_input
= input_line_pointer
;
8742 char sp
[][4] = {"esp", "rsp"};
8745 input_line_pointer
= sp
[flag_code
>> 1];
8746 tc_x86_parse_to_dw2regnum (&exp
);
8747 assert (exp
.X_op
== O_constant
);
8748 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8749 input_line_pointer
= saved_input
;
8752 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8753 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8757 i386_elf_section_type (const char *str
, size_t len
)
8759 if (flag_code
== CODE_64BIT
8760 && len
== sizeof ("unwind") - 1
8761 && strncmp (str
, "unwind", 6) == 0)
8762 return SHT_X86_64_UNWIND
;
8769 i386_solaris_fix_up_eh_frame (segT sec
)
8771 if (flag_code
== CODE_64BIT
)
8772 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8778 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8782 expr
.X_op
= O_secrel
;
8783 expr
.X_add_symbol
= symbol
;
8784 expr
.X_add_number
= 0;
8785 emit_expr (&expr
, size
);
8789 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8790 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8793 x86_64_section_letter (int letter
, char **ptr_msg
)
8795 if (flag_code
== CODE_64BIT
)
8798 return SHF_X86_64_LARGE
;
8800 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8803 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8808 x86_64_section_word (char *str
, size_t len
)
8810 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8811 return SHF_X86_64_LARGE
;
8817 handle_large_common (int small ATTRIBUTE_UNUSED
)
8819 if (flag_code
!= CODE_64BIT
)
8821 s_comm_internal (0, elf_common_parse
);
8822 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8826 static segT lbss_section
;
8827 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8828 asection
*saved_bss_section
= bss_section
;
8830 if (lbss_section
== NULL
)
8832 flagword applicable
;
8834 subsegT subseg
= now_subseg
;
8836 /* The .lbss section is for local .largecomm symbols. */
8837 lbss_section
= subseg_new (".lbss", 0);
8838 applicable
= bfd_applicable_section_flags (stdoutput
);
8839 bfd_set_section_flags (stdoutput
, lbss_section
,
8840 applicable
& SEC_ALLOC
);
8841 seg_info (lbss_section
)->bss
= 1;
8843 subseg_set (seg
, subseg
);
8846 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8847 bss_section
= lbss_section
;
8849 s_comm_internal (0, elf_common_parse
);
8851 elf_com_section_ptr
= saved_com_section_ptr
;
8852 bss_section
= saved_bss_section
;
8855 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */