1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
135 unsigned int negated
; /* turn off indicated flags. */
139 static void update_code_flag (int, int);
140 static void set_code_flag (int);
141 static void set_16bit_gcc_code_flag (int);
142 static void set_intel_syntax (int);
143 static void set_intel_mnemonic (int);
144 static void set_allow_index_reg (int);
145 static void set_sse_check (int);
146 static void set_cpu_arch (int);
148 static void pe_directive_secrel (int);
150 static void signed_cons (int);
151 static char *output_invalid (int c
);
152 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
154 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
156 static int i386_att_operand (char *);
157 static int i386_intel_operand (char *, int);
158 static int i386_intel_simplify (expressionS
*);
159 static int i386_intel_parse_name (const char *, expressionS
*);
160 static const reg_entry
*parse_register (char *, char **);
161 static char *parse_insn (char *, char *);
162 static char *parse_operands (char *, const char *);
163 static void swap_operands (void);
164 static void swap_2_operands (int, int);
165 static void optimize_imm (void);
166 static void optimize_disp (void);
167 static const insn_template
*match_template (void);
168 static int check_string (void);
169 static int process_suffix (void);
170 static int check_byte_reg (void);
171 static int check_long_reg (void);
172 static int check_qword_reg (void);
173 static int check_word_reg (void);
174 static int finalize_imm (void);
175 static int process_operands (void);
176 static const seg_entry
*build_modrm_byte (void);
177 static void output_insn (void);
178 static void output_imm (fragS
*, offsetT
);
179 static void output_disp (fragS
*, offsetT
);
181 static void s_bss (int);
183 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
184 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
187 static const char *default_arch
= DEFAULT_ARCH
;
192 /* VEX prefix is either 2 byte or 3 byte. */
193 unsigned char bytes
[3];
195 /* Destination or source register specifier. */
196 const reg_entry
*register_specifier
;
199 /* 'md_assemble ()' gathers together information and puts it into a
206 const reg_entry
*regs
;
211 operand_size_mismatch
,
212 operand_type_mismatch
,
213 register_type_mismatch
,
214 number_of_operands_mismatch
,
215 invalid_instruction_suffix
,
218 unsupported_with_intel_mnemonic
,
225 /* TM holds the template for the insn were currently assembling. */
228 /* SUFFIX holds the instruction size suffix for byte, word, dword
229 or qword, if given. */
232 /* OPERANDS gives the number of given operands. */
233 unsigned int operands
;
235 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
236 of given register, displacement, memory operands and immediate
238 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
240 /* TYPES [i] is the type (see above #defines) which tells us how to
241 use OP[i] for the corresponding operand. */
242 i386_operand_type types
[MAX_OPERANDS
];
244 /* Displacement expression, immediate expression, or register for each
246 union i386_op op
[MAX_OPERANDS
];
248 /* Flags for operands. */
249 unsigned int flags
[MAX_OPERANDS
];
250 #define Operand_PCrel 1
252 /* Relocation type for operand */
253 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
255 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
256 the base index byte below. */
257 const reg_entry
*base_reg
;
258 const reg_entry
*index_reg
;
259 unsigned int log2_scale_factor
;
261 /* SEG gives the seg_entries of this insn. They are zero unless
262 explicit segment overrides are given. */
263 const seg_entry
*seg
[2];
265 /* PREFIX holds all the given prefix opcodes (usually null).
266 PREFIXES is the number of prefix opcodes. */
267 unsigned int prefixes
;
268 unsigned char prefix
[MAX_PREFIXES
];
270 /* RM and SIB are the modrm byte and the sib byte where the
271 addressing modes of this insn are encoded. */
277 /* Swap operand in encoding. */
278 unsigned int swap_operand
;
280 /* Force 32bit displacement in encoding. */
281 unsigned int disp32_encoding
;
284 enum i386_error error
;
287 typedef struct _i386_insn i386_insn
;
289 /* List of chars besides those in app.c:symbol_chars that can start an
290 operand. Used to prevent the scrubber eating vital white-space. */
291 const char extra_symbol_chars
[] = "*%-(["
300 #if (defined (TE_I386AIX) \
301 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
302 && !defined (TE_GNU) \
303 && !defined (TE_LINUX) \
304 && !defined (TE_NETWARE) \
305 && !defined (TE_FreeBSD) \
306 && !defined (TE_NetBSD)))
307 /* This array holds the chars that always start a comment. If the
308 pre-processor is disabled, these aren't very useful. The option
309 --divide will remove '/' from this list. */
310 const char *i386_comment_chars
= "#/";
311 #define SVR4_COMMENT_CHARS 1
312 #define PREFIX_SEPARATOR '\\'
315 const char *i386_comment_chars
= "#";
316 #define PREFIX_SEPARATOR '/'
319 /* This array holds the chars that only start a comment at the beginning of
320 a line. If the line seems to have the form '# 123 filename'
321 .line and .file directives will appear in the pre-processed output.
322 Note that input_file.c hand checks for '#' at the beginning of the
323 first line of the input file. This is because the compiler outputs
324 #NO_APP at the beginning of its output.
325 Also note that comments started like this one will always work if
326 '/' isn't otherwise defined. */
327 const char line_comment_chars
[] = "#/";
329 const char line_separator_chars
[] = ";";
331 /* Chars that can be used to separate mant from exp in floating point
333 const char EXP_CHARS
[] = "eE";
335 /* Chars that mean this number is a floating point constant
338 const char FLT_CHARS
[] = "fFdDxX";
340 /* Tables for lexical analysis. */
341 static char mnemonic_chars
[256];
342 static char register_chars
[256];
343 static char operand_chars
[256];
344 static char identifier_chars
[256];
345 static char digit_chars
[256];
347 /* Lexical macros. */
348 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
349 #define is_operand_char(x) (operand_chars[(unsigned char) x])
350 #define is_register_char(x) (register_chars[(unsigned char) x])
351 #define is_space_char(x) ((x) == ' ')
352 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
353 #define is_digit_char(x) (digit_chars[(unsigned char) x])
355 /* All non-digit non-letter characters that may occur in an operand. */
356 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
358 /* md_assemble() always leaves the strings it's passed unaltered. To
359 effect this we maintain a stack of saved characters that we've smashed
360 with '\0's (indicating end of strings for various sub-fields of the
361 assembler instruction). */
362 static char save_stack
[32];
363 static char *save_stack_p
;
364 #define END_STRING_AND_SAVE(s) \
365 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
366 #define RESTORE_END_STRING(s) \
367 do { *(s) = *--save_stack_p; } while (0)
369 /* The instruction we're assembling. */
372 /* Possible templates for current insn. */
373 static const templates
*current_templates
;
375 /* Per instruction expressionS buffers: max displacements & immediates. */
376 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
377 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
379 /* Current operand we are working on. */
380 static int this_operand
= -1;
382 /* We support four different modes. FLAG_CODE variable is used to distinguish
390 static enum flag_code flag_code
;
391 static unsigned int object_64bit
;
392 static int use_rela_relocations
= 0;
394 /* The ELF ABI to use. */
402 static enum x86_elf_abi x86_elf_abi
= I386_ABI
;
404 /* The names used to print error messages. */
405 static const char *flag_code_names
[] =
412 /* 1 for intel syntax,
414 static int intel_syntax
= 0;
416 /* 1 for intel mnemonic,
417 0 if att mnemonic. */
418 static int intel_mnemonic
= !SYSV386_COMPAT
;
420 /* 1 if support old (<= 2.8.1) versions of gcc. */
421 static int old_gcc
= OLDGCC_COMPAT
;
423 /* 1 if pseudo registers are permitted. */
424 static int allow_pseudo_reg
= 0;
426 /* 1 if register prefix % not required. */
427 static int allow_naked_reg
= 0;
429 /* 1 if pseudo index register, eiz/riz, is allowed . */
430 static int allow_index_reg
= 0;
440 /* Register prefix used for error message. */
441 static const char *register_prefix
= "%";
443 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
444 leave, push, and pop instructions so that gcc has the same stack
445 frame as in 32 bit mode. */
446 static char stackop_size
= '\0';
448 /* Non-zero to optimize code alignment. */
449 int optimize_align_code
= 1;
451 /* Non-zero to quieten some warnings. */
452 static int quiet_warnings
= 0;
455 static const char *cpu_arch_name
= NULL
;
456 static char *cpu_sub_arch_name
= NULL
;
458 /* CPU feature flags. */
459 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
461 /* If we have selected a cpu we are generating instructions for. */
462 static int cpu_arch_tune_set
= 0;
464 /* Cpu we are generating instructions for. */
465 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
467 /* CPU feature flags of cpu we are generating instructions for. */
468 static i386_cpu_flags cpu_arch_tune_flags
;
470 /* CPU instruction set architecture used. */
471 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
473 /* CPU feature flags of instruction set architecture used. */
474 i386_cpu_flags cpu_arch_isa_flags
;
476 /* If set, conditional jumps are not automatically promoted to handle
477 larger than a byte offset. */
478 static unsigned int no_cond_jump_promotion
= 0;
480 /* Encode SSE instructions with VEX prefix. */
481 static unsigned int sse2avx
;
483 /* Encode scalar AVX instructions with specific vector length. */
490 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
491 static symbolS
*GOT_symbol
;
493 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
494 unsigned int x86_dwarf2_return_column
;
496 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
497 int x86_cie_data_alignment
;
499 /* Interface to relax_segment.
500 There are 3 major relax states for 386 jump insns because the
501 different types of jumps add different sizes to frags when we're
502 figuring out what sort of jump to choose to reach a given label. */
505 #define UNCOND_JUMP 0
507 #define COND_JUMP86 2
512 #define SMALL16 (SMALL | CODE16)
514 #define BIG16 (BIG | CODE16)
518 #define INLINE __inline__
524 #define ENCODE_RELAX_STATE(type, size) \
525 ((relax_substateT) (((type) << 2) | (size)))
526 #define TYPE_FROM_RELAX_STATE(s) \
528 #define DISP_SIZE_FROM_RELAX_STATE(s) \
529 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
531 /* This table is used by relax_frag to promote short jumps to long
532 ones where necessary. SMALL (short) jumps may be promoted to BIG
533 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
534 don't allow a short jump in a 32 bit code segment to be promoted to
535 a 16 bit offset jump because it's slower (requires data size
536 prefix), and doesn't work, unless the destination is in the bottom
537 64k of the code segment (The top 16 bits of eip are zeroed). */
539 const relax_typeS md_relax_table
[] =
542 1) most positive reach of this state,
543 2) most negative reach of this state,
544 3) how many bytes this mode will have in the variable part of the frag
545 4) which index into the table to try if we can't fit into this one. */
547 /* UNCOND_JUMP states. */
548 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
549 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
550 /* dword jmp adds 4 bytes to frag:
551 0 extra opcode bytes, 4 displacement bytes. */
553 /* word jmp adds 2 byte2 to frag:
554 0 extra opcode bytes, 2 displacement bytes. */
557 /* COND_JUMP states. */
558 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
559 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
560 /* dword conditionals adds 5 bytes to frag:
561 1 extra opcode byte, 4 displacement bytes. */
563 /* word conditionals add 3 bytes to frag:
564 1 extra opcode byte, 2 displacement bytes. */
567 /* COND_JUMP86 states. */
568 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
569 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
570 /* dword conditionals adds 5 bytes to frag:
571 1 extra opcode byte, 4 displacement bytes. */
573 /* word conditionals add 4 bytes to frag:
574 1 displacement byte and a 3 byte long branch insn. */
578 static const arch_entry cpu_arch
[] =
580 /* Do not replace the first two entries - i386_target_format()
581 relies on them being there in this order. */
582 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
583 CPU_GENERIC32_FLAGS
, 0, 0 },
584 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
585 CPU_GENERIC64_FLAGS
, 0, 0 },
586 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
587 CPU_NONE_FLAGS
, 0, 0 },
588 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
589 CPU_I186_FLAGS
, 0, 0 },
590 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
591 CPU_I286_FLAGS
, 0, 0 },
592 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
593 CPU_I386_FLAGS
, 0, 0 },
594 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
595 CPU_I486_FLAGS
, 0, 0 },
596 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
597 CPU_I586_FLAGS
, 0, 0 },
598 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
599 CPU_I686_FLAGS
, 0, 0 },
600 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
601 CPU_I586_FLAGS
, 0, 0 },
602 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
603 CPU_PENTIUMPRO_FLAGS
, 0, 0 },
604 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
605 CPU_P2_FLAGS
, 0, 0 },
606 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
607 CPU_P3_FLAGS
, 0, 0 },
608 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
609 CPU_P4_FLAGS
, 0, 0 },
610 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
611 CPU_CORE_FLAGS
, 0, 0 },
612 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
613 CPU_NOCONA_FLAGS
, 0, 0 },
614 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
615 CPU_CORE_FLAGS
, 1, 0 },
616 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
617 CPU_CORE_FLAGS
, 0, 0 },
618 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
619 CPU_CORE2_FLAGS
, 1, 0 },
620 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
621 CPU_CORE2_FLAGS
, 0, 0 },
622 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
623 CPU_COREI7_FLAGS
, 0, 0 },
624 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
625 CPU_L1OM_FLAGS
, 0, 0 },
626 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
627 CPU_K6_FLAGS
, 0, 0 },
628 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
629 CPU_K6_2_FLAGS
, 0, 0 },
630 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
631 CPU_ATHLON_FLAGS
, 0, 0 },
632 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
633 CPU_K8_FLAGS
, 1, 0 },
634 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
635 CPU_K8_FLAGS
, 0, 0 },
636 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
637 CPU_K8_FLAGS
, 0, 0 },
638 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
639 CPU_AMDFAM10_FLAGS
, 0, 0 },
640 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
641 CPU_BDVER1_FLAGS
, 0, 0 },
642 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
643 CPU_8087_FLAGS
, 0, 0 },
644 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
645 CPU_287_FLAGS
, 0, 0 },
646 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
647 CPU_387_FLAGS
, 0, 0 },
648 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
649 CPU_ANY87_FLAGS
, 0, 1 },
650 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
651 CPU_MMX_FLAGS
, 0, 0 },
652 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
653 CPU_3DNOWA_FLAGS
, 0, 1 },
654 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
655 CPU_SSE_FLAGS
, 0, 0 },
656 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
657 CPU_SSE2_FLAGS
, 0, 0 },
658 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
659 CPU_SSE3_FLAGS
, 0, 0 },
660 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
661 CPU_SSSE3_FLAGS
, 0, 0 },
662 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
663 CPU_SSE4_1_FLAGS
, 0, 0 },
664 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
665 CPU_SSE4_2_FLAGS
, 0, 0 },
666 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
667 CPU_SSE4_2_FLAGS
, 0, 0 },
668 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
669 CPU_ANY_SSE_FLAGS
, 0, 1 },
670 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
671 CPU_AVX_FLAGS
, 0, 0 },
672 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
673 CPU_ANY_AVX_FLAGS
, 0, 1 },
674 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
675 CPU_VMX_FLAGS
, 0, 0 },
676 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
677 CPU_SMX_FLAGS
, 0, 0 },
678 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
679 CPU_XSAVE_FLAGS
, 0, 0 },
680 { STRING_COMMA_LEN (".xsaveopt"), PROCESSOR_UNKNOWN
,
681 CPU_XSAVEOPT_FLAGS
, 0, 0 },
682 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
683 CPU_AES_FLAGS
, 0, 0 },
684 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
685 CPU_PCLMUL_FLAGS
, 0, 0 },
686 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
687 CPU_PCLMUL_FLAGS
, 1, 0 },
688 { STRING_COMMA_LEN (".fsgsbase"), PROCESSOR_UNKNOWN
,
689 CPU_FSGSBASE_FLAGS
, 0, 0 },
690 { STRING_COMMA_LEN (".rdrnd"), PROCESSOR_UNKNOWN
,
691 CPU_RDRND_FLAGS
, 0, 0 },
692 { STRING_COMMA_LEN (".f16c"), PROCESSOR_UNKNOWN
,
693 CPU_F16C_FLAGS
, 0, 0 },
694 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
695 CPU_FMA_FLAGS
, 0, 0 },
696 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
697 CPU_FMA4_FLAGS
, 0, 0 },
698 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
699 CPU_XOP_FLAGS
, 0, 0 },
700 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
701 CPU_LWP_FLAGS
, 0, 0 },
702 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
703 CPU_MOVBE_FLAGS
, 0, 0 },
704 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
705 CPU_EPT_FLAGS
, 0, 0 },
706 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
707 CPU_CLFLUSH_FLAGS
, 0, 0 },
708 { STRING_COMMA_LEN (".nop"), PROCESSOR_UNKNOWN
,
709 CPU_NOP_FLAGS
, 0, 0 },
710 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
711 CPU_SYSCALL_FLAGS
, 0, 0 },
712 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
713 CPU_RDTSCP_FLAGS
, 0, 0 },
714 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
715 CPU_3DNOW_FLAGS
, 0, 0 },
716 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
717 CPU_3DNOWA_FLAGS
, 0, 0 },
718 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
719 CPU_PADLOCK_FLAGS
, 0, 0 },
720 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
721 CPU_SVME_FLAGS
, 1, 0 },
722 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
723 CPU_SVME_FLAGS
, 0, 0 },
724 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
725 CPU_SSE4A_FLAGS
, 0, 0 },
726 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
727 CPU_ABM_FLAGS
, 0, 0 },
731 /* Like s_lcomm_internal in gas/read.c but the alignment string
732 is allowed to be optional. */
735 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
742 && *input_line_pointer
== ',')
744 align
= parse_align (needs_align
- 1);
746 if (align
== (addressT
) -1)
761 bss_alloc (symbolP
, size
, align
);
766 pe_lcomm (int needs_align
)
768 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
772 const pseudo_typeS md_pseudo_table
[] =
774 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
775 {"align", s_align_bytes
, 0},
777 {"align", s_align_ptwo
, 0},
779 {"arch", set_cpu_arch
, 0},
783 {"lcomm", pe_lcomm
, 1},
785 {"ffloat", float_cons
, 'f'},
786 {"dfloat", float_cons
, 'd'},
787 {"tfloat", float_cons
, 'x'},
789 {"slong", signed_cons
, 4},
790 {"noopt", s_ignore
, 0},
791 {"optim", s_ignore
, 0},
792 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
793 {"code16", set_code_flag
, CODE_16BIT
},
794 {"code32", set_code_flag
, CODE_32BIT
},
795 {"code64", set_code_flag
, CODE_64BIT
},
796 {"intel_syntax", set_intel_syntax
, 1},
797 {"att_syntax", set_intel_syntax
, 0},
798 {"intel_mnemonic", set_intel_mnemonic
, 1},
799 {"att_mnemonic", set_intel_mnemonic
, 0},
800 {"allow_index_reg", set_allow_index_reg
, 1},
801 {"disallow_index_reg", set_allow_index_reg
, 0},
802 {"sse_check", set_sse_check
, 0},
803 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
804 {"largecomm", handle_large_common
, 0},
806 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
807 {"loc", dwarf2_directive_loc
, 0},
808 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
811 {"secrel32", pe_directive_secrel
, 0},
816 /* For interface with expression (). */
817 extern char *input_line_pointer
;
819 /* Hash table for instruction mnemonic lookup. */
820 static struct hash_control
*op_hash
;
822 /* Hash table for register lookup. */
823 static struct hash_control
*reg_hash
;
826 i386_align_code (fragS
*fragP
, int count
)
828 /* Various efficient no-op patterns for aligning code labels.
829 Note: Don't try to assemble the instructions in the comments.
830 0L and 0w are not legal. */
831 static const char f32_1
[] =
833 static const char f32_2
[] =
834 {0x66,0x90}; /* xchg %ax,%ax */
835 static const char f32_3
[] =
836 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
837 static const char f32_4
[] =
838 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
839 static const char f32_5
[] =
841 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
842 static const char f32_6
[] =
843 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
844 static const char f32_7
[] =
845 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
846 static const char f32_8
[] =
848 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
849 static const char f32_9
[] =
850 {0x89,0xf6, /* movl %esi,%esi */
851 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
852 static const char f32_10
[] =
853 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
854 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
855 static const char f32_11
[] =
856 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
857 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
858 static const char f32_12
[] =
859 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
860 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
861 static const char f32_13
[] =
862 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
863 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
864 static const char f32_14
[] =
865 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
866 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
867 static const char f16_3
[] =
868 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
869 static const char f16_4
[] =
870 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
871 static const char f16_5
[] =
873 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
874 static const char f16_6
[] =
875 {0x89,0xf6, /* mov %si,%si */
876 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
877 static const char f16_7
[] =
878 {0x8d,0x74,0x00, /* lea 0(%si),%si */
879 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
880 static const char f16_8
[] =
881 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
882 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
883 static const char jump_31
[] =
884 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
885 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
886 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
887 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
888 static const char *const f32_patt
[] = {
889 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
890 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
892 static const char *const f16_patt
[] = {
893 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
896 static const char alt_3
[] =
898 /* nopl 0(%[re]ax) */
899 static const char alt_4
[] =
900 {0x0f,0x1f,0x40,0x00};
901 /* nopl 0(%[re]ax,%[re]ax,1) */
902 static const char alt_5
[] =
903 {0x0f,0x1f,0x44,0x00,0x00};
904 /* nopw 0(%[re]ax,%[re]ax,1) */
905 static const char alt_6
[] =
906 {0x66,0x0f,0x1f,0x44,0x00,0x00};
907 /* nopl 0L(%[re]ax) */
908 static const char alt_7
[] =
909 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
910 /* nopl 0L(%[re]ax,%[re]ax,1) */
911 static const char alt_8
[] =
912 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
913 /* nopw 0L(%[re]ax,%[re]ax,1) */
914 static const char alt_9
[] =
915 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
916 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
917 static const char alt_10
[] =
918 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
920 nopw %cs:0L(%[re]ax,%[re]ax,1) */
921 static const char alt_long_11
[] =
923 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
926 nopw %cs:0L(%[re]ax,%[re]ax,1) */
927 static const char alt_long_12
[] =
930 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
934 nopw %cs:0L(%[re]ax,%[re]ax,1) */
935 static const char alt_long_13
[] =
939 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
944 nopw %cs:0L(%[re]ax,%[re]ax,1) */
945 static const char alt_long_14
[] =
950 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
956 nopw %cs:0L(%[re]ax,%[re]ax,1) */
957 static const char alt_long_15
[] =
963 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
964 /* nopl 0(%[re]ax,%[re]ax,1)
965 nopw 0(%[re]ax,%[re]ax,1) */
966 static const char alt_short_11
[] =
967 {0x0f,0x1f,0x44,0x00,0x00,
968 0x66,0x0f,0x1f,0x44,0x00,0x00};
969 /* nopw 0(%[re]ax,%[re]ax,1)
970 nopw 0(%[re]ax,%[re]ax,1) */
971 static const char alt_short_12
[] =
972 {0x66,0x0f,0x1f,0x44,0x00,0x00,
973 0x66,0x0f,0x1f,0x44,0x00,0x00};
974 /* nopw 0(%[re]ax,%[re]ax,1)
976 static const char alt_short_13
[] =
977 {0x66,0x0f,0x1f,0x44,0x00,0x00,
978 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
981 static const char alt_short_14
[] =
982 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
983 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
985 nopl 0L(%[re]ax,%[re]ax,1) */
986 static const char alt_short_15
[] =
987 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
988 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
989 static const char *const alt_short_patt
[] = {
990 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
991 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
992 alt_short_14
, alt_short_15
994 static const char *const alt_long_patt
[] = {
995 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
996 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
997 alt_long_14
, alt_long_15
1000 /* Only align for at least a positive non-zero boundary. */
1001 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
1004 /* We need to decide which NOP sequence to use for 32bit and
1005 64bit. When -mtune= is used:
1007 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
1008 PROCESSOR_GENERIC32, f32_patt will be used.
1009 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
1010 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
1011 PROCESSOR_GENERIC64, alt_long_patt will be used.
1012 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
1013 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
1016 When -mtune= isn't used, alt_long_patt will be used if
1017 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt will
1020 When -march= or .arch is used, we can't use anything beyond
1021 cpu_arch_isa_flags. */
1023 if (flag_code
== CODE_16BIT
)
1027 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1029 /* Adjust jump offset. */
1030 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1033 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1034 f16_patt
[count
- 1], count
);
1038 const char *const *patt
= NULL
;
1040 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1042 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1043 switch (cpu_arch_tune
)
1045 case PROCESSOR_UNKNOWN
:
1046 /* We use cpu_arch_isa_flags to check if we SHOULD
1047 optimize with nops. */
1048 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1049 patt
= alt_long_patt
;
1053 case PROCESSOR_PENTIUMPRO
:
1054 case PROCESSOR_PENTIUM4
:
1055 case PROCESSOR_NOCONA
:
1056 case PROCESSOR_CORE
:
1057 case PROCESSOR_CORE2
:
1058 case PROCESSOR_COREI7
:
1059 case PROCESSOR_L1OM
:
1060 case PROCESSOR_GENERIC64
:
1061 patt
= alt_long_patt
;
1064 case PROCESSOR_ATHLON
:
1066 case PROCESSOR_AMDFAM10
:
1067 case PROCESSOR_BDVER1
:
1068 patt
= alt_short_patt
;
1070 case PROCESSOR_I386
:
1071 case PROCESSOR_I486
:
1072 case PROCESSOR_PENTIUM
:
1073 case PROCESSOR_GENERIC32
:
1080 switch (fragP
->tc_frag_data
.tune
)
1082 case PROCESSOR_UNKNOWN
:
1083 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1084 PROCESSOR_UNKNOWN. */
1088 case PROCESSOR_I386
:
1089 case PROCESSOR_I486
:
1090 case PROCESSOR_PENTIUM
:
1092 case PROCESSOR_ATHLON
:
1094 case PROCESSOR_AMDFAM10
:
1095 case PROCESSOR_BDVER1
:
1096 case PROCESSOR_GENERIC32
:
1097 /* We use cpu_arch_isa_flags to check if we CAN optimize
1099 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1100 patt
= alt_short_patt
;
1104 case PROCESSOR_PENTIUMPRO
:
1105 case PROCESSOR_PENTIUM4
:
1106 case PROCESSOR_NOCONA
:
1107 case PROCESSOR_CORE
:
1108 case PROCESSOR_CORE2
:
1109 case PROCESSOR_COREI7
:
1110 case PROCESSOR_L1OM
:
1111 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpunop
)
1112 patt
= alt_long_patt
;
1116 case PROCESSOR_GENERIC64
:
1117 patt
= alt_long_patt
;
1122 if (patt
== f32_patt
)
1124 /* If the padding is less than 15 bytes, we use the normal
1125 ones. Otherwise, we use a jump instruction and adjust
1129 /* For 64bit, the limit is 3 bytes. */
1130 if (flag_code
== CODE_64BIT
1131 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1136 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1137 patt
[count
- 1], count
);
1140 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1142 /* Adjust jump offset. */
1143 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1148 /* Maximum length of an instruction is 15 byte. If the
1149 padding is greater than 15 bytes and we don't use jump,
1150 we have to break it into smaller pieces. */
1151 int padding
= count
;
1152 while (padding
> 15)
1155 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1160 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1161 patt
[padding
- 1], padding
);
1164 fragP
->fr_var
= count
;
1168 operand_type_all_zero (const union i386_operand_type
*x
)
1170 switch (ARRAY_SIZE(x
->array
))
1179 return !x
->array
[0];
1186 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1188 switch (ARRAY_SIZE(x
->array
))
1203 operand_type_equal (const union i386_operand_type
*x
,
1204 const union i386_operand_type
*y
)
1206 switch (ARRAY_SIZE(x
->array
))
1209 if (x
->array
[2] != y
->array
[2])
1212 if (x
->array
[1] != y
->array
[1])
1215 return x
->array
[0] == y
->array
[0];
1223 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1225 switch (ARRAY_SIZE(x
->array
))
1234 return !x
->array
[0];
1241 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1243 switch (ARRAY_SIZE(x
->array
))
1258 cpu_flags_equal (const union i386_cpu_flags
*x
,
1259 const union i386_cpu_flags
*y
)
1261 switch (ARRAY_SIZE(x
->array
))
1264 if (x
->array
[2] != y
->array
[2])
1267 if (x
->array
[1] != y
->array
[1])
1270 return x
->array
[0] == y
->array
[0];
1278 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1280 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1281 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1284 static INLINE i386_cpu_flags
1285 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1287 switch (ARRAY_SIZE (x
.array
))
1290 x
.array
[2] &= y
.array
[2];
1292 x
.array
[1] &= y
.array
[1];
1294 x
.array
[0] &= y
.array
[0];
1302 static INLINE i386_cpu_flags
1303 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1305 switch (ARRAY_SIZE (x
.array
))
1308 x
.array
[2] |= y
.array
[2];
1310 x
.array
[1] |= y
.array
[1];
1312 x
.array
[0] |= y
.array
[0];
1320 static INLINE i386_cpu_flags
1321 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1323 switch (ARRAY_SIZE (x
.array
))
1326 x
.array
[2] &= ~y
.array
[2];
1328 x
.array
[1] &= ~y
.array
[1];
1330 x
.array
[0] &= ~y
.array
[0];
1338 #define CPU_FLAGS_ARCH_MATCH 0x1
1339 #define CPU_FLAGS_64BIT_MATCH 0x2
1340 #define CPU_FLAGS_AES_MATCH 0x4
1341 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1342 #define CPU_FLAGS_AVX_MATCH 0x10
1344 #define CPU_FLAGS_32BIT_MATCH \
1345 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1346 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1347 #define CPU_FLAGS_PERFECT_MATCH \
1348 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1350 /* Return CPU flags match bits. */
1353 cpu_flags_match (const insn_template
*t
)
1355 i386_cpu_flags x
= t
->cpu_flags
;
1356 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1358 x
.bitfield
.cpu64
= 0;
1359 x
.bitfield
.cpuno64
= 0;
1361 if (cpu_flags_all_zero (&x
))
1363 /* This instruction is available on all archs. */
1364 match
|= CPU_FLAGS_32BIT_MATCH
;
1368 /* This instruction is available only on some archs. */
1369 i386_cpu_flags cpu
= cpu_arch_flags
;
1371 cpu
.bitfield
.cpu64
= 0;
1372 cpu
.bitfield
.cpuno64
= 0;
1373 cpu
= cpu_flags_and (x
, cpu
);
1374 if (!cpu_flags_all_zero (&cpu
))
1376 if (x
.bitfield
.cpuavx
)
1378 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1379 if (cpu
.bitfield
.cpuavx
)
1381 /* Check SSE2AVX. */
1382 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1384 match
|= (CPU_FLAGS_ARCH_MATCH
1385 | CPU_FLAGS_AVX_MATCH
);
1387 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1388 match
|= CPU_FLAGS_AES_MATCH
;
1390 if (!x
.bitfield
.cpupclmul
1391 || cpu
.bitfield
.cpupclmul
)
1392 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1396 match
|= CPU_FLAGS_ARCH_MATCH
;
1399 match
|= CPU_FLAGS_32BIT_MATCH
;
1405 static INLINE i386_operand_type
1406 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1408 switch (ARRAY_SIZE (x
.array
))
1411 x
.array
[2] &= y
.array
[2];
1413 x
.array
[1] &= y
.array
[1];
1415 x
.array
[0] &= y
.array
[0];
1423 static INLINE i386_operand_type
1424 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1426 switch (ARRAY_SIZE (x
.array
))
1429 x
.array
[2] |= y
.array
[2];
1431 x
.array
[1] |= y
.array
[1];
1433 x
.array
[0] |= y
.array
[0];
1441 static INLINE i386_operand_type
1442 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1444 switch (ARRAY_SIZE (x
.array
))
1447 x
.array
[2] ^= y
.array
[2];
1449 x
.array
[1] ^= y
.array
[1];
1451 x
.array
[0] ^= y
.array
[0];
1459 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1460 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1461 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1462 static const i386_operand_type inoutportreg
1463 = OPERAND_TYPE_INOUTPORTREG
;
1464 static const i386_operand_type reg16_inoutportreg
1465 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1466 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1467 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1468 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1469 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1470 static const i386_operand_type anydisp
1471 = OPERAND_TYPE_ANYDISP
;
1472 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1473 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1474 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1475 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1476 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1477 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1478 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1479 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1480 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1481 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1482 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1483 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1494 operand_type_check (i386_operand_type t
, enum operand_type c
)
1499 return (t
.bitfield
.reg8
1502 || t
.bitfield
.reg64
);
1505 return (t
.bitfield
.imm8
1509 || t
.bitfield
.imm32s
1510 || t
.bitfield
.imm64
);
1513 return (t
.bitfield
.disp8
1514 || t
.bitfield
.disp16
1515 || t
.bitfield
.disp32
1516 || t
.bitfield
.disp32s
1517 || t
.bitfield
.disp64
);
1520 return (t
.bitfield
.disp8
1521 || t
.bitfield
.disp16
1522 || t
.bitfield
.disp32
1523 || t
.bitfield
.disp32s
1524 || t
.bitfield
.disp64
1525 || t
.bitfield
.baseindex
);
1534 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1535 operand J for instruction template T. */
1538 match_reg_size (const insn_template
*t
, unsigned int j
)
1540 return !((i
.types
[j
].bitfield
.byte
1541 && !t
->operand_types
[j
].bitfield
.byte
)
1542 || (i
.types
[j
].bitfield
.word
1543 && !t
->operand_types
[j
].bitfield
.word
)
1544 || (i
.types
[j
].bitfield
.dword
1545 && !t
->operand_types
[j
].bitfield
.dword
)
1546 || (i
.types
[j
].bitfield
.qword
1547 && !t
->operand_types
[j
].bitfield
.qword
));
1550 /* Return 1 if there is no conflict in any size on operand J for
1551 instruction template T. */
1554 match_mem_size (const insn_template
*t
, unsigned int j
)
1556 return (match_reg_size (t
, j
)
1557 && !((i
.types
[j
].bitfield
.unspecified
1558 && !t
->operand_types
[j
].bitfield
.unspecified
)
1559 || (i
.types
[j
].bitfield
.fword
1560 && !t
->operand_types
[j
].bitfield
.fword
)
1561 || (i
.types
[j
].bitfield
.tbyte
1562 && !t
->operand_types
[j
].bitfield
.tbyte
)
1563 || (i
.types
[j
].bitfield
.xmmword
1564 && !t
->operand_types
[j
].bitfield
.xmmword
)
1565 || (i
.types
[j
].bitfield
.ymmword
1566 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1569 /* Return 1 if there is no size conflict on any operands for
1570 instruction template T. */
1573 operand_size_match (const insn_template
*t
)
1578 /* Don't check jump instructions. */
1579 if (t
->opcode_modifier
.jump
1580 || t
->opcode_modifier
.jumpbyte
1581 || t
->opcode_modifier
.jumpdword
1582 || t
->opcode_modifier
.jumpintersegment
)
1585 /* Check memory and accumulator operand size. */
1586 for (j
= 0; j
< i
.operands
; j
++)
1588 if (t
->operand_types
[j
].bitfield
.anysize
)
1591 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1597 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1606 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1609 i
.error
= operand_size_mismatch
;
1613 /* Check reverse. */
1614 gas_assert (i
.operands
== 2);
1617 for (j
= 0; j
< 2; j
++)
1619 if (t
->operand_types
[j
].bitfield
.acc
1620 && !match_reg_size (t
, j
? 0 : 1))
1623 if (i
.types
[j
].bitfield
.mem
1624 && !match_mem_size (t
, j
? 0 : 1))
1632 operand_type_match (i386_operand_type overlap
,
1633 i386_operand_type given
)
1635 i386_operand_type temp
= overlap
;
1637 temp
.bitfield
.jumpabsolute
= 0;
1638 temp
.bitfield
.unspecified
= 0;
1639 temp
.bitfield
.byte
= 0;
1640 temp
.bitfield
.word
= 0;
1641 temp
.bitfield
.dword
= 0;
1642 temp
.bitfield
.fword
= 0;
1643 temp
.bitfield
.qword
= 0;
1644 temp
.bitfield
.tbyte
= 0;
1645 temp
.bitfield
.xmmword
= 0;
1646 temp
.bitfield
.ymmword
= 0;
1647 if (operand_type_all_zero (&temp
))
1650 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1651 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1655 i
.error
= operand_type_mismatch
;
1659 /* If given types g0 and g1 are registers they must be of the same type
1660 unless the expected operand type register overlap is null.
1661 Note that Acc in a template matches every size of reg. */
1664 operand_type_register_match (i386_operand_type m0
,
1665 i386_operand_type g0
,
1666 i386_operand_type t0
,
1667 i386_operand_type m1
,
1668 i386_operand_type g1
,
1669 i386_operand_type t1
)
1671 if (!operand_type_check (g0
, reg
))
1674 if (!operand_type_check (g1
, reg
))
1677 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1678 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1679 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1680 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1683 if (m0
.bitfield
.acc
)
1685 t0
.bitfield
.reg8
= 1;
1686 t0
.bitfield
.reg16
= 1;
1687 t0
.bitfield
.reg32
= 1;
1688 t0
.bitfield
.reg64
= 1;
1691 if (m1
.bitfield
.acc
)
1693 t1
.bitfield
.reg8
= 1;
1694 t1
.bitfield
.reg16
= 1;
1695 t1
.bitfield
.reg32
= 1;
1696 t1
.bitfield
.reg64
= 1;
1699 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1700 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1701 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1702 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1705 i
.error
= register_type_mismatch
;
1710 static INLINE
unsigned int
1711 mode_from_disp_size (i386_operand_type t
)
1713 if (t
.bitfield
.disp8
)
1715 else if (t
.bitfield
.disp16
1716 || t
.bitfield
.disp32
1717 || t
.bitfield
.disp32s
)
1724 fits_in_signed_byte (offsetT num
)
1726 return (num
>= -128) && (num
<= 127);
1730 fits_in_unsigned_byte (offsetT num
)
1732 return (num
& 0xff) == num
;
1736 fits_in_unsigned_word (offsetT num
)
1738 return (num
& 0xffff) == num
;
1742 fits_in_signed_word (offsetT num
)
1744 return (-32768 <= num
) && (num
<= 32767);
1748 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1753 return (!(((offsetT
) -1 << 31) & num
)
1754 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1756 } /* fits_in_signed_long() */
1759 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1764 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1766 } /* fits_in_unsigned_long() */
1769 fits_in_imm4 (offsetT num
)
1771 return (num
& 0xf) == num
;
1774 static i386_operand_type
1775 smallest_imm_type (offsetT num
)
1777 i386_operand_type t
;
1779 operand_type_set (&t
, 0);
1780 t
.bitfield
.imm64
= 1;
1782 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1784 /* This code is disabled on the 486 because all the Imm1 forms
1785 in the opcode table are slower on the i486. They're the
1786 versions with the implicitly specified single-position
1787 displacement, which has another syntax if you really want to
1789 t
.bitfield
.imm1
= 1;
1790 t
.bitfield
.imm8
= 1;
1791 t
.bitfield
.imm8s
= 1;
1792 t
.bitfield
.imm16
= 1;
1793 t
.bitfield
.imm32
= 1;
1794 t
.bitfield
.imm32s
= 1;
1796 else if (fits_in_signed_byte (num
))
1798 t
.bitfield
.imm8
= 1;
1799 t
.bitfield
.imm8s
= 1;
1800 t
.bitfield
.imm16
= 1;
1801 t
.bitfield
.imm32
= 1;
1802 t
.bitfield
.imm32s
= 1;
1804 else if (fits_in_unsigned_byte (num
))
1806 t
.bitfield
.imm8
= 1;
1807 t
.bitfield
.imm16
= 1;
1808 t
.bitfield
.imm32
= 1;
1809 t
.bitfield
.imm32s
= 1;
1811 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1813 t
.bitfield
.imm16
= 1;
1814 t
.bitfield
.imm32
= 1;
1815 t
.bitfield
.imm32s
= 1;
1817 else if (fits_in_signed_long (num
))
1819 t
.bitfield
.imm32
= 1;
1820 t
.bitfield
.imm32s
= 1;
1822 else if (fits_in_unsigned_long (num
))
1823 t
.bitfield
.imm32
= 1;
1829 offset_in_range (offsetT val
, int size
)
1835 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1836 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1837 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1839 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1845 /* If BFD64, sign extend val for 32bit address mode. */
1846 if (flag_code
!= CODE_64BIT
1847 || i
.prefix
[ADDR_PREFIX
])
1848 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1849 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1852 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1854 char buf1
[40], buf2
[40];
1856 sprint_value (buf1
, val
);
1857 sprint_value (buf2
, val
& mask
);
1858 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1872 a. PREFIX_EXIST if attempting to add a prefix where one from the
1873 same class already exists.
1874 b. PREFIX_LOCK if lock prefix is added.
1875 c. PREFIX_REP if rep/repne prefix is added.
1876 d. PREFIX_OTHER if other prefix is added.
1879 static enum PREFIX_GROUP
1880 add_prefix (unsigned int prefix
)
1882 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1885 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1886 && flag_code
== CODE_64BIT
)
1888 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1889 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1890 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1901 case CS_PREFIX_OPCODE
:
1902 case DS_PREFIX_OPCODE
:
1903 case ES_PREFIX_OPCODE
:
1904 case FS_PREFIX_OPCODE
:
1905 case GS_PREFIX_OPCODE
:
1906 case SS_PREFIX_OPCODE
:
1910 case REPNE_PREFIX_OPCODE
:
1911 case REPE_PREFIX_OPCODE
:
1916 case LOCK_PREFIX_OPCODE
:
1925 case ADDR_PREFIX_OPCODE
:
1929 case DATA_PREFIX_OPCODE
:
1933 if (i
.prefix
[q
] != 0)
1941 i
.prefix
[q
] |= prefix
;
1944 as_bad (_("same type of prefix used twice"));
1950 update_code_flag (int value
, int check
)
1952 PRINTF_LIKE ((*as_error
));
1954 flag_code
= (enum flag_code
) value
;
1955 if (flag_code
== CODE_64BIT
)
1957 cpu_arch_flags
.bitfield
.cpu64
= 1;
1958 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1962 cpu_arch_flags
.bitfield
.cpu64
= 0;
1963 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1965 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1968 as_error
= as_fatal
;
1971 (*as_error
) (_("64bit mode not supported on `%s'."),
1972 cpu_arch_name
? cpu_arch_name
: default_arch
);
1974 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1977 as_error
= as_fatal
;
1980 (*as_error
) (_("32bit mode not supported on `%s'."),
1981 cpu_arch_name
? cpu_arch_name
: default_arch
);
1983 stackop_size
= '\0';
1987 set_code_flag (int value
)
1989 update_code_flag (value
, 0);
1993 set_16bit_gcc_code_flag (int new_code_flag
)
1995 flag_code
= (enum flag_code
) new_code_flag
;
1996 if (flag_code
!= CODE_16BIT
)
1998 cpu_arch_flags
.bitfield
.cpu64
= 0;
1999 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2000 stackop_size
= LONG_MNEM_SUFFIX
;
2004 set_intel_syntax (int syntax_flag
)
2006 /* Find out if register prefixing is specified. */
2007 int ask_naked_reg
= 0;
2010 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2012 char *string
= input_line_pointer
;
2013 int e
= get_symbol_end ();
2015 if (strcmp (string
, "prefix") == 0)
2017 else if (strcmp (string
, "noprefix") == 0)
2020 as_bad (_("bad argument to syntax directive."));
2021 *input_line_pointer
= e
;
2023 demand_empty_rest_of_line ();
2025 intel_syntax
= syntax_flag
;
2027 if (ask_naked_reg
== 0)
2028 allow_naked_reg
= (intel_syntax
2029 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
2031 allow_naked_reg
= (ask_naked_reg
< 0);
2033 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
2035 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
2036 identifier_chars
['$'] = intel_syntax
? '$' : 0;
2037 register_prefix
= allow_naked_reg
? "" : "%";
2041 set_intel_mnemonic (int mnemonic_flag
)
2043 intel_mnemonic
= mnemonic_flag
;
2047 set_allow_index_reg (int flag
)
2049 allow_index_reg
= flag
;
2053 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2057 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2059 char *string
= input_line_pointer
;
2060 int e
= get_symbol_end ();
2062 if (strcmp (string
, "none") == 0)
2063 sse_check
= sse_check_none
;
2064 else if (strcmp (string
, "warning") == 0)
2065 sse_check
= sse_check_warning
;
2066 else if (strcmp (string
, "error") == 0)
2067 sse_check
= sse_check_error
;
2069 as_bad (_("bad argument to sse_check directive."));
2070 *input_line_pointer
= e
;
2073 as_bad (_("missing argument for sse_check directive"));
2075 demand_empty_rest_of_line ();
2079 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2080 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2082 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2083 static const char *arch
;
2085 /* Intel LIOM is only supported on ELF. */
2091 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2092 use default_arch. */
2093 arch
= cpu_arch_name
;
2095 arch
= default_arch
;
2098 /* If we are targeting Intel L1OM, we must enable it. */
2099 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2100 || new_flag
.bitfield
.cpul1om
)
2103 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2108 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2112 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2114 char *string
= input_line_pointer
;
2115 int e
= get_symbol_end ();
2117 i386_cpu_flags flags
;
2119 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2121 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2123 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2127 cpu_arch_name
= cpu_arch
[j
].name
;
2128 cpu_sub_arch_name
= NULL
;
2129 cpu_arch_flags
= cpu_arch
[j
].flags
;
2130 if (flag_code
== CODE_64BIT
)
2132 cpu_arch_flags
.bitfield
.cpu64
= 1;
2133 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2137 cpu_arch_flags
.bitfield
.cpu64
= 0;
2138 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2140 cpu_arch_isa
= cpu_arch
[j
].type
;
2141 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2142 if (!cpu_arch_tune_set
)
2144 cpu_arch_tune
= cpu_arch_isa
;
2145 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2150 if (!cpu_arch
[j
].negated
)
2151 flags
= cpu_flags_or (cpu_arch_flags
,
2154 flags
= cpu_flags_and_not (cpu_arch_flags
,
2156 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2158 if (cpu_sub_arch_name
)
2160 char *name
= cpu_sub_arch_name
;
2161 cpu_sub_arch_name
= concat (name
,
2163 (const char *) NULL
);
2167 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2168 cpu_arch_flags
= flags
;
2170 *input_line_pointer
= e
;
2171 demand_empty_rest_of_line ();
2175 if (j
>= ARRAY_SIZE (cpu_arch
))
2176 as_bad (_("no such architecture: `%s'"), string
);
2178 *input_line_pointer
= e
;
2181 as_bad (_("missing cpu architecture"));
2183 no_cond_jump_promotion
= 0;
2184 if (*input_line_pointer
== ','
2185 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2187 char *string
= ++input_line_pointer
;
2188 int e
= get_symbol_end ();
2190 if (strcmp (string
, "nojumps") == 0)
2191 no_cond_jump_promotion
= 1;
2192 else if (strcmp (string
, "jumps") == 0)
2195 as_bad (_("no such architecture modifier: `%s'"), string
);
2197 *input_line_pointer
= e
;
2200 demand_empty_rest_of_line ();
2203 enum bfd_architecture
2206 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2208 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2209 || flag_code
!= CODE_64BIT
)
2210 as_fatal (_("Intel L1OM is 64bit ELF only"));
2211 return bfd_arch_l1om
;
2214 return bfd_arch_i386
;
2220 if (!strncmp (default_arch
, "x86_64", 6))
2222 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2224 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2225 || default_arch
[6] != '\0')
2226 as_fatal (_("Intel L1OM is 64bit ELF only"));
2227 return bfd_mach_l1om
;
2229 else if (default_arch
[6] == '\0')
2230 return bfd_mach_x86_64
;
2232 return bfd_mach_x64_32
;
2234 else if (!strcmp (default_arch
, "i386"))
2235 return bfd_mach_i386_i386
;
2237 as_fatal (_("Unknown architecture"));
2243 const char *hash_err
;
2245 /* Initialize op_hash hash table. */
2246 op_hash
= hash_new ();
2249 const insn_template
*optab
;
2250 templates
*core_optab
;
2252 /* Setup for loop. */
2254 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2255 core_optab
->start
= optab
;
2260 if (optab
->name
== NULL
2261 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2263 /* different name --> ship out current template list;
2264 add to hash table; & begin anew. */
2265 core_optab
->end
= optab
;
2266 hash_err
= hash_insert (op_hash
,
2268 (void *) core_optab
);
2271 as_fatal (_("Internal Error: Can't hash %s: %s"),
2275 if (optab
->name
== NULL
)
2277 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2278 core_optab
->start
= optab
;
2283 /* Initialize reg_hash hash table. */
2284 reg_hash
= hash_new ();
2286 const reg_entry
*regtab
;
2287 unsigned int regtab_size
= i386_regtab_size
;
2289 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2291 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2293 as_fatal (_("Internal Error: Can't hash %s: %s"),
2299 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2304 for (c
= 0; c
< 256; c
++)
2309 mnemonic_chars
[c
] = c
;
2310 register_chars
[c
] = c
;
2311 operand_chars
[c
] = c
;
2313 else if (ISLOWER (c
))
2315 mnemonic_chars
[c
] = c
;
2316 register_chars
[c
] = c
;
2317 operand_chars
[c
] = c
;
2319 else if (ISUPPER (c
))
2321 mnemonic_chars
[c
] = TOLOWER (c
);
2322 register_chars
[c
] = mnemonic_chars
[c
];
2323 operand_chars
[c
] = c
;
2326 if (ISALPHA (c
) || ISDIGIT (c
))
2327 identifier_chars
[c
] = c
;
2330 identifier_chars
[c
] = c
;
2331 operand_chars
[c
] = c
;
2336 identifier_chars
['@'] = '@';
2339 identifier_chars
['?'] = '?';
2340 operand_chars
['?'] = '?';
2342 digit_chars
['-'] = '-';
2343 mnemonic_chars
['_'] = '_';
2344 mnemonic_chars
['-'] = '-';
2345 mnemonic_chars
['.'] = '.';
2346 identifier_chars
['_'] = '_';
2347 identifier_chars
['.'] = '.';
2349 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2350 operand_chars
[(unsigned char) *p
] = *p
;
2353 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2356 record_alignment (text_section
, 2);
2357 record_alignment (data_section
, 2);
2358 record_alignment (bss_section
, 2);
2362 if (flag_code
== CODE_64BIT
)
2364 x86_dwarf2_return_column
= 16;
2365 x86_cie_data_alignment
= -8;
2369 x86_dwarf2_return_column
= 8;
2370 x86_cie_data_alignment
= -4;
2375 i386_print_statistics (FILE *file
)
2377 hash_print_statistics (file
, "i386 opcode", op_hash
);
2378 hash_print_statistics (file
, "i386 register", reg_hash
);
2383 /* Debugging routines for md_assemble. */
2384 static void pte (insn_template
*);
2385 static void pt (i386_operand_type
);
2386 static void pe (expressionS
*);
2387 static void ps (symbolS
*);
2390 pi (char *line
, i386_insn
*x
)
2394 fprintf (stdout
, "%s: template ", line
);
2396 fprintf (stdout
, " address: base %s index %s scale %x\n",
2397 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2398 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2399 x
->log2_scale_factor
);
2400 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2401 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2402 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2403 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2404 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2405 (x
->rex
& REX_W
) != 0,
2406 (x
->rex
& REX_R
) != 0,
2407 (x
->rex
& REX_X
) != 0,
2408 (x
->rex
& REX_B
) != 0);
2409 for (j
= 0; j
< x
->operands
; j
++)
2411 fprintf (stdout
, " #%d: ", j
+ 1);
2413 fprintf (stdout
, "\n");
2414 if (x
->types
[j
].bitfield
.reg8
2415 || x
->types
[j
].bitfield
.reg16
2416 || x
->types
[j
].bitfield
.reg32
2417 || x
->types
[j
].bitfield
.reg64
2418 || x
->types
[j
].bitfield
.regmmx
2419 || x
->types
[j
].bitfield
.regxmm
2420 || x
->types
[j
].bitfield
.regymm
2421 || x
->types
[j
].bitfield
.sreg2
2422 || x
->types
[j
].bitfield
.sreg3
2423 || x
->types
[j
].bitfield
.control
2424 || x
->types
[j
].bitfield
.debug
2425 || x
->types
[j
].bitfield
.test
)
2426 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2427 if (operand_type_check (x
->types
[j
], imm
))
2429 if (operand_type_check (x
->types
[j
], disp
))
2430 pe (x
->op
[j
].disps
);
2435 pte (insn_template
*t
)
2438 fprintf (stdout
, " %d operands ", t
->operands
);
2439 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2440 if (t
->extension_opcode
!= None
)
2441 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2442 if (t
->opcode_modifier
.d
)
2443 fprintf (stdout
, "D");
2444 if (t
->opcode_modifier
.w
)
2445 fprintf (stdout
, "W");
2446 fprintf (stdout
, "\n");
2447 for (j
= 0; j
< t
->operands
; j
++)
2449 fprintf (stdout
, " #%d type ", j
+ 1);
2450 pt (t
->operand_types
[j
]);
2451 fprintf (stdout
, "\n");
2458 fprintf (stdout
, " operation %d\n", e
->X_op
);
2459 fprintf (stdout
, " add_number %ld (%lx)\n",
2460 (long) e
->X_add_number
, (long) e
->X_add_number
);
2461 if (e
->X_add_symbol
)
2463 fprintf (stdout
, " add_symbol ");
2464 ps (e
->X_add_symbol
);
2465 fprintf (stdout
, "\n");
2469 fprintf (stdout
, " op_symbol ");
2470 ps (e
->X_op_symbol
);
2471 fprintf (stdout
, "\n");
2478 fprintf (stdout
, "%s type %s%s",
2480 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2481 segment_name (S_GET_SEGMENT (s
)));
2484 static struct type_name
2486 i386_operand_type mask
;
2489 const type_names
[] =
2491 { OPERAND_TYPE_REG8
, "r8" },
2492 { OPERAND_TYPE_REG16
, "r16" },
2493 { OPERAND_TYPE_REG32
, "r32" },
2494 { OPERAND_TYPE_REG64
, "r64" },
2495 { OPERAND_TYPE_IMM8
, "i8" },
2496 { OPERAND_TYPE_IMM8
, "i8s" },
2497 { OPERAND_TYPE_IMM16
, "i16" },
2498 { OPERAND_TYPE_IMM32
, "i32" },
2499 { OPERAND_TYPE_IMM32S
, "i32s" },
2500 { OPERAND_TYPE_IMM64
, "i64" },
2501 { OPERAND_TYPE_IMM1
, "i1" },
2502 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2503 { OPERAND_TYPE_DISP8
, "d8" },
2504 { OPERAND_TYPE_DISP16
, "d16" },
2505 { OPERAND_TYPE_DISP32
, "d32" },
2506 { OPERAND_TYPE_DISP32S
, "d32s" },
2507 { OPERAND_TYPE_DISP64
, "d64" },
2508 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2509 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2510 { OPERAND_TYPE_CONTROL
, "control reg" },
2511 { OPERAND_TYPE_TEST
, "test reg" },
2512 { OPERAND_TYPE_DEBUG
, "debug reg" },
2513 { OPERAND_TYPE_FLOATREG
, "FReg" },
2514 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2515 { OPERAND_TYPE_SREG2
, "SReg2" },
2516 { OPERAND_TYPE_SREG3
, "SReg3" },
2517 { OPERAND_TYPE_ACC
, "Acc" },
2518 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2519 { OPERAND_TYPE_REGMMX
, "rMMX" },
2520 { OPERAND_TYPE_REGXMM
, "rXMM" },
2521 { OPERAND_TYPE_REGYMM
, "rYMM" },
2522 { OPERAND_TYPE_ESSEG
, "es" },
2526 pt (i386_operand_type t
)
2529 i386_operand_type a
;
2531 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2533 a
= operand_type_and (t
, type_names
[j
].mask
);
2534 if (!operand_type_all_zero (&a
))
2535 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2540 #endif /* DEBUG386 */
2542 static bfd_reloc_code_real_type
2543 reloc (unsigned int size
,
2546 bfd_reloc_code_real_type other
)
2548 if (other
!= NO_RELOC
)
2550 reloc_howto_type
*rel
;
2555 case BFD_RELOC_X86_64_GOT32
:
2556 return BFD_RELOC_X86_64_GOT64
;
2558 case BFD_RELOC_X86_64_PLTOFF64
:
2559 return BFD_RELOC_X86_64_PLTOFF64
;
2561 case BFD_RELOC_X86_64_GOTPC32
:
2562 other
= BFD_RELOC_X86_64_GOTPC64
;
2564 case BFD_RELOC_X86_64_GOTPCREL
:
2565 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2567 case BFD_RELOC_X86_64_TPOFF32
:
2568 other
= BFD_RELOC_X86_64_TPOFF64
;
2570 case BFD_RELOC_X86_64_DTPOFF32
:
2571 other
= BFD_RELOC_X86_64_DTPOFF64
;
2577 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2578 if (size
== 4 && flag_code
!= CODE_64BIT
)
2581 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2583 as_bad (_("unknown relocation (%u)"), other
);
2584 else if (size
!= bfd_get_reloc_size (rel
))
2585 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2586 bfd_get_reloc_size (rel
),
2588 else if (pcrel
&& !rel
->pc_relative
)
2589 as_bad (_("non-pc-relative relocation for pc-relative field"));
2590 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2592 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2594 as_bad (_("relocated field and relocation type differ in signedness"));
2603 as_bad (_("there are no unsigned pc-relative relocations"));
2606 case 1: return BFD_RELOC_8_PCREL
;
2607 case 2: return BFD_RELOC_16_PCREL
;
2608 case 4: return BFD_RELOC_32_PCREL
;
2609 case 8: return BFD_RELOC_64_PCREL
;
2611 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2618 case 4: return BFD_RELOC_X86_64_32S
;
2623 case 1: return BFD_RELOC_8
;
2624 case 2: return BFD_RELOC_16
;
2625 case 4: return BFD_RELOC_32
;
2626 case 8: return BFD_RELOC_64
;
2628 as_bad (_("cannot do %s %u byte relocation"),
2629 sign
> 0 ? "signed" : "unsigned", size
);
2635 /* Here we decide which fixups can be adjusted to make them relative to
2636 the beginning of the section instead of the symbol. Basically we need
2637 to make sure that the dynamic relocations are done correctly, so in
2638 some cases we force the original symbol to be used. */
2641 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2643 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2647 /* Don't adjust pc-relative references to merge sections in 64-bit
2649 if (use_rela_relocations
2650 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2654 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2655 and changed later by validate_fix. */
2656 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2657 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2660 /* adjust_reloc_syms doesn't know about the GOT. */
2661 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2662 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2663 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2664 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2665 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2666 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2667 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2668 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2669 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2670 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2671 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2672 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2673 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2674 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2675 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2676 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2677 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2678 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2679 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2680 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2681 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2682 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2683 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2684 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2685 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2686 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2687 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2688 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2695 intel_float_operand (const char *mnemonic
)
2697 /* Note that the value returned is meaningful only for opcodes with (memory)
2698 operands, hence the code here is free to improperly handle opcodes that
2699 have no operands (for better performance and smaller code). */
2701 if (mnemonic
[0] != 'f')
2702 return 0; /* non-math */
2704 switch (mnemonic
[1])
2706 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2707 the fs segment override prefix not currently handled because no
2708 call path can make opcodes without operands get here */
2710 return 2 /* integer op */;
2712 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2713 return 3; /* fldcw/fldenv */
2716 if (mnemonic
[2] != 'o' /* fnop */)
2717 return 3; /* non-waiting control op */
2720 if (mnemonic
[2] == 's')
2721 return 3; /* frstor/frstpm */
2724 if (mnemonic
[2] == 'a')
2725 return 3; /* fsave */
2726 if (mnemonic
[2] == 't')
2728 switch (mnemonic
[3])
2730 case 'c': /* fstcw */
2731 case 'd': /* fstdw */
2732 case 'e': /* fstenv */
2733 case 's': /* fsts[gw] */
2739 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2740 return 0; /* fxsave/fxrstor are not really math ops */
2747 /* Build the VEX prefix. */
2750 build_vex_prefix (const insn_template
*t
)
2752 unsigned int register_specifier
;
2753 unsigned int implied_prefix
;
2754 unsigned int vector_length
;
2756 /* Check register specifier. */
2757 if (i
.vex
.register_specifier
)
2759 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2760 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2761 register_specifier
+= 8;
2762 register_specifier
= ~register_specifier
& 0xf;
2765 register_specifier
= 0xf;
2767 /* Use 2-byte VEX prefix by swappping destination and source
2770 && i
.operands
== i
.reg_operands
2771 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2772 && i
.tm
.opcode_modifier
.s
2775 unsigned int xchg
= i
.operands
- 1;
2776 union i386_op temp_op
;
2777 i386_operand_type temp_type
;
2779 temp_type
= i
.types
[xchg
];
2780 i
.types
[xchg
] = i
.types
[0];
2781 i
.types
[0] = temp_type
;
2782 temp_op
= i
.op
[xchg
];
2783 i
.op
[xchg
] = i
.op
[0];
2786 gas_assert (i
.rm
.mode
== 3);
2790 i
.rm
.regmem
= i
.rm
.reg
;
2793 /* Use the next insn. */
2797 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2798 vector_length
= avxscalar
;
2800 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2802 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2807 case DATA_PREFIX_OPCODE
:
2810 case REPE_PREFIX_OPCODE
:
2813 case REPNE_PREFIX_OPCODE
:
2820 /* Use 2-byte VEX prefix if possible. */
2821 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2822 && i
.tm
.opcode_modifier
.vexw
!= VEXW1
2823 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2825 /* 2-byte VEX prefix. */
2829 i
.vex
.bytes
[0] = 0xc5;
2831 /* Check the REX.R bit. */
2832 r
= (i
.rex
& REX_R
) ? 0 : 1;
2833 i
.vex
.bytes
[1] = (r
<< 7
2834 | register_specifier
<< 3
2835 | vector_length
<< 2
2840 /* 3-byte VEX prefix. */
2845 switch (i
.tm
.opcode_modifier
.vexopcode
)
2849 i
.vex
.bytes
[0] = 0xc4;
2853 i
.vex
.bytes
[0] = 0xc4;
2857 i
.vex
.bytes
[0] = 0xc4;
2861 i
.vex
.bytes
[0] = 0x8f;
2865 i
.vex
.bytes
[0] = 0x8f;
2869 i
.vex
.bytes
[0] = 0x8f;
2875 /* The high 3 bits of the second VEX byte are 1's compliment
2876 of RXB bits from REX. */
2877 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2879 /* Check the REX.W bit. */
2880 w
= (i
.rex
& REX_W
) ? 1 : 0;
2881 if (i
.tm
.opcode_modifier
.vexw
)
2886 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2890 i
.vex
.bytes
[2] = (w
<< 7
2891 | register_specifier
<< 3
2892 | vector_length
<< 2
2898 process_immext (void)
2902 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2904 /* SSE3 Instructions have the fixed operands with an opcode
2905 suffix which is coded in the same place as an 8-bit immediate
2906 field would be. Here we check those operands and remove them
2910 for (x
= 0; x
< i
.operands
; x
++)
2911 if (i
.op
[x
].regs
->reg_num
!= x
)
2912 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2913 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2919 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2920 which is coded in the same place as an 8-bit immediate field
2921 would be. Here we fake an 8-bit immediate operand from the
2922 opcode suffix stored in tm.extension_opcode.
2924 AVX instructions also use this encoding, for some of
2925 3 argument instructions. */
2927 gas_assert (i
.imm_operands
== 0
2929 || (i
.tm
.opcode_modifier
.vex
2930 && i
.operands
<= 4)));
2932 exp
= &im_expressions
[i
.imm_operands
++];
2933 i
.op
[i
.operands
].imms
= exp
;
2934 i
.types
[i
.operands
] = imm8
;
2936 exp
->X_op
= O_constant
;
2937 exp
->X_add_number
= i
.tm
.extension_opcode
;
2938 i
.tm
.extension_opcode
= None
;
2941 /* This is the guts of the machine-dependent assembler. LINE points to a
2942 machine dependent instruction. This function is supposed to emit
2943 the frags/bytes it assembles to. */
2946 md_assemble (char *line
)
2949 char mnemonic
[MAX_MNEM_SIZE
];
2950 const insn_template
*t
;
2952 /* Initialize globals. */
2953 memset (&i
, '\0', sizeof (i
));
2954 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2955 i
.reloc
[j
] = NO_RELOC
;
2956 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2957 memset (im_expressions
, '\0', sizeof (im_expressions
));
2958 save_stack_p
= save_stack
;
2960 /* First parse an instruction mnemonic & call i386_operand for the operands.
2961 We assume that the scrubber has arranged it so that line[0] is the valid
2962 start of a (possibly prefixed) mnemonic. */
2964 line
= parse_insn (line
, mnemonic
);
2968 line
= parse_operands (line
, mnemonic
);
2973 /* Now we've parsed the mnemonic into a set of templates, and have the
2974 operands at hand. */
2976 /* All intel opcodes have reversed operands except for "bound" and
2977 "enter". We also don't reverse intersegment "jmp" and "call"
2978 instructions with 2 immediate operands so that the immediate segment
2979 precedes the offset, as it does when in AT&T mode. */
2982 && (strcmp (mnemonic
, "bound") != 0)
2983 && (strcmp (mnemonic
, "invlpga") != 0)
2984 && !(operand_type_check (i
.types
[0], imm
)
2985 && operand_type_check (i
.types
[1], imm
)))
2988 /* The order of the immediates should be reversed
2989 for 2 immediates extrq and insertq instructions */
2990 if (i
.imm_operands
== 2
2991 && (strcmp (mnemonic
, "extrq") == 0
2992 || strcmp (mnemonic
, "insertq") == 0))
2993 swap_2_operands (0, 1);
2998 /* Don't optimize displacement for movabs since it only takes 64bit
3001 && !i
.disp32_encoding
3002 && (flag_code
!= CODE_64BIT
3003 || strcmp (mnemonic
, "movabs") != 0))
3006 /* Next, we find a template that matches the given insn,
3007 making sure the overlap of the given operands types is consistent
3008 with the template operand types. */
3010 if (!(t
= match_template ()))
3013 if (sse_check
!= sse_check_none
3014 && !i
.tm
.opcode_modifier
.noavx
3015 && (i
.tm
.cpu_flags
.bitfield
.cpusse
3016 || i
.tm
.cpu_flags
.bitfield
.cpusse2
3017 || i
.tm
.cpu_flags
.bitfield
.cpusse3
3018 || i
.tm
.cpu_flags
.bitfield
.cpussse3
3019 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
3020 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
3022 (sse_check
== sse_check_warning
3024 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
3027 /* Zap movzx and movsx suffix. The suffix has been set from
3028 "word ptr" or "byte ptr" on the source operand in Intel syntax
3029 or extracted from mnemonic in AT&T syntax. But we'll use
3030 the destination register to choose the suffix for encoding. */
3031 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
3033 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
3034 there is no suffix, the default will be byte extension. */
3035 if (i
.reg_operands
!= 2
3038 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
3043 if (i
.tm
.opcode_modifier
.fwait
)
3044 if (!add_prefix (FWAIT_OPCODE
))
3047 /* Check for lock without a lockable instruction. Destination operand
3048 must be memory unless it is xchg (0x86). */
3049 if (i
.prefix
[LOCK_PREFIX
]
3050 && (!i
.tm
.opcode_modifier
.islockable
3051 || i
.mem_operands
== 0
3052 || (i
.tm
.base_opcode
!= 0x86
3053 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3055 as_bad (_("expecting lockable instruction after `lock'"));
3059 /* Check string instruction segment overrides. */
3060 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3062 if (!check_string ())
3064 i
.disp_operands
= 0;
3067 if (!process_suffix ())
3070 /* Update operand types. */
3071 for (j
= 0; j
< i
.operands
; j
++)
3072 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3074 /* Make still unresolved immediate matches conform to size of immediate
3075 given in i.suffix. */
3076 if (!finalize_imm ())
3079 if (i
.types
[0].bitfield
.imm1
)
3080 i
.imm_operands
= 0; /* kludge for shift insns. */
3082 /* We only need to check those implicit registers for instructions
3083 with 3 operands or less. */
3084 if (i
.operands
<= 3)
3085 for (j
= 0; j
< i
.operands
; j
++)
3086 if (i
.types
[j
].bitfield
.inoutportreg
3087 || i
.types
[j
].bitfield
.shiftcount
3088 || i
.types
[j
].bitfield
.acc
3089 || i
.types
[j
].bitfield
.floatacc
)
3092 /* ImmExt should be processed after SSE2AVX. */
3093 if (!i
.tm
.opcode_modifier
.sse2avx
3094 && i
.tm
.opcode_modifier
.immext
)
3097 /* For insns with operands there are more diddles to do to the opcode. */
3100 if (!process_operands ())
3103 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3105 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3106 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3109 if (i
.tm
.opcode_modifier
.vex
)
3110 build_vex_prefix (t
);
3112 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3113 instructions may define INT_OPCODE as well, so avoid this corner
3114 case for those instructions that use MODRM. */
3115 if (i
.tm
.base_opcode
== INT_OPCODE
3116 && !i
.tm
.opcode_modifier
.modrm
3117 && i
.op
[0].imms
->X_add_number
== 3)
3119 i
.tm
.base_opcode
= INT3_OPCODE
;
3123 if ((i
.tm
.opcode_modifier
.jump
3124 || i
.tm
.opcode_modifier
.jumpbyte
3125 || i
.tm
.opcode_modifier
.jumpdword
)
3126 && i
.op
[0].disps
->X_op
== O_constant
)
3128 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3129 the absolute address given by the constant. Since ix86 jumps and
3130 calls are pc relative, we need to generate a reloc. */
3131 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3132 i
.op
[0].disps
->X_op
= O_symbol
;
3135 if (i
.tm
.opcode_modifier
.rex64
)
3138 /* For 8 bit registers we need an empty rex prefix. Also if the
3139 instruction already has a prefix, we need to convert old
3140 registers to new ones. */
3142 if ((i
.types
[0].bitfield
.reg8
3143 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3144 || (i
.types
[1].bitfield
.reg8
3145 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3146 || ((i
.types
[0].bitfield
.reg8
3147 || i
.types
[1].bitfield
.reg8
)
3152 i
.rex
|= REX_OPCODE
;
3153 for (x
= 0; x
< 2; x
++)
3155 /* Look for 8 bit operand that uses old registers. */
3156 if (i
.types
[x
].bitfield
.reg8
3157 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3159 /* In case it is "hi" register, give up. */
3160 if (i
.op
[x
].regs
->reg_num
> 3)
3161 as_bad (_("can't encode register '%s%s' in an "
3162 "instruction requiring REX prefix."),
3163 register_prefix
, i
.op
[x
].regs
->reg_name
);
3165 /* Otherwise it is equivalent to the extended register.
3166 Since the encoding doesn't change this is merely
3167 cosmetic cleanup for debug output. */
3169 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3175 add_prefix (REX_OPCODE
| i
.rex
);
3177 /* We are ready to output the insn. */
3182 parse_insn (char *line
, char *mnemonic
)
3185 char *token_start
= l
;
3188 const insn_template
*t
;
3191 /* Non-zero if we found a prefix only acceptable with string insns. */
3192 const char *expecting_string_instruction
= NULL
;
3197 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3202 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3204 as_bad (_("no such instruction: `%s'"), token_start
);
3209 if (!is_space_char (*l
)
3210 && *l
!= END_OF_INSN
3212 || (*l
!= PREFIX_SEPARATOR
3215 as_bad (_("invalid character %s in mnemonic"),
3216 output_invalid (*l
));
3219 if (token_start
== l
)
3221 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3222 as_bad (_("expecting prefix; got nothing"));
3224 as_bad (_("expecting mnemonic; got nothing"));
3228 /* Look up instruction (or prefix) via hash table. */
3229 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3231 if (*l
!= END_OF_INSN
3232 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3233 && current_templates
3234 && current_templates
->start
->opcode_modifier
.isprefix
)
3236 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3238 as_bad ((flag_code
!= CODE_64BIT
3239 ? _("`%s' is only supported in 64-bit mode")
3240 : _("`%s' is not supported in 64-bit mode")),
3241 current_templates
->start
->name
);
3244 /* If we are in 16-bit mode, do not allow addr16 or data16.
3245 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3246 if ((current_templates
->start
->opcode_modifier
.size16
3247 || current_templates
->start
->opcode_modifier
.size32
)
3248 && flag_code
!= CODE_64BIT
3249 && (current_templates
->start
->opcode_modifier
.size32
3250 ^ (flag_code
== CODE_16BIT
)))
3252 as_bad (_("redundant %s prefix"),
3253 current_templates
->start
->name
);
3256 /* Add prefix, checking for repeated prefixes. */
3257 switch (add_prefix (current_templates
->start
->base_opcode
))
3262 expecting_string_instruction
= current_templates
->start
->name
;
3267 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3274 if (!current_templates
)
3276 /* Check if we should swap operand or force 32bit displacement in
3278 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3280 else if (mnem_p
- 4 == dot_p
3284 i
.disp32_encoding
= 1;
3289 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3292 if (!current_templates
)
3295 /* See if we can get a match by trimming off a suffix. */
3298 case WORD_MNEM_SUFFIX
:
3299 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3300 i
.suffix
= SHORT_MNEM_SUFFIX
;
3302 case BYTE_MNEM_SUFFIX
:
3303 case QWORD_MNEM_SUFFIX
:
3304 i
.suffix
= mnem_p
[-1];
3306 current_templates
= (const templates
*) hash_find (op_hash
,
3309 case SHORT_MNEM_SUFFIX
:
3310 case LONG_MNEM_SUFFIX
:
3313 i
.suffix
= mnem_p
[-1];
3315 current_templates
= (const templates
*) hash_find (op_hash
,
3324 if (intel_float_operand (mnemonic
) == 1)
3325 i
.suffix
= SHORT_MNEM_SUFFIX
;
3327 i
.suffix
= LONG_MNEM_SUFFIX
;
3329 current_templates
= (const templates
*) hash_find (op_hash
,
3334 if (!current_templates
)
3336 as_bad (_("no such instruction: `%s'"), token_start
);
3341 if (current_templates
->start
->opcode_modifier
.jump
3342 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3344 /* Check for a branch hint. We allow ",pt" and ",pn" for
3345 predict taken and predict not taken respectively.
3346 I'm not sure that branch hints actually do anything on loop
3347 and jcxz insns (JumpByte) for current Pentium4 chips. They
3348 may work in the future and it doesn't hurt to accept them
3350 if (l
[0] == ',' && l
[1] == 'p')
3354 if (!add_prefix (DS_PREFIX_OPCODE
))
3358 else if (l
[2] == 'n')
3360 if (!add_prefix (CS_PREFIX_OPCODE
))
3366 /* Any other comma loses. */
3369 as_bad (_("invalid character %s in mnemonic"),
3370 output_invalid (*l
));
3374 /* Check if instruction is supported on specified architecture. */
3376 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3378 supported
|= cpu_flags_match (t
);
3379 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3383 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3385 as_bad (flag_code
== CODE_64BIT
3386 ? _("`%s' is not supported in 64-bit mode")
3387 : _("`%s' is only supported in 64-bit mode"),
3388 current_templates
->start
->name
);
3391 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3393 as_bad (_("`%s' is not supported on `%s%s'"),
3394 current_templates
->start
->name
,
3395 cpu_arch_name
? cpu_arch_name
: default_arch
,
3396 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3401 if (!cpu_arch_flags
.bitfield
.cpui386
3402 && (flag_code
!= CODE_16BIT
))
3404 as_warn (_("use .code16 to ensure correct addressing mode"));
3407 /* Check for rep/repne without a string instruction. */
3408 if (expecting_string_instruction
)
3410 static templates override
;
3412 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3413 if (t
->opcode_modifier
.isstring
)
3415 if (t
>= current_templates
->end
)
3417 as_bad (_("expecting string instruction after `%s'"),
3418 expecting_string_instruction
);
3421 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3422 if (!t
->opcode_modifier
.isstring
)
3425 current_templates
= &override
;
3432 parse_operands (char *l
, const char *mnemonic
)
3436 /* 1 if operand is pending after ','. */
3437 unsigned int expecting_operand
= 0;
3439 /* Non-zero if operand parens not balanced. */
3440 unsigned int paren_not_balanced
;
3442 while (*l
!= END_OF_INSN
)
3444 /* Skip optional white space before operand. */
3445 if (is_space_char (*l
))
3447 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3449 as_bad (_("invalid character %s before operand %d"),
3450 output_invalid (*l
),
3454 token_start
= l
; /* after white space */
3455 paren_not_balanced
= 0;
3456 while (paren_not_balanced
|| *l
!= ',')
3458 if (*l
== END_OF_INSN
)
3460 if (paren_not_balanced
)
3463 as_bad (_("unbalanced parenthesis in operand %d."),
3466 as_bad (_("unbalanced brackets in operand %d."),
3471 break; /* we are done */
3473 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3475 as_bad (_("invalid character %s in operand %d"),
3476 output_invalid (*l
),
3483 ++paren_not_balanced
;
3485 --paren_not_balanced
;
3490 ++paren_not_balanced
;
3492 --paren_not_balanced
;
3496 if (l
!= token_start
)
3497 { /* Yes, we've read in another operand. */
3498 unsigned int operand_ok
;
3499 this_operand
= i
.operands
++;
3500 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3501 if (i
.operands
> MAX_OPERANDS
)
3503 as_bad (_("spurious operands; (%d operands/instruction max)"),
3507 /* Now parse operand adding info to 'i' as we go along. */
3508 END_STRING_AND_SAVE (l
);
3512 i386_intel_operand (token_start
,
3513 intel_float_operand (mnemonic
));
3515 operand_ok
= i386_att_operand (token_start
);
3517 RESTORE_END_STRING (l
);
3523 if (expecting_operand
)
3525 expecting_operand_after_comma
:
3526 as_bad (_("expecting operand after ','; got nothing"));
3531 as_bad (_("expecting operand before ','; got nothing"));
3536 /* Now *l must be either ',' or END_OF_INSN. */
3539 if (*++l
== END_OF_INSN
)
3541 /* Just skip it, if it's \n complain. */
3542 goto expecting_operand_after_comma
;
3544 expecting_operand
= 1;
3551 swap_2_operands (int xchg1
, int xchg2
)
3553 union i386_op temp_op
;
3554 i386_operand_type temp_type
;
3555 enum bfd_reloc_code_real temp_reloc
;
3557 temp_type
= i
.types
[xchg2
];
3558 i
.types
[xchg2
] = i
.types
[xchg1
];
3559 i
.types
[xchg1
] = temp_type
;
3560 temp_op
= i
.op
[xchg2
];
3561 i
.op
[xchg2
] = i
.op
[xchg1
];
3562 i
.op
[xchg1
] = temp_op
;
3563 temp_reloc
= i
.reloc
[xchg2
];
3564 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3565 i
.reloc
[xchg1
] = temp_reloc
;
3569 swap_operands (void)
3575 swap_2_operands (1, i
.operands
- 2);
3578 swap_2_operands (0, i
.operands
- 1);
3584 if (i
.mem_operands
== 2)
3586 const seg_entry
*temp_seg
;
3587 temp_seg
= i
.seg
[0];
3588 i
.seg
[0] = i
.seg
[1];
3589 i
.seg
[1] = temp_seg
;
3593 /* Try to ensure constant immediates are represented in the smallest
3598 char guess_suffix
= 0;
3602 guess_suffix
= i
.suffix
;
3603 else if (i
.reg_operands
)
3605 /* Figure out a suffix from the last register operand specified.
3606 We can't do this properly yet, ie. excluding InOutPortReg,
3607 but the following works for instructions with immediates.
3608 In any case, we can't set i.suffix yet. */
3609 for (op
= i
.operands
; --op
>= 0;)
3610 if (i
.types
[op
].bitfield
.reg8
)
3612 guess_suffix
= BYTE_MNEM_SUFFIX
;
3615 else if (i
.types
[op
].bitfield
.reg16
)
3617 guess_suffix
= WORD_MNEM_SUFFIX
;
3620 else if (i
.types
[op
].bitfield
.reg32
)
3622 guess_suffix
= LONG_MNEM_SUFFIX
;
3625 else if (i
.types
[op
].bitfield
.reg64
)
3627 guess_suffix
= QWORD_MNEM_SUFFIX
;
3631 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3632 guess_suffix
= WORD_MNEM_SUFFIX
;
3634 for (op
= i
.operands
; --op
>= 0;)
3635 if (operand_type_check (i
.types
[op
], imm
))
3637 switch (i
.op
[op
].imms
->X_op
)
3640 /* If a suffix is given, this operand may be shortened. */
3641 switch (guess_suffix
)
3643 case LONG_MNEM_SUFFIX
:
3644 i
.types
[op
].bitfield
.imm32
= 1;
3645 i
.types
[op
].bitfield
.imm64
= 1;
3647 case WORD_MNEM_SUFFIX
:
3648 i
.types
[op
].bitfield
.imm16
= 1;
3649 i
.types
[op
].bitfield
.imm32
= 1;
3650 i
.types
[op
].bitfield
.imm32s
= 1;
3651 i
.types
[op
].bitfield
.imm64
= 1;
3653 case BYTE_MNEM_SUFFIX
:
3654 i
.types
[op
].bitfield
.imm8
= 1;
3655 i
.types
[op
].bitfield
.imm8s
= 1;
3656 i
.types
[op
].bitfield
.imm16
= 1;
3657 i
.types
[op
].bitfield
.imm32
= 1;
3658 i
.types
[op
].bitfield
.imm32s
= 1;
3659 i
.types
[op
].bitfield
.imm64
= 1;
3663 /* If this operand is at most 16 bits, convert it
3664 to a signed 16 bit number before trying to see
3665 whether it will fit in an even smaller size.
3666 This allows a 16-bit operand such as $0xffe0 to
3667 be recognised as within Imm8S range. */
3668 if ((i
.types
[op
].bitfield
.imm16
)
3669 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3671 i
.op
[op
].imms
->X_add_number
=
3672 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3674 if ((i
.types
[op
].bitfield
.imm32
)
3675 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3678 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3679 ^ ((offsetT
) 1 << 31))
3680 - ((offsetT
) 1 << 31));
3683 = operand_type_or (i
.types
[op
],
3684 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3686 /* We must avoid matching of Imm32 templates when 64bit
3687 only immediate is available. */
3688 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3689 i
.types
[op
].bitfield
.imm32
= 0;
3696 /* Symbols and expressions. */
3698 /* Convert symbolic operand to proper sizes for matching, but don't
3699 prevent matching a set of insns that only supports sizes other
3700 than those matching the insn suffix. */
3702 i386_operand_type mask
, allowed
;
3703 const insn_template
*t
;
3705 operand_type_set (&mask
, 0);
3706 operand_type_set (&allowed
, 0);
3708 for (t
= current_templates
->start
;
3709 t
< current_templates
->end
;
3711 allowed
= operand_type_or (allowed
,
3712 t
->operand_types
[op
]);
3713 switch (guess_suffix
)
3715 case QWORD_MNEM_SUFFIX
:
3716 mask
.bitfield
.imm64
= 1;
3717 mask
.bitfield
.imm32s
= 1;
3719 case LONG_MNEM_SUFFIX
:
3720 mask
.bitfield
.imm32
= 1;
3722 case WORD_MNEM_SUFFIX
:
3723 mask
.bitfield
.imm16
= 1;
3725 case BYTE_MNEM_SUFFIX
:
3726 mask
.bitfield
.imm8
= 1;
3731 allowed
= operand_type_and (mask
, allowed
);
3732 if (!operand_type_all_zero (&allowed
))
3733 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3740 /* Try to use the smallest displacement type too. */
3742 optimize_disp (void)
3746 for (op
= i
.operands
; --op
>= 0;)
3747 if (operand_type_check (i
.types
[op
], disp
))
3749 if (i
.op
[op
].disps
->X_op
== O_constant
)
3751 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3753 if (i
.types
[op
].bitfield
.disp16
3754 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3756 /* If this operand is at most 16 bits, convert
3757 to a signed 16 bit number and don't use 64bit
3759 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3760 i
.types
[op
].bitfield
.disp64
= 0;
3762 if (i
.types
[op
].bitfield
.disp32
3763 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3765 /* If this operand is at most 32 bits, convert
3766 to a signed 32 bit number and don't use 64bit
3768 op_disp
&= (((offsetT
) 2 << 31) - 1);
3769 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3770 i
.types
[op
].bitfield
.disp64
= 0;
3772 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3774 i
.types
[op
].bitfield
.disp8
= 0;
3775 i
.types
[op
].bitfield
.disp16
= 0;
3776 i
.types
[op
].bitfield
.disp32
= 0;
3777 i
.types
[op
].bitfield
.disp32s
= 0;
3778 i
.types
[op
].bitfield
.disp64
= 0;
3782 else if (flag_code
== CODE_64BIT
)
3784 if (fits_in_signed_long (op_disp
))
3786 i
.types
[op
].bitfield
.disp64
= 0;
3787 i
.types
[op
].bitfield
.disp32s
= 1;
3789 if (i
.prefix
[ADDR_PREFIX
]
3790 && fits_in_unsigned_long (op_disp
))
3791 i
.types
[op
].bitfield
.disp32
= 1;
3793 if ((i
.types
[op
].bitfield
.disp32
3794 || i
.types
[op
].bitfield
.disp32s
3795 || i
.types
[op
].bitfield
.disp16
)
3796 && fits_in_signed_byte (op_disp
))
3797 i
.types
[op
].bitfield
.disp8
= 1;
3799 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3800 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3802 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3803 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3804 i
.types
[op
].bitfield
.disp8
= 0;
3805 i
.types
[op
].bitfield
.disp16
= 0;
3806 i
.types
[op
].bitfield
.disp32
= 0;
3807 i
.types
[op
].bitfield
.disp32s
= 0;
3808 i
.types
[op
].bitfield
.disp64
= 0;
3811 /* We only support 64bit displacement on constants. */
3812 i
.types
[op
].bitfield
.disp64
= 0;
3816 /* Check if operands are valid for the instruction. Update VEX
3820 VEX_check_operands (const insn_template
*t
)
3822 if (!t
->opcode_modifier
.vex
)
3825 /* Only check VEX_Imm4, which must be the first operand. */
3826 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3828 if (i
.op
[0].imms
->X_op
!= O_constant
3829 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3835 /* Turn off Imm8 so that update_imm won't complain. */
3836 i
.types
[0] = vec_imm4
;
3842 static const insn_template
*
3843 match_template (void)
3845 /* Points to template once we've found it. */
3846 const insn_template
*t
;
3847 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3848 i386_operand_type overlap4
;
3849 unsigned int found_reverse_match
;
3850 i386_opcode_modifier suffix_check
;
3851 i386_operand_type operand_types
[MAX_OPERANDS
];
3852 int addr_prefix_disp
;
3854 unsigned int found_cpu_match
;
3855 unsigned int check_register
;
3857 #if MAX_OPERANDS != 5
3858 # error "MAX_OPERANDS must be 5."
3861 found_reverse_match
= 0;
3862 addr_prefix_disp
= -1;
3864 memset (&suffix_check
, 0, sizeof (suffix_check
));
3865 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3866 suffix_check
.no_bsuf
= 1;
3867 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3868 suffix_check
.no_wsuf
= 1;
3869 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3870 suffix_check
.no_ssuf
= 1;
3871 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3872 suffix_check
.no_lsuf
= 1;
3873 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3874 suffix_check
.no_qsuf
= 1;
3875 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3876 suffix_check
.no_ldsuf
= 1;
3878 /* Must have right number of operands. */
3879 i
.error
= number_of_operands_mismatch
;
3881 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3883 addr_prefix_disp
= -1;
3885 if (i
.operands
!= t
->operands
)
3888 /* Check processor support. */
3889 i
.error
= unsupported
;
3890 found_cpu_match
= (cpu_flags_match (t
)
3891 == CPU_FLAGS_PERFECT_MATCH
);
3892 if (!found_cpu_match
)
3895 /* Check old gcc support. */
3896 i
.error
= old_gcc_only
;
3897 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3900 /* Check AT&T mnemonic. */
3901 i
.error
= unsupported_with_intel_mnemonic
;
3902 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3905 /* Check AT&T/Intel syntax. */
3906 i
.error
= unsupported_syntax
;
3907 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3908 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3911 /* Check the suffix, except for some instructions in intel mode. */
3912 i
.error
= invalid_instruction_suffix
;
3913 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3914 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3915 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3916 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3917 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3918 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3919 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3922 if (!operand_size_match (t
))
3925 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3926 operand_types
[j
] = t
->operand_types
[j
];
3928 /* In general, don't allow 64-bit operands in 32-bit mode. */
3929 if (i
.suffix
== QWORD_MNEM_SUFFIX
3930 && flag_code
!= CODE_64BIT
3932 ? (!t
->opcode_modifier
.ignoresize
3933 && !intel_float_operand (t
->name
))
3934 : intel_float_operand (t
->name
) != 2)
3935 && ((!operand_types
[0].bitfield
.regmmx
3936 && !operand_types
[0].bitfield
.regxmm
3937 && !operand_types
[0].bitfield
.regymm
)
3938 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3939 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3940 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3941 && (t
->base_opcode
!= 0x0fc7
3942 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3945 /* In general, don't allow 32-bit operands on pre-386. */
3946 else if (i
.suffix
== LONG_MNEM_SUFFIX
3947 && !cpu_arch_flags
.bitfield
.cpui386
3949 ? (!t
->opcode_modifier
.ignoresize
3950 && !intel_float_operand (t
->name
))
3951 : intel_float_operand (t
->name
) != 2)
3952 && ((!operand_types
[0].bitfield
.regmmx
3953 && !operand_types
[0].bitfield
.regxmm
)
3954 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3955 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3958 /* Do not verify operands when there are none. */
3962 /* We've found a match; break out of loop. */
3966 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3967 into Disp32/Disp16/Disp32 operand. */
3968 if (i
.prefix
[ADDR_PREFIX
] != 0)
3970 /* There should be only one Disp operand. */
3974 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3976 if (operand_types
[j
].bitfield
.disp16
)
3978 addr_prefix_disp
= j
;
3979 operand_types
[j
].bitfield
.disp32
= 1;
3980 operand_types
[j
].bitfield
.disp16
= 0;
3986 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3988 if (operand_types
[j
].bitfield
.disp32
)
3990 addr_prefix_disp
= j
;
3991 operand_types
[j
].bitfield
.disp32
= 0;
3992 operand_types
[j
].bitfield
.disp16
= 1;
3998 for (j
= 0; j
< MAX_OPERANDS
; j
++)
4000 if (operand_types
[j
].bitfield
.disp64
)
4002 addr_prefix_disp
= j
;
4003 operand_types
[j
].bitfield
.disp64
= 0;
4004 operand_types
[j
].bitfield
.disp32
= 1;
4012 /* We check register size if needed. */
4013 check_register
= t
->opcode_modifier
.checkregsize
;
4014 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
4015 switch (t
->operands
)
4018 if (!operand_type_match (overlap0
, i
.types
[0]))
4022 /* xchg %eax, %eax is a special case. It is an aliase for nop
4023 only in 32bit mode and we can use opcode 0x90. In 64bit
4024 mode, we can't use 0x90 for xchg %eax, %eax since it should
4025 zero-extend %eax to %rax. */
4026 if (flag_code
== CODE_64BIT
4027 && t
->base_opcode
== 0x90
4028 && operand_type_equal (&i
.types
[0], &acc32
)
4029 && operand_type_equal (&i
.types
[1], &acc32
))
4033 /* If we swap operand in encoding, we either match
4034 the next one or reverse direction of operands. */
4035 if (t
->opcode_modifier
.s
)
4037 else if (t
->opcode_modifier
.d
)
4042 /* If we swap operand in encoding, we match the next one. */
4043 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
4047 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
4048 if (!operand_type_match (overlap0
, i
.types
[0])
4049 || !operand_type_match (overlap1
, i
.types
[1])
4051 && !operand_type_register_match (overlap0
, i
.types
[0],
4053 overlap1
, i
.types
[1],
4056 /* Check if other direction is valid ... */
4057 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4061 /* Try reversing direction of operands. */
4062 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4063 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4064 if (!operand_type_match (overlap0
, i
.types
[0])
4065 || !operand_type_match (overlap1
, i
.types
[1])
4067 && !operand_type_register_match (overlap0
,
4074 /* Does not match either direction. */
4077 /* found_reverse_match holds which of D or FloatDR
4079 if (t
->opcode_modifier
.d
)
4080 found_reverse_match
= Opcode_D
;
4081 else if (t
->opcode_modifier
.floatd
)
4082 found_reverse_match
= Opcode_FloatD
;
4084 found_reverse_match
= 0;
4085 if (t
->opcode_modifier
.floatr
)
4086 found_reverse_match
|= Opcode_FloatR
;
4090 /* Found a forward 2 operand match here. */
4091 switch (t
->operands
)
4094 overlap4
= operand_type_and (i
.types
[4],
4097 overlap3
= operand_type_and (i
.types
[3],
4100 overlap2
= operand_type_and (i
.types
[2],
4105 switch (t
->operands
)
4108 if (!operand_type_match (overlap4
, i
.types
[4])
4109 || !operand_type_register_match (overlap3
,
4117 if (!operand_type_match (overlap3
, i
.types
[3])
4119 && !operand_type_register_match (overlap2
,
4127 /* Here we make use of the fact that there are no
4128 reverse match 3 operand instructions, and all 3
4129 operand instructions only need to be checked for
4130 register consistency between operands 2 and 3. */
4131 if (!operand_type_match (overlap2
, i
.types
[2])
4133 && !operand_type_register_match (overlap1
,
4143 /* Found either forward/reverse 2, 3 or 4 operand match here:
4144 slip through to break. */
4146 if (!found_cpu_match
)
4148 found_reverse_match
= 0;
4152 /* Check if VEX operands are valid. */
4153 if (VEX_check_operands (t
))
4156 /* We've found a match; break out of loop. */
4160 if (t
== current_templates
->end
)
4162 /* We found no match. */
4163 const char *err_msg
;
4168 case operand_size_mismatch
:
4169 err_msg
= _("operand size mismatch");
4171 case operand_type_mismatch
:
4172 err_msg
= _("operand type mismatch");
4174 case register_type_mismatch
:
4175 err_msg
= _("register type mismatch");
4177 case number_of_operands_mismatch
:
4178 err_msg
= _("number of operands mismatch");
4180 case invalid_instruction_suffix
:
4181 err_msg
= _("invalid instruction suffix");
4184 err_msg
= _("Imm4 isn't the first operand");
4187 err_msg
= _("only supported with old gcc");
4189 case unsupported_with_intel_mnemonic
:
4190 err_msg
= _("unsupported with Intel mnemonic");
4192 case unsupported_syntax
:
4193 err_msg
= _("unsupported syntax");
4196 err_msg
= _("unsupported");
4199 as_bad (_("%s for `%s'"), err_msg
,
4200 current_templates
->start
->name
);
4204 if (!quiet_warnings
)
4207 && (i
.types
[0].bitfield
.jumpabsolute
4208 != operand_types
[0].bitfield
.jumpabsolute
))
4210 as_warn (_("indirect %s without `*'"), t
->name
);
4213 if (t
->opcode_modifier
.isprefix
4214 && t
->opcode_modifier
.ignoresize
)
4216 /* Warn them that a data or address size prefix doesn't
4217 affect assembly of the next line of code. */
4218 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4222 /* Copy the template we found. */
4225 if (addr_prefix_disp
!= -1)
4226 i
.tm
.operand_types
[addr_prefix_disp
]
4227 = operand_types
[addr_prefix_disp
];
4229 if (found_reverse_match
)
4231 /* If we found a reverse match we must alter the opcode
4232 direction bit. found_reverse_match holds bits to change
4233 (different for int & float insns). */
4235 i
.tm
.base_opcode
^= found_reverse_match
;
4237 i
.tm
.operand_types
[0] = operand_types
[1];
4238 i
.tm
.operand_types
[1] = operand_types
[0];
4247 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4248 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4250 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4252 as_bad (_("`%s' operand %d must use `%ses' segment"),
4258 /* There's only ever one segment override allowed per instruction.
4259 This instruction possibly has a legal segment override on the
4260 second operand, so copy the segment to where non-string
4261 instructions store it, allowing common code. */
4262 i
.seg
[0] = i
.seg
[1];
4264 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4266 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4268 as_bad (_("`%s' operand %d must use `%ses' segment"),
4279 process_suffix (void)
4281 /* If matched instruction specifies an explicit instruction mnemonic
4283 if (i
.tm
.opcode_modifier
.size16
)
4284 i
.suffix
= WORD_MNEM_SUFFIX
;
4285 else if (i
.tm
.opcode_modifier
.size32
)
4286 i
.suffix
= LONG_MNEM_SUFFIX
;
4287 else if (i
.tm
.opcode_modifier
.size64
)
4288 i
.suffix
= QWORD_MNEM_SUFFIX
;
4289 else if (i
.reg_operands
)
4291 /* If there's no instruction mnemonic suffix we try to invent one
4292 based on register operands. */
4295 /* We take i.suffix from the last register operand specified,
4296 Destination register type is more significant than source
4297 register type. crc32 in SSE4.2 prefers source register
4299 if (i
.tm
.base_opcode
== 0xf20f38f1)
4301 if (i
.types
[0].bitfield
.reg16
)
4302 i
.suffix
= WORD_MNEM_SUFFIX
;
4303 else if (i
.types
[0].bitfield
.reg32
)
4304 i
.suffix
= LONG_MNEM_SUFFIX
;
4305 else if (i
.types
[0].bitfield
.reg64
)
4306 i
.suffix
= QWORD_MNEM_SUFFIX
;
4308 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4310 if (i
.types
[0].bitfield
.reg8
)
4311 i
.suffix
= BYTE_MNEM_SUFFIX
;
4318 if (i
.tm
.base_opcode
== 0xf20f38f1
4319 || i
.tm
.base_opcode
== 0xf20f38f0)
4321 /* We have to know the operand size for crc32. */
4322 as_bad (_("ambiguous memory operand size for `%s`"),
4327 for (op
= i
.operands
; --op
>= 0;)
4328 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4330 if (i
.types
[op
].bitfield
.reg8
)
4332 i
.suffix
= BYTE_MNEM_SUFFIX
;
4335 else if (i
.types
[op
].bitfield
.reg16
)
4337 i
.suffix
= WORD_MNEM_SUFFIX
;
4340 else if (i
.types
[op
].bitfield
.reg32
)
4342 i
.suffix
= LONG_MNEM_SUFFIX
;
4345 else if (i
.types
[op
].bitfield
.reg64
)
4347 i
.suffix
= QWORD_MNEM_SUFFIX
;
4353 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4356 && i
.tm
.opcode_modifier
.ignoresize
4357 && i
.tm
.opcode_modifier
.no_bsuf
)
4359 else if (!check_byte_reg ())
4362 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4365 && i
.tm
.opcode_modifier
.ignoresize
4366 && i
.tm
.opcode_modifier
.no_lsuf
)
4368 else if (!check_long_reg ())
4371 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4374 && i
.tm
.opcode_modifier
.ignoresize
4375 && i
.tm
.opcode_modifier
.no_qsuf
)
4377 else if (!check_qword_reg ())
4380 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4383 && i
.tm
.opcode_modifier
.ignoresize
4384 && i
.tm
.opcode_modifier
.no_wsuf
)
4386 else if (!check_word_reg ())
4389 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4390 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4392 /* Skip if the instruction has x/y suffix. match_template
4393 should check if it is a valid suffix. */
4395 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4396 /* Do nothing if the instruction is going to ignore the prefix. */
4401 else if (i
.tm
.opcode_modifier
.defaultsize
4403 /* exclude fldenv/frstor/fsave/fstenv */
4404 && i
.tm
.opcode_modifier
.no_ssuf
)
4406 i
.suffix
= stackop_size
;
4408 else if (intel_syntax
4410 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4411 || i
.tm
.opcode_modifier
.jumpbyte
4412 || i
.tm
.opcode_modifier
.jumpintersegment
4413 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4414 && i
.tm
.extension_opcode
<= 3)))
4419 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4421 i
.suffix
= QWORD_MNEM_SUFFIX
;
4425 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4426 i
.suffix
= LONG_MNEM_SUFFIX
;
4429 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4430 i
.suffix
= WORD_MNEM_SUFFIX
;
4439 if (i
.tm
.opcode_modifier
.w
)
4441 as_bad (_("no instruction mnemonic suffix given and "
4442 "no register operands; can't size instruction"));
4448 unsigned int suffixes
;
4450 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4451 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4453 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4455 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4457 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4459 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4462 /* There are more than suffix matches. */
4463 if (i
.tm
.opcode_modifier
.w
4464 || ((suffixes
& (suffixes
- 1))
4465 && !i
.tm
.opcode_modifier
.defaultsize
4466 && !i
.tm
.opcode_modifier
.ignoresize
))
4468 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4474 /* Change the opcode based on the operand size given by i.suffix;
4475 We don't need to change things for byte insns. */
4478 && i
.suffix
!= BYTE_MNEM_SUFFIX
4479 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4480 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4482 /* It's not a byte, select word/dword operation. */
4483 if (i
.tm
.opcode_modifier
.w
)
4485 if (i
.tm
.opcode_modifier
.shortform
)
4486 i
.tm
.base_opcode
|= 8;
4488 i
.tm
.base_opcode
|= 1;
4491 /* Now select between word & dword operations via the operand
4492 size prefix, except for instructions that will ignore this
4494 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4496 /* The address size override prefix changes the size of the
4498 if ((flag_code
== CODE_32BIT
4499 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4500 || (flag_code
!= CODE_32BIT
4501 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4502 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4505 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4506 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4507 && !i
.tm
.opcode_modifier
.ignoresize
4508 && !i
.tm
.opcode_modifier
.floatmf
4509 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4510 || (flag_code
== CODE_64BIT
4511 && i
.tm
.opcode_modifier
.jumpbyte
)))
4513 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4515 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4516 prefix
= ADDR_PREFIX_OPCODE
;
4518 if (!add_prefix (prefix
))
4522 /* Set mode64 for an operand. */
4523 if (i
.suffix
== QWORD_MNEM_SUFFIX
4524 && flag_code
== CODE_64BIT
4525 && !i
.tm
.opcode_modifier
.norex64
)
4527 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4528 need rex64. cmpxchg8b is also a special case. */
4529 if (! (i
.operands
== 2
4530 && i
.tm
.base_opcode
== 0x90
4531 && i
.tm
.extension_opcode
== None
4532 && operand_type_equal (&i
.types
[0], &acc64
)
4533 && operand_type_equal (&i
.types
[1], &acc64
))
4534 && ! (i
.operands
== 1
4535 && i
.tm
.base_opcode
== 0xfc7
4536 && i
.tm
.extension_opcode
== 1
4537 && !operand_type_check (i
.types
[0], reg
)
4538 && operand_type_check (i
.types
[0], anymem
)))
4542 /* Size floating point instruction. */
4543 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4544 if (i
.tm
.opcode_modifier
.floatmf
)
4545 i
.tm
.base_opcode
^= 4;
4552 check_byte_reg (void)
4556 for (op
= i
.operands
; --op
>= 0;)
4558 /* If this is an eight bit register, it's OK. If it's the 16 or
4559 32 bit version of an eight bit register, we will just use the
4560 low portion, and that's OK too. */
4561 if (i
.types
[op
].bitfield
.reg8
)
4564 /* crc32 doesn't generate this warning. */
4565 if (i
.tm
.base_opcode
== 0xf20f38f0)
4568 if ((i
.types
[op
].bitfield
.reg16
4569 || i
.types
[op
].bitfield
.reg32
4570 || i
.types
[op
].bitfield
.reg64
)
4571 && i
.op
[op
].regs
->reg_num
< 4)
4573 /* Prohibit these changes in the 64bit mode, since the
4574 lowering is more complicated. */
4575 if (flag_code
== CODE_64BIT
4576 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4578 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4579 register_prefix
, i
.op
[op
].regs
->reg_name
,
4583 #if REGISTER_WARNINGS
4585 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4586 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4588 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4589 ? REGNAM_AL
- REGNAM_AX
4590 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4592 i
.op
[op
].regs
->reg_name
,
4597 /* Any other register is bad. */
4598 if (i
.types
[op
].bitfield
.reg16
4599 || i
.types
[op
].bitfield
.reg32
4600 || i
.types
[op
].bitfield
.reg64
4601 || i
.types
[op
].bitfield
.regmmx
4602 || i
.types
[op
].bitfield
.regxmm
4603 || i
.types
[op
].bitfield
.regymm
4604 || i
.types
[op
].bitfield
.sreg2
4605 || i
.types
[op
].bitfield
.sreg3
4606 || i
.types
[op
].bitfield
.control
4607 || i
.types
[op
].bitfield
.debug
4608 || i
.types
[op
].bitfield
.test
4609 || i
.types
[op
].bitfield
.floatreg
4610 || i
.types
[op
].bitfield
.floatacc
)
4612 as_bad (_("`%s%s' not allowed with `%s%c'"),
4614 i
.op
[op
].regs
->reg_name
,
4624 check_long_reg (void)
4628 for (op
= i
.operands
; --op
>= 0;)
4629 /* Reject eight bit registers, except where the template requires
4630 them. (eg. movzb) */
4631 if (i
.types
[op
].bitfield
.reg8
4632 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4633 || i
.tm
.operand_types
[op
].bitfield
.reg32
4634 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4636 as_bad (_("`%s%s' not allowed with `%s%c'"),
4638 i
.op
[op
].regs
->reg_name
,
4643 /* Warn if the e prefix on a general reg is missing. */
4644 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4645 && i
.types
[op
].bitfield
.reg16
4646 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4647 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4649 /* Prohibit these changes in the 64bit mode, since the
4650 lowering is more complicated. */
4651 if (flag_code
== CODE_64BIT
)
4653 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4654 register_prefix
, i
.op
[op
].regs
->reg_name
,
4658 #if REGISTER_WARNINGS
4660 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4662 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4664 i
.op
[op
].regs
->reg_name
,
4668 /* Warn if the r prefix on a general reg is missing. */
4669 else if (i
.types
[op
].bitfield
.reg64
4670 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4671 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4674 && i
.tm
.opcode_modifier
.toqword
4675 && !i
.types
[0].bitfield
.regxmm
)
4677 /* Convert to QWORD. We want REX byte. */
4678 i
.suffix
= QWORD_MNEM_SUFFIX
;
4682 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4683 register_prefix
, i
.op
[op
].regs
->reg_name
,
4692 check_qword_reg (void)
4696 for (op
= i
.operands
; --op
>= 0; )
4697 /* Reject eight bit registers, except where the template requires
4698 them. (eg. movzb) */
4699 if (i
.types
[op
].bitfield
.reg8
4700 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4701 || i
.tm
.operand_types
[op
].bitfield
.reg32
4702 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4704 as_bad (_("`%s%s' not allowed with `%s%c'"),
4706 i
.op
[op
].regs
->reg_name
,
4711 /* Warn if the e prefix on a general reg is missing. */
4712 else if ((i
.types
[op
].bitfield
.reg16
4713 || i
.types
[op
].bitfield
.reg32
)
4714 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4715 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4717 /* Prohibit these changes in the 64bit mode, since the
4718 lowering is more complicated. */
4720 && i
.tm
.opcode_modifier
.todword
4721 && !i
.types
[0].bitfield
.regxmm
)
4723 /* Convert to DWORD. We don't want REX byte. */
4724 i
.suffix
= LONG_MNEM_SUFFIX
;
4728 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4729 register_prefix
, i
.op
[op
].regs
->reg_name
,
4738 check_word_reg (void)
4741 for (op
= i
.operands
; --op
>= 0;)
4742 /* Reject eight bit registers, except where the template requires
4743 them. (eg. movzb) */
4744 if (i
.types
[op
].bitfield
.reg8
4745 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4746 || i
.tm
.operand_types
[op
].bitfield
.reg32
4747 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4749 as_bad (_("`%s%s' not allowed with `%s%c'"),
4751 i
.op
[op
].regs
->reg_name
,
4756 /* Warn if the e prefix on a general reg is present. */
4757 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4758 && i
.types
[op
].bitfield
.reg32
4759 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4760 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4762 /* Prohibit these changes in the 64bit mode, since the
4763 lowering is more complicated. */
4764 if (flag_code
== CODE_64BIT
)
4766 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4767 register_prefix
, i
.op
[op
].regs
->reg_name
,
4772 #if REGISTER_WARNINGS
4773 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4775 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4777 i
.op
[op
].regs
->reg_name
,
4785 update_imm (unsigned int j
)
4787 i386_operand_type overlap
= i
.types
[j
];
4788 if ((overlap
.bitfield
.imm8
4789 || overlap
.bitfield
.imm8s
4790 || overlap
.bitfield
.imm16
4791 || overlap
.bitfield
.imm32
4792 || overlap
.bitfield
.imm32s
4793 || overlap
.bitfield
.imm64
)
4794 && !operand_type_equal (&overlap
, &imm8
)
4795 && !operand_type_equal (&overlap
, &imm8s
)
4796 && !operand_type_equal (&overlap
, &imm16
)
4797 && !operand_type_equal (&overlap
, &imm32
)
4798 && !operand_type_equal (&overlap
, &imm32s
)
4799 && !operand_type_equal (&overlap
, &imm64
))
4803 i386_operand_type temp
;
4805 operand_type_set (&temp
, 0);
4806 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4808 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4809 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4811 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4812 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4813 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4815 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4816 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4819 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4822 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4823 || operand_type_equal (&overlap
, &imm16_32
)
4824 || operand_type_equal (&overlap
, &imm16_32s
))
4826 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4831 if (!operand_type_equal (&overlap
, &imm8
)
4832 && !operand_type_equal (&overlap
, &imm8s
)
4833 && !operand_type_equal (&overlap
, &imm16
)
4834 && !operand_type_equal (&overlap
, &imm32
)
4835 && !operand_type_equal (&overlap
, &imm32s
)
4836 && !operand_type_equal (&overlap
, &imm64
))
4838 as_bad (_("no instruction mnemonic suffix given; "
4839 "can't determine immediate size"));
4843 i
.types
[j
] = overlap
;
4853 /* Update the first 2 immediate operands. */
4854 n
= i
.operands
> 2 ? 2 : i
.operands
;
4857 for (j
= 0; j
< n
; j
++)
4858 if (update_imm (j
) == 0)
4861 /* The 3rd operand can't be immediate operand. */
4862 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4869 bad_implicit_operand (int xmm
)
4871 const char *ireg
= xmm
? "xmm0" : "ymm0";
4874 as_bad (_("the last operand of `%s' must be `%s%s'"),
4875 i
.tm
.name
, register_prefix
, ireg
);
4877 as_bad (_("the first operand of `%s' must be `%s%s'"),
4878 i
.tm
.name
, register_prefix
, ireg
);
4883 process_operands (void)
4885 /* Default segment register this instruction will use for memory
4886 accesses. 0 means unknown. This is only for optimizing out
4887 unnecessary segment overrides. */
4888 const seg_entry
*default_seg
= 0;
4890 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4892 unsigned int dupl
= i
.operands
;
4893 unsigned int dest
= dupl
- 1;
4896 /* The destination must be an xmm register. */
4897 gas_assert (i
.reg_operands
4898 && MAX_OPERANDS
> dupl
4899 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4901 if (i
.tm
.opcode_modifier
.firstxmm0
)
4903 /* The first operand is implicit and must be xmm0. */
4904 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4905 if (i
.op
[0].regs
->reg_num
!= 0)
4906 return bad_implicit_operand (1);
4908 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4910 /* Keep xmm0 for instructions with VEX prefix and 3
4916 /* We remove the first xmm0 and keep the number of
4917 operands unchanged, which in fact duplicates the
4919 for (j
= 1; j
< i
.operands
; j
++)
4921 i
.op
[j
- 1] = i
.op
[j
];
4922 i
.types
[j
- 1] = i
.types
[j
];
4923 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4927 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4929 gas_assert ((MAX_OPERANDS
- 1) > dupl
4930 && (i
.tm
.opcode_modifier
.vexsources
4933 /* Add the implicit xmm0 for instructions with VEX prefix
4935 for (j
= i
.operands
; j
> 0; j
--)
4937 i
.op
[j
] = i
.op
[j
- 1];
4938 i
.types
[j
] = i
.types
[j
- 1];
4939 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4942 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4943 i
.types
[0] = regxmm
;
4944 i
.tm
.operand_types
[0] = regxmm
;
4947 i
.reg_operands
+= 2;
4952 i
.op
[dupl
] = i
.op
[dest
];
4953 i
.types
[dupl
] = i
.types
[dest
];
4954 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4963 i
.op
[dupl
] = i
.op
[dest
];
4964 i
.types
[dupl
] = i
.types
[dest
];
4965 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4968 if (i
.tm
.opcode_modifier
.immext
)
4971 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4975 /* The first operand is implicit and must be xmm0/ymm0. */
4976 gas_assert (i
.reg_operands
4977 && (operand_type_equal (&i
.types
[0], ®xmm
)
4978 || operand_type_equal (&i
.types
[0], ®ymm
)));
4979 if (i
.op
[0].regs
->reg_num
!= 0)
4980 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4982 for (j
= 1; j
< i
.operands
; j
++)
4984 i
.op
[j
- 1] = i
.op
[j
];
4985 i
.types
[j
- 1] = i
.types
[j
];
4987 /* We need to adjust fields in i.tm since they are used by
4988 build_modrm_byte. */
4989 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4996 else if (i
.tm
.opcode_modifier
.regkludge
)
4998 /* The imul $imm, %reg instruction is converted into
4999 imul $imm, %reg, %reg, and the clr %reg instruction
5000 is converted into xor %reg, %reg. */
5002 unsigned int first_reg_op
;
5004 if (operand_type_check (i
.types
[0], reg
))
5008 /* Pretend we saw the extra register operand. */
5009 gas_assert (i
.reg_operands
== 1
5010 && i
.op
[first_reg_op
+ 1].regs
== 0);
5011 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
5012 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
5017 if (i
.tm
.opcode_modifier
.shortform
)
5019 if (i
.types
[0].bitfield
.sreg2
5020 || i
.types
[0].bitfield
.sreg3
)
5022 if (i
.tm
.base_opcode
== POP_SEG_SHORT
5023 && i
.op
[0].regs
->reg_num
== 1)
5025 as_bad (_("you can't `pop %scs'"), register_prefix
);
5028 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
5029 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
5034 /* The register or float register operand is in operand
5038 if (i
.types
[0].bitfield
.floatreg
5039 || operand_type_check (i
.types
[0], reg
))
5043 /* Register goes in low 3 bits of opcode. */
5044 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
5045 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5047 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
5049 /* Warn about some common errors, but press on regardless.
5050 The first case can be generated by gcc (<= 2.8.1). */
5051 if (i
.operands
== 2)
5053 /* Reversed arguments on faddp, fsubp, etc. */
5054 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5055 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5056 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5060 /* Extraneous `l' suffix on fp insn. */
5061 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5062 register_prefix
, i
.op
[0].regs
->reg_name
);
5067 else if (i
.tm
.opcode_modifier
.modrm
)
5069 /* The opcode is completed (modulo i.tm.extension_opcode which
5070 must be put into the modrm byte). Now, we make the modrm and
5071 index base bytes based on all the info we've collected. */
5073 default_seg
= build_modrm_byte ();
5075 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5079 else if (i
.tm
.opcode_modifier
.isstring
)
5081 /* For the string instructions that allow a segment override
5082 on one of their operands, the default segment is ds. */
5086 if (i
.tm
.base_opcode
== 0x8d /* lea */
5089 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5091 /* If a segment was explicitly specified, and the specified segment
5092 is not the default, use an opcode prefix to select it. If we
5093 never figured out what the default segment is, then default_seg
5094 will be zero at this point, and the specified segment prefix will
5096 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5098 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5104 static const seg_entry
*
5105 build_modrm_byte (void)
5107 const seg_entry
*default_seg
= 0;
5108 unsigned int source
, dest
;
5111 /* The first operand of instructions with VEX prefix and 3 sources
5112 must be VEX_Imm4. */
5113 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5116 unsigned int nds
, reg_slot
;
5119 if (i
.tm
.opcode_modifier
.veximmext
5120 && i
.tm
.opcode_modifier
.immext
)
5122 dest
= i
.operands
- 2;
5123 gas_assert (dest
== 3);
5126 dest
= i
.operands
- 1;
5129 /* There are 2 kinds of instructions:
5130 1. 5 operands: 4 register operands or 3 register operands
5131 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5132 VexW0 or VexW1. The destination must be either XMM or YMM
5134 2. 4 operands: 4 register operands or 3 register operands
5135 plus 1 memory operand, VexXDS, and VexImmExt */
5136 gas_assert ((i
.reg_operands
== 4
5137 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5138 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5139 && (i
.tm
.opcode_modifier
.veximmext
5140 || (i
.imm_operands
== 1
5141 && i
.types
[0].bitfield
.vec_imm4
5142 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5143 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5144 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5145 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5147 if (i
.imm_operands
== 0)
5149 /* When there is no immediate operand, generate an 8bit
5150 immediate operand to encode the first operand. */
5151 exp
= &im_expressions
[i
.imm_operands
++];
5152 i
.op
[i
.operands
].imms
= exp
;
5153 i
.types
[i
.operands
] = imm8
;
5155 /* If VexW1 is set, the first operand is the source and
5156 the second operand is encoded in the immediate operand. */
5157 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5168 /* FMA swaps REG and NDS. */
5169 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5177 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5179 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5181 exp
->X_op
= O_constant
;
5183 = ((i
.op
[reg_slot
].regs
->reg_num
5184 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5189 unsigned int imm_slot
;
5191 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5193 /* If VexW0 is set, the third operand is the source and
5194 the second operand is encoded in the immediate
5201 /* VexW1 is set, the second operand is the source and
5202 the third operand is encoded in the immediate
5208 if (i
.tm
.opcode_modifier
.immext
)
5210 /* When ImmExt is set, the immdiate byte is the last
5212 imm_slot
= i
.operands
- 1;
5220 /* Turn on Imm8 so that output_imm will generate it. */
5221 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5224 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5226 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5228 i
.op
[imm_slot
].imms
->X_add_number
5229 |= ((i
.op
[reg_slot
].regs
->reg_num
5230 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5234 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5235 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5237 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5242 /* i.reg_operands MUST be the number of real register operands;
5243 implicit registers do not count. If there are 3 register
5244 operands, it must be a instruction with VexNDS. For a
5245 instruction with VexNDD, the destination register is encoded
5246 in VEX prefix. If there are 4 register operands, it must be
5247 a instruction with VEX prefix and 3 sources. */
5248 if (i
.mem_operands
== 0
5249 && ((i
.reg_operands
== 2
5250 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5251 || (i
.reg_operands
== 3
5252 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5253 || (i
.reg_operands
== 4 && vex_3_sources
)))
5261 /* When there are 3 operands, one of them may be immediate,
5262 which may be the first or the last operand. Otherwise,
5263 the first operand must be shift count register (cl) or it
5264 is an instruction with VexNDS. */
5265 gas_assert (i
.imm_operands
== 1
5266 || (i
.imm_operands
== 0
5267 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5268 || i
.types
[0].bitfield
.shiftcount
)));
5269 if (operand_type_check (i
.types
[0], imm
)
5270 || i
.types
[0].bitfield
.shiftcount
)
5276 /* When there are 4 operands, the first two must be 8bit
5277 immediate operands. The source operand will be the 3rd
5280 For instructions with VexNDS, if the first operand
5281 an imm8, the source operand is the 2nd one. If the last
5282 operand is imm8, the source operand is the first one. */
5283 gas_assert ((i
.imm_operands
== 2
5284 && i
.types
[0].bitfield
.imm8
5285 && i
.types
[1].bitfield
.imm8
)
5286 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5287 && i
.imm_operands
== 1
5288 && (i
.types
[0].bitfield
.imm8
5289 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5290 if (i
.imm_operands
== 2)
5294 if (i
.types
[0].bitfield
.imm8
)
5310 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5312 /* For instructions with VexNDS, the register-only
5313 source operand must be 32/64bit integer, XMM or
5314 YMM register. It is encoded in VEX prefix. We
5315 need to clear RegMem bit before calling
5316 operand_type_equal. */
5318 i386_operand_type op
;
5321 /* Check register-only source operand when two source
5322 operands are swapped. */
5323 if (!i
.tm
.operand_types
[source
].bitfield
.baseindex
5324 && i
.tm
.operand_types
[dest
].bitfield
.baseindex
)
5332 op
= i
.tm
.operand_types
[vvvv
];
5333 op
.bitfield
.regmem
= 0;
5334 if ((dest
+ 1) >= i
.operands
5335 || (op
.bitfield
.reg32
!= 1
5336 && !op
.bitfield
.reg64
!= 1
5337 && !operand_type_equal (&op
, ®xmm
)
5338 && !operand_type_equal (&op
, ®ymm
)))
5340 i
.vex
.register_specifier
= i
.op
[vvvv
].regs
;
5346 /* One of the register operands will be encoded in the i.tm.reg
5347 field, the other in the combined i.tm.mode and i.tm.regmem
5348 fields. If no form of this instruction supports a memory
5349 destination operand, then we assume the source operand may
5350 sometimes be a memory operand and so we need to store the
5351 destination in the i.rm.reg field. */
5352 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5353 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5355 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5356 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5357 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5359 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5364 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5365 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5366 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5368 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5371 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5373 if (!i
.types
[0].bitfield
.control
5374 && !i
.types
[1].bitfield
.control
)
5376 i
.rex
&= ~(REX_R
| REX_B
);
5377 add_prefix (LOCK_PREFIX_OPCODE
);
5381 { /* If it's not 2 reg operands... */
5386 unsigned int fake_zero_displacement
= 0;
5389 for (op
= 0; op
< i
.operands
; op
++)
5390 if (operand_type_check (i
.types
[op
], anymem
))
5392 gas_assert (op
< i
.operands
);
5396 if (i
.base_reg
== 0)
5399 if (!i
.disp_operands
)
5400 fake_zero_displacement
= 1;
5401 if (i
.index_reg
== 0)
5403 /* Operand is just <disp> */
5404 if (flag_code
== CODE_64BIT
)
5406 /* 64bit mode overwrites the 32bit absolute
5407 addressing by RIP relative addressing and
5408 absolute addressing is encoded by one of the
5409 redundant SIB forms. */
5410 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5411 i
.sib
.base
= NO_BASE_REGISTER
;
5412 i
.sib
.index
= NO_INDEX_REGISTER
;
5413 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5414 ? disp32s
: disp32
);
5416 else if ((flag_code
== CODE_16BIT
)
5417 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5419 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5420 i
.types
[op
] = disp16
;
5424 i
.rm
.regmem
= NO_BASE_REGISTER
;
5425 i
.types
[op
] = disp32
;
5428 else /* !i.base_reg && i.index_reg */
5430 if (i
.index_reg
->reg_num
== RegEiz
5431 || i
.index_reg
->reg_num
== RegRiz
)
5432 i
.sib
.index
= NO_INDEX_REGISTER
;
5434 i
.sib
.index
= i
.index_reg
->reg_num
;
5435 i
.sib
.base
= NO_BASE_REGISTER
;
5436 i
.sib
.scale
= i
.log2_scale_factor
;
5437 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5438 i
.types
[op
].bitfield
.disp8
= 0;
5439 i
.types
[op
].bitfield
.disp16
= 0;
5440 i
.types
[op
].bitfield
.disp64
= 0;
5441 if (flag_code
!= CODE_64BIT
)
5443 /* Must be 32 bit */
5444 i
.types
[op
].bitfield
.disp32
= 1;
5445 i
.types
[op
].bitfield
.disp32s
= 0;
5449 i
.types
[op
].bitfield
.disp32
= 0;
5450 i
.types
[op
].bitfield
.disp32s
= 1;
5452 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5456 /* RIP addressing for 64bit mode. */
5457 else if (i
.base_reg
->reg_num
== RegRip
||
5458 i
.base_reg
->reg_num
== RegEip
)
5460 i
.rm
.regmem
= NO_BASE_REGISTER
;
5461 i
.types
[op
].bitfield
.disp8
= 0;
5462 i
.types
[op
].bitfield
.disp16
= 0;
5463 i
.types
[op
].bitfield
.disp32
= 0;
5464 i
.types
[op
].bitfield
.disp32s
= 1;
5465 i
.types
[op
].bitfield
.disp64
= 0;
5466 i
.flags
[op
] |= Operand_PCrel
;
5467 if (! i
.disp_operands
)
5468 fake_zero_displacement
= 1;
5470 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5472 switch (i
.base_reg
->reg_num
)
5475 if (i
.index_reg
== 0)
5477 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5478 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5482 if (i
.index_reg
== 0)
5485 if (operand_type_check (i
.types
[op
], disp
) == 0)
5487 /* fake (%bp) into 0(%bp) */
5488 i
.types
[op
].bitfield
.disp8
= 1;
5489 fake_zero_displacement
= 1;
5492 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5493 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5495 default: /* (%si) -> 4 or (%di) -> 5 */
5496 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5498 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5500 else /* i.base_reg and 32/64 bit mode */
5502 if (flag_code
== CODE_64BIT
5503 && operand_type_check (i
.types
[op
], disp
))
5505 i386_operand_type temp
;
5506 operand_type_set (&temp
, 0);
5507 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5509 if (i
.prefix
[ADDR_PREFIX
] == 0)
5510 i
.types
[op
].bitfield
.disp32s
= 1;
5512 i
.types
[op
].bitfield
.disp32
= 1;
5515 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5516 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5518 i
.sib
.base
= i
.base_reg
->reg_num
;
5519 /* x86-64 ignores REX prefix bit here to avoid decoder
5521 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5524 if (i
.disp_operands
== 0)
5526 fake_zero_displacement
= 1;
5527 i
.types
[op
].bitfield
.disp8
= 1;
5530 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5534 i
.sib
.scale
= i
.log2_scale_factor
;
5535 if (i
.index_reg
== 0)
5537 /* <disp>(%esp) becomes two byte modrm with no index
5538 register. We've already stored the code for esp
5539 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5540 Any base register besides %esp will not use the
5541 extra modrm byte. */
5542 i
.sib
.index
= NO_INDEX_REGISTER
;
5546 if (i
.index_reg
->reg_num
== RegEiz
5547 || i
.index_reg
->reg_num
== RegRiz
)
5548 i
.sib
.index
= NO_INDEX_REGISTER
;
5550 i
.sib
.index
= i
.index_reg
->reg_num
;
5551 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5552 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5557 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5558 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5561 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5564 if (fake_zero_displacement
)
5566 /* Fakes a zero displacement assuming that i.types[op]
5567 holds the correct displacement size. */
5570 gas_assert (i
.op
[op
].disps
== 0);
5571 exp
= &disp_expressions
[i
.disp_operands
++];
5572 i
.op
[op
].disps
= exp
;
5573 exp
->X_op
= O_constant
;
5574 exp
->X_add_number
= 0;
5575 exp
->X_add_symbol
= (symbolS
*) 0;
5576 exp
->X_op_symbol
= (symbolS
*) 0;
5584 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5586 if (operand_type_check (i
.types
[0], imm
))
5587 i
.vex
.register_specifier
= NULL
;
5590 /* VEX.vvvv encodes one of the sources when the first
5591 operand is not an immediate. */
5592 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5593 i
.vex
.register_specifier
= i
.op
[0].regs
;
5595 i
.vex
.register_specifier
= i
.op
[1].regs
;
5598 /* Destination is a XMM register encoded in the ModRM.reg
5600 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5601 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5604 /* ModRM.rm and VEX.B encodes the other source. */
5605 if (!i
.mem_operands
)
5609 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5610 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5612 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5614 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5618 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5620 i
.vex
.register_specifier
= i
.op
[2].regs
;
5621 if (!i
.mem_operands
)
5624 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5625 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5629 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5630 (if any) based on i.tm.extension_opcode. Again, we must be
5631 careful to make sure that segment/control/debug/test/MMX
5632 registers are coded into the i.rm.reg field. */
5633 else if (i
.reg_operands
)
5636 unsigned int vex_reg
= ~0;
5638 for (op
= 0; op
< i
.operands
; op
++)
5639 if (i
.types
[op
].bitfield
.reg8
5640 || i
.types
[op
].bitfield
.reg16
5641 || i
.types
[op
].bitfield
.reg32
5642 || i
.types
[op
].bitfield
.reg64
5643 || i
.types
[op
].bitfield
.regmmx
5644 || i
.types
[op
].bitfield
.regxmm
5645 || i
.types
[op
].bitfield
.regymm
5646 || i
.types
[op
].bitfield
.sreg2
5647 || i
.types
[op
].bitfield
.sreg3
5648 || i
.types
[op
].bitfield
.control
5649 || i
.types
[op
].bitfield
.debug
5650 || i
.types
[op
].bitfield
.test
)
5655 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5657 /* For instructions with VexNDS, the register-only
5658 source operand is encoded in VEX prefix. */
5659 gas_assert (mem
!= (unsigned int) ~0);
5664 gas_assert (op
< i
.operands
);
5668 /* Check register-only source operand when two source
5669 operands are swapped. */
5670 if (!i
.tm
.operand_types
[op
].bitfield
.baseindex
5671 && i
.tm
.operand_types
[op
+ 1].bitfield
.baseindex
)
5675 gas_assert (mem
== (vex_reg
+ 1)
5676 && op
< i
.operands
);
5681 gas_assert (vex_reg
< i
.operands
);
5685 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5687 /* For instructions with VexNDD, the register destination
5688 is encoded in VEX prefix. */
5689 if (i
.mem_operands
== 0)
5691 /* There is no memory operand. */
5692 gas_assert ((op
+ 2) == i
.operands
);
5697 /* There are only 2 operands. */
5698 gas_assert (op
< 2 && i
.operands
== 2);
5703 gas_assert (op
< i
.operands
);
5705 if (vex_reg
!= (unsigned int) ~0)
5707 i386_operand_type
*type
= &i
.tm
.operand_types
[vex_reg
];
5709 if (type
->bitfield
.reg32
!= 1
5710 && type
->bitfield
.reg64
!= 1
5711 && !operand_type_equal (type
, ®xmm
)
5712 && !operand_type_equal (type
, ®ymm
))
5715 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5718 /* Don't set OP operand twice. */
5721 /* If there is an extension opcode to put here, the
5722 register number must be put into the regmem field. */
5723 if (i
.tm
.extension_opcode
!= None
)
5725 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5726 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5731 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5732 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5737 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5738 must set it to 3 to indicate this is a register operand
5739 in the regmem field. */
5740 if (!i
.mem_operands
)
5744 /* Fill in i.rm.reg field with extension opcode (if any). */
5745 if (i
.tm
.extension_opcode
!= None
)
5746 i
.rm
.reg
= i
.tm
.extension_opcode
;
5752 output_branch (void)
5758 relax_substateT subtype
;
5762 code16
= flag_code
== CODE_16BIT
? CODE16
: 0;
5763 size
= i
.disp32_encoding
? BIG
: SMALL
;
5766 if (i
.prefix
[DATA_PREFIX
] != 0)
5772 /* Pentium4 branch hints. */
5773 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5774 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5779 if (i
.prefix
[REX_PREFIX
] != 0)
5785 if (i
.prefixes
!= 0 && !intel_syntax
)
5786 as_warn (_("skipping prefixes on this instruction"));
5788 /* It's always a symbol; End frag & setup for relax.
5789 Make sure there is enough room in this frag for the largest
5790 instruction we may generate in md_convert_frag. This is 2
5791 bytes for the opcode and room for the prefix and largest
5793 frag_grow (prefix
+ 2 + 4);
5794 /* Prefix and 1 opcode byte go in fr_fix. */
5795 p
= frag_more (prefix
+ 1);
5796 if (i
.prefix
[DATA_PREFIX
] != 0)
5797 *p
++ = DATA_PREFIX_OPCODE
;
5798 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5799 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5800 *p
++ = i
.prefix
[SEG_PREFIX
];
5801 if (i
.prefix
[REX_PREFIX
] != 0)
5802 *p
++ = i
.prefix
[REX_PREFIX
];
5803 *p
= i
.tm
.base_opcode
;
5805 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5806 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, size
);
5807 else if (cpu_arch_flags
.bitfield
.cpui386
)
5808 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, size
);
5810 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, size
);
5813 sym
= i
.op
[0].disps
->X_add_symbol
;
5814 off
= i
.op
[0].disps
->X_add_number
;
5816 if (i
.op
[0].disps
->X_op
!= O_constant
5817 && i
.op
[0].disps
->X_op
!= O_symbol
)
5819 /* Handle complex expressions. */
5820 sym
= make_expr_symbol (i
.op
[0].disps
);
5824 /* 1 possible extra opcode + 4 byte displacement go in var part.
5825 Pass reloc in fr_var. */
5826 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5836 if (i
.tm
.opcode_modifier
.jumpbyte
)
5838 /* This is a loop or jecxz type instruction. */
5840 if (i
.prefix
[ADDR_PREFIX
] != 0)
5842 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5845 /* Pentium4 branch hints. */
5846 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5847 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5849 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5858 if (flag_code
== CODE_16BIT
)
5861 if (i
.prefix
[DATA_PREFIX
] != 0)
5863 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5873 if (i
.prefix
[REX_PREFIX
] != 0)
5875 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5879 if (i
.prefixes
!= 0 && !intel_syntax
)
5880 as_warn (_("skipping prefixes on this instruction"));
5882 p
= frag_more (1 + size
);
5883 *p
++ = i
.tm
.base_opcode
;
5885 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5886 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5888 /* All jumps handled here are signed, but don't use a signed limit
5889 check for 32 and 16 bit jumps as we want to allow wrap around at
5890 4G and 64k respectively. */
5892 fixP
->fx_signed
= 1;
5896 output_interseg_jump (void)
5904 if (flag_code
== CODE_16BIT
)
5908 if (i
.prefix
[DATA_PREFIX
] != 0)
5914 if (i
.prefix
[REX_PREFIX
] != 0)
5924 if (i
.prefixes
!= 0 && !intel_syntax
)
5925 as_warn (_("skipping prefixes on this instruction"));
5927 /* 1 opcode; 2 segment; offset */
5928 p
= frag_more (prefix
+ 1 + 2 + size
);
5930 if (i
.prefix
[DATA_PREFIX
] != 0)
5931 *p
++ = DATA_PREFIX_OPCODE
;
5933 if (i
.prefix
[REX_PREFIX
] != 0)
5934 *p
++ = i
.prefix
[REX_PREFIX
];
5936 *p
++ = i
.tm
.base_opcode
;
5937 if (i
.op
[1].imms
->X_op
== O_constant
)
5939 offsetT n
= i
.op
[1].imms
->X_add_number
;
5942 && !fits_in_unsigned_word (n
)
5943 && !fits_in_signed_word (n
))
5945 as_bad (_("16-bit jump out of range"));
5948 md_number_to_chars (p
, n
, size
);
5951 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5952 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5953 if (i
.op
[0].imms
->X_op
!= O_constant
)
5954 as_bad (_("can't handle non absolute segment in `%s'"),
5956 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5962 fragS
*insn_start_frag
;
5963 offsetT insn_start_off
;
5965 /* Tie dwarf2 debug info to the address at the start of the insn.
5966 We can't do this after the insn has been output as the current
5967 frag may have been closed off. eg. by frag_var. */
5968 dwarf2_emit_insn (0);
5970 insn_start_frag
= frag_now
;
5971 insn_start_off
= frag_now_fix ();
5974 if (i
.tm
.opcode_modifier
.jump
)
5976 else if (i
.tm
.opcode_modifier
.jumpbyte
5977 || i
.tm
.opcode_modifier
.jumpdword
)
5979 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5980 output_interseg_jump ();
5983 /* Output normal instructions here. */
5987 unsigned int prefix
;
5989 /* Since the VEX prefix contains the implicit prefix, we don't
5990 need the explicit prefix. */
5991 if (!i
.tm
.opcode_modifier
.vex
)
5993 switch (i
.tm
.opcode_length
)
5996 if (i
.tm
.base_opcode
& 0xff000000)
5998 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
6003 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
6005 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
6006 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
6009 if (prefix
!= REPE_PREFIX_OPCODE
6010 || (i
.prefix
[REP_PREFIX
]
6011 != REPE_PREFIX_OPCODE
))
6012 add_prefix (prefix
);
6015 add_prefix (prefix
);
6024 /* The prefix bytes. */
6025 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
6027 FRAG_APPEND_1_CHAR (*q
);
6030 if (i
.tm
.opcode_modifier
.vex
)
6032 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
6037 /* REX byte is encoded in VEX prefix. */
6041 FRAG_APPEND_1_CHAR (*q
);
6044 /* There should be no other prefixes for instructions
6049 /* Now the VEX prefix. */
6050 p
= frag_more (i
.vex
.length
);
6051 for (j
= 0; j
< i
.vex
.length
; j
++)
6052 p
[j
] = i
.vex
.bytes
[j
];
6055 /* Now the opcode; be careful about word order here! */
6056 if (i
.tm
.opcode_length
== 1)
6058 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
6062 switch (i
.tm
.opcode_length
)
6066 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
6076 /* Put out high byte first: can't use md_number_to_chars! */
6077 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
6078 *p
= i
.tm
.base_opcode
& 0xff;
6081 /* Now the modrm byte and sib byte (if present). */
6082 if (i
.tm
.opcode_modifier
.modrm
)
6084 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
6087 /* If i.rm.regmem == ESP (4)
6088 && i.rm.mode != (Register mode)
6090 ==> need second modrm byte. */
6091 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6093 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6094 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6096 | i
.sib
.scale
<< 6));
6099 if (i
.disp_operands
)
6100 output_disp (insn_start_frag
, insn_start_off
);
6103 output_imm (insn_start_frag
, insn_start_off
);
6109 pi ("" /*line*/, &i
);
6111 #endif /* DEBUG386 */
6114 /* Return the size of the displacement operand N. */
6117 disp_size (unsigned int n
)
6120 if (i
.types
[n
].bitfield
.disp64
)
6122 else if (i
.types
[n
].bitfield
.disp8
)
6124 else if (i
.types
[n
].bitfield
.disp16
)
6129 /* Return the size of the immediate operand N. */
6132 imm_size (unsigned int n
)
6135 if (i
.types
[n
].bitfield
.imm64
)
6137 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6139 else if (i
.types
[n
].bitfield
.imm16
)
6145 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6150 for (n
= 0; n
< i
.operands
; n
++)
6152 if (operand_type_check (i
.types
[n
], disp
))
6154 if (i
.op
[n
].disps
->X_op
== O_constant
)
6156 int size
= disp_size (n
);
6159 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6161 p
= frag_more (size
);
6162 md_number_to_chars (p
, val
, size
);
6166 enum bfd_reloc_code_real reloc_type
;
6167 int size
= disp_size (n
);
6168 int sign
= i
.types
[n
].bitfield
.disp32s
;
6169 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6171 /* We can't have 8 bit displacement here. */
6172 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6174 /* The PC relative address is computed relative
6175 to the instruction boundary, so in case immediate
6176 fields follows, we need to adjust the value. */
6177 if (pcrel
&& i
.imm_operands
)
6182 for (n1
= 0; n1
< i
.operands
; n1
++)
6183 if (operand_type_check (i
.types
[n1
], imm
))
6185 /* Only one immediate is allowed for PC
6186 relative address. */
6187 gas_assert (sz
== 0);
6189 i
.op
[n
].disps
->X_add_number
-= sz
;
6191 /* We should find the immediate. */
6192 gas_assert (sz
!= 0);
6195 p
= frag_more (size
);
6196 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6198 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6199 && (((reloc_type
== BFD_RELOC_32
6200 || reloc_type
== BFD_RELOC_X86_64_32S
6201 || (reloc_type
== BFD_RELOC_64
6203 && (i
.op
[n
].disps
->X_op
== O_symbol
6204 || (i
.op
[n
].disps
->X_op
== O_add
6205 && ((symbol_get_value_expression
6206 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6208 || reloc_type
== BFD_RELOC_32_PCREL
))
6212 if (insn_start_frag
== frag_now
)
6213 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6218 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6219 for (fr
= insn_start_frag
->fr_next
;
6220 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6222 add
+= p
- frag_now
->fr_literal
;
6227 reloc_type
= BFD_RELOC_386_GOTPC
;
6228 i
.op
[n
].imms
->X_add_number
+= add
;
6230 else if (reloc_type
== BFD_RELOC_64
)
6231 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6233 /* Don't do the adjustment for x86-64, as there
6234 the pcrel addressing is relative to the _next_
6235 insn, and that is taken care of in other code. */
6236 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6238 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6239 i
.op
[n
].disps
, pcrel
, reloc_type
);
6246 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6251 for (n
= 0; n
< i
.operands
; n
++)
6253 if (operand_type_check (i
.types
[n
], imm
))
6255 if (i
.op
[n
].imms
->X_op
== O_constant
)
6257 int size
= imm_size (n
);
6260 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6262 p
= frag_more (size
);
6263 md_number_to_chars (p
, val
, size
);
6267 /* Not absolute_section.
6268 Need a 32-bit fixup (don't support 8bit
6269 non-absolute imms). Try to support other
6271 enum bfd_reloc_code_real reloc_type
;
6272 int size
= imm_size (n
);
6275 if (i
.types
[n
].bitfield
.imm32s
6276 && (i
.suffix
== QWORD_MNEM_SUFFIX
6277 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6282 p
= frag_more (size
);
6283 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6285 /* This is tough to explain. We end up with this one if we
6286 * have operands that look like
6287 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6288 * obtain the absolute address of the GOT, and it is strongly
6289 * preferable from a performance point of view to avoid using
6290 * a runtime relocation for this. The actual sequence of
6291 * instructions often look something like:
6296 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6298 * The call and pop essentially return the absolute address
6299 * of the label .L66 and store it in %ebx. The linker itself
6300 * will ultimately change the first operand of the addl so
6301 * that %ebx points to the GOT, but to keep things simple, the
6302 * .o file must have this operand set so that it generates not
6303 * the absolute address of .L66, but the absolute address of
6304 * itself. This allows the linker itself simply treat a GOTPC
6305 * relocation as asking for a pcrel offset to the GOT to be
6306 * added in, and the addend of the relocation is stored in the
6307 * operand field for the instruction itself.
6309 * Our job here is to fix the operand so that it would add
6310 * the correct offset so that %ebx would point to itself. The
6311 * thing that is tricky is that .-.L66 will point to the
6312 * beginning of the instruction, so we need to further modify
6313 * the operand so that it will point to itself. There are
6314 * other cases where you have something like:
6316 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6318 * and here no correction would be required. Internally in
6319 * the assembler we treat operands of this form as not being
6320 * pcrel since the '.' is explicitly mentioned, and I wonder
6321 * whether it would simplify matters to do it this way. Who
6322 * knows. In earlier versions of the PIC patches, the
6323 * pcrel_adjust field was used to store the correction, but
6324 * since the expression is not pcrel, I felt it would be
6325 * confusing to do it this way. */
6327 if ((reloc_type
== BFD_RELOC_32
6328 || reloc_type
== BFD_RELOC_X86_64_32S
6329 || reloc_type
== BFD_RELOC_64
)
6331 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6332 && (i
.op
[n
].imms
->X_op
== O_symbol
6333 || (i
.op
[n
].imms
->X_op
== O_add
6334 && ((symbol_get_value_expression
6335 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6340 if (insn_start_frag
== frag_now
)
6341 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6346 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6347 for (fr
= insn_start_frag
->fr_next
;
6348 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6350 add
+= p
- frag_now
->fr_literal
;
6354 reloc_type
= BFD_RELOC_386_GOTPC
;
6356 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6358 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6359 i
.op
[n
].imms
->X_add_number
+= add
;
6361 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6362 i
.op
[n
].imms
, 0, reloc_type
);
6368 /* x86_cons_fix_new is called via the expression parsing code when a
6369 reloc is needed. We use this hook to get the correct .got reloc. */
6370 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6371 static int cons_sign
= -1;
6374 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6377 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6379 got_reloc
= NO_RELOC
;
6382 if (exp
->X_op
== O_secrel
)
6384 exp
->X_op
= O_symbol
;
6385 r
= BFD_RELOC_32_SECREL
;
6389 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6392 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6393 # define lex_got(reloc, adjust, types) NULL
6395 /* Parse operands of the form
6396 <symbol>@GOTOFF+<nnn>
6397 and similar .plt or .got references.
6399 If we find one, set up the correct relocation in RELOC and copy the
6400 input string, minus the `@GOTOFF' into a malloc'd buffer for
6401 parsing by the calling routine. Return this buffer, and if ADJUST
6402 is non-null set it to the length of the string we removed from the
6403 input line. Otherwise return NULL. */
6405 lex_got (enum bfd_reloc_code_real
*rel
,
6407 i386_operand_type
*types
)
6409 /* Some of the relocations depend on the size of what field is to
6410 be relocated. But in our callers i386_immediate and i386_displacement
6411 we don't yet know the operand size (this will be set by insn
6412 matching). Hence we record the word32 relocation here,
6413 and adjust the reloc according to the real size in reloc(). */
6414 static const struct {
6417 const enum bfd_reloc_code_real rel
[2];
6418 const i386_operand_type types64
;
6420 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6421 BFD_RELOC_X86_64_PLTOFF64
},
6422 OPERAND_TYPE_IMM64
},
6423 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6424 BFD_RELOC_X86_64_PLT32
},
6425 OPERAND_TYPE_IMM32_32S_DISP32
},
6426 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6427 BFD_RELOC_X86_64_GOTPLT64
},
6428 OPERAND_TYPE_IMM64_DISP64
},
6429 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6430 BFD_RELOC_X86_64_GOTOFF64
},
6431 OPERAND_TYPE_IMM64_DISP64
},
6432 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6433 BFD_RELOC_X86_64_GOTPCREL
},
6434 OPERAND_TYPE_IMM32_32S_DISP32
},
6435 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6436 BFD_RELOC_X86_64_TLSGD
},
6437 OPERAND_TYPE_IMM32_32S_DISP32
},
6438 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6439 _dummy_first_bfd_reloc_code_real
},
6440 OPERAND_TYPE_NONE
},
6441 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6442 BFD_RELOC_X86_64_TLSLD
},
6443 OPERAND_TYPE_IMM32_32S_DISP32
},
6444 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6445 BFD_RELOC_X86_64_GOTTPOFF
},
6446 OPERAND_TYPE_IMM32_32S_DISP32
},
6447 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6448 BFD_RELOC_X86_64_TPOFF32
},
6449 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6450 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6451 _dummy_first_bfd_reloc_code_real
},
6452 OPERAND_TYPE_NONE
},
6453 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6454 BFD_RELOC_X86_64_DTPOFF32
},
6455 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6456 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6457 _dummy_first_bfd_reloc_code_real
},
6458 OPERAND_TYPE_NONE
},
6459 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6460 _dummy_first_bfd_reloc_code_real
},
6461 OPERAND_TYPE_NONE
},
6462 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6463 BFD_RELOC_X86_64_GOT32
},
6464 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6465 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6466 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6467 OPERAND_TYPE_IMM32_32S_DISP32
},
6468 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6469 BFD_RELOC_X86_64_TLSDESC_CALL
},
6470 OPERAND_TYPE_IMM32_32S_DISP32
},
6478 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6479 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6482 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6484 int len
= gotrel
[j
].len
;
6485 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6487 if (gotrel
[j
].rel
[object_64bit
] != 0)
6490 char *tmpbuf
, *past_reloc
;
6492 *rel
= gotrel
[j
].rel
[object_64bit
];
6498 if (flag_code
!= CODE_64BIT
)
6500 types
->bitfield
.imm32
= 1;
6501 types
->bitfield
.disp32
= 1;
6504 *types
= gotrel
[j
].types64
;
6507 if (GOT_symbol
== NULL
)
6508 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6510 /* The length of the first part of our input line. */
6511 first
= cp
- input_line_pointer
;
6513 /* The second part goes from after the reloc token until
6514 (and including) an end_of_line char or comma. */
6515 past_reloc
= cp
+ 1 + len
;
6517 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6519 second
= cp
+ 1 - past_reloc
;
6521 /* Allocate and copy string. The trailing NUL shouldn't
6522 be necessary, but be safe. */
6523 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6524 memcpy (tmpbuf
, input_line_pointer
, first
);
6525 if (second
!= 0 && *past_reloc
!= ' ')
6526 /* Replace the relocation token with ' ', so that
6527 errors like foo@GOTOFF1 will be detected. */
6528 tmpbuf
[first
++] = ' ';
6529 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6530 tmpbuf
[first
+ second
] = '\0';
6534 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6535 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6540 /* Might be a symbol version string. Don't as_bad here. */
6545 x86_cons (expressionS
*exp
, int size
)
6547 intel_syntax
= -intel_syntax
;
6550 if (size
== 4 || (object_64bit
&& size
== 8))
6552 /* Handle @GOTOFF and the like in an expression. */
6554 char *gotfree_input_line
;
6557 save
= input_line_pointer
;
6558 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6559 if (gotfree_input_line
)
6560 input_line_pointer
= gotfree_input_line
;
6564 if (gotfree_input_line
)
6566 /* expression () has merrily parsed up to the end of line,
6567 or a comma - in the wrong buffer. Transfer how far
6568 input_line_pointer has moved to the right buffer. */
6569 input_line_pointer
= (save
6570 + (input_line_pointer
- gotfree_input_line
)
6572 free (gotfree_input_line
);
6573 if (exp
->X_op
== O_constant
6574 || exp
->X_op
== O_absent
6575 || exp
->X_op
== O_illegal
6576 || exp
->X_op
== O_register
6577 || exp
->X_op
== O_big
)
6579 char c
= *input_line_pointer
;
6580 *input_line_pointer
= 0;
6581 as_bad (_("missing or invalid expression `%s'"), save
);
6582 *input_line_pointer
= c
;
6589 intel_syntax
= -intel_syntax
;
6592 i386_intel_simplify (exp
);
6597 signed_cons (int size
)
6599 if (flag_code
== CODE_64BIT
)
6607 pe_directive_secrel (dummy
)
6608 int dummy ATTRIBUTE_UNUSED
;
6615 if (exp
.X_op
== O_symbol
)
6616 exp
.X_op
= O_secrel
;
6618 emit_expr (&exp
, 4);
6620 while (*input_line_pointer
++ == ',');
6622 input_line_pointer
--;
6623 demand_empty_rest_of_line ();
6628 i386_immediate (char *imm_start
)
6630 char *save_input_line_pointer
;
6631 char *gotfree_input_line
;
6634 i386_operand_type types
;
6636 operand_type_set (&types
, ~0);
6638 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6640 as_bad (_("at most %d immediate operands are allowed"),
6641 MAX_IMMEDIATE_OPERANDS
);
6645 exp
= &im_expressions
[i
.imm_operands
++];
6646 i
.op
[this_operand
].imms
= exp
;
6648 if (is_space_char (*imm_start
))
6651 save_input_line_pointer
= input_line_pointer
;
6652 input_line_pointer
= imm_start
;
6654 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6655 if (gotfree_input_line
)
6656 input_line_pointer
= gotfree_input_line
;
6658 exp_seg
= expression (exp
);
6661 if (*input_line_pointer
)
6662 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6664 input_line_pointer
= save_input_line_pointer
;
6665 if (gotfree_input_line
)
6667 free (gotfree_input_line
);
6669 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6670 exp
->X_op
= O_illegal
;
6673 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6677 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6678 i386_operand_type types
, const char *imm_start
)
6680 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6683 as_bad (_("missing or invalid immediate expression `%s'"),
6687 else if (exp
->X_op
== O_constant
)
6689 /* Size it properly later. */
6690 i
.types
[this_operand
].bitfield
.imm64
= 1;
6691 /* If not 64bit, sign extend val. */
6692 if (flag_code
!= CODE_64BIT
6693 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6695 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6697 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6698 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6699 && exp_seg
!= absolute_section
6700 && exp_seg
!= text_section
6701 && exp_seg
!= data_section
6702 && exp_seg
!= bss_section
6703 && exp_seg
!= undefined_section
6704 && !bfd_is_com_section (exp_seg
))
6706 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6710 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6713 as_bad (_("illegal immediate register operand %s"), imm_start
);
6718 /* This is an address. The size of the address will be
6719 determined later, depending on destination register,
6720 suffix, or the default for the section. */
6721 i
.types
[this_operand
].bitfield
.imm8
= 1;
6722 i
.types
[this_operand
].bitfield
.imm16
= 1;
6723 i
.types
[this_operand
].bitfield
.imm32
= 1;
6724 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6725 i
.types
[this_operand
].bitfield
.imm64
= 1;
6726 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6734 i386_scale (char *scale
)
6737 char *save
= input_line_pointer
;
6739 input_line_pointer
= scale
;
6740 val
= get_absolute_expression ();
6745 i
.log2_scale_factor
= 0;
6748 i
.log2_scale_factor
= 1;
6751 i
.log2_scale_factor
= 2;
6754 i
.log2_scale_factor
= 3;
6758 char sep
= *input_line_pointer
;
6760 *input_line_pointer
= '\0';
6761 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6763 *input_line_pointer
= sep
;
6764 input_line_pointer
= save
;
6768 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6770 as_warn (_("scale factor of %d without an index register"),
6771 1 << i
.log2_scale_factor
);
6772 i
.log2_scale_factor
= 0;
6774 scale
= input_line_pointer
;
6775 input_line_pointer
= save
;
6780 i386_displacement (char *disp_start
, char *disp_end
)
6784 char *save_input_line_pointer
;
6785 char *gotfree_input_line
;
6787 i386_operand_type bigdisp
, types
= anydisp
;
6790 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6792 as_bad (_("at most %d displacement operands are allowed"),
6793 MAX_MEMORY_OPERANDS
);
6797 operand_type_set (&bigdisp
, 0);
6798 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6799 || (!current_templates
->start
->opcode_modifier
.jump
6800 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6802 bigdisp
.bitfield
.disp32
= 1;
6803 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6804 if (flag_code
== CODE_64BIT
)
6808 bigdisp
.bitfield
.disp32s
= 1;
6809 bigdisp
.bitfield
.disp64
= 1;
6812 else if ((flag_code
== CODE_16BIT
) ^ override
)
6814 bigdisp
.bitfield
.disp32
= 0;
6815 bigdisp
.bitfield
.disp16
= 1;
6820 /* For PC-relative branches, the width of the displacement
6821 is dependent upon data size, not address size. */
6822 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6823 if (flag_code
== CODE_64BIT
)
6825 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6826 bigdisp
.bitfield
.disp16
= 1;
6829 bigdisp
.bitfield
.disp32
= 1;
6830 bigdisp
.bitfield
.disp32s
= 1;
6836 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6838 : LONG_MNEM_SUFFIX
));
6839 bigdisp
.bitfield
.disp32
= 1;
6840 if ((flag_code
== CODE_16BIT
) ^ override
)
6842 bigdisp
.bitfield
.disp32
= 0;
6843 bigdisp
.bitfield
.disp16
= 1;
6847 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6850 exp
= &disp_expressions
[i
.disp_operands
];
6851 i
.op
[this_operand
].disps
= exp
;
6853 save_input_line_pointer
= input_line_pointer
;
6854 input_line_pointer
= disp_start
;
6855 END_STRING_AND_SAVE (disp_end
);
6857 #ifndef GCC_ASM_O_HACK
6858 #define GCC_ASM_O_HACK 0
6861 END_STRING_AND_SAVE (disp_end
+ 1);
6862 if (i
.types
[this_operand
].bitfield
.baseIndex
6863 && displacement_string_end
[-1] == '+')
6865 /* This hack is to avoid a warning when using the "o"
6866 constraint within gcc asm statements.
6869 #define _set_tssldt_desc(n,addr,limit,type) \
6870 __asm__ __volatile__ ( \
6872 "movw %w1,2+%0\n\t" \
6874 "movb %b1,4+%0\n\t" \
6875 "movb %4,5+%0\n\t" \
6876 "movb $0,6+%0\n\t" \
6877 "movb %h1,7+%0\n\t" \
6879 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6881 This works great except that the output assembler ends
6882 up looking a bit weird if it turns out that there is
6883 no offset. You end up producing code that looks like:
6896 So here we provide the missing zero. */
6898 *displacement_string_end
= '0';
6901 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6902 if (gotfree_input_line
)
6903 input_line_pointer
= gotfree_input_line
;
6905 exp_seg
= expression (exp
);
6908 if (*input_line_pointer
)
6909 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6911 RESTORE_END_STRING (disp_end
+ 1);
6913 input_line_pointer
= save_input_line_pointer
;
6914 if (gotfree_input_line
)
6916 free (gotfree_input_line
);
6918 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6919 exp
->X_op
= O_illegal
;
6922 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6924 RESTORE_END_STRING (disp_end
);
6930 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6931 i386_operand_type types
, const char *disp_start
)
6933 i386_operand_type bigdisp
;
6936 /* We do this to make sure that the section symbol is in
6937 the symbol table. We will ultimately change the relocation
6938 to be relative to the beginning of the section. */
6939 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6940 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6941 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6943 if (exp
->X_op
!= O_symbol
)
6946 if (S_IS_LOCAL (exp
->X_add_symbol
)
6947 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
6948 && S_GET_SEGMENT (exp
->X_add_symbol
) != expr_section
)
6949 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6950 exp
->X_op
= O_subtract
;
6951 exp
->X_op_symbol
= GOT_symbol
;
6952 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6953 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6954 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6955 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6957 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6960 else if (exp
->X_op
== O_absent
6961 || exp
->X_op
== O_illegal
6962 || exp
->X_op
== O_big
)
6965 as_bad (_("missing or invalid displacement expression `%s'"),
6970 else if (flag_code
== CODE_64BIT
6971 && !i
.prefix
[ADDR_PREFIX
]
6972 && exp
->X_op
== O_constant
)
6974 /* Since displacement is signed extended to 64bit, don't allow
6975 disp32 and turn off disp32s if they are out of range. */
6976 i
.types
[this_operand
].bitfield
.disp32
= 0;
6977 if (!fits_in_signed_long (exp
->X_add_number
))
6979 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6980 if (i
.types
[this_operand
].bitfield
.baseindex
)
6982 as_bad (_("0x%lx out range of signed 32bit displacement"),
6983 (long) exp
->X_add_number
);
6989 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6990 else if (exp
->X_op
!= O_constant
6991 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6992 && exp_seg
!= absolute_section
6993 && exp_seg
!= text_section
6994 && exp_seg
!= data_section
6995 && exp_seg
!= bss_section
6996 && exp_seg
!= undefined_section
6997 && !bfd_is_com_section (exp_seg
))
6999 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
7004 /* Check if this is a displacement only operand. */
7005 bigdisp
= i
.types
[this_operand
];
7006 bigdisp
.bitfield
.disp8
= 0;
7007 bigdisp
.bitfield
.disp16
= 0;
7008 bigdisp
.bitfield
.disp32
= 0;
7009 bigdisp
.bitfield
.disp32s
= 0;
7010 bigdisp
.bitfield
.disp64
= 0;
7011 if (operand_type_all_zero (&bigdisp
))
7012 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
7018 /* Make sure the memory operand we've been dealt is valid.
7019 Return 1 on success, 0 on a failure. */
7022 i386_index_check (const char *operand_string
)
7025 const char *kind
= "base/index";
7026 #if INFER_ADDR_PREFIX
7032 if (current_templates
->start
->opcode_modifier
.isstring
7033 && !current_templates
->start
->opcode_modifier
.immext
7034 && (current_templates
->end
[-1].opcode_modifier
.isstring
7037 /* Memory operands of string insns are special in that they only allow
7038 a single register (rDI, rSI, or rBX) as their memory address. */
7039 unsigned int expected
;
7041 kind
= "string address";
7043 if (current_templates
->start
->opcode_modifier
.w
)
7045 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
7047 if (!type
.bitfield
.baseindex
7048 || ((!i
.mem_operands
!= !intel_syntax
)
7049 && current_templates
->end
[-1].operand_types
[1]
7050 .bitfield
.baseindex
))
7051 type
= current_templates
->end
[-1].operand_types
[1];
7052 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
7055 expected
= 3 /* rBX */;
7057 if (!i
.base_reg
|| i
.index_reg
7058 || operand_type_check (i
.types
[this_operand
], disp
))
7060 else if (!(flag_code
== CODE_64BIT
7061 ? i
.prefix
[ADDR_PREFIX
]
7062 ? i
.base_reg
->reg_type
.bitfield
.reg32
7063 : i
.base_reg
->reg_type
.bitfield
.reg64
7064 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7065 ? i
.base_reg
->reg_type
.bitfield
.reg32
7066 : i
.base_reg
->reg_type
.bitfield
.reg16
))
7068 else if (i
.base_reg
->reg_num
!= expected
)
7075 for (j
= 0; j
< i386_regtab_size
; ++j
)
7076 if ((flag_code
== CODE_64BIT
7077 ? i
.prefix
[ADDR_PREFIX
]
7078 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7079 : i386_regtab
[j
].reg_type
.bitfield
.reg64
7080 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
7081 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
7082 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
7083 && i386_regtab
[j
].reg_num
== expected
)
7085 gas_assert (j
< i386_regtab_size
);
7086 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
7088 intel_syntax
? '[' : '(',
7090 i386_regtab
[j
].reg_name
,
7091 intel_syntax
? ']' : ')');
7095 else if (flag_code
== CODE_64BIT
)
7098 && ((i
.prefix
[ADDR_PREFIX
] == 0
7099 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7100 || (i
.prefix
[ADDR_PREFIX
]
7101 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7103 || i
.base_reg
->reg_num
!=
7104 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7106 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7107 || (i
.prefix
[ADDR_PREFIX
] == 0
7108 && i
.index_reg
->reg_num
!= RegRiz
7109 && !i
.index_reg
->reg_type
.bitfield
.reg64
7111 || (i
.prefix
[ADDR_PREFIX
]
7112 && i
.index_reg
->reg_num
!= RegEiz
7113 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7118 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7122 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7123 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7125 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7126 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7128 && i
.base_reg
->reg_num
< 6
7129 && i
.index_reg
->reg_num
>= 6
7130 && i
.log2_scale_factor
== 0))))
7137 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7139 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7140 && i
.index_reg
->reg_num
!= RegEiz
)
7141 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7147 #if INFER_ADDR_PREFIX
7148 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7150 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7152 /* Change the size of any displacement too. At most one of
7153 Disp16 or Disp32 is set.
7154 FIXME. There doesn't seem to be any real need for separate
7155 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7156 Removing them would probably clean up the code quite a lot. */
7157 if (flag_code
!= CODE_64BIT
7158 && (i
.types
[this_operand
].bitfield
.disp16
7159 || i
.types
[this_operand
].bitfield
.disp32
))
7160 i
.types
[this_operand
]
7161 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7166 as_bad (_("`%s' is not a valid %s expression"),
7171 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7173 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7174 ? flag_code
== CODE_32BIT
7183 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7187 i386_att_operand (char *operand_string
)
7191 char *op_string
= operand_string
;
7193 if (is_space_char (*op_string
))
7196 /* We check for an absolute prefix (differentiating,
7197 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7198 if (*op_string
== ABSOLUTE_PREFIX
)
7201 if (is_space_char (*op_string
))
7203 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7206 /* Check if operand is a register. */
7207 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7209 i386_operand_type temp
;
7211 /* Check for a segment override by searching for ':' after a
7212 segment register. */
7214 if (is_space_char (*op_string
))
7216 if (*op_string
== ':'
7217 && (r
->reg_type
.bitfield
.sreg2
7218 || r
->reg_type
.bitfield
.sreg3
))
7223 i
.seg
[i
.mem_operands
] = &es
;
7226 i
.seg
[i
.mem_operands
] = &cs
;
7229 i
.seg
[i
.mem_operands
] = &ss
;
7232 i
.seg
[i
.mem_operands
] = &ds
;
7235 i
.seg
[i
.mem_operands
] = &fs
;
7238 i
.seg
[i
.mem_operands
] = &gs
;
7242 /* Skip the ':' and whitespace. */
7244 if (is_space_char (*op_string
))
7247 if (!is_digit_char (*op_string
)
7248 && !is_identifier_char (*op_string
)
7249 && *op_string
!= '('
7250 && *op_string
!= ABSOLUTE_PREFIX
)
7252 as_bad (_("bad memory operand `%s'"), op_string
);
7255 /* Handle case of %es:*foo. */
7256 if (*op_string
== ABSOLUTE_PREFIX
)
7259 if (is_space_char (*op_string
))
7261 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7263 goto do_memory_reference
;
7267 as_bad (_("junk `%s' after register"), op_string
);
7271 temp
.bitfield
.baseindex
= 0;
7272 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7274 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7275 i
.op
[this_operand
].regs
= r
;
7278 else if (*op_string
== REGISTER_PREFIX
)
7280 as_bad (_("bad register name `%s'"), op_string
);
7283 else if (*op_string
== IMMEDIATE_PREFIX
)
7286 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7288 as_bad (_("immediate operand illegal with absolute jump"));
7291 if (!i386_immediate (op_string
))
7294 else if (is_digit_char (*op_string
)
7295 || is_identifier_char (*op_string
)
7296 || *op_string
== '(')
7298 /* This is a memory reference of some sort. */
7301 /* Start and end of displacement string expression (if found). */
7302 char *displacement_string_start
;
7303 char *displacement_string_end
;
7305 do_memory_reference
:
7306 if ((i
.mem_operands
== 1
7307 && !current_templates
->start
->opcode_modifier
.isstring
)
7308 || i
.mem_operands
== 2)
7310 as_bad (_("too many memory references for `%s'"),
7311 current_templates
->start
->name
);
7315 /* Check for base index form. We detect the base index form by
7316 looking for an ')' at the end of the operand, searching
7317 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7319 base_string
= op_string
+ strlen (op_string
);
7322 if (is_space_char (*base_string
))
7325 /* If we only have a displacement, set-up for it to be parsed later. */
7326 displacement_string_start
= op_string
;
7327 displacement_string_end
= base_string
+ 1;
7329 if (*base_string
== ')')
7332 unsigned int parens_balanced
= 1;
7333 /* We've already checked that the number of left & right ()'s are
7334 equal, so this loop will not be infinite. */
7338 if (*base_string
== ')')
7340 if (*base_string
== '(')
7343 while (parens_balanced
);
7345 temp_string
= base_string
;
7347 /* Skip past '(' and whitespace. */
7349 if (is_space_char (*base_string
))
7352 if (*base_string
== ','
7353 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7356 displacement_string_end
= temp_string
;
7358 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7362 base_string
= end_op
;
7363 if (is_space_char (*base_string
))
7367 /* There may be an index reg or scale factor here. */
7368 if (*base_string
== ',')
7371 if (is_space_char (*base_string
))
7374 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7377 base_string
= end_op
;
7378 if (is_space_char (*base_string
))
7380 if (*base_string
== ',')
7383 if (is_space_char (*base_string
))
7386 else if (*base_string
!= ')')
7388 as_bad (_("expecting `,' or `)' "
7389 "after index register in `%s'"),
7394 else if (*base_string
== REGISTER_PREFIX
)
7396 as_bad (_("bad register name `%s'"), base_string
);
7400 /* Check for scale factor. */
7401 if (*base_string
!= ')')
7403 char *end_scale
= i386_scale (base_string
);
7408 base_string
= end_scale
;
7409 if (is_space_char (*base_string
))
7411 if (*base_string
!= ')')
7413 as_bad (_("expecting `)' "
7414 "after scale factor in `%s'"),
7419 else if (!i
.index_reg
)
7421 as_bad (_("expecting index register or scale factor "
7422 "after `,'; got '%c'"),
7427 else if (*base_string
!= ')')
7429 as_bad (_("expecting `,' or `)' "
7430 "after base register in `%s'"),
7435 else if (*base_string
== REGISTER_PREFIX
)
7437 as_bad (_("bad register name `%s'"), base_string
);
7442 /* If there's an expression beginning the operand, parse it,
7443 assuming displacement_string_start and
7444 displacement_string_end are meaningful. */
7445 if (displacement_string_start
!= displacement_string_end
)
7447 if (!i386_displacement (displacement_string_start
,
7448 displacement_string_end
))
7452 /* Special case for (%dx) while doing input/output op. */
7454 && operand_type_equal (&i
.base_reg
->reg_type
,
7455 ®16_inoutportreg
)
7457 && i
.log2_scale_factor
== 0
7458 && i
.seg
[i
.mem_operands
] == 0
7459 && !operand_type_check (i
.types
[this_operand
], disp
))
7461 i
.types
[this_operand
] = inoutportreg
;
7465 if (i386_index_check (operand_string
) == 0)
7467 i
.types
[this_operand
].bitfield
.mem
= 1;
7472 /* It's not a memory operand; argh! */
7473 as_bad (_("invalid char %s beginning operand %d `%s'"),
7474 output_invalid (*op_string
),
7479 return 1; /* Normal return. */
7482 /* md_estimate_size_before_relax()
7484 Called just before relax() for rs_machine_dependent frags. The x86
7485 assembler uses these frags to handle variable size jump
7488 Any symbol that is now undefined will not become defined.
7489 Return the correct fr_subtype in the frag.
7490 Return the initial "guess for variable size of frag" to caller.
7491 The guess is actually the growth beyond the fixed part. Whatever
7492 we do to grow the fixed or variable part contributes to our
7496 md_estimate_size_before_relax (fragP
, segment
)
7500 /* We've already got fragP->fr_subtype right; all we have to do is
7501 check for un-relaxable symbols. On an ELF system, we can't relax
7502 an externally visible symbol, because it may be overridden by a
7504 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7505 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7507 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7508 || S_IS_WEAK (fragP
->fr_symbol
)
7509 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7510 & BSF_GNU_INDIRECT_FUNCTION
))))
7512 #if defined (OBJ_COFF) && defined (TE_PE)
7513 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7514 && S_IS_WEAK (fragP
->fr_symbol
))
7518 /* Symbol is undefined in this segment, or we need to keep a
7519 reloc so that weak symbols can be overridden. */
7520 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7521 enum bfd_reloc_code_real reloc_type
;
7522 unsigned char *opcode
;
7525 if (fragP
->fr_var
!= NO_RELOC
)
7526 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7528 reloc_type
= BFD_RELOC_16_PCREL
;
7530 reloc_type
= BFD_RELOC_32_PCREL
;
7532 old_fr_fix
= fragP
->fr_fix
;
7533 opcode
= (unsigned char *) fragP
->fr_opcode
;
7535 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7538 /* Make jmp (0xeb) a (d)word displacement jump. */
7540 fragP
->fr_fix
+= size
;
7541 fix_new (fragP
, old_fr_fix
, size
,
7543 fragP
->fr_offset
, 1,
7549 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7551 /* Negate the condition, and branch past an
7552 unconditional jump. */
7555 /* Insert an unconditional jump. */
7557 /* We added two extra opcode bytes, and have a two byte
7559 fragP
->fr_fix
+= 2 + 2;
7560 fix_new (fragP
, old_fr_fix
+ 2, 2,
7562 fragP
->fr_offset
, 1,
7569 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7574 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7576 fragP
->fr_offset
, 1,
7578 fixP
->fx_signed
= 1;
7582 /* This changes the byte-displacement jump 0x7N
7583 to the (d)word-displacement jump 0x0f,0x8N. */
7584 opcode
[1] = opcode
[0] + 0x10;
7585 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7586 /* We've added an opcode byte. */
7587 fragP
->fr_fix
+= 1 + size
;
7588 fix_new (fragP
, old_fr_fix
+ 1, size
,
7590 fragP
->fr_offset
, 1,
7595 BAD_CASE (fragP
->fr_subtype
);
7599 return fragP
->fr_fix
- old_fr_fix
;
7602 /* Guess size depending on current relax state. Initially the relax
7603 state will correspond to a short jump and we return 1, because
7604 the variable part of the frag (the branch offset) is one byte
7605 long. However, we can relax a section more than once and in that
7606 case we must either set fr_subtype back to the unrelaxed state,
7607 or return the value for the appropriate branch. */
7608 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7611 /* Called after relax() is finished.
7613 In: Address of frag.
7614 fr_type == rs_machine_dependent.
7615 fr_subtype is what the address relaxed to.
7617 Out: Any fixSs and constants are set up.
7618 Caller will turn frag into a ".space 0". */
7621 md_convert_frag (abfd
, sec
, fragP
)
7622 bfd
*abfd ATTRIBUTE_UNUSED
;
7623 segT sec ATTRIBUTE_UNUSED
;
7626 unsigned char *opcode
;
7627 unsigned char *where_to_put_displacement
= NULL
;
7628 offsetT target_address
;
7629 offsetT opcode_address
;
7630 unsigned int extension
= 0;
7631 offsetT displacement_from_opcode_start
;
7633 opcode
= (unsigned char *) fragP
->fr_opcode
;
7635 /* Address we want to reach in file space. */
7636 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7638 /* Address opcode resides at in file space. */
7639 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7641 /* Displacement from opcode start to fill into instruction. */
7642 displacement_from_opcode_start
= target_address
- opcode_address
;
7644 if ((fragP
->fr_subtype
& BIG
) == 0)
7646 /* Don't have to change opcode. */
7647 extension
= 1; /* 1 opcode + 1 displacement */
7648 where_to_put_displacement
= &opcode
[1];
7652 if (no_cond_jump_promotion
7653 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7654 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7655 _("long jump required"));
7657 switch (fragP
->fr_subtype
)
7659 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7660 extension
= 4; /* 1 opcode + 4 displacement */
7662 where_to_put_displacement
= &opcode
[1];
7665 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7666 extension
= 2; /* 1 opcode + 2 displacement */
7668 where_to_put_displacement
= &opcode
[1];
7671 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7672 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7673 extension
= 5; /* 2 opcode + 4 displacement */
7674 opcode
[1] = opcode
[0] + 0x10;
7675 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7676 where_to_put_displacement
= &opcode
[2];
7679 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7680 extension
= 3; /* 2 opcode + 2 displacement */
7681 opcode
[1] = opcode
[0] + 0x10;
7682 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7683 where_to_put_displacement
= &opcode
[2];
7686 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7691 where_to_put_displacement
= &opcode
[3];
7695 BAD_CASE (fragP
->fr_subtype
);
7700 /* If size if less then four we are sure that the operand fits,
7701 but if it's 4, then it could be that the displacement is larger
7703 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7705 && ((addressT
) (displacement_from_opcode_start
- extension
7706 + ((addressT
) 1 << 31))
7707 > (((addressT
) 2 << 31) - 1)))
7709 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7710 _("jump target out of range"));
7711 /* Make us emit 0. */
7712 displacement_from_opcode_start
= extension
;
7714 /* Now put displacement after opcode. */
7715 md_number_to_chars ((char *) where_to_put_displacement
,
7716 (valueT
) (displacement_from_opcode_start
- extension
),
7717 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7718 fragP
->fr_fix
+= extension
;
7721 /* Apply a fixup (fixS) to segment data, once it has been determined
7722 by our caller that we have all the info we need to fix it up.
7724 On the 386, immediates, displacements, and data pointers are all in
7725 the same (little-endian) format, so we don't need to care about which
7729 md_apply_fix (fixP
, valP
, seg
)
7730 /* The fix we're to put in. */
7732 /* Pointer to the value of the bits. */
7734 /* Segment fix is from. */
7735 segT seg ATTRIBUTE_UNUSED
;
7737 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7738 valueT value
= *valP
;
7740 #if !defined (TE_Mach)
7743 switch (fixP
->fx_r_type
)
7749 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7752 case BFD_RELOC_X86_64_32S
:
7753 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7756 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7759 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7764 if (fixP
->fx_addsy
!= NULL
7765 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7766 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7767 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7768 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7769 && !use_rela_relocations
)
7771 /* This is a hack. There should be a better way to handle this.
7772 This covers for the fact that bfd_install_relocation will
7773 subtract the current location (for partial_inplace, PC relative
7774 relocations); see more below. */
7778 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7781 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7783 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7786 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7789 || (symbol_section_p (fixP
->fx_addsy
)
7790 && sym_seg
!= absolute_section
))
7791 && !generic_force_reloc (fixP
))
7793 /* Yes, we add the values in twice. This is because
7794 bfd_install_relocation subtracts them out again. I think
7795 bfd_install_relocation is broken, but I don't dare change
7797 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7801 #if defined (OBJ_COFF) && defined (TE_PE)
7802 /* For some reason, the PE format does not store a
7803 section address offset for a PC relative symbol. */
7804 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7805 || S_IS_WEAK (fixP
->fx_addsy
))
7806 value
+= md_pcrel_from (fixP
);
7809 #if defined (OBJ_COFF) && defined (TE_PE)
7810 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7812 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7816 /* Fix a few things - the dynamic linker expects certain values here,
7817 and we must not disappoint it. */
7818 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7819 if (IS_ELF
&& fixP
->fx_addsy
)
7820 switch (fixP
->fx_r_type
)
7822 case BFD_RELOC_386_PLT32
:
7823 case BFD_RELOC_X86_64_PLT32
:
7824 /* Make the jump instruction point to the address of the operand. At
7825 runtime we merely add the offset to the actual PLT entry. */
7829 case BFD_RELOC_386_TLS_GD
:
7830 case BFD_RELOC_386_TLS_LDM
:
7831 case BFD_RELOC_386_TLS_IE_32
:
7832 case BFD_RELOC_386_TLS_IE
:
7833 case BFD_RELOC_386_TLS_GOTIE
:
7834 case BFD_RELOC_386_TLS_GOTDESC
:
7835 case BFD_RELOC_X86_64_TLSGD
:
7836 case BFD_RELOC_X86_64_TLSLD
:
7837 case BFD_RELOC_X86_64_GOTTPOFF
:
7838 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7839 value
= 0; /* Fully resolved at runtime. No addend. */
7841 case BFD_RELOC_386_TLS_LE
:
7842 case BFD_RELOC_386_TLS_LDO_32
:
7843 case BFD_RELOC_386_TLS_LE_32
:
7844 case BFD_RELOC_X86_64_DTPOFF32
:
7845 case BFD_RELOC_X86_64_DTPOFF64
:
7846 case BFD_RELOC_X86_64_TPOFF32
:
7847 case BFD_RELOC_X86_64_TPOFF64
:
7848 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7851 case BFD_RELOC_386_TLS_DESC_CALL
:
7852 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7853 value
= 0; /* Fully resolved at runtime. No addend. */
7854 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7858 case BFD_RELOC_386_GOT32
:
7859 case BFD_RELOC_X86_64_GOT32
:
7860 value
= 0; /* Fully resolved at runtime. No addend. */
7863 case BFD_RELOC_VTABLE_INHERIT
:
7864 case BFD_RELOC_VTABLE_ENTRY
:
7871 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7873 #endif /* !defined (TE_Mach) */
7875 /* Are we finished with this relocation now? */
7876 if (fixP
->fx_addsy
== NULL
)
7878 #if defined (OBJ_COFF) && defined (TE_PE)
7879 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7882 /* Remember value for tc_gen_reloc. */
7883 fixP
->fx_addnumber
= value
;
7884 /* Clear out the frag for now. */
7888 else if (use_rela_relocations
)
7890 fixP
->fx_no_overflow
= 1;
7891 /* Remember value for tc_gen_reloc. */
7892 fixP
->fx_addnumber
= value
;
7896 md_number_to_chars (p
, value
, fixP
->fx_size
);
7900 md_atof (int type
, char *litP
, int *sizeP
)
7902 /* This outputs the LITTLENUMs in REVERSE order;
7903 in accord with the bigendian 386. */
7904 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7907 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7910 output_invalid (int c
)
7913 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7916 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7917 "(0x%x)", (unsigned char) c
);
7918 return output_invalid_buf
;
7921 /* REG_STRING starts *before* REGISTER_PREFIX. */
7923 static const reg_entry
*
7924 parse_real_register (char *reg_string
, char **end_op
)
7926 char *s
= reg_string
;
7928 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7931 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7932 if (*s
== REGISTER_PREFIX
)
7935 if (is_space_char (*s
))
7939 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7941 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7942 return (const reg_entry
*) NULL
;
7946 /* For naked regs, make sure that we are not dealing with an identifier.
7947 This prevents confusing an identifier like `eax_var' with register
7949 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7950 return (const reg_entry
*) NULL
;
7954 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7956 /* Handle floating point regs, allowing spaces in the (i) part. */
7957 if (r
== i386_regtab
/* %st is first entry of table */)
7959 if (is_space_char (*s
))
7964 if (is_space_char (*s
))
7966 if (*s
>= '0' && *s
<= '7')
7970 if (is_space_char (*s
))
7975 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7980 /* We have "%st(" then garbage. */
7981 return (const reg_entry
*) NULL
;
7985 if (r
== NULL
|| allow_pseudo_reg
)
7988 if (operand_type_all_zero (&r
->reg_type
))
7989 return (const reg_entry
*) NULL
;
7991 if ((r
->reg_type
.bitfield
.reg32
7992 || r
->reg_type
.bitfield
.sreg3
7993 || r
->reg_type
.bitfield
.control
7994 || r
->reg_type
.bitfield
.debug
7995 || r
->reg_type
.bitfield
.test
)
7996 && !cpu_arch_flags
.bitfield
.cpui386
)
7997 return (const reg_entry
*) NULL
;
7999 if (r
->reg_type
.bitfield
.floatreg
8000 && !cpu_arch_flags
.bitfield
.cpu8087
8001 && !cpu_arch_flags
.bitfield
.cpu287
8002 && !cpu_arch_flags
.bitfield
.cpu387
)
8003 return (const reg_entry
*) NULL
;
8005 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
8006 return (const reg_entry
*) NULL
;
8008 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
8009 return (const reg_entry
*) NULL
;
8011 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
8012 return (const reg_entry
*) NULL
;
8014 /* Don't allow fake index register unless allow_index_reg isn't 0. */
8015 if (!allow_index_reg
8016 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
8017 return (const reg_entry
*) NULL
;
8019 if (((r
->reg_flags
& (RegRex64
| RegRex
))
8020 || r
->reg_type
.bitfield
.reg64
)
8021 && (!cpu_arch_flags
.bitfield
.cpulm
8022 || !operand_type_equal (&r
->reg_type
, &control
))
8023 && flag_code
!= CODE_64BIT
)
8024 return (const reg_entry
*) NULL
;
8026 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
8027 return (const reg_entry
*) NULL
;
8032 /* REG_STRING starts *before* REGISTER_PREFIX. */
8034 static const reg_entry
*
8035 parse_register (char *reg_string
, char **end_op
)
8039 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
8040 r
= parse_real_register (reg_string
, end_op
);
8045 char *save
= input_line_pointer
;
8049 input_line_pointer
= reg_string
;
8050 c
= get_symbol_end ();
8051 symbolP
= symbol_find (reg_string
);
8052 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
8054 const expressionS
*e
= symbol_get_value_expression (symbolP
);
8056 know (e
->X_op
== O_register
);
8057 know (e
->X_add_number
>= 0
8058 && (valueT
) e
->X_add_number
< i386_regtab_size
);
8059 r
= i386_regtab
+ e
->X_add_number
;
8060 *end_op
= input_line_pointer
;
8062 *input_line_pointer
= c
;
8063 input_line_pointer
= save
;
8069 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
8072 char *end
= input_line_pointer
;
8075 r
= parse_register (name
, &input_line_pointer
);
8076 if (r
&& end
<= input_line_pointer
)
8078 *nextcharP
= *input_line_pointer
;
8079 *input_line_pointer
= 0;
8080 e
->X_op
= O_register
;
8081 e
->X_add_number
= r
- i386_regtab
;
8084 input_line_pointer
= end
;
8086 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
8090 md_operand (expressionS
*e
)
8095 switch (*input_line_pointer
)
8097 case REGISTER_PREFIX
:
8098 r
= parse_real_register (input_line_pointer
, &end
);
8101 e
->X_op
= O_register
;
8102 e
->X_add_number
= r
- i386_regtab
;
8103 input_line_pointer
= end
;
8108 gas_assert (intel_syntax
);
8109 end
= input_line_pointer
++;
8111 if (*input_line_pointer
== ']')
8113 ++input_line_pointer
;
8114 e
->X_op_symbol
= make_expr_symbol (e
);
8115 e
->X_add_symbol
= NULL
;
8116 e
->X_add_number
= 0;
8122 input_line_pointer
= end
;
8129 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8130 const char *md_shortopts
= "kVQ:sqn";
8132 const char *md_shortopts
= "qn";
8135 #define OPTION_32 (OPTION_MD_BASE + 0)
8136 #define OPTION_64 (OPTION_MD_BASE + 1)
8137 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8138 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8139 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8140 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8141 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8142 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8143 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8144 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8145 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8146 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8147 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8148 #define OPTION_N32 (OPTION_MD_BASE + 13)
8150 struct option md_longopts
[] =
8152 {"32", no_argument
, NULL
, OPTION_32
},
8153 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8154 || defined (TE_PE) || defined (TE_PEP))
8155 {"64", no_argument
, NULL
, OPTION_64
},
8157 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8158 {"n32", no_argument
, NULL
, OPTION_N32
},
8160 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8161 {"march", required_argument
, NULL
, OPTION_MARCH
},
8162 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8163 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8164 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8165 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8166 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8167 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8168 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8169 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8170 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8171 {NULL
, no_argument
, NULL
, 0}
8173 size_t md_longopts_size
= sizeof (md_longopts
);
8176 md_parse_option (int c
, char *arg
)
8184 optimize_align_code
= 0;
8191 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8192 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8193 should be emitted or not. FIXME: Not implemented. */
8197 /* -V: SVR4 argument to print version ID. */
8199 print_version_id ();
8202 /* -k: Ignore for FreeBSD compatibility. */
8207 /* -s: On i386 Solaris, this tells the native assembler to use
8208 .stab instead of .stab.excl. We always use .stab anyhow. */
8211 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8212 || defined (TE_PE) || defined (TE_PEP))
8215 const char **list
, **l
;
8217 list
= bfd_target_list ();
8218 for (l
= list
; *l
!= NULL
; l
++)
8219 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8220 || strcmp (*l
, "coff-x86-64") == 0
8221 || strcmp (*l
, "pe-x86-64") == 0
8222 || strcmp (*l
, "pei-x86-64") == 0)
8224 default_arch
= "x86_64";
8228 as_fatal (_("No compiled in support for x86_64"));
8234 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8238 const char **list
, **l
;
8240 list
= bfd_target_list ();
8241 for (l
= list
; *l
!= NULL
; l
++)
8242 if (CONST_STRNEQ (*l
, "elf32-x86-64"))
8244 default_arch
= "x86_64:32";
8248 as_fatal (_("No compiled in support for 32bit x86_64"));
8252 as_fatal (_("32bit x86_64 is only supported for ELF"));
8257 default_arch
= "i386";
8261 #ifdef SVR4_COMMENT_CHARS
8266 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8268 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8272 i386_comment_chars
= n
;
8278 arch
= xstrdup (arg
);
8282 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8283 next
= strchr (arch
, '+');
8286 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8288 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8291 if (! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8294 cpu_arch_name
= cpu_arch
[j
].name
;
8295 cpu_sub_arch_name
= NULL
;
8296 cpu_arch_flags
= cpu_arch
[j
].flags
;
8297 cpu_arch_isa
= cpu_arch
[j
].type
;
8298 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8299 if (!cpu_arch_tune_set
)
8301 cpu_arch_tune
= cpu_arch_isa
;
8302 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8306 else if (*cpu_arch
[j
].name
== '.'
8307 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8309 /* ISA entension. */
8310 i386_cpu_flags flags
;
8312 if (!cpu_arch
[j
].negated
)
8313 flags
= cpu_flags_or (cpu_arch_flags
,
8316 flags
= cpu_flags_and_not (cpu_arch_flags
,
8318 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8320 if (cpu_sub_arch_name
)
8322 char *name
= cpu_sub_arch_name
;
8323 cpu_sub_arch_name
= concat (name
,
8325 (const char *) NULL
);
8329 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8330 cpu_arch_flags
= flags
;
8336 if (j
>= ARRAY_SIZE (cpu_arch
))
8337 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8341 while (next
!= NULL
);
8346 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8347 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8349 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8351 cpu_arch_tune_set
= 1;
8352 cpu_arch_tune
= cpu_arch
[j
].type
;
8353 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8357 if (j
>= ARRAY_SIZE (cpu_arch
))
8358 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8361 case OPTION_MMNEMONIC
:
8362 if (strcasecmp (arg
, "att") == 0)
8364 else if (strcasecmp (arg
, "intel") == 0)
8367 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8370 case OPTION_MSYNTAX
:
8371 if (strcasecmp (arg
, "att") == 0)
8373 else if (strcasecmp (arg
, "intel") == 0)
8376 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8379 case OPTION_MINDEX_REG
:
8380 allow_index_reg
= 1;
8383 case OPTION_MNAKED_REG
:
8384 allow_naked_reg
= 1;
8387 case OPTION_MOLD_GCC
:
8391 case OPTION_MSSE2AVX
:
8395 case OPTION_MSSE_CHECK
:
8396 if (strcasecmp (arg
, "error") == 0)
8397 sse_check
= sse_check_error
;
8398 else if (strcasecmp (arg
, "warning") == 0)
8399 sse_check
= sse_check_warning
;
8400 else if (strcasecmp (arg
, "none") == 0)
8401 sse_check
= sse_check_none
;
8403 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8406 case OPTION_MAVXSCALAR
:
8407 if (strcasecmp (arg
, "128") == 0)
8409 else if (strcasecmp (arg
, "256") == 0)
8412 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8421 #define MESSAGE_TEMPLATE \
8425 show_arch (FILE *stream
, int ext
, int check
)
8427 static char message
[] = MESSAGE_TEMPLATE
;
8428 char *start
= message
+ 27;
8430 int size
= sizeof (MESSAGE_TEMPLATE
);
8437 left
= size
- (start
- message
);
8438 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8440 /* Should it be skipped? */
8441 if (cpu_arch
[j
].skip
)
8444 name
= cpu_arch
[j
].name
;
8445 len
= cpu_arch
[j
].len
;
8448 /* It is an extension. Skip if we aren't asked to show it. */
8459 /* It is an processor. Skip if we show only extension. */
8462 else if (check
&& ! cpu_arch
[j
].flags
.bitfield
.cpui386
)
8464 /* It is an impossible processor - skip. */
8468 /* Reserve 2 spaces for ", " or ",\0" */
8471 /* Check if there is any room. */
8479 p
= mempcpy (p
, name
, len
);
8483 /* Output the current message now and start a new one. */
8486 fprintf (stream
, "%s\n", message
);
8488 left
= size
- (start
- message
) - len
- 2;
8490 gas_assert (left
>= 0);
8492 p
= mempcpy (p
, name
, len
);
8497 fprintf (stream
, "%s\n", message
);
8501 md_show_usage (FILE *stream
)
8503 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8504 fprintf (stream
, _("\
8506 -V print assembler version number\n\
8509 fprintf (stream
, _("\
8510 -n Do not optimize code alignment\n\
8511 -q quieten some warnings\n"));
8512 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8513 fprintf (stream
, _("\
8516 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8517 || defined (TE_PE) || defined (TE_PEP))
8518 fprintf (stream
, _("\
8519 --32/--64/--n32 generate 32bit/64bit/n32bit code\n"));
8521 #ifdef SVR4_COMMENT_CHARS
8522 fprintf (stream
, _("\
8523 --divide do not treat `/' as a comment character\n"));
8525 fprintf (stream
, _("\
8526 --divide ignored\n"));
8528 fprintf (stream
, _("\
8529 -march=CPU[,+EXTENSION...]\n\
8530 generate code for CPU and EXTENSION, CPU is one of:\n"));
8531 show_arch (stream
, 0, 1);
8532 fprintf (stream
, _("\
8533 EXTENSION is combination of:\n"));
8534 show_arch (stream
, 1, 0);
8535 fprintf (stream
, _("\
8536 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8537 show_arch (stream
, 0, 0);
8538 fprintf (stream
, _("\
8539 -msse2avx encode SSE instructions with VEX prefix\n"));
8540 fprintf (stream
, _("\
8541 -msse-check=[none|error|warning]\n\
8542 check SSE instructions\n"));
8543 fprintf (stream
, _("\
8544 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8546 fprintf (stream
, _("\
8547 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8548 fprintf (stream
, _("\
8549 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8550 fprintf (stream
, _("\
8551 -mindex-reg support pseudo index registers\n"));
8552 fprintf (stream
, _("\
8553 -mnaked-reg don't require `%%' prefix for registers\n"));
8554 fprintf (stream
, _("\
8555 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8558 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8559 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8560 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8562 /* Pick the target format to use. */
8565 i386_target_format (void)
8567 if (!strncmp (default_arch
, "x86_64", 6))
8569 update_code_flag (CODE_64BIT
, 1);
8570 if (default_arch
[6] == '\0')
8571 x86_elf_abi
= X86_64_LP64_ABI
;
8573 x86_elf_abi
= X86_64_ILP32_ABI
;
8575 else if (!strcmp (default_arch
, "i386"))
8576 update_code_flag (CODE_32BIT
, 1);
8578 as_fatal (_("Unknown architecture"));
8580 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8581 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8582 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8583 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8585 switch (OUTPUT_FLAVOR
)
8587 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8588 case bfd_target_aout_flavour
:
8589 return AOUT_TARGET_FORMAT
;
8591 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8592 # if defined (TE_PE) || defined (TE_PEP)
8593 case bfd_target_coff_flavour
:
8594 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8595 # elif defined (TE_GO32)
8596 case bfd_target_coff_flavour
:
8599 case bfd_target_coff_flavour
:
8603 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8604 case bfd_target_elf_flavour
:
8608 switch (x86_elf_abi
)
8611 format
= ELF_TARGET_FORMAT
;
8613 case X86_64_LP64_ABI
:
8614 use_rela_relocations
= 1;
8616 format
= ELF_TARGET_FORMAT64
;
8618 case X86_64_ILP32_ABI
:
8619 use_rela_relocations
= 1;
8621 format
= ELF_TARGET_FORMAT32
;
8624 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8626 if (x86_elf_abi
!= X86_64_LP64_ABI
)
8627 as_fatal (_("Intel L1OM is 64bit only"));
8628 return ELF_TARGET_L1OM_FORMAT
;
8634 #if defined (OBJ_MACH_O)
8635 case bfd_target_mach_o_flavour
:
8636 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8644 #endif /* OBJ_MAYBE_ more than one */
8646 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8648 i386_elf_emit_arch_note (void)
8650 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8653 asection
*seg
= now_seg
;
8654 subsegT subseg
= now_subseg
;
8655 Elf_Internal_Note i_note
;
8656 Elf_External_Note e_note
;
8657 asection
*note_secp
;
8660 /* Create the .note section. */
8661 note_secp
= subseg_new (".note", 0);
8662 bfd_set_section_flags (stdoutput
,
8664 SEC_HAS_CONTENTS
| SEC_READONLY
);
8666 /* Process the arch string. */
8667 len
= strlen (cpu_arch_name
);
8669 i_note
.namesz
= len
+ 1;
8671 i_note
.type
= NT_ARCH
;
8672 p
= frag_more (sizeof (e_note
.namesz
));
8673 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8674 p
= frag_more (sizeof (e_note
.descsz
));
8675 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8676 p
= frag_more (sizeof (e_note
.type
));
8677 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8678 p
= frag_more (len
+ 1);
8679 strcpy (p
, cpu_arch_name
);
8681 frag_align (2, 0, 0);
8683 subseg_set (seg
, subseg
);
8689 md_undefined_symbol (name
)
8692 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8693 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8694 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8695 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8699 if (symbol_find (name
))
8700 as_bad (_("GOT already in symbol table"));
8701 GOT_symbol
= symbol_new (name
, undefined_section
,
8702 (valueT
) 0, &zero_address_frag
);
8709 /* Round up a section size to the appropriate boundary. */
8712 md_section_align (segment
, size
)
8713 segT segment ATTRIBUTE_UNUSED
;
8716 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8717 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8719 /* For a.out, force the section size to be aligned. If we don't do
8720 this, BFD will align it for us, but it will not write out the
8721 final bytes of the section. This may be a bug in BFD, but it is
8722 easier to fix it here since that is how the other a.out targets
8726 align
= bfd_get_section_alignment (stdoutput
, segment
);
8727 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8734 /* On the i386, PC-relative offsets are relative to the start of the
8735 next instruction. That is, the address of the offset, plus its
8736 size, since the offset is always the last part of the insn. */
8739 md_pcrel_from (fixS
*fixP
)
8741 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8747 s_bss (int ignore ATTRIBUTE_UNUSED
)
8751 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8753 obj_elf_section_change_hook ();
8755 temp
= get_absolute_expression ();
8756 subseg_set (bss_section
, (subsegT
) temp
);
8757 demand_empty_rest_of_line ();
8763 i386_validate_fix (fixS
*fixp
)
8765 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8767 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8771 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8776 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8778 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8785 tc_gen_reloc (section
, fixp
)
8786 asection
*section ATTRIBUTE_UNUSED
;
8790 bfd_reloc_code_real_type code
;
8792 switch (fixp
->fx_r_type
)
8794 case BFD_RELOC_X86_64_PLT32
:
8795 case BFD_RELOC_X86_64_GOT32
:
8796 case BFD_RELOC_X86_64_GOTPCREL
:
8797 case BFD_RELOC_386_PLT32
:
8798 case BFD_RELOC_386_GOT32
:
8799 case BFD_RELOC_386_GOTOFF
:
8800 case BFD_RELOC_386_GOTPC
:
8801 case BFD_RELOC_386_TLS_GD
:
8802 case BFD_RELOC_386_TLS_LDM
:
8803 case BFD_RELOC_386_TLS_LDO_32
:
8804 case BFD_RELOC_386_TLS_IE_32
:
8805 case BFD_RELOC_386_TLS_IE
:
8806 case BFD_RELOC_386_TLS_GOTIE
:
8807 case BFD_RELOC_386_TLS_LE_32
:
8808 case BFD_RELOC_386_TLS_LE
:
8809 case BFD_RELOC_386_TLS_GOTDESC
:
8810 case BFD_RELOC_386_TLS_DESC_CALL
:
8811 case BFD_RELOC_X86_64_TLSGD
:
8812 case BFD_RELOC_X86_64_TLSLD
:
8813 case BFD_RELOC_X86_64_DTPOFF32
:
8814 case BFD_RELOC_X86_64_DTPOFF64
:
8815 case BFD_RELOC_X86_64_GOTTPOFF
:
8816 case BFD_RELOC_X86_64_TPOFF32
:
8817 case BFD_RELOC_X86_64_TPOFF64
:
8818 case BFD_RELOC_X86_64_GOTOFF64
:
8819 case BFD_RELOC_X86_64_GOTPC32
:
8820 case BFD_RELOC_X86_64_GOT64
:
8821 case BFD_RELOC_X86_64_GOTPCREL64
:
8822 case BFD_RELOC_X86_64_GOTPC64
:
8823 case BFD_RELOC_X86_64_GOTPLT64
:
8824 case BFD_RELOC_X86_64_PLTOFF64
:
8825 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8826 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8828 case BFD_RELOC_VTABLE_ENTRY
:
8829 case BFD_RELOC_VTABLE_INHERIT
:
8831 case BFD_RELOC_32_SECREL
:
8833 code
= fixp
->fx_r_type
;
8835 case BFD_RELOC_X86_64_32S
:
8836 if (!fixp
->fx_pcrel
)
8838 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8839 code
= fixp
->fx_r_type
;
8845 switch (fixp
->fx_size
)
8848 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8849 _("can not do %d byte pc-relative relocation"),
8851 code
= BFD_RELOC_32_PCREL
;
8853 case 1: code
= BFD_RELOC_8_PCREL
; break;
8854 case 2: code
= BFD_RELOC_16_PCREL
; break;
8855 case 4: code
= BFD_RELOC_32_PCREL
; break;
8857 case 8: code
= BFD_RELOC_64_PCREL
; break;
8863 switch (fixp
->fx_size
)
8866 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8867 _("can not do %d byte relocation"),
8869 code
= BFD_RELOC_32
;
8871 case 1: code
= BFD_RELOC_8
; break;
8872 case 2: code
= BFD_RELOC_16
; break;
8873 case 4: code
= BFD_RELOC_32
; break;
8875 case 8: code
= BFD_RELOC_64
; break;
8882 if ((code
== BFD_RELOC_32
8883 || code
== BFD_RELOC_32_PCREL
8884 || code
== BFD_RELOC_X86_64_32S
)
8886 && fixp
->fx_addsy
== GOT_symbol
)
8889 code
= BFD_RELOC_386_GOTPC
;
8891 code
= BFD_RELOC_X86_64_GOTPC32
;
8893 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8895 && fixp
->fx_addsy
== GOT_symbol
)
8897 code
= BFD_RELOC_X86_64_GOTPC64
;
8900 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8901 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8902 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8904 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8906 if (!use_rela_relocations
)
8908 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8909 vtable entry to be used in the relocation's section offset. */
8910 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8911 rel
->address
= fixp
->fx_offset
;
8912 #if defined (OBJ_COFF) && defined (TE_PE)
8913 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8914 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8919 /* Use the rela in 64bit mode. */
8922 if (!fixp
->fx_pcrel
)
8923 rel
->addend
= fixp
->fx_offset
;
8927 case BFD_RELOC_X86_64_PLT32
:
8928 case BFD_RELOC_X86_64_GOT32
:
8929 case BFD_RELOC_X86_64_GOTPCREL
:
8930 case BFD_RELOC_X86_64_TLSGD
:
8931 case BFD_RELOC_X86_64_TLSLD
:
8932 case BFD_RELOC_X86_64_GOTTPOFF
:
8933 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8934 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8935 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8938 rel
->addend
= (section
->vma
8940 + fixp
->fx_addnumber
8941 + md_pcrel_from (fixp
));
8946 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8947 if (rel
->howto
== NULL
)
8949 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8950 _("cannot represent relocation type %s"),
8951 bfd_get_reloc_code_name (code
));
8952 /* Set howto to a garbage value so that we can keep going. */
8953 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8954 gas_assert (rel
->howto
!= NULL
);
8960 #include "tc-i386-intel.c"
8963 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8965 int saved_naked_reg
;
8966 char saved_register_dot
;
8968 saved_naked_reg
= allow_naked_reg
;
8969 allow_naked_reg
= 1;
8970 saved_register_dot
= register_chars
['.'];
8971 register_chars
['.'] = '.';
8972 allow_pseudo_reg
= 1;
8973 expression_and_evaluate (exp
);
8974 allow_pseudo_reg
= 0;
8975 register_chars
['.'] = saved_register_dot
;
8976 allow_naked_reg
= saved_naked_reg
;
8978 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8980 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8982 exp
->X_op
= O_constant
;
8983 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8984 .dw2_regnum
[flag_code
>> 1];
8987 exp
->X_op
= O_illegal
;
8992 tc_x86_frame_initial_instructions (void)
8994 static unsigned int sp_regno
[2];
8996 if (!sp_regno
[flag_code
>> 1])
8998 char *saved_input
= input_line_pointer
;
8999 char sp
[][4] = {"esp", "rsp"};
9002 input_line_pointer
= sp
[flag_code
>> 1];
9003 tc_x86_parse_to_dw2regnum (&exp
);
9004 gas_assert (exp
.X_op
== O_constant
);
9005 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
9006 input_line_pointer
= saved_input
;
9009 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
9010 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
9014 i386_elf_section_type (const char *str
, size_t len
)
9016 if (flag_code
== CODE_64BIT
9017 && len
== sizeof ("unwind") - 1
9018 && strncmp (str
, "unwind", 6) == 0)
9019 return SHT_X86_64_UNWIND
;
9026 i386_solaris_fix_up_eh_frame (segT sec
)
9028 if (flag_code
== CODE_64BIT
)
9029 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
9035 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
9039 exp
.X_op
= O_secrel
;
9040 exp
.X_add_symbol
= symbol
;
9041 exp
.X_add_number
= 0;
9042 emit_expr (&exp
, size
);
9046 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
9047 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
9050 x86_64_section_letter (int letter
, char **ptr_msg
)
9052 if (flag_code
== CODE_64BIT
)
9055 return SHF_X86_64_LARGE
;
9057 *ptr_msg
= _("bad .section directive: want a,l,w,x,M,S,G,T in string");
9060 *ptr_msg
= _("bad .section directive: want a,w,x,M,S,G,T in string");
9065 x86_64_section_word (char *str
, size_t len
)
9067 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
9068 return SHF_X86_64_LARGE
;
9074 handle_large_common (int small ATTRIBUTE_UNUSED
)
9076 if (flag_code
!= CODE_64BIT
)
9078 s_comm_internal (0, elf_common_parse
);
9079 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
9083 static segT lbss_section
;
9084 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
9085 asection
*saved_bss_section
= bss_section
;
9087 if (lbss_section
== NULL
)
9089 flagword applicable
;
9091 subsegT subseg
= now_subseg
;
9093 /* The .lbss section is for local .largecomm symbols. */
9094 lbss_section
= subseg_new (".lbss", 0);
9095 applicable
= bfd_applicable_section_flags (stdoutput
);
9096 bfd_set_section_flags (stdoutput
, lbss_section
,
9097 applicable
& SEC_ALLOC
);
9098 seg_info (lbss_section
)->bss
= 1;
9100 subseg_set (seg
, subseg
);
9103 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
9104 bss_section
= lbss_section
;
9106 s_comm_internal (0, elf_common_parse
);
9108 elf_com_section_ptr
= saved_com_section_ptr
;
9109 bss_section
= saved_bss_section
;
9112 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */