1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void set_code_flag (int);
139 static void set_16bit_gcc_code_flag (int);
140 static void set_intel_syntax (int);
141 static void set_intel_mnemonic (int);
142 static void set_allow_index_reg (int);
143 static void set_sse_check (int);
144 static void set_cpu_arch (int);
146 static void pe_directive_secrel (int);
148 static void signed_cons (int);
149 static char *output_invalid (int c
);
150 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
152 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
154 static int i386_att_operand (char *);
155 static int i386_intel_operand (char *, int);
156 static int i386_intel_simplify (expressionS
*);
157 static int i386_intel_parse_name (const char *, expressionS
*);
158 static const reg_entry
*parse_register (char *, char **);
159 static char *parse_insn (char *, char *);
160 static char *parse_operands (char *, const char *);
161 static void swap_operands (void);
162 static void swap_2_operands (int, int);
163 static void optimize_imm (void);
164 static void optimize_disp (void);
165 static const insn_template
*match_template (void);
166 static int check_string (void);
167 static int process_suffix (void);
168 static int check_byte_reg (void);
169 static int check_long_reg (void);
170 static int check_qword_reg (void);
171 static int check_word_reg (void);
172 static int finalize_imm (void);
173 static int process_operands (void);
174 static const seg_entry
*build_modrm_byte (void);
175 static void output_insn (void);
176 static void output_imm (fragS
*, offsetT
);
177 static void output_disp (fragS
*, offsetT
);
179 static void s_bss (int);
181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
185 static const char *default_arch
= DEFAULT_ARCH
;
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes
[3];
193 /* Destination or source register specifier. */
194 const reg_entry
*register_specifier
;
197 /* 'md_assemble ()' gathers together information and puts it into a
204 const reg_entry
*regs
;
209 /* TM holds the template for the insn were currently assembling. */
212 /* SUFFIX holds the instruction size suffix for byte, word, dword
213 or qword, if given. */
216 /* OPERANDS gives the number of given operands. */
217 unsigned int operands
;
219 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
220 of given register, displacement, memory operands and immediate
222 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
224 /* TYPES [i] is the type (see above #defines) which tells us how to
225 use OP[i] for the corresponding operand. */
226 i386_operand_type types
[MAX_OPERANDS
];
228 /* Displacement expression, immediate expression, or register for each
230 union i386_op op
[MAX_OPERANDS
];
232 /* Flags for operands. */
233 unsigned int flags
[MAX_OPERANDS
];
234 #define Operand_PCrel 1
236 /* Relocation type for operand */
237 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
239 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
240 the base index byte below. */
241 const reg_entry
*base_reg
;
242 const reg_entry
*index_reg
;
243 unsigned int log2_scale_factor
;
245 /* SEG gives the seg_entries of this insn. They are zero unless
246 explicit segment overrides are given. */
247 const seg_entry
*seg
[2];
249 /* PREFIX holds all the given prefix opcodes (usually null).
250 PREFIXES is the number of prefix opcodes. */
251 unsigned int prefixes
;
252 unsigned char prefix
[MAX_PREFIXES
];
254 /* RM and SIB are the modrm byte and the sib byte where the
255 addressing modes of this insn are encoded. */
261 /* Swap operand in encoding. */
262 unsigned int swap_operand
;
268 typedef struct _i386_insn i386_insn
;
270 /* List of chars besides those in app.c:symbol_chars that can start an
271 operand. Used to prevent the scrubber eating vital white-space. */
272 const char extra_symbol_chars
[] = "*%-(["
281 #if (defined (TE_I386AIX) \
282 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
283 && !defined (TE_GNU) \
284 && !defined (TE_LINUX) \
285 && !defined (TE_NETWARE) \
286 && !defined (TE_FreeBSD) \
287 && !defined (TE_NetBSD)))
288 /* This array holds the chars that always start a comment. If the
289 pre-processor is disabled, these aren't very useful. The option
290 --divide will remove '/' from this list. */
291 const char *i386_comment_chars
= "#/";
292 #define SVR4_COMMENT_CHARS 1
293 #define PREFIX_SEPARATOR '\\'
296 const char *i386_comment_chars
= "#";
297 #define PREFIX_SEPARATOR '/'
300 /* This array holds the chars that only start a comment at the beginning of
301 a line. If the line seems to have the form '# 123 filename'
302 .line and .file directives will appear in the pre-processed output.
303 Note that input_file.c hand checks for '#' at the beginning of the
304 first line of the input file. This is because the compiler outputs
305 #NO_APP at the beginning of its output.
306 Also note that comments started like this one will always work if
307 '/' isn't otherwise defined. */
308 const char line_comment_chars
[] = "#/";
310 const char line_separator_chars
[] = ";";
312 /* Chars that can be used to separate mant from exp in floating point
314 const char EXP_CHARS
[] = "eE";
316 /* Chars that mean this number is a floating point constant
319 const char FLT_CHARS
[] = "fFdDxX";
321 /* Tables for lexical analysis. */
322 static char mnemonic_chars
[256];
323 static char register_chars
[256];
324 static char operand_chars
[256];
325 static char identifier_chars
[256];
326 static char digit_chars
[256];
328 /* Lexical macros. */
329 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
330 #define is_operand_char(x) (operand_chars[(unsigned char) x])
331 #define is_register_char(x) (register_chars[(unsigned char) x])
332 #define is_space_char(x) ((x) == ' ')
333 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
334 #define is_digit_char(x) (digit_chars[(unsigned char) x])
336 /* All non-digit non-letter characters that may occur in an operand. */
337 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
339 /* md_assemble() always leaves the strings it's passed unaltered. To
340 effect this we maintain a stack of saved characters that we've smashed
341 with '\0's (indicating end of strings for various sub-fields of the
342 assembler instruction). */
343 static char save_stack
[32];
344 static char *save_stack_p
;
345 #define END_STRING_AND_SAVE(s) \
346 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
347 #define RESTORE_END_STRING(s) \
348 do { *(s) = *--save_stack_p; } while (0)
350 /* The instruction we're assembling. */
353 /* Possible templates for current insn. */
354 static const templates
*current_templates
;
356 /* Per instruction expressionS buffers: max displacements & immediates. */
357 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
358 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
360 /* Current operand we are working on. */
361 static int this_operand
= -1;
363 /* We support four different modes. FLAG_CODE variable is used to distinguish
371 static enum flag_code flag_code
;
372 static unsigned int object_64bit
;
373 static int use_rela_relocations
= 0;
375 /* The names used to print error messages. */
376 static const char *flag_code_names
[] =
383 /* 1 for intel syntax,
385 static int intel_syntax
= 0;
387 /* 1 for intel mnemonic,
388 0 if att mnemonic. */
389 static int intel_mnemonic
= !SYSV386_COMPAT
;
391 /* 1 if support old (<= 2.8.1) versions of gcc. */
392 static int old_gcc
= OLDGCC_COMPAT
;
394 /* 1 if pseudo registers are permitted. */
395 static int allow_pseudo_reg
= 0;
397 /* 1 if register prefix % not required. */
398 static int allow_naked_reg
= 0;
400 /* 1 if pseudo index register, eiz/riz, is allowed . */
401 static int allow_index_reg
= 0;
411 /* Register prefix used for error message. */
412 static const char *register_prefix
= "%";
414 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
415 leave, push, and pop instructions so that gcc has the same stack
416 frame as in 32 bit mode. */
417 static char stackop_size
= '\0';
419 /* Non-zero to optimize code alignment. */
420 int optimize_align_code
= 1;
422 /* Non-zero to quieten some warnings. */
423 static int quiet_warnings
= 0;
426 static const char *cpu_arch_name
= NULL
;
427 static char *cpu_sub_arch_name
= NULL
;
429 /* CPU feature flags. */
430 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
432 /* If we have selected a cpu we are generating instructions for. */
433 static int cpu_arch_tune_set
= 0;
435 /* Cpu we are generating instructions for. */
436 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of cpu we are generating instructions for. */
439 static i386_cpu_flags cpu_arch_tune_flags
;
441 /* CPU instruction set architecture used. */
442 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
444 /* CPU feature flags of instruction set architecture used. */
445 i386_cpu_flags cpu_arch_isa_flags
;
447 /* If set, conditional jumps are not automatically promoted to handle
448 larger than a byte offset. */
449 static unsigned int no_cond_jump_promotion
= 0;
451 /* Encode SSE instructions with VEX prefix. */
452 static unsigned int sse2avx
;
454 /* Encode scalar AVX instructions with specific vector length. */
461 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
462 static symbolS
*GOT_symbol
;
464 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
465 unsigned int x86_dwarf2_return_column
;
467 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
468 int x86_cie_data_alignment
;
470 /* Interface to relax_segment.
471 There are 3 major relax states for 386 jump insns because the
472 different types of jumps add different sizes to frags when we're
473 figuring out what sort of jump to choose to reach a given label. */
476 #define UNCOND_JUMP 0
478 #define COND_JUMP86 2
483 #define SMALL16 (SMALL | CODE16)
485 #define BIG16 (BIG | CODE16)
489 #define INLINE __inline__
495 #define ENCODE_RELAX_STATE(type, size) \
496 ((relax_substateT) (((type) << 2) | (size)))
497 #define TYPE_FROM_RELAX_STATE(s) \
499 #define DISP_SIZE_FROM_RELAX_STATE(s) \
500 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
502 /* This table is used by relax_frag to promote short jumps to long
503 ones where necessary. SMALL (short) jumps may be promoted to BIG
504 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
505 don't allow a short jump in a 32 bit code segment to be promoted to
506 a 16 bit offset jump because it's slower (requires data size
507 prefix), and doesn't work, unless the destination is in the bottom
508 64k of the code segment (The top 16 bits of eip are zeroed). */
510 const relax_typeS md_relax_table
[] =
513 1) most positive reach of this state,
514 2) most negative reach of this state,
515 3) how many bytes this mode will have in the variable part of the frag
516 4) which index into the table to try if we can't fit into this one. */
518 /* UNCOND_JUMP states. */
519 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
520 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
521 /* dword jmp adds 4 bytes to frag:
522 0 extra opcode bytes, 4 displacement bytes. */
524 /* word jmp adds 2 byte2 to frag:
525 0 extra opcode bytes, 2 displacement bytes. */
528 /* COND_JUMP states. */
529 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
530 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
531 /* dword conditionals adds 5 bytes to frag:
532 1 extra opcode byte, 4 displacement bytes. */
534 /* word conditionals add 3 bytes to frag:
535 1 extra opcode byte, 2 displacement bytes. */
538 /* COND_JUMP86 states. */
539 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
540 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
541 /* dword conditionals adds 5 bytes to frag:
542 1 extra opcode byte, 4 displacement bytes. */
544 /* word conditionals add 4 bytes to frag:
545 1 displacement byte and a 3 byte long branch insn. */
549 static const arch_entry cpu_arch
[] =
551 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
552 CPU_GENERIC32_FLAGS
, 0 },
553 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
554 CPU_GENERIC64_FLAGS
, 0 },
555 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
557 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
559 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
561 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
563 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
565 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
567 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
569 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
571 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
573 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
575 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
577 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
579 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
581 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
582 CPU_NOCONA_FLAGS
, 0 },
583 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
585 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
587 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
588 CPU_CORE2_FLAGS
, 1 },
589 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
590 CPU_CORE2_FLAGS
, 0 },
591 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
592 CPU_COREI7_FLAGS
, 0 },
593 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
595 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
597 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
599 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
600 CPU_ATHLON_FLAGS
, 0 },
601 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
603 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
605 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
607 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
608 CPU_AMDFAM10_FLAGS
, 0 },
609 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
610 CPU_BDVER1_FLAGS
, 0 },
611 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
613 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
615 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
617 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
618 CPU_ANY87_FLAGS
, 0 },
619 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
621 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
622 CPU_3DNOWA_FLAGS
, 0 },
623 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
625 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
627 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
629 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
630 CPU_SSSE3_FLAGS
, 0 },
631 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
632 CPU_SSE4_1_FLAGS
, 0 },
633 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
634 CPU_SSE4_2_FLAGS
, 0 },
635 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
636 CPU_SSE4_2_FLAGS
, 0 },
637 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
638 CPU_ANY_SSE_FLAGS
, 0 },
639 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
641 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
642 CPU_ANY_AVX_FLAGS
, 0 },
643 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
645 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
647 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
648 CPU_XSAVE_FLAGS
, 0 },
649 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
651 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
652 CPU_PCLMUL_FLAGS
, 0 },
653 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
654 CPU_PCLMUL_FLAGS
, 1 },
655 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
657 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
659 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
661 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
663 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
664 CPU_MOVBE_FLAGS
, 0 },
665 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
667 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
668 CPU_CLFLUSH_FLAGS
, 0 },
669 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
670 CPU_SYSCALL_FLAGS
, 0 },
671 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
672 CPU_RDTSCP_FLAGS
, 0 },
673 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
674 CPU_3DNOW_FLAGS
, 0 },
675 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
676 CPU_3DNOWA_FLAGS
, 0 },
677 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
678 CPU_PADLOCK_FLAGS
, 0 },
679 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
681 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
683 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
684 CPU_SSE4A_FLAGS
, 0 },
685 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
690 /* Like s_lcomm_internal in gas/read.c but the alignment string
691 is allowed to be optional. */
694 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
701 && *input_line_pointer
== ',')
703 align
= parse_align (needs_align
- 1);
705 if (align
== (addressT
) -1)
720 bss_alloc (symbolP
, size
, align
);
725 pe_lcomm (int needs_align
)
727 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
731 const pseudo_typeS md_pseudo_table
[] =
733 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
734 {"align", s_align_bytes
, 0},
736 {"align", s_align_ptwo
, 0},
738 {"arch", set_cpu_arch
, 0},
742 {"lcomm", pe_lcomm
, 1},
744 {"ffloat", float_cons
, 'f'},
745 {"dfloat", float_cons
, 'd'},
746 {"tfloat", float_cons
, 'x'},
748 {"slong", signed_cons
, 4},
749 {"noopt", s_ignore
, 0},
750 {"optim", s_ignore
, 0},
751 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
752 {"code16", set_code_flag
, CODE_16BIT
},
753 {"code32", set_code_flag
, CODE_32BIT
},
754 {"code64", set_code_flag
, CODE_64BIT
},
755 {"intel_syntax", set_intel_syntax
, 1},
756 {"att_syntax", set_intel_syntax
, 0},
757 {"intel_mnemonic", set_intel_mnemonic
, 1},
758 {"att_mnemonic", set_intel_mnemonic
, 0},
759 {"allow_index_reg", set_allow_index_reg
, 1},
760 {"disallow_index_reg", set_allow_index_reg
, 0},
761 {"sse_check", set_sse_check
, 0},
762 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
763 {"largecomm", handle_large_common
, 0},
765 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
766 {"loc", dwarf2_directive_loc
, 0},
767 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
770 {"secrel32", pe_directive_secrel
, 0},
775 /* For interface with expression (). */
776 extern char *input_line_pointer
;
778 /* Hash table for instruction mnemonic lookup. */
779 static struct hash_control
*op_hash
;
781 /* Hash table for register lookup. */
782 static struct hash_control
*reg_hash
;
785 i386_align_code (fragS
*fragP
, int count
)
787 /* Various efficient no-op patterns for aligning code labels.
788 Note: Don't try to assemble the instructions in the comments.
789 0L and 0w are not legal. */
790 static const char f32_1
[] =
792 static const char f32_2
[] =
793 {0x66,0x90}; /* xchg %ax,%ax */
794 static const char f32_3
[] =
795 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
796 static const char f32_4
[] =
797 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
798 static const char f32_5
[] =
800 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
801 static const char f32_6
[] =
802 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
803 static const char f32_7
[] =
804 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
805 static const char f32_8
[] =
807 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
808 static const char f32_9
[] =
809 {0x89,0xf6, /* movl %esi,%esi */
810 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
811 static const char f32_10
[] =
812 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
813 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
814 static const char f32_11
[] =
815 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
816 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
817 static const char f32_12
[] =
818 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
819 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
820 static const char f32_13
[] =
821 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
822 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
823 static const char f32_14
[] =
824 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
825 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
826 static const char f16_3
[] =
827 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
828 static const char f16_4
[] =
829 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
830 static const char f16_5
[] =
832 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
833 static const char f16_6
[] =
834 {0x89,0xf6, /* mov %si,%si */
835 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
836 static const char f16_7
[] =
837 {0x8d,0x74,0x00, /* lea 0(%si),%si */
838 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
839 static const char f16_8
[] =
840 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
841 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
842 static const char jump_31
[] =
843 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
844 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
845 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
846 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
847 static const char *const f32_patt
[] = {
848 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
849 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
851 static const char *const f16_patt
[] = {
852 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
855 static const char alt_3
[] =
857 /* nopl 0(%[re]ax) */
858 static const char alt_4
[] =
859 {0x0f,0x1f,0x40,0x00};
860 /* nopl 0(%[re]ax,%[re]ax,1) */
861 static const char alt_5
[] =
862 {0x0f,0x1f,0x44,0x00,0x00};
863 /* nopw 0(%[re]ax,%[re]ax,1) */
864 static const char alt_6
[] =
865 {0x66,0x0f,0x1f,0x44,0x00,0x00};
866 /* nopl 0L(%[re]ax) */
867 static const char alt_7
[] =
868 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
869 /* nopl 0L(%[re]ax,%[re]ax,1) */
870 static const char alt_8
[] =
871 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
872 /* nopw 0L(%[re]ax,%[re]ax,1) */
873 static const char alt_9
[] =
874 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
875 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
876 static const char alt_10
[] =
877 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
879 nopw %cs:0L(%[re]ax,%[re]ax,1) */
880 static const char alt_long_11
[] =
882 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
885 nopw %cs:0L(%[re]ax,%[re]ax,1) */
886 static const char alt_long_12
[] =
889 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
893 nopw %cs:0L(%[re]ax,%[re]ax,1) */
894 static const char alt_long_13
[] =
898 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
903 nopw %cs:0L(%[re]ax,%[re]ax,1) */
904 static const char alt_long_14
[] =
909 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
915 nopw %cs:0L(%[re]ax,%[re]ax,1) */
916 static const char alt_long_15
[] =
922 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
923 /* nopl 0(%[re]ax,%[re]ax,1)
924 nopw 0(%[re]ax,%[re]ax,1) */
925 static const char alt_short_11
[] =
926 {0x0f,0x1f,0x44,0x00,0x00,
927 0x66,0x0f,0x1f,0x44,0x00,0x00};
928 /* nopw 0(%[re]ax,%[re]ax,1)
929 nopw 0(%[re]ax,%[re]ax,1) */
930 static const char alt_short_12
[] =
931 {0x66,0x0f,0x1f,0x44,0x00,0x00,
932 0x66,0x0f,0x1f,0x44,0x00,0x00};
933 /* nopw 0(%[re]ax,%[re]ax,1)
935 static const char alt_short_13
[] =
936 {0x66,0x0f,0x1f,0x44,0x00,0x00,
937 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
940 static const char alt_short_14
[] =
941 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
942 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
944 nopl 0L(%[re]ax,%[re]ax,1) */
945 static const char alt_short_15
[] =
946 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
947 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
948 static const char *const alt_short_patt
[] = {
949 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
950 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
951 alt_short_14
, alt_short_15
953 static const char *const alt_long_patt
[] = {
954 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
955 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
956 alt_long_14
, alt_long_15
959 /* Only align for at least a positive non-zero boundary. */
960 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
963 /* We need to decide which NOP sequence to use for 32bit and
964 64bit. When -mtune= is used:
966 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
967 PROCESSOR_GENERIC32, f32_patt will be used.
968 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
969 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
970 PROCESSOR_GENERIC64, alt_long_patt will be used.
971 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
972 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
975 When -mtune= isn't used, alt_long_patt will be used if
976 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
979 When -march= or .arch is used, we can't use anything beyond
980 cpu_arch_isa_flags. */
982 if (flag_code
== CODE_16BIT
)
986 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
988 /* Adjust jump offset. */
989 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
992 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
993 f16_patt
[count
- 1], count
);
997 const char *const *patt
= NULL
;
999 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1001 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1002 switch (cpu_arch_tune
)
1004 case PROCESSOR_UNKNOWN
:
1005 /* We use cpu_arch_isa_flags to check if we SHOULD
1006 optimize for Cpu686. */
1007 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1008 patt
= alt_long_patt
;
1012 case PROCESSOR_PENTIUMPRO
:
1013 case PROCESSOR_PENTIUM4
:
1014 case PROCESSOR_NOCONA
:
1015 case PROCESSOR_CORE
:
1016 case PROCESSOR_CORE2
:
1017 case PROCESSOR_COREI7
:
1018 case PROCESSOR_L1OM
:
1019 case PROCESSOR_GENERIC64
:
1020 patt
= alt_long_patt
;
1023 case PROCESSOR_ATHLON
:
1025 case PROCESSOR_AMDFAM10
:
1026 case PROCESSOR_BDVER1
:
1027 patt
= alt_short_patt
;
1029 case PROCESSOR_I386
:
1030 case PROCESSOR_I486
:
1031 case PROCESSOR_PENTIUM
:
1032 case PROCESSOR_GENERIC32
:
1039 switch (fragP
->tc_frag_data
.tune
)
1041 case PROCESSOR_UNKNOWN
:
1042 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1043 PROCESSOR_UNKNOWN. */
1047 case PROCESSOR_I386
:
1048 case PROCESSOR_I486
:
1049 case PROCESSOR_PENTIUM
:
1051 case PROCESSOR_ATHLON
:
1053 case PROCESSOR_AMDFAM10
:
1054 case PROCESSOR_BDVER1
:
1055 case PROCESSOR_GENERIC32
:
1056 /* We use cpu_arch_isa_flags to check if we CAN optimize
1058 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1059 patt
= alt_short_patt
;
1063 case PROCESSOR_PENTIUMPRO
:
1064 case PROCESSOR_PENTIUM4
:
1065 case PROCESSOR_NOCONA
:
1066 case PROCESSOR_CORE
:
1067 case PROCESSOR_CORE2
:
1068 case PROCESSOR_COREI7
:
1069 case PROCESSOR_L1OM
:
1070 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1071 patt
= alt_long_patt
;
1075 case PROCESSOR_GENERIC64
:
1076 patt
= alt_long_patt
;
1081 if (patt
== f32_patt
)
1083 /* If the padding is less than 15 bytes, we use the normal
1084 ones. Otherwise, we use a jump instruction and adjust
1088 /* For 64bit, the limit is 3 bytes. */
1089 if (flag_code
== CODE_64BIT
1090 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1095 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1096 patt
[count
- 1], count
);
1099 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1101 /* Adjust jump offset. */
1102 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1107 /* Maximum length of an instruction is 15 byte. If the
1108 padding is greater than 15 bytes and we don't use jump,
1109 we have to break it into smaller pieces. */
1110 int padding
= count
;
1111 while (padding
> 15)
1114 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1119 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1120 patt
[padding
- 1], padding
);
1123 fragP
->fr_var
= count
;
1127 operand_type_all_zero (const union i386_operand_type
*x
)
1129 switch (ARRAY_SIZE(x
->array
))
1138 return !x
->array
[0];
1145 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1147 switch (ARRAY_SIZE(x
->array
))
1162 operand_type_equal (const union i386_operand_type
*x
,
1163 const union i386_operand_type
*y
)
1165 switch (ARRAY_SIZE(x
->array
))
1168 if (x
->array
[2] != y
->array
[2])
1171 if (x
->array
[1] != y
->array
[1])
1174 return x
->array
[0] == y
->array
[0];
1182 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1184 switch (ARRAY_SIZE(x
->array
))
1193 return !x
->array
[0];
1200 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1202 switch (ARRAY_SIZE(x
->array
))
1217 cpu_flags_equal (const union i386_cpu_flags
*x
,
1218 const union i386_cpu_flags
*y
)
1220 switch (ARRAY_SIZE(x
->array
))
1223 if (x
->array
[2] != y
->array
[2])
1226 if (x
->array
[1] != y
->array
[1])
1229 return x
->array
[0] == y
->array
[0];
1237 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1239 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1240 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1243 static INLINE i386_cpu_flags
1244 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1246 switch (ARRAY_SIZE (x
.array
))
1249 x
.array
[2] &= y
.array
[2];
1251 x
.array
[1] &= y
.array
[1];
1253 x
.array
[0] &= y
.array
[0];
1261 static INLINE i386_cpu_flags
1262 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1264 switch (ARRAY_SIZE (x
.array
))
1267 x
.array
[2] |= y
.array
[2];
1269 x
.array
[1] |= y
.array
[1];
1271 x
.array
[0] |= y
.array
[0];
1279 static INLINE i386_cpu_flags
1280 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1282 switch (ARRAY_SIZE (x
.array
))
1285 x
.array
[2] &= ~y
.array
[2];
1287 x
.array
[1] &= ~y
.array
[1];
1289 x
.array
[0] &= ~y
.array
[0];
1297 #define CPU_FLAGS_ARCH_MATCH 0x1
1298 #define CPU_FLAGS_64BIT_MATCH 0x2
1299 #define CPU_FLAGS_AES_MATCH 0x4
1300 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1301 #define CPU_FLAGS_AVX_MATCH 0x10
1303 #define CPU_FLAGS_32BIT_MATCH \
1304 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1305 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1306 #define CPU_FLAGS_PERFECT_MATCH \
1307 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1309 /* Return CPU flags match bits. */
1312 cpu_flags_match (const insn_template
*t
)
1314 i386_cpu_flags x
= t
->cpu_flags
;
1315 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1317 x
.bitfield
.cpu64
= 0;
1318 x
.bitfield
.cpuno64
= 0;
1320 if (cpu_flags_all_zero (&x
))
1322 /* This instruction is available on all archs. */
1323 match
|= CPU_FLAGS_32BIT_MATCH
;
1327 /* This instruction is available only on some archs. */
1328 i386_cpu_flags cpu
= cpu_arch_flags
;
1330 cpu
.bitfield
.cpu64
= 0;
1331 cpu
.bitfield
.cpuno64
= 0;
1332 cpu
= cpu_flags_and (x
, cpu
);
1333 if (!cpu_flags_all_zero (&cpu
))
1335 if (x
.bitfield
.cpuavx
)
1337 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1338 if (cpu
.bitfield
.cpuavx
)
1340 /* Check SSE2AVX. */
1341 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1343 match
|= (CPU_FLAGS_ARCH_MATCH
1344 | CPU_FLAGS_AVX_MATCH
);
1346 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1347 match
|= CPU_FLAGS_AES_MATCH
;
1349 if (!x
.bitfield
.cpupclmul
1350 || cpu
.bitfield
.cpupclmul
)
1351 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1355 match
|= CPU_FLAGS_ARCH_MATCH
;
1358 match
|= CPU_FLAGS_32BIT_MATCH
;
1364 static INLINE i386_operand_type
1365 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1367 switch (ARRAY_SIZE (x
.array
))
1370 x
.array
[2] &= y
.array
[2];
1372 x
.array
[1] &= y
.array
[1];
1374 x
.array
[0] &= y
.array
[0];
1382 static INLINE i386_operand_type
1383 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1385 switch (ARRAY_SIZE (x
.array
))
1388 x
.array
[2] |= y
.array
[2];
1390 x
.array
[1] |= y
.array
[1];
1392 x
.array
[0] |= y
.array
[0];
1400 static INLINE i386_operand_type
1401 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1403 switch (ARRAY_SIZE (x
.array
))
1406 x
.array
[2] ^= y
.array
[2];
1408 x
.array
[1] ^= y
.array
[1];
1410 x
.array
[0] ^= y
.array
[0];
1418 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1419 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1420 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1421 static const i386_operand_type inoutportreg
1422 = OPERAND_TYPE_INOUTPORTREG
;
1423 static const i386_operand_type reg16_inoutportreg
1424 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1425 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1426 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1427 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1428 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1429 static const i386_operand_type anydisp
1430 = OPERAND_TYPE_ANYDISP
;
1431 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1432 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1433 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1434 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1435 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1436 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1437 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1438 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1439 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1440 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1441 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1442 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1453 operand_type_check (i386_operand_type t
, enum operand_type c
)
1458 return (t
.bitfield
.reg8
1461 || t
.bitfield
.reg64
);
1464 return (t
.bitfield
.imm8
1468 || t
.bitfield
.imm32s
1469 || t
.bitfield
.imm64
);
1472 return (t
.bitfield
.disp8
1473 || t
.bitfield
.disp16
1474 || t
.bitfield
.disp32
1475 || t
.bitfield
.disp32s
1476 || t
.bitfield
.disp64
);
1479 return (t
.bitfield
.disp8
1480 || t
.bitfield
.disp16
1481 || t
.bitfield
.disp32
1482 || t
.bitfield
.disp32s
1483 || t
.bitfield
.disp64
1484 || t
.bitfield
.baseindex
);
1493 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1494 operand J for instruction template T. */
1497 match_reg_size (const insn_template
*t
, unsigned int j
)
1499 return !((i
.types
[j
].bitfield
.byte
1500 && !t
->operand_types
[j
].bitfield
.byte
)
1501 || (i
.types
[j
].bitfield
.word
1502 && !t
->operand_types
[j
].bitfield
.word
)
1503 || (i
.types
[j
].bitfield
.dword
1504 && !t
->operand_types
[j
].bitfield
.dword
)
1505 || (i
.types
[j
].bitfield
.qword
1506 && !t
->operand_types
[j
].bitfield
.qword
));
1509 /* Return 1 if there is no conflict in any size on operand J for
1510 instruction template T. */
1513 match_mem_size (const insn_template
*t
, unsigned int j
)
1515 return (match_reg_size (t
, j
)
1516 && !((i
.types
[j
].bitfield
.unspecified
1517 && !t
->operand_types
[j
].bitfield
.unspecified
)
1518 || (i
.types
[j
].bitfield
.fword
1519 && !t
->operand_types
[j
].bitfield
.fword
)
1520 || (i
.types
[j
].bitfield
.tbyte
1521 && !t
->operand_types
[j
].bitfield
.tbyte
)
1522 || (i
.types
[j
].bitfield
.xmmword
1523 && !t
->operand_types
[j
].bitfield
.xmmword
)
1524 || (i
.types
[j
].bitfield
.ymmword
1525 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1528 /* Return 1 if there is no size conflict on any operands for
1529 instruction template T. */
1532 operand_size_match (const insn_template
*t
)
1537 /* Don't check jump instructions. */
1538 if (t
->opcode_modifier
.jump
1539 || t
->opcode_modifier
.jumpbyte
1540 || t
->opcode_modifier
.jumpdword
1541 || t
->opcode_modifier
.jumpintersegment
)
1544 /* Check memory and accumulator operand size. */
1545 for (j
= 0; j
< i
.operands
; j
++)
1547 if (t
->operand_types
[j
].bitfield
.anysize
)
1550 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1556 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1565 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1568 i
.err_msg
= _("operand size mismatch");
1572 /* Check reverse. */
1573 gas_assert (i
.operands
== 2);
1576 for (j
= 0; j
< 2; j
++)
1578 if (t
->operand_types
[j
].bitfield
.acc
1579 && !match_reg_size (t
, j
? 0 : 1))
1582 if (i
.types
[j
].bitfield
.mem
1583 && !match_mem_size (t
, j
? 0 : 1))
1591 operand_type_match (i386_operand_type overlap
,
1592 i386_operand_type given
)
1594 i386_operand_type temp
= overlap
;
1596 temp
.bitfield
.jumpabsolute
= 0;
1597 temp
.bitfield
.unspecified
= 0;
1598 temp
.bitfield
.byte
= 0;
1599 temp
.bitfield
.word
= 0;
1600 temp
.bitfield
.dword
= 0;
1601 temp
.bitfield
.fword
= 0;
1602 temp
.bitfield
.qword
= 0;
1603 temp
.bitfield
.tbyte
= 0;
1604 temp
.bitfield
.xmmword
= 0;
1605 temp
.bitfield
.ymmword
= 0;
1606 if (operand_type_all_zero (&temp
))
1609 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1610 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1614 i
.err_msg
= _("operand type mismatch");
1618 /* If given types g0 and g1 are registers they must be of the same type
1619 unless the expected operand type register overlap is null.
1620 Note that Acc in a template matches every size of reg. */
1623 operand_type_register_match (i386_operand_type m0
,
1624 i386_operand_type g0
,
1625 i386_operand_type t0
,
1626 i386_operand_type m1
,
1627 i386_operand_type g1
,
1628 i386_operand_type t1
)
1630 if (!operand_type_check (g0
, reg
))
1633 if (!operand_type_check (g1
, reg
))
1636 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1637 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1638 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1639 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1642 if (m0
.bitfield
.acc
)
1644 t0
.bitfield
.reg8
= 1;
1645 t0
.bitfield
.reg16
= 1;
1646 t0
.bitfield
.reg32
= 1;
1647 t0
.bitfield
.reg64
= 1;
1650 if (m1
.bitfield
.acc
)
1652 t1
.bitfield
.reg8
= 1;
1653 t1
.bitfield
.reg16
= 1;
1654 t1
.bitfield
.reg32
= 1;
1655 t1
.bitfield
.reg64
= 1;
1658 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1659 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1660 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1661 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1664 i
.err_msg
= _("register type mismatch");
1669 static INLINE
unsigned int
1670 mode_from_disp_size (i386_operand_type t
)
1672 if (t
.bitfield
.disp8
)
1674 else if (t
.bitfield
.disp16
1675 || t
.bitfield
.disp32
1676 || t
.bitfield
.disp32s
)
1683 fits_in_signed_byte (offsetT num
)
1685 return (num
>= -128) && (num
<= 127);
1689 fits_in_unsigned_byte (offsetT num
)
1691 return (num
& 0xff) == num
;
1695 fits_in_unsigned_word (offsetT num
)
1697 return (num
& 0xffff) == num
;
1701 fits_in_signed_word (offsetT num
)
1703 return (-32768 <= num
) && (num
<= 32767);
1707 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1712 return (!(((offsetT
) -1 << 31) & num
)
1713 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1715 } /* fits_in_signed_long() */
1718 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1723 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1725 } /* fits_in_unsigned_long() */
1728 fits_in_imm4 (offsetT num
)
1730 return (num
& 0xf) == num
;
1733 static i386_operand_type
1734 smallest_imm_type (offsetT num
)
1736 i386_operand_type t
;
1738 operand_type_set (&t
, 0);
1739 t
.bitfield
.imm64
= 1;
1741 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1743 /* This code is disabled on the 486 because all the Imm1 forms
1744 in the opcode table are slower on the i486. They're the
1745 versions with the implicitly specified single-position
1746 displacement, which has another syntax if you really want to
1748 t
.bitfield
.imm1
= 1;
1749 t
.bitfield
.imm8
= 1;
1750 t
.bitfield
.imm8s
= 1;
1751 t
.bitfield
.imm16
= 1;
1752 t
.bitfield
.imm32
= 1;
1753 t
.bitfield
.imm32s
= 1;
1755 else if (fits_in_signed_byte (num
))
1757 t
.bitfield
.imm8
= 1;
1758 t
.bitfield
.imm8s
= 1;
1759 t
.bitfield
.imm16
= 1;
1760 t
.bitfield
.imm32
= 1;
1761 t
.bitfield
.imm32s
= 1;
1763 else if (fits_in_unsigned_byte (num
))
1765 t
.bitfield
.imm8
= 1;
1766 t
.bitfield
.imm16
= 1;
1767 t
.bitfield
.imm32
= 1;
1768 t
.bitfield
.imm32s
= 1;
1770 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1772 t
.bitfield
.imm16
= 1;
1773 t
.bitfield
.imm32
= 1;
1774 t
.bitfield
.imm32s
= 1;
1776 else if (fits_in_signed_long (num
))
1778 t
.bitfield
.imm32
= 1;
1779 t
.bitfield
.imm32s
= 1;
1781 else if (fits_in_unsigned_long (num
))
1782 t
.bitfield
.imm32
= 1;
1788 offset_in_range (offsetT val
, int size
)
1794 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1795 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1796 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1798 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1804 /* If BFD64, sign extend val for 32bit address mode. */
1805 if (flag_code
!= CODE_64BIT
1806 || i
.prefix
[ADDR_PREFIX
])
1807 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1808 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1811 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1813 char buf1
[40], buf2
[40];
1815 sprint_value (buf1
, val
);
1816 sprint_value (buf2
, val
& mask
);
1817 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1831 a. PREFIX_EXIST if attempting to add a prefix where one from the
1832 same class already exists.
1833 b. PREFIX_LOCK if lock prefix is added.
1834 c. PREFIX_REP if rep/repne prefix is added.
1835 d. PREFIX_OTHER if other prefix is added.
1838 static enum PREFIX_GROUP
1839 add_prefix (unsigned int prefix
)
1841 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1844 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1845 && flag_code
== CODE_64BIT
)
1847 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1848 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1849 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1860 case CS_PREFIX_OPCODE
:
1861 case DS_PREFIX_OPCODE
:
1862 case ES_PREFIX_OPCODE
:
1863 case FS_PREFIX_OPCODE
:
1864 case GS_PREFIX_OPCODE
:
1865 case SS_PREFIX_OPCODE
:
1869 case REPNE_PREFIX_OPCODE
:
1870 case REPE_PREFIX_OPCODE
:
1875 case LOCK_PREFIX_OPCODE
:
1884 case ADDR_PREFIX_OPCODE
:
1888 case DATA_PREFIX_OPCODE
:
1892 if (i
.prefix
[q
] != 0)
1900 i
.prefix
[q
] |= prefix
;
1903 as_bad (_("same type of prefix used twice"));
1909 set_code_flag (int value
)
1911 flag_code
= (enum flag_code
) value
;
1912 if (flag_code
== CODE_64BIT
)
1914 cpu_arch_flags
.bitfield
.cpu64
= 1;
1915 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1919 cpu_arch_flags
.bitfield
.cpu64
= 0;
1920 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1922 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1924 as_bad (_("64bit mode not supported on this CPU."));
1926 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1928 as_bad (_("32bit mode not supported on this CPU."));
1930 stackop_size
= '\0';
1934 set_16bit_gcc_code_flag (int new_code_flag
)
1936 flag_code
= (enum flag_code
) new_code_flag
;
1937 if (flag_code
!= CODE_16BIT
)
1939 cpu_arch_flags
.bitfield
.cpu64
= 0;
1940 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1941 stackop_size
= LONG_MNEM_SUFFIX
;
1945 set_intel_syntax (int syntax_flag
)
1947 /* Find out if register prefixing is specified. */
1948 int ask_naked_reg
= 0;
1951 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1953 char *string
= input_line_pointer
;
1954 int e
= get_symbol_end ();
1956 if (strcmp (string
, "prefix") == 0)
1958 else if (strcmp (string
, "noprefix") == 0)
1961 as_bad (_("bad argument to syntax directive."));
1962 *input_line_pointer
= e
;
1964 demand_empty_rest_of_line ();
1966 intel_syntax
= syntax_flag
;
1968 if (ask_naked_reg
== 0)
1969 allow_naked_reg
= (intel_syntax
1970 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1972 allow_naked_reg
= (ask_naked_reg
< 0);
1974 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1976 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1977 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1978 register_prefix
= allow_naked_reg
? "" : "%";
1982 set_intel_mnemonic (int mnemonic_flag
)
1984 intel_mnemonic
= mnemonic_flag
;
1988 set_allow_index_reg (int flag
)
1990 allow_index_reg
= flag
;
1994 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1998 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2000 char *string
= input_line_pointer
;
2001 int e
= get_symbol_end ();
2003 if (strcmp (string
, "none") == 0)
2004 sse_check
= sse_check_none
;
2005 else if (strcmp (string
, "warning") == 0)
2006 sse_check
= sse_check_warning
;
2007 else if (strcmp (string
, "error") == 0)
2008 sse_check
= sse_check_error
;
2010 as_bad (_("bad argument to sse_check directive."));
2011 *input_line_pointer
= e
;
2014 as_bad (_("missing argument for sse_check directive"));
2016 demand_empty_rest_of_line ();
2020 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2021 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2023 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2024 static const char *arch
;
2026 /* Intel LIOM is only supported on ELF. */
2032 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2033 use default_arch. */
2034 arch
= cpu_arch_name
;
2036 arch
= default_arch
;
2039 /* If we are targeting Intel L1OM, we must enable it. */
2040 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2041 || new_flag
.bitfield
.cpul1om
)
2044 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2049 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2053 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2055 char *string
= input_line_pointer
;
2056 int e
= get_symbol_end ();
2058 i386_cpu_flags flags
;
2060 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2062 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2064 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2068 cpu_arch_name
= cpu_arch
[j
].name
;
2069 cpu_sub_arch_name
= NULL
;
2070 cpu_arch_flags
= cpu_arch
[j
].flags
;
2071 if (flag_code
== CODE_64BIT
)
2073 cpu_arch_flags
.bitfield
.cpu64
= 1;
2074 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2078 cpu_arch_flags
.bitfield
.cpu64
= 0;
2079 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2081 cpu_arch_isa
= cpu_arch
[j
].type
;
2082 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2083 if (!cpu_arch_tune_set
)
2085 cpu_arch_tune
= cpu_arch_isa
;
2086 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2091 if (strncmp (string
+ 1, "no", 2))
2092 flags
= cpu_flags_or (cpu_arch_flags
,
2095 flags
= cpu_flags_and_not (cpu_arch_flags
,
2097 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2099 if (cpu_sub_arch_name
)
2101 char *name
= cpu_sub_arch_name
;
2102 cpu_sub_arch_name
= concat (name
,
2104 (const char *) NULL
);
2108 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2109 cpu_arch_flags
= flags
;
2111 *input_line_pointer
= e
;
2112 demand_empty_rest_of_line ();
2116 if (j
>= ARRAY_SIZE (cpu_arch
))
2117 as_bad (_("no such architecture: `%s'"), string
);
2119 *input_line_pointer
= e
;
2122 as_bad (_("missing cpu architecture"));
2124 no_cond_jump_promotion
= 0;
2125 if (*input_line_pointer
== ','
2126 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2128 char *string
= ++input_line_pointer
;
2129 int e
= get_symbol_end ();
2131 if (strcmp (string
, "nojumps") == 0)
2132 no_cond_jump_promotion
= 1;
2133 else if (strcmp (string
, "jumps") == 0)
2136 as_bad (_("no such architecture modifier: `%s'"), string
);
2138 *input_line_pointer
= e
;
2141 demand_empty_rest_of_line ();
2144 enum bfd_architecture
2147 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2149 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2150 || flag_code
!= CODE_64BIT
)
2151 as_fatal (_("Intel L1OM is 64bit ELF only"));
2152 return bfd_arch_l1om
;
2155 return bfd_arch_i386
;
2161 if (!strcmp (default_arch
, "x86_64"))
2163 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2165 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2166 as_fatal (_("Intel L1OM is 64bit ELF only"));
2167 return bfd_mach_l1om
;
2170 return bfd_mach_x86_64
;
2172 else if (!strcmp (default_arch
, "i386"))
2173 return bfd_mach_i386_i386
;
2175 as_fatal (_("Unknown architecture"));
2181 const char *hash_err
;
2183 /* Initialize op_hash hash table. */
2184 op_hash
= hash_new ();
2187 const insn_template
*optab
;
2188 templates
*core_optab
;
2190 /* Setup for loop. */
2192 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2193 core_optab
->start
= optab
;
2198 if (optab
->name
== NULL
2199 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2201 /* different name --> ship out current template list;
2202 add to hash table; & begin anew. */
2203 core_optab
->end
= optab
;
2204 hash_err
= hash_insert (op_hash
,
2206 (void *) core_optab
);
2209 as_fatal (_("Internal Error: Can't hash %s: %s"),
2213 if (optab
->name
== NULL
)
2215 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2216 core_optab
->start
= optab
;
2221 /* Initialize reg_hash hash table. */
2222 reg_hash
= hash_new ();
2224 const reg_entry
*regtab
;
2225 unsigned int regtab_size
= i386_regtab_size
;
2227 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2229 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2231 as_fatal (_("Internal Error: Can't hash %s: %s"),
2237 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2242 for (c
= 0; c
< 256; c
++)
2247 mnemonic_chars
[c
] = c
;
2248 register_chars
[c
] = c
;
2249 operand_chars
[c
] = c
;
2251 else if (ISLOWER (c
))
2253 mnemonic_chars
[c
] = c
;
2254 register_chars
[c
] = c
;
2255 operand_chars
[c
] = c
;
2257 else if (ISUPPER (c
))
2259 mnemonic_chars
[c
] = TOLOWER (c
);
2260 register_chars
[c
] = mnemonic_chars
[c
];
2261 operand_chars
[c
] = c
;
2264 if (ISALPHA (c
) || ISDIGIT (c
))
2265 identifier_chars
[c
] = c
;
2268 identifier_chars
[c
] = c
;
2269 operand_chars
[c
] = c
;
2274 identifier_chars
['@'] = '@';
2277 identifier_chars
['?'] = '?';
2278 operand_chars
['?'] = '?';
2280 digit_chars
['-'] = '-';
2281 mnemonic_chars
['_'] = '_';
2282 mnemonic_chars
['-'] = '-';
2283 mnemonic_chars
['.'] = '.';
2284 identifier_chars
['_'] = '_';
2285 identifier_chars
['.'] = '.';
2287 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2288 operand_chars
[(unsigned char) *p
] = *p
;
2291 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2294 record_alignment (text_section
, 2);
2295 record_alignment (data_section
, 2);
2296 record_alignment (bss_section
, 2);
2300 if (flag_code
== CODE_64BIT
)
2302 x86_dwarf2_return_column
= 16;
2303 x86_cie_data_alignment
= -8;
2307 x86_dwarf2_return_column
= 8;
2308 x86_cie_data_alignment
= -4;
2313 i386_print_statistics (FILE *file
)
2315 hash_print_statistics (file
, "i386 opcode", op_hash
);
2316 hash_print_statistics (file
, "i386 register", reg_hash
);
2321 /* Debugging routines for md_assemble. */
2322 static void pte (insn_template
*);
2323 static void pt (i386_operand_type
);
2324 static void pe (expressionS
*);
2325 static void ps (symbolS
*);
2328 pi (char *line
, i386_insn
*x
)
2332 fprintf (stdout
, "%s: template ", line
);
2334 fprintf (stdout
, " address: base %s index %s scale %x\n",
2335 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2336 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2337 x
->log2_scale_factor
);
2338 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2339 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2340 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2341 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2342 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2343 (x
->rex
& REX_W
) != 0,
2344 (x
->rex
& REX_R
) != 0,
2345 (x
->rex
& REX_X
) != 0,
2346 (x
->rex
& REX_B
) != 0);
2347 for (i
= 0; i
< x
->operands
; i
++)
2349 fprintf (stdout
, " #%d: ", i
+ 1);
2351 fprintf (stdout
, "\n");
2352 if (x
->types
[i
].bitfield
.reg8
2353 || x
->types
[i
].bitfield
.reg16
2354 || x
->types
[i
].bitfield
.reg32
2355 || x
->types
[i
].bitfield
.reg64
2356 || x
->types
[i
].bitfield
.regmmx
2357 || x
->types
[i
].bitfield
.regxmm
2358 || x
->types
[i
].bitfield
.regymm
2359 || x
->types
[i
].bitfield
.sreg2
2360 || x
->types
[i
].bitfield
.sreg3
2361 || x
->types
[i
].bitfield
.control
2362 || x
->types
[i
].bitfield
.debug
2363 || x
->types
[i
].bitfield
.test
)
2364 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2365 if (operand_type_check (x
->types
[i
], imm
))
2367 if (operand_type_check (x
->types
[i
], disp
))
2368 pe (x
->op
[i
].disps
);
2373 pte (insn_template
*t
)
2376 fprintf (stdout
, " %d operands ", t
->operands
);
2377 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2378 if (t
->extension_opcode
!= None
)
2379 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2380 if (t
->opcode_modifier
.d
)
2381 fprintf (stdout
, "D");
2382 if (t
->opcode_modifier
.w
)
2383 fprintf (stdout
, "W");
2384 fprintf (stdout
, "\n");
2385 for (i
= 0; i
< t
->operands
; i
++)
2387 fprintf (stdout
, " #%d type ", i
+ 1);
2388 pt (t
->operand_types
[i
]);
2389 fprintf (stdout
, "\n");
2396 fprintf (stdout
, " operation %d\n", e
->X_op
);
2397 fprintf (stdout
, " add_number %ld (%lx)\n",
2398 (long) e
->X_add_number
, (long) e
->X_add_number
);
2399 if (e
->X_add_symbol
)
2401 fprintf (stdout
, " add_symbol ");
2402 ps (e
->X_add_symbol
);
2403 fprintf (stdout
, "\n");
2407 fprintf (stdout
, " op_symbol ");
2408 ps (e
->X_op_symbol
);
2409 fprintf (stdout
, "\n");
2416 fprintf (stdout
, "%s type %s%s",
2418 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2419 segment_name (S_GET_SEGMENT (s
)));
2422 static struct type_name
2424 i386_operand_type mask
;
2427 const type_names
[] =
2429 { OPERAND_TYPE_REG8
, "r8" },
2430 { OPERAND_TYPE_REG16
, "r16" },
2431 { OPERAND_TYPE_REG32
, "r32" },
2432 { OPERAND_TYPE_REG64
, "r64" },
2433 { OPERAND_TYPE_IMM8
, "i8" },
2434 { OPERAND_TYPE_IMM8
, "i8s" },
2435 { OPERAND_TYPE_IMM16
, "i16" },
2436 { OPERAND_TYPE_IMM32
, "i32" },
2437 { OPERAND_TYPE_IMM32S
, "i32s" },
2438 { OPERAND_TYPE_IMM64
, "i64" },
2439 { OPERAND_TYPE_IMM1
, "i1" },
2440 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2441 { OPERAND_TYPE_DISP8
, "d8" },
2442 { OPERAND_TYPE_DISP16
, "d16" },
2443 { OPERAND_TYPE_DISP32
, "d32" },
2444 { OPERAND_TYPE_DISP32S
, "d32s" },
2445 { OPERAND_TYPE_DISP64
, "d64" },
2446 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2447 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2448 { OPERAND_TYPE_CONTROL
, "control reg" },
2449 { OPERAND_TYPE_TEST
, "test reg" },
2450 { OPERAND_TYPE_DEBUG
, "debug reg" },
2451 { OPERAND_TYPE_FLOATREG
, "FReg" },
2452 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2453 { OPERAND_TYPE_SREG2
, "SReg2" },
2454 { OPERAND_TYPE_SREG3
, "SReg3" },
2455 { OPERAND_TYPE_ACC
, "Acc" },
2456 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2457 { OPERAND_TYPE_REGMMX
, "rMMX" },
2458 { OPERAND_TYPE_REGXMM
, "rXMM" },
2459 { OPERAND_TYPE_REGYMM
, "rYMM" },
2460 { OPERAND_TYPE_ESSEG
, "es" },
2464 pt (i386_operand_type t
)
2467 i386_operand_type a
;
2469 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2471 a
= operand_type_and (t
, type_names
[j
].mask
);
2472 if (!operand_type_all_zero (&a
))
2473 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2478 #endif /* DEBUG386 */
2480 static bfd_reloc_code_real_type
2481 reloc (unsigned int size
,
2484 bfd_reloc_code_real_type other
)
2486 if (other
!= NO_RELOC
)
2488 reloc_howto_type
*rel
;
2493 case BFD_RELOC_X86_64_GOT32
:
2494 return BFD_RELOC_X86_64_GOT64
;
2496 case BFD_RELOC_X86_64_PLTOFF64
:
2497 return BFD_RELOC_X86_64_PLTOFF64
;
2499 case BFD_RELOC_X86_64_GOTPC32
:
2500 other
= BFD_RELOC_X86_64_GOTPC64
;
2502 case BFD_RELOC_X86_64_GOTPCREL
:
2503 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2505 case BFD_RELOC_X86_64_TPOFF32
:
2506 other
= BFD_RELOC_X86_64_TPOFF64
;
2508 case BFD_RELOC_X86_64_DTPOFF32
:
2509 other
= BFD_RELOC_X86_64_DTPOFF64
;
2515 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2516 if (size
== 4 && flag_code
!= CODE_64BIT
)
2519 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2521 as_bad (_("unknown relocation (%u)"), other
);
2522 else if (size
!= bfd_get_reloc_size (rel
))
2523 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2524 bfd_get_reloc_size (rel
),
2526 else if (pcrel
&& !rel
->pc_relative
)
2527 as_bad (_("non-pc-relative relocation for pc-relative field"));
2528 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2530 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2532 as_bad (_("relocated field and relocation type differ in signedness"));
2541 as_bad (_("there are no unsigned pc-relative relocations"));
2544 case 1: return BFD_RELOC_8_PCREL
;
2545 case 2: return BFD_RELOC_16_PCREL
;
2546 case 4: return BFD_RELOC_32_PCREL
;
2547 case 8: return BFD_RELOC_64_PCREL
;
2549 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2556 case 4: return BFD_RELOC_X86_64_32S
;
2561 case 1: return BFD_RELOC_8
;
2562 case 2: return BFD_RELOC_16
;
2563 case 4: return BFD_RELOC_32
;
2564 case 8: return BFD_RELOC_64
;
2566 as_bad (_("cannot do %s %u byte relocation"),
2567 sign
> 0 ? "signed" : "unsigned", size
);
2573 /* Here we decide which fixups can be adjusted to make them relative to
2574 the beginning of the section instead of the symbol. Basically we need
2575 to make sure that the dynamic relocations are done correctly, so in
2576 some cases we force the original symbol to be used. */
2579 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2581 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2585 /* Don't adjust pc-relative references to merge sections in 64-bit
2587 if (use_rela_relocations
2588 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2592 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2593 and changed later by validate_fix. */
2594 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2595 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2598 /* adjust_reloc_syms doesn't know about the GOT. */
2599 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2600 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2601 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2602 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2603 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2604 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2605 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2606 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2607 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2608 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2609 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2610 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2611 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2612 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2613 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2614 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2615 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2616 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2617 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2618 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2619 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2620 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2621 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2622 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2623 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2624 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2625 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2626 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2633 intel_float_operand (const char *mnemonic
)
2635 /* Note that the value returned is meaningful only for opcodes with (memory)
2636 operands, hence the code here is free to improperly handle opcodes that
2637 have no operands (for better performance and smaller code). */
2639 if (mnemonic
[0] != 'f')
2640 return 0; /* non-math */
2642 switch (mnemonic
[1])
2644 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2645 the fs segment override prefix not currently handled because no
2646 call path can make opcodes without operands get here */
2648 return 2 /* integer op */;
2650 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2651 return 3; /* fldcw/fldenv */
2654 if (mnemonic
[2] != 'o' /* fnop */)
2655 return 3; /* non-waiting control op */
2658 if (mnemonic
[2] == 's')
2659 return 3; /* frstor/frstpm */
2662 if (mnemonic
[2] == 'a')
2663 return 3; /* fsave */
2664 if (mnemonic
[2] == 't')
2666 switch (mnemonic
[3])
2668 case 'c': /* fstcw */
2669 case 'd': /* fstdw */
2670 case 'e': /* fstenv */
2671 case 's': /* fsts[gw] */
2677 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2678 return 0; /* fxsave/fxrstor are not really math ops */
2685 /* Build the VEX prefix. */
2688 build_vex_prefix (const insn_template
*t
)
2690 unsigned int register_specifier
;
2691 unsigned int implied_prefix
;
2692 unsigned int vector_length
;
2694 /* Check register specifier. */
2695 if (i
.vex
.register_specifier
)
2697 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2698 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2699 register_specifier
+= 8;
2700 register_specifier
= ~register_specifier
& 0xf;
2703 register_specifier
= 0xf;
2705 /* Use 2-byte VEX prefix by swappping destination and source
2708 && i
.operands
== i
.reg_operands
2709 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2710 && i
.tm
.opcode_modifier
.s
2713 unsigned int xchg
= i
.operands
- 1;
2714 union i386_op temp_op
;
2715 i386_operand_type temp_type
;
2717 temp_type
= i
.types
[xchg
];
2718 i
.types
[xchg
] = i
.types
[0];
2719 i
.types
[0] = temp_type
;
2720 temp_op
= i
.op
[xchg
];
2721 i
.op
[xchg
] = i
.op
[0];
2724 gas_assert (i
.rm
.mode
== 3);
2728 i
.rm
.regmem
= i
.rm
.reg
;
2731 /* Use the next insn. */
2735 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2736 vector_length
= avxscalar
;
2738 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2740 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2745 case DATA_PREFIX_OPCODE
:
2748 case REPE_PREFIX_OPCODE
:
2751 case REPNE_PREFIX_OPCODE
:
2758 /* Use 2-byte VEX prefix if possible. */
2759 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2760 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2762 /* 2-byte VEX prefix. */
2766 i
.vex
.bytes
[0] = 0xc5;
2768 /* Check the REX.R bit. */
2769 r
= (i
.rex
& REX_R
) ? 0 : 1;
2770 i
.vex
.bytes
[1] = (r
<< 7
2771 | register_specifier
<< 3
2772 | vector_length
<< 2
2777 /* 3-byte VEX prefix. */
2782 switch (i
.tm
.opcode_modifier
.vexopcode
)
2786 i
.vex
.bytes
[0] = 0xc4;
2790 i
.vex
.bytes
[0] = 0xc4;
2794 i
.vex
.bytes
[0] = 0xc4;
2798 i
.vex
.bytes
[0] = 0x8f;
2802 i
.vex
.bytes
[0] = 0x8f;
2806 i
.vex
.bytes
[0] = 0x8f;
2812 /* The high 3 bits of the second VEX byte are 1's compliment
2813 of RXB bits from REX. */
2814 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2816 /* Check the REX.W bit. */
2817 w
= (i
.rex
& REX_W
) ? 1 : 0;
2818 if (i
.tm
.opcode_modifier
.vexw
)
2823 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2827 i
.vex
.bytes
[2] = (w
<< 7
2828 | register_specifier
<< 3
2829 | vector_length
<< 2
2835 process_immext (void)
2839 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2841 /* SSE3 Instructions have the fixed operands with an opcode
2842 suffix which is coded in the same place as an 8-bit immediate
2843 field would be. Here we check those operands and remove them
2847 for (x
= 0; x
< i
.operands
; x
++)
2848 if (i
.op
[x
].regs
->reg_num
!= x
)
2849 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2850 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2856 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2857 which is coded in the same place as an 8-bit immediate field
2858 would be. Here we fake an 8-bit immediate operand from the
2859 opcode suffix stored in tm.extension_opcode.
2861 AVX instructions also use this encoding, for some of
2862 3 argument instructions. */
2864 gas_assert (i
.imm_operands
== 0
2866 || (i
.tm
.opcode_modifier
.vex
2867 && i
.operands
<= 4)));
2869 exp
= &im_expressions
[i
.imm_operands
++];
2870 i
.op
[i
.operands
].imms
= exp
;
2871 i
.types
[i
.operands
] = imm8
;
2873 exp
->X_op
= O_constant
;
2874 exp
->X_add_number
= i
.tm
.extension_opcode
;
2875 i
.tm
.extension_opcode
= None
;
2878 /* This is the guts of the machine-dependent assembler. LINE points to a
2879 machine dependent instruction. This function is supposed to emit
2880 the frags/bytes it assembles to. */
2883 md_assemble (char *line
)
2886 char mnemonic
[MAX_MNEM_SIZE
];
2887 const insn_template
*t
;
2889 /* Initialize globals. */
2890 memset (&i
, '\0', sizeof (i
));
2891 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2892 i
.reloc
[j
] = NO_RELOC
;
2893 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2894 memset (im_expressions
, '\0', sizeof (im_expressions
));
2895 save_stack_p
= save_stack
;
2897 /* First parse an instruction mnemonic & call i386_operand for the operands.
2898 We assume that the scrubber has arranged it so that line[0] is the valid
2899 start of a (possibly prefixed) mnemonic. */
2901 line
= parse_insn (line
, mnemonic
);
2905 line
= parse_operands (line
, mnemonic
);
2910 /* Now we've parsed the mnemonic into a set of templates, and have the
2911 operands at hand. */
2913 /* All intel opcodes have reversed operands except for "bound" and
2914 "enter". We also don't reverse intersegment "jmp" and "call"
2915 instructions with 2 immediate operands so that the immediate segment
2916 precedes the offset, as it does when in AT&T mode. */
2919 && (strcmp (mnemonic
, "bound") != 0)
2920 && (strcmp (mnemonic
, "invlpga") != 0)
2921 && !(operand_type_check (i
.types
[0], imm
)
2922 && operand_type_check (i
.types
[1], imm
)))
2925 /* The order of the immediates should be reversed
2926 for 2 immediates extrq and insertq instructions */
2927 if (i
.imm_operands
== 2
2928 && (strcmp (mnemonic
, "extrq") == 0
2929 || strcmp (mnemonic
, "insertq") == 0))
2930 swap_2_operands (0, 1);
2935 /* Don't optimize displacement for movabs since it only takes 64bit
2938 && (flag_code
!= CODE_64BIT
2939 || strcmp (mnemonic
, "movabs") != 0))
2942 /* Next, we find a template that matches the given insn,
2943 making sure the overlap of the given operands types is consistent
2944 with the template operand types. */
2946 if (!(t
= match_template ()))
2949 if (sse_check
!= sse_check_none
2950 && !i
.tm
.opcode_modifier
.noavx
2951 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2952 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2953 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2954 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2955 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2956 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2958 (sse_check
== sse_check_warning
2960 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2963 /* Zap movzx and movsx suffix. The suffix has been set from
2964 "word ptr" or "byte ptr" on the source operand in Intel syntax
2965 or extracted from mnemonic in AT&T syntax. But we'll use
2966 the destination register to choose the suffix for encoding. */
2967 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2969 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2970 there is no suffix, the default will be byte extension. */
2971 if (i
.reg_operands
!= 2
2974 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2979 if (i
.tm
.opcode_modifier
.fwait
)
2980 if (!add_prefix (FWAIT_OPCODE
))
2983 /* Check for lock without a lockable instruction. Destination operand
2984 must be memory unless it is xchg (0x86). */
2985 if (i
.prefix
[LOCK_PREFIX
]
2986 && (!i
.tm
.opcode_modifier
.islockable
2987 || i
.mem_operands
== 0
2988 || (i
.tm
.base_opcode
!= 0x86
2989 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
2991 as_bad (_("expecting lockable instruction after `lock'"));
2995 /* Check string instruction segment overrides. */
2996 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2998 if (!check_string ())
3000 i
.disp_operands
= 0;
3003 if (!process_suffix ())
3006 /* Update operand types. */
3007 for (j
= 0; j
< i
.operands
; j
++)
3008 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3010 /* Make still unresolved immediate matches conform to size of immediate
3011 given in i.suffix. */
3012 if (!finalize_imm ())
3015 if (i
.types
[0].bitfield
.imm1
)
3016 i
.imm_operands
= 0; /* kludge for shift insns. */
3018 /* We only need to check those implicit registers for instructions
3019 with 3 operands or less. */
3020 if (i
.operands
<= 3)
3021 for (j
= 0; j
< i
.operands
; j
++)
3022 if (i
.types
[j
].bitfield
.inoutportreg
3023 || i
.types
[j
].bitfield
.shiftcount
3024 || i
.types
[j
].bitfield
.acc
3025 || i
.types
[j
].bitfield
.floatacc
)
3028 /* ImmExt should be processed after SSE2AVX. */
3029 if (!i
.tm
.opcode_modifier
.sse2avx
3030 && i
.tm
.opcode_modifier
.immext
)
3033 /* For insns with operands there are more diddles to do to the opcode. */
3036 if (!process_operands ())
3039 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3041 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3042 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3045 if (i
.tm
.opcode_modifier
.vex
)
3046 build_vex_prefix (t
);
3048 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3049 instructions may define INT_OPCODE as well, so avoid this corner
3050 case for those instructions that use MODRM. */
3051 if (i
.tm
.base_opcode
== INT_OPCODE
3052 && !i
.tm
.opcode_modifier
.modrm
3053 && i
.op
[0].imms
->X_add_number
== 3)
3055 i
.tm
.base_opcode
= INT3_OPCODE
;
3059 if ((i
.tm
.opcode_modifier
.jump
3060 || i
.tm
.opcode_modifier
.jumpbyte
3061 || i
.tm
.opcode_modifier
.jumpdword
)
3062 && i
.op
[0].disps
->X_op
== O_constant
)
3064 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3065 the absolute address given by the constant. Since ix86 jumps and
3066 calls are pc relative, we need to generate a reloc. */
3067 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3068 i
.op
[0].disps
->X_op
= O_symbol
;
3071 if (i
.tm
.opcode_modifier
.rex64
)
3074 /* For 8 bit registers we need an empty rex prefix. Also if the
3075 instruction already has a prefix, we need to convert old
3076 registers to new ones. */
3078 if ((i
.types
[0].bitfield
.reg8
3079 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3080 || (i
.types
[1].bitfield
.reg8
3081 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3082 || ((i
.types
[0].bitfield
.reg8
3083 || i
.types
[1].bitfield
.reg8
)
3088 i
.rex
|= REX_OPCODE
;
3089 for (x
= 0; x
< 2; x
++)
3091 /* Look for 8 bit operand that uses old registers. */
3092 if (i
.types
[x
].bitfield
.reg8
3093 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3095 /* In case it is "hi" register, give up. */
3096 if (i
.op
[x
].regs
->reg_num
> 3)
3097 as_bad (_("can't encode register '%s%s' in an "
3098 "instruction requiring REX prefix."),
3099 register_prefix
, i
.op
[x
].regs
->reg_name
);
3101 /* Otherwise it is equivalent to the extended register.
3102 Since the encoding doesn't change this is merely
3103 cosmetic cleanup for debug output. */
3105 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3111 add_prefix (REX_OPCODE
| i
.rex
);
3113 /* We are ready to output the insn. */
3118 parse_insn (char *line
, char *mnemonic
)
3121 char *token_start
= l
;
3124 const insn_template
*t
;
3127 /* Non-zero if we found a prefix only acceptable with string insns. */
3128 const char *expecting_string_instruction
= NULL
;
3133 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3138 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3140 as_bad (_("no such instruction: `%s'"), token_start
);
3145 if (!is_space_char (*l
)
3146 && *l
!= END_OF_INSN
3148 || (*l
!= PREFIX_SEPARATOR
3151 as_bad (_("invalid character %s in mnemonic"),
3152 output_invalid (*l
));
3155 if (token_start
== l
)
3157 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3158 as_bad (_("expecting prefix; got nothing"));
3160 as_bad (_("expecting mnemonic; got nothing"));
3164 /* Look up instruction (or prefix) via hash table. */
3165 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3167 if (*l
!= END_OF_INSN
3168 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3169 && current_templates
3170 && current_templates
->start
->opcode_modifier
.isprefix
)
3172 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3174 as_bad ((flag_code
!= CODE_64BIT
3175 ? _("`%s' is only supported in 64-bit mode")
3176 : _("`%s' is not supported in 64-bit mode")),
3177 current_templates
->start
->name
);
3180 /* If we are in 16-bit mode, do not allow addr16 or data16.
3181 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3182 if ((current_templates
->start
->opcode_modifier
.size16
3183 || current_templates
->start
->opcode_modifier
.size32
)
3184 && flag_code
!= CODE_64BIT
3185 && (current_templates
->start
->opcode_modifier
.size32
3186 ^ (flag_code
== CODE_16BIT
)))
3188 as_bad (_("redundant %s prefix"),
3189 current_templates
->start
->name
);
3192 /* Add prefix, checking for repeated prefixes. */
3193 switch (add_prefix (current_templates
->start
->base_opcode
))
3198 expecting_string_instruction
= current_templates
->start
->name
;
3203 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3210 if (!current_templates
)
3212 /* Check if we should swap operand in encoding. */
3213 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3219 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3222 if (!current_templates
)
3225 /* See if we can get a match by trimming off a suffix. */
3228 case WORD_MNEM_SUFFIX
:
3229 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3230 i
.suffix
= SHORT_MNEM_SUFFIX
;
3232 case BYTE_MNEM_SUFFIX
:
3233 case QWORD_MNEM_SUFFIX
:
3234 i
.suffix
= mnem_p
[-1];
3236 current_templates
= (const templates
*) hash_find (op_hash
,
3239 case SHORT_MNEM_SUFFIX
:
3240 case LONG_MNEM_SUFFIX
:
3243 i
.suffix
= mnem_p
[-1];
3245 current_templates
= (const templates
*) hash_find (op_hash
,
3254 if (intel_float_operand (mnemonic
) == 1)
3255 i
.suffix
= SHORT_MNEM_SUFFIX
;
3257 i
.suffix
= LONG_MNEM_SUFFIX
;
3259 current_templates
= (const templates
*) hash_find (op_hash
,
3264 if (!current_templates
)
3266 as_bad (_("no such instruction: `%s'"), token_start
);
3271 if (current_templates
->start
->opcode_modifier
.jump
3272 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3274 /* Check for a branch hint. We allow ",pt" and ",pn" for
3275 predict taken and predict not taken respectively.
3276 I'm not sure that branch hints actually do anything on loop
3277 and jcxz insns (JumpByte) for current Pentium4 chips. They
3278 may work in the future and it doesn't hurt to accept them
3280 if (l
[0] == ',' && l
[1] == 'p')
3284 if (!add_prefix (DS_PREFIX_OPCODE
))
3288 else if (l
[2] == 'n')
3290 if (!add_prefix (CS_PREFIX_OPCODE
))
3296 /* Any other comma loses. */
3299 as_bad (_("invalid character %s in mnemonic"),
3300 output_invalid (*l
));
3304 /* Check if instruction is supported on specified architecture. */
3306 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3308 supported
|= cpu_flags_match (t
);
3309 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3313 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3315 as_bad (flag_code
== CODE_64BIT
3316 ? _("`%s' is not supported in 64-bit mode")
3317 : _("`%s' is only supported in 64-bit mode"),
3318 current_templates
->start
->name
);
3321 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3323 as_bad (_("`%s' is not supported on `%s%s'"),
3324 current_templates
->start
->name
,
3325 cpu_arch_name
? cpu_arch_name
: default_arch
,
3326 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3331 if (!cpu_arch_flags
.bitfield
.cpui386
3332 && (flag_code
!= CODE_16BIT
))
3334 as_warn (_("use .code16 to ensure correct addressing mode"));
3337 /* Check for rep/repne without a string instruction. */
3338 if (expecting_string_instruction
)
3340 static templates override
;
3342 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3343 if (t
->opcode_modifier
.isstring
)
3345 if (t
>= current_templates
->end
)
3347 as_bad (_("expecting string instruction after `%s'"),
3348 expecting_string_instruction
);
3351 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3352 if (!t
->opcode_modifier
.isstring
)
3355 current_templates
= &override
;
3362 parse_operands (char *l
, const char *mnemonic
)
3366 /* 1 if operand is pending after ','. */
3367 unsigned int expecting_operand
= 0;
3369 /* Non-zero if operand parens not balanced. */
3370 unsigned int paren_not_balanced
;
3372 while (*l
!= END_OF_INSN
)
3374 /* Skip optional white space before operand. */
3375 if (is_space_char (*l
))
3377 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3379 as_bad (_("invalid character %s before operand %d"),
3380 output_invalid (*l
),
3384 token_start
= l
; /* after white space */
3385 paren_not_balanced
= 0;
3386 while (paren_not_balanced
|| *l
!= ',')
3388 if (*l
== END_OF_INSN
)
3390 if (paren_not_balanced
)
3393 as_bad (_("unbalanced parenthesis in operand %d."),
3396 as_bad (_("unbalanced brackets in operand %d."),
3401 break; /* we are done */
3403 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3405 as_bad (_("invalid character %s in operand %d"),
3406 output_invalid (*l
),
3413 ++paren_not_balanced
;
3415 --paren_not_balanced
;
3420 ++paren_not_balanced
;
3422 --paren_not_balanced
;
3426 if (l
!= token_start
)
3427 { /* Yes, we've read in another operand. */
3428 unsigned int operand_ok
;
3429 this_operand
= i
.operands
++;
3430 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3431 if (i
.operands
> MAX_OPERANDS
)
3433 as_bad (_("spurious operands; (%d operands/instruction max)"),
3437 /* Now parse operand adding info to 'i' as we go along. */
3438 END_STRING_AND_SAVE (l
);
3442 i386_intel_operand (token_start
,
3443 intel_float_operand (mnemonic
));
3445 operand_ok
= i386_att_operand (token_start
);
3447 RESTORE_END_STRING (l
);
3453 if (expecting_operand
)
3455 expecting_operand_after_comma
:
3456 as_bad (_("expecting operand after ','; got nothing"));
3461 as_bad (_("expecting operand before ','; got nothing"));
3466 /* Now *l must be either ',' or END_OF_INSN. */
3469 if (*++l
== END_OF_INSN
)
3471 /* Just skip it, if it's \n complain. */
3472 goto expecting_operand_after_comma
;
3474 expecting_operand
= 1;
3481 swap_2_operands (int xchg1
, int xchg2
)
3483 union i386_op temp_op
;
3484 i386_operand_type temp_type
;
3485 enum bfd_reloc_code_real temp_reloc
;
3487 temp_type
= i
.types
[xchg2
];
3488 i
.types
[xchg2
] = i
.types
[xchg1
];
3489 i
.types
[xchg1
] = temp_type
;
3490 temp_op
= i
.op
[xchg2
];
3491 i
.op
[xchg2
] = i
.op
[xchg1
];
3492 i
.op
[xchg1
] = temp_op
;
3493 temp_reloc
= i
.reloc
[xchg2
];
3494 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3495 i
.reloc
[xchg1
] = temp_reloc
;
3499 swap_operands (void)
3505 swap_2_operands (1, i
.operands
- 2);
3508 swap_2_operands (0, i
.operands
- 1);
3514 if (i
.mem_operands
== 2)
3516 const seg_entry
*temp_seg
;
3517 temp_seg
= i
.seg
[0];
3518 i
.seg
[0] = i
.seg
[1];
3519 i
.seg
[1] = temp_seg
;
3523 /* Try to ensure constant immediates are represented in the smallest
3528 char guess_suffix
= 0;
3532 guess_suffix
= i
.suffix
;
3533 else if (i
.reg_operands
)
3535 /* Figure out a suffix from the last register operand specified.
3536 We can't do this properly yet, ie. excluding InOutPortReg,
3537 but the following works for instructions with immediates.
3538 In any case, we can't set i.suffix yet. */
3539 for (op
= i
.operands
; --op
>= 0;)
3540 if (i
.types
[op
].bitfield
.reg8
)
3542 guess_suffix
= BYTE_MNEM_SUFFIX
;
3545 else if (i
.types
[op
].bitfield
.reg16
)
3547 guess_suffix
= WORD_MNEM_SUFFIX
;
3550 else if (i
.types
[op
].bitfield
.reg32
)
3552 guess_suffix
= LONG_MNEM_SUFFIX
;
3555 else if (i
.types
[op
].bitfield
.reg64
)
3557 guess_suffix
= QWORD_MNEM_SUFFIX
;
3561 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3562 guess_suffix
= WORD_MNEM_SUFFIX
;
3564 for (op
= i
.operands
; --op
>= 0;)
3565 if (operand_type_check (i
.types
[op
], imm
))
3567 switch (i
.op
[op
].imms
->X_op
)
3570 /* If a suffix is given, this operand may be shortened. */
3571 switch (guess_suffix
)
3573 case LONG_MNEM_SUFFIX
:
3574 i
.types
[op
].bitfield
.imm32
= 1;
3575 i
.types
[op
].bitfield
.imm64
= 1;
3577 case WORD_MNEM_SUFFIX
:
3578 i
.types
[op
].bitfield
.imm16
= 1;
3579 i
.types
[op
].bitfield
.imm32
= 1;
3580 i
.types
[op
].bitfield
.imm32s
= 1;
3581 i
.types
[op
].bitfield
.imm64
= 1;
3583 case BYTE_MNEM_SUFFIX
:
3584 i
.types
[op
].bitfield
.imm8
= 1;
3585 i
.types
[op
].bitfield
.imm8s
= 1;
3586 i
.types
[op
].bitfield
.imm16
= 1;
3587 i
.types
[op
].bitfield
.imm32
= 1;
3588 i
.types
[op
].bitfield
.imm32s
= 1;
3589 i
.types
[op
].bitfield
.imm64
= 1;
3593 /* If this operand is at most 16 bits, convert it
3594 to a signed 16 bit number before trying to see
3595 whether it will fit in an even smaller size.
3596 This allows a 16-bit operand such as $0xffe0 to
3597 be recognised as within Imm8S range. */
3598 if ((i
.types
[op
].bitfield
.imm16
)
3599 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3601 i
.op
[op
].imms
->X_add_number
=
3602 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3604 if ((i
.types
[op
].bitfield
.imm32
)
3605 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3608 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3609 ^ ((offsetT
) 1 << 31))
3610 - ((offsetT
) 1 << 31));
3613 = operand_type_or (i
.types
[op
],
3614 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3616 /* We must avoid matching of Imm32 templates when 64bit
3617 only immediate is available. */
3618 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3619 i
.types
[op
].bitfield
.imm32
= 0;
3626 /* Symbols and expressions. */
3628 /* Convert symbolic operand to proper sizes for matching, but don't
3629 prevent matching a set of insns that only supports sizes other
3630 than those matching the insn suffix. */
3632 i386_operand_type mask
, allowed
;
3633 const insn_template
*t
;
3635 operand_type_set (&mask
, 0);
3636 operand_type_set (&allowed
, 0);
3638 for (t
= current_templates
->start
;
3639 t
< current_templates
->end
;
3641 allowed
= operand_type_or (allowed
,
3642 t
->operand_types
[op
]);
3643 switch (guess_suffix
)
3645 case QWORD_MNEM_SUFFIX
:
3646 mask
.bitfield
.imm64
= 1;
3647 mask
.bitfield
.imm32s
= 1;
3649 case LONG_MNEM_SUFFIX
:
3650 mask
.bitfield
.imm32
= 1;
3652 case WORD_MNEM_SUFFIX
:
3653 mask
.bitfield
.imm16
= 1;
3655 case BYTE_MNEM_SUFFIX
:
3656 mask
.bitfield
.imm8
= 1;
3661 allowed
= operand_type_and (mask
, allowed
);
3662 if (!operand_type_all_zero (&allowed
))
3663 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3670 /* Try to use the smallest displacement type too. */
3672 optimize_disp (void)
3676 for (op
= i
.operands
; --op
>= 0;)
3677 if (operand_type_check (i
.types
[op
], disp
))
3679 if (i
.op
[op
].disps
->X_op
== O_constant
)
3681 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3683 if (i
.types
[op
].bitfield
.disp16
3684 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3686 /* If this operand is at most 16 bits, convert
3687 to a signed 16 bit number and don't use 64bit
3689 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3690 i
.types
[op
].bitfield
.disp64
= 0;
3692 if (i
.types
[op
].bitfield
.disp32
3693 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3695 /* If this operand is at most 32 bits, convert
3696 to a signed 32 bit number and don't use 64bit
3698 op_disp
&= (((offsetT
) 2 << 31) - 1);
3699 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3700 i
.types
[op
].bitfield
.disp64
= 0;
3702 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3704 i
.types
[op
].bitfield
.disp8
= 0;
3705 i
.types
[op
].bitfield
.disp16
= 0;
3706 i
.types
[op
].bitfield
.disp32
= 0;
3707 i
.types
[op
].bitfield
.disp32s
= 0;
3708 i
.types
[op
].bitfield
.disp64
= 0;
3712 else if (flag_code
== CODE_64BIT
)
3714 if (fits_in_signed_long (op_disp
))
3716 i
.types
[op
].bitfield
.disp64
= 0;
3717 i
.types
[op
].bitfield
.disp32s
= 1;
3719 if (i
.prefix
[ADDR_PREFIX
]
3720 && fits_in_unsigned_long (op_disp
))
3721 i
.types
[op
].bitfield
.disp32
= 1;
3723 if ((i
.types
[op
].bitfield
.disp32
3724 || i
.types
[op
].bitfield
.disp32s
3725 || i
.types
[op
].bitfield
.disp16
)
3726 && fits_in_signed_byte (op_disp
))
3727 i
.types
[op
].bitfield
.disp8
= 1;
3729 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3730 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3732 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3733 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3734 i
.types
[op
].bitfield
.disp8
= 0;
3735 i
.types
[op
].bitfield
.disp16
= 0;
3736 i
.types
[op
].bitfield
.disp32
= 0;
3737 i
.types
[op
].bitfield
.disp32s
= 0;
3738 i
.types
[op
].bitfield
.disp64
= 0;
3741 /* We only support 64bit displacement on constants. */
3742 i
.types
[op
].bitfield
.disp64
= 0;
3746 /* Check if operands are valid for the instrucrtion. Update VEX
3750 VEX_check_operands (const insn_template
*t
)
3752 if (!t
->opcode_modifier
.vex
)
3755 /* Only check VEX_Imm4, which must be the first operand. */
3756 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3758 if (i
.op
[0].imms
->X_op
!= O_constant
3759 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3761 i
.err_msg
= _("Imm4 isn't the first operand");
3765 /* Turn off Imm8 so that update_imm won't complain. */
3766 i
.types
[0] = vec_imm4
;
3772 static const insn_template
*
3773 match_template (void)
3775 /* Points to template once we've found it. */
3776 const insn_template
*t
;
3777 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3778 i386_operand_type overlap4
;
3779 unsigned int found_reverse_match
;
3780 i386_opcode_modifier suffix_check
;
3781 i386_operand_type operand_types
[MAX_OPERANDS
];
3782 int addr_prefix_disp
;
3784 unsigned int found_cpu_match
;
3785 unsigned int check_register
;
3787 #if MAX_OPERANDS != 5
3788 # error "MAX_OPERANDS must be 5."
3791 found_reverse_match
= 0;
3792 addr_prefix_disp
= -1;
3794 memset (&suffix_check
, 0, sizeof (suffix_check
));
3795 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3796 suffix_check
.no_bsuf
= 1;
3797 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3798 suffix_check
.no_wsuf
= 1;
3799 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3800 suffix_check
.no_ssuf
= 1;
3801 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3802 suffix_check
.no_lsuf
= 1;
3803 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3804 suffix_check
.no_qsuf
= 1;
3805 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3806 suffix_check
.no_ldsuf
= 1;
3808 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3810 addr_prefix_disp
= -1;
3812 /* Must have right number of operands. */
3813 i
.err_msg
= _("number of operands mismatch");
3814 if (i
.operands
!= t
->operands
)
3817 /* Check processor support. */
3818 i
.err_msg
= _("unsupported");
3819 found_cpu_match
= (cpu_flags_match (t
)
3820 == CPU_FLAGS_PERFECT_MATCH
);
3821 if (!found_cpu_match
)
3824 /* Check old gcc support. */
3825 i
.err_msg
= _("only supported with old gcc");
3826 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3829 /* Check AT&T mnemonic. */
3830 i
.err_msg
= _("unsupported with Intel mnemonic");
3831 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3834 /* Check AT&T/Intel syntax. */
3835 i
.err_msg
= _("unsupported syntax");
3836 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3837 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3840 /* Check the suffix, except for some instructions in intel mode. */
3841 i
.err_msg
= _("invalid instruction suffix");
3842 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3843 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3844 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3845 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3846 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3847 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3848 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3851 if (!operand_size_match (t
))
3854 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3855 operand_types
[j
] = t
->operand_types
[j
];
3857 /* In general, don't allow 64-bit operands in 32-bit mode. */
3858 if (i
.suffix
== QWORD_MNEM_SUFFIX
3859 && flag_code
!= CODE_64BIT
3861 ? (!t
->opcode_modifier
.ignoresize
3862 && !intel_float_operand (t
->name
))
3863 : intel_float_operand (t
->name
) != 2)
3864 && ((!operand_types
[0].bitfield
.regmmx
3865 && !operand_types
[0].bitfield
.regxmm
3866 && !operand_types
[0].bitfield
.regymm
)
3867 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3868 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3869 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3870 && (t
->base_opcode
!= 0x0fc7
3871 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3874 /* In general, don't allow 32-bit operands on pre-386. */
3875 else if (i
.suffix
== LONG_MNEM_SUFFIX
3876 && !cpu_arch_flags
.bitfield
.cpui386
3878 ? (!t
->opcode_modifier
.ignoresize
3879 && !intel_float_operand (t
->name
))
3880 : intel_float_operand (t
->name
) != 2)
3881 && ((!operand_types
[0].bitfield
.regmmx
3882 && !operand_types
[0].bitfield
.regxmm
)
3883 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3884 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3887 /* Do not verify operands when there are none. */
3891 /* We've found a match; break out of loop. */
3895 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3896 into Disp32/Disp16/Disp32 operand. */
3897 if (i
.prefix
[ADDR_PREFIX
] != 0)
3899 /* There should be only one Disp operand. */
3903 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3905 if (operand_types
[j
].bitfield
.disp16
)
3907 addr_prefix_disp
= j
;
3908 operand_types
[j
].bitfield
.disp32
= 1;
3909 operand_types
[j
].bitfield
.disp16
= 0;
3915 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3917 if (operand_types
[j
].bitfield
.disp32
)
3919 addr_prefix_disp
= j
;
3920 operand_types
[j
].bitfield
.disp32
= 0;
3921 operand_types
[j
].bitfield
.disp16
= 1;
3927 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3929 if (operand_types
[j
].bitfield
.disp64
)
3931 addr_prefix_disp
= j
;
3932 operand_types
[j
].bitfield
.disp64
= 0;
3933 operand_types
[j
].bitfield
.disp32
= 1;
3941 /* We check register size only if size of operands can be
3942 encoded the canonical way. */
3943 check_register
= t
->opcode_modifier
.w
;
3944 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3945 switch (t
->operands
)
3948 if (!operand_type_match (overlap0
, i
.types
[0]))
3952 /* xchg %eax, %eax is a special case. It is an aliase for nop
3953 only in 32bit mode and we can use opcode 0x90. In 64bit
3954 mode, we can't use 0x90 for xchg %eax, %eax since it should
3955 zero-extend %eax to %rax. */
3956 if (flag_code
== CODE_64BIT
3957 && t
->base_opcode
== 0x90
3958 && operand_type_equal (&i
.types
[0], &acc32
)
3959 && operand_type_equal (&i
.types
[1], &acc32
))
3963 /* If we swap operand in encoding, we either match
3964 the next one or reverse direction of operands. */
3965 if (t
->opcode_modifier
.s
)
3967 else if (t
->opcode_modifier
.d
)
3972 /* If we swap operand in encoding, we match the next one. */
3973 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3977 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3978 if (!operand_type_match (overlap0
, i
.types
[0])
3979 || !operand_type_match (overlap1
, i
.types
[1])
3981 && !operand_type_register_match (overlap0
, i
.types
[0],
3983 overlap1
, i
.types
[1],
3986 /* Check if other direction is valid ... */
3987 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3991 /* Try reversing direction of operands. */
3992 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3993 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3994 if (!operand_type_match (overlap0
, i
.types
[0])
3995 || !operand_type_match (overlap1
, i
.types
[1])
3997 && !operand_type_register_match (overlap0
,
4004 /* Does not match either direction. */
4007 /* found_reverse_match holds which of D or FloatDR
4009 if (t
->opcode_modifier
.d
)
4010 found_reverse_match
= Opcode_D
;
4011 else if (t
->opcode_modifier
.floatd
)
4012 found_reverse_match
= Opcode_FloatD
;
4014 found_reverse_match
= 0;
4015 if (t
->opcode_modifier
.floatr
)
4016 found_reverse_match
|= Opcode_FloatR
;
4020 /* Found a forward 2 operand match here. */
4021 switch (t
->operands
)
4024 overlap4
= operand_type_and (i
.types
[4],
4027 overlap3
= operand_type_and (i
.types
[3],
4030 overlap2
= operand_type_and (i
.types
[2],
4035 switch (t
->operands
)
4038 if (!operand_type_match (overlap4
, i
.types
[4])
4039 || !operand_type_register_match (overlap3
,
4047 if (!operand_type_match (overlap3
, i
.types
[3])
4049 && !operand_type_register_match (overlap2
,
4057 /* Here we make use of the fact that there are no
4058 reverse match 3 operand instructions, and all 3
4059 operand instructions only need to be checked for
4060 register consistency between operands 2 and 3. */
4061 if (!operand_type_match (overlap2
, i
.types
[2])
4063 && !operand_type_register_match (overlap1
,
4073 /* Found either forward/reverse 2, 3 or 4 operand match here:
4074 slip through to break. */
4076 if (!found_cpu_match
)
4078 found_reverse_match
= 0;
4082 /* Check if VEX operands are valid. */
4083 if (VEX_check_operands (t
))
4086 /* We've found a match; break out of loop. */
4090 if (t
== current_templates
->end
)
4092 /* We found no match. */
4093 as_bad (_("%s for `%s'"), i
.err_msg
,
4094 current_templates
->start
->name
);
4098 if (!quiet_warnings
)
4101 && (i
.types
[0].bitfield
.jumpabsolute
4102 != operand_types
[0].bitfield
.jumpabsolute
))
4104 as_warn (_("indirect %s without `*'"), t
->name
);
4107 if (t
->opcode_modifier
.isprefix
4108 && t
->opcode_modifier
.ignoresize
)
4110 /* Warn them that a data or address size prefix doesn't
4111 affect assembly of the next line of code. */
4112 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4116 /* Copy the template we found. */
4119 if (addr_prefix_disp
!= -1)
4120 i
.tm
.operand_types
[addr_prefix_disp
]
4121 = operand_types
[addr_prefix_disp
];
4123 if (found_reverse_match
)
4125 /* If we found a reverse match we must alter the opcode
4126 direction bit. found_reverse_match holds bits to change
4127 (different for int & float insns). */
4129 i
.tm
.base_opcode
^= found_reverse_match
;
4131 i
.tm
.operand_types
[0] = operand_types
[1];
4132 i
.tm
.operand_types
[1] = operand_types
[0];
4141 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4142 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4144 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4146 as_bad (_("`%s' operand %d must use `%ses' segment"),
4152 /* There's only ever one segment override allowed per instruction.
4153 This instruction possibly has a legal segment override on the
4154 second operand, so copy the segment to where non-string
4155 instructions store it, allowing common code. */
4156 i
.seg
[0] = i
.seg
[1];
4158 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4160 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4162 as_bad (_("`%s' operand %d must use `%ses' segment"),
4173 process_suffix (void)
4175 /* If matched instruction specifies an explicit instruction mnemonic
4177 if (i
.tm
.opcode_modifier
.size16
)
4178 i
.suffix
= WORD_MNEM_SUFFIX
;
4179 else if (i
.tm
.opcode_modifier
.size32
)
4180 i
.suffix
= LONG_MNEM_SUFFIX
;
4181 else if (i
.tm
.opcode_modifier
.size64
)
4182 i
.suffix
= QWORD_MNEM_SUFFIX
;
4183 else if (i
.reg_operands
)
4185 /* If there's no instruction mnemonic suffix we try to invent one
4186 based on register operands. */
4189 /* We take i.suffix from the last register operand specified,
4190 Destination register type is more significant than source
4191 register type. crc32 in SSE4.2 prefers source register
4193 if (i
.tm
.base_opcode
== 0xf20f38f1)
4195 if (i
.types
[0].bitfield
.reg16
)
4196 i
.suffix
= WORD_MNEM_SUFFIX
;
4197 else if (i
.types
[0].bitfield
.reg32
)
4198 i
.suffix
= LONG_MNEM_SUFFIX
;
4199 else if (i
.types
[0].bitfield
.reg64
)
4200 i
.suffix
= QWORD_MNEM_SUFFIX
;
4202 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4204 if (i
.types
[0].bitfield
.reg8
)
4205 i
.suffix
= BYTE_MNEM_SUFFIX
;
4212 if (i
.tm
.base_opcode
== 0xf20f38f1
4213 || i
.tm
.base_opcode
== 0xf20f38f0)
4215 /* We have to know the operand size for crc32. */
4216 as_bad (_("ambiguous memory operand size for `%s`"),
4221 for (op
= i
.operands
; --op
>= 0;)
4222 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4224 if (i
.types
[op
].bitfield
.reg8
)
4226 i
.suffix
= BYTE_MNEM_SUFFIX
;
4229 else if (i
.types
[op
].bitfield
.reg16
)
4231 i
.suffix
= WORD_MNEM_SUFFIX
;
4234 else if (i
.types
[op
].bitfield
.reg32
)
4236 i
.suffix
= LONG_MNEM_SUFFIX
;
4239 else if (i
.types
[op
].bitfield
.reg64
)
4241 i
.suffix
= QWORD_MNEM_SUFFIX
;
4247 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4250 && i
.tm
.opcode_modifier
.ignoresize
4251 && i
.tm
.opcode_modifier
.no_bsuf
)
4253 else if (!check_byte_reg ())
4256 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4259 && i
.tm
.opcode_modifier
.ignoresize
4260 && i
.tm
.opcode_modifier
.no_lsuf
)
4262 else if (!check_long_reg ())
4265 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4268 && i
.tm
.opcode_modifier
.ignoresize
4269 && i
.tm
.opcode_modifier
.no_qsuf
)
4271 else if (!check_qword_reg ())
4274 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4277 && i
.tm
.opcode_modifier
.ignoresize
4278 && i
.tm
.opcode_modifier
.no_wsuf
)
4280 else if (!check_word_reg ())
4283 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4284 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4286 /* Skip if the instruction has x/y suffix. match_template
4287 should check if it is a valid suffix. */
4289 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4290 /* Do nothing if the instruction is going to ignore the prefix. */
4295 else if (i
.tm
.opcode_modifier
.defaultsize
4297 /* exclude fldenv/frstor/fsave/fstenv */
4298 && i
.tm
.opcode_modifier
.no_ssuf
)
4300 i
.suffix
= stackop_size
;
4302 else if (intel_syntax
4304 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4305 || i
.tm
.opcode_modifier
.jumpbyte
4306 || i
.tm
.opcode_modifier
.jumpintersegment
4307 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4308 && i
.tm
.extension_opcode
<= 3)))
4313 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4315 i
.suffix
= QWORD_MNEM_SUFFIX
;
4319 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4320 i
.suffix
= LONG_MNEM_SUFFIX
;
4323 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4324 i
.suffix
= WORD_MNEM_SUFFIX
;
4333 if (i
.tm
.opcode_modifier
.w
)
4335 as_bad (_("no instruction mnemonic suffix given and "
4336 "no register operands; can't size instruction"));
4342 unsigned int suffixes
;
4344 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4345 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4347 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4349 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4351 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4353 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4356 /* There are more than suffix matches. */
4357 if (i
.tm
.opcode_modifier
.w
4358 || ((suffixes
& (suffixes
- 1))
4359 && !i
.tm
.opcode_modifier
.defaultsize
4360 && !i
.tm
.opcode_modifier
.ignoresize
))
4362 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4368 /* Change the opcode based on the operand size given by i.suffix;
4369 We don't need to change things for byte insns. */
4372 && i
.suffix
!= BYTE_MNEM_SUFFIX
4373 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4374 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4376 /* It's not a byte, select word/dword operation. */
4377 if (i
.tm
.opcode_modifier
.w
)
4379 if (i
.tm
.opcode_modifier
.shortform
)
4380 i
.tm
.base_opcode
|= 8;
4382 i
.tm
.base_opcode
|= 1;
4385 /* Now select between word & dword operations via the operand
4386 size prefix, except for instructions that will ignore this
4388 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4390 /* The address size override prefix changes the size of the
4392 if ((flag_code
== CODE_32BIT
4393 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4394 || (flag_code
!= CODE_32BIT
4395 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4396 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4399 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4400 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4401 && !i
.tm
.opcode_modifier
.ignoresize
4402 && !i
.tm
.opcode_modifier
.floatmf
4403 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4404 || (flag_code
== CODE_64BIT
4405 && i
.tm
.opcode_modifier
.jumpbyte
)))
4407 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4409 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4410 prefix
= ADDR_PREFIX_OPCODE
;
4412 if (!add_prefix (prefix
))
4416 /* Set mode64 for an operand. */
4417 if (i
.suffix
== QWORD_MNEM_SUFFIX
4418 && flag_code
== CODE_64BIT
4419 && !i
.tm
.opcode_modifier
.norex64
)
4421 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4422 need rex64. cmpxchg8b is also a special case. */
4423 if (! (i
.operands
== 2
4424 && i
.tm
.base_opcode
== 0x90
4425 && i
.tm
.extension_opcode
== None
4426 && operand_type_equal (&i
.types
[0], &acc64
)
4427 && operand_type_equal (&i
.types
[1], &acc64
))
4428 && ! (i
.operands
== 1
4429 && i
.tm
.base_opcode
== 0xfc7
4430 && i
.tm
.extension_opcode
== 1
4431 && !operand_type_check (i
.types
[0], reg
)
4432 && operand_type_check (i
.types
[0], anymem
)))
4436 /* Size floating point instruction. */
4437 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4438 if (i
.tm
.opcode_modifier
.floatmf
)
4439 i
.tm
.base_opcode
^= 4;
4446 check_byte_reg (void)
4450 for (op
= i
.operands
; --op
>= 0;)
4452 /* If this is an eight bit register, it's OK. If it's the 16 or
4453 32 bit version of an eight bit register, we will just use the
4454 low portion, and that's OK too. */
4455 if (i
.types
[op
].bitfield
.reg8
)
4458 /* crc32 doesn't generate this warning. */
4459 if (i
.tm
.base_opcode
== 0xf20f38f0)
4462 if ((i
.types
[op
].bitfield
.reg16
4463 || i
.types
[op
].bitfield
.reg32
4464 || i
.types
[op
].bitfield
.reg64
)
4465 && i
.op
[op
].regs
->reg_num
< 4)
4467 /* Prohibit these changes in the 64bit mode, since the
4468 lowering is more complicated. */
4469 if (flag_code
== CODE_64BIT
4470 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4472 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4473 register_prefix
, i
.op
[op
].regs
->reg_name
,
4477 #if REGISTER_WARNINGS
4479 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4480 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4482 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4483 ? REGNAM_AL
- REGNAM_AX
4484 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4486 i
.op
[op
].regs
->reg_name
,
4491 /* Any other register is bad. */
4492 if (i
.types
[op
].bitfield
.reg16
4493 || i
.types
[op
].bitfield
.reg32
4494 || i
.types
[op
].bitfield
.reg64
4495 || i
.types
[op
].bitfield
.regmmx
4496 || i
.types
[op
].bitfield
.regxmm
4497 || i
.types
[op
].bitfield
.regymm
4498 || i
.types
[op
].bitfield
.sreg2
4499 || i
.types
[op
].bitfield
.sreg3
4500 || i
.types
[op
].bitfield
.control
4501 || i
.types
[op
].bitfield
.debug
4502 || i
.types
[op
].bitfield
.test
4503 || i
.types
[op
].bitfield
.floatreg
4504 || i
.types
[op
].bitfield
.floatacc
)
4506 as_bad (_("`%s%s' not allowed with `%s%c'"),
4508 i
.op
[op
].regs
->reg_name
,
4518 check_long_reg (void)
4522 for (op
= i
.operands
; --op
>= 0;)
4523 /* Reject eight bit registers, except where the template requires
4524 them. (eg. movzb) */
4525 if (i
.types
[op
].bitfield
.reg8
4526 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4527 || i
.tm
.operand_types
[op
].bitfield
.reg32
4528 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4530 as_bad (_("`%s%s' not allowed with `%s%c'"),
4532 i
.op
[op
].regs
->reg_name
,
4537 /* Warn if the e prefix on a general reg is missing. */
4538 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4539 && i
.types
[op
].bitfield
.reg16
4540 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4541 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4543 /* Prohibit these changes in the 64bit mode, since the
4544 lowering is more complicated. */
4545 if (flag_code
== CODE_64BIT
)
4547 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4548 register_prefix
, i
.op
[op
].regs
->reg_name
,
4552 #if REGISTER_WARNINGS
4554 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4556 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4558 i
.op
[op
].regs
->reg_name
,
4562 /* Warn if the r prefix on a general reg is missing. */
4563 else if (i
.types
[op
].bitfield
.reg64
4564 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4565 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4568 && i
.tm
.opcode_modifier
.toqword
4569 && !i
.types
[0].bitfield
.regxmm
)
4571 /* Convert to QWORD. We want REX byte. */
4572 i
.suffix
= QWORD_MNEM_SUFFIX
;
4576 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4577 register_prefix
, i
.op
[op
].regs
->reg_name
,
4586 check_qword_reg (void)
4590 for (op
= i
.operands
; --op
>= 0; )
4591 /* Reject eight bit registers, except where the template requires
4592 them. (eg. movzb) */
4593 if (i
.types
[op
].bitfield
.reg8
4594 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4595 || i
.tm
.operand_types
[op
].bitfield
.reg32
4596 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4598 as_bad (_("`%s%s' not allowed with `%s%c'"),
4600 i
.op
[op
].regs
->reg_name
,
4605 /* Warn if the e prefix on a general reg is missing. */
4606 else if ((i
.types
[op
].bitfield
.reg16
4607 || i
.types
[op
].bitfield
.reg32
)
4608 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4609 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4611 /* Prohibit these changes in the 64bit mode, since the
4612 lowering is more complicated. */
4614 && i
.tm
.opcode_modifier
.todword
4615 && !i
.types
[0].bitfield
.regxmm
)
4617 /* Convert to DWORD. We don't want REX byte. */
4618 i
.suffix
= LONG_MNEM_SUFFIX
;
4622 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4623 register_prefix
, i
.op
[op
].regs
->reg_name
,
4632 check_word_reg (void)
4635 for (op
= i
.operands
; --op
>= 0;)
4636 /* Reject eight bit registers, except where the template requires
4637 them. (eg. movzb) */
4638 if (i
.types
[op
].bitfield
.reg8
4639 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4640 || i
.tm
.operand_types
[op
].bitfield
.reg32
4641 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4643 as_bad (_("`%s%s' not allowed with `%s%c'"),
4645 i
.op
[op
].regs
->reg_name
,
4650 /* Warn if the e prefix on a general reg is present. */
4651 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4652 && i
.types
[op
].bitfield
.reg32
4653 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4654 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4656 /* Prohibit these changes in the 64bit mode, since the
4657 lowering is more complicated. */
4658 if (flag_code
== CODE_64BIT
)
4660 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4661 register_prefix
, i
.op
[op
].regs
->reg_name
,
4666 #if REGISTER_WARNINGS
4667 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4669 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4671 i
.op
[op
].regs
->reg_name
,
4679 update_imm (unsigned int j
)
4681 i386_operand_type overlap
= i
.types
[j
];
4682 if ((overlap
.bitfield
.imm8
4683 || overlap
.bitfield
.imm8s
4684 || overlap
.bitfield
.imm16
4685 || overlap
.bitfield
.imm32
4686 || overlap
.bitfield
.imm32s
4687 || overlap
.bitfield
.imm64
)
4688 && !operand_type_equal (&overlap
, &imm8
)
4689 && !operand_type_equal (&overlap
, &imm8s
)
4690 && !operand_type_equal (&overlap
, &imm16
)
4691 && !operand_type_equal (&overlap
, &imm32
)
4692 && !operand_type_equal (&overlap
, &imm32s
)
4693 && !operand_type_equal (&overlap
, &imm64
))
4697 i386_operand_type temp
;
4699 operand_type_set (&temp
, 0);
4700 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4702 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4703 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4705 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4706 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4707 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4709 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4710 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4713 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4716 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4717 || operand_type_equal (&overlap
, &imm16_32
)
4718 || operand_type_equal (&overlap
, &imm16_32s
))
4720 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4725 if (!operand_type_equal (&overlap
, &imm8
)
4726 && !operand_type_equal (&overlap
, &imm8s
)
4727 && !operand_type_equal (&overlap
, &imm16
)
4728 && !operand_type_equal (&overlap
, &imm32
)
4729 && !operand_type_equal (&overlap
, &imm32s
)
4730 && !operand_type_equal (&overlap
, &imm64
))
4732 as_bad (_("no instruction mnemonic suffix given; "
4733 "can't determine immediate size"));
4737 i
.types
[j
] = overlap
;
4747 /* Update the first 2 immediate operands. */
4748 n
= i
.operands
> 2 ? 2 : i
.operands
;
4751 for (j
= 0; j
< n
; j
++)
4752 if (update_imm (j
) == 0)
4755 /* The 3rd operand can't be immediate operand. */
4756 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4763 bad_implicit_operand (int xmm
)
4765 const char *ireg
= xmm
? "xmm0" : "ymm0";
4768 as_bad (_("the last operand of `%s' must be `%s%s'"),
4769 i
.tm
.name
, register_prefix
, ireg
);
4771 as_bad (_("the first operand of `%s' must be `%s%s'"),
4772 i
.tm
.name
, register_prefix
, ireg
);
4777 process_operands (void)
4779 /* Default segment register this instruction will use for memory
4780 accesses. 0 means unknown. This is only for optimizing out
4781 unnecessary segment overrides. */
4782 const seg_entry
*default_seg
= 0;
4784 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4786 unsigned int dupl
= i
.operands
;
4787 unsigned int dest
= dupl
- 1;
4790 /* The destination must be an xmm register. */
4791 gas_assert (i
.reg_operands
4792 && MAX_OPERANDS
> dupl
4793 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4795 if (i
.tm
.opcode_modifier
.firstxmm0
)
4797 /* The first operand is implicit and must be xmm0. */
4798 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4799 if (i
.op
[0].regs
->reg_num
!= 0)
4800 return bad_implicit_operand (1);
4802 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4804 /* Keep xmm0 for instructions with VEX prefix and 3
4810 /* We remove the first xmm0 and keep the number of
4811 operands unchanged, which in fact duplicates the
4813 for (j
= 1; j
< i
.operands
; j
++)
4815 i
.op
[j
- 1] = i
.op
[j
];
4816 i
.types
[j
- 1] = i
.types
[j
];
4817 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4821 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4823 gas_assert ((MAX_OPERANDS
- 1) > dupl
4824 && (i
.tm
.opcode_modifier
.vexsources
4827 /* Add the implicit xmm0 for instructions with VEX prefix
4829 for (j
= i
.operands
; j
> 0; j
--)
4831 i
.op
[j
] = i
.op
[j
- 1];
4832 i
.types
[j
] = i
.types
[j
- 1];
4833 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4836 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4837 i
.types
[0] = regxmm
;
4838 i
.tm
.operand_types
[0] = regxmm
;
4841 i
.reg_operands
+= 2;
4846 i
.op
[dupl
] = i
.op
[dest
];
4847 i
.types
[dupl
] = i
.types
[dest
];
4848 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4857 i
.op
[dupl
] = i
.op
[dest
];
4858 i
.types
[dupl
] = i
.types
[dest
];
4859 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4862 if (i
.tm
.opcode_modifier
.immext
)
4865 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4869 /* The first operand is implicit and must be xmm0/ymm0. */
4870 gas_assert (i
.reg_operands
4871 && (operand_type_equal (&i
.types
[0], ®xmm
)
4872 || operand_type_equal (&i
.types
[0], ®ymm
)));
4873 if (i
.op
[0].regs
->reg_num
!= 0)
4874 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4876 for (j
= 1; j
< i
.operands
; j
++)
4878 i
.op
[j
- 1] = i
.op
[j
];
4879 i
.types
[j
- 1] = i
.types
[j
];
4881 /* We need to adjust fields in i.tm since they are used by
4882 build_modrm_byte. */
4883 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4890 else if (i
.tm
.opcode_modifier
.regkludge
)
4892 /* The imul $imm, %reg instruction is converted into
4893 imul $imm, %reg, %reg, and the clr %reg instruction
4894 is converted into xor %reg, %reg. */
4896 unsigned int first_reg_op
;
4898 if (operand_type_check (i
.types
[0], reg
))
4902 /* Pretend we saw the extra register operand. */
4903 gas_assert (i
.reg_operands
== 1
4904 && i
.op
[first_reg_op
+ 1].regs
== 0);
4905 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4906 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4911 if (i
.tm
.opcode_modifier
.shortform
)
4913 if (i
.types
[0].bitfield
.sreg2
4914 || i
.types
[0].bitfield
.sreg3
)
4916 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4917 && i
.op
[0].regs
->reg_num
== 1)
4919 as_bad (_("you can't `pop %scs'"), register_prefix
);
4922 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4923 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4928 /* The register or float register operand is in operand
4932 if (i
.types
[0].bitfield
.floatreg
4933 || operand_type_check (i
.types
[0], reg
))
4937 /* Register goes in low 3 bits of opcode. */
4938 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4939 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4941 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4943 /* Warn about some common errors, but press on regardless.
4944 The first case can be generated by gcc (<= 2.8.1). */
4945 if (i
.operands
== 2)
4947 /* Reversed arguments on faddp, fsubp, etc. */
4948 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4949 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4950 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4954 /* Extraneous `l' suffix on fp insn. */
4955 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4956 register_prefix
, i
.op
[0].regs
->reg_name
);
4961 else if (i
.tm
.opcode_modifier
.modrm
)
4963 /* The opcode is completed (modulo i.tm.extension_opcode which
4964 must be put into the modrm byte). Now, we make the modrm and
4965 index base bytes based on all the info we've collected. */
4967 default_seg
= build_modrm_byte ();
4969 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4973 else if (i
.tm
.opcode_modifier
.isstring
)
4975 /* For the string instructions that allow a segment override
4976 on one of their operands, the default segment is ds. */
4980 if (i
.tm
.base_opcode
== 0x8d /* lea */
4983 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4985 /* If a segment was explicitly specified, and the specified segment
4986 is not the default, use an opcode prefix to select it. If we
4987 never figured out what the default segment is, then default_seg
4988 will be zero at this point, and the specified segment prefix will
4990 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4992 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4998 static const seg_entry
*
4999 build_modrm_byte (void)
5001 const seg_entry
*default_seg
= 0;
5002 unsigned int source
, dest
;
5005 /* The first operand of instructions with VEX prefix and 3 sources
5006 must be VEX_Imm4. */
5007 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5010 unsigned int nds
, reg_slot
;
5013 if (i
.tm
.opcode_modifier
.veximmext
5014 && i
.tm
.opcode_modifier
.immext
)
5016 dest
= i
.operands
- 2;
5017 gas_assert (dest
== 3);
5020 dest
= i
.operands
- 1;
5023 /* There are 2 kinds of instructions:
5024 1. 5 operands: 4 register operands or 3 register operands
5025 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5026 VexW0 or VexW1. The destination must be either XMM or YMM
5028 2. 4 operands: 4 register operands or 3 register operands
5029 plus 1 memory operand, VexXDS, and VexImmExt */
5030 gas_assert ((i
.reg_operands
== 4
5031 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5032 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5033 && (i
.tm
.opcode_modifier
.veximmext
5034 || (i
.imm_operands
== 1
5035 && i
.types
[0].bitfield
.vec_imm4
5036 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5037 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5038 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5039 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5041 if (i
.imm_operands
== 0)
5043 /* When there is no immediate operand, generate an 8bit
5044 immediate operand to encode the first operand. */
5045 exp
= &im_expressions
[i
.imm_operands
++];
5046 i
.op
[i
.operands
].imms
= exp
;
5047 i
.types
[i
.operands
] = imm8
;
5049 /* If VexW1 is set, the first operand is the source and
5050 the second operand is encoded in the immediate operand. */
5051 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5062 /* FMA swaps REG and NDS. */
5063 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5071 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5073 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5075 exp
->X_op
= O_constant
;
5077 = ((i
.op
[reg_slot
].regs
->reg_num
5078 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5083 unsigned int imm_slot
;
5085 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5087 /* If VexW0 is set, the third operand is the source and
5088 the second operand is encoded in the immediate
5095 /* VexW1 is set, the second operand is the source and
5096 the third operand is encoded in the immediate
5102 if (i
.tm
.opcode_modifier
.immext
)
5104 /* When ImmExt is set, the immdiate byte is the last
5106 imm_slot
= i
.operands
- 1;
5114 /* Turn on Imm8 so that output_imm will generate it. */
5115 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5118 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5120 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5122 i
.op
[imm_slot
].imms
->X_add_number
5123 |= ((i
.op
[reg_slot
].regs
->reg_num
5124 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5128 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5129 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5131 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5136 /* i.reg_operands MUST be the number of real register operands;
5137 implicit registers do not count. If there are 3 register
5138 operands, it must be a instruction with VexNDS. For a
5139 instruction with VexNDD, the destination register is encoded
5140 in VEX prefix. If there are 4 register operands, it must be
5141 a instruction with VEX prefix and 3 sources. */
5142 if (i
.mem_operands
== 0
5143 && ((i
.reg_operands
== 2
5144 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5145 || (i
.reg_operands
== 3
5146 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5147 || (i
.reg_operands
== 4 && vex_3_sources
)))
5155 /* When there are 3 operands, one of them may be immediate,
5156 which may be the first or the last operand. Otherwise,
5157 the first operand must be shift count register (cl) or it
5158 is an instruction with VexNDS. */
5159 gas_assert (i
.imm_operands
== 1
5160 || (i
.imm_operands
== 0
5161 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5162 || i
.types
[0].bitfield
.shiftcount
)));
5163 if (operand_type_check (i
.types
[0], imm
)
5164 || i
.types
[0].bitfield
.shiftcount
)
5170 /* When there are 4 operands, the first two must be 8bit
5171 immediate operands. The source operand will be the 3rd
5174 For instructions with VexNDS, if the first operand
5175 an imm8, the source operand is the 2nd one. If the last
5176 operand is imm8, the source operand is the first one. */
5177 gas_assert ((i
.imm_operands
== 2
5178 && i
.types
[0].bitfield
.imm8
5179 && i
.types
[1].bitfield
.imm8
)
5180 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5181 && i
.imm_operands
== 1
5182 && (i
.types
[0].bitfield
.imm8
5183 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5184 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5186 if (i
.types
[0].bitfield
.imm8
)
5204 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5206 /* For instructions with VexNDS, the register-only
5207 source operand must be XMM or YMM register. It is
5208 encoded in VEX prefix. We need to clear RegMem bit
5209 before calling operand_type_equal. */
5210 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5211 op
.bitfield
.regmem
= 0;
5212 if ((dest
+ 1) >= i
.operands
5213 || (!operand_type_equal (&op
, ®xmm
)
5214 && !operand_type_equal (&op
, ®ymm
)))
5216 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5222 /* One of the register operands will be encoded in the i.tm.reg
5223 field, the other in the combined i.tm.mode and i.tm.regmem
5224 fields. If no form of this instruction supports a memory
5225 destination operand, then we assume the source operand may
5226 sometimes be a memory operand and so we need to store the
5227 destination in the i.rm.reg field. */
5228 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5229 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5231 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5232 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5233 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5235 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5240 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5241 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5242 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5244 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5247 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5249 if (!i
.types
[0].bitfield
.control
5250 && !i
.types
[1].bitfield
.control
)
5252 i
.rex
&= ~(REX_R
| REX_B
);
5253 add_prefix (LOCK_PREFIX_OPCODE
);
5257 { /* If it's not 2 reg operands... */
5262 unsigned int fake_zero_displacement
= 0;
5265 for (op
= 0; op
< i
.operands
; op
++)
5266 if (operand_type_check (i
.types
[op
], anymem
))
5268 gas_assert (op
< i
.operands
);
5272 if (i
.base_reg
== 0)
5275 if (!i
.disp_operands
)
5276 fake_zero_displacement
= 1;
5277 if (i
.index_reg
== 0)
5279 /* Operand is just <disp> */
5280 if (flag_code
== CODE_64BIT
)
5282 /* 64bit mode overwrites the 32bit absolute
5283 addressing by RIP relative addressing and
5284 absolute addressing is encoded by one of the
5285 redundant SIB forms. */
5286 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5287 i
.sib
.base
= NO_BASE_REGISTER
;
5288 i
.sib
.index
= NO_INDEX_REGISTER
;
5289 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5290 ? disp32s
: disp32
);
5292 else if ((flag_code
== CODE_16BIT
)
5293 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5295 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5296 i
.types
[op
] = disp16
;
5300 i
.rm
.regmem
= NO_BASE_REGISTER
;
5301 i
.types
[op
] = disp32
;
5304 else /* !i.base_reg && i.index_reg */
5306 if (i
.index_reg
->reg_num
== RegEiz
5307 || i
.index_reg
->reg_num
== RegRiz
)
5308 i
.sib
.index
= NO_INDEX_REGISTER
;
5310 i
.sib
.index
= i
.index_reg
->reg_num
;
5311 i
.sib
.base
= NO_BASE_REGISTER
;
5312 i
.sib
.scale
= i
.log2_scale_factor
;
5313 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5314 i
.types
[op
].bitfield
.disp8
= 0;
5315 i
.types
[op
].bitfield
.disp16
= 0;
5316 i
.types
[op
].bitfield
.disp64
= 0;
5317 if (flag_code
!= CODE_64BIT
)
5319 /* Must be 32 bit */
5320 i
.types
[op
].bitfield
.disp32
= 1;
5321 i
.types
[op
].bitfield
.disp32s
= 0;
5325 i
.types
[op
].bitfield
.disp32
= 0;
5326 i
.types
[op
].bitfield
.disp32s
= 1;
5328 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5332 /* RIP addressing for 64bit mode. */
5333 else if (i
.base_reg
->reg_num
== RegRip
||
5334 i
.base_reg
->reg_num
== RegEip
)
5336 i
.rm
.regmem
= NO_BASE_REGISTER
;
5337 i
.types
[op
].bitfield
.disp8
= 0;
5338 i
.types
[op
].bitfield
.disp16
= 0;
5339 i
.types
[op
].bitfield
.disp32
= 0;
5340 i
.types
[op
].bitfield
.disp32s
= 1;
5341 i
.types
[op
].bitfield
.disp64
= 0;
5342 i
.flags
[op
] |= Operand_PCrel
;
5343 if (! i
.disp_operands
)
5344 fake_zero_displacement
= 1;
5346 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5348 switch (i
.base_reg
->reg_num
)
5351 if (i
.index_reg
== 0)
5353 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5354 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5358 if (i
.index_reg
== 0)
5361 if (operand_type_check (i
.types
[op
], disp
) == 0)
5363 /* fake (%bp) into 0(%bp) */
5364 i
.types
[op
].bitfield
.disp8
= 1;
5365 fake_zero_displacement
= 1;
5368 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5369 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5371 default: /* (%si) -> 4 or (%di) -> 5 */
5372 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5374 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5376 else /* i.base_reg and 32/64 bit mode */
5378 if (flag_code
== CODE_64BIT
5379 && operand_type_check (i
.types
[op
], disp
))
5381 i386_operand_type temp
;
5382 operand_type_set (&temp
, 0);
5383 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5385 if (i
.prefix
[ADDR_PREFIX
] == 0)
5386 i
.types
[op
].bitfield
.disp32s
= 1;
5388 i
.types
[op
].bitfield
.disp32
= 1;
5391 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5392 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5394 i
.sib
.base
= i
.base_reg
->reg_num
;
5395 /* x86-64 ignores REX prefix bit here to avoid decoder
5397 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5400 if (i
.disp_operands
== 0)
5402 fake_zero_displacement
= 1;
5403 i
.types
[op
].bitfield
.disp8
= 1;
5406 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5410 i
.sib
.scale
= i
.log2_scale_factor
;
5411 if (i
.index_reg
== 0)
5413 /* <disp>(%esp) becomes two byte modrm with no index
5414 register. We've already stored the code for esp
5415 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5416 Any base register besides %esp will not use the
5417 extra modrm byte. */
5418 i
.sib
.index
= NO_INDEX_REGISTER
;
5422 if (i
.index_reg
->reg_num
== RegEiz
5423 || i
.index_reg
->reg_num
== RegRiz
)
5424 i
.sib
.index
= NO_INDEX_REGISTER
;
5426 i
.sib
.index
= i
.index_reg
->reg_num
;
5427 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5428 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5433 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5434 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5437 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5440 if (fake_zero_displacement
)
5442 /* Fakes a zero displacement assuming that i.types[op]
5443 holds the correct displacement size. */
5446 gas_assert (i
.op
[op
].disps
== 0);
5447 exp
= &disp_expressions
[i
.disp_operands
++];
5448 i
.op
[op
].disps
= exp
;
5449 exp
->X_op
= O_constant
;
5450 exp
->X_add_number
= 0;
5451 exp
->X_add_symbol
= (symbolS
*) 0;
5452 exp
->X_op_symbol
= (symbolS
*) 0;
5460 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5462 if (operand_type_check (i
.types
[0], imm
))
5463 i
.vex
.register_specifier
= NULL
;
5466 /* VEX.vvvv encodes one of the sources when the first
5467 operand is not an immediate. */
5468 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5469 i
.vex
.register_specifier
= i
.op
[0].regs
;
5471 i
.vex
.register_specifier
= i
.op
[1].regs
;
5474 /* Destination is a XMM register encoded in the ModRM.reg
5476 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5477 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5480 /* ModRM.rm and VEX.B encodes the other source. */
5481 if (!i
.mem_operands
)
5485 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5486 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5488 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5490 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5494 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5496 i
.vex
.register_specifier
= i
.op
[2].regs
;
5497 if (!i
.mem_operands
)
5500 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5501 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5505 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5506 (if any) based on i.tm.extension_opcode. Again, we must be
5507 careful to make sure that segment/control/debug/test/MMX
5508 registers are coded into the i.rm.reg field. */
5509 else if (i
.reg_operands
)
5512 unsigned int vex_reg
= ~0;
5514 for (op
= 0; op
< i
.operands
; op
++)
5515 if (i
.types
[op
].bitfield
.reg8
5516 || i
.types
[op
].bitfield
.reg16
5517 || i
.types
[op
].bitfield
.reg32
5518 || i
.types
[op
].bitfield
.reg64
5519 || i
.types
[op
].bitfield
.regmmx
5520 || i
.types
[op
].bitfield
.regxmm
5521 || i
.types
[op
].bitfield
.regymm
5522 || i
.types
[op
].bitfield
.sreg2
5523 || i
.types
[op
].bitfield
.sreg3
5524 || i
.types
[op
].bitfield
.control
5525 || i
.types
[op
].bitfield
.debug
5526 || i
.types
[op
].bitfield
.test
)
5531 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5533 /* For instructions with VexNDS, the register-only
5534 source operand is encoded in VEX prefix. */
5535 gas_assert (mem
!= (unsigned int) ~0);
5540 gas_assert (op
< i
.operands
);
5545 gas_assert (vex_reg
< i
.operands
);
5548 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5550 /* For instructions with VexNDD, there should be
5551 no memory operand and the register destination
5552 is encoded in VEX prefix. */
5553 gas_assert (i
.mem_operands
== 0
5554 && (op
+ 2) == i
.operands
);
5558 gas_assert (op
< i
.operands
);
5560 if (vex_reg
!= (unsigned int) ~0)
5562 gas_assert (i
.reg_operands
== 2);
5564 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5566 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5570 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5573 /* Don't set OP operand twice. */
5576 /* If there is an extension opcode to put here, the
5577 register number must be put into the regmem field. */
5578 if (i
.tm
.extension_opcode
!= None
)
5580 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5581 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5586 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5587 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5592 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5593 must set it to 3 to indicate this is a register operand
5594 in the regmem field. */
5595 if (!i
.mem_operands
)
5599 /* Fill in i.rm.reg field with extension opcode (if any). */
5600 if (i
.tm
.extension_opcode
!= None
)
5601 i
.rm
.reg
= i
.tm
.extension_opcode
;
5607 output_branch (void)
5612 relax_substateT subtype
;
5617 if (flag_code
== CODE_16BIT
)
5621 if (i
.prefix
[DATA_PREFIX
] != 0)
5627 /* Pentium4 branch hints. */
5628 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5629 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5634 if (i
.prefix
[REX_PREFIX
] != 0)
5640 if (i
.prefixes
!= 0 && !intel_syntax
)
5641 as_warn (_("skipping prefixes on this instruction"));
5643 /* It's always a symbol; End frag & setup for relax.
5644 Make sure there is enough room in this frag for the largest
5645 instruction we may generate in md_convert_frag. This is 2
5646 bytes for the opcode and room for the prefix and largest
5648 frag_grow (prefix
+ 2 + 4);
5649 /* Prefix and 1 opcode byte go in fr_fix. */
5650 p
= frag_more (prefix
+ 1);
5651 if (i
.prefix
[DATA_PREFIX
] != 0)
5652 *p
++ = DATA_PREFIX_OPCODE
;
5653 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5654 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5655 *p
++ = i
.prefix
[SEG_PREFIX
];
5656 if (i
.prefix
[REX_PREFIX
] != 0)
5657 *p
++ = i
.prefix
[REX_PREFIX
];
5658 *p
= i
.tm
.base_opcode
;
5660 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5661 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5662 else if (cpu_arch_flags
.bitfield
.cpui386
)
5663 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5665 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5668 sym
= i
.op
[0].disps
->X_add_symbol
;
5669 off
= i
.op
[0].disps
->X_add_number
;
5671 if (i
.op
[0].disps
->X_op
!= O_constant
5672 && i
.op
[0].disps
->X_op
!= O_symbol
)
5674 /* Handle complex expressions. */
5675 sym
= make_expr_symbol (i
.op
[0].disps
);
5679 /* 1 possible extra opcode + 4 byte displacement go in var part.
5680 Pass reloc in fr_var. */
5681 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5691 if (i
.tm
.opcode_modifier
.jumpbyte
)
5693 /* This is a loop or jecxz type instruction. */
5695 if (i
.prefix
[ADDR_PREFIX
] != 0)
5697 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5700 /* Pentium4 branch hints. */
5701 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5702 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5704 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5713 if (flag_code
== CODE_16BIT
)
5716 if (i
.prefix
[DATA_PREFIX
] != 0)
5718 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5728 if (i
.prefix
[REX_PREFIX
] != 0)
5730 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5734 if (i
.prefixes
!= 0 && !intel_syntax
)
5735 as_warn (_("skipping prefixes on this instruction"));
5737 p
= frag_more (1 + size
);
5738 *p
++ = i
.tm
.base_opcode
;
5740 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5741 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5743 /* All jumps handled here are signed, but don't use a signed limit
5744 check for 32 and 16 bit jumps as we want to allow wrap around at
5745 4G and 64k respectively. */
5747 fixP
->fx_signed
= 1;
5751 output_interseg_jump (void)
5759 if (flag_code
== CODE_16BIT
)
5763 if (i
.prefix
[DATA_PREFIX
] != 0)
5769 if (i
.prefix
[REX_PREFIX
] != 0)
5779 if (i
.prefixes
!= 0 && !intel_syntax
)
5780 as_warn (_("skipping prefixes on this instruction"));
5782 /* 1 opcode; 2 segment; offset */
5783 p
= frag_more (prefix
+ 1 + 2 + size
);
5785 if (i
.prefix
[DATA_PREFIX
] != 0)
5786 *p
++ = DATA_PREFIX_OPCODE
;
5788 if (i
.prefix
[REX_PREFIX
] != 0)
5789 *p
++ = i
.prefix
[REX_PREFIX
];
5791 *p
++ = i
.tm
.base_opcode
;
5792 if (i
.op
[1].imms
->X_op
== O_constant
)
5794 offsetT n
= i
.op
[1].imms
->X_add_number
;
5797 && !fits_in_unsigned_word (n
)
5798 && !fits_in_signed_word (n
))
5800 as_bad (_("16-bit jump out of range"));
5803 md_number_to_chars (p
, n
, size
);
5806 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5807 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5808 if (i
.op
[0].imms
->X_op
!= O_constant
)
5809 as_bad (_("can't handle non absolute segment in `%s'"),
5811 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5817 fragS
*insn_start_frag
;
5818 offsetT insn_start_off
;
5820 /* Tie dwarf2 debug info to the address at the start of the insn.
5821 We can't do this after the insn has been output as the current
5822 frag may have been closed off. eg. by frag_var. */
5823 dwarf2_emit_insn (0);
5825 insn_start_frag
= frag_now
;
5826 insn_start_off
= frag_now_fix ();
5829 if (i
.tm
.opcode_modifier
.jump
)
5831 else if (i
.tm
.opcode_modifier
.jumpbyte
5832 || i
.tm
.opcode_modifier
.jumpdword
)
5834 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5835 output_interseg_jump ();
5838 /* Output normal instructions here. */
5842 unsigned int prefix
;
5844 /* Since the VEX prefix contains the implicit prefix, we don't
5845 need the explicit prefix. */
5846 if (!i
.tm
.opcode_modifier
.vex
)
5848 switch (i
.tm
.opcode_length
)
5851 if (i
.tm
.base_opcode
& 0xff000000)
5853 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5858 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5860 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5861 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5864 if (prefix
!= REPE_PREFIX_OPCODE
5865 || (i
.prefix
[REP_PREFIX
]
5866 != REPE_PREFIX_OPCODE
))
5867 add_prefix (prefix
);
5870 add_prefix (prefix
);
5879 /* The prefix bytes. */
5880 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5882 FRAG_APPEND_1_CHAR (*q
);
5885 if (i
.tm
.opcode_modifier
.vex
)
5887 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5892 /* REX byte is encoded in VEX prefix. */
5896 FRAG_APPEND_1_CHAR (*q
);
5899 /* There should be no other prefixes for instructions
5904 /* Now the VEX prefix. */
5905 p
= frag_more (i
.vex
.length
);
5906 for (j
= 0; j
< i
.vex
.length
; j
++)
5907 p
[j
] = i
.vex
.bytes
[j
];
5910 /* Now the opcode; be careful about word order here! */
5911 if (i
.tm
.opcode_length
== 1)
5913 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5917 switch (i
.tm
.opcode_length
)
5921 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5931 /* Put out high byte first: can't use md_number_to_chars! */
5932 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5933 *p
= i
.tm
.base_opcode
& 0xff;
5936 /* Now the modrm byte and sib byte (if present). */
5937 if (i
.tm
.opcode_modifier
.modrm
)
5939 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5942 /* If i.rm.regmem == ESP (4)
5943 && i.rm.mode != (Register mode)
5945 ==> need second modrm byte. */
5946 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5948 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5949 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5951 | i
.sib
.scale
<< 6));
5954 if (i
.disp_operands
)
5955 output_disp (insn_start_frag
, insn_start_off
);
5958 output_imm (insn_start_frag
, insn_start_off
);
5964 pi ("" /*line*/, &i
);
5966 #endif /* DEBUG386 */
5969 /* Return the size of the displacement operand N. */
5972 disp_size (unsigned int n
)
5975 if (i
.types
[n
].bitfield
.disp64
)
5977 else if (i
.types
[n
].bitfield
.disp8
)
5979 else if (i
.types
[n
].bitfield
.disp16
)
5984 /* Return the size of the immediate operand N. */
5987 imm_size (unsigned int n
)
5990 if (i
.types
[n
].bitfield
.imm64
)
5992 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5994 else if (i
.types
[n
].bitfield
.imm16
)
6000 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6005 for (n
= 0; n
< i
.operands
; n
++)
6007 if (operand_type_check (i
.types
[n
], disp
))
6009 if (i
.op
[n
].disps
->X_op
== O_constant
)
6011 int size
= disp_size (n
);
6014 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6016 p
= frag_more (size
);
6017 md_number_to_chars (p
, val
, size
);
6021 enum bfd_reloc_code_real reloc_type
;
6022 int size
= disp_size (n
);
6023 int sign
= i
.types
[n
].bitfield
.disp32s
;
6024 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6026 /* We can't have 8 bit displacement here. */
6027 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6029 /* The PC relative address is computed relative
6030 to the instruction boundary, so in case immediate
6031 fields follows, we need to adjust the value. */
6032 if (pcrel
&& i
.imm_operands
)
6037 for (n1
= 0; n1
< i
.operands
; n1
++)
6038 if (operand_type_check (i
.types
[n1
], imm
))
6040 /* Only one immediate is allowed for PC
6041 relative address. */
6042 gas_assert (sz
== 0);
6044 i
.op
[n
].disps
->X_add_number
-= sz
;
6046 /* We should find the immediate. */
6047 gas_assert (sz
!= 0);
6050 p
= frag_more (size
);
6051 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6053 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6054 && (((reloc_type
== BFD_RELOC_32
6055 || reloc_type
== BFD_RELOC_X86_64_32S
6056 || (reloc_type
== BFD_RELOC_64
6058 && (i
.op
[n
].disps
->X_op
== O_symbol
6059 || (i
.op
[n
].disps
->X_op
== O_add
6060 && ((symbol_get_value_expression
6061 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6063 || reloc_type
== BFD_RELOC_32_PCREL
))
6067 if (insn_start_frag
== frag_now
)
6068 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6073 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6074 for (fr
= insn_start_frag
->fr_next
;
6075 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6077 add
+= p
- frag_now
->fr_literal
;
6082 reloc_type
= BFD_RELOC_386_GOTPC
;
6083 i
.op
[n
].imms
->X_add_number
+= add
;
6085 else if (reloc_type
== BFD_RELOC_64
)
6086 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6088 /* Don't do the adjustment for x86-64, as there
6089 the pcrel addressing is relative to the _next_
6090 insn, and that is taken care of in other code. */
6091 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6093 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6094 i
.op
[n
].disps
, pcrel
, reloc_type
);
6101 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6106 for (n
= 0; n
< i
.operands
; n
++)
6108 if (operand_type_check (i
.types
[n
], imm
))
6110 if (i
.op
[n
].imms
->X_op
== O_constant
)
6112 int size
= imm_size (n
);
6115 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6117 p
= frag_more (size
);
6118 md_number_to_chars (p
, val
, size
);
6122 /* Not absolute_section.
6123 Need a 32-bit fixup (don't support 8bit
6124 non-absolute imms). Try to support other
6126 enum bfd_reloc_code_real reloc_type
;
6127 int size
= imm_size (n
);
6130 if (i
.types
[n
].bitfield
.imm32s
6131 && (i
.suffix
== QWORD_MNEM_SUFFIX
6132 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6137 p
= frag_more (size
);
6138 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6140 /* This is tough to explain. We end up with this one if we
6141 * have operands that look like
6142 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6143 * obtain the absolute address of the GOT, and it is strongly
6144 * preferable from a performance point of view to avoid using
6145 * a runtime relocation for this. The actual sequence of
6146 * instructions often look something like:
6151 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6153 * The call and pop essentially return the absolute address
6154 * of the label .L66 and store it in %ebx. The linker itself
6155 * will ultimately change the first operand of the addl so
6156 * that %ebx points to the GOT, but to keep things simple, the
6157 * .o file must have this operand set so that it generates not
6158 * the absolute address of .L66, but the absolute address of
6159 * itself. This allows the linker itself simply treat a GOTPC
6160 * relocation as asking for a pcrel offset to the GOT to be
6161 * added in, and the addend of the relocation is stored in the
6162 * operand field for the instruction itself.
6164 * Our job here is to fix the operand so that it would add
6165 * the correct offset so that %ebx would point to itself. The
6166 * thing that is tricky is that .-.L66 will point to the
6167 * beginning of the instruction, so we need to further modify
6168 * the operand so that it will point to itself. There are
6169 * other cases where you have something like:
6171 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6173 * and here no correction would be required. Internally in
6174 * the assembler we treat operands of this form as not being
6175 * pcrel since the '.' is explicitly mentioned, and I wonder
6176 * whether it would simplify matters to do it this way. Who
6177 * knows. In earlier versions of the PIC patches, the
6178 * pcrel_adjust field was used to store the correction, but
6179 * since the expression is not pcrel, I felt it would be
6180 * confusing to do it this way. */
6182 if ((reloc_type
== BFD_RELOC_32
6183 || reloc_type
== BFD_RELOC_X86_64_32S
6184 || reloc_type
== BFD_RELOC_64
)
6186 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6187 && (i
.op
[n
].imms
->X_op
== O_symbol
6188 || (i
.op
[n
].imms
->X_op
== O_add
6189 && ((symbol_get_value_expression
6190 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6195 if (insn_start_frag
== frag_now
)
6196 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6201 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6202 for (fr
= insn_start_frag
->fr_next
;
6203 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6205 add
+= p
- frag_now
->fr_literal
;
6209 reloc_type
= BFD_RELOC_386_GOTPC
;
6211 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6213 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6214 i
.op
[n
].imms
->X_add_number
+= add
;
6216 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6217 i
.op
[n
].imms
, 0, reloc_type
);
6223 /* x86_cons_fix_new is called via the expression parsing code when a
6224 reloc is needed. We use this hook to get the correct .got reloc. */
6225 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6226 static int cons_sign
= -1;
6229 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6232 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6234 got_reloc
= NO_RELOC
;
6237 if (exp
->X_op
== O_secrel
)
6239 exp
->X_op
= O_symbol
;
6240 r
= BFD_RELOC_32_SECREL
;
6244 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6247 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6248 # define lex_got(reloc, adjust, types) NULL
6250 /* Parse operands of the form
6251 <symbol>@GOTOFF+<nnn>
6252 and similar .plt or .got references.
6254 If we find one, set up the correct relocation in RELOC and copy the
6255 input string, minus the `@GOTOFF' into a malloc'd buffer for
6256 parsing by the calling routine. Return this buffer, and if ADJUST
6257 is non-null set it to the length of the string we removed from the
6258 input line. Otherwise return NULL. */
6260 lex_got (enum bfd_reloc_code_real
*rel
,
6262 i386_operand_type
*types
)
6264 /* Some of the relocations depend on the size of what field is to
6265 be relocated. But in our callers i386_immediate and i386_displacement
6266 we don't yet know the operand size (this will be set by insn
6267 matching). Hence we record the word32 relocation here,
6268 and adjust the reloc according to the real size in reloc(). */
6269 static const struct {
6271 const enum bfd_reloc_code_real rel
[2];
6272 const i386_operand_type types64
;
6274 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6275 BFD_RELOC_X86_64_PLTOFF64
},
6276 OPERAND_TYPE_IMM64
},
6277 { "PLT", { BFD_RELOC_386_PLT32
,
6278 BFD_RELOC_X86_64_PLT32
},
6279 OPERAND_TYPE_IMM32_32S_DISP32
},
6280 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6281 BFD_RELOC_X86_64_GOTPLT64
},
6282 OPERAND_TYPE_IMM64_DISP64
},
6283 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6284 BFD_RELOC_X86_64_GOTOFF64
},
6285 OPERAND_TYPE_IMM64_DISP64
},
6286 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6287 BFD_RELOC_X86_64_GOTPCREL
},
6288 OPERAND_TYPE_IMM32_32S_DISP32
},
6289 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6290 BFD_RELOC_X86_64_TLSGD
},
6291 OPERAND_TYPE_IMM32_32S_DISP32
},
6292 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6293 _dummy_first_bfd_reloc_code_real
},
6294 OPERAND_TYPE_NONE
},
6295 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6296 BFD_RELOC_X86_64_TLSLD
},
6297 OPERAND_TYPE_IMM32_32S_DISP32
},
6298 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6299 BFD_RELOC_X86_64_GOTTPOFF
},
6300 OPERAND_TYPE_IMM32_32S_DISP32
},
6301 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6302 BFD_RELOC_X86_64_TPOFF32
},
6303 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6304 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6305 _dummy_first_bfd_reloc_code_real
},
6306 OPERAND_TYPE_NONE
},
6307 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6308 BFD_RELOC_X86_64_DTPOFF32
},
6310 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6311 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6312 _dummy_first_bfd_reloc_code_real
},
6313 OPERAND_TYPE_NONE
},
6314 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6315 _dummy_first_bfd_reloc_code_real
},
6316 OPERAND_TYPE_NONE
},
6317 { "GOT", { BFD_RELOC_386_GOT32
,
6318 BFD_RELOC_X86_64_GOT32
},
6319 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6320 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6321 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6322 OPERAND_TYPE_IMM32_32S_DISP32
},
6323 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6324 BFD_RELOC_X86_64_TLSDESC_CALL
},
6325 OPERAND_TYPE_IMM32_32S_DISP32
},
6333 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6334 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6337 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6341 len
= strlen (gotrel
[j
].str
);
6342 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6344 if (gotrel
[j
].rel
[object_64bit
] != 0)
6347 char *tmpbuf
, *past_reloc
;
6349 *rel
= gotrel
[j
].rel
[object_64bit
];
6355 if (flag_code
!= CODE_64BIT
)
6357 types
->bitfield
.imm32
= 1;
6358 types
->bitfield
.disp32
= 1;
6361 *types
= gotrel
[j
].types64
;
6364 if (GOT_symbol
== NULL
)
6365 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6367 /* The length of the first part of our input line. */
6368 first
= cp
- input_line_pointer
;
6370 /* The second part goes from after the reloc token until
6371 (and including) an end_of_line char or comma. */
6372 past_reloc
= cp
+ 1 + len
;
6374 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6376 second
= cp
+ 1 - past_reloc
;
6378 /* Allocate and copy string. The trailing NUL shouldn't
6379 be necessary, but be safe. */
6380 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6381 memcpy (tmpbuf
, input_line_pointer
, first
);
6382 if (second
!= 0 && *past_reloc
!= ' ')
6383 /* Replace the relocation token with ' ', so that
6384 errors like foo@GOTOFF1 will be detected. */
6385 tmpbuf
[first
++] = ' ';
6386 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6387 tmpbuf
[first
+ second
] = '\0';
6391 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6392 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6397 /* Might be a symbol version string. Don't as_bad here. */
6402 x86_cons (expressionS
*exp
, int size
)
6404 intel_syntax
= -intel_syntax
;
6406 if (size
== 4 || (object_64bit
&& size
== 8))
6408 /* Handle @GOTOFF and the like in an expression. */
6410 char *gotfree_input_line
;
6413 save
= input_line_pointer
;
6414 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6415 if (gotfree_input_line
)
6416 input_line_pointer
= gotfree_input_line
;
6420 if (gotfree_input_line
)
6422 /* expression () has merrily parsed up to the end of line,
6423 or a comma - in the wrong buffer. Transfer how far
6424 input_line_pointer has moved to the right buffer. */
6425 input_line_pointer
= (save
6426 + (input_line_pointer
- gotfree_input_line
)
6428 free (gotfree_input_line
);
6429 if (exp
->X_op
== O_constant
6430 || exp
->X_op
== O_absent
6431 || exp
->X_op
== O_illegal
6432 || exp
->X_op
== O_register
6433 || exp
->X_op
== O_big
)
6435 char c
= *input_line_pointer
;
6436 *input_line_pointer
= 0;
6437 as_bad (_("missing or invalid expression `%s'"), save
);
6438 *input_line_pointer
= c
;
6445 intel_syntax
= -intel_syntax
;
6448 i386_intel_simplify (exp
);
6453 signed_cons (int size
)
6455 if (flag_code
== CODE_64BIT
)
6463 pe_directive_secrel (dummy
)
6464 int dummy ATTRIBUTE_UNUSED
;
6471 if (exp
.X_op
== O_symbol
)
6472 exp
.X_op
= O_secrel
;
6474 emit_expr (&exp
, 4);
6476 while (*input_line_pointer
++ == ',');
6478 input_line_pointer
--;
6479 demand_empty_rest_of_line ();
6484 i386_immediate (char *imm_start
)
6486 char *save_input_line_pointer
;
6487 char *gotfree_input_line
;
6490 i386_operand_type types
;
6492 operand_type_set (&types
, ~0);
6494 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6496 as_bad (_("at most %d immediate operands are allowed"),
6497 MAX_IMMEDIATE_OPERANDS
);
6501 exp
= &im_expressions
[i
.imm_operands
++];
6502 i
.op
[this_operand
].imms
= exp
;
6504 if (is_space_char (*imm_start
))
6507 save_input_line_pointer
= input_line_pointer
;
6508 input_line_pointer
= imm_start
;
6510 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6511 if (gotfree_input_line
)
6512 input_line_pointer
= gotfree_input_line
;
6514 exp_seg
= expression (exp
);
6517 if (*input_line_pointer
)
6518 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6520 input_line_pointer
= save_input_line_pointer
;
6521 if (gotfree_input_line
)
6523 free (gotfree_input_line
);
6525 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6526 exp
->X_op
= O_illegal
;
6529 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6533 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6534 i386_operand_type types
, const char *imm_start
)
6536 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6539 as_bad (_("missing or invalid immediate expression `%s'"),
6543 else if (exp
->X_op
== O_constant
)
6545 /* Size it properly later. */
6546 i
.types
[this_operand
].bitfield
.imm64
= 1;
6547 /* If BFD64, sign extend val. */
6548 if (!use_rela_relocations
6549 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6551 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6553 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6554 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6555 && exp_seg
!= absolute_section
6556 && exp_seg
!= text_section
6557 && exp_seg
!= data_section
6558 && exp_seg
!= bss_section
6559 && exp_seg
!= undefined_section
6560 && !bfd_is_com_section (exp_seg
))
6562 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6566 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6569 as_bad (_("illegal immediate register operand %s"), imm_start
);
6574 /* This is an address. The size of the address will be
6575 determined later, depending on destination register,
6576 suffix, or the default for the section. */
6577 i
.types
[this_operand
].bitfield
.imm8
= 1;
6578 i
.types
[this_operand
].bitfield
.imm16
= 1;
6579 i
.types
[this_operand
].bitfield
.imm32
= 1;
6580 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6581 i
.types
[this_operand
].bitfield
.imm64
= 1;
6582 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6590 i386_scale (char *scale
)
6593 char *save
= input_line_pointer
;
6595 input_line_pointer
= scale
;
6596 val
= get_absolute_expression ();
6601 i
.log2_scale_factor
= 0;
6604 i
.log2_scale_factor
= 1;
6607 i
.log2_scale_factor
= 2;
6610 i
.log2_scale_factor
= 3;
6614 char sep
= *input_line_pointer
;
6616 *input_line_pointer
= '\0';
6617 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6619 *input_line_pointer
= sep
;
6620 input_line_pointer
= save
;
6624 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6626 as_warn (_("scale factor of %d without an index register"),
6627 1 << i
.log2_scale_factor
);
6628 i
.log2_scale_factor
= 0;
6630 scale
= input_line_pointer
;
6631 input_line_pointer
= save
;
6636 i386_displacement (char *disp_start
, char *disp_end
)
6640 char *save_input_line_pointer
;
6641 char *gotfree_input_line
;
6643 i386_operand_type bigdisp
, types
= anydisp
;
6646 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6648 as_bad (_("at most %d displacement operands are allowed"),
6649 MAX_MEMORY_OPERANDS
);
6653 operand_type_set (&bigdisp
, 0);
6654 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6655 || (!current_templates
->start
->opcode_modifier
.jump
6656 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6658 bigdisp
.bitfield
.disp32
= 1;
6659 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6660 if (flag_code
== CODE_64BIT
)
6664 bigdisp
.bitfield
.disp32s
= 1;
6665 bigdisp
.bitfield
.disp64
= 1;
6668 else if ((flag_code
== CODE_16BIT
) ^ override
)
6670 bigdisp
.bitfield
.disp32
= 0;
6671 bigdisp
.bitfield
.disp16
= 1;
6676 /* For PC-relative branches, the width of the displacement
6677 is dependent upon data size, not address size. */
6678 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6679 if (flag_code
== CODE_64BIT
)
6681 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6682 bigdisp
.bitfield
.disp16
= 1;
6685 bigdisp
.bitfield
.disp32
= 1;
6686 bigdisp
.bitfield
.disp32s
= 1;
6692 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6694 : LONG_MNEM_SUFFIX
));
6695 bigdisp
.bitfield
.disp32
= 1;
6696 if ((flag_code
== CODE_16BIT
) ^ override
)
6698 bigdisp
.bitfield
.disp32
= 0;
6699 bigdisp
.bitfield
.disp16
= 1;
6703 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6706 exp
= &disp_expressions
[i
.disp_operands
];
6707 i
.op
[this_operand
].disps
= exp
;
6709 save_input_line_pointer
= input_line_pointer
;
6710 input_line_pointer
= disp_start
;
6711 END_STRING_AND_SAVE (disp_end
);
6713 #ifndef GCC_ASM_O_HACK
6714 #define GCC_ASM_O_HACK 0
6717 END_STRING_AND_SAVE (disp_end
+ 1);
6718 if (i
.types
[this_operand
].bitfield
.baseIndex
6719 && displacement_string_end
[-1] == '+')
6721 /* This hack is to avoid a warning when using the "o"
6722 constraint within gcc asm statements.
6725 #define _set_tssldt_desc(n,addr,limit,type) \
6726 __asm__ __volatile__ ( \
6728 "movw %w1,2+%0\n\t" \
6730 "movb %b1,4+%0\n\t" \
6731 "movb %4,5+%0\n\t" \
6732 "movb $0,6+%0\n\t" \
6733 "movb %h1,7+%0\n\t" \
6735 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6737 This works great except that the output assembler ends
6738 up looking a bit weird if it turns out that there is
6739 no offset. You end up producing code that looks like:
6752 So here we provide the missing zero. */
6754 *displacement_string_end
= '0';
6757 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6758 if (gotfree_input_line
)
6759 input_line_pointer
= gotfree_input_line
;
6761 exp_seg
= expression (exp
);
6764 if (*input_line_pointer
)
6765 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6767 RESTORE_END_STRING (disp_end
+ 1);
6769 input_line_pointer
= save_input_line_pointer
;
6770 if (gotfree_input_line
)
6772 free (gotfree_input_line
);
6774 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6775 exp
->X_op
= O_illegal
;
6778 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6780 RESTORE_END_STRING (disp_end
);
6786 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6787 i386_operand_type types
, const char *disp_start
)
6789 i386_operand_type bigdisp
;
6792 /* We do this to make sure that the section symbol is in
6793 the symbol table. We will ultimately change the relocation
6794 to be relative to the beginning of the section. */
6795 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6796 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6797 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6799 if (exp
->X_op
!= O_symbol
)
6802 if (S_IS_LOCAL (exp
->X_add_symbol
)
6803 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6804 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6805 exp
->X_op
= O_subtract
;
6806 exp
->X_op_symbol
= GOT_symbol
;
6807 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6808 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6809 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6810 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6812 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6815 else if (exp
->X_op
== O_absent
6816 || exp
->X_op
== O_illegal
6817 || exp
->X_op
== O_big
)
6820 as_bad (_("missing or invalid displacement expression `%s'"),
6825 else if (flag_code
== CODE_64BIT
6826 && !i
.prefix
[ADDR_PREFIX
]
6827 && exp
->X_op
== O_constant
)
6829 /* Since displacement is signed extended to 64bit, don't allow
6830 disp32 and turn off disp32s if they are out of range. */
6831 i
.types
[this_operand
].bitfield
.disp32
= 0;
6832 if (!fits_in_signed_long (exp
->X_add_number
))
6834 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6835 if (i
.types
[this_operand
].bitfield
.baseindex
)
6837 as_bad (_("0x%lx out range of signed 32bit displacement"),
6838 (long) exp
->X_add_number
);
6844 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6845 else if (exp
->X_op
!= O_constant
6846 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6847 && exp_seg
!= absolute_section
6848 && exp_seg
!= text_section
6849 && exp_seg
!= data_section
6850 && exp_seg
!= bss_section
6851 && exp_seg
!= undefined_section
6852 && !bfd_is_com_section (exp_seg
))
6854 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6859 /* Check if this is a displacement only operand. */
6860 bigdisp
= i
.types
[this_operand
];
6861 bigdisp
.bitfield
.disp8
= 0;
6862 bigdisp
.bitfield
.disp16
= 0;
6863 bigdisp
.bitfield
.disp32
= 0;
6864 bigdisp
.bitfield
.disp32s
= 0;
6865 bigdisp
.bitfield
.disp64
= 0;
6866 if (operand_type_all_zero (&bigdisp
))
6867 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6873 /* Make sure the memory operand we've been dealt is valid.
6874 Return 1 on success, 0 on a failure. */
6877 i386_index_check (const char *operand_string
)
6880 const char *kind
= "base/index";
6881 #if INFER_ADDR_PREFIX
6887 if (current_templates
->start
->opcode_modifier
.isstring
6888 && !current_templates
->start
->opcode_modifier
.immext
6889 && (current_templates
->end
[-1].opcode_modifier
.isstring
6892 /* Memory operands of string insns are special in that they only allow
6893 a single register (rDI, rSI, or rBX) as their memory address. */
6894 unsigned int expected
;
6896 kind
= "string address";
6898 if (current_templates
->start
->opcode_modifier
.w
)
6900 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6902 if (!type
.bitfield
.baseindex
6903 || ((!i
.mem_operands
!= !intel_syntax
)
6904 && current_templates
->end
[-1].operand_types
[1]
6905 .bitfield
.baseindex
))
6906 type
= current_templates
->end
[-1].operand_types
[1];
6907 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6910 expected
= 3 /* rBX */;
6912 if (!i
.base_reg
|| i
.index_reg
6913 || operand_type_check (i
.types
[this_operand
], disp
))
6915 else if (!(flag_code
== CODE_64BIT
6916 ? i
.prefix
[ADDR_PREFIX
]
6917 ? i
.base_reg
->reg_type
.bitfield
.reg32
6918 : i
.base_reg
->reg_type
.bitfield
.reg64
6919 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6920 ? i
.base_reg
->reg_type
.bitfield
.reg32
6921 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6923 else if (i
.base_reg
->reg_num
!= expected
)
6930 for (j
= 0; j
< i386_regtab_size
; ++j
)
6931 if ((flag_code
== CODE_64BIT
6932 ? i
.prefix
[ADDR_PREFIX
]
6933 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6934 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6935 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6936 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6937 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6938 && i386_regtab
[j
].reg_num
== expected
)
6940 gas_assert (j
< i386_regtab_size
);
6941 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6943 intel_syntax
? '[' : '(',
6945 i386_regtab
[j
].reg_name
,
6946 intel_syntax
? ']' : ')');
6950 else if (flag_code
== CODE_64BIT
)
6953 && ((i
.prefix
[ADDR_PREFIX
] == 0
6954 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6955 || (i
.prefix
[ADDR_PREFIX
]
6956 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6958 || i
.base_reg
->reg_num
!=
6959 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6961 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6962 || (i
.prefix
[ADDR_PREFIX
] == 0
6963 && i
.index_reg
->reg_num
!= RegRiz
6964 && !i
.index_reg
->reg_type
.bitfield
.reg64
6966 || (i
.prefix
[ADDR_PREFIX
]
6967 && i
.index_reg
->reg_num
!= RegEiz
6968 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6973 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6977 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6978 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6980 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6981 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6983 && i
.base_reg
->reg_num
< 6
6984 && i
.index_reg
->reg_num
>= 6
6985 && i
.log2_scale_factor
== 0))))
6992 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6994 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6995 && i
.index_reg
->reg_num
!= RegEiz
)
6996 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7002 #if INFER_ADDR_PREFIX
7003 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7005 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7007 /* Change the size of any displacement too. At most one of
7008 Disp16 or Disp32 is set.
7009 FIXME. There doesn't seem to be any real need for separate
7010 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7011 Removing them would probably clean up the code quite a lot. */
7012 if (flag_code
!= CODE_64BIT
7013 && (i
.types
[this_operand
].bitfield
.disp16
7014 || i
.types
[this_operand
].bitfield
.disp32
))
7015 i
.types
[this_operand
]
7016 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7021 as_bad (_("`%s' is not a valid %s expression"),
7026 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7028 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7029 ? flag_code
== CODE_32BIT
7038 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7042 i386_att_operand (char *operand_string
)
7046 char *op_string
= operand_string
;
7048 if (is_space_char (*op_string
))
7051 /* We check for an absolute prefix (differentiating,
7052 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7053 if (*op_string
== ABSOLUTE_PREFIX
)
7056 if (is_space_char (*op_string
))
7058 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7061 /* Check if operand is a register. */
7062 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7064 i386_operand_type temp
;
7066 /* Check for a segment override by searching for ':' after a
7067 segment register. */
7069 if (is_space_char (*op_string
))
7071 if (*op_string
== ':'
7072 && (r
->reg_type
.bitfield
.sreg2
7073 || r
->reg_type
.bitfield
.sreg3
))
7078 i
.seg
[i
.mem_operands
] = &es
;
7081 i
.seg
[i
.mem_operands
] = &cs
;
7084 i
.seg
[i
.mem_operands
] = &ss
;
7087 i
.seg
[i
.mem_operands
] = &ds
;
7090 i
.seg
[i
.mem_operands
] = &fs
;
7093 i
.seg
[i
.mem_operands
] = &gs
;
7097 /* Skip the ':' and whitespace. */
7099 if (is_space_char (*op_string
))
7102 if (!is_digit_char (*op_string
)
7103 && !is_identifier_char (*op_string
)
7104 && *op_string
!= '('
7105 && *op_string
!= ABSOLUTE_PREFIX
)
7107 as_bad (_("bad memory operand `%s'"), op_string
);
7110 /* Handle case of %es:*foo. */
7111 if (*op_string
== ABSOLUTE_PREFIX
)
7114 if (is_space_char (*op_string
))
7116 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7118 goto do_memory_reference
;
7122 as_bad (_("junk `%s' after register"), op_string
);
7126 temp
.bitfield
.baseindex
= 0;
7127 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7129 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7130 i
.op
[this_operand
].regs
= r
;
7133 else if (*op_string
== REGISTER_PREFIX
)
7135 as_bad (_("bad register name `%s'"), op_string
);
7138 else if (*op_string
== IMMEDIATE_PREFIX
)
7141 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7143 as_bad (_("immediate operand illegal with absolute jump"));
7146 if (!i386_immediate (op_string
))
7149 else if (is_digit_char (*op_string
)
7150 || is_identifier_char (*op_string
)
7151 || *op_string
== '(')
7153 /* This is a memory reference of some sort. */
7156 /* Start and end of displacement string expression (if found). */
7157 char *displacement_string_start
;
7158 char *displacement_string_end
;
7160 do_memory_reference
:
7161 if ((i
.mem_operands
== 1
7162 && !current_templates
->start
->opcode_modifier
.isstring
)
7163 || i
.mem_operands
== 2)
7165 as_bad (_("too many memory references for `%s'"),
7166 current_templates
->start
->name
);
7170 /* Check for base index form. We detect the base index form by
7171 looking for an ')' at the end of the operand, searching
7172 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7174 base_string
= op_string
+ strlen (op_string
);
7177 if (is_space_char (*base_string
))
7180 /* If we only have a displacement, set-up for it to be parsed later. */
7181 displacement_string_start
= op_string
;
7182 displacement_string_end
= base_string
+ 1;
7184 if (*base_string
== ')')
7187 unsigned int parens_balanced
= 1;
7188 /* We've already checked that the number of left & right ()'s are
7189 equal, so this loop will not be infinite. */
7193 if (*base_string
== ')')
7195 if (*base_string
== '(')
7198 while (parens_balanced
);
7200 temp_string
= base_string
;
7202 /* Skip past '(' and whitespace. */
7204 if (is_space_char (*base_string
))
7207 if (*base_string
== ','
7208 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7211 displacement_string_end
= temp_string
;
7213 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7217 base_string
= end_op
;
7218 if (is_space_char (*base_string
))
7222 /* There may be an index reg or scale factor here. */
7223 if (*base_string
== ',')
7226 if (is_space_char (*base_string
))
7229 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7232 base_string
= end_op
;
7233 if (is_space_char (*base_string
))
7235 if (*base_string
== ',')
7238 if (is_space_char (*base_string
))
7241 else if (*base_string
!= ')')
7243 as_bad (_("expecting `,' or `)' "
7244 "after index register in `%s'"),
7249 else if (*base_string
== REGISTER_PREFIX
)
7251 as_bad (_("bad register name `%s'"), base_string
);
7255 /* Check for scale factor. */
7256 if (*base_string
!= ')')
7258 char *end_scale
= i386_scale (base_string
);
7263 base_string
= end_scale
;
7264 if (is_space_char (*base_string
))
7266 if (*base_string
!= ')')
7268 as_bad (_("expecting `)' "
7269 "after scale factor in `%s'"),
7274 else if (!i
.index_reg
)
7276 as_bad (_("expecting index register or scale factor "
7277 "after `,'; got '%c'"),
7282 else if (*base_string
!= ')')
7284 as_bad (_("expecting `,' or `)' "
7285 "after base register in `%s'"),
7290 else if (*base_string
== REGISTER_PREFIX
)
7292 as_bad (_("bad register name `%s'"), base_string
);
7297 /* If there's an expression beginning the operand, parse it,
7298 assuming displacement_string_start and
7299 displacement_string_end are meaningful. */
7300 if (displacement_string_start
!= displacement_string_end
)
7302 if (!i386_displacement (displacement_string_start
,
7303 displacement_string_end
))
7307 /* Special case for (%dx) while doing input/output op. */
7309 && operand_type_equal (&i
.base_reg
->reg_type
,
7310 ®16_inoutportreg
)
7312 && i
.log2_scale_factor
== 0
7313 && i
.seg
[i
.mem_operands
] == 0
7314 && !operand_type_check (i
.types
[this_operand
], disp
))
7316 i
.types
[this_operand
] = inoutportreg
;
7320 if (i386_index_check (operand_string
) == 0)
7322 i
.types
[this_operand
].bitfield
.mem
= 1;
7327 /* It's not a memory operand; argh! */
7328 as_bad (_("invalid char %s beginning operand %d `%s'"),
7329 output_invalid (*op_string
),
7334 return 1; /* Normal return. */
7337 /* md_estimate_size_before_relax()
7339 Called just before relax() for rs_machine_dependent frags. The x86
7340 assembler uses these frags to handle variable size jump
7343 Any symbol that is now undefined will not become defined.
7344 Return the correct fr_subtype in the frag.
7345 Return the initial "guess for variable size of frag" to caller.
7346 The guess is actually the growth beyond the fixed part. Whatever
7347 we do to grow the fixed or variable part contributes to our
7351 md_estimate_size_before_relax (fragP
, segment
)
7355 /* We've already got fragP->fr_subtype right; all we have to do is
7356 check for un-relaxable symbols. On an ELF system, we can't relax
7357 an externally visible symbol, because it may be overridden by a
7359 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7360 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7362 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7363 || S_IS_WEAK (fragP
->fr_symbol
)
7364 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7365 & BSF_GNU_INDIRECT_FUNCTION
))))
7367 #if defined (OBJ_COFF) && defined (TE_PE)
7368 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7369 && S_IS_WEAK (fragP
->fr_symbol
))
7373 /* Symbol is undefined in this segment, or we need to keep a
7374 reloc so that weak symbols can be overridden. */
7375 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7376 enum bfd_reloc_code_real reloc_type
;
7377 unsigned char *opcode
;
7380 if (fragP
->fr_var
!= NO_RELOC
)
7381 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7383 reloc_type
= BFD_RELOC_16_PCREL
;
7385 reloc_type
= BFD_RELOC_32_PCREL
;
7387 old_fr_fix
= fragP
->fr_fix
;
7388 opcode
= (unsigned char *) fragP
->fr_opcode
;
7390 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7393 /* Make jmp (0xeb) a (d)word displacement jump. */
7395 fragP
->fr_fix
+= size
;
7396 fix_new (fragP
, old_fr_fix
, size
,
7398 fragP
->fr_offset
, 1,
7404 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7406 /* Negate the condition, and branch past an
7407 unconditional jump. */
7410 /* Insert an unconditional jump. */
7412 /* We added two extra opcode bytes, and have a two byte
7414 fragP
->fr_fix
+= 2 + 2;
7415 fix_new (fragP
, old_fr_fix
+ 2, 2,
7417 fragP
->fr_offset
, 1,
7424 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7429 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7431 fragP
->fr_offset
, 1,
7433 fixP
->fx_signed
= 1;
7437 /* This changes the byte-displacement jump 0x7N
7438 to the (d)word-displacement jump 0x0f,0x8N. */
7439 opcode
[1] = opcode
[0] + 0x10;
7440 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7441 /* We've added an opcode byte. */
7442 fragP
->fr_fix
+= 1 + size
;
7443 fix_new (fragP
, old_fr_fix
+ 1, size
,
7445 fragP
->fr_offset
, 1,
7450 BAD_CASE (fragP
->fr_subtype
);
7454 return fragP
->fr_fix
- old_fr_fix
;
7457 /* Guess size depending on current relax state. Initially the relax
7458 state will correspond to a short jump and we return 1, because
7459 the variable part of the frag (the branch offset) is one byte
7460 long. However, we can relax a section more than once and in that
7461 case we must either set fr_subtype back to the unrelaxed state,
7462 or return the value for the appropriate branch. */
7463 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7466 /* Called after relax() is finished.
7468 In: Address of frag.
7469 fr_type == rs_machine_dependent.
7470 fr_subtype is what the address relaxed to.
7472 Out: Any fixSs and constants are set up.
7473 Caller will turn frag into a ".space 0". */
7476 md_convert_frag (abfd
, sec
, fragP
)
7477 bfd
*abfd ATTRIBUTE_UNUSED
;
7478 segT sec ATTRIBUTE_UNUSED
;
7481 unsigned char *opcode
;
7482 unsigned char *where_to_put_displacement
= NULL
;
7483 offsetT target_address
;
7484 offsetT opcode_address
;
7485 unsigned int extension
= 0;
7486 offsetT displacement_from_opcode_start
;
7488 opcode
= (unsigned char *) fragP
->fr_opcode
;
7490 /* Address we want to reach in file space. */
7491 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7493 /* Address opcode resides at in file space. */
7494 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7496 /* Displacement from opcode start to fill into instruction. */
7497 displacement_from_opcode_start
= target_address
- opcode_address
;
7499 if ((fragP
->fr_subtype
& BIG
) == 0)
7501 /* Don't have to change opcode. */
7502 extension
= 1; /* 1 opcode + 1 displacement */
7503 where_to_put_displacement
= &opcode
[1];
7507 if (no_cond_jump_promotion
7508 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7509 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7510 _("long jump required"));
7512 switch (fragP
->fr_subtype
)
7514 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7515 extension
= 4; /* 1 opcode + 4 displacement */
7517 where_to_put_displacement
= &opcode
[1];
7520 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7521 extension
= 2; /* 1 opcode + 2 displacement */
7523 where_to_put_displacement
= &opcode
[1];
7526 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7527 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7528 extension
= 5; /* 2 opcode + 4 displacement */
7529 opcode
[1] = opcode
[0] + 0x10;
7530 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7531 where_to_put_displacement
= &opcode
[2];
7534 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7535 extension
= 3; /* 2 opcode + 2 displacement */
7536 opcode
[1] = opcode
[0] + 0x10;
7537 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7538 where_to_put_displacement
= &opcode
[2];
7541 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7546 where_to_put_displacement
= &opcode
[3];
7550 BAD_CASE (fragP
->fr_subtype
);
7555 /* If size if less then four we are sure that the operand fits,
7556 but if it's 4, then it could be that the displacement is larger
7558 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7560 && ((addressT
) (displacement_from_opcode_start
- extension
7561 + ((addressT
) 1 << 31))
7562 > (((addressT
) 2 << 31) - 1)))
7564 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7565 _("jump target out of range"));
7566 /* Make us emit 0. */
7567 displacement_from_opcode_start
= extension
;
7569 /* Now put displacement after opcode. */
7570 md_number_to_chars ((char *) where_to_put_displacement
,
7571 (valueT
) (displacement_from_opcode_start
- extension
),
7572 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7573 fragP
->fr_fix
+= extension
;
7576 /* Apply a fixup (fixS) to segment data, once it has been determined
7577 by our caller that we have all the info we need to fix it up.
7579 On the 386, immediates, displacements, and data pointers are all in
7580 the same (little-endian) format, so we don't need to care about which
7584 md_apply_fix (fixP
, valP
, seg
)
7585 /* The fix we're to put in. */
7587 /* Pointer to the value of the bits. */
7589 /* Segment fix is from. */
7590 segT seg ATTRIBUTE_UNUSED
;
7592 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7593 valueT value
= *valP
;
7595 #if !defined (TE_Mach)
7598 switch (fixP
->fx_r_type
)
7604 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7607 case BFD_RELOC_X86_64_32S
:
7608 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7611 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7614 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7619 if (fixP
->fx_addsy
!= NULL
7620 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7621 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7622 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7623 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7624 && !use_rela_relocations
)
7626 /* This is a hack. There should be a better way to handle this.
7627 This covers for the fact that bfd_install_relocation will
7628 subtract the current location (for partial_inplace, PC relative
7629 relocations); see more below. */
7633 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7636 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7638 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7641 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7644 || (symbol_section_p (fixP
->fx_addsy
)
7645 && sym_seg
!= absolute_section
))
7646 && !generic_force_reloc (fixP
))
7648 /* Yes, we add the values in twice. This is because
7649 bfd_install_relocation subtracts them out again. I think
7650 bfd_install_relocation is broken, but I don't dare change
7652 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7656 #if defined (OBJ_COFF) && defined (TE_PE)
7657 /* For some reason, the PE format does not store a
7658 section address offset for a PC relative symbol. */
7659 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7660 || S_IS_WEAK (fixP
->fx_addsy
))
7661 value
+= md_pcrel_from (fixP
);
7664 #if defined (OBJ_COFF) && defined (TE_PE)
7665 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7667 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7671 /* Fix a few things - the dynamic linker expects certain values here,
7672 and we must not disappoint it. */
7673 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7674 if (IS_ELF
&& fixP
->fx_addsy
)
7675 switch (fixP
->fx_r_type
)
7677 case BFD_RELOC_386_PLT32
:
7678 case BFD_RELOC_X86_64_PLT32
:
7679 /* Make the jump instruction point to the address of the operand. At
7680 runtime we merely add the offset to the actual PLT entry. */
7684 case BFD_RELOC_386_TLS_GD
:
7685 case BFD_RELOC_386_TLS_LDM
:
7686 case BFD_RELOC_386_TLS_IE_32
:
7687 case BFD_RELOC_386_TLS_IE
:
7688 case BFD_RELOC_386_TLS_GOTIE
:
7689 case BFD_RELOC_386_TLS_GOTDESC
:
7690 case BFD_RELOC_X86_64_TLSGD
:
7691 case BFD_RELOC_X86_64_TLSLD
:
7692 case BFD_RELOC_X86_64_GOTTPOFF
:
7693 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7694 value
= 0; /* Fully resolved at runtime. No addend. */
7696 case BFD_RELOC_386_TLS_LE
:
7697 case BFD_RELOC_386_TLS_LDO_32
:
7698 case BFD_RELOC_386_TLS_LE_32
:
7699 case BFD_RELOC_X86_64_DTPOFF32
:
7700 case BFD_RELOC_X86_64_DTPOFF64
:
7701 case BFD_RELOC_X86_64_TPOFF32
:
7702 case BFD_RELOC_X86_64_TPOFF64
:
7703 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7706 case BFD_RELOC_386_TLS_DESC_CALL
:
7707 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7708 value
= 0; /* Fully resolved at runtime. No addend. */
7709 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7713 case BFD_RELOC_386_GOT32
:
7714 case BFD_RELOC_X86_64_GOT32
:
7715 value
= 0; /* Fully resolved at runtime. No addend. */
7718 case BFD_RELOC_VTABLE_INHERIT
:
7719 case BFD_RELOC_VTABLE_ENTRY
:
7726 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7728 #endif /* !defined (TE_Mach) */
7730 /* Are we finished with this relocation now? */
7731 if (fixP
->fx_addsy
== NULL
)
7733 #if defined (OBJ_COFF) && defined (TE_PE)
7734 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7737 /* Remember value for tc_gen_reloc. */
7738 fixP
->fx_addnumber
= value
;
7739 /* Clear out the frag for now. */
7743 else if (use_rela_relocations
)
7745 fixP
->fx_no_overflow
= 1;
7746 /* Remember value for tc_gen_reloc. */
7747 fixP
->fx_addnumber
= value
;
7751 md_number_to_chars (p
, value
, fixP
->fx_size
);
7755 md_atof (int type
, char *litP
, int *sizeP
)
7757 /* This outputs the LITTLENUMs in REVERSE order;
7758 in accord with the bigendian 386. */
7759 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7762 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7765 output_invalid (int c
)
7768 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7771 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7772 "(0x%x)", (unsigned char) c
);
7773 return output_invalid_buf
;
7776 /* REG_STRING starts *before* REGISTER_PREFIX. */
7778 static const reg_entry
*
7779 parse_real_register (char *reg_string
, char **end_op
)
7781 char *s
= reg_string
;
7783 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7786 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7787 if (*s
== REGISTER_PREFIX
)
7790 if (is_space_char (*s
))
7794 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7796 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7797 return (const reg_entry
*) NULL
;
7801 /* For naked regs, make sure that we are not dealing with an identifier.
7802 This prevents confusing an identifier like `eax_var' with register
7804 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7805 return (const reg_entry
*) NULL
;
7809 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7811 /* Handle floating point regs, allowing spaces in the (i) part. */
7812 if (r
== i386_regtab
/* %st is first entry of table */)
7814 if (is_space_char (*s
))
7819 if (is_space_char (*s
))
7821 if (*s
>= '0' && *s
<= '7')
7825 if (is_space_char (*s
))
7830 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7835 /* We have "%st(" then garbage. */
7836 return (const reg_entry
*) NULL
;
7840 if (r
== NULL
|| allow_pseudo_reg
)
7843 if (operand_type_all_zero (&r
->reg_type
))
7844 return (const reg_entry
*) NULL
;
7846 if ((r
->reg_type
.bitfield
.reg32
7847 || r
->reg_type
.bitfield
.sreg3
7848 || r
->reg_type
.bitfield
.control
7849 || r
->reg_type
.bitfield
.debug
7850 || r
->reg_type
.bitfield
.test
)
7851 && !cpu_arch_flags
.bitfield
.cpui386
)
7852 return (const reg_entry
*) NULL
;
7854 if (r
->reg_type
.bitfield
.floatreg
7855 && !cpu_arch_flags
.bitfield
.cpu8087
7856 && !cpu_arch_flags
.bitfield
.cpu287
7857 && !cpu_arch_flags
.bitfield
.cpu387
)
7858 return (const reg_entry
*) NULL
;
7860 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7861 return (const reg_entry
*) NULL
;
7863 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7864 return (const reg_entry
*) NULL
;
7866 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7867 return (const reg_entry
*) NULL
;
7869 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7870 if (!allow_index_reg
7871 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7872 return (const reg_entry
*) NULL
;
7874 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7875 || r
->reg_type
.bitfield
.reg64
)
7876 && (!cpu_arch_flags
.bitfield
.cpulm
7877 || !operand_type_equal (&r
->reg_type
, &control
))
7878 && flag_code
!= CODE_64BIT
)
7879 return (const reg_entry
*) NULL
;
7881 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7882 return (const reg_entry
*) NULL
;
7887 /* REG_STRING starts *before* REGISTER_PREFIX. */
7889 static const reg_entry
*
7890 parse_register (char *reg_string
, char **end_op
)
7894 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7895 r
= parse_real_register (reg_string
, end_op
);
7900 char *save
= input_line_pointer
;
7904 input_line_pointer
= reg_string
;
7905 c
= get_symbol_end ();
7906 symbolP
= symbol_find (reg_string
);
7907 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7909 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7911 know (e
->X_op
== O_register
);
7912 know (e
->X_add_number
>= 0
7913 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7914 r
= i386_regtab
+ e
->X_add_number
;
7915 *end_op
= input_line_pointer
;
7917 *input_line_pointer
= c
;
7918 input_line_pointer
= save
;
7924 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7927 char *end
= input_line_pointer
;
7930 r
= parse_register (name
, &input_line_pointer
);
7931 if (r
&& end
<= input_line_pointer
)
7933 *nextcharP
= *input_line_pointer
;
7934 *input_line_pointer
= 0;
7935 e
->X_op
= O_register
;
7936 e
->X_add_number
= r
- i386_regtab
;
7939 input_line_pointer
= end
;
7941 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7945 md_operand (expressionS
*e
)
7950 switch (*input_line_pointer
)
7952 case REGISTER_PREFIX
:
7953 r
= parse_real_register (input_line_pointer
, &end
);
7956 e
->X_op
= O_register
;
7957 e
->X_add_number
= r
- i386_regtab
;
7958 input_line_pointer
= end
;
7963 gas_assert (intel_syntax
);
7964 end
= input_line_pointer
++;
7966 if (*input_line_pointer
== ']')
7968 ++input_line_pointer
;
7969 e
->X_op_symbol
= make_expr_symbol (e
);
7970 e
->X_add_symbol
= NULL
;
7971 e
->X_add_number
= 0;
7977 input_line_pointer
= end
;
7984 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7985 const char *md_shortopts
= "kVQ:sqn";
7987 const char *md_shortopts
= "qn";
7990 #define OPTION_32 (OPTION_MD_BASE + 0)
7991 #define OPTION_64 (OPTION_MD_BASE + 1)
7992 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7993 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7994 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7995 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7996 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7997 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7998 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7999 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8000 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8001 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8002 #define OPTION_MAVXSCALAR (OPTION_MSSE_CHECK + 11)
8004 struct option md_longopts
[] =
8006 {"32", no_argument
, NULL
, OPTION_32
},
8007 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8008 || defined (TE_PE) || defined (TE_PEP))
8009 {"64", no_argument
, NULL
, OPTION_64
},
8011 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8012 {"march", required_argument
, NULL
, OPTION_MARCH
},
8013 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8014 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8015 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8016 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8017 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8018 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8019 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8020 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8021 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8022 {NULL
, no_argument
, NULL
, 0}
8024 size_t md_longopts_size
= sizeof (md_longopts
);
8027 md_parse_option (int c
, char *arg
)
8035 optimize_align_code
= 0;
8042 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8043 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8044 should be emitted or not. FIXME: Not implemented. */
8048 /* -V: SVR4 argument to print version ID. */
8050 print_version_id ();
8053 /* -k: Ignore for FreeBSD compatibility. */
8058 /* -s: On i386 Solaris, this tells the native assembler to use
8059 .stab instead of .stab.excl. We always use .stab anyhow. */
8062 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8063 || defined (TE_PE) || defined (TE_PEP))
8066 const char **list
, **l
;
8068 list
= bfd_target_list ();
8069 for (l
= list
; *l
!= NULL
; l
++)
8070 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8071 || strcmp (*l
, "coff-x86-64") == 0
8072 || strcmp (*l
, "pe-x86-64") == 0
8073 || strcmp (*l
, "pei-x86-64") == 0)
8075 default_arch
= "x86_64";
8079 as_fatal (_("No compiled in support for x86_64"));
8086 default_arch
= "i386";
8090 #ifdef SVR4_COMMENT_CHARS
8095 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8097 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8101 i386_comment_chars
= n
;
8107 arch
= xstrdup (arg
);
8111 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8112 next
= strchr (arch
, '+');
8115 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8117 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8120 cpu_arch_name
= cpu_arch
[j
].name
;
8121 cpu_sub_arch_name
= NULL
;
8122 cpu_arch_flags
= cpu_arch
[j
].flags
;
8123 cpu_arch_isa
= cpu_arch
[j
].type
;
8124 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8125 if (!cpu_arch_tune_set
)
8127 cpu_arch_tune
= cpu_arch_isa
;
8128 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8132 else if (*cpu_arch
[j
].name
== '.'
8133 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8135 /* ISA entension. */
8136 i386_cpu_flags flags
;
8138 if (strncmp (arch
, "no", 2))
8139 flags
= cpu_flags_or (cpu_arch_flags
,
8142 flags
= cpu_flags_and_not (cpu_arch_flags
,
8144 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8146 if (cpu_sub_arch_name
)
8148 char *name
= cpu_sub_arch_name
;
8149 cpu_sub_arch_name
= concat (name
,
8151 (const char *) NULL
);
8155 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8156 cpu_arch_flags
= flags
;
8162 if (j
>= ARRAY_SIZE (cpu_arch
))
8163 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8167 while (next
!= NULL
);
8172 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8173 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8175 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8177 cpu_arch_tune_set
= 1;
8178 cpu_arch_tune
= cpu_arch
[j
].type
;
8179 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8183 if (j
>= ARRAY_SIZE (cpu_arch
))
8184 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8187 case OPTION_MMNEMONIC
:
8188 if (strcasecmp (arg
, "att") == 0)
8190 else if (strcasecmp (arg
, "intel") == 0)
8193 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8196 case OPTION_MSYNTAX
:
8197 if (strcasecmp (arg
, "att") == 0)
8199 else if (strcasecmp (arg
, "intel") == 0)
8202 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8205 case OPTION_MINDEX_REG
:
8206 allow_index_reg
= 1;
8209 case OPTION_MNAKED_REG
:
8210 allow_naked_reg
= 1;
8213 case OPTION_MOLD_GCC
:
8217 case OPTION_MSSE2AVX
:
8221 case OPTION_MSSE_CHECK
:
8222 if (strcasecmp (arg
, "error") == 0)
8223 sse_check
= sse_check_error
;
8224 else if (strcasecmp (arg
, "warning") == 0)
8225 sse_check
= sse_check_warning
;
8226 else if (strcasecmp (arg
, "none") == 0)
8227 sse_check
= sse_check_none
;
8229 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8232 case OPTION_MAVXSCALAR
:
8233 if (strcasecmp (arg
, "128") == 0)
8235 else if (strcasecmp (arg
, "256") == 0)
8238 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8247 #define MESSAGE_TEMPLATE \
8251 show_arch (FILE *stream
, int ext
)
8253 static char message
[] = MESSAGE_TEMPLATE
;
8254 char *start
= message
+ 27;
8256 int size
= sizeof (MESSAGE_TEMPLATE
);
8263 left
= size
- (start
- message
);
8264 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8266 /* Should it be skipped? */
8267 if (cpu_arch
[j
].skip
)
8270 name
= cpu_arch
[j
].name
;
8271 len
= cpu_arch
[j
].len
;
8274 /* It is an extension. Skip if we aren't asked to show it. */
8285 /* It is an processor. Skip if we show only extension. */
8289 /* Reserve 2 spaces for ", " or ",\0" */
8292 /* Check if there is any room. */
8300 p
= mempcpy (p
, name
, len
);
8304 /* Output the current message now and start a new one. */
8307 fprintf (stream
, "%s\n", message
);
8309 left
= size
- (start
- message
) - len
- 2;
8311 gas_assert (left
>= 0);
8313 p
= mempcpy (p
, name
, len
);
8318 fprintf (stream
, "%s\n", message
);
8322 md_show_usage (FILE *stream
)
8324 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8325 fprintf (stream
, _("\
8327 -V print assembler version number\n\
8330 fprintf (stream
, _("\
8331 -n Do not optimize code alignment\n\
8332 -q quieten some warnings\n"));
8333 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8334 fprintf (stream
, _("\
8337 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8338 || defined (TE_PE) || defined (TE_PEP))
8339 fprintf (stream
, _("\
8340 --32/--64 generate 32bit/64bit code\n"));
8342 #ifdef SVR4_COMMENT_CHARS
8343 fprintf (stream
, _("\
8344 --divide do not treat `/' as a comment character\n"));
8346 fprintf (stream
, _("\
8347 --divide ignored\n"));
8349 fprintf (stream
, _("\
8350 -march=CPU[,+EXTENSION...]\n\
8351 generate code for CPU and EXTENSION, CPU is one of:\n"));
8352 show_arch (stream
, 0);
8353 fprintf (stream
, _("\
8354 EXTENSION is combination of:\n"));
8355 show_arch (stream
, 1);
8356 fprintf (stream
, _("\
8357 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8358 show_arch (stream
, 0);
8359 fprintf (stream
, _("\
8360 -msse2avx encode SSE instructions with VEX prefix\n"));
8361 fprintf (stream
, _("\
8362 -msse-check=[none|error|warning]\n\
8363 check SSE instructions\n"));
8364 fprintf (stream
, _("\
8365 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8367 fprintf (stream
, _("\
8368 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8369 fprintf (stream
, _("\
8370 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8371 fprintf (stream
, _("\
8372 -mindex-reg support pseudo index registers\n"));
8373 fprintf (stream
, _("\
8374 -mnaked-reg don't require `%%' prefix for registers\n"));
8375 fprintf (stream
, _("\
8376 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8379 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8380 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8381 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8383 /* Pick the target format to use. */
8386 i386_target_format (void)
8388 if (!strcmp (default_arch
, "x86_64"))
8390 set_code_flag (CODE_64BIT
);
8391 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8393 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8394 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8395 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8396 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8397 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8398 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8399 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8400 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8401 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8402 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8403 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8405 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8407 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8408 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8409 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8410 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8411 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8412 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8413 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8414 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8415 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8416 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8419 else if (!strcmp (default_arch
, "i386"))
8421 set_code_flag (CODE_32BIT
);
8422 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8424 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8425 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8426 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8428 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8430 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8431 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8432 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8436 as_fatal (_("Unknown architecture"));
8437 switch (OUTPUT_FLAVOR
)
8439 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8440 case bfd_target_aout_flavour
:
8441 return AOUT_TARGET_FORMAT
;
8443 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8444 # if defined (TE_PE) || defined (TE_PEP)
8445 case bfd_target_coff_flavour
:
8446 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8447 # elif defined (TE_GO32)
8448 case bfd_target_coff_flavour
:
8451 case bfd_target_coff_flavour
:
8455 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8456 case bfd_target_elf_flavour
:
8458 if (flag_code
== CODE_64BIT
)
8461 use_rela_relocations
= 1;
8463 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8465 if (flag_code
!= CODE_64BIT
)
8466 as_fatal (_("Intel L1OM is 64bit only"));
8467 return ELF_TARGET_L1OM_FORMAT
;
8470 return (flag_code
== CODE_64BIT
8471 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8474 #if defined (OBJ_MACH_O)
8475 case bfd_target_mach_o_flavour
:
8476 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8484 #endif /* OBJ_MAYBE_ more than one */
8486 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8488 i386_elf_emit_arch_note (void)
8490 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8493 asection
*seg
= now_seg
;
8494 subsegT subseg
= now_subseg
;
8495 Elf_Internal_Note i_note
;
8496 Elf_External_Note e_note
;
8497 asection
*note_secp
;
8500 /* Create the .note section. */
8501 note_secp
= subseg_new (".note", 0);
8502 bfd_set_section_flags (stdoutput
,
8504 SEC_HAS_CONTENTS
| SEC_READONLY
);
8506 /* Process the arch string. */
8507 len
= strlen (cpu_arch_name
);
8509 i_note
.namesz
= len
+ 1;
8511 i_note
.type
= NT_ARCH
;
8512 p
= frag_more (sizeof (e_note
.namesz
));
8513 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8514 p
= frag_more (sizeof (e_note
.descsz
));
8515 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8516 p
= frag_more (sizeof (e_note
.type
));
8517 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8518 p
= frag_more (len
+ 1);
8519 strcpy (p
, cpu_arch_name
);
8521 frag_align (2, 0, 0);
8523 subseg_set (seg
, subseg
);
8529 md_undefined_symbol (name
)
8532 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8533 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8534 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8535 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8539 if (symbol_find (name
))
8540 as_bad (_("GOT already in symbol table"));
8541 GOT_symbol
= symbol_new (name
, undefined_section
,
8542 (valueT
) 0, &zero_address_frag
);
8549 /* Round up a section size to the appropriate boundary. */
8552 md_section_align (segment
, size
)
8553 segT segment ATTRIBUTE_UNUSED
;
8556 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8557 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8559 /* For a.out, force the section size to be aligned. If we don't do
8560 this, BFD will align it for us, but it will not write out the
8561 final bytes of the section. This may be a bug in BFD, but it is
8562 easier to fix it here since that is how the other a.out targets
8566 align
= bfd_get_section_alignment (stdoutput
, segment
);
8567 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8574 /* On the i386, PC-relative offsets are relative to the start of the
8575 next instruction. That is, the address of the offset, plus its
8576 size, since the offset is always the last part of the insn. */
8579 md_pcrel_from (fixS
*fixP
)
8581 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8587 s_bss (int ignore ATTRIBUTE_UNUSED
)
8591 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8593 obj_elf_section_change_hook ();
8595 temp
= get_absolute_expression ();
8596 subseg_set (bss_section
, (subsegT
) temp
);
8597 demand_empty_rest_of_line ();
8603 i386_validate_fix (fixS
*fixp
)
8605 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8607 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8611 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8616 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8618 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8625 tc_gen_reloc (section
, fixp
)
8626 asection
*section ATTRIBUTE_UNUSED
;
8630 bfd_reloc_code_real_type code
;
8632 switch (fixp
->fx_r_type
)
8634 case BFD_RELOC_X86_64_PLT32
:
8635 case BFD_RELOC_X86_64_GOT32
:
8636 case BFD_RELOC_X86_64_GOTPCREL
:
8637 case BFD_RELOC_386_PLT32
:
8638 case BFD_RELOC_386_GOT32
:
8639 case BFD_RELOC_386_GOTOFF
:
8640 case BFD_RELOC_386_GOTPC
:
8641 case BFD_RELOC_386_TLS_GD
:
8642 case BFD_RELOC_386_TLS_LDM
:
8643 case BFD_RELOC_386_TLS_LDO_32
:
8644 case BFD_RELOC_386_TLS_IE_32
:
8645 case BFD_RELOC_386_TLS_IE
:
8646 case BFD_RELOC_386_TLS_GOTIE
:
8647 case BFD_RELOC_386_TLS_LE_32
:
8648 case BFD_RELOC_386_TLS_LE
:
8649 case BFD_RELOC_386_TLS_GOTDESC
:
8650 case BFD_RELOC_386_TLS_DESC_CALL
:
8651 case BFD_RELOC_X86_64_TLSGD
:
8652 case BFD_RELOC_X86_64_TLSLD
:
8653 case BFD_RELOC_X86_64_DTPOFF32
:
8654 case BFD_RELOC_X86_64_DTPOFF64
:
8655 case BFD_RELOC_X86_64_GOTTPOFF
:
8656 case BFD_RELOC_X86_64_TPOFF32
:
8657 case BFD_RELOC_X86_64_TPOFF64
:
8658 case BFD_RELOC_X86_64_GOTOFF64
:
8659 case BFD_RELOC_X86_64_GOTPC32
:
8660 case BFD_RELOC_X86_64_GOT64
:
8661 case BFD_RELOC_X86_64_GOTPCREL64
:
8662 case BFD_RELOC_X86_64_GOTPC64
:
8663 case BFD_RELOC_X86_64_GOTPLT64
:
8664 case BFD_RELOC_X86_64_PLTOFF64
:
8665 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8666 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8668 case BFD_RELOC_VTABLE_ENTRY
:
8669 case BFD_RELOC_VTABLE_INHERIT
:
8671 case BFD_RELOC_32_SECREL
:
8673 code
= fixp
->fx_r_type
;
8675 case BFD_RELOC_X86_64_32S
:
8676 if (!fixp
->fx_pcrel
)
8678 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8679 code
= fixp
->fx_r_type
;
8685 switch (fixp
->fx_size
)
8688 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8689 _("can not do %d byte pc-relative relocation"),
8691 code
= BFD_RELOC_32_PCREL
;
8693 case 1: code
= BFD_RELOC_8_PCREL
; break;
8694 case 2: code
= BFD_RELOC_16_PCREL
; break;
8695 case 4: code
= BFD_RELOC_32_PCREL
; break;
8697 case 8: code
= BFD_RELOC_64_PCREL
; break;
8703 switch (fixp
->fx_size
)
8706 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8707 _("can not do %d byte relocation"),
8709 code
= BFD_RELOC_32
;
8711 case 1: code
= BFD_RELOC_8
; break;
8712 case 2: code
= BFD_RELOC_16
; break;
8713 case 4: code
= BFD_RELOC_32
; break;
8715 case 8: code
= BFD_RELOC_64
; break;
8722 if ((code
== BFD_RELOC_32
8723 || code
== BFD_RELOC_32_PCREL
8724 || code
== BFD_RELOC_X86_64_32S
)
8726 && fixp
->fx_addsy
== GOT_symbol
)
8729 code
= BFD_RELOC_386_GOTPC
;
8731 code
= BFD_RELOC_X86_64_GOTPC32
;
8733 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8735 && fixp
->fx_addsy
== GOT_symbol
)
8737 code
= BFD_RELOC_X86_64_GOTPC64
;
8740 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8741 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8742 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8744 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8746 if (!use_rela_relocations
)
8748 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8749 vtable entry to be used in the relocation's section offset. */
8750 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8751 rel
->address
= fixp
->fx_offset
;
8752 #if defined (OBJ_COFF) && defined (TE_PE)
8753 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8754 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8759 /* Use the rela in 64bit mode. */
8762 if (!fixp
->fx_pcrel
)
8763 rel
->addend
= fixp
->fx_offset
;
8767 case BFD_RELOC_X86_64_PLT32
:
8768 case BFD_RELOC_X86_64_GOT32
:
8769 case BFD_RELOC_X86_64_GOTPCREL
:
8770 case BFD_RELOC_X86_64_TLSGD
:
8771 case BFD_RELOC_X86_64_TLSLD
:
8772 case BFD_RELOC_X86_64_GOTTPOFF
:
8773 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8774 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8775 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8778 rel
->addend
= (section
->vma
8780 + fixp
->fx_addnumber
8781 + md_pcrel_from (fixp
));
8786 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8787 if (rel
->howto
== NULL
)
8789 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8790 _("cannot represent relocation type %s"),
8791 bfd_get_reloc_code_name (code
));
8792 /* Set howto to a garbage value so that we can keep going. */
8793 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8794 gas_assert (rel
->howto
!= NULL
);
8800 #include "tc-i386-intel.c"
8803 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8805 int saved_naked_reg
;
8806 char saved_register_dot
;
8808 saved_naked_reg
= allow_naked_reg
;
8809 allow_naked_reg
= 1;
8810 saved_register_dot
= register_chars
['.'];
8811 register_chars
['.'] = '.';
8812 allow_pseudo_reg
= 1;
8813 expression_and_evaluate (exp
);
8814 allow_pseudo_reg
= 0;
8815 register_chars
['.'] = saved_register_dot
;
8816 allow_naked_reg
= saved_naked_reg
;
8818 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8820 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8822 exp
->X_op
= O_constant
;
8823 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8824 .dw2_regnum
[flag_code
>> 1];
8827 exp
->X_op
= O_illegal
;
8832 tc_x86_frame_initial_instructions (void)
8834 static unsigned int sp_regno
[2];
8836 if (!sp_regno
[flag_code
>> 1])
8838 char *saved_input
= input_line_pointer
;
8839 char sp
[][4] = {"esp", "rsp"};
8842 input_line_pointer
= sp
[flag_code
>> 1];
8843 tc_x86_parse_to_dw2regnum (&exp
);
8844 gas_assert (exp
.X_op
== O_constant
);
8845 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8846 input_line_pointer
= saved_input
;
8849 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8850 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8854 i386_elf_section_type (const char *str
, size_t len
)
8856 if (flag_code
== CODE_64BIT
8857 && len
== sizeof ("unwind") - 1
8858 && strncmp (str
, "unwind", 6) == 0)
8859 return SHT_X86_64_UNWIND
;
8866 i386_solaris_fix_up_eh_frame (segT sec
)
8868 if (flag_code
== CODE_64BIT
)
8869 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8875 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8879 exp
.X_op
= O_secrel
;
8880 exp
.X_add_symbol
= symbol
;
8881 exp
.X_add_number
= 0;
8882 emit_expr (&exp
, size
);
8886 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8887 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8890 x86_64_section_letter (int letter
, char **ptr_msg
)
8892 if (flag_code
== CODE_64BIT
)
8895 return SHF_X86_64_LARGE
;
8897 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8900 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8905 x86_64_section_word (char *str
, size_t len
)
8907 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8908 return SHF_X86_64_LARGE
;
8914 handle_large_common (int small ATTRIBUTE_UNUSED
)
8916 if (flag_code
!= CODE_64BIT
)
8918 s_comm_internal (0, elf_common_parse
);
8919 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8923 static segT lbss_section
;
8924 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8925 asection
*saved_bss_section
= bss_section
;
8927 if (lbss_section
== NULL
)
8929 flagword applicable
;
8931 subsegT subseg
= now_subseg
;
8933 /* The .lbss section is for local .largecomm symbols. */
8934 lbss_section
= subseg_new (".lbss", 0);
8935 applicable
= bfd_applicable_section_flags (stdoutput
);
8936 bfd_set_section_flags (stdoutput
, lbss_section
,
8937 applicable
& SEC_ALLOC
);
8938 seg_info (lbss_section
)->bss
= 1;
8940 subseg_set (seg
, subseg
);
8943 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8944 bss_section
= lbss_section
;
8946 s_comm_internal (0, elf_common_parse
);
8948 elf_com_section_ptr
= saved_com_section_ptr
;
8949 bss_section
= saved_bss_section
;
8952 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */