1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
62 REP_PREFIX, LOCK_PREFIX. */
69 #define REX_PREFIX 6 /* must come last. */
70 #define MAX_PREFIXES 7 /* max prefixes per opcode */
72 /* we define the syntax here (modulo base,index,scale syntax) */
73 #define REGISTER_PREFIX '%'
74 #define IMMEDIATE_PREFIX '$'
75 #define ABSOLUTE_PREFIX '*'
77 /* these are the instruction mnemonic suffixes in AT&T syntax or
78 memory operand size in Intel syntax. */
79 #define WORD_MNEM_SUFFIX 'w'
80 #define BYTE_MNEM_SUFFIX 'b'
81 #define SHORT_MNEM_SUFFIX 's'
82 #define LONG_MNEM_SUFFIX 'l'
83 #define QWORD_MNEM_SUFFIX 'q'
84 #define XMMWORD_MNEM_SUFFIX 'x'
85 #define YMMWORD_MNEM_SUFFIX 'y'
86 /* Intel Syntax. Use a non-ascii letter since since it never appears
88 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
90 #define END_OF_INSN '\0'
93 'templates' is for grouping together 'template' structures for opcodes
94 of the same name. This is only used for storing the insns in the grand
95 ole hash table of insns.
96 The templates themselves start at START and range up to (but not including)
101 const insn_template
*start
;
102 const insn_template
*end
;
106 /* 386 operand encoding bytes: see 386 book for details of this. */
109 unsigned int regmem
; /* codes register or memory operand */
110 unsigned int reg
; /* codes register operand (or extended opcode) */
111 unsigned int mode
; /* how to interpret regmem & reg */
115 /* x86-64 extension prefix. */
116 typedef int rex_byte
;
118 /* 386 opcode byte to code indirect addressing. */
127 /* x86 arch names, types and features */
130 const char *name
; /* arch name */
131 unsigned int len
; /* arch string length */
132 enum processor_type type
; /* arch type */
133 i386_cpu_flags flags
; /* cpu feature flags */
134 unsigned int skip
; /* show_arch should skip this. */
138 static void set_code_flag (int);
139 static void set_16bit_gcc_code_flag (int);
140 static void set_intel_syntax (int);
141 static void set_intel_mnemonic (int);
142 static void set_allow_index_reg (int);
143 static void set_sse_check (int);
144 static void set_cpu_arch (int);
146 static void pe_directive_secrel (int);
148 static void signed_cons (int);
149 static char *output_invalid (int c
);
150 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
152 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
154 static int i386_att_operand (char *);
155 static int i386_intel_operand (char *, int);
156 static int i386_intel_simplify (expressionS
*);
157 static int i386_intel_parse_name (const char *, expressionS
*);
158 static const reg_entry
*parse_register (char *, char **);
159 static char *parse_insn (char *, char *);
160 static char *parse_operands (char *, const char *);
161 static void swap_operands (void);
162 static void swap_2_operands (int, int);
163 static void optimize_imm (void);
164 static void optimize_disp (void);
165 static const insn_template
*match_template (void);
166 static int check_string (void);
167 static int process_suffix (void);
168 static int check_byte_reg (void);
169 static int check_long_reg (void);
170 static int check_qword_reg (void);
171 static int check_word_reg (void);
172 static int finalize_imm (void);
173 static int process_operands (void);
174 static const seg_entry
*build_modrm_byte (void);
175 static void output_insn (void);
176 static void output_imm (fragS
*, offsetT
);
177 static void output_disp (fragS
*, offsetT
);
179 static void s_bss (int);
181 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
182 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
185 static const char *default_arch
= DEFAULT_ARCH
;
190 /* VEX prefix is either 2 byte or 3 byte. */
191 unsigned char bytes
[3];
193 /* Destination or source register specifier. */
194 const reg_entry
*register_specifier
;
197 /* 'md_assemble ()' gathers together information and puts it into a
204 const reg_entry
*regs
;
209 operand_size_mismatch
,
210 operand_type_mismatch
,
211 register_type_mismatch
,
212 number_of_operands_mismatch
,
213 invalid_instruction_suffix
,
216 unsupported_with_intel_mnemonic
,
223 /* TM holds the template for the insn were currently assembling. */
226 /* SUFFIX holds the instruction size suffix for byte, word, dword
227 or qword, if given. */
230 /* OPERANDS gives the number of given operands. */
231 unsigned int operands
;
233 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
234 of given register, displacement, memory operands and immediate
236 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
238 /* TYPES [i] is the type (see above #defines) which tells us how to
239 use OP[i] for the corresponding operand. */
240 i386_operand_type types
[MAX_OPERANDS
];
242 /* Displacement expression, immediate expression, or register for each
244 union i386_op op
[MAX_OPERANDS
];
246 /* Flags for operands. */
247 unsigned int flags
[MAX_OPERANDS
];
248 #define Operand_PCrel 1
250 /* Relocation type for operand */
251 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
253 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
254 the base index byte below. */
255 const reg_entry
*base_reg
;
256 const reg_entry
*index_reg
;
257 unsigned int log2_scale_factor
;
259 /* SEG gives the seg_entries of this insn. They are zero unless
260 explicit segment overrides are given. */
261 const seg_entry
*seg
[2];
263 /* PREFIX holds all the given prefix opcodes (usually null).
264 PREFIXES is the number of prefix opcodes. */
265 unsigned int prefixes
;
266 unsigned char prefix
[MAX_PREFIXES
];
268 /* RM and SIB are the modrm byte and the sib byte where the
269 addressing modes of this insn are encoded. */
275 /* Swap operand in encoding. */
276 unsigned int swap_operand
;
279 enum i386_error error
;
282 typedef struct _i386_insn i386_insn
;
284 /* List of chars besides those in app.c:symbol_chars that can start an
285 operand. Used to prevent the scrubber eating vital white-space. */
286 const char extra_symbol_chars
[] = "*%-(["
295 #if (defined (TE_I386AIX) \
296 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
297 && !defined (TE_GNU) \
298 && !defined (TE_LINUX) \
299 && !defined (TE_NETWARE) \
300 && !defined (TE_FreeBSD) \
301 && !defined (TE_NetBSD)))
302 /* This array holds the chars that always start a comment. If the
303 pre-processor is disabled, these aren't very useful. The option
304 --divide will remove '/' from this list. */
305 const char *i386_comment_chars
= "#/";
306 #define SVR4_COMMENT_CHARS 1
307 #define PREFIX_SEPARATOR '\\'
310 const char *i386_comment_chars
= "#";
311 #define PREFIX_SEPARATOR '/'
314 /* This array holds the chars that only start a comment at the beginning of
315 a line. If the line seems to have the form '# 123 filename'
316 .line and .file directives will appear in the pre-processed output.
317 Note that input_file.c hand checks for '#' at the beginning of the
318 first line of the input file. This is because the compiler outputs
319 #NO_APP at the beginning of its output.
320 Also note that comments started like this one will always work if
321 '/' isn't otherwise defined. */
322 const char line_comment_chars
[] = "#/";
324 const char line_separator_chars
[] = ";";
326 /* Chars that can be used to separate mant from exp in floating point
328 const char EXP_CHARS
[] = "eE";
330 /* Chars that mean this number is a floating point constant
333 const char FLT_CHARS
[] = "fFdDxX";
335 /* Tables for lexical analysis. */
336 static char mnemonic_chars
[256];
337 static char register_chars
[256];
338 static char operand_chars
[256];
339 static char identifier_chars
[256];
340 static char digit_chars
[256];
342 /* Lexical macros. */
343 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
344 #define is_operand_char(x) (operand_chars[(unsigned char) x])
345 #define is_register_char(x) (register_chars[(unsigned char) x])
346 #define is_space_char(x) ((x) == ' ')
347 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
348 #define is_digit_char(x) (digit_chars[(unsigned char) x])
350 /* All non-digit non-letter characters that may occur in an operand. */
351 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
353 /* md_assemble() always leaves the strings it's passed unaltered. To
354 effect this we maintain a stack of saved characters that we've smashed
355 with '\0's (indicating end of strings for various sub-fields of the
356 assembler instruction). */
357 static char save_stack
[32];
358 static char *save_stack_p
;
359 #define END_STRING_AND_SAVE(s) \
360 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
361 #define RESTORE_END_STRING(s) \
362 do { *(s) = *--save_stack_p; } while (0)
364 /* The instruction we're assembling. */
367 /* Possible templates for current insn. */
368 static const templates
*current_templates
;
370 /* Per instruction expressionS buffers: max displacements & immediates. */
371 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
372 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
374 /* Current operand we are working on. */
375 static int this_operand
= -1;
377 /* We support four different modes. FLAG_CODE variable is used to distinguish
385 static enum flag_code flag_code
;
386 static unsigned int object_64bit
;
387 static int use_rela_relocations
= 0;
389 /* The names used to print error messages. */
390 static const char *flag_code_names
[] =
397 /* 1 for intel syntax,
399 static int intel_syntax
= 0;
401 /* 1 for intel mnemonic,
402 0 if att mnemonic. */
403 static int intel_mnemonic
= !SYSV386_COMPAT
;
405 /* 1 if support old (<= 2.8.1) versions of gcc. */
406 static int old_gcc
= OLDGCC_COMPAT
;
408 /* 1 if pseudo registers are permitted. */
409 static int allow_pseudo_reg
= 0;
411 /* 1 if register prefix % not required. */
412 static int allow_naked_reg
= 0;
414 /* 1 if pseudo index register, eiz/riz, is allowed . */
415 static int allow_index_reg
= 0;
425 /* Register prefix used for error message. */
426 static const char *register_prefix
= "%";
428 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
429 leave, push, and pop instructions so that gcc has the same stack
430 frame as in 32 bit mode. */
431 static char stackop_size
= '\0';
433 /* Non-zero to optimize code alignment. */
434 int optimize_align_code
= 1;
436 /* Non-zero to quieten some warnings. */
437 static int quiet_warnings
= 0;
440 static const char *cpu_arch_name
= NULL
;
441 static char *cpu_sub_arch_name
= NULL
;
443 /* CPU feature flags. */
444 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
446 /* If we have selected a cpu we are generating instructions for. */
447 static int cpu_arch_tune_set
= 0;
449 /* Cpu we are generating instructions for. */
450 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
452 /* CPU feature flags of cpu we are generating instructions for. */
453 static i386_cpu_flags cpu_arch_tune_flags
;
455 /* CPU instruction set architecture used. */
456 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
458 /* CPU feature flags of instruction set architecture used. */
459 i386_cpu_flags cpu_arch_isa_flags
;
461 /* If set, conditional jumps are not automatically promoted to handle
462 larger than a byte offset. */
463 static unsigned int no_cond_jump_promotion
= 0;
465 /* Encode SSE instructions with VEX prefix. */
466 static unsigned int sse2avx
;
468 /* Encode scalar AVX instructions with specific vector length. */
475 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
476 static symbolS
*GOT_symbol
;
478 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
479 unsigned int x86_dwarf2_return_column
;
481 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
482 int x86_cie_data_alignment
;
484 /* Interface to relax_segment.
485 There are 3 major relax states for 386 jump insns because the
486 different types of jumps add different sizes to frags when we're
487 figuring out what sort of jump to choose to reach a given label. */
490 #define UNCOND_JUMP 0
492 #define COND_JUMP86 2
497 #define SMALL16 (SMALL | CODE16)
499 #define BIG16 (BIG | CODE16)
503 #define INLINE __inline__
509 #define ENCODE_RELAX_STATE(type, size) \
510 ((relax_substateT) (((type) << 2) | (size)))
511 #define TYPE_FROM_RELAX_STATE(s) \
513 #define DISP_SIZE_FROM_RELAX_STATE(s) \
514 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
516 /* This table is used by relax_frag to promote short jumps to long
517 ones where necessary. SMALL (short) jumps may be promoted to BIG
518 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
519 don't allow a short jump in a 32 bit code segment to be promoted to
520 a 16 bit offset jump because it's slower (requires data size
521 prefix), and doesn't work, unless the destination is in the bottom
522 64k of the code segment (The top 16 bits of eip are zeroed). */
524 const relax_typeS md_relax_table
[] =
527 1) most positive reach of this state,
528 2) most negative reach of this state,
529 3) how many bytes this mode will have in the variable part of the frag
530 4) which index into the table to try if we can't fit into this one. */
532 /* UNCOND_JUMP states. */
533 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
534 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
535 /* dword jmp adds 4 bytes to frag:
536 0 extra opcode bytes, 4 displacement bytes. */
538 /* word jmp adds 2 byte2 to frag:
539 0 extra opcode bytes, 2 displacement bytes. */
542 /* COND_JUMP states. */
543 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
544 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
545 /* dword conditionals adds 5 bytes to frag:
546 1 extra opcode byte, 4 displacement bytes. */
548 /* word conditionals add 3 bytes to frag:
549 1 extra opcode byte, 2 displacement bytes. */
552 /* COND_JUMP86 states. */
553 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
554 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
555 /* dword conditionals adds 5 bytes to frag:
556 1 extra opcode byte, 4 displacement bytes. */
558 /* word conditionals add 4 bytes to frag:
559 1 displacement byte and a 3 byte long branch insn. */
563 static const arch_entry cpu_arch
[] =
565 /* Do not replace the first two entries - i386_target_format()
566 relies on them being there in this order. */
567 { STRING_COMMA_LEN ("generic32"), PROCESSOR_GENERIC32
,
568 CPU_GENERIC32_FLAGS
, 0 },
569 { STRING_COMMA_LEN ("generic64"), PROCESSOR_GENERIC64
,
570 CPU_GENERIC64_FLAGS
, 0 },
571 { STRING_COMMA_LEN ("i8086"), PROCESSOR_UNKNOWN
,
573 { STRING_COMMA_LEN ("i186"), PROCESSOR_UNKNOWN
,
575 { STRING_COMMA_LEN ("i286"), PROCESSOR_UNKNOWN
,
577 { STRING_COMMA_LEN ("i386"), PROCESSOR_I386
,
579 { STRING_COMMA_LEN ("i486"), PROCESSOR_I486
,
581 { STRING_COMMA_LEN ("i586"), PROCESSOR_PENTIUM
,
583 { STRING_COMMA_LEN ("i686"), PROCESSOR_PENTIUMPRO
,
585 { STRING_COMMA_LEN ("pentium"), PROCESSOR_PENTIUM
,
587 { STRING_COMMA_LEN ("pentiumpro"), PROCESSOR_PENTIUMPRO
,
589 { STRING_COMMA_LEN ("pentiumii"), PROCESSOR_PENTIUMPRO
,
591 { STRING_COMMA_LEN ("pentiumiii"),PROCESSOR_PENTIUMPRO
,
593 { STRING_COMMA_LEN ("pentium4"), PROCESSOR_PENTIUM4
,
595 { STRING_COMMA_LEN ("prescott"), PROCESSOR_NOCONA
,
597 { STRING_COMMA_LEN ("nocona"), PROCESSOR_NOCONA
,
598 CPU_NOCONA_FLAGS
, 0 },
599 { STRING_COMMA_LEN ("yonah"), PROCESSOR_CORE
,
601 { STRING_COMMA_LEN ("core"), PROCESSOR_CORE
,
603 { STRING_COMMA_LEN ("merom"), PROCESSOR_CORE2
,
604 CPU_CORE2_FLAGS
, 1 },
605 { STRING_COMMA_LEN ("core2"), PROCESSOR_CORE2
,
606 CPU_CORE2_FLAGS
, 0 },
607 { STRING_COMMA_LEN ("corei7"), PROCESSOR_COREI7
,
608 CPU_COREI7_FLAGS
, 0 },
609 { STRING_COMMA_LEN ("l1om"), PROCESSOR_L1OM
,
611 { STRING_COMMA_LEN ("k6"), PROCESSOR_K6
,
613 { STRING_COMMA_LEN ("k6_2"), PROCESSOR_K6
,
615 { STRING_COMMA_LEN ("athlon"), PROCESSOR_ATHLON
,
616 CPU_ATHLON_FLAGS
, 0 },
617 { STRING_COMMA_LEN ("sledgehammer"), PROCESSOR_K8
,
619 { STRING_COMMA_LEN ("opteron"), PROCESSOR_K8
,
621 { STRING_COMMA_LEN ("k8"), PROCESSOR_K8
,
623 { STRING_COMMA_LEN ("amdfam10"), PROCESSOR_AMDFAM10
,
624 CPU_AMDFAM10_FLAGS
, 0 },
625 { STRING_COMMA_LEN ("bdver1"), PROCESSOR_BDVER1
,
626 CPU_BDVER1_FLAGS
, 0 },
627 { STRING_COMMA_LEN (".8087"), PROCESSOR_UNKNOWN
,
629 { STRING_COMMA_LEN (".287"), PROCESSOR_UNKNOWN
,
631 { STRING_COMMA_LEN (".387"), PROCESSOR_UNKNOWN
,
633 { STRING_COMMA_LEN (".no87"), PROCESSOR_UNKNOWN
,
634 CPU_ANY87_FLAGS
, 0 },
635 { STRING_COMMA_LEN (".mmx"), PROCESSOR_UNKNOWN
,
637 { STRING_COMMA_LEN (".nommx"), PROCESSOR_UNKNOWN
,
638 CPU_3DNOWA_FLAGS
, 0 },
639 { STRING_COMMA_LEN (".sse"), PROCESSOR_UNKNOWN
,
641 { STRING_COMMA_LEN (".sse2"), PROCESSOR_UNKNOWN
,
643 { STRING_COMMA_LEN (".sse3"), PROCESSOR_UNKNOWN
,
645 { STRING_COMMA_LEN (".ssse3"), PROCESSOR_UNKNOWN
,
646 CPU_SSSE3_FLAGS
, 0 },
647 { STRING_COMMA_LEN (".sse4.1"), PROCESSOR_UNKNOWN
,
648 CPU_SSE4_1_FLAGS
, 0 },
649 { STRING_COMMA_LEN (".sse4.2"), PROCESSOR_UNKNOWN
,
650 CPU_SSE4_2_FLAGS
, 0 },
651 { STRING_COMMA_LEN (".sse4"), PROCESSOR_UNKNOWN
,
652 CPU_SSE4_2_FLAGS
, 0 },
653 { STRING_COMMA_LEN (".nosse"), PROCESSOR_UNKNOWN
,
654 CPU_ANY_SSE_FLAGS
, 0 },
655 { STRING_COMMA_LEN (".avx"), PROCESSOR_UNKNOWN
,
657 { STRING_COMMA_LEN (".noavx"), PROCESSOR_UNKNOWN
,
658 CPU_ANY_AVX_FLAGS
, 0 },
659 { STRING_COMMA_LEN (".vmx"), PROCESSOR_UNKNOWN
,
661 { STRING_COMMA_LEN (".smx"), PROCESSOR_UNKNOWN
,
663 { STRING_COMMA_LEN (".xsave"), PROCESSOR_UNKNOWN
,
664 CPU_XSAVE_FLAGS
, 0 },
665 { STRING_COMMA_LEN (".aes"), PROCESSOR_UNKNOWN
,
667 { STRING_COMMA_LEN (".pclmul"), PROCESSOR_UNKNOWN
,
668 CPU_PCLMUL_FLAGS
, 0 },
669 { STRING_COMMA_LEN (".clmul"), PROCESSOR_UNKNOWN
,
670 CPU_PCLMUL_FLAGS
, 1 },
671 { STRING_COMMA_LEN (".fma"), PROCESSOR_UNKNOWN
,
673 { STRING_COMMA_LEN (".fma4"), PROCESSOR_UNKNOWN
,
675 { STRING_COMMA_LEN (".xop"), PROCESSOR_UNKNOWN
,
677 { STRING_COMMA_LEN (".lwp"), PROCESSOR_UNKNOWN
,
679 { STRING_COMMA_LEN (".movbe"), PROCESSOR_UNKNOWN
,
680 CPU_MOVBE_FLAGS
, 0 },
681 { STRING_COMMA_LEN (".ept"), PROCESSOR_UNKNOWN
,
683 { STRING_COMMA_LEN (".clflush"), PROCESSOR_UNKNOWN
,
684 CPU_CLFLUSH_FLAGS
, 0 },
685 { STRING_COMMA_LEN (".syscall"), PROCESSOR_UNKNOWN
,
686 CPU_SYSCALL_FLAGS
, 0 },
687 { STRING_COMMA_LEN (".rdtscp"), PROCESSOR_UNKNOWN
,
688 CPU_RDTSCP_FLAGS
, 0 },
689 { STRING_COMMA_LEN (".3dnow"), PROCESSOR_UNKNOWN
,
690 CPU_3DNOW_FLAGS
, 0 },
691 { STRING_COMMA_LEN (".3dnowa"), PROCESSOR_UNKNOWN
,
692 CPU_3DNOWA_FLAGS
, 0 },
693 { STRING_COMMA_LEN (".padlock"), PROCESSOR_UNKNOWN
,
694 CPU_PADLOCK_FLAGS
, 0 },
695 { STRING_COMMA_LEN (".pacifica"), PROCESSOR_UNKNOWN
,
697 { STRING_COMMA_LEN (".svme"), PROCESSOR_UNKNOWN
,
699 { STRING_COMMA_LEN (".sse4a"), PROCESSOR_UNKNOWN
,
700 CPU_SSE4A_FLAGS
, 0 },
701 { STRING_COMMA_LEN (".abm"), PROCESSOR_UNKNOWN
,
706 /* Like s_lcomm_internal in gas/read.c but the alignment string
707 is allowed to be optional. */
710 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
717 && *input_line_pointer
== ',')
719 align
= parse_align (needs_align
- 1);
721 if (align
== (addressT
) -1)
736 bss_alloc (symbolP
, size
, align
);
741 pe_lcomm (int needs_align
)
743 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
747 const pseudo_typeS md_pseudo_table
[] =
749 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
750 {"align", s_align_bytes
, 0},
752 {"align", s_align_ptwo
, 0},
754 {"arch", set_cpu_arch
, 0},
758 {"lcomm", pe_lcomm
, 1},
760 {"ffloat", float_cons
, 'f'},
761 {"dfloat", float_cons
, 'd'},
762 {"tfloat", float_cons
, 'x'},
764 {"slong", signed_cons
, 4},
765 {"noopt", s_ignore
, 0},
766 {"optim", s_ignore
, 0},
767 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
768 {"code16", set_code_flag
, CODE_16BIT
},
769 {"code32", set_code_flag
, CODE_32BIT
},
770 {"code64", set_code_flag
, CODE_64BIT
},
771 {"intel_syntax", set_intel_syntax
, 1},
772 {"att_syntax", set_intel_syntax
, 0},
773 {"intel_mnemonic", set_intel_mnemonic
, 1},
774 {"att_mnemonic", set_intel_mnemonic
, 0},
775 {"allow_index_reg", set_allow_index_reg
, 1},
776 {"disallow_index_reg", set_allow_index_reg
, 0},
777 {"sse_check", set_sse_check
, 0},
778 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
779 {"largecomm", handle_large_common
, 0},
781 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
782 {"loc", dwarf2_directive_loc
, 0},
783 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
786 {"secrel32", pe_directive_secrel
, 0},
791 /* For interface with expression (). */
792 extern char *input_line_pointer
;
794 /* Hash table for instruction mnemonic lookup. */
795 static struct hash_control
*op_hash
;
797 /* Hash table for register lookup. */
798 static struct hash_control
*reg_hash
;
801 i386_align_code (fragS
*fragP
, int count
)
803 /* Various efficient no-op patterns for aligning code labels.
804 Note: Don't try to assemble the instructions in the comments.
805 0L and 0w are not legal. */
806 static const char f32_1
[] =
808 static const char f32_2
[] =
809 {0x66,0x90}; /* xchg %ax,%ax */
810 static const char f32_3
[] =
811 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
812 static const char f32_4
[] =
813 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
814 static const char f32_5
[] =
816 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
817 static const char f32_6
[] =
818 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
819 static const char f32_7
[] =
820 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
821 static const char f32_8
[] =
823 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
824 static const char f32_9
[] =
825 {0x89,0xf6, /* movl %esi,%esi */
826 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
827 static const char f32_10
[] =
828 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
829 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
830 static const char f32_11
[] =
831 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
832 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
833 static const char f32_12
[] =
834 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
835 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
836 static const char f32_13
[] =
837 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
838 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
839 static const char f32_14
[] =
840 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
841 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
842 static const char f16_3
[] =
843 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
844 static const char f16_4
[] =
845 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
846 static const char f16_5
[] =
848 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
849 static const char f16_6
[] =
850 {0x89,0xf6, /* mov %si,%si */
851 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
852 static const char f16_7
[] =
853 {0x8d,0x74,0x00, /* lea 0(%si),%si */
854 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
855 static const char f16_8
[] =
856 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
857 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
858 static const char jump_31
[] =
859 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
860 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
861 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
862 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
863 static const char *const f32_patt
[] = {
864 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
865 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
867 static const char *const f16_patt
[] = {
868 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
871 static const char alt_3
[] =
873 /* nopl 0(%[re]ax) */
874 static const char alt_4
[] =
875 {0x0f,0x1f,0x40,0x00};
876 /* nopl 0(%[re]ax,%[re]ax,1) */
877 static const char alt_5
[] =
878 {0x0f,0x1f,0x44,0x00,0x00};
879 /* nopw 0(%[re]ax,%[re]ax,1) */
880 static const char alt_6
[] =
881 {0x66,0x0f,0x1f,0x44,0x00,0x00};
882 /* nopl 0L(%[re]ax) */
883 static const char alt_7
[] =
884 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
885 /* nopl 0L(%[re]ax,%[re]ax,1) */
886 static const char alt_8
[] =
887 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
888 /* nopw 0L(%[re]ax,%[re]ax,1) */
889 static const char alt_9
[] =
890 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
891 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
892 static const char alt_10
[] =
893 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
895 nopw %cs:0L(%[re]ax,%[re]ax,1) */
896 static const char alt_long_11
[] =
898 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
901 nopw %cs:0L(%[re]ax,%[re]ax,1) */
902 static const char alt_long_12
[] =
905 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
909 nopw %cs:0L(%[re]ax,%[re]ax,1) */
910 static const char alt_long_13
[] =
914 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
919 nopw %cs:0L(%[re]ax,%[re]ax,1) */
920 static const char alt_long_14
[] =
925 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 nopw %cs:0L(%[re]ax,%[re]ax,1) */
932 static const char alt_long_15
[] =
938 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
939 /* nopl 0(%[re]ax,%[re]ax,1)
940 nopw 0(%[re]ax,%[re]ax,1) */
941 static const char alt_short_11
[] =
942 {0x0f,0x1f,0x44,0x00,0x00,
943 0x66,0x0f,0x1f,0x44,0x00,0x00};
944 /* nopw 0(%[re]ax,%[re]ax,1)
945 nopw 0(%[re]ax,%[re]ax,1) */
946 static const char alt_short_12
[] =
947 {0x66,0x0f,0x1f,0x44,0x00,0x00,
948 0x66,0x0f,0x1f,0x44,0x00,0x00};
949 /* nopw 0(%[re]ax,%[re]ax,1)
951 static const char alt_short_13
[] =
952 {0x66,0x0f,0x1f,0x44,0x00,0x00,
953 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
956 static const char alt_short_14
[] =
957 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
958 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
960 nopl 0L(%[re]ax,%[re]ax,1) */
961 static const char alt_short_15
[] =
962 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
963 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
964 static const char *const alt_short_patt
[] = {
965 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
966 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
967 alt_short_14
, alt_short_15
969 static const char *const alt_long_patt
[] = {
970 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
971 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
972 alt_long_14
, alt_long_15
975 /* Only align for at least a positive non-zero boundary. */
976 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
979 /* We need to decide which NOP sequence to use for 32bit and
980 64bit. When -mtune= is used:
982 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
983 PROCESSOR_GENERIC32, f32_patt will be used.
984 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
985 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
986 PROCESSOR_GENERIC64, alt_long_patt will be used.
987 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
988 PROCESSOR_AMDFAM10, and PROCESSOR_BDVER1, alt_short_patt
991 When -mtune= isn't used, alt_long_patt will be used if
992 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
995 When -march= or .arch is used, we can't use anything beyond
996 cpu_arch_isa_flags. */
998 if (flag_code
== CODE_16BIT
)
1002 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1004 /* Adjust jump offset. */
1005 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1008 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1009 f16_patt
[count
- 1], count
);
1013 const char *const *patt
= NULL
;
1015 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
1017 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
1018 switch (cpu_arch_tune
)
1020 case PROCESSOR_UNKNOWN
:
1021 /* We use cpu_arch_isa_flags to check if we SHOULD
1022 optimize for Cpu686. */
1023 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1024 patt
= alt_long_patt
;
1028 case PROCESSOR_PENTIUMPRO
:
1029 case PROCESSOR_PENTIUM4
:
1030 case PROCESSOR_NOCONA
:
1031 case PROCESSOR_CORE
:
1032 case PROCESSOR_CORE2
:
1033 case PROCESSOR_COREI7
:
1034 case PROCESSOR_L1OM
:
1035 case PROCESSOR_GENERIC64
:
1036 patt
= alt_long_patt
;
1039 case PROCESSOR_ATHLON
:
1041 case PROCESSOR_AMDFAM10
:
1042 case PROCESSOR_BDVER1
:
1043 patt
= alt_short_patt
;
1045 case PROCESSOR_I386
:
1046 case PROCESSOR_I486
:
1047 case PROCESSOR_PENTIUM
:
1048 case PROCESSOR_GENERIC32
:
1055 switch (fragP
->tc_frag_data
.tune
)
1057 case PROCESSOR_UNKNOWN
:
1058 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1059 PROCESSOR_UNKNOWN. */
1063 case PROCESSOR_I386
:
1064 case PROCESSOR_I486
:
1065 case PROCESSOR_PENTIUM
:
1067 case PROCESSOR_ATHLON
:
1069 case PROCESSOR_AMDFAM10
:
1070 case PROCESSOR_BDVER1
:
1071 case PROCESSOR_GENERIC32
:
1072 /* We use cpu_arch_isa_flags to check if we CAN optimize
1074 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1075 patt
= alt_short_patt
;
1079 case PROCESSOR_PENTIUMPRO
:
1080 case PROCESSOR_PENTIUM4
:
1081 case PROCESSOR_NOCONA
:
1082 case PROCESSOR_CORE
:
1083 case PROCESSOR_CORE2
:
1084 case PROCESSOR_COREI7
:
1085 case PROCESSOR_L1OM
:
1086 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1087 patt
= alt_long_patt
;
1091 case PROCESSOR_GENERIC64
:
1092 patt
= alt_long_patt
;
1097 if (patt
== f32_patt
)
1099 /* If the padding is less than 15 bytes, we use the normal
1100 ones. Otherwise, we use a jump instruction and adjust
1104 /* For 64bit, the limit is 3 bytes. */
1105 if (flag_code
== CODE_64BIT
1106 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1111 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1112 patt
[count
- 1], count
);
1115 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1117 /* Adjust jump offset. */
1118 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1123 /* Maximum length of an instruction is 15 byte. If the
1124 padding is greater than 15 bytes and we don't use jump,
1125 we have to break it into smaller pieces. */
1126 int padding
= count
;
1127 while (padding
> 15)
1130 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1135 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1136 patt
[padding
- 1], padding
);
1139 fragP
->fr_var
= count
;
1143 operand_type_all_zero (const union i386_operand_type
*x
)
1145 switch (ARRAY_SIZE(x
->array
))
1154 return !x
->array
[0];
1161 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1163 switch (ARRAY_SIZE(x
->array
))
1178 operand_type_equal (const union i386_operand_type
*x
,
1179 const union i386_operand_type
*y
)
1181 switch (ARRAY_SIZE(x
->array
))
1184 if (x
->array
[2] != y
->array
[2])
1187 if (x
->array
[1] != y
->array
[1])
1190 return x
->array
[0] == y
->array
[0];
1198 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1200 switch (ARRAY_SIZE(x
->array
))
1209 return !x
->array
[0];
1216 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1218 switch (ARRAY_SIZE(x
->array
))
1233 cpu_flags_equal (const union i386_cpu_flags
*x
,
1234 const union i386_cpu_flags
*y
)
1236 switch (ARRAY_SIZE(x
->array
))
1239 if (x
->array
[2] != y
->array
[2])
1242 if (x
->array
[1] != y
->array
[1])
1245 return x
->array
[0] == y
->array
[0];
1253 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1255 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1256 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1259 static INLINE i386_cpu_flags
1260 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1262 switch (ARRAY_SIZE (x
.array
))
1265 x
.array
[2] &= y
.array
[2];
1267 x
.array
[1] &= y
.array
[1];
1269 x
.array
[0] &= y
.array
[0];
1277 static INLINE i386_cpu_flags
1278 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1280 switch (ARRAY_SIZE (x
.array
))
1283 x
.array
[2] |= y
.array
[2];
1285 x
.array
[1] |= y
.array
[1];
1287 x
.array
[0] |= y
.array
[0];
1295 static INLINE i386_cpu_flags
1296 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1298 switch (ARRAY_SIZE (x
.array
))
1301 x
.array
[2] &= ~y
.array
[2];
1303 x
.array
[1] &= ~y
.array
[1];
1305 x
.array
[0] &= ~y
.array
[0];
1313 #define CPU_FLAGS_ARCH_MATCH 0x1
1314 #define CPU_FLAGS_64BIT_MATCH 0x2
1315 #define CPU_FLAGS_AES_MATCH 0x4
1316 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1317 #define CPU_FLAGS_AVX_MATCH 0x10
1319 #define CPU_FLAGS_32BIT_MATCH \
1320 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1321 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1322 #define CPU_FLAGS_PERFECT_MATCH \
1323 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1325 /* Return CPU flags match bits. */
1328 cpu_flags_match (const insn_template
*t
)
1330 i386_cpu_flags x
= t
->cpu_flags
;
1331 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1333 x
.bitfield
.cpu64
= 0;
1334 x
.bitfield
.cpuno64
= 0;
1336 if (cpu_flags_all_zero (&x
))
1338 /* This instruction is available on all archs. */
1339 match
|= CPU_FLAGS_32BIT_MATCH
;
1343 /* This instruction is available only on some archs. */
1344 i386_cpu_flags cpu
= cpu_arch_flags
;
1346 cpu
.bitfield
.cpu64
= 0;
1347 cpu
.bitfield
.cpuno64
= 0;
1348 cpu
= cpu_flags_and (x
, cpu
);
1349 if (!cpu_flags_all_zero (&cpu
))
1351 if (x
.bitfield
.cpuavx
)
1353 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1354 if (cpu
.bitfield
.cpuavx
)
1356 /* Check SSE2AVX. */
1357 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1359 match
|= (CPU_FLAGS_ARCH_MATCH
1360 | CPU_FLAGS_AVX_MATCH
);
1362 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1363 match
|= CPU_FLAGS_AES_MATCH
;
1365 if (!x
.bitfield
.cpupclmul
1366 || cpu
.bitfield
.cpupclmul
)
1367 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1371 match
|= CPU_FLAGS_ARCH_MATCH
;
1374 match
|= CPU_FLAGS_32BIT_MATCH
;
1380 static INLINE i386_operand_type
1381 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1383 switch (ARRAY_SIZE (x
.array
))
1386 x
.array
[2] &= y
.array
[2];
1388 x
.array
[1] &= y
.array
[1];
1390 x
.array
[0] &= y
.array
[0];
1398 static INLINE i386_operand_type
1399 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1401 switch (ARRAY_SIZE (x
.array
))
1404 x
.array
[2] |= y
.array
[2];
1406 x
.array
[1] |= y
.array
[1];
1408 x
.array
[0] |= y
.array
[0];
1416 static INLINE i386_operand_type
1417 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1419 switch (ARRAY_SIZE (x
.array
))
1422 x
.array
[2] ^= y
.array
[2];
1424 x
.array
[1] ^= y
.array
[1];
1426 x
.array
[0] ^= y
.array
[0];
1434 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1435 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1436 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1437 static const i386_operand_type inoutportreg
1438 = OPERAND_TYPE_INOUTPORTREG
;
1439 static const i386_operand_type reg16_inoutportreg
1440 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1441 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1442 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1443 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1444 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1445 static const i386_operand_type anydisp
1446 = OPERAND_TYPE_ANYDISP
;
1447 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1448 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1449 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1450 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1451 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1452 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1453 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1454 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1455 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1456 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1457 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1458 static const i386_operand_type vec_imm4
= OPERAND_TYPE_VEC_IMM4
;
1469 operand_type_check (i386_operand_type t
, enum operand_type c
)
1474 return (t
.bitfield
.reg8
1477 || t
.bitfield
.reg64
);
1480 return (t
.bitfield
.imm8
1484 || t
.bitfield
.imm32s
1485 || t
.bitfield
.imm64
);
1488 return (t
.bitfield
.disp8
1489 || t
.bitfield
.disp16
1490 || t
.bitfield
.disp32
1491 || t
.bitfield
.disp32s
1492 || t
.bitfield
.disp64
);
1495 return (t
.bitfield
.disp8
1496 || t
.bitfield
.disp16
1497 || t
.bitfield
.disp32
1498 || t
.bitfield
.disp32s
1499 || t
.bitfield
.disp64
1500 || t
.bitfield
.baseindex
);
1509 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1510 operand J for instruction template T. */
1513 match_reg_size (const insn_template
*t
, unsigned int j
)
1515 return !((i
.types
[j
].bitfield
.byte
1516 && !t
->operand_types
[j
].bitfield
.byte
)
1517 || (i
.types
[j
].bitfield
.word
1518 && !t
->operand_types
[j
].bitfield
.word
)
1519 || (i
.types
[j
].bitfield
.dword
1520 && !t
->operand_types
[j
].bitfield
.dword
)
1521 || (i
.types
[j
].bitfield
.qword
1522 && !t
->operand_types
[j
].bitfield
.qword
));
1525 /* Return 1 if there is no conflict in any size on operand J for
1526 instruction template T. */
1529 match_mem_size (const insn_template
*t
, unsigned int j
)
1531 return (match_reg_size (t
, j
)
1532 && !((i
.types
[j
].bitfield
.unspecified
1533 && !t
->operand_types
[j
].bitfield
.unspecified
)
1534 || (i
.types
[j
].bitfield
.fword
1535 && !t
->operand_types
[j
].bitfield
.fword
)
1536 || (i
.types
[j
].bitfield
.tbyte
1537 && !t
->operand_types
[j
].bitfield
.tbyte
)
1538 || (i
.types
[j
].bitfield
.xmmword
1539 && !t
->operand_types
[j
].bitfield
.xmmword
)
1540 || (i
.types
[j
].bitfield
.ymmword
1541 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1544 /* Return 1 if there is no size conflict on any operands for
1545 instruction template T. */
1548 operand_size_match (const insn_template
*t
)
1553 /* Don't check jump instructions. */
1554 if (t
->opcode_modifier
.jump
1555 || t
->opcode_modifier
.jumpbyte
1556 || t
->opcode_modifier
.jumpdword
1557 || t
->opcode_modifier
.jumpintersegment
)
1560 /* Check memory and accumulator operand size. */
1561 for (j
= 0; j
< i
.operands
; j
++)
1563 if (t
->operand_types
[j
].bitfield
.anysize
)
1566 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1572 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1581 else if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
1584 i
.error
= operand_size_mismatch
;
1588 /* Check reverse. */
1589 gas_assert (i
.operands
== 2);
1592 for (j
= 0; j
< 2; j
++)
1594 if (t
->operand_types
[j
].bitfield
.acc
1595 && !match_reg_size (t
, j
? 0 : 1))
1598 if (i
.types
[j
].bitfield
.mem
1599 && !match_mem_size (t
, j
? 0 : 1))
1607 operand_type_match (i386_operand_type overlap
,
1608 i386_operand_type given
)
1610 i386_operand_type temp
= overlap
;
1612 temp
.bitfield
.jumpabsolute
= 0;
1613 temp
.bitfield
.unspecified
= 0;
1614 temp
.bitfield
.byte
= 0;
1615 temp
.bitfield
.word
= 0;
1616 temp
.bitfield
.dword
= 0;
1617 temp
.bitfield
.fword
= 0;
1618 temp
.bitfield
.qword
= 0;
1619 temp
.bitfield
.tbyte
= 0;
1620 temp
.bitfield
.xmmword
= 0;
1621 temp
.bitfield
.ymmword
= 0;
1622 if (operand_type_all_zero (&temp
))
1625 if (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1626 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
)
1630 i
.error
= operand_type_mismatch
;
1634 /* If given types g0 and g1 are registers they must be of the same type
1635 unless the expected operand type register overlap is null.
1636 Note that Acc in a template matches every size of reg. */
1639 operand_type_register_match (i386_operand_type m0
,
1640 i386_operand_type g0
,
1641 i386_operand_type t0
,
1642 i386_operand_type m1
,
1643 i386_operand_type g1
,
1644 i386_operand_type t1
)
1646 if (!operand_type_check (g0
, reg
))
1649 if (!operand_type_check (g1
, reg
))
1652 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1653 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1654 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1655 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1658 if (m0
.bitfield
.acc
)
1660 t0
.bitfield
.reg8
= 1;
1661 t0
.bitfield
.reg16
= 1;
1662 t0
.bitfield
.reg32
= 1;
1663 t0
.bitfield
.reg64
= 1;
1666 if (m1
.bitfield
.acc
)
1668 t1
.bitfield
.reg8
= 1;
1669 t1
.bitfield
.reg16
= 1;
1670 t1
.bitfield
.reg32
= 1;
1671 t1
.bitfield
.reg64
= 1;
1674 if (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1675 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1676 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1677 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
))
1680 i
.error
= register_type_mismatch
;
1685 static INLINE
unsigned int
1686 mode_from_disp_size (i386_operand_type t
)
1688 if (t
.bitfield
.disp8
)
1690 else if (t
.bitfield
.disp16
1691 || t
.bitfield
.disp32
1692 || t
.bitfield
.disp32s
)
1699 fits_in_signed_byte (offsetT num
)
1701 return (num
>= -128) && (num
<= 127);
1705 fits_in_unsigned_byte (offsetT num
)
1707 return (num
& 0xff) == num
;
1711 fits_in_unsigned_word (offsetT num
)
1713 return (num
& 0xffff) == num
;
1717 fits_in_signed_word (offsetT num
)
1719 return (-32768 <= num
) && (num
<= 32767);
1723 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1728 return (!(((offsetT
) -1 << 31) & num
)
1729 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1731 } /* fits_in_signed_long() */
1734 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1739 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1741 } /* fits_in_unsigned_long() */
1744 fits_in_imm4 (offsetT num
)
1746 return (num
& 0xf) == num
;
1749 static i386_operand_type
1750 smallest_imm_type (offsetT num
)
1752 i386_operand_type t
;
1754 operand_type_set (&t
, 0);
1755 t
.bitfield
.imm64
= 1;
1757 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1759 /* This code is disabled on the 486 because all the Imm1 forms
1760 in the opcode table are slower on the i486. They're the
1761 versions with the implicitly specified single-position
1762 displacement, which has another syntax if you really want to
1764 t
.bitfield
.imm1
= 1;
1765 t
.bitfield
.imm8
= 1;
1766 t
.bitfield
.imm8s
= 1;
1767 t
.bitfield
.imm16
= 1;
1768 t
.bitfield
.imm32
= 1;
1769 t
.bitfield
.imm32s
= 1;
1771 else if (fits_in_signed_byte (num
))
1773 t
.bitfield
.imm8
= 1;
1774 t
.bitfield
.imm8s
= 1;
1775 t
.bitfield
.imm16
= 1;
1776 t
.bitfield
.imm32
= 1;
1777 t
.bitfield
.imm32s
= 1;
1779 else if (fits_in_unsigned_byte (num
))
1781 t
.bitfield
.imm8
= 1;
1782 t
.bitfield
.imm16
= 1;
1783 t
.bitfield
.imm32
= 1;
1784 t
.bitfield
.imm32s
= 1;
1786 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1788 t
.bitfield
.imm16
= 1;
1789 t
.bitfield
.imm32
= 1;
1790 t
.bitfield
.imm32s
= 1;
1792 else if (fits_in_signed_long (num
))
1794 t
.bitfield
.imm32
= 1;
1795 t
.bitfield
.imm32s
= 1;
1797 else if (fits_in_unsigned_long (num
))
1798 t
.bitfield
.imm32
= 1;
1804 offset_in_range (offsetT val
, int size
)
1810 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1811 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1812 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1814 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1820 /* If BFD64, sign extend val for 32bit address mode. */
1821 if (flag_code
!= CODE_64BIT
1822 || i
.prefix
[ADDR_PREFIX
])
1823 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1824 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1827 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1829 char buf1
[40], buf2
[40];
1831 sprint_value (buf1
, val
);
1832 sprint_value (buf2
, val
& mask
);
1833 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1847 a. PREFIX_EXIST if attempting to add a prefix where one from the
1848 same class already exists.
1849 b. PREFIX_LOCK if lock prefix is added.
1850 c. PREFIX_REP if rep/repne prefix is added.
1851 d. PREFIX_OTHER if other prefix is added.
1854 static enum PREFIX_GROUP
1855 add_prefix (unsigned int prefix
)
1857 enum PREFIX_GROUP ret
= PREFIX_OTHER
;
1860 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1861 && flag_code
== CODE_64BIT
)
1863 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1864 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1865 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1876 case CS_PREFIX_OPCODE
:
1877 case DS_PREFIX_OPCODE
:
1878 case ES_PREFIX_OPCODE
:
1879 case FS_PREFIX_OPCODE
:
1880 case GS_PREFIX_OPCODE
:
1881 case SS_PREFIX_OPCODE
:
1885 case REPNE_PREFIX_OPCODE
:
1886 case REPE_PREFIX_OPCODE
:
1891 case LOCK_PREFIX_OPCODE
:
1900 case ADDR_PREFIX_OPCODE
:
1904 case DATA_PREFIX_OPCODE
:
1908 if (i
.prefix
[q
] != 0)
1916 i
.prefix
[q
] |= prefix
;
1919 as_bad (_("same type of prefix used twice"));
1925 set_code_flag (int value
)
1927 flag_code
= (enum flag_code
) value
;
1928 if (flag_code
== CODE_64BIT
)
1930 cpu_arch_flags
.bitfield
.cpu64
= 1;
1931 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1935 cpu_arch_flags
.bitfield
.cpu64
= 0;
1936 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1938 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1940 as_bad (_("64bit mode not supported on this CPU."));
1942 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1944 as_bad (_("32bit mode not supported on this CPU."));
1946 stackop_size
= '\0';
1950 set_16bit_gcc_code_flag (int new_code_flag
)
1952 flag_code
= (enum flag_code
) new_code_flag
;
1953 if (flag_code
!= CODE_16BIT
)
1955 cpu_arch_flags
.bitfield
.cpu64
= 0;
1956 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1957 stackop_size
= LONG_MNEM_SUFFIX
;
1961 set_intel_syntax (int syntax_flag
)
1963 /* Find out if register prefixing is specified. */
1964 int ask_naked_reg
= 0;
1967 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1969 char *string
= input_line_pointer
;
1970 int e
= get_symbol_end ();
1972 if (strcmp (string
, "prefix") == 0)
1974 else if (strcmp (string
, "noprefix") == 0)
1977 as_bad (_("bad argument to syntax directive."));
1978 *input_line_pointer
= e
;
1980 demand_empty_rest_of_line ();
1982 intel_syntax
= syntax_flag
;
1984 if (ask_naked_reg
== 0)
1985 allow_naked_reg
= (intel_syntax
1986 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1988 allow_naked_reg
= (ask_naked_reg
< 0);
1990 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1992 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1993 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1994 register_prefix
= allow_naked_reg
? "" : "%";
1998 set_intel_mnemonic (int mnemonic_flag
)
2000 intel_mnemonic
= mnemonic_flag
;
2004 set_allow_index_reg (int flag
)
2006 allow_index_reg
= flag
;
2010 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
2014 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2016 char *string
= input_line_pointer
;
2017 int e
= get_symbol_end ();
2019 if (strcmp (string
, "none") == 0)
2020 sse_check
= sse_check_none
;
2021 else if (strcmp (string
, "warning") == 0)
2022 sse_check
= sse_check_warning
;
2023 else if (strcmp (string
, "error") == 0)
2024 sse_check
= sse_check_error
;
2026 as_bad (_("bad argument to sse_check directive."));
2027 *input_line_pointer
= e
;
2030 as_bad (_("missing argument for sse_check directive"));
2032 demand_empty_rest_of_line ();
2036 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
2037 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
2039 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2040 static const char *arch
;
2042 /* Intel LIOM is only supported on ELF. */
2048 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
2049 use default_arch. */
2050 arch
= cpu_arch_name
;
2052 arch
= default_arch
;
2055 /* If we are targeting Intel L1OM, we must enable it. */
2056 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
2057 || new_flag
.bitfield
.cpul1om
)
2060 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
2065 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2069 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2071 char *string
= input_line_pointer
;
2072 int e
= get_symbol_end ();
2074 i386_cpu_flags flags
;
2076 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
2078 if (strcmp (string
, cpu_arch
[j
].name
) == 0)
2080 check_cpu_arch_compatible (string
, cpu_arch
[j
].flags
);
2084 cpu_arch_name
= cpu_arch
[j
].name
;
2085 cpu_sub_arch_name
= NULL
;
2086 cpu_arch_flags
= cpu_arch
[j
].flags
;
2087 if (flag_code
== CODE_64BIT
)
2089 cpu_arch_flags
.bitfield
.cpu64
= 1;
2090 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2094 cpu_arch_flags
.bitfield
.cpu64
= 0;
2095 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2097 cpu_arch_isa
= cpu_arch
[j
].type
;
2098 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
2099 if (!cpu_arch_tune_set
)
2101 cpu_arch_tune
= cpu_arch_isa
;
2102 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2107 if (strncmp (string
+ 1, "no", 2))
2108 flags
= cpu_flags_or (cpu_arch_flags
,
2111 flags
= cpu_flags_and_not (cpu_arch_flags
,
2113 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2115 if (cpu_sub_arch_name
)
2117 char *name
= cpu_sub_arch_name
;
2118 cpu_sub_arch_name
= concat (name
,
2120 (const char *) NULL
);
2124 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
2125 cpu_arch_flags
= flags
;
2127 *input_line_pointer
= e
;
2128 demand_empty_rest_of_line ();
2132 if (j
>= ARRAY_SIZE (cpu_arch
))
2133 as_bad (_("no such architecture: `%s'"), string
);
2135 *input_line_pointer
= e
;
2138 as_bad (_("missing cpu architecture"));
2140 no_cond_jump_promotion
= 0;
2141 if (*input_line_pointer
== ','
2142 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2144 char *string
= ++input_line_pointer
;
2145 int e
= get_symbol_end ();
2147 if (strcmp (string
, "nojumps") == 0)
2148 no_cond_jump_promotion
= 1;
2149 else if (strcmp (string
, "jumps") == 0)
2152 as_bad (_("no such architecture modifier: `%s'"), string
);
2154 *input_line_pointer
= e
;
2157 demand_empty_rest_of_line ();
2160 enum bfd_architecture
2163 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2165 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2166 || flag_code
!= CODE_64BIT
)
2167 as_fatal (_("Intel L1OM is 64bit ELF only"));
2168 return bfd_arch_l1om
;
2171 return bfd_arch_i386
;
2177 if (!strcmp (default_arch
, "x86_64"))
2179 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2181 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2182 as_fatal (_("Intel L1OM is 64bit ELF only"));
2183 return bfd_mach_l1om
;
2186 return bfd_mach_x86_64
;
2188 else if (!strcmp (default_arch
, "i386"))
2189 return bfd_mach_i386_i386
;
2191 as_fatal (_("Unknown architecture"));
2197 const char *hash_err
;
2199 /* Initialize op_hash hash table. */
2200 op_hash
= hash_new ();
2203 const insn_template
*optab
;
2204 templates
*core_optab
;
2206 /* Setup for loop. */
2208 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2209 core_optab
->start
= optab
;
2214 if (optab
->name
== NULL
2215 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2217 /* different name --> ship out current template list;
2218 add to hash table; & begin anew. */
2219 core_optab
->end
= optab
;
2220 hash_err
= hash_insert (op_hash
,
2222 (void *) core_optab
);
2225 as_fatal (_("Internal Error: Can't hash %s: %s"),
2229 if (optab
->name
== NULL
)
2231 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2232 core_optab
->start
= optab
;
2237 /* Initialize reg_hash hash table. */
2238 reg_hash
= hash_new ();
2240 const reg_entry
*regtab
;
2241 unsigned int regtab_size
= i386_regtab_size
;
2243 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2245 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2247 as_fatal (_("Internal Error: Can't hash %s: %s"),
2253 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2258 for (c
= 0; c
< 256; c
++)
2263 mnemonic_chars
[c
] = c
;
2264 register_chars
[c
] = c
;
2265 operand_chars
[c
] = c
;
2267 else if (ISLOWER (c
))
2269 mnemonic_chars
[c
] = c
;
2270 register_chars
[c
] = c
;
2271 operand_chars
[c
] = c
;
2273 else if (ISUPPER (c
))
2275 mnemonic_chars
[c
] = TOLOWER (c
);
2276 register_chars
[c
] = mnemonic_chars
[c
];
2277 operand_chars
[c
] = c
;
2280 if (ISALPHA (c
) || ISDIGIT (c
))
2281 identifier_chars
[c
] = c
;
2284 identifier_chars
[c
] = c
;
2285 operand_chars
[c
] = c
;
2290 identifier_chars
['@'] = '@';
2293 identifier_chars
['?'] = '?';
2294 operand_chars
['?'] = '?';
2296 digit_chars
['-'] = '-';
2297 mnemonic_chars
['_'] = '_';
2298 mnemonic_chars
['-'] = '-';
2299 mnemonic_chars
['.'] = '.';
2300 identifier_chars
['_'] = '_';
2301 identifier_chars
['.'] = '.';
2303 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2304 operand_chars
[(unsigned char) *p
] = *p
;
2307 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2310 record_alignment (text_section
, 2);
2311 record_alignment (data_section
, 2);
2312 record_alignment (bss_section
, 2);
2316 if (flag_code
== CODE_64BIT
)
2318 x86_dwarf2_return_column
= 16;
2319 x86_cie_data_alignment
= -8;
2323 x86_dwarf2_return_column
= 8;
2324 x86_cie_data_alignment
= -4;
2329 i386_print_statistics (FILE *file
)
2331 hash_print_statistics (file
, "i386 opcode", op_hash
);
2332 hash_print_statistics (file
, "i386 register", reg_hash
);
2337 /* Debugging routines for md_assemble. */
2338 static void pte (insn_template
*);
2339 static void pt (i386_operand_type
);
2340 static void pe (expressionS
*);
2341 static void ps (symbolS
*);
2344 pi (char *line
, i386_insn
*x
)
2348 fprintf (stdout
, "%s: template ", line
);
2350 fprintf (stdout
, " address: base %s index %s scale %x\n",
2351 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2352 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2353 x
->log2_scale_factor
);
2354 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2355 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2356 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2357 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2358 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2359 (x
->rex
& REX_W
) != 0,
2360 (x
->rex
& REX_R
) != 0,
2361 (x
->rex
& REX_X
) != 0,
2362 (x
->rex
& REX_B
) != 0);
2363 for (j
= 0; j
< x
->operands
; j
++)
2365 fprintf (stdout
, " #%d: ", j
+ 1);
2367 fprintf (stdout
, "\n");
2368 if (x
->types
[j
].bitfield
.reg8
2369 || x
->types
[j
].bitfield
.reg16
2370 || x
->types
[j
].bitfield
.reg32
2371 || x
->types
[j
].bitfield
.reg64
2372 || x
->types
[j
].bitfield
.regmmx
2373 || x
->types
[j
].bitfield
.regxmm
2374 || x
->types
[j
].bitfield
.regymm
2375 || x
->types
[j
].bitfield
.sreg2
2376 || x
->types
[j
].bitfield
.sreg3
2377 || x
->types
[j
].bitfield
.control
2378 || x
->types
[j
].bitfield
.debug
2379 || x
->types
[j
].bitfield
.test
)
2380 fprintf (stdout
, "%s\n", x
->op
[j
].regs
->reg_name
);
2381 if (operand_type_check (x
->types
[j
], imm
))
2383 if (operand_type_check (x
->types
[j
], disp
))
2384 pe (x
->op
[j
].disps
);
2389 pte (insn_template
*t
)
2392 fprintf (stdout
, " %d operands ", t
->operands
);
2393 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2394 if (t
->extension_opcode
!= None
)
2395 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2396 if (t
->opcode_modifier
.d
)
2397 fprintf (stdout
, "D");
2398 if (t
->opcode_modifier
.w
)
2399 fprintf (stdout
, "W");
2400 fprintf (stdout
, "\n");
2401 for (j
= 0; j
< t
->operands
; j
++)
2403 fprintf (stdout
, " #%d type ", j
+ 1);
2404 pt (t
->operand_types
[j
]);
2405 fprintf (stdout
, "\n");
2412 fprintf (stdout
, " operation %d\n", e
->X_op
);
2413 fprintf (stdout
, " add_number %ld (%lx)\n",
2414 (long) e
->X_add_number
, (long) e
->X_add_number
);
2415 if (e
->X_add_symbol
)
2417 fprintf (stdout
, " add_symbol ");
2418 ps (e
->X_add_symbol
);
2419 fprintf (stdout
, "\n");
2423 fprintf (stdout
, " op_symbol ");
2424 ps (e
->X_op_symbol
);
2425 fprintf (stdout
, "\n");
2432 fprintf (stdout
, "%s type %s%s",
2434 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2435 segment_name (S_GET_SEGMENT (s
)));
2438 static struct type_name
2440 i386_operand_type mask
;
2443 const type_names
[] =
2445 { OPERAND_TYPE_REG8
, "r8" },
2446 { OPERAND_TYPE_REG16
, "r16" },
2447 { OPERAND_TYPE_REG32
, "r32" },
2448 { OPERAND_TYPE_REG64
, "r64" },
2449 { OPERAND_TYPE_IMM8
, "i8" },
2450 { OPERAND_TYPE_IMM8
, "i8s" },
2451 { OPERAND_TYPE_IMM16
, "i16" },
2452 { OPERAND_TYPE_IMM32
, "i32" },
2453 { OPERAND_TYPE_IMM32S
, "i32s" },
2454 { OPERAND_TYPE_IMM64
, "i64" },
2455 { OPERAND_TYPE_IMM1
, "i1" },
2456 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2457 { OPERAND_TYPE_DISP8
, "d8" },
2458 { OPERAND_TYPE_DISP16
, "d16" },
2459 { OPERAND_TYPE_DISP32
, "d32" },
2460 { OPERAND_TYPE_DISP32S
, "d32s" },
2461 { OPERAND_TYPE_DISP64
, "d64" },
2462 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2463 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2464 { OPERAND_TYPE_CONTROL
, "control reg" },
2465 { OPERAND_TYPE_TEST
, "test reg" },
2466 { OPERAND_TYPE_DEBUG
, "debug reg" },
2467 { OPERAND_TYPE_FLOATREG
, "FReg" },
2468 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2469 { OPERAND_TYPE_SREG2
, "SReg2" },
2470 { OPERAND_TYPE_SREG3
, "SReg3" },
2471 { OPERAND_TYPE_ACC
, "Acc" },
2472 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2473 { OPERAND_TYPE_REGMMX
, "rMMX" },
2474 { OPERAND_TYPE_REGXMM
, "rXMM" },
2475 { OPERAND_TYPE_REGYMM
, "rYMM" },
2476 { OPERAND_TYPE_ESSEG
, "es" },
2480 pt (i386_operand_type t
)
2483 i386_operand_type a
;
2485 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2487 a
= operand_type_and (t
, type_names
[j
].mask
);
2488 if (!operand_type_all_zero (&a
))
2489 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2494 #endif /* DEBUG386 */
2496 static bfd_reloc_code_real_type
2497 reloc (unsigned int size
,
2500 bfd_reloc_code_real_type other
)
2502 if (other
!= NO_RELOC
)
2504 reloc_howto_type
*rel
;
2509 case BFD_RELOC_X86_64_GOT32
:
2510 return BFD_RELOC_X86_64_GOT64
;
2512 case BFD_RELOC_X86_64_PLTOFF64
:
2513 return BFD_RELOC_X86_64_PLTOFF64
;
2515 case BFD_RELOC_X86_64_GOTPC32
:
2516 other
= BFD_RELOC_X86_64_GOTPC64
;
2518 case BFD_RELOC_X86_64_GOTPCREL
:
2519 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2521 case BFD_RELOC_X86_64_TPOFF32
:
2522 other
= BFD_RELOC_X86_64_TPOFF64
;
2524 case BFD_RELOC_X86_64_DTPOFF32
:
2525 other
= BFD_RELOC_X86_64_DTPOFF64
;
2531 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2532 if (size
== 4 && flag_code
!= CODE_64BIT
)
2535 rel
= bfd_reloc_type_lookup (stdoutput
, other
);
2537 as_bad (_("unknown relocation (%u)"), other
);
2538 else if (size
!= bfd_get_reloc_size (rel
))
2539 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2540 bfd_get_reloc_size (rel
),
2542 else if (pcrel
&& !rel
->pc_relative
)
2543 as_bad (_("non-pc-relative relocation for pc-relative field"));
2544 else if ((rel
->complain_on_overflow
== complain_overflow_signed
2546 || (rel
->complain_on_overflow
== complain_overflow_unsigned
2548 as_bad (_("relocated field and relocation type differ in signedness"));
2557 as_bad (_("there are no unsigned pc-relative relocations"));
2560 case 1: return BFD_RELOC_8_PCREL
;
2561 case 2: return BFD_RELOC_16_PCREL
;
2562 case 4: return BFD_RELOC_32_PCREL
;
2563 case 8: return BFD_RELOC_64_PCREL
;
2565 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2572 case 4: return BFD_RELOC_X86_64_32S
;
2577 case 1: return BFD_RELOC_8
;
2578 case 2: return BFD_RELOC_16
;
2579 case 4: return BFD_RELOC_32
;
2580 case 8: return BFD_RELOC_64
;
2582 as_bad (_("cannot do %s %u byte relocation"),
2583 sign
> 0 ? "signed" : "unsigned", size
);
2589 /* Here we decide which fixups can be adjusted to make them relative to
2590 the beginning of the section instead of the symbol. Basically we need
2591 to make sure that the dynamic relocations are done correctly, so in
2592 some cases we force the original symbol to be used. */
2595 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2597 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2601 /* Don't adjust pc-relative references to merge sections in 64-bit
2603 if (use_rela_relocations
2604 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2608 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2609 and changed later by validate_fix. */
2610 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2611 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2614 /* adjust_reloc_syms doesn't know about the GOT. */
2615 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2616 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2617 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2618 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2619 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2620 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2621 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2622 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2623 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2624 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2625 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2626 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2627 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2628 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2629 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2630 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2631 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2632 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2633 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2634 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2635 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2636 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2637 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2638 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2639 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2640 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2641 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2642 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2649 intel_float_operand (const char *mnemonic
)
2651 /* Note that the value returned is meaningful only for opcodes with (memory)
2652 operands, hence the code here is free to improperly handle opcodes that
2653 have no operands (for better performance and smaller code). */
2655 if (mnemonic
[0] != 'f')
2656 return 0; /* non-math */
2658 switch (mnemonic
[1])
2660 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2661 the fs segment override prefix not currently handled because no
2662 call path can make opcodes without operands get here */
2664 return 2 /* integer op */;
2666 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2667 return 3; /* fldcw/fldenv */
2670 if (mnemonic
[2] != 'o' /* fnop */)
2671 return 3; /* non-waiting control op */
2674 if (mnemonic
[2] == 's')
2675 return 3; /* frstor/frstpm */
2678 if (mnemonic
[2] == 'a')
2679 return 3; /* fsave */
2680 if (mnemonic
[2] == 't')
2682 switch (mnemonic
[3])
2684 case 'c': /* fstcw */
2685 case 'd': /* fstdw */
2686 case 'e': /* fstenv */
2687 case 's': /* fsts[gw] */
2693 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2694 return 0; /* fxsave/fxrstor are not really math ops */
2701 /* Build the VEX prefix. */
2704 build_vex_prefix (const insn_template
*t
)
2706 unsigned int register_specifier
;
2707 unsigned int implied_prefix
;
2708 unsigned int vector_length
;
2710 /* Check register specifier. */
2711 if (i
.vex
.register_specifier
)
2713 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2714 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2715 register_specifier
+= 8;
2716 register_specifier
= ~register_specifier
& 0xf;
2719 register_specifier
= 0xf;
2721 /* Use 2-byte VEX prefix by swappping destination and source
2724 && i
.operands
== i
.reg_operands
2725 && i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2726 && i
.tm
.opcode_modifier
.s
2729 unsigned int xchg
= i
.operands
- 1;
2730 union i386_op temp_op
;
2731 i386_operand_type temp_type
;
2733 temp_type
= i
.types
[xchg
];
2734 i
.types
[xchg
] = i
.types
[0];
2735 i
.types
[0] = temp_type
;
2736 temp_op
= i
.op
[xchg
];
2737 i
.op
[xchg
] = i
.op
[0];
2740 gas_assert (i
.rm
.mode
== 3);
2744 i
.rm
.regmem
= i
.rm
.reg
;
2747 /* Use the next insn. */
2751 if (i
.tm
.opcode_modifier
.vex
== VEXScalar
)
2752 vector_length
= avxscalar
;
2754 vector_length
= i
.tm
.opcode_modifier
.vex
== VEX256
? 1 : 0;
2756 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2761 case DATA_PREFIX_OPCODE
:
2764 case REPE_PREFIX_OPCODE
:
2767 case REPNE_PREFIX_OPCODE
:
2774 /* Use 2-byte VEX prefix if possible. */
2775 if (i
.tm
.opcode_modifier
.vexopcode
== VEX0F
2776 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2778 /* 2-byte VEX prefix. */
2782 i
.vex
.bytes
[0] = 0xc5;
2784 /* Check the REX.R bit. */
2785 r
= (i
.rex
& REX_R
) ? 0 : 1;
2786 i
.vex
.bytes
[1] = (r
<< 7
2787 | register_specifier
<< 3
2788 | vector_length
<< 2
2793 /* 3-byte VEX prefix. */
2798 switch (i
.tm
.opcode_modifier
.vexopcode
)
2802 i
.vex
.bytes
[0] = 0xc4;
2806 i
.vex
.bytes
[0] = 0xc4;
2810 i
.vex
.bytes
[0] = 0xc4;
2814 i
.vex
.bytes
[0] = 0x8f;
2818 i
.vex
.bytes
[0] = 0x8f;
2822 i
.vex
.bytes
[0] = 0x8f;
2828 /* The high 3 bits of the second VEX byte are 1's compliment
2829 of RXB bits from REX. */
2830 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2832 /* Check the REX.W bit. */
2833 w
= (i
.rex
& REX_W
) ? 1 : 0;
2834 if (i
.tm
.opcode_modifier
.vexw
)
2839 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
2843 i
.vex
.bytes
[2] = (w
<< 7
2844 | register_specifier
<< 3
2845 | vector_length
<< 2
2851 process_immext (void)
2855 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2857 /* SSE3 Instructions have the fixed operands with an opcode
2858 suffix which is coded in the same place as an 8-bit immediate
2859 field would be. Here we check those operands and remove them
2863 for (x
= 0; x
< i
.operands
; x
++)
2864 if (i
.op
[x
].regs
->reg_num
!= x
)
2865 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2866 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2872 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2873 which is coded in the same place as an 8-bit immediate field
2874 would be. Here we fake an 8-bit immediate operand from the
2875 opcode suffix stored in tm.extension_opcode.
2877 AVX instructions also use this encoding, for some of
2878 3 argument instructions. */
2880 gas_assert (i
.imm_operands
== 0
2882 || (i
.tm
.opcode_modifier
.vex
2883 && i
.operands
<= 4)));
2885 exp
= &im_expressions
[i
.imm_operands
++];
2886 i
.op
[i
.operands
].imms
= exp
;
2887 i
.types
[i
.operands
] = imm8
;
2889 exp
->X_op
= O_constant
;
2890 exp
->X_add_number
= i
.tm
.extension_opcode
;
2891 i
.tm
.extension_opcode
= None
;
2894 /* This is the guts of the machine-dependent assembler. LINE points to a
2895 machine dependent instruction. This function is supposed to emit
2896 the frags/bytes it assembles to. */
2899 md_assemble (char *line
)
2902 char mnemonic
[MAX_MNEM_SIZE
];
2903 const insn_template
*t
;
2905 /* Initialize globals. */
2906 memset (&i
, '\0', sizeof (i
));
2907 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2908 i
.reloc
[j
] = NO_RELOC
;
2909 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2910 memset (im_expressions
, '\0', sizeof (im_expressions
));
2911 save_stack_p
= save_stack
;
2913 /* First parse an instruction mnemonic & call i386_operand for the operands.
2914 We assume that the scrubber has arranged it so that line[0] is the valid
2915 start of a (possibly prefixed) mnemonic. */
2917 line
= parse_insn (line
, mnemonic
);
2921 line
= parse_operands (line
, mnemonic
);
2926 /* Now we've parsed the mnemonic into a set of templates, and have the
2927 operands at hand. */
2929 /* All intel opcodes have reversed operands except for "bound" and
2930 "enter". We also don't reverse intersegment "jmp" and "call"
2931 instructions with 2 immediate operands so that the immediate segment
2932 precedes the offset, as it does when in AT&T mode. */
2935 && (strcmp (mnemonic
, "bound") != 0)
2936 && (strcmp (mnemonic
, "invlpga") != 0)
2937 && !(operand_type_check (i
.types
[0], imm
)
2938 && operand_type_check (i
.types
[1], imm
)))
2941 /* The order of the immediates should be reversed
2942 for 2 immediates extrq and insertq instructions */
2943 if (i
.imm_operands
== 2
2944 && (strcmp (mnemonic
, "extrq") == 0
2945 || strcmp (mnemonic
, "insertq") == 0))
2946 swap_2_operands (0, 1);
2951 /* Don't optimize displacement for movabs since it only takes 64bit
2954 && (flag_code
!= CODE_64BIT
2955 || strcmp (mnemonic
, "movabs") != 0))
2958 /* Next, we find a template that matches the given insn,
2959 making sure the overlap of the given operands types is consistent
2960 with the template operand types. */
2962 if (!(t
= match_template ()))
2965 if (sse_check
!= sse_check_none
2966 && !i
.tm
.opcode_modifier
.noavx
2967 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2968 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2969 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2970 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2971 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2972 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2974 (sse_check
== sse_check_warning
2976 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2979 /* Zap movzx and movsx suffix. The suffix has been set from
2980 "word ptr" or "byte ptr" on the source operand in Intel syntax
2981 or extracted from mnemonic in AT&T syntax. But we'll use
2982 the destination register to choose the suffix for encoding. */
2983 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2985 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2986 there is no suffix, the default will be byte extension. */
2987 if (i
.reg_operands
!= 2
2990 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2995 if (i
.tm
.opcode_modifier
.fwait
)
2996 if (!add_prefix (FWAIT_OPCODE
))
2999 /* Check for lock without a lockable instruction. Destination operand
3000 must be memory unless it is xchg (0x86). */
3001 if (i
.prefix
[LOCK_PREFIX
]
3002 && (!i
.tm
.opcode_modifier
.islockable
3003 || i
.mem_operands
== 0
3004 || (i
.tm
.base_opcode
!= 0x86
3005 && !operand_type_check (i
.types
[i
.operands
- 1], anymem
))))
3007 as_bad (_("expecting lockable instruction after `lock'"));
3011 /* Check string instruction segment overrides. */
3012 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
3014 if (!check_string ())
3016 i
.disp_operands
= 0;
3019 if (!process_suffix ())
3022 /* Update operand types. */
3023 for (j
= 0; j
< i
.operands
; j
++)
3024 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
3026 /* Make still unresolved immediate matches conform to size of immediate
3027 given in i.suffix. */
3028 if (!finalize_imm ())
3031 if (i
.types
[0].bitfield
.imm1
)
3032 i
.imm_operands
= 0; /* kludge for shift insns. */
3034 /* We only need to check those implicit registers for instructions
3035 with 3 operands or less. */
3036 if (i
.operands
<= 3)
3037 for (j
= 0; j
< i
.operands
; j
++)
3038 if (i
.types
[j
].bitfield
.inoutportreg
3039 || i
.types
[j
].bitfield
.shiftcount
3040 || i
.types
[j
].bitfield
.acc
3041 || i
.types
[j
].bitfield
.floatacc
)
3044 /* ImmExt should be processed after SSE2AVX. */
3045 if (!i
.tm
.opcode_modifier
.sse2avx
3046 && i
.tm
.opcode_modifier
.immext
)
3049 /* For insns with operands there are more diddles to do to the opcode. */
3052 if (!process_operands ())
3055 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
3057 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
3058 as_warn (_("translating to `%sp'"), i
.tm
.name
);
3061 if (i
.tm
.opcode_modifier
.vex
)
3062 build_vex_prefix (t
);
3064 /* Handle conversion of 'int $3' --> special int3 insn. XOP or FMA4
3065 instructions may define INT_OPCODE as well, so avoid this corner
3066 case for those instructions that use MODRM. */
3067 if (i
.tm
.base_opcode
== INT_OPCODE
3068 && !i
.tm
.opcode_modifier
.modrm
3069 && i
.op
[0].imms
->X_add_number
== 3)
3071 i
.tm
.base_opcode
= INT3_OPCODE
;
3075 if ((i
.tm
.opcode_modifier
.jump
3076 || i
.tm
.opcode_modifier
.jumpbyte
3077 || i
.tm
.opcode_modifier
.jumpdword
)
3078 && i
.op
[0].disps
->X_op
== O_constant
)
3080 /* Convert "jmp constant" (and "call constant") to a jump (call) to
3081 the absolute address given by the constant. Since ix86 jumps and
3082 calls are pc relative, we need to generate a reloc. */
3083 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
3084 i
.op
[0].disps
->X_op
= O_symbol
;
3087 if (i
.tm
.opcode_modifier
.rex64
)
3090 /* For 8 bit registers we need an empty rex prefix. Also if the
3091 instruction already has a prefix, we need to convert old
3092 registers to new ones. */
3094 if ((i
.types
[0].bitfield
.reg8
3095 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
3096 || (i
.types
[1].bitfield
.reg8
3097 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3098 || ((i
.types
[0].bitfield
.reg8
3099 || i
.types
[1].bitfield
.reg8
)
3104 i
.rex
|= REX_OPCODE
;
3105 for (x
= 0; x
< 2; x
++)
3107 /* Look for 8 bit operand that uses old registers. */
3108 if (i
.types
[x
].bitfield
.reg8
3109 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3111 /* In case it is "hi" register, give up. */
3112 if (i
.op
[x
].regs
->reg_num
> 3)
3113 as_bad (_("can't encode register '%s%s' in an "
3114 "instruction requiring REX prefix."),
3115 register_prefix
, i
.op
[x
].regs
->reg_name
);
3117 /* Otherwise it is equivalent to the extended register.
3118 Since the encoding doesn't change this is merely
3119 cosmetic cleanup for debug output. */
3121 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3127 add_prefix (REX_OPCODE
| i
.rex
);
3129 /* We are ready to output the insn. */
3134 parse_insn (char *line
, char *mnemonic
)
3137 char *token_start
= l
;
3140 const insn_template
*t
;
3143 /* Non-zero if we found a prefix only acceptable with string insns. */
3144 const char *expecting_string_instruction
= NULL
;
3149 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3154 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3156 as_bad (_("no such instruction: `%s'"), token_start
);
3161 if (!is_space_char (*l
)
3162 && *l
!= END_OF_INSN
3164 || (*l
!= PREFIX_SEPARATOR
3167 as_bad (_("invalid character %s in mnemonic"),
3168 output_invalid (*l
));
3171 if (token_start
== l
)
3173 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3174 as_bad (_("expecting prefix; got nothing"));
3176 as_bad (_("expecting mnemonic; got nothing"));
3180 /* Look up instruction (or prefix) via hash table. */
3181 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3183 if (*l
!= END_OF_INSN
3184 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3185 && current_templates
3186 && current_templates
->start
->opcode_modifier
.isprefix
)
3188 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3190 as_bad ((flag_code
!= CODE_64BIT
3191 ? _("`%s' is only supported in 64-bit mode")
3192 : _("`%s' is not supported in 64-bit mode")),
3193 current_templates
->start
->name
);
3196 /* If we are in 16-bit mode, do not allow addr16 or data16.
3197 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3198 if ((current_templates
->start
->opcode_modifier
.size16
3199 || current_templates
->start
->opcode_modifier
.size32
)
3200 && flag_code
!= CODE_64BIT
3201 && (current_templates
->start
->opcode_modifier
.size32
3202 ^ (flag_code
== CODE_16BIT
)))
3204 as_bad (_("redundant %s prefix"),
3205 current_templates
->start
->name
);
3208 /* Add prefix, checking for repeated prefixes. */
3209 switch (add_prefix (current_templates
->start
->base_opcode
))
3214 expecting_string_instruction
= current_templates
->start
->name
;
3219 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3226 if (!current_templates
)
3228 /* Check if we should swap operand in encoding. */
3229 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3235 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3238 if (!current_templates
)
3241 /* See if we can get a match by trimming off a suffix. */
3244 case WORD_MNEM_SUFFIX
:
3245 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3246 i
.suffix
= SHORT_MNEM_SUFFIX
;
3248 case BYTE_MNEM_SUFFIX
:
3249 case QWORD_MNEM_SUFFIX
:
3250 i
.suffix
= mnem_p
[-1];
3252 current_templates
= (const templates
*) hash_find (op_hash
,
3255 case SHORT_MNEM_SUFFIX
:
3256 case LONG_MNEM_SUFFIX
:
3259 i
.suffix
= mnem_p
[-1];
3261 current_templates
= (const templates
*) hash_find (op_hash
,
3270 if (intel_float_operand (mnemonic
) == 1)
3271 i
.suffix
= SHORT_MNEM_SUFFIX
;
3273 i
.suffix
= LONG_MNEM_SUFFIX
;
3275 current_templates
= (const templates
*) hash_find (op_hash
,
3280 if (!current_templates
)
3282 as_bad (_("no such instruction: `%s'"), token_start
);
3287 if (current_templates
->start
->opcode_modifier
.jump
3288 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3290 /* Check for a branch hint. We allow ",pt" and ",pn" for
3291 predict taken and predict not taken respectively.
3292 I'm not sure that branch hints actually do anything on loop
3293 and jcxz insns (JumpByte) for current Pentium4 chips. They
3294 may work in the future and it doesn't hurt to accept them
3296 if (l
[0] == ',' && l
[1] == 'p')
3300 if (!add_prefix (DS_PREFIX_OPCODE
))
3304 else if (l
[2] == 'n')
3306 if (!add_prefix (CS_PREFIX_OPCODE
))
3312 /* Any other comma loses. */
3315 as_bad (_("invalid character %s in mnemonic"),
3316 output_invalid (*l
));
3320 /* Check if instruction is supported on specified architecture. */
3322 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3324 supported
|= cpu_flags_match (t
);
3325 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3329 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3331 as_bad (flag_code
== CODE_64BIT
3332 ? _("`%s' is not supported in 64-bit mode")
3333 : _("`%s' is only supported in 64-bit mode"),
3334 current_templates
->start
->name
);
3337 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3339 as_bad (_("`%s' is not supported on `%s%s'"),
3340 current_templates
->start
->name
,
3341 cpu_arch_name
? cpu_arch_name
: default_arch
,
3342 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3347 if (!cpu_arch_flags
.bitfield
.cpui386
3348 && (flag_code
!= CODE_16BIT
))
3350 as_warn (_("use .code16 to ensure correct addressing mode"));
3353 /* Check for rep/repne without a string instruction. */
3354 if (expecting_string_instruction
)
3356 static templates override
;
3358 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3359 if (t
->opcode_modifier
.isstring
)
3361 if (t
>= current_templates
->end
)
3363 as_bad (_("expecting string instruction after `%s'"),
3364 expecting_string_instruction
);
3367 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3368 if (!t
->opcode_modifier
.isstring
)
3371 current_templates
= &override
;
3378 parse_operands (char *l
, const char *mnemonic
)
3382 /* 1 if operand is pending after ','. */
3383 unsigned int expecting_operand
= 0;
3385 /* Non-zero if operand parens not balanced. */
3386 unsigned int paren_not_balanced
;
3388 while (*l
!= END_OF_INSN
)
3390 /* Skip optional white space before operand. */
3391 if (is_space_char (*l
))
3393 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3395 as_bad (_("invalid character %s before operand %d"),
3396 output_invalid (*l
),
3400 token_start
= l
; /* after white space */
3401 paren_not_balanced
= 0;
3402 while (paren_not_balanced
|| *l
!= ',')
3404 if (*l
== END_OF_INSN
)
3406 if (paren_not_balanced
)
3409 as_bad (_("unbalanced parenthesis in operand %d."),
3412 as_bad (_("unbalanced brackets in operand %d."),
3417 break; /* we are done */
3419 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3421 as_bad (_("invalid character %s in operand %d"),
3422 output_invalid (*l
),
3429 ++paren_not_balanced
;
3431 --paren_not_balanced
;
3436 ++paren_not_balanced
;
3438 --paren_not_balanced
;
3442 if (l
!= token_start
)
3443 { /* Yes, we've read in another operand. */
3444 unsigned int operand_ok
;
3445 this_operand
= i
.operands
++;
3446 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3447 if (i
.operands
> MAX_OPERANDS
)
3449 as_bad (_("spurious operands; (%d operands/instruction max)"),
3453 /* Now parse operand adding info to 'i' as we go along. */
3454 END_STRING_AND_SAVE (l
);
3458 i386_intel_operand (token_start
,
3459 intel_float_operand (mnemonic
));
3461 operand_ok
= i386_att_operand (token_start
);
3463 RESTORE_END_STRING (l
);
3469 if (expecting_operand
)
3471 expecting_operand_after_comma
:
3472 as_bad (_("expecting operand after ','; got nothing"));
3477 as_bad (_("expecting operand before ','; got nothing"));
3482 /* Now *l must be either ',' or END_OF_INSN. */
3485 if (*++l
== END_OF_INSN
)
3487 /* Just skip it, if it's \n complain. */
3488 goto expecting_operand_after_comma
;
3490 expecting_operand
= 1;
3497 swap_2_operands (int xchg1
, int xchg2
)
3499 union i386_op temp_op
;
3500 i386_operand_type temp_type
;
3501 enum bfd_reloc_code_real temp_reloc
;
3503 temp_type
= i
.types
[xchg2
];
3504 i
.types
[xchg2
] = i
.types
[xchg1
];
3505 i
.types
[xchg1
] = temp_type
;
3506 temp_op
= i
.op
[xchg2
];
3507 i
.op
[xchg2
] = i
.op
[xchg1
];
3508 i
.op
[xchg1
] = temp_op
;
3509 temp_reloc
= i
.reloc
[xchg2
];
3510 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3511 i
.reloc
[xchg1
] = temp_reloc
;
3515 swap_operands (void)
3521 swap_2_operands (1, i
.operands
- 2);
3524 swap_2_operands (0, i
.operands
- 1);
3530 if (i
.mem_operands
== 2)
3532 const seg_entry
*temp_seg
;
3533 temp_seg
= i
.seg
[0];
3534 i
.seg
[0] = i
.seg
[1];
3535 i
.seg
[1] = temp_seg
;
3539 /* Try to ensure constant immediates are represented in the smallest
3544 char guess_suffix
= 0;
3548 guess_suffix
= i
.suffix
;
3549 else if (i
.reg_operands
)
3551 /* Figure out a suffix from the last register operand specified.
3552 We can't do this properly yet, ie. excluding InOutPortReg,
3553 but the following works for instructions with immediates.
3554 In any case, we can't set i.suffix yet. */
3555 for (op
= i
.operands
; --op
>= 0;)
3556 if (i
.types
[op
].bitfield
.reg8
)
3558 guess_suffix
= BYTE_MNEM_SUFFIX
;
3561 else if (i
.types
[op
].bitfield
.reg16
)
3563 guess_suffix
= WORD_MNEM_SUFFIX
;
3566 else if (i
.types
[op
].bitfield
.reg32
)
3568 guess_suffix
= LONG_MNEM_SUFFIX
;
3571 else if (i
.types
[op
].bitfield
.reg64
)
3573 guess_suffix
= QWORD_MNEM_SUFFIX
;
3577 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3578 guess_suffix
= WORD_MNEM_SUFFIX
;
3580 for (op
= i
.operands
; --op
>= 0;)
3581 if (operand_type_check (i
.types
[op
], imm
))
3583 switch (i
.op
[op
].imms
->X_op
)
3586 /* If a suffix is given, this operand may be shortened. */
3587 switch (guess_suffix
)
3589 case LONG_MNEM_SUFFIX
:
3590 i
.types
[op
].bitfield
.imm32
= 1;
3591 i
.types
[op
].bitfield
.imm64
= 1;
3593 case WORD_MNEM_SUFFIX
:
3594 i
.types
[op
].bitfield
.imm16
= 1;
3595 i
.types
[op
].bitfield
.imm32
= 1;
3596 i
.types
[op
].bitfield
.imm32s
= 1;
3597 i
.types
[op
].bitfield
.imm64
= 1;
3599 case BYTE_MNEM_SUFFIX
:
3600 i
.types
[op
].bitfield
.imm8
= 1;
3601 i
.types
[op
].bitfield
.imm8s
= 1;
3602 i
.types
[op
].bitfield
.imm16
= 1;
3603 i
.types
[op
].bitfield
.imm32
= 1;
3604 i
.types
[op
].bitfield
.imm32s
= 1;
3605 i
.types
[op
].bitfield
.imm64
= 1;
3609 /* If this operand is at most 16 bits, convert it
3610 to a signed 16 bit number before trying to see
3611 whether it will fit in an even smaller size.
3612 This allows a 16-bit operand such as $0xffe0 to
3613 be recognised as within Imm8S range. */
3614 if ((i
.types
[op
].bitfield
.imm16
)
3615 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3617 i
.op
[op
].imms
->X_add_number
=
3618 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3620 if ((i
.types
[op
].bitfield
.imm32
)
3621 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3624 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3625 ^ ((offsetT
) 1 << 31))
3626 - ((offsetT
) 1 << 31));
3629 = operand_type_or (i
.types
[op
],
3630 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3632 /* We must avoid matching of Imm32 templates when 64bit
3633 only immediate is available. */
3634 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3635 i
.types
[op
].bitfield
.imm32
= 0;
3642 /* Symbols and expressions. */
3644 /* Convert symbolic operand to proper sizes for matching, but don't
3645 prevent matching a set of insns that only supports sizes other
3646 than those matching the insn suffix. */
3648 i386_operand_type mask
, allowed
;
3649 const insn_template
*t
;
3651 operand_type_set (&mask
, 0);
3652 operand_type_set (&allowed
, 0);
3654 for (t
= current_templates
->start
;
3655 t
< current_templates
->end
;
3657 allowed
= operand_type_or (allowed
,
3658 t
->operand_types
[op
]);
3659 switch (guess_suffix
)
3661 case QWORD_MNEM_SUFFIX
:
3662 mask
.bitfield
.imm64
= 1;
3663 mask
.bitfield
.imm32s
= 1;
3665 case LONG_MNEM_SUFFIX
:
3666 mask
.bitfield
.imm32
= 1;
3668 case WORD_MNEM_SUFFIX
:
3669 mask
.bitfield
.imm16
= 1;
3671 case BYTE_MNEM_SUFFIX
:
3672 mask
.bitfield
.imm8
= 1;
3677 allowed
= operand_type_and (mask
, allowed
);
3678 if (!operand_type_all_zero (&allowed
))
3679 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3686 /* Try to use the smallest displacement type too. */
3688 optimize_disp (void)
3692 for (op
= i
.operands
; --op
>= 0;)
3693 if (operand_type_check (i
.types
[op
], disp
))
3695 if (i
.op
[op
].disps
->X_op
== O_constant
)
3697 offsetT op_disp
= i
.op
[op
].disps
->X_add_number
;
3699 if (i
.types
[op
].bitfield
.disp16
3700 && (op_disp
& ~(offsetT
) 0xffff) == 0)
3702 /* If this operand is at most 16 bits, convert
3703 to a signed 16 bit number and don't use 64bit
3705 op_disp
= (((op_disp
& 0xffff) ^ 0x8000) - 0x8000);
3706 i
.types
[op
].bitfield
.disp64
= 0;
3708 if (i
.types
[op
].bitfield
.disp32
3709 && (op_disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3711 /* If this operand is at most 32 bits, convert
3712 to a signed 32 bit number and don't use 64bit
3714 op_disp
&= (((offsetT
) 2 << 31) - 1);
3715 op_disp
= (op_disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3716 i
.types
[op
].bitfield
.disp64
= 0;
3718 if (!op_disp
&& i
.types
[op
].bitfield
.baseindex
)
3720 i
.types
[op
].bitfield
.disp8
= 0;
3721 i
.types
[op
].bitfield
.disp16
= 0;
3722 i
.types
[op
].bitfield
.disp32
= 0;
3723 i
.types
[op
].bitfield
.disp32s
= 0;
3724 i
.types
[op
].bitfield
.disp64
= 0;
3728 else if (flag_code
== CODE_64BIT
)
3730 if (fits_in_signed_long (op_disp
))
3732 i
.types
[op
].bitfield
.disp64
= 0;
3733 i
.types
[op
].bitfield
.disp32s
= 1;
3735 if (i
.prefix
[ADDR_PREFIX
]
3736 && fits_in_unsigned_long (op_disp
))
3737 i
.types
[op
].bitfield
.disp32
= 1;
3739 if ((i
.types
[op
].bitfield
.disp32
3740 || i
.types
[op
].bitfield
.disp32s
3741 || i
.types
[op
].bitfield
.disp16
)
3742 && fits_in_signed_byte (op_disp
))
3743 i
.types
[op
].bitfield
.disp8
= 1;
3745 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3746 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3748 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3749 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3750 i
.types
[op
].bitfield
.disp8
= 0;
3751 i
.types
[op
].bitfield
.disp16
= 0;
3752 i
.types
[op
].bitfield
.disp32
= 0;
3753 i
.types
[op
].bitfield
.disp32s
= 0;
3754 i
.types
[op
].bitfield
.disp64
= 0;
3757 /* We only support 64bit displacement on constants. */
3758 i
.types
[op
].bitfield
.disp64
= 0;
3762 /* Check if operands are valid for the instrucrtion. Update VEX
3766 VEX_check_operands (const insn_template
*t
)
3768 if (!t
->opcode_modifier
.vex
)
3771 /* Only check VEX_Imm4, which must be the first operand. */
3772 if (t
->operand_types
[0].bitfield
.vec_imm4
)
3774 if (i
.op
[0].imms
->X_op
!= O_constant
3775 || !fits_in_imm4 (i
.op
[0].imms
->X_add_number
))
3781 /* Turn off Imm8 so that update_imm won't complain. */
3782 i
.types
[0] = vec_imm4
;
3788 static const insn_template
*
3789 match_template (void)
3791 /* Points to template once we've found it. */
3792 const insn_template
*t
;
3793 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3794 i386_operand_type overlap4
;
3795 unsigned int found_reverse_match
;
3796 i386_opcode_modifier suffix_check
;
3797 i386_operand_type operand_types
[MAX_OPERANDS
];
3798 int addr_prefix_disp
;
3800 unsigned int found_cpu_match
;
3801 unsigned int check_register
;
3803 #if MAX_OPERANDS != 5
3804 # error "MAX_OPERANDS must be 5."
3807 found_reverse_match
= 0;
3808 addr_prefix_disp
= -1;
3810 memset (&suffix_check
, 0, sizeof (suffix_check
));
3811 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3812 suffix_check
.no_bsuf
= 1;
3813 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3814 suffix_check
.no_wsuf
= 1;
3815 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3816 suffix_check
.no_ssuf
= 1;
3817 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3818 suffix_check
.no_lsuf
= 1;
3819 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3820 suffix_check
.no_qsuf
= 1;
3821 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3822 suffix_check
.no_ldsuf
= 1;
3824 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3826 addr_prefix_disp
= -1;
3828 /* Must have right number of operands. */
3829 i
.error
= number_of_operands_mismatch
;
3830 if (i
.operands
!= t
->operands
)
3833 /* Check processor support. */
3834 i
.error
= unsupported
;
3835 found_cpu_match
= (cpu_flags_match (t
)
3836 == CPU_FLAGS_PERFECT_MATCH
);
3837 if (!found_cpu_match
)
3840 /* Check old gcc support. */
3841 i
.error
= old_gcc_only
;
3842 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3845 /* Check AT&T mnemonic. */
3846 i
.error
= unsupported_with_intel_mnemonic
;
3847 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3850 /* Check AT&T/Intel syntax. */
3851 i
.error
= unsupported_syntax
;
3852 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3853 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3856 /* Check the suffix, except for some instructions in intel mode. */
3857 i
.error
= invalid_instruction_suffix
;
3858 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3859 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3860 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3861 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3862 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3863 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3864 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3867 if (!operand_size_match (t
))
3870 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3871 operand_types
[j
] = t
->operand_types
[j
];
3873 /* In general, don't allow 64-bit operands in 32-bit mode. */
3874 if (i
.suffix
== QWORD_MNEM_SUFFIX
3875 && flag_code
!= CODE_64BIT
3877 ? (!t
->opcode_modifier
.ignoresize
3878 && !intel_float_operand (t
->name
))
3879 : intel_float_operand (t
->name
) != 2)
3880 && ((!operand_types
[0].bitfield
.regmmx
3881 && !operand_types
[0].bitfield
.regxmm
3882 && !operand_types
[0].bitfield
.regymm
)
3883 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3884 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3885 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3886 && (t
->base_opcode
!= 0x0fc7
3887 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3890 /* In general, don't allow 32-bit operands on pre-386. */
3891 else if (i
.suffix
== LONG_MNEM_SUFFIX
3892 && !cpu_arch_flags
.bitfield
.cpui386
3894 ? (!t
->opcode_modifier
.ignoresize
3895 && !intel_float_operand (t
->name
))
3896 : intel_float_operand (t
->name
) != 2)
3897 && ((!operand_types
[0].bitfield
.regmmx
3898 && !operand_types
[0].bitfield
.regxmm
)
3899 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3900 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3903 /* Do not verify operands when there are none. */
3907 /* We've found a match; break out of loop. */
3911 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3912 into Disp32/Disp16/Disp32 operand. */
3913 if (i
.prefix
[ADDR_PREFIX
] != 0)
3915 /* There should be only one Disp operand. */
3919 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3921 if (operand_types
[j
].bitfield
.disp16
)
3923 addr_prefix_disp
= j
;
3924 operand_types
[j
].bitfield
.disp32
= 1;
3925 operand_types
[j
].bitfield
.disp16
= 0;
3931 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3933 if (operand_types
[j
].bitfield
.disp32
)
3935 addr_prefix_disp
= j
;
3936 operand_types
[j
].bitfield
.disp32
= 0;
3937 operand_types
[j
].bitfield
.disp16
= 1;
3943 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3945 if (operand_types
[j
].bitfield
.disp64
)
3947 addr_prefix_disp
= j
;
3948 operand_types
[j
].bitfield
.disp64
= 0;
3949 operand_types
[j
].bitfield
.disp32
= 1;
3957 /* We check register size only if size of operands can be
3958 encoded the canonical way. */
3959 check_register
= t
->opcode_modifier
.w
;
3960 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3961 switch (t
->operands
)
3964 if (!operand_type_match (overlap0
, i
.types
[0]))
3968 /* xchg %eax, %eax is a special case. It is an aliase for nop
3969 only in 32bit mode and we can use opcode 0x90. In 64bit
3970 mode, we can't use 0x90 for xchg %eax, %eax since it should
3971 zero-extend %eax to %rax. */
3972 if (flag_code
== CODE_64BIT
3973 && t
->base_opcode
== 0x90
3974 && operand_type_equal (&i
.types
[0], &acc32
)
3975 && operand_type_equal (&i
.types
[1], &acc32
))
3979 /* If we swap operand in encoding, we either match
3980 the next one or reverse direction of operands. */
3981 if (t
->opcode_modifier
.s
)
3983 else if (t
->opcode_modifier
.d
)
3988 /* If we swap operand in encoding, we match the next one. */
3989 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3993 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3994 if (!operand_type_match (overlap0
, i
.types
[0])
3995 || !operand_type_match (overlap1
, i
.types
[1])
3997 && !operand_type_register_match (overlap0
, i
.types
[0],
3999 overlap1
, i
.types
[1],
4002 /* Check if other direction is valid ... */
4003 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
4007 /* Try reversing direction of operands. */
4008 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
4009 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
4010 if (!operand_type_match (overlap0
, i
.types
[0])
4011 || !operand_type_match (overlap1
, i
.types
[1])
4013 && !operand_type_register_match (overlap0
,
4020 /* Does not match either direction. */
4023 /* found_reverse_match holds which of D or FloatDR
4025 if (t
->opcode_modifier
.d
)
4026 found_reverse_match
= Opcode_D
;
4027 else if (t
->opcode_modifier
.floatd
)
4028 found_reverse_match
= Opcode_FloatD
;
4030 found_reverse_match
= 0;
4031 if (t
->opcode_modifier
.floatr
)
4032 found_reverse_match
|= Opcode_FloatR
;
4036 /* Found a forward 2 operand match here. */
4037 switch (t
->operands
)
4040 overlap4
= operand_type_and (i
.types
[4],
4043 overlap3
= operand_type_and (i
.types
[3],
4046 overlap2
= operand_type_and (i
.types
[2],
4051 switch (t
->operands
)
4054 if (!operand_type_match (overlap4
, i
.types
[4])
4055 || !operand_type_register_match (overlap3
,
4063 if (!operand_type_match (overlap3
, i
.types
[3])
4065 && !operand_type_register_match (overlap2
,
4073 /* Here we make use of the fact that there are no
4074 reverse match 3 operand instructions, and all 3
4075 operand instructions only need to be checked for
4076 register consistency between operands 2 and 3. */
4077 if (!operand_type_match (overlap2
, i
.types
[2])
4079 && !operand_type_register_match (overlap1
,
4089 /* Found either forward/reverse 2, 3 or 4 operand match here:
4090 slip through to break. */
4092 if (!found_cpu_match
)
4094 found_reverse_match
= 0;
4098 /* Check if VEX operands are valid. */
4099 if (VEX_check_operands (t
))
4102 /* We've found a match; break out of loop. */
4106 if (t
== current_templates
->end
)
4108 /* We found no match. */
4109 const char *err_msg
;
4114 case operand_size_mismatch
:
4115 err_msg
= _("operand size mismatch");
4117 case operand_type_mismatch
:
4118 err_msg
= _("operand type mismatch");
4120 case register_type_mismatch
:
4121 err_msg
= _("register type mismatch");
4123 case number_of_operands_mismatch
:
4124 err_msg
= _("number of operands mismatch");
4126 case invalid_instruction_suffix
:
4127 err_msg
= _("invalid instruction suffix");
4130 err_msg
= _("Imm4 isn't the first operand");
4133 err_msg
= _("only supported with old gcc");
4135 case unsupported_with_intel_mnemonic
:
4136 err_msg
= _("unsupported with Intel mnemonic");
4138 case unsupported_syntax
:
4139 err_msg
= _("unsupported syntax");
4142 err_msg
= _("unsupported");
4145 as_bad (_("%s for `%s'"), err_msg
,
4146 current_templates
->start
->name
);
4150 if (!quiet_warnings
)
4153 && (i
.types
[0].bitfield
.jumpabsolute
4154 != operand_types
[0].bitfield
.jumpabsolute
))
4156 as_warn (_("indirect %s without `*'"), t
->name
);
4159 if (t
->opcode_modifier
.isprefix
4160 && t
->opcode_modifier
.ignoresize
)
4162 /* Warn them that a data or address size prefix doesn't
4163 affect assembly of the next line of code. */
4164 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4168 /* Copy the template we found. */
4171 if (addr_prefix_disp
!= -1)
4172 i
.tm
.operand_types
[addr_prefix_disp
]
4173 = operand_types
[addr_prefix_disp
];
4175 if (found_reverse_match
)
4177 /* If we found a reverse match we must alter the opcode
4178 direction bit. found_reverse_match holds bits to change
4179 (different for int & float insns). */
4181 i
.tm
.base_opcode
^= found_reverse_match
;
4183 i
.tm
.operand_types
[0] = operand_types
[1];
4184 i
.tm
.operand_types
[1] = operand_types
[0];
4193 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4194 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4196 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4198 as_bad (_("`%s' operand %d must use `%ses' segment"),
4204 /* There's only ever one segment override allowed per instruction.
4205 This instruction possibly has a legal segment override on the
4206 second operand, so copy the segment to where non-string
4207 instructions store it, allowing common code. */
4208 i
.seg
[0] = i
.seg
[1];
4210 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4212 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4214 as_bad (_("`%s' operand %d must use `%ses' segment"),
4225 process_suffix (void)
4227 /* If matched instruction specifies an explicit instruction mnemonic
4229 if (i
.tm
.opcode_modifier
.size16
)
4230 i
.suffix
= WORD_MNEM_SUFFIX
;
4231 else if (i
.tm
.opcode_modifier
.size32
)
4232 i
.suffix
= LONG_MNEM_SUFFIX
;
4233 else if (i
.tm
.opcode_modifier
.size64
)
4234 i
.suffix
= QWORD_MNEM_SUFFIX
;
4235 else if (i
.reg_operands
)
4237 /* If there's no instruction mnemonic suffix we try to invent one
4238 based on register operands. */
4241 /* We take i.suffix from the last register operand specified,
4242 Destination register type is more significant than source
4243 register type. crc32 in SSE4.2 prefers source register
4245 if (i
.tm
.base_opcode
== 0xf20f38f1)
4247 if (i
.types
[0].bitfield
.reg16
)
4248 i
.suffix
= WORD_MNEM_SUFFIX
;
4249 else if (i
.types
[0].bitfield
.reg32
)
4250 i
.suffix
= LONG_MNEM_SUFFIX
;
4251 else if (i
.types
[0].bitfield
.reg64
)
4252 i
.suffix
= QWORD_MNEM_SUFFIX
;
4254 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4256 if (i
.types
[0].bitfield
.reg8
)
4257 i
.suffix
= BYTE_MNEM_SUFFIX
;
4264 if (i
.tm
.base_opcode
== 0xf20f38f1
4265 || i
.tm
.base_opcode
== 0xf20f38f0)
4267 /* We have to know the operand size for crc32. */
4268 as_bad (_("ambiguous memory operand size for `%s`"),
4273 for (op
= i
.operands
; --op
>= 0;)
4274 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4276 if (i
.types
[op
].bitfield
.reg8
)
4278 i
.suffix
= BYTE_MNEM_SUFFIX
;
4281 else if (i
.types
[op
].bitfield
.reg16
)
4283 i
.suffix
= WORD_MNEM_SUFFIX
;
4286 else if (i
.types
[op
].bitfield
.reg32
)
4288 i
.suffix
= LONG_MNEM_SUFFIX
;
4291 else if (i
.types
[op
].bitfield
.reg64
)
4293 i
.suffix
= QWORD_MNEM_SUFFIX
;
4299 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4302 && i
.tm
.opcode_modifier
.ignoresize
4303 && i
.tm
.opcode_modifier
.no_bsuf
)
4305 else if (!check_byte_reg ())
4308 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4311 && i
.tm
.opcode_modifier
.ignoresize
4312 && i
.tm
.opcode_modifier
.no_lsuf
)
4314 else if (!check_long_reg ())
4317 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4320 && i
.tm
.opcode_modifier
.ignoresize
4321 && i
.tm
.opcode_modifier
.no_qsuf
)
4323 else if (!check_qword_reg ())
4326 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4329 && i
.tm
.opcode_modifier
.ignoresize
4330 && i
.tm
.opcode_modifier
.no_wsuf
)
4332 else if (!check_word_reg ())
4335 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4336 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4338 /* Skip if the instruction has x/y suffix. match_template
4339 should check if it is a valid suffix. */
4341 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4342 /* Do nothing if the instruction is going to ignore the prefix. */
4347 else if (i
.tm
.opcode_modifier
.defaultsize
4349 /* exclude fldenv/frstor/fsave/fstenv */
4350 && i
.tm
.opcode_modifier
.no_ssuf
)
4352 i
.suffix
= stackop_size
;
4354 else if (intel_syntax
4356 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4357 || i
.tm
.opcode_modifier
.jumpbyte
4358 || i
.tm
.opcode_modifier
.jumpintersegment
4359 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4360 && i
.tm
.extension_opcode
<= 3)))
4365 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4367 i
.suffix
= QWORD_MNEM_SUFFIX
;
4371 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4372 i
.suffix
= LONG_MNEM_SUFFIX
;
4375 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4376 i
.suffix
= WORD_MNEM_SUFFIX
;
4385 if (i
.tm
.opcode_modifier
.w
)
4387 as_bad (_("no instruction mnemonic suffix given and "
4388 "no register operands; can't size instruction"));
4394 unsigned int suffixes
;
4396 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4397 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4399 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4401 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4403 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4405 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4408 /* There are more than suffix matches. */
4409 if (i
.tm
.opcode_modifier
.w
4410 || ((suffixes
& (suffixes
- 1))
4411 && !i
.tm
.opcode_modifier
.defaultsize
4412 && !i
.tm
.opcode_modifier
.ignoresize
))
4414 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4420 /* Change the opcode based on the operand size given by i.suffix;
4421 We don't need to change things for byte insns. */
4424 && i
.suffix
!= BYTE_MNEM_SUFFIX
4425 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4426 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4428 /* It's not a byte, select word/dword operation. */
4429 if (i
.tm
.opcode_modifier
.w
)
4431 if (i
.tm
.opcode_modifier
.shortform
)
4432 i
.tm
.base_opcode
|= 8;
4434 i
.tm
.base_opcode
|= 1;
4437 /* Now select between word & dword operations via the operand
4438 size prefix, except for instructions that will ignore this
4440 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4442 /* The address size override prefix changes the size of the
4444 if ((flag_code
== CODE_32BIT
4445 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4446 || (flag_code
!= CODE_32BIT
4447 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4448 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4451 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4452 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4453 && !i
.tm
.opcode_modifier
.ignoresize
4454 && !i
.tm
.opcode_modifier
.floatmf
4455 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4456 || (flag_code
== CODE_64BIT
4457 && i
.tm
.opcode_modifier
.jumpbyte
)))
4459 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4461 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4462 prefix
= ADDR_PREFIX_OPCODE
;
4464 if (!add_prefix (prefix
))
4468 /* Set mode64 for an operand. */
4469 if (i
.suffix
== QWORD_MNEM_SUFFIX
4470 && flag_code
== CODE_64BIT
4471 && !i
.tm
.opcode_modifier
.norex64
)
4473 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4474 need rex64. cmpxchg8b is also a special case. */
4475 if (! (i
.operands
== 2
4476 && i
.tm
.base_opcode
== 0x90
4477 && i
.tm
.extension_opcode
== None
4478 && operand_type_equal (&i
.types
[0], &acc64
)
4479 && operand_type_equal (&i
.types
[1], &acc64
))
4480 && ! (i
.operands
== 1
4481 && i
.tm
.base_opcode
== 0xfc7
4482 && i
.tm
.extension_opcode
== 1
4483 && !operand_type_check (i
.types
[0], reg
)
4484 && operand_type_check (i
.types
[0], anymem
)))
4488 /* Size floating point instruction. */
4489 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4490 if (i
.tm
.opcode_modifier
.floatmf
)
4491 i
.tm
.base_opcode
^= 4;
4498 check_byte_reg (void)
4502 for (op
= i
.operands
; --op
>= 0;)
4504 /* If this is an eight bit register, it's OK. If it's the 16 or
4505 32 bit version of an eight bit register, we will just use the
4506 low portion, and that's OK too. */
4507 if (i
.types
[op
].bitfield
.reg8
)
4510 /* crc32 doesn't generate this warning. */
4511 if (i
.tm
.base_opcode
== 0xf20f38f0)
4514 if ((i
.types
[op
].bitfield
.reg16
4515 || i
.types
[op
].bitfield
.reg32
4516 || i
.types
[op
].bitfield
.reg64
)
4517 && i
.op
[op
].regs
->reg_num
< 4)
4519 /* Prohibit these changes in the 64bit mode, since the
4520 lowering is more complicated. */
4521 if (flag_code
== CODE_64BIT
4522 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4524 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4525 register_prefix
, i
.op
[op
].regs
->reg_name
,
4529 #if REGISTER_WARNINGS
4531 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4532 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4534 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4535 ? REGNAM_AL
- REGNAM_AX
4536 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4538 i
.op
[op
].regs
->reg_name
,
4543 /* Any other register is bad. */
4544 if (i
.types
[op
].bitfield
.reg16
4545 || i
.types
[op
].bitfield
.reg32
4546 || i
.types
[op
].bitfield
.reg64
4547 || i
.types
[op
].bitfield
.regmmx
4548 || i
.types
[op
].bitfield
.regxmm
4549 || i
.types
[op
].bitfield
.regymm
4550 || i
.types
[op
].bitfield
.sreg2
4551 || i
.types
[op
].bitfield
.sreg3
4552 || i
.types
[op
].bitfield
.control
4553 || i
.types
[op
].bitfield
.debug
4554 || i
.types
[op
].bitfield
.test
4555 || i
.types
[op
].bitfield
.floatreg
4556 || i
.types
[op
].bitfield
.floatacc
)
4558 as_bad (_("`%s%s' not allowed with `%s%c'"),
4560 i
.op
[op
].regs
->reg_name
,
4570 check_long_reg (void)
4574 for (op
= i
.operands
; --op
>= 0;)
4575 /* Reject eight bit registers, except where the template requires
4576 them. (eg. movzb) */
4577 if (i
.types
[op
].bitfield
.reg8
4578 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4579 || i
.tm
.operand_types
[op
].bitfield
.reg32
4580 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4582 as_bad (_("`%s%s' not allowed with `%s%c'"),
4584 i
.op
[op
].regs
->reg_name
,
4589 /* Warn if the e prefix on a general reg is missing. */
4590 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4591 && i
.types
[op
].bitfield
.reg16
4592 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4593 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4595 /* Prohibit these changes in the 64bit mode, since the
4596 lowering is more complicated. */
4597 if (flag_code
== CODE_64BIT
)
4599 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4600 register_prefix
, i
.op
[op
].regs
->reg_name
,
4604 #if REGISTER_WARNINGS
4606 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4608 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4610 i
.op
[op
].regs
->reg_name
,
4614 /* Warn if the r prefix on a general reg is missing. */
4615 else if (i
.types
[op
].bitfield
.reg64
4616 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4617 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4620 && i
.tm
.opcode_modifier
.toqword
4621 && !i
.types
[0].bitfield
.regxmm
)
4623 /* Convert to QWORD. We want REX byte. */
4624 i
.suffix
= QWORD_MNEM_SUFFIX
;
4628 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4629 register_prefix
, i
.op
[op
].regs
->reg_name
,
4638 check_qword_reg (void)
4642 for (op
= i
.operands
; --op
>= 0; )
4643 /* Reject eight bit registers, except where the template requires
4644 them. (eg. movzb) */
4645 if (i
.types
[op
].bitfield
.reg8
4646 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4647 || i
.tm
.operand_types
[op
].bitfield
.reg32
4648 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4650 as_bad (_("`%s%s' not allowed with `%s%c'"),
4652 i
.op
[op
].regs
->reg_name
,
4657 /* Warn if the e prefix on a general reg is missing. */
4658 else if ((i
.types
[op
].bitfield
.reg16
4659 || i
.types
[op
].bitfield
.reg32
)
4660 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4661 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4663 /* Prohibit these changes in the 64bit mode, since the
4664 lowering is more complicated. */
4666 && i
.tm
.opcode_modifier
.todword
4667 && !i
.types
[0].bitfield
.regxmm
)
4669 /* Convert to DWORD. We don't want REX byte. */
4670 i
.suffix
= LONG_MNEM_SUFFIX
;
4674 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4675 register_prefix
, i
.op
[op
].regs
->reg_name
,
4684 check_word_reg (void)
4687 for (op
= i
.operands
; --op
>= 0;)
4688 /* Reject eight bit registers, except where the template requires
4689 them. (eg. movzb) */
4690 if (i
.types
[op
].bitfield
.reg8
4691 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4692 || i
.tm
.operand_types
[op
].bitfield
.reg32
4693 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4695 as_bad (_("`%s%s' not allowed with `%s%c'"),
4697 i
.op
[op
].regs
->reg_name
,
4702 /* Warn if the e prefix on a general reg is present. */
4703 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4704 && i
.types
[op
].bitfield
.reg32
4705 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4706 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4708 /* Prohibit these changes in the 64bit mode, since the
4709 lowering is more complicated. */
4710 if (flag_code
== CODE_64BIT
)
4712 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4713 register_prefix
, i
.op
[op
].regs
->reg_name
,
4718 #if REGISTER_WARNINGS
4719 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4721 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4723 i
.op
[op
].regs
->reg_name
,
4731 update_imm (unsigned int j
)
4733 i386_operand_type overlap
= i
.types
[j
];
4734 if ((overlap
.bitfield
.imm8
4735 || overlap
.bitfield
.imm8s
4736 || overlap
.bitfield
.imm16
4737 || overlap
.bitfield
.imm32
4738 || overlap
.bitfield
.imm32s
4739 || overlap
.bitfield
.imm64
)
4740 && !operand_type_equal (&overlap
, &imm8
)
4741 && !operand_type_equal (&overlap
, &imm8s
)
4742 && !operand_type_equal (&overlap
, &imm16
)
4743 && !operand_type_equal (&overlap
, &imm32
)
4744 && !operand_type_equal (&overlap
, &imm32s
)
4745 && !operand_type_equal (&overlap
, &imm64
))
4749 i386_operand_type temp
;
4751 operand_type_set (&temp
, 0);
4752 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4754 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4755 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4757 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4758 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4759 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4761 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4762 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4765 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4768 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4769 || operand_type_equal (&overlap
, &imm16_32
)
4770 || operand_type_equal (&overlap
, &imm16_32s
))
4772 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4777 if (!operand_type_equal (&overlap
, &imm8
)
4778 && !operand_type_equal (&overlap
, &imm8s
)
4779 && !operand_type_equal (&overlap
, &imm16
)
4780 && !operand_type_equal (&overlap
, &imm32
)
4781 && !operand_type_equal (&overlap
, &imm32s
)
4782 && !operand_type_equal (&overlap
, &imm64
))
4784 as_bad (_("no instruction mnemonic suffix given; "
4785 "can't determine immediate size"));
4789 i
.types
[j
] = overlap
;
4799 /* Update the first 2 immediate operands. */
4800 n
= i
.operands
> 2 ? 2 : i
.operands
;
4803 for (j
= 0; j
< n
; j
++)
4804 if (update_imm (j
) == 0)
4807 /* The 3rd operand can't be immediate operand. */
4808 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4815 bad_implicit_operand (int xmm
)
4817 const char *ireg
= xmm
? "xmm0" : "ymm0";
4820 as_bad (_("the last operand of `%s' must be `%s%s'"),
4821 i
.tm
.name
, register_prefix
, ireg
);
4823 as_bad (_("the first operand of `%s' must be `%s%s'"),
4824 i
.tm
.name
, register_prefix
, ireg
);
4829 process_operands (void)
4831 /* Default segment register this instruction will use for memory
4832 accesses. 0 means unknown. This is only for optimizing out
4833 unnecessary segment overrides. */
4834 const seg_entry
*default_seg
= 0;
4836 if (i
.tm
.opcode_modifier
.sse2avx
&& i
.tm
.opcode_modifier
.vexvvvv
)
4838 unsigned int dupl
= i
.operands
;
4839 unsigned int dest
= dupl
- 1;
4842 /* The destination must be an xmm register. */
4843 gas_assert (i
.reg_operands
4844 && MAX_OPERANDS
> dupl
4845 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4847 if (i
.tm
.opcode_modifier
.firstxmm0
)
4849 /* The first operand is implicit and must be xmm0. */
4850 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4851 if (i
.op
[0].regs
->reg_num
!= 0)
4852 return bad_implicit_operand (1);
4854 if (i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
)
4856 /* Keep xmm0 for instructions with VEX prefix and 3
4862 /* We remove the first xmm0 and keep the number of
4863 operands unchanged, which in fact duplicates the
4865 for (j
= 1; j
< i
.operands
; j
++)
4867 i
.op
[j
- 1] = i
.op
[j
];
4868 i
.types
[j
- 1] = i
.types
[j
];
4869 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4873 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4875 gas_assert ((MAX_OPERANDS
- 1) > dupl
4876 && (i
.tm
.opcode_modifier
.vexsources
4879 /* Add the implicit xmm0 for instructions with VEX prefix
4881 for (j
= i
.operands
; j
> 0; j
--)
4883 i
.op
[j
] = i
.op
[j
- 1];
4884 i
.types
[j
] = i
.types
[j
- 1];
4885 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4888 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4889 i
.types
[0] = regxmm
;
4890 i
.tm
.operand_types
[0] = regxmm
;
4893 i
.reg_operands
+= 2;
4898 i
.op
[dupl
] = i
.op
[dest
];
4899 i
.types
[dupl
] = i
.types
[dest
];
4900 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4909 i
.op
[dupl
] = i
.op
[dest
];
4910 i
.types
[dupl
] = i
.types
[dest
];
4911 i
.tm
.operand_types
[dupl
] = i
.tm
.operand_types
[dest
];
4914 if (i
.tm
.opcode_modifier
.immext
)
4917 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4921 /* The first operand is implicit and must be xmm0/ymm0. */
4922 gas_assert (i
.reg_operands
4923 && (operand_type_equal (&i
.types
[0], ®xmm
)
4924 || operand_type_equal (&i
.types
[0], ®ymm
)));
4925 if (i
.op
[0].regs
->reg_num
!= 0)
4926 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4928 for (j
= 1; j
< i
.operands
; j
++)
4930 i
.op
[j
- 1] = i
.op
[j
];
4931 i
.types
[j
- 1] = i
.types
[j
];
4933 /* We need to adjust fields in i.tm since they are used by
4934 build_modrm_byte. */
4935 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4942 else if (i
.tm
.opcode_modifier
.regkludge
)
4944 /* The imul $imm, %reg instruction is converted into
4945 imul $imm, %reg, %reg, and the clr %reg instruction
4946 is converted into xor %reg, %reg. */
4948 unsigned int first_reg_op
;
4950 if (operand_type_check (i
.types
[0], reg
))
4954 /* Pretend we saw the extra register operand. */
4955 gas_assert (i
.reg_operands
== 1
4956 && i
.op
[first_reg_op
+ 1].regs
== 0);
4957 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4958 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4963 if (i
.tm
.opcode_modifier
.shortform
)
4965 if (i
.types
[0].bitfield
.sreg2
4966 || i
.types
[0].bitfield
.sreg3
)
4968 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4969 && i
.op
[0].regs
->reg_num
== 1)
4971 as_bad (_("you can't `pop %scs'"), register_prefix
);
4974 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4975 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4980 /* The register or float register operand is in operand
4984 if (i
.types
[0].bitfield
.floatreg
4985 || operand_type_check (i
.types
[0], reg
))
4989 /* Register goes in low 3 bits of opcode. */
4990 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4991 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4993 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4995 /* Warn about some common errors, but press on regardless.
4996 The first case can be generated by gcc (<= 2.8.1). */
4997 if (i
.operands
== 2)
4999 /* Reversed arguments on faddp, fsubp, etc. */
5000 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
5001 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
5002 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
5006 /* Extraneous `l' suffix on fp insn. */
5007 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
5008 register_prefix
, i
.op
[0].regs
->reg_name
);
5013 else if (i
.tm
.opcode_modifier
.modrm
)
5015 /* The opcode is completed (modulo i.tm.extension_opcode which
5016 must be put into the modrm byte). Now, we make the modrm and
5017 index base bytes based on all the info we've collected. */
5019 default_seg
= build_modrm_byte ();
5021 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
5025 else if (i
.tm
.opcode_modifier
.isstring
)
5027 /* For the string instructions that allow a segment override
5028 on one of their operands, the default segment is ds. */
5032 if (i
.tm
.base_opcode
== 0x8d /* lea */
5035 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
5037 /* If a segment was explicitly specified, and the specified segment
5038 is not the default, use an opcode prefix to select it. If we
5039 never figured out what the default segment is, then default_seg
5040 will be zero at this point, and the specified segment prefix will
5042 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
5044 if (!add_prefix (i
.seg
[0]->seg_prefix
))
5050 static const seg_entry
*
5051 build_modrm_byte (void)
5053 const seg_entry
*default_seg
= 0;
5054 unsigned int source
, dest
;
5057 /* The first operand of instructions with VEX prefix and 3 sources
5058 must be VEX_Imm4. */
5059 vex_3_sources
= i
.tm
.opcode_modifier
.vexsources
== VEX3SOURCES
;
5062 unsigned int nds
, reg_slot
;
5065 if (i
.tm
.opcode_modifier
.veximmext
5066 && i
.tm
.opcode_modifier
.immext
)
5068 dest
= i
.operands
- 2;
5069 gas_assert (dest
== 3);
5072 dest
= i
.operands
- 1;
5075 /* There are 2 kinds of instructions:
5076 1. 5 operands: 4 register operands or 3 register operands
5077 plus 1 memory operand plus one Vec_Imm4 operand, VexXDS, and
5078 VexW0 or VexW1. The destination must be either XMM or YMM
5080 2. 4 operands: 4 register operands or 3 register operands
5081 plus 1 memory operand, VexXDS, and VexImmExt */
5082 gas_assert ((i
.reg_operands
== 4
5083 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
5084 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5085 && (i
.tm
.opcode_modifier
.veximmext
5086 || (i
.imm_operands
== 1
5087 && i
.types
[0].bitfield
.vec_imm4
5088 && (i
.tm
.opcode_modifier
.vexw
== VEXW0
5089 || i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5090 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
5091 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)))));
5093 if (i
.imm_operands
== 0)
5095 /* When there is no immediate operand, generate an 8bit
5096 immediate operand to encode the first operand. */
5097 exp
= &im_expressions
[i
.imm_operands
++];
5098 i
.op
[i
.operands
].imms
= exp
;
5099 i
.types
[i
.operands
] = imm8
;
5101 /* If VexW1 is set, the first operand is the source and
5102 the second operand is encoded in the immediate operand. */
5103 if (i
.tm
.opcode_modifier
.vexw
== VEXW1
)
5114 /* FMA swaps REG and NDS. */
5115 if (i
.tm
.cpu_flags
.bitfield
.cpufma
)
5123 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5125 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5127 exp
->X_op
= O_constant
;
5129 = ((i
.op
[reg_slot
].regs
->reg_num
5130 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5135 unsigned int imm_slot
;
5137 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5139 /* If VexW0 is set, the third operand is the source and
5140 the second operand is encoded in the immediate
5147 /* VexW1 is set, the second operand is the source and
5148 the third operand is encoded in the immediate
5154 if (i
.tm
.opcode_modifier
.immext
)
5156 /* When ImmExt is set, the immdiate byte is the last
5158 imm_slot
= i
.operands
- 1;
5166 /* Turn on Imm8 so that output_imm will generate it. */
5167 i
.types
[imm_slot
].bitfield
.imm8
= 1;
5170 gas_assert (operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5172 || operand_type_equal (&i
.tm
.operand_types
[reg_slot
],
5174 i
.op
[imm_slot
].imms
->X_add_number
5175 |= ((i
.op
[reg_slot
].regs
->reg_num
5176 + ((i
.op
[reg_slot
].regs
->reg_flags
& RegRex
) ? 8 : 0))
5180 gas_assert (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
5181 || operand_type_equal (&i
.tm
.operand_types
[nds
],
5183 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
5188 /* i.reg_operands MUST be the number of real register operands;
5189 implicit registers do not count. If there are 3 register
5190 operands, it must be a instruction with VexNDS. For a
5191 instruction with VexNDD, the destination register is encoded
5192 in VEX prefix. If there are 4 register operands, it must be
5193 a instruction with VEX prefix and 3 sources. */
5194 if (i
.mem_operands
== 0
5195 && ((i
.reg_operands
== 2
5196 && i
.tm
.opcode_modifier
.vexvvvv
<= VEXXDS
)
5197 || (i
.reg_operands
== 3
5198 && i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5199 || (i
.reg_operands
== 4 && vex_3_sources
)))
5207 /* When there are 3 operands, one of them may be immediate,
5208 which may be the first or the last operand. Otherwise,
5209 the first operand must be shift count register (cl) or it
5210 is an instruction with VexNDS. */
5211 gas_assert (i
.imm_operands
== 1
5212 || (i
.imm_operands
== 0
5213 && (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5214 || i
.types
[0].bitfield
.shiftcount
)));
5215 if (operand_type_check (i
.types
[0], imm
)
5216 || i
.types
[0].bitfield
.shiftcount
)
5222 /* When there are 4 operands, the first two must be 8bit
5223 immediate operands. The source operand will be the 3rd
5226 For instructions with VexNDS, if the first operand
5227 an imm8, the source operand is the 2nd one. If the last
5228 operand is imm8, the source operand is the first one. */
5229 gas_assert ((i
.imm_operands
== 2
5230 && i
.types
[0].bitfield
.imm8
5231 && i
.types
[1].bitfield
.imm8
)
5232 || (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
5233 && i
.imm_operands
== 1
5234 && (i
.types
[0].bitfield
.imm8
5235 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
5236 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5238 if (i
.types
[0].bitfield
.imm8
)
5256 if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5258 /* For instructions with VexNDS, the register-only
5259 source operand must be XMM or YMM register. It is
5260 encoded in VEX prefix. We need to clear RegMem bit
5261 before calling operand_type_equal. */
5262 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5263 op
.bitfield
.regmem
= 0;
5264 if ((dest
+ 1) >= i
.operands
5265 || (!operand_type_equal (&op
, ®xmm
)
5266 && !operand_type_equal (&op
, ®ymm
)))
5268 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5274 /* One of the register operands will be encoded in the i.tm.reg
5275 field, the other in the combined i.tm.mode and i.tm.regmem
5276 fields. If no form of this instruction supports a memory
5277 destination operand, then we assume the source operand may
5278 sometimes be a memory operand and so we need to store the
5279 destination in the i.rm.reg field. */
5280 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5281 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5283 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5284 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5285 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5287 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5292 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5293 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5294 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5296 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5299 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5301 if (!i
.types
[0].bitfield
.control
5302 && !i
.types
[1].bitfield
.control
)
5304 i
.rex
&= ~(REX_R
| REX_B
);
5305 add_prefix (LOCK_PREFIX_OPCODE
);
5309 { /* If it's not 2 reg operands... */
5314 unsigned int fake_zero_displacement
= 0;
5317 for (op
= 0; op
< i
.operands
; op
++)
5318 if (operand_type_check (i
.types
[op
], anymem
))
5320 gas_assert (op
< i
.operands
);
5324 if (i
.base_reg
== 0)
5327 if (!i
.disp_operands
)
5328 fake_zero_displacement
= 1;
5329 if (i
.index_reg
== 0)
5331 /* Operand is just <disp> */
5332 if (flag_code
== CODE_64BIT
)
5334 /* 64bit mode overwrites the 32bit absolute
5335 addressing by RIP relative addressing and
5336 absolute addressing is encoded by one of the
5337 redundant SIB forms. */
5338 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5339 i
.sib
.base
= NO_BASE_REGISTER
;
5340 i
.sib
.index
= NO_INDEX_REGISTER
;
5341 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5342 ? disp32s
: disp32
);
5344 else if ((flag_code
== CODE_16BIT
)
5345 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5347 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5348 i
.types
[op
] = disp16
;
5352 i
.rm
.regmem
= NO_BASE_REGISTER
;
5353 i
.types
[op
] = disp32
;
5356 else /* !i.base_reg && i.index_reg */
5358 if (i
.index_reg
->reg_num
== RegEiz
5359 || i
.index_reg
->reg_num
== RegRiz
)
5360 i
.sib
.index
= NO_INDEX_REGISTER
;
5362 i
.sib
.index
= i
.index_reg
->reg_num
;
5363 i
.sib
.base
= NO_BASE_REGISTER
;
5364 i
.sib
.scale
= i
.log2_scale_factor
;
5365 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5366 i
.types
[op
].bitfield
.disp8
= 0;
5367 i
.types
[op
].bitfield
.disp16
= 0;
5368 i
.types
[op
].bitfield
.disp64
= 0;
5369 if (flag_code
!= CODE_64BIT
)
5371 /* Must be 32 bit */
5372 i
.types
[op
].bitfield
.disp32
= 1;
5373 i
.types
[op
].bitfield
.disp32s
= 0;
5377 i
.types
[op
].bitfield
.disp32
= 0;
5378 i
.types
[op
].bitfield
.disp32s
= 1;
5380 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5384 /* RIP addressing for 64bit mode. */
5385 else if (i
.base_reg
->reg_num
== RegRip
||
5386 i
.base_reg
->reg_num
== RegEip
)
5388 i
.rm
.regmem
= NO_BASE_REGISTER
;
5389 i
.types
[op
].bitfield
.disp8
= 0;
5390 i
.types
[op
].bitfield
.disp16
= 0;
5391 i
.types
[op
].bitfield
.disp32
= 0;
5392 i
.types
[op
].bitfield
.disp32s
= 1;
5393 i
.types
[op
].bitfield
.disp64
= 0;
5394 i
.flags
[op
] |= Operand_PCrel
;
5395 if (! i
.disp_operands
)
5396 fake_zero_displacement
= 1;
5398 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5400 switch (i
.base_reg
->reg_num
)
5403 if (i
.index_reg
== 0)
5405 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5406 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5410 if (i
.index_reg
== 0)
5413 if (operand_type_check (i
.types
[op
], disp
) == 0)
5415 /* fake (%bp) into 0(%bp) */
5416 i
.types
[op
].bitfield
.disp8
= 1;
5417 fake_zero_displacement
= 1;
5420 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5421 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5423 default: /* (%si) -> 4 or (%di) -> 5 */
5424 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5426 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5428 else /* i.base_reg and 32/64 bit mode */
5430 if (flag_code
== CODE_64BIT
5431 && operand_type_check (i
.types
[op
], disp
))
5433 i386_operand_type temp
;
5434 operand_type_set (&temp
, 0);
5435 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5437 if (i
.prefix
[ADDR_PREFIX
] == 0)
5438 i
.types
[op
].bitfield
.disp32s
= 1;
5440 i
.types
[op
].bitfield
.disp32
= 1;
5443 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5444 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5446 i
.sib
.base
= i
.base_reg
->reg_num
;
5447 /* x86-64 ignores REX prefix bit here to avoid decoder
5449 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5452 if (i
.disp_operands
== 0)
5454 fake_zero_displacement
= 1;
5455 i
.types
[op
].bitfield
.disp8
= 1;
5458 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5462 i
.sib
.scale
= i
.log2_scale_factor
;
5463 if (i
.index_reg
== 0)
5465 /* <disp>(%esp) becomes two byte modrm with no index
5466 register. We've already stored the code for esp
5467 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5468 Any base register besides %esp will not use the
5469 extra modrm byte. */
5470 i
.sib
.index
= NO_INDEX_REGISTER
;
5474 if (i
.index_reg
->reg_num
== RegEiz
5475 || i
.index_reg
->reg_num
== RegRiz
)
5476 i
.sib
.index
= NO_INDEX_REGISTER
;
5478 i
.sib
.index
= i
.index_reg
->reg_num
;
5479 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5480 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5485 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5486 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5489 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5492 if (fake_zero_displacement
)
5494 /* Fakes a zero displacement assuming that i.types[op]
5495 holds the correct displacement size. */
5498 gas_assert (i
.op
[op
].disps
== 0);
5499 exp
= &disp_expressions
[i
.disp_operands
++];
5500 i
.op
[op
].disps
= exp
;
5501 exp
->X_op
= O_constant
;
5502 exp
->X_add_number
= 0;
5503 exp
->X_add_symbol
= (symbolS
*) 0;
5504 exp
->X_op_symbol
= (symbolS
*) 0;
5512 if (i
.tm
.opcode_modifier
.vexsources
== XOP2SOURCES
)
5514 if (operand_type_check (i
.types
[0], imm
))
5515 i
.vex
.register_specifier
= NULL
;
5518 /* VEX.vvvv encodes one of the sources when the first
5519 operand is not an immediate. */
5520 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5521 i
.vex
.register_specifier
= i
.op
[0].regs
;
5523 i
.vex
.register_specifier
= i
.op
[1].regs
;
5526 /* Destination is a XMM register encoded in the ModRM.reg
5528 i
.rm
.reg
= i
.op
[2].regs
->reg_num
;
5529 if ((i
.op
[2].regs
->reg_flags
& RegRex
) != 0)
5532 /* ModRM.rm and VEX.B encodes the other source. */
5533 if (!i
.mem_operands
)
5537 if (i
.tm
.opcode_modifier
.vexw
== VEXW0
)
5538 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5540 i
.rm
.regmem
= i
.op
[0].regs
->reg_num
;
5542 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5546 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXLWP
)
5548 i
.vex
.register_specifier
= i
.op
[2].regs
;
5549 if (!i
.mem_operands
)
5552 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5553 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5557 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5558 (if any) based on i.tm.extension_opcode. Again, we must be
5559 careful to make sure that segment/control/debug/test/MMX
5560 registers are coded into the i.rm.reg field. */
5561 else if (i
.reg_operands
)
5564 unsigned int vex_reg
= ~0;
5566 for (op
= 0; op
< i
.operands
; op
++)
5567 if (i
.types
[op
].bitfield
.reg8
5568 || i
.types
[op
].bitfield
.reg16
5569 || i
.types
[op
].bitfield
.reg32
5570 || i
.types
[op
].bitfield
.reg64
5571 || i
.types
[op
].bitfield
.regmmx
5572 || i
.types
[op
].bitfield
.regxmm
5573 || i
.types
[op
].bitfield
.regymm
5574 || i
.types
[op
].bitfield
.sreg2
5575 || i
.types
[op
].bitfield
.sreg3
5576 || i
.types
[op
].bitfield
.control
5577 || i
.types
[op
].bitfield
.debug
5578 || i
.types
[op
].bitfield
.test
)
5583 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXXDS
)
5585 /* For instructions with VexNDS, the register-only
5586 source operand is encoded in VEX prefix. */
5587 gas_assert (mem
!= (unsigned int) ~0);
5592 gas_assert (op
< i
.operands
);
5597 gas_assert (vex_reg
< i
.operands
);
5600 else if (i
.tm
.opcode_modifier
.vexvvvv
== VEXNDD
)
5602 /* For instructions with VexNDD, there should be
5603 no memory operand and the register destination
5604 is encoded in VEX prefix. */
5605 gas_assert (i
.mem_operands
== 0
5606 && (op
+ 2) == i
.operands
);
5610 gas_assert (op
< i
.operands
);
5612 if (vex_reg
!= (unsigned int) ~0)
5614 gas_assert (i
.reg_operands
== 2);
5616 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5618 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5622 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5625 /* Don't set OP operand twice. */
5628 /* If there is an extension opcode to put here, the
5629 register number must be put into the regmem field. */
5630 if (i
.tm
.extension_opcode
!= None
)
5632 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5633 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5638 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5639 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5644 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5645 must set it to 3 to indicate this is a register operand
5646 in the regmem field. */
5647 if (!i
.mem_operands
)
5651 /* Fill in i.rm.reg field with extension opcode (if any). */
5652 if (i
.tm
.extension_opcode
!= None
)
5653 i
.rm
.reg
= i
.tm
.extension_opcode
;
5659 output_branch (void)
5664 relax_substateT subtype
;
5669 if (flag_code
== CODE_16BIT
)
5673 if (i
.prefix
[DATA_PREFIX
] != 0)
5679 /* Pentium4 branch hints. */
5680 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5681 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5686 if (i
.prefix
[REX_PREFIX
] != 0)
5692 if (i
.prefixes
!= 0 && !intel_syntax
)
5693 as_warn (_("skipping prefixes on this instruction"));
5695 /* It's always a symbol; End frag & setup for relax.
5696 Make sure there is enough room in this frag for the largest
5697 instruction we may generate in md_convert_frag. This is 2
5698 bytes for the opcode and room for the prefix and largest
5700 frag_grow (prefix
+ 2 + 4);
5701 /* Prefix and 1 opcode byte go in fr_fix. */
5702 p
= frag_more (prefix
+ 1);
5703 if (i
.prefix
[DATA_PREFIX
] != 0)
5704 *p
++ = DATA_PREFIX_OPCODE
;
5705 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5706 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5707 *p
++ = i
.prefix
[SEG_PREFIX
];
5708 if (i
.prefix
[REX_PREFIX
] != 0)
5709 *p
++ = i
.prefix
[REX_PREFIX
];
5710 *p
= i
.tm
.base_opcode
;
5712 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5713 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5714 else if (cpu_arch_flags
.bitfield
.cpui386
)
5715 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5717 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5720 sym
= i
.op
[0].disps
->X_add_symbol
;
5721 off
= i
.op
[0].disps
->X_add_number
;
5723 if (i
.op
[0].disps
->X_op
!= O_constant
5724 && i
.op
[0].disps
->X_op
!= O_symbol
)
5726 /* Handle complex expressions. */
5727 sym
= make_expr_symbol (i
.op
[0].disps
);
5731 /* 1 possible extra opcode + 4 byte displacement go in var part.
5732 Pass reloc in fr_var. */
5733 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5743 if (i
.tm
.opcode_modifier
.jumpbyte
)
5745 /* This is a loop or jecxz type instruction. */
5747 if (i
.prefix
[ADDR_PREFIX
] != 0)
5749 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5752 /* Pentium4 branch hints. */
5753 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5754 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5756 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5765 if (flag_code
== CODE_16BIT
)
5768 if (i
.prefix
[DATA_PREFIX
] != 0)
5770 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5780 if (i
.prefix
[REX_PREFIX
] != 0)
5782 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5786 if (i
.prefixes
!= 0 && !intel_syntax
)
5787 as_warn (_("skipping prefixes on this instruction"));
5789 p
= frag_more (1 + size
);
5790 *p
++ = i
.tm
.base_opcode
;
5792 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5793 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5795 /* All jumps handled here are signed, but don't use a signed limit
5796 check for 32 and 16 bit jumps as we want to allow wrap around at
5797 4G and 64k respectively. */
5799 fixP
->fx_signed
= 1;
5803 output_interseg_jump (void)
5811 if (flag_code
== CODE_16BIT
)
5815 if (i
.prefix
[DATA_PREFIX
] != 0)
5821 if (i
.prefix
[REX_PREFIX
] != 0)
5831 if (i
.prefixes
!= 0 && !intel_syntax
)
5832 as_warn (_("skipping prefixes on this instruction"));
5834 /* 1 opcode; 2 segment; offset */
5835 p
= frag_more (prefix
+ 1 + 2 + size
);
5837 if (i
.prefix
[DATA_PREFIX
] != 0)
5838 *p
++ = DATA_PREFIX_OPCODE
;
5840 if (i
.prefix
[REX_PREFIX
] != 0)
5841 *p
++ = i
.prefix
[REX_PREFIX
];
5843 *p
++ = i
.tm
.base_opcode
;
5844 if (i
.op
[1].imms
->X_op
== O_constant
)
5846 offsetT n
= i
.op
[1].imms
->X_add_number
;
5849 && !fits_in_unsigned_word (n
)
5850 && !fits_in_signed_word (n
))
5852 as_bad (_("16-bit jump out of range"));
5855 md_number_to_chars (p
, n
, size
);
5858 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5859 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5860 if (i
.op
[0].imms
->X_op
!= O_constant
)
5861 as_bad (_("can't handle non absolute segment in `%s'"),
5863 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5869 fragS
*insn_start_frag
;
5870 offsetT insn_start_off
;
5872 /* Tie dwarf2 debug info to the address at the start of the insn.
5873 We can't do this after the insn has been output as the current
5874 frag may have been closed off. eg. by frag_var. */
5875 dwarf2_emit_insn (0);
5877 insn_start_frag
= frag_now
;
5878 insn_start_off
= frag_now_fix ();
5881 if (i
.tm
.opcode_modifier
.jump
)
5883 else if (i
.tm
.opcode_modifier
.jumpbyte
5884 || i
.tm
.opcode_modifier
.jumpdword
)
5886 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5887 output_interseg_jump ();
5890 /* Output normal instructions here. */
5894 unsigned int prefix
;
5896 /* Since the VEX prefix contains the implicit prefix, we don't
5897 need the explicit prefix. */
5898 if (!i
.tm
.opcode_modifier
.vex
)
5900 switch (i
.tm
.opcode_length
)
5903 if (i
.tm
.base_opcode
& 0xff000000)
5905 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5910 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5912 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5913 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5916 if (prefix
!= REPE_PREFIX_OPCODE
5917 || (i
.prefix
[REP_PREFIX
]
5918 != REPE_PREFIX_OPCODE
))
5919 add_prefix (prefix
);
5922 add_prefix (prefix
);
5931 /* The prefix bytes. */
5932 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5934 FRAG_APPEND_1_CHAR (*q
);
5937 if (i
.tm
.opcode_modifier
.vex
)
5939 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5944 /* REX byte is encoded in VEX prefix. */
5948 FRAG_APPEND_1_CHAR (*q
);
5951 /* There should be no other prefixes for instructions
5956 /* Now the VEX prefix. */
5957 p
= frag_more (i
.vex
.length
);
5958 for (j
= 0; j
< i
.vex
.length
; j
++)
5959 p
[j
] = i
.vex
.bytes
[j
];
5962 /* Now the opcode; be careful about word order here! */
5963 if (i
.tm
.opcode_length
== 1)
5965 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5969 switch (i
.tm
.opcode_length
)
5973 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5983 /* Put out high byte first: can't use md_number_to_chars! */
5984 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5985 *p
= i
.tm
.base_opcode
& 0xff;
5988 /* Now the modrm byte and sib byte (if present). */
5989 if (i
.tm
.opcode_modifier
.modrm
)
5991 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5994 /* If i.rm.regmem == ESP (4)
5995 && i.rm.mode != (Register mode)
5997 ==> need second modrm byte. */
5998 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
6000 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
6001 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
6003 | i
.sib
.scale
<< 6));
6006 if (i
.disp_operands
)
6007 output_disp (insn_start_frag
, insn_start_off
);
6010 output_imm (insn_start_frag
, insn_start_off
);
6016 pi ("" /*line*/, &i
);
6018 #endif /* DEBUG386 */
6021 /* Return the size of the displacement operand N. */
6024 disp_size (unsigned int n
)
6027 if (i
.types
[n
].bitfield
.disp64
)
6029 else if (i
.types
[n
].bitfield
.disp8
)
6031 else if (i
.types
[n
].bitfield
.disp16
)
6036 /* Return the size of the immediate operand N. */
6039 imm_size (unsigned int n
)
6042 if (i
.types
[n
].bitfield
.imm64
)
6044 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
6046 else if (i
.types
[n
].bitfield
.imm16
)
6052 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
6057 for (n
= 0; n
< i
.operands
; n
++)
6059 if (operand_type_check (i
.types
[n
], disp
))
6061 if (i
.op
[n
].disps
->X_op
== O_constant
)
6063 int size
= disp_size (n
);
6066 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
6068 p
= frag_more (size
);
6069 md_number_to_chars (p
, val
, size
);
6073 enum bfd_reloc_code_real reloc_type
;
6074 int size
= disp_size (n
);
6075 int sign
= i
.types
[n
].bitfield
.disp32s
;
6076 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
6078 /* We can't have 8 bit displacement here. */
6079 gas_assert (!i
.types
[n
].bitfield
.disp8
);
6081 /* The PC relative address is computed relative
6082 to the instruction boundary, so in case immediate
6083 fields follows, we need to adjust the value. */
6084 if (pcrel
&& i
.imm_operands
)
6089 for (n1
= 0; n1
< i
.operands
; n1
++)
6090 if (operand_type_check (i
.types
[n1
], imm
))
6092 /* Only one immediate is allowed for PC
6093 relative address. */
6094 gas_assert (sz
== 0);
6096 i
.op
[n
].disps
->X_add_number
-= sz
;
6098 /* We should find the immediate. */
6099 gas_assert (sz
!= 0);
6102 p
= frag_more (size
);
6103 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
6105 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
6106 && (((reloc_type
== BFD_RELOC_32
6107 || reloc_type
== BFD_RELOC_X86_64_32S
6108 || (reloc_type
== BFD_RELOC_64
6110 && (i
.op
[n
].disps
->X_op
== O_symbol
6111 || (i
.op
[n
].disps
->X_op
== O_add
6112 && ((symbol_get_value_expression
6113 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
6115 || reloc_type
== BFD_RELOC_32_PCREL
))
6119 if (insn_start_frag
== frag_now
)
6120 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6125 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6126 for (fr
= insn_start_frag
->fr_next
;
6127 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6129 add
+= p
- frag_now
->fr_literal
;
6134 reloc_type
= BFD_RELOC_386_GOTPC
;
6135 i
.op
[n
].imms
->X_add_number
+= add
;
6137 else if (reloc_type
== BFD_RELOC_64
)
6138 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6140 /* Don't do the adjustment for x86-64, as there
6141 the pcrel addressing is relative to the _next_
6142 insn, and that is taken care of in other code. */
6143 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6145 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6146 i
.op
[n
].disps
, pcrel
, reloc_type
);
6153 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
6158 for (n
= 0; n
< i
.operands
; n
++)
6160 if (operand_type_check (i
.types
[n
], imm
))
6162 if (i
.op
[n
].imms
->X_op
== O_constant
)
6164 int size
= imm_size (n
);
6167 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
6169 p
= frag_more (size
);
6170 md_number_to_chars (p
, val
, size
);
6174 /* Not absolute_section.
6175 Need a 32-bit fixup (don't support 8bit
6176 non-absolute imms). Try to support other
6178 enum bfd_reloc_code_real reloc_type
;
6179 int size
= imm_size (n
);
6182 if (i
.types
[n
].bitfield
.imm32s
6183 && (i
.suffix
== QWORD_MNEM_SUFFIX
6184 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
6189 p
= frag_more (size
);
6190 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
6192 /* This is tough to explain. We end up with this one if we
6193 * have operands that look like
6194 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
6195 * obtain the absolute address of the GOT, and it is strongly
6196 * preferable from a performance point of view to avoid using
6197 * a runtime relocation for this. The actual sequence of
6198 * instructions often look something like:
6203 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
6205 * The call and pop essentially return the absolute address
6206 * of the label .L66 and store it in %ebx. The linker itself
6207 * will ultimately change the first operand of the addl so
6208 * that %ebx points to the GOT, but to keep things simple, the
6209 * .o file must have this operand set so that it generates not
6210 * the absolute address of .L66, but the absolute address of
6211 * itself. This allows the linker itself simply treat a GOTPC
6212 * relocation as asking for a pcrel offset to the GOT to be
6213 * added in, and the addend of the relocation is stored in the
6214 * operand field for the instruction itself.
6216 * Our job here is to fix the operand so that it would add
6217 * the correct offset so that %ebx would point to itself. The
6218 * thing that is tricky is that .-.L66 will point to the
6219 * beginning of the instruction, so we need to further modify
6220 * the operand so that it will point to itself. There are
6221 * other cases where you have something like:
6223 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
6225 * and here no correction would be required. Internally in
6226 * the assembler we treat operands of this form as not being
6227 * pcrel since the '.' is explicitly mentioned, and I wonder
6228 * whether it would simplify matters to do it this way. Who
6229 * knows. In earlier versions of the PIC patches, the
6230 * pcrel_adjust field was used to store the correction, but
6231 * since the expression is not pcrel, I felt it would be
6232 * confusing to do it this way. */
6234 if ((reloc_type
== BFD_RELOC_32
6235 || reloc_type
== BFD_RELOC_X86_64_32S
6236 || reloc_type
== BFD_RELOC_64
)
6238 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
6239 && (i
.op
[n
].imms
->X_op
== O_symbol
6240 || (i
.op
[n
].imms
->X_op
== O_add
6241 && ((symbol_get_value_expression
6242 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
6247 if (insn_start_frag
== frag_now
)
6248 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
6253 add
= insn_start_frag
->fr_fix
- insn_start_off
;
6254 for (fr
= insn_start_frag
->fr_next
;
6255 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
6257 add
+= p
- frag_now
->fr_literal
;
6261 reloc_type
= BFD_RELOC_386_GOTPC
;
6263 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
6265 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
6266 i
.op
[n
].imms
->X_add_number
+= add
;
6268 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
6269 i
.op
[n
].imms
, 0, reloc_type
);
6275 /* x86_cons_fix_new is called via the expression parsing code when a
6276 reloc is needed. We use this hook to get the correct .got reloc. */
6277 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
6278 static int cons_sign
= -1;
6281 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6284 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6286 got_reloc
= NO_RELOC
;
6289 if (exp
->X_op
== O_secrel
)
6291 exp
->X_op
= O_symbol
;
6292 r
= BFD_RELOC_32_SECREL
;
6296 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6299 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6300 # define lex_got(reloc, adjust, types) NULL
6302 /* Parse operands of the form
6303 <symbol>@GOTOFF+<nnn>
6304 and similar .plt or .got references.
6306 If we find one, set up the correct relocation in RELOC and copy the
6307 input string, minus the `@GOTOFF' into a malloc'd buffer for
6308 parsing by the calling routine. Return this buffer, and if ADJUST
6309 is non-null set it to the length of the string we removed from the
6310 input line. Otherwise return NULL. */
6312 lex_got (enum bfd_reloc_code_real
*rel
,
6314 i386_operand_type
*types
)
6316 /* Some of the relocations depend on the size of what field is to
6317 be relocated. But in our callers i386_immediate and i386_displacement
6318 we don't yet know the operand size (this will be set by insn
6319 matching). Hence we record the word32 relocation here,
6320 and adjust the reloc according to the real size in reloc(). */
6321 static const struct {
6324 const enum bfd_reloc_code_real rel
[2];
6325 const i386_operand_type types64
;
6327 { STRING_COMMA_LEN ("PLTOFF"), { _dummy_first_bfd_reloc_code_real
,
6328 BFD_RELOC_X86_64_PLTOFF64
},
6329 OPERAND_TYPE_IMM64
},
6330 { STRING_COMMA_LEN ("PLT"), { BFD_RELOC_386_PLT32
,
6331 BFD_RELOC_X86_64_PLT32
},
6332 OPERAND_TYPE_IMM32_32S_DISP32
},
6333 { STRING_COMMA_LEN ("GOTPLT"), { _dummy_first_bfd_reloc_code_real
,
6334 BFD_RELOC_X86_64_GOTPLT64
},
6335 OPERAND_TYPE_IMM64_DISP64
},
6336 { STRING_COMMA_LEN ("GOTOFF"), { BFD_RELOC_386_GOTOFF
,
6337 BFD_RELOC_X86_64_GOTOFF64
},
6338 OPERAND_TYPE_IMM64_DISP64
},
6339 { STRING_COMMA_LEN ("GOTPCREL"), { _dummy_first_bfd_reloc_code_real
,
6340 BFD_RELOC_X86_64_GOTPCREL
},
6341 OPERAND_TYPE_IMM32_32S_DISP32
},
6342 { STRING_COMMA_LEN ("TLSGD"), { BFD_RELOC_386_TLS_GD
,
6343 BFD_RELOC_X86_64_TLSGD
},
6344 OPERAND_TYPE_IMM32_32S_DISP32
},
6345 { STRING_COMMA_LEN ("TLSLDM"), { BFD_RELOC_386_TLS_LDM
,
6346 _dummy_first_bfd_reloc_code_real
},
6347 OPERAND_TYPE_NONE
},
6348 { STRING_COMMA_LEN ("TLSLD"), { _dummy_first_bfd_reloc_code_real
,
6349 BFD_RELOC_X86_64_TLSLD
},
6350 OPERAND_TYPE_IMM32_32S_DISP32
},
6351 { STRING_COMMA_LEN ("GOTTPOFF"), { BFD_RELOC_386_TLS_IE_32
,
6352 BFD_RELOC_X86_64_GOTTPOFF
},
6353 OPERAND_TYPE_IMM32_32S_DISP32
},
6354 { STRING_COMMA_LEN ("TPOFF"), { BFD_RELOC_386_TLS_LE_32
,
6355 BFD_RELOC_X86_64_TPOFF32
},
6356 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6357 { STRING_COMMA_LEN ("NTPOFF"), { BFD_RELOC_386_TLS_LE
,
6358 _dummy_first_bfd_reloc_code_real
},
6359 OPERAND_TYPE_NONE
},
6360 { STRING_COMMA_LEN ("DTPOFF"), { BFD_RELOC_386_TLS_LDO_32
,
6361 BFD_RELOC_X86_64_DTPOFF32
},
6362 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6363 { STRING_COMMA_LEN ("GOTNTPOFF"),{ BFD_RELOC_386_TLS_GOTIE
,
6364 _dummy_first_bfd_reloc_code_real
},
6365 OPERAND_TYPE_NONE
},
6366 { STRING_COMMA_LEN ("INDNTPOFF"),{ BFD_RELOC_386_TLS_IE
,
6367 _dummy_first_bfd_reloc_code_real
},
6368 OPERAND_TYPE_NONE
},
6369 { STRING_COMMA_LEN ("GOT"), { BFD_RELOC_386_GOT32
,
6370 BFD_RELOC_X86_64_GOT32
},
6371 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6372 { STRING_COMMA_LEN ("TLSDESC"), { BFD_RELOC_386_TLS_GOTDESC
,
6373 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6374 OPERAND_TYPE_IMM32_32S_DISP32
},
6375 { STRING_COMMA_LEN ("TLSCALL"), { BFD_RELOC_386_TLS_DESC_CALL
,
6376 BFD_RELOC_X86_64_TLSDESC_CALL
},
6377 OPERAND_TYPE_IMM32_32S_DISP32
},
6385 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6386 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6389 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6391 int len
= gotrel
[j
].len
;
6392 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6394 if (gotrel
[j
].rel
[object_64bit
] != 0)
6397 char *tmpbuf
, *past_reloc
;
6399 *rel
= gotrel
[j
].rel
[object_64bit
];
6405 if (flag_code
!= CODE_64BIT
)
6407 types
->bitfield
.imm32
= 1;
6408 types
->bitfield
.disp32
= 1;
6411 *types
= gotrel
[j
].types64
;
6414 if (GOT_symbol
== NULL
)
6415 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6417 /* The length of the first part of our input line. */
6418 first
= cp
- input_line_pointer
;
6420 /* The second part goes from after the reloc token until
6421 (and including) an end_of_line char or comma. */
6422 past_reloc
= cp
+ 1 + len
;
6424 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6426 second
= cp
+ 1 - past_reloc
;
6428 /* Allocate and copy string. The trailing NUL shouldn't
6429 be necessary, but be safe. */
6430 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6431 memcpy (tmpbuf
, input_line_pointer
, first
);
6432 if (second
!= 0 && *past_reloc
!= ' ')
6433 /* Replace the relocation token with ' ', so that
6434 errors like foo@GOTOFF1 will be detected. */
6435 tmpbuf
[first
++] = ' ';
6436 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6437 tmpbuf
[first
+ second
] = '\0';
6441 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6442 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6447 /* Might be a symbol version string. Don't as_bad here. */
6452 x86_cons (expressionS
*exp
, int size
)
6454 intel_syntax
= -intel_syntax
;
6457 if (size
== 4 || (object_64bit
&& size
== 8))
6459 /* Handle @GOTOFF and the like in an expression. */
6461 char *gotfree_input_line
;
6464 save
= input_line_pointer
;
6465 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6466 if (gotfree_input_line
)
6467 input_line_pointer
= gotfree_input_line
;
6471 if (gotfree_input_line
)
6473 /* expression () has merrily parsed up to the end of line,
6474 or a comma - in the wrong buffer. Transfer how far
6475 input_line_pointer has moved to the right buffer. */
6476 input_line_pointer
= (save
6477 + (input_line_pointer
- gotfree_input_line
)
6479 free (gotfree_input_line
);
6480 if (exp
->X_op
== O_constant
6481 || exp
->X_op
== O_absent
6482 || exp
->X_op
== O_illegal
6483 || exp
->X_op
== O_register
6484 || exp
->X_op
== O_big
)
6486 char c
= *input_line_pointer
;
6487 *input_line_pointer
= 0;
6488 as_bad (_("missing or invalid expression `%s'"), save
);
6489 *input_line_pointer
= c
;
6496 intel_syntax
= -intel_syntax
;
6499 i386_intel_simplify (exp
);
6504 signed_cons (int size
)
6506 if (flag_code
== CODE_64BIT
)
6514 pe_directive_secrel (dummy
)
6515 int dummy ATTRIBUTE_UNUSED
;
6522 if (exp
.X_op
== O_symbol
)
6523 exp
.X_op
= O_secrel
;
6525 emit_expr (&exp
, 4);
6527 while (*input_line_pointer
++ == ',');
6529 input_line_pointer
--;
6530 demand_empty_rest_of_line ();
6535 i386_immediate (char *imm_start
)
6537 char *save_input_line_pointer
;
6538 char *gotfree_input_line
;
6541 i386_operand_type types
;
6543 operand_type_set (&types
, ~0);
6545 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6547 as_bad (_("at most %d immediate operands are allowed"),
6548 MAX_IMMEDIATE_OPERANDS
);
6552 exp
= &im_expressions
[i
.imm_operands
++];
6553 i
.op
[this_operand
].imms
= exp
;
6555 if (is_space_char (*imm_start
))
6558 save_input_line_pointer
= input_line_pointer
;
6559 input_line_pointer
= imm_start
;
6561 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6562 if (gotfree_input_line
)
6563 input_line_pointer
= gotfree_input_line
;
6565 exp_seg
= expression (exp
);
6568 if (*input_line_pointer
)
6569 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6571 input_line_pointer
= save_input_line_pointer
;
6572 if (gotfree_input_line
)
6574 free (gotfree_input_line
);
6576 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6577 exp
->X_op
= O_illegal
;
6580 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6584 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6585 i386_operand_type types
, const char *imm_start
)
6587 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6590 as_bad (_("missing or invalid immediate expression `%s'"),
6594 else if (exp
->X_op
== O_constant
)
6596 /* Size it properly later. */
6597 i
.types
[this_operand
].bitfield
.imm64
= 1;
6598 /* If BFD64, sign extend val. */
6599 if (!use_rela_relocations
6600 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6602 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6604 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6605 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6606 && exp_seg
!= absolute_section
6607 && exp_seg
!= text_section
6608 && exp_seg
!= data_section
6609 && exp_seg
!= bss_section
6610 && exp_seg
!= undefined_section
6611 && !bfd_is_com_section (exp_seg
))
6613 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6617 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6620 as_bad (_("illegal immediate register operand %s"), imm_start
);
6625 /* This is an address. The size of the address will be
6626 determined later, depending on destination register,
6627 suffix, or the default for the section. */
6628 i
.types
[this_operand
].bitfield
.imm8
= 1;
6629 i
.types
[this_operand
].bitfield
.imm16
= 1;
6630 i
.types
[this_operand
].bitfield
.imm32
= 1;
6631 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6632 i
.types
[this_operand
].bitfield
.imm64
= 1;
6633 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6641 i386_scale (char *scale
)
6644 char *save
= input_line_pointer
;
6646 input_line_pointer
= scale
;
6647 val
= get_absolute_expression ();
6652 i
.log2_scale_factor
= 0;
6655 i
.log2_scale_factor
= 1;
6658 i
.log2_scale_factor
= 2;
6661 i
.log2_scale_factor
= 3;
6665 char sep
= *input_line_pointer
;
6667 *input_line_pointer
= '\0';
6668 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6670 *input_line_pointer
= sep
;
6671 input_line_pointer
= save
;
6675 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6677 as_warn (_("scale factor of %d without an index register"),
6678 1 << i
.log2_scale_factor
);
6679 i
.log2_scale_factor
= 0;
6681 scale
= input_line_pointer
;
6682 input_line_pointer
= save
;
6687 i386_displacement (char *disp_start
, char *disp_end
)
6691 char *save_input_line_pointer
;
6692 char *gotfree_input_line
;
6694 i386_operand_type bigdisp
, types
= anydisp
;
6697 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6699 as_bad (_("at most %d displacement operands are allowed"),
6700 MAX_MEMORY_OPERANDS
);
6704 operand_type_set (&bigdisp
, 0);
6705 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6706 || (!current_templates
->start
->opcode_modifier
.jump
6707 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6709 bigdisp
.bitfield
.disp32
= 1;
6710 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6711 if (flag_code
== CODE_64BIT
)
6715 bigdisp
.bitfield
.disp32s
= 1;
6716 bigdisp
.bitfield
.disp64
= 1;
6719 else if ((flag_code
== CODE_16BIT
) ^ override
)
6721 bigdisp
.bitfield
.disp32
= 0;
6722 bigdisp
.bitfield
.disp16
= 1;
6727 /* For PC-relative branches, the width of the displacement
6728 is dependent upon data size, not address size. */
6729 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6730 if (flag_code
== CODE_64BIT
)
6732 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6733 bigdisp
.bitfield
.disp16
= 1;
6736 bigdisp
.bitfield
.disp32
= 1;
6737 bigdisp
.bitfield
.disp32s
= 1;
6743 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6745 : LONG_MNEM_SUFFIX
));
6746 bigdisp
.bitfield
.disp32
= 1;
6747 if ((flag_code
== CODE_16BIT
) ^ override
)
6749 bigdisp
.bitfield
.disp32
= 0;
6750 bigdisp
.bitfield
.disp16
= 1;
6754 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6757 exp
= &disp_expressions
[i
.disp_operands
];
6758 i
.op
[this_operand
].disps
= exp
;
6760 save_input_line_pointer
= input_line_pointer
;
6761 input_line_pointer
= disp_start
;
6762 END_STRING_AND_SAVE (disp_end
);
6764 #ifndef GCC_ASM_O_HACK
6765 #define GCC_ASM_O_HACK 0
6768 END_STRING_AND_SAVE (disp_end
+ 1);
6769 if (i
.types
[this_operand
].bitfield
.baseIndex
6770 && displacement_string_end
[-1] == '+')
6772 /* This hack is to avoid a warning when using the "o"
6773 constraint within gcc asm statements.
6776 #define _set_tssldt_desc(n,addr,limit,type) \
6777 __asm__ __volatile__ ( \
6779 "movw %w1,2+%0\n\t" \
6781 "movb %b1,4+%0\n\t" \
6782 "movb %4,5+%0\n\t" \
6783 "movb $0,6+%0\n\t" \
6784 "movb %h1,7+%0\n\t" \
6786 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6788 This works great except that the output assembler ends
6789 up looking a bit weird if it turns out that there is
6790 no offset. You end up producing code that looks like:
6803 So here we provide the missing zero. */
6805 *displacement_string_end
= '0';
6808 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6809 if (gotfree_input_line
)
6810 input_line_pointer
= gotfree_input_line
;
6812 exp_seg
= expression (exp
);
6815 if (*input_line_pointer
)
6816 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6818 RESTORE_END_STRING (disp_end
+ 1);
6820 input_line_pointer
= save_input_line_pointer
;
6821 if (gotfree_input_line
)
6823 free (gotfree_input_line
);
6825 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6826 exp
->X_op
= O_illegal
;
6829 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6831 RESTORE_END_STRING (disp_end
);
6837 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6838 i386_operand_type types
, const char *disp_start
)
6840 i386_operand_type bigdisp
;
6843 /* We do this to make sure that the section symbol is in
6844 the symbol table. We will ultimately change the relocation
6845 to be relative to the beginning of the section. */
6846 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6847 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6848 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6850 if (exp
->X_op
!= O_symbol
)
6853 if (S_IS_LOCAL (exp
->X_add_symbol
)
6854 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6855 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6856 exp
->X_op
= O_subtract
;
6857 exp
->X_op_symbol
= GOT_symbol
;
6858 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6859 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6860 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6861 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6863 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6866 else if (exp
->X_op
== O_absent
6867 || exp
->X_op
== O_illegal
6868 || exp
->X_op
== O_big
)
6871 as_bad (_("missing or invalid displacement expression `%s'"),
6876 else if (flag_code
== CODE_64BIT
6877 && !i
.prefix
[ADDR_PREFIX
]
6878 && exp
->X_op
== O_constant
)
6880 /* Since displacement is signed extended to 64bit, don't allow
6881 disp32 and turn off disp32s if they are out of range. */
6882 i
.types
[this_operand
].bitfield
.disp32
= 0;
6883 if (!fits_in_signed_long (exp
->X_add_number
))
6885 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6886 if (i
.types
[this_operand
].bitfield
.baseindex
)
6888 as_bad (_("0x%lx out range of signed 32bit displacement"),
6889 (long) exp
->X_add_number
);
6895 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6896 else if (exp
->X_op
!= O_constant
6897 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6898 && exp_seg
!= absolute_section
6899 && exp_seg
!= text_section
6900 && exp_seg
!= data_section
6901 && exp_seg
!= bss_section
6902 && exp_seg
!= undefined_section
6903 && !bfd_is_com_section (exp_seg
))
6905 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6910 /* Check if this is a displacement only operand. */
6911 bigdisp
= i
.types
[this_operand
];
6912 bigdisp
.bitfield
.disp8
= 0;
6913 bigdisp
.bitfield
.disp16
= 0;
6914 bigdisp
.bitfield
.disp32
= 0;
6915 bigdisp
.bitfield
.disp32s
= 0;
6916 bigdisp
.bitfield
.disp64
= 0;
6917 if (operand_type_all_zero (&bigdisp
))
6918 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6924 /* Make sure the memory operand we've been dealt is valid.
6925 Return 1 on success, 0 on a failure. */
6928 i386_index_check (const char *operand_string
)
6931 const char *kind
= "base/index";
6932 #if INFER_ADDR_PREFIX
6938 if (current_templates
->start
->opcode_modifier
.isstring
6939 && !current_templates
->start
->opcode_modifier
.immext
6940 && (current_templates
->end
[-1].opcode_modifier
.isstring
6943 /* Memory operands of string insns are special in that they only allow
6944 a single register (rDI, rSI, or rBX) as their memory address. */
6945 unsigned int expected
;
6947 kind
= "string address";
6949 if (current_templates
->start
->opcode_modifier
.w
)
6951 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6953 if (!type
.bitfield
.baseindex
6954 || ((!i
.mem_operands
!= !intel_syntax
)
6955 && current_templates
->end
[-1].operand_types
[1]
6956 .bitfield
.baseindex
))
6957 type
= current_templates
->end
[-1].operand_types
[1];
6958 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6961 expected
= 3 /* rBX */;
6963 if (!i
.base_reg
|| i
.index_reg
6964 || operand_type_check (i
.types
[this_operand
], disp
))
6966 else if (!(flag_code
== CODE_64BIT
6967 ? i
.prefix
[ADDR_PREFIX
]
6968 ? i
.base_reg
->reg_type
.bitfield
.reg32
6969 : i
.base_reg
->reg_type
.bitfield
.reg64
6970 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6971 ? i
.base_reg
->reg_type
.bitfield
.reg32
6972 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6974 else if (i
.base_reg
->reg_num
!= expected
)
6981 for (j
= 0; j
< i386_regtab_size
; ++j
)
6982 if ((flag_code
== CODE_64BIT
6983 ? i
.prefix
[ADDR_PREFIX
]
6984 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6985 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6986 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6987 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6988 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6989 && i386_regtab
[j
].reg_num
== expected
)
6991 gas_assert (j
< i386_regtab_size
);
6992 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6994 intel_syntax
? '[' : '(',
6996 i386_regtab
[j
].reg_name
,
6997 intel_syntax
? ']' : ')');
7001 else if (flag_code
== CODE_64BIT
)
7004 && ((i
.prefix
[ADDR_PREFIX
] == 0
7005 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
7006 || (i
.prefix
[ADDR_PREFIX
]
7007 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
7009 || i
.base_reg
->reg_num
!=
7010 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
7012 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
7013 || (i
.prefix
[ADDR_PREFIX
] == 0
7014 && i
.index_reg
->reg_num
!= RegRiz
7015 && !i
.index_reg
->reg_type
.bitfield
.reg64
7017 || (i
.prefix
[ADDR_PREFIX
]
7018 && i
.index_reg
->reg_num
!= RegEiz
7019 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
7024 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
7028 && (!i
.base_reg
->reg_type
.bitfield
.reg16
7029 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
7031 && (!i
.index_reg
->reg_type
.bitfield
.reg16
7032 || !i
.index_reg
->reg_type
.bitfield
.baseindex
7034 && i
.base_reg
->reg_num
< 6
7035 && i
.index_reg
->reg_num
>= 6
7036 && i
.log2_scale_factor
== 0))))
7043 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
7045 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
7046 && i
.index_reg
->reg_num
!= RegEiz
)
7047 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
7053 #if INFER_ADDR_PREFIX
7054 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
7056 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
7058 /* Change the size of any displacement too. At most one of
7059 Disp16 or Disp32 is set.
7060 FIXME. There doesn't seem to be any real need for separate
7061 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
7062 Removing them would probably clean up the code quite a lot. */
7063 if (flag_code
!= CODE_64BIT
7064 && (i
.types
[this_operand
].bitfield
.disp16
7065 || i
.types
[this_operand
].bitfield
.disp32
))
7066 i
.types
[this_operand
]
7067 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
7072 as_bad (_("`%s' is not a valid %s expression"),
7077 as_bad (_("`%s' is not a valid %s-bit %s expression"),
7079 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
7080 ? flag_code
== CODE_32BIT
7089 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
7093 i386_att_operand (char *operand_string
)
7097 char *op_string
= operand_string
;
7099 if (is_space_char (*op_string
))
7102 /* We check for an absolute prefix (differentiating,
7103 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
7104 if (*op_string
== ABSOLUTE_PREFIX
)
7107 if (is_space_char (*op_string
))
7109 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7112 /* Check if operand is a register. */
7113 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
7115 i386_operand_type temp
;
7117 /* Check for a segment override by searching for ':' after a
7118 segment register. */
7120 if (is_space_char (*op_string
))
7122 if (*op_string
== ':'
7123 && (r
->reg_type
.bitfield
.sreg2
7124 || r
->reg_type
.bitfield
.sreg3
))
7129 i
.seg
[i
.mem_operands
] = &es
;
7132 i
.seg
[i
.mem_operands
] = &cs
;
7135 i
.seg
[i
.mem_operands
] = &ss
;
7138 i
.seg
[i
.mem_operands
] = &ds
;
7141 i
.seg
[i
.mem_operands
] = &fs
;
7144 i
.seg
[i
.mem_operands
] = &gs
;
7148 /* Skip the ':' and whitespace. */
7150 if (is_space_char (*op_string
))
7153 if (!is_digit_char (*op_string
)
7154 && !is_identifier_char (*op_string
)
7155 && *op_string
!= '('
7156 && *op_string
!= ABSOLUTE_PREFIX
)
7158 as_bad (_("bad memory operand `%s'"), op_string
);
7161 /* Handle case of %es:*foo. */
7162 if (*op_string
== ABSOLUTE_PREFIX
)
7165 if (is_space_char (*op_string
))
7167 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
7169 goto do_memory_reference
;
7173 as_bad (_("junk `%s' after register"), op_string
);
7177 temp
.bitfield
.baseindex
= 0;
7178 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
7180 i
.types
[this_operand
].bitfield
.unspecified
= 0;
7181 i
.op
[this_operand
].regs
= r
;
7184 else if (*op_string
== REGISTER_PREFIX
)
7186 as_bad (_("bad register name `%s'"), op_string
);
7189 else if (*op_string
== IMMEDIATE_PREFIX
)
7192 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
7194 as_bad (_("immediate operand illegal with absolute jump"));
7197 if (!i386_immediate (op_string
))
7200 else if (is_digit_char (*op_string
)
7201 || is_identifier_char (*op_string
)
7202 || *op_string
== '(')
7204 /* This is a memory reference of some sort. */
7207 /* Start and end of displacement string expression (if found). */
7208 char *displacement_string_start
;
7209 char *displacement_string_end
;
7211 do_memory_reference
:
7212 if ((i
.mem_operands
== 1
7213 && !current_templates
->start
->opcode_modifier
.isstring
)
7214 || i
.mem_operands
== 2)
7216 as_bad (_("too many memory references for `%s'"),
7217 current_templates
->start
->name
);
7221 /* Check for base index form. We detect the base index form by
7222 looking for an ')' at the end of the operand, searching
7223 for the '(' matching it, and finding a REGISTER_PREFIX or ','
7225 base_string
= op_string
+ strlen (op_string
);
7228 if (is_space_char (*base_string
))
7231 /* If we only have a displacement, set-up for it to be parsed later. */
7232 displacement_string_start
= op_string
;
7233 displacement_string_end
= base_string
+ 1;
7235 if (*base_string
== ')')
7238 unsigned int parens_balanced
= 1;
7239 /* We've already checked that the number of left & right ()'s are
7240 equal, so this loop will not be infinite. */
7244 if (*base_string
== ')')
7246 if (*base_string
== '(')
7249 while (parens_balanced
);
7251 temp_string
= base_string
;
7253 /* Skip past '(' and whitespace. */
7255 if (is_space_char (*base_string
))
7258 if (*base_string
== ','
7259 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
7262 displacement_string_end
= temp_string
;
7264 i
.types
[this_operand
].bitfield
.baseindex
= 1;
7268 base_string
= end_op
;
7269 if (is_space_char (*base_string
))
7273 /* There may be an index reg or scale factor here. */
7274 if (*base_string
== ',')
7277 if (is_space_char (*base_string
))
7280 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7283 base_string
= end_op
;
7284 if (is_space_char (*base_string
))
7286 if (*base_string
== ',')
7289 if (is_space_char (*base_string
))
7292 else if (*base_string
!= ')')
7294 as_bad (_("expecting `,' or `)' "
7295 "after index register in `%s'"),
7300 else if (*base_string
== REGISTER_PREFIX
)
7302 as_bad (_("bad register name `%s'"), base_string
);
7306 /* Check for scale factor. */
7307 if (*base_string
!= ')')
7309 char *end_scale
= i386_scale (base_string
);
7314 base_string
= end_scale
;
7315 if (is_space_char (*base_string
))
7317 if (*base_string
!= ')')
7319 as_bad (_("expecting `)' "
7320 "after scale factor in `%s'"),
7325 else if (!i
.index_reg
)
7327 as_bad (_("expecting index register or scale factor "
7328 "after `,'; got '%c'"),
7333 else if (*base_string
!= ')')
7335 as_bad (_("expecting `,' or `)' "
7336 "after base register in `%s'"),
7341 else if (*base_string
== REGISTER_PREFIX
)
7343 as_bad (_("bad register name `%s'"), base_string
);
7348 /* If there's an expression beginning the operand, parse it,
7349 assuming displacement_string_start and
7350 displacement_string_end are meaningful. */
7351 if (displacement_string_start
!= displacement_string_end
)
7353 if (!i386_displacement (displacement_string_start
,
7354 displacement_string_end
))
7358 /* Special case for (%dx) while doing input/output op. */
7360 && operand_type_equal (&i
.base_reg
->reg_type
,
7361 ®16_inoutportreg
)
7363 && i
.log2_scale_factor
== 0
7364 && i
.seg
[i
.mem_operands
] == 0
7365 && !operand_type_check (i
.types
[this_operand
], disp
))
7367 i
.types
[this_operand
] = inoutportreg
;
7371 if (i386_index_check (operand_string
) == 0)
7373 i
.types
[this_operand
].bitfield
.mem
= 1;
7378 /* It's not a memory operand; argh! */
7379 as_bad (_("invalid char %s beginning operand %d `%s'"),
7380 output_invalid (*op_string
),
7385 return 1; /* Normal return. */
7388 /* md_estimate_size_before_relax()
7390 Called just before relax() for rs_machine_dependent frags. The x86
7391 assembler uses these frags to handle variable size jump
7394 Any symbol that is now undefined will not become defined.
7395 Return the correct fr_subtype in the frag.
7396 Return the initial "guess for variable size of frag" to caller.
7397 The guess is actually the growth beyond the fixed part. Whatever
7398 we do to grow the fixed or variable part contributes to our
7402 md_estimate_size_before_relax (fragP
, segment
)
7406 /* We've already got fragP->fr_subtype right; all we have to do is
7407 check for un-relaxable symbols. On an ELF system, we can't relax
7408 an externally visible symbol, because it may be overridden by a
7410 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7411 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7413 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7414 || S_IS_WEAK (fragP
->fr_symbol
)
7415 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7416 & BSF_GNU_INDIRECT_FUNCTION
))))
7418 #if defined (OBJ_COFF) && defined (TE_PE)
7419 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7420 && S_IS_WEAK (fragP
->fr_symbol
))
7424 /* Symbol is undefined in this segment, or we need to keep a
7425 reloc so that weak symbols can be overridden. */
7426 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7427 enum bfd_reloc_code_real reloc_type
;
7428 unsigned char *opcode
;
7431 if (fragP
->fr_var
!= NO_RELOC
)
7432 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7434 reloc_type
= BFD_RELOC_16_PCREL
;
7436 reloc_type
= BFD_RELOC_32_PCREL
;
7438 old_fr_fix
= fragP
->fr_fix
;
7439 opcode
= (unsigned char *) fragP
->fr_opcode
;
7441 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7444 /* Make jmp (0xeb) a (d)word displacement jump. */
7446 fragP
->fr_fix
+= size
;
7447 fix_new (fragP
, old_fr_fix
, size
,
7449 fragP
->fr_offset
, 1,
7455 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7457 /* Negate the condition, and branch past an
7458 unconditional jump. */
7461 /* Insert an unconditional jump. */
7463 /* We added two extra opcode bytes, and have a two byte
7465 fragP
->fr_fix
+= 2 + 2;
7466 fix_new (fragP
, old_fr_fix
+ 2, 2,
7468 fragP
->fr_offset
, 1,
7475 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7480 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7482 fragP
->fr_offset
, 1,
7484 fixP
->fx_signed
= 1;
7488 /* This changes the byte-displacement jump 0x7N
7489 to the (d)word-displacement jump 0x0f,0x8N. */
7490 opcode
[1] = opcode
[0] + 0x10;
7491 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7492 /* We've added an opcode byte. */
7493 fragP
->fr_fix
+= 1 + size
;
7494 fix_new (fragP
, old_fr_fix
+ 1, size
,
7496 fragP
->fr_offset
, 1,
7501 BAD_CASE (fragP
->fr_subtype
);
7505 return fragP
->fr_fix
- old_fr_fix
;
7508 /* Guess size depending on current relax state. Initially the relax
7509 state will correspond to a short jump and we return 1, because
7510 the variable part of the frag (the branch offset) is one byte
7511 long. However, we can relax a section more than once and in that
7512 case we must either set fr_subtype back to the unrelaxed state,
7513 or return the value for the appropriate branch. */
7514 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7517 /* Called after relax() is finished.
7519 In: Address of frag.
7520 fr_type == rs_machine_dependent.
7521 fr_subtype is what the address relaxed to.
7523 Out: Any fixSs and constants are set up.
7524 Caller will turn frag into a ".space 0". */
7527 md_convert_frag (abfd
, sec
, fragP
)
7528 bfd
*abfd ATTRIBUTE_UNUSED
;
7529 segT sec ATTRIBUTE_UNUSED
;
7532 unsigned char *opcode
;
7533 unsigned char *where_to_put_displacement
= NULL
;
7534 offsetT target_address
;
7535 offsetT opcode_address
;
7536 unsigned int extension
= 0;
7537 offsetT displacement_from_opcode_start
;
7539 opcode
= (unsigned char *) fragP
->fr_opcode
;
7541 /* Address we want to reach in file space. */
7542 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7544 /* Address opcode resides at in file space. */
7545 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7547 /* Displacement from opcode start to fill into instruction. */
7548 displacement_from_opcode_start
= target_address
- opcode_address
;
7550 if ((fragP
->fr_subtype
& BIG
) == 0)
7552 /* Don't have to change opcode. */
7553 extension
= 1; /* 1 opcode + 1 displacement */
7554 where_to_put_displacement
= &opcode
[1];
7558 if (no_cond_jump_promotion
7559 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7560 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7561 _("long jump required"));
7563 switch (fragP
->fr_subtype
)
7565 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7566 extension
= 4; /* 1 opcode + 4 displacement */
7568 where_to_put_displacement
= &opcode
[1];
7571 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7572 extension
= 2; /* 1 opcode + 2 displacement */
7574 where_to_put_displacement
= &opcode
[1];
7577 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7578 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7579 extension
= 5; /* 2 opcode + 4 displacement */
7580 opcode
[1] = opcode
[0] + 0x10;
7581 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7582 where_to_put_displacement
= &opcode
[2];
7585 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7586 extension
= 3; /* 2 opcode + 2 displacement */
7587 opcode
[1] = opcode
[0] + 0x10;
7588 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7589 where_to_put_displacement
= &opcode
[2];
7592 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7597 where_to_put_displacement
= &opcode
[3];
7601 BAD_CASE (fragP
->fr_subtype
);
7606 /* If size if less then four we are sure that the operand fits,
7607 but if it's 4, then it could be that the displacement is larger
7609 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7611 && ((addressT
) (displacement_from_opcode_start
- extension
7612 + ((addressT
) 1 << 31))
7613 > (((addressT
) 2 << 31) - 1)))
7615 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7616 _("jump target out of range"));
7617 /* Make us emit 0. */
7618 displacement_from_opcode_start
= extension
;
7620 /* Now put displacement after opcode. */
7621 md_number_to_chars ((char *) where_to_put_displacement
,
7622 (valueT
) (displacement_from_opcode_start
- extension
),
7623 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7624 fragP
->fr_fix
+= extension
;
7627 /* Apply a fixup (fixS) to segment data, once it has been determined
7628 by our caller that we have all the info we need to fix it up.
7630 On the 386, immediates, displacements, and data pointers are all in
7631 the same (little-endian) format, so we don't need to care about which
7635 md_apply_fix (fixP
, valP
, seg
)
7636 /* The fix we're to put in. */
7638 /* Pointer to the value of the bits. */
7640 /* Segment fix is from. */
7641 segT seg ATTRIBUTE_UNUSED
;
7643 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7644 valueT value
= *valP
;
7646 #if !defined (TE_Mach)
7649 switch (fixP
->fx_r_type
)
7655 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7658 case BFD_RELOC_X86_64_32S
:
7659 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7662 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7665 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7670 if (fixP
->fx_addsy
!= NULL
7671 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7672 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7673 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7674 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7675 && !use_rela_relocations
)
7677 /* This is a hack. There should be a better way to handle this.
7678 This covers for the fact that bfd_install_relocation will
7679 subtract the current location (for partial_inplace, PC relative
7680 relocations); see more below. */
7684 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7687 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7689 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7692 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7695 || (symbol_section_p (fixP
->fx_addsy
)
7696 && sym_seg
!= absolute_section
))
7697 && !generic_force_reloc (fixP
))
7699 /* Yes, we add the values in twice. This is because
7700 bfd_install_relocation subtracts them out again. I think
7701 bfd_install_relocation is broken, but I don't dare change
7703 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7707 #if defined (OBJ_COFF) && defined (TE_PE)
7708 /* For some reason, the PE format does not store a
7709 section address offset for a PC relative symbol. */
7710 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7711 || S_IS_WEAK (fixP
->fx_addsy
))
7712 value
+= md_pcrel_from (fixP
);
7715 #if defined (OBJ_COFF) && defined (TE_PE)
7716 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7718 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7722 /* Fix a few things - the dynamic linker expects certain values here,
7723 and we must not disappoint it. */
7724 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7725 if (IS_ELF
&& fixP
->fx_addsy
)
7726 switch (fixP
->fx_r_type
)
7728 case BFD_RELOC_386_PLT32
:
7729 case BFD_RELOC_X86_64_PLT32
:
7730 /* Make the jump instruction point to the address of the operand. At
7731 runtime we merely add the offset to the actual PLT entry. */
7735 case BFD_RELOC_386_TLS_GD
:
7736 case BFD_RELOC_386_TLS_LDM
:
7737 case BFD_RELOC_386_TLS_IE_32
:
7738 case BFD_RELOC_386_TLS_IE
:
7739 case BFD_RELOC_386_TLS_GOTIE
:
7740 case BFD_RELOC_386_TLS_GOTDESC
:
7741 case BFD_RELOC_X86_64_TLSGD
:
7742 case BFD_RELOC_X86_64_TLSLD
:
7743 case BFD_RELOC_X86_64_GOTTPOFF
:
7744 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7745 value
= 0; /* Fully resolved at runtime. No addend. */
7747 case BFD_RELOC_386_TLS_LE
:
7748 case BFD_RELOC_386_TLS_LDO_32
:
7749 case BFD_RELOC_386_TLS_LE_32
:
7750 case BFD_RELOC_X86_64_DTPOFF32
:
7751 case BFD_RELOC_X86_64_DTPOFF64
:
7752 case BFD_RELOC_X86_64_TPOFF32
:
7753 case BFD_RELOC_X86_64_TPOFF64
:
7754 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7757 case BFD_RELOC_386_TLS_DESC_CALL
:
7758 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7759 value
= 0; /* Fully resolved at runtime. No addend. */
7760 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7764 case BFD_RELOC_386_GOT32
:
7765 case BFD_RELOC_X86_64_GOT32
:
7766 value
= 0; /* Fully resolved at runtime. No addend. */
7769 case BFD_RELOC_VTABLE_INHERIT
:
7770 case BFD_RELOC_VTABLE_ENTRY
:
7777 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7779 #endif /* !defined (TE_Mach) */
7781 /* Are we finished with this relocation now? */
7782 if (fixP
->fx_addsy
== NULL
)
7784 #if defined (OBJ_COFF) && defined (TE_PE)
7785 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7788 /* Remember value for tc_gen_reloc. */
7789 fixP
->fx_addnumber
= value
;
7790 /* Clear out the frag for now. */
7794 else if (use_rela_relocations
)
7796 fixP
->fx_no_overflow
= 1;
7797 /* Remember value for tc_gen_reloc. */
7798 fixP
->fx_addnumber
= value
;
7802 md_number_to_chars (p
, value
, fixP
->fx_size
);
7806 md_atof (int type
, char *litP
, int *sizeP
)
7808 /* This outputs the LITTLENUMs in REVERSE order;
7809 in accord with the bigendian 386. */
7810 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7813 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7816 output_invalid (int c
)
7819 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7822 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7823 "(0x%x)", (unsigned char) c
);
7824 return output_invalid_buf
;
7827 /* REG_STRING starts *before* REGISTER_PREFIX. */
7829 static const reg_entry
*
7830 parse_real_register (char *reg_string
, char **end_op
)
7832 char *s
= reg_string
;
7834 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7837 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7838 if (*s
== REGISTER_PREFIX
)
7841 if (is_space_char (*s
))
7845 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7847 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7848 return (const reg_entry
*) NULL
;
7852 /* For naked regs, make sure that we are not dealing with an identifier.
7853 This prevents confusing an identifier like `eax_var' with register
7855 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7856 return (const reg_entry
*) NULL
;
7860 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7862 /* Handle floating point regs, allowing spaces in the (i) part. */
7863 if (r
== i386_regtab
/* %st is first entry of table */)
7865 if (is_space_char (*s
))
7870 if (is_space_char (*s
))
7872 if (*s
>= '0' && *s
<= '7')
7876 if (is_space_char (*s
))
7881 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7886 /* We have "%st(" then garbage. */
7887 return (const reg_entry
*) NULL
;
7891 if (r
== NULL
|| allow_pseudo_reg
)
7894 if (operand_type_all_zero (&r
->reg_type
))
7895 return (const reg_entry
*) NULL
;
7897 if ((r
->reg_type
.bitfield
.reg32
7898 || r
->reg_type
.bitfield
.sreg3
7899 || r
->reg_type
.bitfield
.control
7900 || r
->reg_type
.bitfield
.debug
7901 || r
->reg_type
.bitfield
.test
)
7902 && !cpu_arch_flags
.bitfield
.cpui386
)
7903 return (const reg_entry
*) NULL
;
7905 if (r
->reg_type
.bitfield
.floatreg
7906 && !cpu_arch_flags
.bitfield
.cpu8087
7907 && !cpu_arch_flags
.bitfield
.cpu287
7908 && !cpu_arch_flags
.bitfield
.cpu387
)
7909 return (const reg_entry
*) NULL
;
7911 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7912 return (const reg_entry
*) NULL
;
7914 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7915 return (const reg_entry
*) NULL
;
7917 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7918 return (const reg_entry
*) NULL
;
7920 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7921 if (!allow_index_reg
7922 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7923 return (const reg_entry
*) NULL
;
7925 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7926 || r
->reg_type
.bitfield
.reg64
)
7927 && (!cpu_arch_flags
.bitfield
.cpulm
7928 || !operand_type_equal (&r
->reg_type
, &control
))
7929 && flag_code
!= CODE_64BIT
)
7930 return (const reg_entry
*) NULL
;
7932 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7933 return (const reg_entry
*) NULL
;
7938 /* REG_STRING starts *before* REGISTER_PREFIX. */
7940 static const reg_entry
*
7941 parse_register (char *reg_string
, char **end_op
)
7945 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7946 r
= parse_real_register (reg_string
, end_op
);
7951 char *save
= input_line_pointer
;
7955 input_line_pointer
= reg_string
;
7956 c
= get_symbol_end ();
7957 symbolP
= symbol_find (reg_string
);
7958 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7960 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7962 know (e
->X_op
== O_register
);
7963 know (e
->X_add_number
>= 0
7964 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7965 r
= i386_regtab
+ e
->X_add_number
;
7966 *end_op
= input_line_pointer
;
7968 *input_line_pointer
= c
;
7969 input_line_pointer
= save
;
7975 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7978 char *end
= input_line_pointer
;
7981 r
= parse_register (name
, &input_line_pointer
);
7982 if (r
&& end
<= input_line_pointer
)
7984 *nextcharP
= *input_line_pointer
;
7985 *input_line_pointer
= 0;
7986 e
->X_op
= O_register
;
7987 e
->X_add_number
= r
- i386_regtab
;
7990 input_line_pointer
= end
;
7992 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7996 md_operand (expressionS
*e
)
8001 switch (*input_line_pointer
)
8003 case REGISTER_PREFIX
:
8004 r
= parse_real_register (input_line_pointer
, &end
);
8007 e
->X_op
= O_register
;
8008 e
->X_add_number
= r
- i386_regtab
;
8009 input_line_pointer
= end
;
8014 gas_assert (intel_syntax
);
8015 end
= input_line_pointer
++;
8017 if (*input_line_pointer
== ']')
8019 ++input_line_pointer
;
8020 e
->X_op_symbol
= make_expr_symbol (e
);
8021 e
->X_add_symbol
= NULL
;
8022 e
->X_add_number
= 0;
8028 input_line_pointer
= end
;
8035 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8036 const char *md_shortopts
= "kVQ:sqn";
8038 const char *md_shortopts
= "qn";
8041 #define OPTION_32 (OPTION_MD_BASE + 0)
8042 #define OPTION_64 (OPTION_MD_BASE + 1)
8043 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
8044 #define OPTION_MARCH (OPTION_MD_BASE + 3)
8045 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
8046 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
8047 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
8048 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
8049 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
8050 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
8051 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
8052 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
8053 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 12)
8055 struct option md_longopts
[] =
8057 {"32", no_argument
, NULL
, OPTION_32
},
8058 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8059 || defined (TE_PE) || defined (TE_PEP))
8060 {"64", no_argument
, NULL
, OPTION_64
},
8062 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
8063 {"march", required_argument
, NULL
, OPTION_MARCH
},
8064 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
8065 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
8066 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
8067 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
8068 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
8069 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
8070 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
8071 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
8072 {"mavxscalar", required_argument
, NULL
, OPTION_MAVXSCALAR
},
8073 {NULL
, no_argument
, NULL
, 0}
8075 size_t md_longopts_size
= sizeof (md_longopts
);
8078 md_parse_option (int c
, char *arg
)
8086 optimize_align_code
= 0;
8093 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8094 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
8095 should be emitted or not. FIXME: Not implemented. */
8099 /* -V: SVR4 argument to print version ID. */
8101 print_version_id ();
8104 /* -k: Ignore for FreeBSD compatibility. */
8109 /* -s: On i386 Solaris, this tells the native assembler to use
8110 .stab instead of .stab.excl. We always use .stab anyhow. */
8113 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8114 || defined (TE_PE) || defined (TE_PEP))
8117 const char **list
, **l
;
8119 list
= bfd_target_list ();
8120 for (l
= list
; *l
!= NULL
; l
++)
8121 if (CONST_STRNEQ (*l
, "elf64-x86-64")
8122 || strcmp (*l
, "coff-x86-64") == 0
8123 || strcmp (*l
, "pe-x86-64") == 0
8124 || strcmp (*l
, "pei-x86-64") == 0)
8126 default_arch
= "x86_64";
8130 as_fatal (_("No compiled in support for x86_64"));
8137 default_arch
= "i386";
8141 #ifdef SVR4_COMMENT_CHARS
8146 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
8148 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
8152 i386_comment_chars
= n
;
8158 arch
= xstrdup (arg
);
8162 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8163 next
= strchr (arch
, '+');
8166 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8168 if (strcmp (arch
, cpu_arch
[j
].name
) == 0)
8171 cpu_arch_name
= cpu_arch
[j
].name
;
8172 cpu_sub_arch_name
= NULL
;
8173 cpu_arch_flags
= cpu_arch
[j
].flags
;
8174 cpu_arch_isa
= cpu_arch
[j
].type
;
8175 cpu_arch_isa_flags
= cpu_arch
[j
].flags
;
8176 if (!cpu_arch_tune_set
)
8178 cpu_arch_tune
= cpu_arch_isa
;
8179 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
8183 else if (*cpu_arch
[j
].name
== '.'
8184 && strcmp (arch
, cpu_arch
[j
].name
+ 1) == 0)
8186 /* ISA entension. */
8187 i386_cpu_flags flags
;
8189 if (strncmp (arch
, "no", 2))
8190 flags
= cpu_flags_or (cpu_arch_flags
,
8193 flags
= cpu_flags_and_not (cpu_arch_flags
,
8195 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
8197 if (cpu_sub_arch_name
)
8199 char *name
= cpu_sub_arch_name
;
8200 cpu_sub_arch_name
= concat (name
,
8202 (const char *) NULL
);
8206 cpu_sub_arch_name
= xstrdup (cpu_arch
[j
].name
);
8207 cpu_arch_flags
= flags
;
8213 if (j
>= ARRAY_SIZE (cpu_arch
))
8214 as_fatal (_("Invalid -march= option: `%s'"), arg
);
8218 while (next
!= NULL
);
8223 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8224 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8226 if (strcmp (arg
, cpu_arch
[j
].name
) == 0)
8228 cpu_arch_tune_set
= 1;
8229 cpu_arch_tune
= cpu_arch
[j
].type
;
8230 cpu_arch_tune_flags
= cpu_arch
[j
].flags
;
8234 if (j
>= ARRAY_SIZE (cpu_arch
))
8235 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
8238 case OPTION_MMNEMONIC
:
8239 if (strcasecmp (arg
, "att") == 0)
8241 else if (strcasecmp (arg
, "intel") == 0)
8244 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
8247 case OPTION_MSYNTAX
:
8248 if (strcasecmp (arg
, "att") == 0)
8250 else if (strcasecmp (arg
, "intel") == 0)
8253 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
8256 case OPTION_MINDEX_REG
:
8257 allow_index_reg
= 1;
8260 case OPTION_MNAKED_REG
:
8261 allow_naked_reg
= 1;
8264 case OPTION_MOLD_GCC
:
8268 case OPTION_MSSE2AVX
:
8272 case OPTION_MSSE_CHECK
:
8273 if (strcasecmp (arg
, "error") == 0)
8274 sse_check
= sse_check_error
;
8275 else if (strcasecmp (arg
, "warning") == 0)
8276 sse_check
= sse_check_warning
;
8277 else if (strcasecmp (arg
, "none") == 0)
8278 sse_check
= sse_check_none
;
8280 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8283 case OPTION_MAVXSCALAR
:
8284 if (strcasecmp (arg
, "128") == 0)
8286 else if (strcasecmp (arg
, "256") == 0)
8289 as_fatal (_("Invalid -mavxscalar= option: `%s'"), arg
);
8298 #define MESSAGE_TEMPLATE \
8302 show_arch (FILE *stream
, int ext
)
8304 static char message
[] = MESSAGE_TEMPLATE
;
8305 char *start
= message
+ 27;
8307 int size
= sizeof (MESSAGE_TEMPLATE
);
8314 left
= size
- (start
- message
);
8315 for (j
= 0; j
< ARRAY_SIZE (cpu_arch
); j
++)
8317 /* Should it be skipped? */
8318 if (cpu_arch
[j
].skip
)
8321 name
= cpu_arch
[j
].name
;
8322 len
= cpu_arch
[j
].len
;
8325 /* It is an extension. Skip if we aren't asked to show it. */
8336 /* It is an processor. Skip if we show only extension. */
8340 /* Reserve 2 spaces for ", " or ",\0" */
8343 /* Check if there is any room. */
8351 p
= mempcpy (p
, name
, len
);
8355 /* Output the current message now and start a new one. */
8358 fprintf (stream
, "%s\n", message
);
8360 left
= size
- (start
- message
) - len
- 2;
8362 gas_assert (left
>= 0);
8364 p
= mempcpy (p
, name
, len
);
8369 fprintf (stream
, "%s\n", message
);
8373 md_show_usage (FILE *stream
)
8375 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8376 fprintf (stream
, _("\
8378 -V print assembler version number\n\
8381 fprintf (stream
, _("\
8382 -n Do not optimize code alignment\n\
8383 -q quieten some warnings\n"));
8384 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8385 fprintf (stream
, _("\
8388 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8389 || defined (TE_PE) || defined (TE_PEP))
8390 fprintf (stream
, _("\
8391 --32/--64 generate 32bit/64bit code\n"));
8393 #ifdef SVR4_COMMENT_CHARS
8394 fprintf (stream
, _("\
8395 --divide do not treat `/' as a comment character\n"));
8397 fprintf (stream
, _("\
8398 --divide ignored\n"));
8400 fprintf (stream
, _("\
8401 -march=CPU[,+EXTENSION...]\n\
8402 generate code for CPU and EXTENSION, CPU is one of:\n"));
8403 show_arch (stream
, 0);
8404 fprintf (stream
, _("\
8405 EXTENSION is combination of:\n"));
8406 show_arch (stream
, 1);
8407 fprintf (stream
, _("\
8408 -mtune=CPU optimize for CPU, CPU is one of:\n"));
8409 show_arch (stream
, 0);
8410 fprintf (stream
, _("\
8411 -msse2avx encode SSE instructions with VEX prefix\n"));
8412 fprintf (stream
, _("\
8413 -msse-check=[none|error|warning]\n\
8414 check SSE instructions\n"));
8415 fprintf (stream
, _("\
8416 -mavxscalar=[128|256] encode scalar AVX instructions with specific vector\n\
8418 fprintf (stream
, _("\
8419 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8420 fprintf (stream
, _("\
8421 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8422 fprintf (stream
, _("\
8423 -mindex-reg support pseudo index registers\n"));
8424 fprintf (stream
, _("\
8425 -mnaked-reg don't require `%%' prefix for registers\n"));
8426 fprintf (stream
, _("\
8427 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8430 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8431 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8432 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8434 /* Pick the target format to use. */
8437 i386_target_format (void)
8439 if (!strcmp (default_arch
, "x86_64"))
8440 set_code_flag (CODE_64BIT
);
8441 else if (!strcmp (default_arch
, "i386"))
8442 set_code_flag (CODE_32BIT
);
8444 as_fatal (_("Unknown architecture"));
8446 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8447 cpu_arch_isa_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8448 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8449 cpu_arch_tune_flags
= cpu_arch
[flag_code
== CODE_64BIT
].flags
;
8451 switch (OUTPUT_FLAVOR
)
8453 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8454 case bfd_target_aout_flavour
:
8455 return AOUT_TARGET_FORMAT
;
8457 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8458 # if defined (TE_PE) || defined (TE_PEP)
8459 case bfd_target_coff_flavour
:
8460 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8461 # elif defined (TE_GO32)
8462 case bfd_target_coff_flavour
:
8465 case bfd_target_coff_flavour
:
8469 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8470 case bfd_target_elf_flavour
:
8472 if (flag_code
== CODE_64BIT
)
8475 use_rela_relocations
= 1;
8477 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8479 if (flag_code
!= CODE_64BIT
)
8480 as_fatal (_("Intel L1OM is 64bit only"));
8481 return ELF_TARGET_L1OM_FORMAT
;
8484 return (flag_code
== CODE_64BIT
8485 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8488 #if defined (OBJ_MACH_O)
8489 case bfd_target_mach_o_flavour
:
8490 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8498 #endif /* OBJ_MAYBE_ more than one */
8500 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8502 i386_elf_emit_arch_note (void)
8504 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8507 asection
*seg
= now_seg
;
8508 subsegT subseg
= now_subseg
;
8509 Elf_Internal_Note i_note
;
8510 Elf_External_Note e_note
;
8511 asection
*note_secp
;
8514 /* Create the .note section. */
8515 note_secp
= subseg_new (".note", 0);
8516 bfd_set_section_flags (stdoutput
,
8518 SEC_HAS_CONTENTS
| SEC_READONLY
);
8520 /* Process the arch string. */
8521 len
= strlen (cpu_arch_name
);
8523 i_note
.namesz
= len
+ 1;
8525 i_note
.type
= NT_ARCH
;
8526 p
= frag_more (sizeof (e_note
.namesz
));
8527 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8528 p
= frag_more (sizeof (e_note
.descsz
));
8529 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8530 p
= frag_more (sizeof (e_note
.type
));
8531 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8532 p
= frag_more (len
+ 1);
8533 strcpy (p
, cpu_arch_name
);
8535 frag_align (2, 0, 0);
8537 subseg_set (seg
, subseg
);
8543 md_undefined_symbol (name
)
8546 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8547 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8548 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8549 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8553 if (symbol_find (name
))
8554 as_bad (_("GOT already in symbol table"));
8555 GOT_symbol
= symbol_new (name
, undefined_section
,
8556 (valueT
) 0, &zero_address_frag
);
8563 /* Round up a section size to the appropriate boundary. */
8566 md_section_align (segment
, size
)
8567 segT segment ATTRIBUTE_UNUSED
;
8570 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8571 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8573 /* For a.out, force the section size to be aligned. If we don't do
8574 this, BFD will align it for us, but it will not write out the
8575 final bytes of the section. This may be a bug in BFD, but it is
8576 easier to fix it here since that is how the other a.out targets
8580 align
= bfd_get_section_alignment (stdoutput
, segment
);
8581 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8588 /* On the i386, PC-relative offsets are relative to the start of the
8589 next instruction. That is, the address of the offset, plus its
8590 size, since the offset is always the last part of the insn. */
8593 md_pcrel_from (fixS
*fixP
)
8595 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8601 s_bss (int ignore ATTRIBUTE_UNUSED
)
8605 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8607 obj_elf_section_change_hook ();
8609 temp
= get_absolute_expression ();
8610 subseg_set (bss_section
, (subsegT
) temp
);
8611 demand_empty_rest_of_line ();
8617 i386_validate_fix (fixS
*fixp
)
8619 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8621 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8625 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8630 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8632 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8639 tc_gen_reloc (section
, fixp
)
8640 asection
*section ATTRIBUTE_UNUSED
;
8644 bfd_reloc_code_real_type code
;
8646 switch (fixp
->fx_r_type
)
8648 case BFD_RELOC_X86_64_PLT32
:
8649 case BFD_RELOC_X86_64_GOT32
:
8650 case BFD_RELOC_X86_64_GOTPCREL
:
8651 case BFD_RELOC_386_PLT32
:
8652 case BFD_RELOC_386_GOT32
:
8653 case BFD_RELOC_386_GOTOFF
:
8654 case BFD_RELOC_386_GOTPC
:
8655 case BFD_RELOC_386_TLS_GD
:
8656 case BFD_RELOC_386_TLS_LDM
:
8657 case BFD_RELOC_386_TLS_LDO_32
:
8658 case BFD_RELOC_386_TLS_IE_32
:
8659 case BFD_RELOC_386_TLS_IE
:
8660 case BFD_RELOC_386_TLS_GOTIE
:
8661 case BFD_RELOC_386_TLS_LE_32
:
8662 case BFD_RELOC_386_TLS_LE
:
8663 case BFD_RELOC_386_TLS_GOTDESC
:
8664 case BFD_RELOC_386_TLS_DESC_CALL
:
8665 case BFD_RELOC_X86_64_TLSGD
:
8666 case BFD_RELOC_X86_64_TLSLD
:
8667 case BFD_RELOC_X86_64_DTPOFF32
:
8668 case BFD_RELOC_X86_64_DTPOFF64
:
8669 case BFD_RELOC_X86_64_GOTTPOFF
:
8670 case BFD_RELOC_X86_64_TPOFF32
:
8671 case BFD_RELOC_X86_64_TPOFF64
:
8672 case BFD_RELOC_X86_64_GOTOFF64
:
8673 case BFD_RELOC_X86_64_GOTPC32
:
8674 case BFD_RELOC_X86_64_GOT64
:
8675 case BFD_RELOC_X86_64_GOTPCREL64
:
8676 case BFD_RELOC_X86_64_GOTPC64
:
8677 case BFD_RELOC_X86_64_GOTPLT64
:
8678 case BFD_RELOC_X86_64_PLTOFF64
:
8679 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8680 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8682 case BFD_RELOC_VTABLE_ENTRY
:
8683 case BFD_RELOC_VTABLE_INHERIT
:
8685 case BFD_RELOC_32_SECREL
:
8687 code
= fixp
->fx_r_type
;
8689 case BFD_RELOC_X86_64_32S
:
8690 if (!fixp
->fx_pcrel
)
8692 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8693 code
= fixp
->fx_r_type
;
8699 switch (fixp
->fx_size
)
8702 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8703 _("can not do %d byte pc-relative relocation"),
8705 code
= BFD_RELOC_32_PCREL
;
8707 case 1: code
= BFD_RELOC_8_PCREL
; break;
8708 case 2: code
= BFD_RELOC_16_PCREL
; break;
8709 case 4: code
= BFD_RELOC_32_PCREL
; break;
8711 case 8: code
= BFD_RELOC_64_PCREL
; break;
8717 switch (fixp
->fx_size
)
8720 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8721 _("can not do %d byte relocation"),
8723 code
= BFD_RELOC_32
;
8725 case 1: code
= BFD_RELOC_8
; break;
8726 case 2: code
= BFD_RELOC_16
; break;
8727 case 4: code
= BFD_RELOC_32
; break;
8729 case 8: code
= BFD_RELOC_64
; break;
8736 if ((code
== BFD_RELOC_32
8737 || code
== BFD_RELOC_32_PCREL
8738 || code
== BFD_RELOC_X86_64_32S
)
8740 && fixp
->fx_addsy
== GOT_symbol
)
8743 code
= BFD_RELOC_386_GOTPC
;
8745 code
= BFD_RELOC_X86_64_GOTPC32
;
8747 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8749 && fixp
->fx_addsy
== GOT_symbol
)
8751 code
= BFD_RELOC_X86_64_GOTPC64
;
8754 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8755 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8756 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8758 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8760 if (!use_rela_relocations
)
8762 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8763 vtable entry to be used in the relocation's section offset. */
8764 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8765 rel
->address
= fixp
->fx_offset
;
8766 #if defined (OBJ_COFF) && defined (TE_PE)
8767 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8768 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8773 /* Use the rela in 64bit mode. */
8776 if (!fixp
->fx_pcrel
)
8777 rel
->addend
= fixp
->fx_offset
;
8781 case BFD_RELOC_X86_64_PLT32
:
8782 case BFD_RELOC_X86_64_GOT32
:
8783 case BFD_RELOC_X86_64_GOTPCREL
:
8784 case BFD_RELOC_X86_64_TLSGD
:
8785 case BFD_RELOC_X86_64_TLSLD
:
8786 case BFD_RELOC_X86_64_GOTTPOFF
:
8787 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8788 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8789 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8792 rel
->addend
= (section
->vma
8794 + fixp
->fx_addnumber
8795 + md_pcrel_from (fixp
));
8800 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8801 if (rel
->howto
== NULL
)
8803 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8804 _("cannot represent relocation type %s"),
8805 bfd_get_reloc_code_name (code
));
8806 /* Set howto to a garbage value so that we can keep going. */
8807 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8808 gas_assert (rel
->howto
!= NULL
);
8814 #include "tc-i386-intel.c"
8817 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8819 int saved_naked_reg
;
8820 char saved_register_dot
;
8822 saved_naked_reg
= allow_naked_reg
;
8823 allow_naked_reg
= 1;
8824 saved_register_dot
= register_chars
['.'];
8825 register_chars
['.'] = '.';
8826 allow_pseudo_reg
= 1;
8827 expression_and_evaluate (exp
);
8828 allow_pseudo_reg
= 0;
8829 register_chars
['.'] = saved_register_dot
;
8830 allow_naked_reg
= saved_naked_reg
;
8832 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8834 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8836 exp
->X_op
= O_constant
;
8837 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8838 .dw2_regnum
[flag_code
>> 1];
8841 exp
->X_op
= O_illegal
;
8846 tc_x86_frame_initial_instructions (void)
8848 static unsigned int sp_regno
[2];
8850 if (!sp_regno
[flag_code
>> 1])
8852 char *saved_input
= input_line_pointer
;
8853 char sp
[][4] = {"esp", "rsp"};
8856 input_line_pointer
= sp
[flag_code
>> 1];
8857 tc_x86_parse_to_dw2regnum (&exp
);
8858 gas_assert (exp
.X_op
== O_constant
);
8859 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8860 input_line_pointer
= saved_input
;
8863 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8864 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8868 i386_elf_section_type (const char *str
, size_t len
)
8870 if (flag_code
== CODE_64BIT
8871 && len
== sizeof ("unwind") - 1
8872 && strncmp (str
, "unwind", 6) == 0)
8873 return SHT_X86_64_UNWIND
;
8880 i386_solaris_fix_up_eh_frame (segT sec
)
8882 if (flag_code
== CODE_64BIT
)
8883 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8889 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8893 exp
.X_op
= O_secrel
;
8894 exp
.X_add_symbol
= symbol
;
8895 exp
.X_add_number
= 0;
8896 emit_expr (&exp
, size
);
8900 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8901 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8904 x86_64_section_letter (int letter
, char **ptr_msg
)
8906 if (flag_code
== CODE_64BIT
)
8909 return SHF_X86_64_LARGE
;
8911 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8914 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8919 x86_64_section_word (char *str
, size_t len
)
8921 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8922 return SHF_X86_64_LARGE
;
8928 handle_large_common (int small ATTRIBUTE_UNUSED
)
8930 if (flag_code
!= CODE_64BIT
)
8932 s_comm_internal (0, elf_common_parse
);
8933 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8937 static segT lbss_section
;
8938 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8939 asection
*saved_bss_section
= bss_section
;
8941 if (lbss_section
== NULL
)
8943 flagword applicable
;
8945 subsegT subseg
= now_subseg
;
8947 /* The .lbss section is for local .largecomm symbols. */
8948 lbss_section
= subseg_new (".lbss", 0);
8949 applicable
= bfd_applicable_section_flags (stdoutput
);
8950 bfd_set_section_flags (stdoutput
, lbss_section
,
8951 applicable
& SEC_ALLOC
);
8952 seg_info (lbss_section
)->bss
= 1;
8954 subseg_set (seg
, subseg
);
8957 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8958 bss_section
= lbss_section
;
8960 s_comm_internal (0, elf_common_parse
);
8962 elf_com_section_ptr
= saved_com_section_ptr
;
8963 bss_section
= saved_bss_section
;
8966 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */