1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "elf/x86-64.h"
36 #include "opcodes/i386-init.h"
38 #ifndef REGISTER_WARNINGS
39 #define REGISTER_WARNINGS 1
42 #ifndef INFER_ADDR_PREFIX
43 #define INFER_ADDR_PREFIX 1
47 #define DEFAULT_ARCH "i386"
52 #define INLINE __inline__
58 /* Prefixes will be emitted in the order defined below.
59 WAIT_PREFIX must be the first prefix since FWAIT is really is an
60 instruction, and so must come before any prefixes.
61 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
67 #define LOCKREP_PREFIX 4
68 #define REX_PREFIX 5 /* must come last. */
69 #define MAX_PREFIXES 6 /* max prefixes per opcode */
71 /* we define the syntax here (modulo base,index,scale syntax) */
72 #define REGISTER_PREFIX '%'
73 #define IMMEDIATE_PREFIX '$'
74 #define ABSOLUTE_PREFIX '*'
76 /* these are the instruction mnemonic suffixes in AT&T syntax or
77 memory operand size in Intel syntax. */
78 #define WORD_MNEM_SUFFIX 'w'
79 #define BYTE_MNEM_SUFFIX 'b'
80 #define SHORT_MNEM_SUFFIX 's'
81 #define LONG_MNEM_SUFFIX 'l'
82 #define QWORD_MNEM_SUFFIX 'q'
83 #define XMMWORD_MNEM_SUFFIX 'x'
84 #define YMMWORD_MNEM_SUFFIX 'y'
85 /* Intel Syntax. Use a non-ascii letter since since it never appears
87 #define LONG_DOUBLE_MNEM_SUFFIX '\1'
89 #define END_OF_INSN '\0'
92 'templates' is for grouping together 'template' structures for opcodes
93 of the same name. This is only used for storing the insns in the grand
94 ole hash table of insns.
95 The templates themselves start at START and range up to (but not including)
100 const insn_template
*start
;
101 const insn_template
*end
;
105 /* 386 operand encoding bytes: see 386 book for details of this. */
108 unsigned int regmem
; /* codes register or memory operand */
109 unsigned int reg
; /* codes register operand (or extended opcode) */
110 unsigned int mode
; /* how to interpret regmem & reg */
114 /* x86-64 extension prefix. */
115 typedef int rex_byte
;
117 /* 386 opcode byte to code indirect addressing. */
126 /* x86 arch names, types and features */
129 const char *name
; /* arch name */
130 enum processor_type type
; /* arch type */
131 i386_cpu_flags flags
; /* cpu feature flags */
135 static void set_code_flag (int);
136 static void set_16bit_gcc_code_flag (int);
137 static void set_intel_syntax (int);
138 static void set_intel_mnemonic (int);
139 static void set_allow_index_reg (int);
140 static void set_sse_check (int);
141 static void set_cpu_arch (int);
143 static void pe_directive_secrel (int);
145 static void signed_cons (int);
146 static char *output_invalid (int c
);
147 static int i386_finalize_immediate (segT
, expressionS
*, i386_operand_type
,
149 static int i386_finalize_displacement (segT
, expressionS
*, i386_operand_type
,
151 static int i386_att_operand (char *);
152 static int i386_intel_operand (char *, int);
153 static int i386_intel_simplify (expressionS
*);
154 static int i386_intel_parse_name (const char *, expressionS
*);
155 static const reg_entry
*parse_register (char *, char **);
156 static char *parse_insn (char *, char *);
157 static char *parse_operands (char *, const char *);
158 static void swap_operands (void);
159 static void swap_2_operands (int, int);
160 static void optimize_imm (void);
161 static void optimize_disp (void);
162 static const insn_template
*match_template (void);
163 static int check_string (void);
164 static int process_suffix (void);
165 static int check_byte_reg (void);
166 static int check_long_reg (void);
167 static int check_qword_reg (void);
168 static int check_word_reg (void);
169 static int finalize_imm (void);
170 static int process_operands (void);
171 static const seg_entry
*build_modrm_byte (void);
172 static void output_insn (void);
173 static void output_imm (fragS
*, offsetT
);
174 static void output_disp (fragS
*, offsetT
);
176 static void s_bss (int);
178 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
179 static void handle_large_common (int small ATTRIBUTE_UNUSED
);
182 static const char *default_arch
= DEFAULT_ARCH
;
187 /* VEX prefix is either 2 byte or 3 byte. */
188 unsigned char bytes
[3];
190 /* Destination or source register specifier. */
191 const reg_entry
*register_specifier
;
194 /* 'md_assemble ()' gathers together information and puts it into a
201 const reg_entry
*regs
;
206 /* TM holds the template for the insn were currently assembling. */
209 /* SUFFIX holds the instruction size suffix for byte, word, dword
210 or qword, if given. */
213 /* OPERANDS gives the number of given operands. */
214 unsigned int operands
;
216 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
217 of given register, displacement, memory operands and immediate
219 unsigned int reg_operands
, disp_operands
, mem_operands
, imm_operands
;
221 /* TYPES [i] is the type (see above #defines) which tells us how to
222 use OP[i] for the corresponding operand. */
223 i386_operand_type types
[MAX_OPERANDS
];
225 /* Displacement expression, immediate expression, or register for each
227 union i386_op op
[MAX_OPERANDS
];
229 /* Flags for operands. */
230 unsigned int flags
[MAX_OPERANDS
];
231 #define Operand_PCrel 1
233 /* Relocation type for operand */
234 enum bfd_reloc_code_real reloc
[MAX_OPERANDS
];
236 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
237 the base index byte below. */
238 const reg_entry
*base_reg
;
239 const reg_entry
*index_reg
;
240 unsigned int log2_scale_factor
;
242 /* SEG gives the seg_entries of this insn. They are zero unless
243 explicit segment overrides are given. */
244 const seg_entry
*seg
[2];
246 /* PREFIX holds all the given prefix opcodes (usually null).
247 PREFIXES is the number of prefix opcodes. */
248 unsigned int prefixes
;
249 unsigned char prefix
[MAX_PREFIXES
];
251 /* RM and SIB are the modrm byte and the sib byte where the
252 addressing modes of this insn are encoded. */
258 /* Swap operand in encoding. */
259 unsigned int swap_operand
: 1;
262 typedef struct _i386_insn i386_insn
;
264 /* List of chars besides those in app.c:symbol_chars that can start an
265 operand. Used to prevent the scrubber eating vital white-space. */
266 const char extra_symbol_chars
[] = "*%-(["
275 #if (defined (TE_I386AIX) \
276 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
277 && !defined (TE_GNU) \
278 && !defined (TE_LINUX) \
279 && !defined (TE_NETWARE) \
280 && !defined (TE_FreeBSD) \
281 && !defined (TE_NetBSD)))
282 /* This array holds the chars that always start a comment. If the
283 pre-processor is disabled, these aren't very useful. The option
284 --divide will remove '/' from this list. */
285 const char *i386_comment_chars
= "#/";
286 #define SVR4_COMMENT_CHARS 1
287 #define PREFIX_SEPARATOR '\\'
290 const char *i386_comment_chars
= "#";
291 #define PREFIX_SEPARATOR '/'
294 /* This array holds the chars that only start a comment at the beginning of
295 a line. If the line seems to have the form '# 123 filename'
296 .line and .file directives will appear in the pre-processed output.
297 Note that input_file.c hand checks for '#' at the beginning of the
298 first line of the input file. This is because the compiler outputs
299 #NO_APP at the beginning of its output.
300 Also note that comments started like this one will always work if
301 '/' isn't otherwise defined. */
302 const char line_comment_chars
[] = "#/";
304 const char line_separator_chars
[] = ";";
306 /* Chars that can be used to separate mant from exp in floating point
308 const char EXP_CHARS
[] = "eE";
310 /* Chars that mean this number is a floating point constant
313 const char FLT_CHARS
[] = "fFdDxX";
315 /* Tables for lexical analysis. */
316 static char mnemonic_chars
[256];
317 static char register_chars
[256];
318 static char operand_chars
[256];
319 static char identifier_chars
[256];
320 static char digit_chars
[256];
322 /* Lexical macros. */
323 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
324 #define is_operand_char(x) (operand_chars[(unsigned char) x])
325 #define is_register_char(x) (register_chars[(unsigned char) x])
326 #define is_space_char(x) ((x) == ' ')
327 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
328 #define is_digit_char(x) (digit_chars[(unsigned char) x])
330 /* All non-digit non-letter characters that may occur in an operand. */
331 static char operand_special_chars
[] = "%$-+(,)*._~/<>|&^!:[@]";
333 /* md_assemble() always leaves the strings it's passed unaltered. To
334 effect this we maintain a stack of saved characters that we've smashed
335 with '\0's (indicating end of strings for various sub-fields of the
336 assembler instruction). */
337 static char save_stack
[32];
338 static char *save_stack_p
;
339 #define END_STRING_AND_SAVE(s) \
340 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
341 #define RESTORE_END_STRING(s) \
342 do { *(s) = *--save_stack_p; } while (0)
344 /* The instruction we're assembling. */
347 /* Possible templates for current insn. */
348 static const templates
*current_templates
;
350 /* Per instruction expressionS buffers: max displacements & immediates. */
351 static expressionS disp_expressions
[MAX_MEMORY_OPERANDS
];
352 static expressionS im_expressions
[MAX_IMMEDIATE_OPERANDS
];
354 /* Current operand we are working on. */
355 static int this_operand
= -1;
357 /* We support four different modes. FLAG_CODE variable is used to distinguish
365 static enum flag_code flag_code
;
366 static unsigned int object_64bit
;
367 static int use_rela_relocations
= 0;
369 /* The names used to print error messages. */
370 static const char *flag_code_names
[] =
377 /* 1 for intel syntax,
379 static int intel_syntax
= 0;
381 /* 1 for intel mnemonic,
382 0 if att mnemonic. */
383 static int intel_mnemonic
= !SYSV386_COMPAT
;
385 /* 1 if support old (<= 2.8.1) versions of gcc. */
386 static int old_gcc
= OLDGCC_COMPAT
;
388 /* 1 if pseudo registers are permitted. */
389 static int allow_pseudo_reg
= 0;
391 /* 1 if register prefix % not required. */
392 static int allow_naked_reg
= 0;
394 /* 1 if pseudo index register, eiz/riz, is allowed . */
395 static int allow_index_reg
= 0;
405 /* Register prefix used for error message. */
406 static const char *register_prefix
= "%";
408 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
409 leave, push, and pop instructions so that gcc has the same stack
410 frame as in 32 bit mode. */
411 static char stackop_size
= '\0';
413 /* Non-zero to optimize code alignment. */
414 int optimize_align_code
= 1;
416 /* Non-zero to quieten some warnings. */
417 static int quiet_warnings
= 0;
420 static const char *cpu_arch_name
= NULL
;
421 static char *cpu_sub_arch_name
= NULL
;
423 /* CPU feature flags. */
424 static i386_cpu_flags cpu_arch_flags
= CPU_UNKNOWN_FLAGS
;
426 /* If we have selected a cpu we are generating instructions for. */
427 static int cpu_arch_tune_set
= 0;
429 /* Cpu we are generating instructions for. */
430 enum processor_type cpu_arch_tune
= PROCESSOR_UNKNOWN
;
432 /* CPU feature flags of cpu we are generating instructions for. */
433 static i386_cpu_flags cpu_arch_tune_flags
;
435 /* CPU instruction set architecture used. */
436 enum processor_type cpu_arch_isa
= PROCESSOR_UNKNOWN
;
438 /* CPU feature flags of instruction set architecture used. */
439 i386_cpu_flags cpu_arch_isa_flags
;
441 /* If set, conditional jumps are not automatically promoted to handle
442 larger than a byte offset. */
443 static unsigned int no_cond_jump_promotion
= 0;
445 /* Encode SSE instructions with VEX prefix. */
446 static unsigned int sse2avx
;
448 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
449 static symbolS
*GOT_symbol
;
451 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
452 unsigned int x86_dwarf2_return_column
;
454 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
455 int x86_cie_data_alignment
;
457 /* Interface to relax_segment.
458 There are 3 major relax states for 386 jump insns because the
459 different types of jumps add different sizes to frags when we're
460 figuring out what sort of jump to choose to reach a given label. */
463 #define UNCOND_JUMP 0
465 #define COND_JUMP86 2
470 #define SMALL16 (SMALL | CODE16)
472 #define BIG16 (BIG | CODE16)
476 #define INLINE __inline__
482 #define ENCODE_RELAX_STATE(type, size) \
483 ((relax_substateT) (((type) << 2) | (size)))
484 #define TYPE_FROM_RELAX_STATE(s) \
486 #define DISP_SIZE_FROM_RELAX_STATE(s) \
487 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
489 /* This table is used by relax_frag to promote short jumps to long
490 ones where necessary. SMALL (short) jumps may be promoted to BIG
491 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
492 don't allow a short jump in a 32 bit code segment to be promoted to
493 a 16 bit offset jump because it's slower (requires data size
494 prefix), and doesn't work, unless the destination is in the bottom
495 64k of the code segment (The top 16 bits of eip are zeroed). */
497 const relax_typeS md_relax_table
[] =
500 1) most positive reach of this state,
501 2) most negative reach of this state,
502 3) how many bytes this mode will have in the variable part of the frag
503 4) which index into the table to try if we can't fit into this one. */
505 /* UNCOND_JUMP states. */
506 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
)},
507 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
)},
508 /* dword jmp adds 4 bytes to frag:
509 0 extra opcode bytes, 4 displacement bytes. */
511 /* word jmp adds 2 byte2 to frag:
512 0 extra opcode bytes, 2 displacement bytes. */
515 /* COND_JUMP states. */
516 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG
)},
517 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP
, BIG16
)},
518 /* dword conditionals adds 5 bytes to frag:
519 1 extra opcode byte, 4 displacement bytes. */
521 /* word conditionals add 3 bytes to frag:
522 1 extra opcode byte, 2 displacement bytes. */
525 /* COND_JUMP86 states. */
526 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG
)},
527 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
)},
528 /* dword conditionals adds 5 bytes to frag:
529 1 extra opcode byte, 4 displacement bytes. */
531 /* word conditionals add 4 bytes to frag:
532 1 displacement byte and a 3 byte long branch insn. */
536 static const arch_entry cpu_arch
[] =
538 { "generic32", PROCESSOR_GENERIC32
,
539 CPU_GENERIC32_FLAGS
},
540 { "generic64", PROCESSOR_GENERIC64
,
541 CPU_GENERIC64_FLAGS
},
542 { "i8086", PROCESSOR_UNKNOWN
,
544 { "i186", PROCESSOR_UNKNOWN
,
546 { "i286", PROCESSOR_UNKNOWN
,
548 { "i386", PROCESSOR_I386
,
550 { "i486", PROCESSOR_I486
,
552 { "i586", PROCESSOR_PENTIUM
,
554 { "i686", PROCESSOR_PENTIUMPRO
,
556 { "pentium", PROCESSOR_PENTIUM
,
558 { "pentiumpro", PROCESSOR_PENTIUMPRO
,
560 { "pentiumii", PROCESSOR_PENTIUMPRO
,
562 { "pentiumiii",PROCESSOR_PENTIUMPRO
,
564 { "pentium4", PROCESSOR_PENTIUM4
,
566 { "prescott", PROCESSOR_NOCONA
,
568 { "nocona", PROCESSOR_NOCONA
,
570 { "yonah", PROCESSOR_CORE
,
572 { "core", PROCESSOR_CORE
,
574 { "merom", PROCESSOR_CORE2
,
576 { "core2", PROCESSOR_CORE2
,
578 { "corei7", PROCESSOR_COREI7
,
580 { "l1om", PROCESSOR_L1OM
,
582 { "k6", PROCESSOR_K6
,
584 { "k6_2", PROCESSOR_K6
,
586 { "athlon", PROCESSOR_ATHLON
,
588 { "sledgehammer", PROCESSOR_K8
,
590 { "opteron", PROCESSOR_K8
,
592 { "k8", PROCESSOR_K8
,
594 { "amdfam10", PROCESSOR_AMDFAM10
,
595 CPU_AMDFAM10_FLAGS
},
596 { ".8087", PROCESSOR_UNKNOWN
,
598 { ".287", PROCESSOR_UNKNOWN
,
600 { ".387", PROCESSOR_UNKNOWN
,
602 { ".no87", PROCESSOR_UNKNOWN
,
604 { ".mmx", PROCESSOR_UNKNOWN
,
606 { ".nommx", PROCESSOR_UNKNOWN
,
608 { ".sse", PROCESSOR_UNKNOWN
,
610 { ".sse2", PROCESSOR_UNKNOWN
,
612 { ".sse3", PROCESSOR_UNKNOWN
,
614 { ".ssse3", PROCESSOR_UNKNOWN
,
616 { ".sse4.1", PROCESSOR_UNKNOWN
,
618 { ".sse4.2", PROCESSOR_UNKNOWN
,
620 { ".sse4", PROCESSOR_UNKNOWN
,
622 { ".nosse", PROCESSOR_UNKNOWN
,
624 { ".avx", PROCESSOR_UNKNOWN
,
626 { ".noavx", PROCESSOR_UNKNOWN
,
628 { ".vmx", PROCESSOR_UNKNOWN
,
630 { ".smx", PROCESSOR_UNKNOWN
,
632 { ".xsave", PROCESSOR_UNKNOWN
,
634 { ".aes", PROCESSOR_UNKNOWN
,
636 { ".pclmul", PROCESSOR_UNKNOWN
,
638 { ".clmul", PROCESSOR_UNKNOWN
,
640 { ".fma", PROCESSOR_UNKNOWN
,
642 { ".fma4", PROCESSOR_UNKNOWN
,
644 { ".lwp", PROCESSOR_UNKNOWN
,
646 { ".movbe", PROCESSOR_UNKNOWN
,
648 { ".ept", PROCESSOR_UNKNOWN
,
650 { ".clflush", PROCESSOR_UNKNOWN
,
652 { ".syscall", PROCESSOR_UNKNOWN
,
654 { ".rdtscp", PROCESSOR_UNKNOWN
,
656 { ".3dnow", PROCESSOR_UNKNOWN
,
658 { ".3dnowa", PROCESSOR_UNKNOWN
,
660 { ".padlock", PROCESSOR_UNKNOWN
,
662 { ".pacifica", PROCESSOR_UNKNOWN
,
664 { ".svme", PROCESSOR_UNKNOWN
,
666 { ".sse4a", PROCESSOR_UNKNOWN
,
668 { ".abm", PROCESSOR_UNKNOWN
,
673 /* Like s_lcomm_internal in gas/read.c but the alignment string
674 is allowed to be optional. */
677 pe_lcomm_internal (int needs_align
, symbolS
*symbolP
, addressT size
)
684 && *input_line_pointer
== ',')
686 align
= parse_align (needs_align
- 1);
688 if (align
== (addressT
) -1)
703 bss_alloc (symbolP
, size
, align
);
708 pe_lcomm (int needs_align
)
710 s_comm_internal (needs_align
* 2, pe_lcomm_internal
);
714 const pseudo_typeS md_pseudo_table
[] =
716 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
717 {"align", s_align_bytes
, 0},
719 {"align", s_align_ptwo
, 0},
721 {"arch", set_cpu_arch
, 0},
725 {"lcomm", pe_lcomm
, 1},
727 {"ffloat", float_cons
, 'f'},
728 {"dfloat", float_cons
, 'd'},
729 {"tfloat", float_cons
, 'x'},
731 {"slong", signed_cons
, 4},
732 {"noopt", s_ignore
, 0},
733 {"optim", s_ignore
, 0},
734 {"code16gcc", set_16bit_gcc_code_flag
, CODE_16BIT
},
735 {"code16", set_code_flag
, CODE_16BIT
},
736 {"code32", set_code_flag
, CODE_32BIT
},
737 {"code64", set_code_flag
, CODE_64BIT
},
738 {"intel_syntax", set_intel_syntax
, 1},
739 {"att_syntax", set_intel_syntax
, 0},
740 {"intel_mnemonic", set_intel_mnemonic
, 1},
741 {"att_mnemonic", set_intel_mnemonic
, 0},
742 {"allow_index_reg", set_allow_index_reg
, 1},
743 {"disallow_index_reg", set_allow_index_reg
, 0},
744 {"sse_check", set_sse_check
, 0},
745 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
746 {"largecomm", handle_large_common
, 0},
748 {"file", (void (*) (int)) dwarf2_directive_file
, 0},
749 {"loc", dwarf2_directive_loc
, 0},
750 {"loc_mark_labels", dwarf2_directive_loc_mark_labels
, 0},
753 {"secrel32", pe_directive_secrel
, 0},
758 /* For interface with expression (). */
759 extern char *input_line_pointer
;
761 /* Hash table for instruction mnemonic lookup. */
762 static struct hash_control
*op_hash
;
764 /* Hash table for register lookup. */
765 static struct hash_control
*reg_hash
;
768 i386_align_code (fragS
*fragP
, int count
)
770 /* Various efficient no-op patterns for aligning code labels.
771 Note: Don't try to assemble the instructions in the comments.
772 0L and 0w are not legal. */
773 static const char f32_1
[] =
775 static const char f32_2
[] =
776 {0x66,0x90}; /* xchg %ax,%ax */
777 static const char f32_3
[] =
778 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
779 static const char f32_4
[] =
780 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
781 static const char f32_5
[] =
783 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
784 static const char f32_6
[] =
785 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
786 static const char f32_7
[] =
787 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
788 static const char f32_8
[] =
790 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
791 static const char f32_9
[] =
792 {0x89,0xf6, /* movl %esi,%esi */
793 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
794 static const char f32_10
[] =
795 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
796 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
797 static const char f32_11
[] =
798 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
799 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
800 static const char f32_12
[] =
801 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
802 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
803 static const char f32_13
[] =
804 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
805 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
806 static const char f32_14
[] =
807 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
808 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
809 static const char f16_3
[] =
810 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
811 static const char f16_4
[] =
812 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
813 static const char f16_5
[] =
815 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
816 static const char f16_6
[] =
817 {0x89,0xf6, /* mov %si,%si */
818 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
819 static const char f16_7
[] =
820 {0x8d,0x74,0x00, /* lea 0(%si),%si */
821 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
822 static const char f16_8
[] =
823 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
824 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
825 static const char jump_31
[] =
826 {0xeb,0x1d,0x90,0x90,0x90,0x90,0x90, /* jmp .+31; lotsa nops */
827 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
828 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90,
829 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
830 static const char *const f32_patt
[] = {
831 f32_1
, f32_2
, f32_3
, f32_4
, f32_5
, f32_6
, f32_7
, f32_8
,
832 f32_9
, f32_10
, f32_11
, f32_12
, f32_13
, f32_14
834 static const char *const f16_patt
[] = {
835 f32_1
, f32_2
, f16_3
, f16_4
, f16_5
, f16_6
, f16_7
, f16_8
838 static const char alt_3
[] =
840 /* nopl 0(%[re]ax) */
841 static const char alt_4
[] =
842 {0x0f,0x1f,0x40,0x00};
843 /* nopl 0(%[re]ax,%[re]ax,1) */
844 static const char alt_5
[] =
845 {0x0f,0x1f,0x44,0x00,0x00};
846 /* nopw 0(%[re]ax,%[re]ax,1) */
847 static const char alt_6
[] =
848 {0x66,0x0f,0x1f,0x44,0x00,0x00};
849 /* nopl 0L(%[re]ax) */
850 static const char alt_7
[] =
851 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
852 /* nopl 0L(%[re]ax,%[re]ax,1) */
853 static const char alt_8
[] =
854 {0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
855 /* nopw 0L(%[re]ax,%[re]ax,1) */
856 static const char alt_9
[] =
857 {0x66,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
858 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
859 static const char alt_10
[] =
860 {0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
862 nopw %cs:0L(%[re]ax,%[re]ax,1) */
863 static const char alt_long_11
[] =
865 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
868 nopw %cs:0L(%[re]ax,%[re]ax,1) */
869 static const char alt_long_12
[] =
872 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
876 nopw %cs:0L(%[re]ax,%[re]ax,1) */
877 static const char alt_long_13
[] =
881 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
886 nopw %cs:0L(%[re]ax,%[re]ax,1) */
887 static const char alt_long_14
[] =
892 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
898 nopw %cs:0L(%[re]ax,%[re]ax,1) */
899 static const char alt_long_15
[] =
905 0x66,0x2e,0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
906 /* nopl 0(%[re]ax,%[re]ax,1)
907 nopw 0(%[re]ax,%[re]ax,1) */
908 static const char alt_short_11
[] =
909 {0x0f,0x1f,0x44,0x00,0x00,
910 0x66,0x0f,0x1f,0x44,0x00,0x00};
911 /* nopw 0(%[re]ax,%[re]ax,1)
912 nopw 0(%[re]ax,%[re]ax,1) */
913 static const char alt_short_12
[] =
914 {0x66,0x0f,0x1f,0x44,0x00,0x00,
915 0x66,0x0f,0x1f,0x44,0x00,0x00};
916 /* nopw 0(%[re]ax,%[re]ax,1)
918 static const char alt_short_13
[] =
919 {0x66,0x0f,0x1f,0x44,0x00,0x00,
920 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
923 static const char alt_short_14
[] =
924 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
925 0x0f,0x1f,0x80,0x00,0x00,0x00,0x00};
927 nopl 0L(%[re]ax,%[re]ax,1) */
928 static const char alt_short_15
[] =
929 {0x0f,0x1f,0x80,0x00,0x00,0x00,0x00,
930 0x0f,0x1f,0x84,0x00,0x00,0x00,0x00,0x00};
931 static const char *const alt_short_patt
[] = {
932 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
933 alt_9
, alt_10
, alt_short_11
, alt_short_12
, alt_short_13
,
934 alt_short_14
, alt_short_15
936 static const char *const alt_long_patt
[] = {
937 f32_1
, f32_2
, alt_3
, alt_4
, alt_5
, alt_6
, alt_7
, alt_8
,
938 alt_9
, alt_10
, alt_long_11
, alt_long_12
, alt_long_13
,
939 alt_long_14
, alt_long_15
942 /* Only align for at least a positive non-zero boundary. */
943 if (count
<= 0 || count
> MAX_MEM_FOR_RS_ALIGN_CODE
)
946 /* We need to decide which NOP sequence to use for 32bit and
947 64bit. When -mtune= is used:
949 1. For PROCESSOR_I386, PROCESSOR_I486, PROCESSOR_PENTIUM and
950 PROCESSOR_GENERIC32, f32_patt will be used.
951 2. For PROCESSOR_PENTIUMPRO, PROCESSOR_PENTIUM4, PROCESSOR_NOCONA,
952 PROCESSOR_CORE, PROCESSOR_CORE2, PROCESSOR_COREI7, and
953 PROCESSOR_GENERIC64, alt_long_patt will be used.
954 3. For PROCESSOR_ATHLON, PROCESSOR_K6, PROCESSOR_K8 and
955 PROCESSOR_AMDFAM10, alt_short_patt will be used.
957 When -mtune= isn't used, alt_long_patt will be used if
958 cpu_arch_isa_flags has Cpu686. Otherwise, f32_patt will
961 When -march= or .arch is used, we can't use anything beyond
962 cpu_arch_isa_flags. */
964 if (flag_code
== CODE_16BIT
)
968 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
970 /* Adjust jump offset. */
971 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
974 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
975 f16_patt
[count
- 1], count
);
979 const char *const *patt
= NULL
;
981 if (fragP
->tc_frag_data
.isa
== PROCESSOR_UNKNOWN
)
983 /* PROCESSOR_UNKNOWN means that all ISAs may be used. */
984 switch (cpu_arch_tune
)
986 case PROCESSOR_UNKNOWN
:
987 /* We use cpu_arch_isa_flags to check if we SHOULD
988 optimize for Cpu686. */
989 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
990 patt
= alt_long_patt
;
994 case PROCESSOR_PENTIUMPRO
:
995 case PROCESSOR_PENTIUM4
:
996 case PROCESSOR_NOCONA
:
998 case PROCESSOR_CORE2
:
999 case PROCESSOR_COREI7
:
1000 case PROCESSOR_L1OM
:
1001 case PROCESSOR_GENERIC64
:
1002 patt
= alt_long_patt
;
1005 case PROCESSOR_ATHLON
:
1007 case PROCESSOR_AMDFAM10
:
1008 patt
= alt_short_patt
;
1010 case PROCESSOR_I386
:
1011 case PROCESSOR_I486
:
1012 case PROCESSOR_PENTIUM
:
1013 case PROCESSOR_GENERIC32
:
1020 switch (fragP
->tc_frag_data
.tune
)
1022 case PROCESSOR_UNKNOWN
:
1023 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1024 PROCESSOR_UNKNOWN. */
1028 case PROCESSOR_I386
:
1029 case PROCESSOR_I486
:
1030 case PROCESSOR_PENTIUM
:
1032 case PROCESSOR_ATHLON
:
1034 case PROCESSOR_AMDFAM10
:
1035 case PROCESSOR_GENERIC32
:
1036 /* We use cpu_arch_isa_flags to check if we CAN optimize
1038 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1039 patt
= alt_short_patt
;
1043 case PROCESSOR_PENTIUMPRO
:
1044 case PROCESSOR_PENTIUM4
:
1045 case PROCESSOR_NOCONA
:
1046 case PROCESSOR_CORE
:
1047 case PROCESSOR_CORE2
:
1048 case PROCESSOR_COREI7
:
1049 case PROCESSOR_L1OM
:
1050 if (fragP
->tc_frag_data
.isa_flags
.bitfield
.cpui686
)
1051 patt
= alt_long_patt
;
1055 case PROCESSOR_GENERIC64
:
1056 patt
= alt_long_patt
;
1061 if (patt
== f32_patt
)
1063 /* If the padding is less than 15 bytes, we use the normal
1064 ones. Otherwise, we use a jump instruction and adjust
1068 /* For 64bit, the limit is 3 bytes. */
1069 if (flag_code
== CODE_64BIT
1070 && fragP
->tc_frag_data
.isa_flags
.bitfield
.cpulm
)
1075 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1076 patt
[count
- 1], count
);
1079 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1081 /* Adjust jump offset. */
1082 fragP
->fr_literal
[fragP
->fr_fix
+ 1] = count
- 2;
1087 /* Maximum length of an instruction is 15 byte. If the
1088 padding is greater than 15 bytes and we don't use jump,
1089 we have to break it into smaller pieces. */
1090 int padding
= count
;
1091 while (padding
> 15)
1094 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
+ padding
,
1099 memcpy (fragP
->fr_literal
+ fragP
->fr_fix
,
1100 patt
[padding
- 1], padding
);
1103 fragP
->fr_var
= count
;
1107 operand_type_all_zero (const union i386_operand_type
*x
)
1109 switch (ARRAY_SIZE(x
->array
))
1118 return !x
->array
[0];
1125 operand_type_set (union i386_operand_type
*x
, unsigned int v
)
1127 switch (ARRAY_SIZE(x
->array
))
1142 operand_type_equal (const union i386_operand_type
*x
,
1143 const union i386_operand_type
*y
)
1145 switch (ARRAY_SIZE(x
->array
))
1148 if (x
->array
[2] != y
->array
[2])
1151 if (x
->array
[1] != y
->array
[1])
1154 return x
->array
[0] == y
->array
[0];
1162 cpu_flags_all_zero (const union i386_cpu_flags
*x
)
1164 switch (ARRAY_SIZE(x
->array
))
1173 return !x
->array
[0];
1180 cpu_flags_set (union i386_cpu_flags
*x
, unsigned int v
)
1182 switch (ARRAY_SIZE(x
->array
))
1197 cpu_flags_equal (const union i386_cpu_flags
*x
,
1198 const union i386_cpu_flags
*y
)
1200 switch (ARRAY_SIZE(x
->array
))
1203 if (x
->array
[2] != y
->array
[2])
1206 if (x
->array
[1] != y
->array
[1])
1209 return x
->array
[0] == y
->array
[0];
1217 cpu_flags_check_cpu64 (i386_cpu_flags f
)
1219 return !((flag_code
== CODE_64BIT
&& f
.bitfield
.cpuno64
)
1220 || (flag_code
!= CODE_64BIT
&& f
.bitfield
.cpu64
));
1223 static INLINE i386_cpu_flags
1224 cpu_flags_and (i386_cpu_flags x
, i386_cpu_flags y
)
1226 switch (ARRAY_SIZE (x
.array
))
1229 x
.array
[2] &= y
.array
[2];
1231 x
.array
[1] &= y
.array
[1];
1233 x
.array
[0] &= y
.array
[0];
1241 static INLINE i386_cpu_flags
1242 cpu_flags_or (i386_cpu_flags x
, i386_cpu_flags y
)
1244 switch (ARRAY_SIZE (x
.array
))
1247 x
.array
[2] |= y
.array
[2];
1249 x
.array
[1] |= y
.array
[1];
1251 x
.array
[0] |= y
.array
[0];
1259 static INLINE i386_cpu_flags
1260 cpu_flags_and_not (i386_cpu_flags x
, i386_cpu_flags y
)
1262 switch (ARRAY_SIZE (x
.array
))
1265 x
.array
[2] &= ~y
.array
[2];
1267 x
.array
[1] &= ~y
.array
[1];
1269 x
.array
[0] &= ~y
.array
[0];
1277 #define CPU_FLAGS_ARCH_MATCH 0x1
1278 #define CPU_FLAGS_64BIT_MATCH 0x2
1279 #define CPU_FLAGS_AES_MATCH 0x4
1280 #define CPU_FLAGS_PCLMUL_MATCH 0x8
1281 #define CPU_FLAGS_AVX_MATCH 0x10
1283 #define CPU_FLAGS_32BIT_MATCH \
1284 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_AES_MATCH \
1285 | CPU_FLAGS_PCLMUL_MATCH | CPU_FLAGS_AVX_MATCH)
1286 #define CPU_FLAGS_PERFECT_MATCH \
1287 (CPU_FLAGS_32BIT_MATCH | CPU_FLAGS_64BIT_MATCH)
1289 /* Return CPU flags match bits. */
1292 cpu_flags_match (const insn_template
*t
)
1294 i386_cpu_flags x
= t
->cpu_flags
;
1295 int match
= cpu_flags_check_cpu64 (x
) ? CPU_FLAGS_64BIT_MATCH
: 0;
1297 x
.bitfield
.cpu64
= 0;
1298 x
.bitfield
.cpuno64
= 0;
1300 if (cpu_flags_all_zero (&x
))
1302 /* This instruction is available on all archs. */
1303 match
|= CPU_FLAGS_32BIT_MATCH
;
1307 /* This instruction is available only on some archs. */
1308 i386_cpu_flags cpu
= cpu_arch_flags
;
1310 cpu
.bitfield
.cpu64
= 0;
1311 cpu
.bitfield
.cpuno64
= 0;
1312 cpu
= cpu_flags_and (x
, cpu
);
1313 if (!cpu_flags_all_zero (&cpu
))
1315 if (x
.bitfield
.cpuavx
)
1317 /* We only need to check AES/PCLMUL/SSE2AVX with AVX. */
1318 if (cpu
.bitfield
.cpuavx
)
1320 /* Check SSE2AVX. */
1321 if (!t
->opcode_modifier
.sse2avx
|| sse2avx
)
1323 match
|= (CPU_FLAGS_ARCH_MATCH
1324 | CPU_FLAGS_AVX_MATCH
);
1326 if (!x
.bitfield
.cpuaes
|| cpu
.bitfield
.cpuaes
)
1327 match
|= CPU_FLAGS_AES_MATCH
;
1329 if (!x
.bitfield
.cpupclmul
1330 || cpu
.bitfield
.cpupclmul
)
1331 match
|= CPU_FLAGS_PCLMUL_MATCH
;
1335 match
|= CPU_FLAGS_ARCH_MATCH
;
1338 match
|= CPU_FLAGS_32BIT_MATCH
;
1344 static INLINE i386_operand_type
1345 operand_type_and (i386_operand_type x
, i386_operand_type y
)
1347 switch (ARRAY_SIZE (x
.array
))
1350 x
.array
[2] &= y
.array
[2];
1352 x
.array
[1] &= y
.array
[1];
1354 x
.array
[0] &= y
.array
[0];
1362 static INLINE i386_operand_type
1363 operand_type_or (i386_operand_type x
, i386_operand_type y
)
1365 switch (ARRAY_SIZE (x
.array
))
1368 x
.array
[2] |= y
.array
[2];
1370 x
.array
[1] |= y
.array
[1];
1372 x
.array
[0] |= y
.array
[0];
1380 static INLINE i386_operand_type
1381 operand_type_xor (i386_operand_type x
, i386_operand_type y
)
1383 switch (ARRAY_SIZE (x
.array
))
1386 x
.array
[2] ^= y
.array
[2];
1388 x
.array
[1] ^= y
.array
[1];
1390 x
.array
[0] ^= y
.array
[0];
1398 static const i386_operand_type acc32
= OPERAND_TYPE_ACC32
;
1399 static const i386_operand_type acc64
= OPERAND_TYPE_ACC64
;
1400 static const i386_operand_type control
= OPERAND_TYPE_CONTROL
;
1401 static const i386_operand_type inoutportreg
1402 = OPERAND_TYPE_INOUTPORTREG
;
1403 static const i386_operand_type reg16_inoutportreg
1404 = OPERAND_TYPE_REG16_INOUTPORTREG
;
1405 static const i386_operand_type disp16
= OPERAND_TYPE_DISP16
;
1406 static const i386_operand_type disp32
= OPERAND_TYPE_DISP32
;
1407 static const i386_operand_type disp32s
= OPERAND_TYPE_DISP32S
;
1408 static const i386_operand_type disp16_32
= OPERAND_TYPE_DISP16_32
;
1409 static const i386_operand_type anydisp
1410 = OPERAND_TYPE_ANYDISP
;
1411 static const i386_operand_type regxmm
= OPERAND_TYPE_REGXMM
;
1412 static const i386_operand_type regymm
= OPERAND_TYPE_REGYMM
;
1413 static const i386_operand_type imm8
= OPERAND_TYPE_IMM8
;
1414 static const i386_operand_type imm8s
= OPERAND_TYPE_IMM8S
;
1415 static const i386_operand_type imm16
= OPERAND_TYPE_IMM16
;
1416 static const i386_operand_type imm32
= OPERAND_TYPE_IMM32
;
1417 static const i386_operand_type imm32s
= OPERAND_TYPE_IMM32S
;
1418 static const i386_operand_type imm64
= OPERAND_TYPE_IMM64
;
1419 static const i386_operand_type imm16_32
= OPERAND_TYPE_IMM16_32
;
1420 static const i386_operand_type imm16_32s
= OPERAND_TYPE_IMM16_32S
;
1421 static const i386_operand_type imm16_32_32s
= OPERAND_TYPE_IMM16_32_32S
;
1432 operand_type_check (i386_operand_type t
, enum operand_type c
)
1437 return (t
.bitfield
.reg8
1440 || t
.bitfield
.reg64
);
1443 return (t
.bitfield
.imm8
1447 || t
.bitfield
.imm32s
1448 || t
.bitfield
.imm64
);
1451 return (t
.bitfield
.disp8
1452 || t
.bitfield
.disp16
1453 || t
.bitfield
.disp32
1454 || t
.bitfield
.disp32s
1455 || t
.bitfield
.disp64
);
1458 return (t
.bitfield
.disp8
1459 || t
.bitfield
.disp16
1460 || t
.bitfield
.disp32
1461 || t
.bitfield
.disp32s
1462 || t
.bitfield
.disp64
1463 || t
.bitfield
.baseindex
);
1472 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit on
1473 operand J for instruction template T. */
1476 match_reg_size (const insn_template
*t
, unsigned int j
)
1478 return !((i
.types
[j
].bitfield
.byte
1479 && !t
->operand_types
[j
].bitfield
.byte
)
1480 || (i
.types
[j
].bitfield
.word
1481 && !t
->operand_types
[j
].bitfield
.word
)
1482 || (i
.types
[j
].bitfield
.dword
1483 && !t
->operand_types
[j
].bitfield
.dword
)
1484 || (i
.types
[j
].bitfield
.qword
1485 && !t
->operand_types
[j
].bitfield
.qword
));
1488 /* Return 1 if there is no conflict in any size on operand J for
1489 instruction template T. */
1492 match_mem_size (const insn_template
*t
, unsigned int j
)
1494 return (match_reg_size (t
, j
)
1495 && !((i
.types
[j
].bitfield
.unspecified
1496 && !t
->operand_types
[j
].bitfield
.unspecified
)
1497 || (i
.types
[j
].bitfield
.fword
1498 && !t
->operand_types
[j
].bitfield
.fword
)
1499 || (i
.types
[j
].bitfield
.tbyte
1500 && !t
->operand_types
[j
].bitfield
.tbyte
)
1501 || (i
.types
[j
].bitfield
.xmmword
1502 && !t
->operand_types
[j
].bitfield
.xmmword
)
1503 || (i
.types
[j
].bitfield
.ymmword
1504 && !t
->operand_types
[j
].bitfield
.ymmword
)));
1507 /* Return 1 if there is no size conflict on any operands for
1508 instruction template T. */
1511 operand_size_match (const insn_template
*t
)
1516 /* Don't check jump instructions. */
1517 if (t
->opcode_modifier
.jump
1518 || t
->opcode_modifier
.jumpbyte
1519 || t
->opcode_modifier
.jumpdword
1520 || t
->opcode_modifier
.jumpintersegment
)
1523 /* Check memory and accumulator operand size. */
1524 for (j
= 0; j
< i
.operands
; j
++)
1526 if (t
->operand_types
[j
].bitfield
.anysize
)
1529 if (t
->operand_types
[j
].bitfield
.acc
&& !match_reg_size (t
, j
))
1535 if (i
.types
[j
].bitfield
.mem
&& !match_mem_size (t
, j
))
1543 || (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
))
1546 /* Check reverse. */
1547 gas_assert (i
.operands
== 2);
1550 for (j
= 0; j
< 2; j
++)
1552 if (t
->operand_types
[j
].bitfield
.acc
1553 && !match_reg_size (t
, j
? 0 : 1))
1559 if (i
.types
[j
].bitfield
.mem
1560 && !match_mem_size (t
, j
? 0 : 1))
1571 operand_type_match (i386_operand_type overlap
,
1572 i386_operand_type given
)
1574 i386_operand_type temp
= overlap
;
1576 temp
.bitfield
.jumpabsolute
= 0;
1577 temp
.bitfield
.unspecified
= 0;
1578 temp
.bitfield
.byte
= 0;
1579 temp
.bitfield
.word
= 0;
1580 temp
.bitfield
.dword
= 0;
1581 temp
.bitfield
.fword
= 0;
1582 temp
.bitfield
.qword
= 0;
1583 temp
.bitfield
.tbyte
= 0;
1584 temp
.bitfield
.xmmword
= 0;
1585 temp
.bitfield
.ymmword
= 0;
1586 if (operand_type_all_zero (&temp
))
1589 return (given
.bitfield
.baseindex
== overlap
.bitfield
.baseindex
1590 && given
.bitfield
.jumpabsolute
== overlap
.bitfield
.jumpabsolute
);
1593 /* If given types g0 and g1 are registers they must be of the same type
1594 unless the expected operand type register overlap is null.
1595 Note that Acc in a template matches every size of reg. */
1598 operand_type_register_match (i386_operand_type m0
,
1599 i386_operand_type g0
,
1600 i386_operand_type t0
,
1601 i386_operand_type m1
,
1602 i386_operand_type g1
,
1603 i386_operand_type t1
)
1605 if (!operand_type_check (g0
, reg
))
1608 if (!operand_type_check (g1
, reg
))
1611 if (g0
.bitfield
.reg8
== g1
.bitfield
.reg8
1612 && g0
.bitfield
.reg16
== g1
.bitfield
.reg16
1613 && g0
.bitfield
.reg32
== g1
.bitfield
.reg32
1614 && g0
.bitfield
.reg64
== g1
.bitfield
.reg64
)
1617 if (m0
.bitfield
.acc
)
1619 t0
.bitfield
.reg8
= 1;
1620 t0
.bitfield
.reg16
= 1;
1621 t0
.bitfield
.reg32
= 1;
1622 t0
.bitfield
.reg64
= 1;
1625 if (m1
.bitfield
.acc
)
1627 t1
.bitfield
.reg8
= 1;
1628 t1
.bitfield
.reg16
= 1;
1629 t1
.bitfield
.reg32
= 1;
1630 t1
.bitfield
.reg64
= 1;
1633 return (!(t0
.bitfield
.reg8
& t1
.bitfield
.reg8
)
1634 && !(t0
.bitfield
.reg16
& t1
.bitfield
.reg16
)
1635 && !(t0
.bitfield
.reg32
& t1
.bitfield
.reg32
)
1636 && !(t0
.bitfield
.reg64
& t1
.bitfield
.reg64
));
1639 static INLINE
unsigned int
1640 mode_from_disp_size (i386_operand_type t
)
1642 if (t
.bitfield
.disp8
)
1644 else if (t
.bitfield
.disp16
1645 || t
.bitfield
.disp32
1646 || t
.bitfield
.disp32s
)
1653 fits_in_signed_byte (offsetT num
)
1655 return (num
>= -128) && (num
<= 127);
1659 fits_in_unsigned_byte (offsetT num
)
1661 return (num
& 0xff) == num
;
1665 fits_in_unsigned_word (offsetT num
)
1667 return (num
& 0xffff) == num
;
1671 fits_in_signed_word (offsetT num
)
1673 return (-32768 <= num
) && (num
<= 32767);
1677 fits_in_signed_long (offsetT num ATTRIBUTE_UNUSED
)
1682 return (!(((offsetT
) -1 << 31) & num
)
1683 || (((offsetT
) -1 << 31) & num
) == ((offsetT
) -1 << 31));
1685 } /* fits_in_signed_long() */
1688 fits_in_unsigned_long (offsetT num ATTRIBUTE_UNUSED
)
1693 return (num
& (((offsetT
) 2 << 31) - 1)) == num
;
1695 } /* fits_in_unsigned_long() */
1697 static i386_operand_type
1698 smallest_imm_type (offsetT num
)
1700 i386_operand_type t
;
1702 operand_type_set (&t
, 0);
1703 t
.bitfield
.imm64
= 1;
1705 if (cpu_arch_tune
!= PROCESSOR_I486
&& num
== 1)
1707 /* This code is disabled on the 486 because all the Imm1 forms
1708 in the opcode table are slower on the i486. They're the
1709 versions with the implicitly specified single-position
1710 displacement, which has another syntax if you really want to
1712 t
.bitfield
.imm1
= 1;
1713 t
.bitfield
.imm8
= 1;
1714 t
.bitfield
.imm8s
= 1;
1715 t
.bitfield
.imm16
= 1;
1716 t
.bitfield
.imm32
= 1;
1717 t
.bitfield
.imm32s
= 1;
1719 else if (fits_in_signed_byte (num
))
1721 t
.bitfield
.imm8
= 1;
1722 t
.bitfield
.imm8s
= 1;
1723 t
.bitfield
.imm16
= 1;
1724 t
.bitfield
.imm32
= 1;
1725 t
.bitfield
.imm32s
= 1;
1727 else if (fits_in_unsigned_byte (num
))
1729 t
.bitfield
.imm8
= 1;
1730 t
.bitfield
.imm16
= 1;
1731 t
.bitfield
.imm32
= 1;
1732 t
.bitfield
.imm32s
= 1;
1734 else if (fits_in_signed_word (num
) || fits_in_unsigned_word (num
))
1736 t
.bitfield
.imm16
= 1;
1737 t
.bitfield
.imm32
= 1;
1738 t
.bitfield
.imm32s
= 1;
1740 else if (fits_in_signed_long (num
))
1742 t
.bitfield
.imm32
= 1;
1743 t
.bitfield
.imm32s
= 1;
1745 else if (fits_in_unsigned_long (num
))
1746 t
.bitfield
.imm32
= 1;
1752 offset_in_range (offsetT val
, int size
)
1758 case 1: mask
= ((addressT
) 1 << 8) - 1; break;
1759 case 2: mask
= ((addressT
) 1 << 16) - 1; break;
1760 case 4: mask
= ((addressT
) 2 << 31) - 1; break;
1762 case 8: mask
= ((addressT
) 2 << 63) - 1; break;
1768 /* If BFD64, sign extend val for 32bit address mode. */
1769 if (flag_code
!= CODE_64BIT
1770 || i
.prefix
[ADDR_PREFIX
])
1771 if ((val
& ~(((addressT
) 2 << 31) - 1)) == 0)
1772 val
= (val
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
1775 if ((val
& ~mask
) != 0 && (val
& ~mask
) != ~mask
)
1777 char buf1
[40], buf2
[40];
1779 sprint_value (buf1
, val
);
1780 sprint_value (buf2
, val
& mask
);
1781 as_warn (_("%s shortened to %s"), buf1
, buf2
);
1786 /* Returns 0 if attempting to add a prefix where one from the same
1787 class already exists, 1 if non rep/repne added, 2 if rep/repne
1790 add_prefix (unsigned int prefix
)
1795 if (prefix
>= REX_OPCODE
&& prefix
< REX_OPCODE
+ 16
1796 && flag_code
== CODE_64BIT
)
1798 if ((i
.prefix
[REX_PREFIX
] & prefix
& REX_W
)
1799 || ((i
.prefix
[REX_PREFIX
] & (REX_R
| REX_X
| REX_B
))
1800 && (prefix
& (REX_R
| REX_X
| REX_B
))))
1811 case CS_PREFIX_OPCODE
:
1812 case DS_PREFIX_OPCODE
:
1813 case ES_PREFIX_OPCODE
:
1814 case FS_PREFIX_OPCODE
:
1815 case GS_PREFIX_OPCODE
:
1816 case SS_PREFIX_OPCODE
:
1820 case REPNE_PREFIX_OPCODE
:
1821 case REPE_PREFIX_OPCODE
:
1824 case LOCK_PREFIX_OPCODE
:
1832 case ADDR_PREFIX_OPCODE
:
1836 case DATA_PREFIX_OPCODE
:
1840 if (i
.prefix
[q
] != 0)
1848 i
.prefix
[q
] |= prefix
;
1851 as_bad (_("same type of prefix used twice"));
1857 set_code_flag (int value
)
1859 flag_code
= (enum flag_code
) value
;
1860 if (flag_code
== CODE_64BIT
)
1862 cpu_arch_flags
.bitfield
.cpu64
= 1;
1863 cpu_arch_flags
.bitfield
.cpuno64
= 0;
1867 cpu_arch_flags
.bitfield
.cpu64
= 0;
1868 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1870 if (value
== CODE_64BIT
&& !cpu_arch_flags
.bitfield
.cpulm
)
1872 as_bad (_("64bit mode not supported on this CPU."));
1874 if (value
== CODE_32BIT
&& !cpu_arch_flags
.bitfield
.cpui386
)
1876 as_bad (_("32bit mode not supported on this CPU."));
1878 stackop_size
= '\0';
1882 set_16bit_gcc_code_flag (int new_code_flag
)
1884 flag_code
= (enum flag_code
) new_code_flag
;
1885 if (flag_code
!= CODE_16BIT
)
1887 cpu_arch_flags
.bitfield
.cpu64
= 0;
1888 cpu_arch_flags
.bitfield
.cpuno64
= 1;
1889 stackop_size
= LONG_MNEM_SUFFIX
;
1893 set_intel_syntax (int syntax_flag
)
1895 /* Find out if register prefixing is specified. */
1896 int ask_naked_reg
= 0;
1899 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1901 char *string
= input_line_pointer
;
1902 int e
= get_symbol_end ();
1904 if (strcmp (string
, "prefix") == 0)
1906 else if (strcmp (string
, "noprefix") == 0)
1909 as_bad (_("bad argument to syntax directive."));
1910 *input_line_pointer
= e
;
1912 demand_empty_rest_of_line ();
1914 intel_syntax
= syntax_flag
;
1916 if (ask_naked_reg
== 0)
1917 allow_naked_reg
= (intel_syntax
1918 && (bfd_get_symbol_leading_char (stdoutput
) != '\0'));
1920 allow_naked_reg
= (ask_naked_reg
< 0);
1922 expr_set_rank (O_full_ptr
, syntax_flag
? 10 : 0);
1924 identifier_chars
['%'] = intel_syntax
&& allow_naked_reg
? '%' : 0;
1925 identifier_chars
['$'] = intel_syntax
? '$' : 0;
1926 register_prefix
= allow_naked_reg
? "" : "%";
1930 set_intel_mnemonic (int mnemonic_flag
)
1932 intel_mnemonic
= mnemonic_flag
;
1936 set_allow_index_reg (int flag
)
1938 allow_index_reg
= flag
;
1942 set_sse_check (int dummy ATTRIBUTE_UNUSED
)
1946 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
1948 char *string
= input_line_pointer
;
1949 int e
= get_symbol_end ();
1951 if (strcmp (string
, "none") == 0)
1952 sse_check
= sse_check_none
;
1953 else if (strcmp (string
, "warning") == 0)
1954 sse_check
= sse_check_warning
;
1955 else if (strcmp (string
, "error") == 0)
1956 sse_check
= sse_check_error
;
1958 as_bad (_("bad argument to sse_check directive."));
1959 *input_line_pointer
= e
;
1962 as_bad (_("missing argument for sse_check directive"));
1964 demand_empty_rest_of_line ();
1968 check_cpu_arch_compatible (const char *name ATTRIBUTE_UNUSED
,
1969 i386_cpu_flags new_flag ATTRIBUTE_UNUSED
)
1971 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1972 static const char *arch
;
1974 /* Intel LIOM is only supported on ELF. */
1980 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
1981 use default_arch. */
1982 arch
= cpu_arch_name
;
1984 arch
= default_arch
;
1987 /* If we are targeting Intel L1OM, we must enable it. */
1988 if (get_elf_backend_data (stdoutput
)->elf_machine_code
!= EM_L1OM
1989 || new_flag
.bitfield
.cpul1om
)
1992 as_bad (_("`%s' is not supported on `%s'"), name
, arch
);
1997 set_cpu_arch (int dummy ATTRIBUTE_UNUSED
)
2001 if (!is_end_of_line
[(unsigned char) *input_line_pointer
])
2003 char *string
= input_line_pointer
;
2004 int e
= get_symbol_end ();
2006 i386_cpu_flags flags
;
2008 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
2010 if (strcmp (string
, cpu_arch
[i
].name
) == 0)
2012 check_cpu_arch_compatible (string
, cpu_arch
[i
].flags
);
2016 cpu_arch_name
= cpu_arch
[i
].name
;
2017 cpu_sub_arch_name
= NULL
;
2018 cpu_arch_flags
= cpu_arch
[i
].flags
;
2019 if (flag_code
== CODE_64BIT
)
2021 cpu_arch_flags
.bitfield
.cpu64
= 1;
2022 cpu_arch_flags
.bitfield
.cpuno64
= 0;
2026 cpu_arch_flags
.bitfield
.cpu64
= 0;
2027 cpu_arch_flags
.bitfield
.cpuno64
= 1;
2029 cpu_arch_isa
= cpu_arch
[i
].type
;
2030 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
2031 if (!cpu_arch_tune_set
)
2033 cpu_arch_tune
= cpu_arch_isa
;
2034 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
2039 if (strncmp (string
+ 1, "no", 2))
2040 flags
= cpu_flags_or (cpu_arch_flags
,
2043 flags
= cpu_flags_and_not (cpu_arch_flags
,
2045 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
2047 if (cpu_sub_arch_name
)
2049 char *name
= cpu_sub_arch_name
;
2050 cpu_sub_arch_name
= concat (name
,
2052 (const char *) NULL
);
2056 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
2057 cpu_arch_flags
= flags
;
2059 *input_line_pointer
= e
;
2060 demand_empty_rest_of_line ();
2064 if (i
>= ARRAY_SIZE (cpu_arch
))
2065 as_bad (_("no such architecture: `%s'"), string
);
2067 *input_line_pointer
= e
;
2070 as_bad (_("missing cpu architecture"));
2072 no_cond_jump_promotion
= 0;
2073 if (*input_line_pointer
== ','
2074 && !is_end_of_line
[(unsigned char) input_line_pointer
[1]])
2076 char *string
= ++input_line_pointer
;
2077 int e
= get_symbol_end ();
2079 if (strcmp (string
, "nojumps") == 0)
2080 no_cond_jump_promotion
= 1;
2081 else if (strcmp (string
, "jumps") == 0)
2084 as_bad (_("no such architecture modifier: `%s'"), string
);
2086 *input_line_pointer
= e
;
2089 demand_empty_rest_of_line ();
2092 enum bfd_architecture
2095 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2097 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
2098 || flag_code
!= CODE_64BIT
)
2099 as_fatal (_("Intel L1OM is 64bit ELF only"));
2100 return bfd_arch_l1om
;
2103 return bfd_arch_i386
;
2109 if (!strcmp (default_arch
, "x86_64"))
2111 if (cpu_arch_isa
== PROCESSOR_L1OM
)
2113 if (OUTPUT_FLAVOR
!= bfd_target_elf_flavour
)
2114 as_fatal (_("Intel L1OM is 64bit ELF only"));
2115 return bfd_mach_l1om
;
2118 return bfd_mach_x86_64
;
2120 else if (!strcmp (default_arch
, "i386"))
2121 return bfd_mach_i386_i386
;
2123 as_fatal (_("Unknown architecture"));
2129 const char *hash_err
;
2131 /* Initialize op_hash hash table. */
2132 op_hash
= hash_new ();
2135 const insn_template
*optab
;
2136 templates
*core_optab
;
2138 /* Setup for loop. */
2140 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2141 core_optab
->start
= optab
;
2146 if (optab
->name
== NULL
2147 || strcmp (optab
->name
, (optab
- 1)->name
) != 0)
2149 /* different name --> ship out current template list;
2150 add to hash table; & begin anew. */
2151 core_optab
->end
= optab
;
2152 hash_err
= hash_insert (op_hash
,
2154 (void *) core_optab
);
2157 as_fatal (_("Internal Error: Can't hash %s: %s"),
2161 if (optab
->name
== NULL
)
2163 core_optab
= (templates
*) xmalloc (sizeof (templates
));
2164 core_optab
->start
= optab
;
2169 /* Initialize reg_hash hash table. */
2170 reg_hash
= hash_new ();
2172 const reg_entry
*regtab
;
2173 unsigned int regtab_size
= i386_regtab_size
;
2175 for (regtab
= i386_regtab
; regtab_size
--; regtab
++)
2177 hash_err
= hash_insert (reg_hash
, regtab
->reg_name
, (void *) regtab
);
2179 as_fatal (_("Internal Error: Can't hash %s: %s"),
2185 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
2190 for (c
= 0; c
< 256; c
++)
2195 mnemonic_chars
[c
] = c
;
2196 register_chars
[c
] = c
;
2197 operand_chars
[c
] = c
;
2199 else if (ISLOWER (c
))
2201 mnemonic_chars
[c
] = c
;
2202 register_chars
[c
] = c
;
2203 operand_chars
[c
] = c
;
2205 else if (ISUPPER (c
))
2207 mnemonic_chars
[c
] = TOLOWER (c
);
2208 register_chars
[c
] = mnemonic_chars
[c
];
2209 operand_chars
[c
] = c
;
2212 if (ISALPHA (c
) || ISDIGIT (c
))
2213 identifier_chars
[c
] = c
;
2216 identifier_chars
[c
] = c
;
2217 operand_chars
[c
] = c
;
2222 identifier_chars
['@'] = '@';
2225 identifier_chars
['?'] = '?';
2226 operand_chars
['?'] = '?';
2228 digit_chars
['-'] = '-';
2229 mnemonic_chars
['_'] = '_';
2230 mnemonic_chars
['-'] = '-';
2231 mnemonic_chars
['.'] = '.';
2232 identifier_chars
['_'] = '_';
2233 identifier_chars
['.'] = '.';
2235 for (p
= operand_special_chars
; *p
!= '\0'; p
++)
2236 operand_chars
[(unsigned char) *p
] = *p
;
2239 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2242 record_alignment (text_section
, 2);
2243 record_alignment (data_section
, 2);
2244 record_alignment (bss_section
, 2);
2248 if (flag_code
== CODE_64BIT
)
2250 x86_dwarf2_return_column
= 16;
2251 x86_cie_data_alignment
= -8;
2255 x86_dwarf2_return_column
= 8;
2256 x86_cie_data_alignment
= -4;
2261 i386_print_statistics (FILE *file
)
2263 hash_print_statistics (file
, "i386 opcode", op_hash
);
2264 hash_print_statistics (file
, "i386 register", reg_hash
);
2269 /* Debugging routines for md_assemble. */
2270 static void pte (insn_template
*);
2271 static void pt (i386_operand_type
);
2272 static void pe (expressionS
*);
2273 static void ps (symbolS
*);
2276 pi (char *line
, i386_insn
*x
)
2280 fprintf (stdout
, "%s: template ", line
);
2282 fprintf (stdout
, " address: base %s index %s scale %x\n",
2283 x
->base_reg
? x
->base_reg
->reg_name
: "none",
2284 x
->index_reg
? x
->index_reg
->reg_name
: "none",
2285 x
->log2_scale_factor
);
2286 fprintf (stdout
, " modrm: mode %x reg %x reg/mem %x\n",
2287 x
->rm
.mode
, x
->rm
.reg
, x
->rm
.regmem
);
2288 fprintf (stdout
, " sib: base %x index %x scale %x\n",
2289 x
->sib
.base
, x
->sib
.index
, x
->sib
.scale
);
2290 fprintf (stdout
, " rex: 64bit %x extX %x extY %x extZ %x\n",
2291 (x
->rex
& REX_W
) != 0,
2292 (x
->rex
& REX_R
) != 0,
2293 (x
->rex
& REX_X
) != 0,
2294 (x
->rex
& REX_B
) != 0);
2295 for (i
= 0; i
< x
->operands
; i
++)
2297 fprintf (stdout
, " #%d: ", i
+ 1);
2299 fprintf (stdout
, "\n");
2300 if (x
->types
[i
].bitfield
.reg8
2301 || x
->types
[i
].bitfield
.reg16
2302 || x
->types
[i
].bitfield
.reg32
2303 || x
->types
[i
].bitfield
.reg64
2304 || x
->types
[i
].bitfield
.regmmx
2305 || x
->types
[i
].bitfield
.regxmm
2306 || x
->types
[i
].bitfield
.regymm
2307 || x
->types
[i
].bitfield
.sreg2
2308 || x
->types
[i
].bitfield
.sreg3
2309 || x
->types
[i
].bitfield
.control
2310 || x
->types
[i
].bitfield
.debug
2311 || x
->types
[i
].bitfield
.test
)
2312 fprintf (stdout
, "%s\n", x
->op
[i
].regs
->reg_name
);
2313 if (operand_type_check (x
->types
[i
], imm
))
2315 if (operand_type_check (x
->types
[i
], disp
))
2316 pe (x
->op
[i
].disps
);
2321 pte (insn_template
*t
)
2324 fprintf (stdout
, " %d operands ", t
->operands
);
2325 fprintf (stdout
, "opcode %x ", t
->base_opcode
);
2326 if (t
->extension_opcode
!= None
)
2327 fprintf (stdout
, "ext %x ", t
->extension_opcode
);
2328 if (t
->opcode_modifier
.d
)
2329 fprintf (stdout
, "D");
2330 if (t
->opcode_modifier
.w
)
2331 fprintf (stdout
, "W");
2332 fprintf (stdout
, "\n");
2333 for (i
= 0; i
< t
->operands
; i
++)
2335 fprintf (stdout
, " #%d type ", i
+ 1);
2336 pt (t
->operand_types
[i
]);
2337 fprintf (stdout
, "\n");
2344 fprintf (stdout
, " operation %d\n", e
->X_op
);
2345 fprintf (stdout
, " add_number %ld (%lx)\n",
2346 (long) e
->X_add_number
, (long) e
->X_add_number
);
2347 if (e
->X_add_symbol
)
2349 fprintf (stdout
, " add_symbol ");
2350 ps (e
->X_add_symbol
);
2351 fprintf (stdout
, "\n");
2355 fprintf (stdout
, " op_symbol ");
2356 ps (e
->X_op_symbol
);
2357 fprintf (stdout
, "\n");
2364 fprintf (stdout
, "%s type %s%s",
2366 S_IS_EXTERNAL (s
) ? "EXTERNAL " : "",
2367 segment_name (S_GET_SEGMENT (s
)));
2370 static struct type_name
2372 i386_operand_type mask
;
2375 const type_names
[] =
2377 { OPERAND_TYPE_REG8
, "r8" },
2378 { OPERAND_TYPE_REG16
, "r16" },
2379 { OPERAND_TYPE_REG32
, "r32" },
2380 { OPERAND_TYPE_REG64
, "r64" },
2381 { OPERAND_TYPE_IMM8
, "i8" },
2382 { OPERAND_TYPE_IMM8
, "i8s" },
2383 { OPERAND_TYPE_IMM16
, "i16" },
2384 { OPERAND_TYPE_IMM32
, "i32" },
2385 { OPERAND_TYPE_IMM32S
, "i32s" },
2386 { OPERAND_TYPE_IMM64
, "i64" },
2387 { OPERAND_TYPE_IMM1
, "i1" },
2388 { OPERAND_TYPE_BASEINDEX
, "BaseIndex" },
2389 { OPERAND_TYPE_DISP8
, "d8" },
2390 { OPERAND_TYPE_DISP16
, "d16" },
2391 { OPERAND_TYPE_DISP32
, "d32" },
2392 { OPERAND_TYPE_DISP32S
, "d32s" },
2393 { OPERAND_TYPE_DISP64
, "d64" },
2394 { OPERAND_TYPE_INOUTPORTREG
, "InOutPortReg" },
2395 { OPERAND_TYPE_SHIFTCOUNT
, "ShiftCount" },
2396 { OPERAND_TYPE_CONTROL
, "control reg" },
2397 { OPERAND_TYPE_TEST
, "test reg" },
2398 { OPERAND_TYPE_DEBUG
, "debug reg" },
2399 { OPERAND_TYPE_FLOATREG
, "FReg" },
2400 { OPERAND_TYPE_FLOATACC
, "FAcc" },
2401 { OPERAND_TYPE_SREG2
, "SReg2" },
2402 { OPERAND_TYPE_SREG3
, "SReg3" },
2403 { OPERAND_TYPE_ACC
, "Acc" },
2404 { OPERAND_TYPE_JUMPABSOLUTE
, "Jump Absolute" },
2405 { OPERAND_TYPE_REGMMX
, "rMMX" },
2406 { OPERAND_TYPE_REGXMM
, "rXMM" },
2407 { OPERAND_TYPE_REGYMM
, "rYMM" },
2408 { OPERAND_TYPE_ESSEG
, "es" },
2412 pt (i386_operand_type t
)
2415 i386_operand_type a
;
2417 for (j
= 0; j
< ARRAY_SIZE (type_names
); j
++)
2419 a
= operand_type_and (t
, type_names
[j
].mask
);
2420 if (!operand_type_all_zero (&a
))
2421 fprintf (stdout
, "%s, ", type_names
[j
].name
);
2426 #endif /* DEBUG386 */
2428 static bfd_reloc_code_real_type
2429 reloc (unsigned int size
,
2432 bfd_reloc_code_real_type other
)
2434 if (other
!= NO_RELOC
)
2436 reloc_howto_type
*reloc
;
2441 case BFD_RELOC_X86_64_GOT32
:
2442 return BFD_RELOC_X86_64_GOT64
;
2444 case BFD_RELOC_X86_64_PLTOFF64
:
2445 return BFD_RELOC_X86_64_PLTOFF64
;
2447 case BFD_RELOC_X86_64_GOTPC32
:
2448 other
= BFD_RELOC_X86_64_GOTPC64
;
2450 case BFD_RELOC_X86_64_GOTPCREL
:
2451 other
= BFD_RELOC_X86_64_GOTPCREL64
;
2453 case BFD_RELOC_X86_64_TPOFF32
:
2454 other
= BFD_RELOC_X86_64_TPOFF64
;
2456 case BFD_RELOC_X86_64_DTPOFF32
:
2457 other
= BFD_RELOC_X86_64_DTPOFF64
;
2463 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
2464 if (size
== 4 && flag_code
!= CODE_64BIT
)
2467 reloc
= bfd_reloc_type_lookup (stdoutput
, other
);
2469 as_bad (_("unknown relocation (%u)"), other
);
2470 else if (size
!= bfd_get_reloc_size (reloc
))
2471 as_bad (_("%u-byte relocation cannot be applied to %u-byte field"),
2472 bfd_get_reloc_size (reloc
),
2474 else if (pcrel
&& !reloc
->pc_relative
)
2475 as_bad (_("non-pc-relative relocation for pc-relative field"));
2476 else if ((reloc
->complain_on_overflow
== complain_overflow_signed
2478 || (reloc
->complain_on_overflow
== complain_overflow_unsigned
2480 as_bad (_("relocated field and relocation type differ in signedness"));
2489 as_bad (_("there are no unsigned pc-relative relocations"));
2492 case 1: return BFD_RELOC_8_PCREL
;
2493 case 2: return BFD_RELOC_16_PCREL
;
2494 case 4: return BFD_RELOC_32_PCREL
;
2495 case 8: return BFD_RELOC_64_PCREL
;
2497 as_bad (_("cannot do %u byte pc-relative relocation"), size
);
2504 case 4: return BFD_RELOC_X86_64_32S
;
2509 case 1: return BFD_RELOC_8
;
2510 case 2: return BFD_RELOC_16
;
2511 case 4: return BFD_RELOC_32
;
2512 case 8: return BFD_RELOC_64
;
2514 as_bad (_("cannot do %s %u byte relocation"),
2515 sign
> 0 ? "signed" : "unsigned", size
);
2521 /* Here we decide which fixups can be adjusted to make them relative to
2522 the beginning of the section instead of the symbol. Basically we need
2523 to make sure that the dynamic relocations are done correctly, so in
2524 some cases we force the original symbol to be used. */
2527 tc_i386_fix_adjustable (fixS
*fixP ATTRIBUTE_UNUSED
)
2529 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
2533 /* Don't adjust pc-relative references to merge sections in 64-bit
2535 if (use_rela_relocations
2536 && (S_GET_SEGMENT (fixP
->fx_addsy
)->flags
& SEC_MERGE
) != 0
2540 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
2541 and changed later by validate_fix. */
2542 if (GOT_symbol
&& fixP
->fx_subsy
== GOT_symbol
2543 && fixP
->fx_r_type
== BFD_RELOC_32_PCREL
)
2546 /* adjust_reloc_syms doesn't know about the GOT. */
2547 if (fixP
->fx_r_type
== BFD_RELOC_386_GOTOFF
2548 || fixP
->fx_r_type
== BFD_RELOC_386_PLT32
2549 || fixP
->fx_r_type
== BFD_RELOC_386_GOT32
2550 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GD
2551 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDM
2552 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LDO_32
2553 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE_32
2554 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_IE
2555 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTIE
2556 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE_32
2557 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_LE
2558 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_GOTDESC
2559 || fixP
->fx_r_type
== BFD_RELOC_386_TLS_DESC_CALL
2560 || fixP
->fx_r_type
== BFD_RELOC_X86_64_PLT32
2561 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOT32
2562 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPCREL
2563 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSGD
2564 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSLD
2565 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF32
2566 || fixP
->fx_r_type
== BFD_RELOC_X86_64_DTPOFF64
2567 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTTPOFF
2568 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF32
2569 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TPOFF64
2570 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTOFF64
2571 || fixP
->fx_r_type
== BFD_RELOC_X86_64_GOTPC32_TLSDESC
2572 || fixP
->fx_r_type
== BFD_RELOC_X86_64_TLSDESC_CALL
2573 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_INHERIT
2574 || fixP
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
2581 intel_float_operand (const char *mnemonic
)
2583 /* Note that the value returned is meaningful only for opcodes with (memory)
2584 operands, hence the code here is free to improperly handle opcodes that
2585 have no operands (for better performance and smaller code). */
2587 if (mnemonic
[0] != 'f')
2588 return 0; /* non-math */
2590 switch (mnemonic
[1])
2592 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
2593 the fs segment override prefix not currently handled because no
2594 call path can make opcodes without operands get here */
2596 return 2 /* integer op */;
2598 if (mnemonic
[2] == 'd' && (mnemonic
[3] == 'c' || mnemonic
[3] == 'e'))
2599 return 3; /* fldcw/fldenv */
2602 if (mnemonic
[2] != 'o' /* fnop */)
2603 return 3; /* non-waiting control op */
2606 if (mnemonic
[2] == 's')
2607 return 3; /* frstor/frstpm */
2610 if (mnemonic
[2] == 'a')
2611 return 3; /* fsave */
2612 if (mnemonic
[2] == 't')
2614 switch (mnemonic
[3])
2616 case 'c': /* fstcw */
2617 case 'd': /* fstdw */
2618 case 'e': /* fstenv */
2619 case 's': /* fsts[gw] */
2625 if (mnemonic
[2] == 'r' || mnemonic
[2] == 's')
2626 return 0; /* fxsave/fxrstor are not really math ops */
2633 /* Build the VEX prefix. */
2636 build_vex_prefix (const insn_template
*t
)
2638 unsigned int register_specifier
;
2639 unsigned int implied_prefix
;
2640 unsigned int vector_length
;
2642 /* Check register specifier. */
2643 if (i
.vex
.register_specifier
)
2645 register_specifier
= i
.vex
.register_specifier
->reg_num
;
2646 if ((i
.vex
.register_specifier
->reg_flags
& RegRex
))
2647 register_specifier
+= 8;
2648 register_specifier
= ~register_specifier
& 0xf;
2651 register_specifier
= 0xf;
2653 /* Use 2-byte VEX prefix by swappping destination and source
2656 && i
.operands
== i
.reg_operands
2657 && i
.tm
.opcode_modifier
.vex0f
2658 && i
.tm
.opcode_modifier
.s
2661 unsigned int xchg
= i
.operands
- 1;
2662 union i386_op temp_op
;
2663 i386_operand_type temp_type
;
2665 temp_type
= i
.types
[xchg
];
2666 i
.types
[xchg
] = i
.types
[0];
2667 i
.types
[0] = temp_type
;
2668 temp_op
= i
.op
[xchg
];
2669 i
.op
[xchg
] = i
.op
[0];
2672 gas_assert (i
.rm
.mode
== 3);
2676 i
.rm
.regmem
= i
.rm
.reg
;
2679 /* Use the next insn. */
2683 vector_length
= i
.tm
.opcode_modifier
.vex
== 2 ? 1 : 0;
2685 switch ((i
.tm
.base_opcode
>> 8) & 0xff)
2690 case DATA_PREFIX_OPCODE
:
2693 case REPE_PREFIX_OPCODE
:
2696 case REPNE_PREFIX_OPCODE
:
2703 /* Use 2-byte VEX prefix if possible. */
2704 if (i
.tm
.opcode_modifier
.vex0f
2705 && (i
.rex
& (REX_W
| REX_X
| REX_B
)) == 0)
2707 /* 2-byte VEX prefix. */
2711 i
.vex
.bytes
[0] = 0xc5;
2713 /* Check the REX.R bit. */
2714 r
= (i
.rex
& REX_R
) ? 0 : 1;
2715 i
.vex
.bytes
[1] = (r
<< 7
2716 | register_specifier
<< 3
2717 | vector_length
<< 2
2722 /* 3-byte VEX prefix. */
2726 i
.vex
.bytes
[0] = 0xc4;
2728 if (i
.tm
.opcode_modifier
.vex0f
)
2730 else if (i
.tm
.opcode_modifier
.vex0f38
)
2732 else if (i
.tm
.opcode_modifier
.vex0f3a
)
2734 else if (i
.tm
.opcode_modifier
.xop09
)
2737 i
.vex
.bytes
[0] = 0x8f;
2739 else if (i
.tm
.opcode_modifier
.xop0a
)
2742 i
.vex
.bytes
[0] = 0x8f;
2747 /* The high 3 bits of the second VEX byte are 1's compliment
2748 of RXB bits from REX. */
2749 i
.vex
.bytes
[1] = (~i
.rex
& 0x7) << 5 | m
;
2751 /* Check the REX.W bit. */
2752 w
= (i
.rex
& REX_W
) ? 1 : 0;
2753 if (i
.tm
.opcode_modifier
.vexw0
|| i
.tm
.opcode_modifier
.vexw1
)
2758 if (i
.tm
.opcode_modifier
.vexw1
)
2762 i
.vex
.bytes
[2] = (w
<< 7
2763 | register_specifier
<< 3
2764 | vector_length
<< 2
2770 process_immext (void)
2774 if (i
.tm
.cpu_flags
.bitfield
.cpusse3
&& i
.operands
> 0)
2776 /* SSE3 Instructions have the fixed operands with an opcode
2777 suffix which is coded in the same place as an 8-bit immediate
2778 field would be. Here we check those operands and remove them
2782 for (x
= 0; x
< i
.operands
; x
++)
2783 if (i
.op
[x
].regs
->reg_num
!= x
)
2784 as_bad (_("can't use register '%s%s' as operand %d in '%s'."),
2785 register_prefix
, i
.op
[x
].regs
->reg_name
, x
+ 1,
2791 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
2792 which is coded in the same place as an 8-bit immediate field
2793 would be. Here we fake an 8-bit immediate operand from the
2794 opcode suffix stored in tm.extension_opcode.
2796 AVX instructions also use this encoding, for some of
2797 3 argument instructions. */
2799 gas_assert (i
.imm_operands
== 0
2801 || (i
.tm
.opcode_modifier
.vex
2802 && i
.operands
<= 4)));
2804 exp
= &im_expressions
[i
.imm_operands
++];
2805 i
.op
[i
.operands
].imms
= exp
;
2806 i
.types
[i
.operands
] = imm8
;
2808 exp
->X_op
= O_constant
;
2809 exp
->X_add_number
= i
.tm
.extension_opcode
;
2810 i
.tm
.extension_opcode
= None
;
2813 /* This is the guts of the machine-dependent assembler. LINE points to a
2814 machine dependent instruction. This function is supposed to emit
2815 the frags/bytes it assembles to. */
2818 md_assemble (char *line
)
2821 char mnemonic
[MAX_MNEM_SIZE
];
2822 const insn_template
*t
;
2824 /* Initialize globals. */
2825 memset (&i
, '\0', sizeof (i
));
2826 for (j
= 0; j
< MAX_OPERANDS
; j
++)
2827 i
.reloc
[j
] = NO_RELOC
;
2828 memset (disp_expressions
, '\0', sizeof (disp_expressions
));
2829 memset (im_expressions
, '\0', sizeof (im_expressions
));
2830 save_stack_p
= save_stack
;
2832 /* First parse an instruction mnemonic & call i386_operand for the operands.
2833 We assume that the scrubber has arranged it so that line[0] is the valid
2834 start of a (possibly prefixed) mnemonic. */
2836 line
= parse_insn (line
, mnemonic
);
2840 line
= parse_operands (line
, mnemonic
);
2845 /* Now we've parsed the mnemonic into a set of templates, and have the
2846 operands at hand. */
2848 /* All intel opcodes have reversed operands except for "bound" and
2849 "enter". We also don't reverse intersegment "jmp" and "call"
2850 instructions with 2 immediate operands so that the immediate segment
2851 precedes the offset, as it does when in AT&T mode. */
2854 && (strcmp (mnemonic
, "bound") != 0)
2855 && (strcmp (mnemonic
, "invlpga") != 0)
2856 && !(operand_type_check (i
.types
[0], imm
)
2857 && operand_type_check (i
.types
[1], imm
)))
2860 /* The order of the immediates should be reversed
2861 for 2 immediates extrq and insertq instructions */
2862 if (i
.imm_operands
== 2
2863 && (strcmp (mnemonic
, "extrq") == 0
2864 || strcmp (mnemonic
, "insertq") == 0))
2865 swap_2_operands (0, 1);
2870 /* Don't optimize displacement for movabs since it only takes 64bit
2873 && (flag_code
!= CODE_64BIT
2874 || strcmp (mnemonic
, "movabs") != 0))
2877 /* Next, we find a template that matches the given insn,
2878 making sure the overlap of the given operands types is consistent
2879 with the template operand types. */
2881 if (!(t
= match_template ()))
2884 if (sse_check
!= sse_check_none
2885 && !i
.tm
.opcode_modifier
.noavx
2886 && (i
.tm
.cpu_flags
.bitfield
.cpusse
2887 || i
.tm
.cpu_flags
.bitfield
.cpusse2
2888 || i
.tm
.cpu_flags
.bitfield
.cpusse3
2889 || i
.tm
.cpu_flags
.bitfield
.cpussse3
2890 || i
.tm
.cpu_flags
.bitfield
.cpusse4_1
2891 || i
.tm
.cpu_flags
.bitfield
.cpusse4_2
))
2893 (sse_check
== sse_check_warning
2895 : as_bad
) (_("SSE instruction `%s' is used"), i
.tm
.name
);
2898 /* Zap movzx and movsx suffix. The suffix has been set from
2899 "word ptr" or "byte ptr" on the source operand in Intel syntax
2900 or extracted from mnemonic in AT&T syntax. But we'll use
2901 the destination register to choose the suffix for encoding. */
2902 if ((i
.tm
.base_opcode
& ~9) == 0x0fb6)
2904 /* In Intel syntax, there must be a suffix. In AT&T syntax, if
2905 there is no suffix, the default will be byte extension. */
2906 if (i
.reg_operands
!= 2
2909 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
2914 if (i
.tm
.opcode_modifier
.fwait
)
2915 if (!add_prefix (FWAIT_OPCODE
))
2918 /* Check string instruction segment overrides. */
2919 if (i
.tm
.opcode_modifier
.isstring
&& i
.mem_operands
!= 0)
2921 if (!check_string ())
2923 i
.disp_operands
= 0;
2926 if (!process_suffix ())
2929 /* Update operand types. */
2930 for (j
= 0; j
< i
.operands
; j
++)
2931 i
.types
[j
] = operand_type_and (i
.types
[j
], i
.tm
.operand_types
[j
]);
2933 /* Make still unresolved immediate matches conform to size of immediate
2934 given in i.suffix. */
2935 if (!finalize_imm ())
2938 if (i
.types
[0].bitfield
.imm1
)
2939 i
.imm_operands
= 0; /* kludge for shift insns. */
2941 /* We only need to check those implicit registers for instructions
2942 with 3 operands or less. */
2943 if (i
.operands
<= 3)
2944 for (j
= 0; j
< i
.operands
; j
++)
2945 if (i
.types
[j
].bitfield
.inoutportreg
2946 || i
.types
[j
].bitfield
.shiftcount
2947 || i
.types
[j
].bitfield
.acc
2948 || i
.types
[j
].bitfield
.floatacc
)
2951 /* ImmExt should be processed after SSE2AVX. */
2952 if (!i
.tm
.opcode_modifier
.sse2avx
2953 && i
.tm
.opcode_modifier
.immext
)
2956 /* For insns with operands there are more diddles to do to the opcode. */
2959 if (!process_operands ())
2962 else if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
2964 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
2965 as_warn (_("translating to `%sp'"), i
.tm
.name
);
2968 if (i
.tm
.opcode_modifier
.vex
)
2969 build_vex_prefix (t
);
2971 /* Handle conversion of 'int $3' --> special int3 insn. */
2972 if (i
.tm
.base_opcode
== INT_OPCODE
&& i
.op
[0].imms
->X_add_number
== 3)
2974 i
.tm
.base_opcode
= INT3_OPCODE
;
2978 if ((i
.tm
.opcode_modifier
.jump
2979 || i
.tm
.opcode_modifier
.jumpbyte
2980 || i
.tm
.opcode_modifier
.jumpdword
)
2981 && i
.op
[0].disps
->X_op
== O_constant
)
2983 /* Convert "jmp constant" (and "call constant") to a jump (call) to
2984 the absolute address given by the constant. Since ix86 jumps and
2985 calls are pc relative, we need to generate a reloc. */
2986 i
.op
[0].disps
->X_add_symbol
= &abs_symbol
;
2987 i
.op
[0].disps
->X_op
= O_symbol
;
2990 if (i
.tm
.opcode_modifier
.rex64
)
2993 /* For 8 bit registers we need an empty rex prefix. Also if the
2994 instruction already has a prefix, we need to convert old
2995 registers to new ones. */
2997 if ((i
.types
[0].bitfield
.reg8
2998 && (i
.op
[0].regs
->reg_flags
& RegRex64
) != 0)
2999 || (i
.types
[1].bitfield
.reg8
3000 && (i
.op
[1].regs
->reg_flags
& RegRex64
) != 0)
3001 || ((i
.types
[0].bitfield
.reg8
3002 || i
.types
[1].bitfield
.reg8
)
3007 i
.rex
|= REX_OPCODE
;
3008 for (x
= 0; x
< 2; x
++)
3010 /* Look for 8 bit operand that uses old registers. */
3011 if (i
.types
[x
].bitfield
.reg8
3012 && (i
.op
[x
].regs
->reg_flags
& RegRex64
) == 0)
3014 /* In case it is "hi" register, give up. */
3015 if (i
.op
[x
].regs
->reg_num
> 3)
3016 as_bad (_("can't encode register '%s%s' in an "
3017 "instruction requiring REX prefix."),
3018 register_prefix
, i
.op
[x
].regs
->reg_name
);
3020 /* Otherwise it is equivalent to the extended register.
3021 Since the encoding doesn't change this is merely
3022 cosmetic cleanup for debug output. */
3024 i
.op
[x
].regs
= i
.op
[x
].regs
+ 8;
3030 add_prefix (REX_OPCODE
| i
.rex
);
3032 /* We are ready to output the insn. */
3037 parse_insn (char *line
, char *mnemonic
)
3040 char *token_start
= l
;
3043 const insn_template
*t
;
3046 /* Non-zero if we found a prefix only acceptable with string insns. */
3047 const char *expecting_string_instruction
= NULL
;
3052 while ((*mnem_p
= mnemonic_chars
[(unsigned char) *l
]) != 0)
3057 if (mnem_p
>= mnemonic
+ MAX_MNEM_SIZE
)
3059 as_bad (_("no such instruction: `%s'"), token_start
);
3064 if (!is_space_char (*l
)
3065 && *l
!= END_OF_INSN
3067 || (*l
!= PREFIX_SEPARATOR
3070 as_bad (_("invalid character %s in mnemonic"),
3071 output_invalid (*l
));
3074 if (token_start
== l
)
3076 if (!intel_syntax
&& *l
== PREFIX_SEPARATOR
)
3077 as_bad (_("expecting prefix; got nothing"));
3079 as_bad (_("expecting mnemonic; got nothing"));
3083 /* Look up instruction (or prefix) via hash table. */
3084 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3086 if (*l
!= END_OF_INSN
3087 && (!is_space_char (*l
) || l
[1] != END_OF_INSN
)
3088 && current_templates
3089 && current_templates
->start
->opcode_modifier
.isprefix
)
3091 if (!cpu_flags_check_cpu64 (current_templates
->start
->cpu_flags
))
3093 as_bad ((flag_code
!= CODE_64BIT
3094 ? _("`%s' is only supported in 64-bit mode")
3095 : _("`%s' is not supported in 64-bit mode")),
3096 current_templates
->start
->name
);
3099 /* If we are in 16-bit mode, do not allow addr16 or data16.
3100 Similarly, in 32-bit mode, do not allow addr32 or data32. */
3101 if ((current_templates
->start
->opcode_modifier
.size16
3102 || current_templates
->start
->opcode_modifier
.size32
)
3103 && flag_code
!= CODE_64BIT
3104 && (current_templates
->start
->opcode_modifier
.size32
3105 ^ (flag_code
== CODE_16BIT
)))
3107 as_bad (_("redundant %s prefix"),
3108 current_templates
->start
->name
);
3111 /* Add prefix, checking for repeated prefixes. */
3112 switch (add_prefix (current_templates
->start
->base_opcode
))
3117 expecting_string_instruction
= current_templates
->start
->name
;
3120 /* Skip past PREFIX_SEPARATOR and reset token_start. */
3127 if (!current_templates
)
3129 /* Check if we should swap operand in encoding. */
3130 if (mnem_p
- 2 == dot_p
&& dot_p
[1] == 's')
3136 current_templates
= (const templates
*) hash_find (op_hash
, mnemonic
);
3139 if (!current_templates
)
3142 /* See if we can get a match by trimming off a suffix. */
3145 case WORD_MNEM_SUFFIX
:
3146 if (intel_syntax
&& (intel_float_operand (mnemonic
) & 2))
3147 i
.suffix
= SHORT_MNEM_SUFFIX
;
3149 case BYTE_MNEM_SUFFIX
:
3150 case QWORD_MNEM_SUFFIX
:
3151 i
.suffix
= mnem_p
[-1];
3153 current_templates
= (const templates
*) hash_find (op_hash
,
3156 case SHORT_MNEM_SUFFIX
:
3157 case LONG_MNEM_SUFFIX
:
3160 i
.suffix
= mnem_p
[-1];
3162 current_templates
= (const templates
*) hash_find (op_hash
,
3171 if (intel_float_operand (mnemonic
) == 1)
3172 i
.suffix
= SHORT_MNEM_SUFFIX
;
3174 i
.suffix
= LONG_MNEM_SUFFIX
;
3176 current_templates
= (const templates
*) hash_find (op_hash
,
3181 if (!current_templates
)
3183 as_bad (_("no such instruction: `%s'"), token_start
);
3188 if (current_templates
->start
->opcode_modifier
.jump
3189 || current_templates
->start
->opcode_modifier
.jumpbyte
)
3191 /* Check for a branch hint. We allow ",pt" and ",pn" for
3192 predict taken and predict not taken respectively.
3193 I'm not sure that branch hints actually do anything on loop
3194 and jcxz insns (JumpByte) for current Pentium4 chips. They
3195 may work in the future and it doesn't hurt to accept them
3197 if (l
[0] == ',' && l
[1] == 'p')
3201 if (!add_prefix (DS_PREFIX_OPCODE
))
3205 else if (l
[2] == 'n')
3207 if (!add_prefix (CS_PREFIX_OPCODE
))
3213 /* Any other comma loses. */
3216 as_bad (_("invalid character %s in mnemonic"),
3217 output_invalid (*l
));
3221 /* Check if instruction is supported on specified architecture. */
3223 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3225 supported
|= cpu_flags_match (t
);
3226 if (supported
== CPU_FLAGS_PERFECT_MATCH
)
3230 if (!(supported
& CPU_FLAGS_64BIT_MATCH
))
3232 as_bad (flag_code
== CODE_64BIT
3233 ? _("`%s' is not supported in 64-bit mode")
3234 : _("`%s' is only supported in 64-bit mode"),
3235 current_templates
->start
->name
);
3238 if (supported
!= CPU_FLAGS_PERFECT_MATCH
)
3240 as_bad (_("`%s' is not supported on `%s%s'"),
3241 current_templates
->start
->name
,
3242 cpu_arch_name
? cpu_arch_name
: default_arch
,
3243 cpu_sub_arch_name
? cpu_sub_arch_name
: "");
3248 if (!cpu_arch_flags
.bitfield
.cpui386
3249 && (flag_code
!= CODE_16BIT
))
3251 as_warn (_("use .code16 to ensure correct addressing mode"));
3254 /* Check for rep/repne without a string instruction. */
3255 if (expecting_string_instruction
)
3257 static templates override
;
3259 for (t
= current_templates
->start
; t
< current_templates
->end
; ++t
)
3260 if (t
->opcode_modifier
.isstring
)
3262 if (t
>= current_templates
->end
)
3264 as_bad (_("expecting string instruction after `%s'"),
3265 expecting_string_instruction
);
3268 for (override
.start
= t
; t
< current_templates
->end
; ++t
)
3269 if (!t
->opcode_modifier
.isstring
)
3272 current_templates
= &override
;
3279 parse_operands (char *l
, const char *mnemonic
)
3283 /* 1 if operand is pending after ','. */
3284 unsigned int expecting_operand
= 0;
3286 /* Non-zero if operand parens not balanced. */
3287 unsigned int paren_not_balanced
;
3289 while (*l
!= END_OF_INSN
)
3291 /* Skip optional white space before operand. */
3292 if (is_space_char (*l
))
3294 if (!is_operand_char (*l
) && *l
!= END_OF_INSN
)
3296 as_bad (_("invalid character %s before operand %d"),
3297 output_invalid (*l
),
3301 token_start
= l
; /* after white space */
3302 paren_not_balanced
= 0;
3303 while (paren_not_balanced
|| *l
!= ',')
3305 if (*l
== END_OF_INSN
)
3307 if (paren_not_balanced
)
3310 as_bad (_("unbalanced parenthesis in operand %d."),
3313 as_bad (_("unbalanced brackets in operand %d."),
3318 break; /* we are done */
3320 else if (!is_operand_char (*l
) && !is_space_char (*l
))
3322 as_bad (_("invalid character %s in operand %d"),
3323 output_invalid (*l
),
3330 ++paren_not_balanced
;
3332 --paren_not_balanced
;
3337 ++paren_not_balanced
;
3339 --paren_not_balanced
;
3343 if (l
!= token_start
)
3344 { /* Yes, we've read in another operand. */
3345 unsigned int operand_ok
;
3346 this_operand
= i
.operands
++;
3347 i
.types
[this_operand
].bitfield
.unspecified
= 1;
3348 if (i
.operands
> MAX_OPERANDS
)
3350 as_bad (_("spurious operands; (%d operands/instruction max)"),
3354 /* Now parse operand adding info to 'i' as we go along. */
3355 END_STRING_AND_SAVE (l
);
3359 i386_intel_operand (token_start
,
3360 intel_float_operand (mnemonic
));
3362 operand_ok
= i386_att_operand (token_start
);
3364 RESTORE_END_STRING (l
);
3370 if (expecting_operand
)
3372 expecting_operand_after_comma
:
3373 as_bad (_("expecting operand after ','; got nothing"));
3378 as_bad (_("expecting operand before ','; got nothing"));
3383 /* Now *l must be either ',' or END_OF_INSN. */
3386 if (*++l
== END_OF_INSN
)
3388 /* Just skip it, if it's \n complain. */
3389 goto expecting_operand_after_comma
;
3391 expecting_operand
= 1;
3398 swap_2_operands (int xchg1
, int xchg2
)
3400 union i386_op temp_op
;
3401 i386_operand_type temp_type
;
3402 enum bfd_reloc_code_real temp_reloc
;
3404 temp_type
= i
.types
[xchg2
];
3405 i
.types
[xchg2
] = i
.types
[xchg1
];
3406 i
.types
[xchg1
] = temp_type
;
3407 temp_op
= i
.op
[xchg2
];
3408 i
.op
[xchg2
] = i
.op
[xchg1
];
3409 i
.op
[xchg1
] = temp_op
;
3410 temp_reloc
= i
.reloc
[xchg2
];
3411 i
.reloc
[xchg2
] = i
.reloc
[xchg1
];
3412 i
.reloc
[xchg1
] = temp_reloc
;
3416 swap_operands (void)
3422 swap_2_operands (1, i
.operands
- 2);
3425 swap_2_operands (0, i
.operands
- 1);
3431 if (i
.mem_operands
== 2)
3433 const seg_entry
*temp_seg
;
3434 temp_seg
= i
.seg
[0];
3435 i
.seg
[0] = i
.seg
[1];
3436 i
.seg
[1] = temp_seg
;
3440 /* Try to ensure constant immediates are represented in the smallest
3445 char guess_suffix
= 0;
3449 guess_suffix
= i
.suffix
;
3450 else if (i
.reg_operands
)
3452 /* Figure out a suffix from the last register operand specified.
3453 We can't do this properly yet, ie. excluding InOutPortReg,
3454 but the following works for instructions with immediates.
3455 In any case, we can't set i.suffix yet. */
3456 for (op
= i
.operands
; --op
>= 0;)
3457 if (i
.types
[op
].bitfield
.reg8
)
3459 guess_suffix
= BYTE_MNEM_SUFFIX
;
3462 else if (i
.types
[op
].bitfield
.reg16
)
3464 guess_suffix
= WORD_MNEM_SUFFIX
;
3467 else if (i
.types
[op
].bitfield
.reg32
)
3469 guess_suffix
= LONG_MNEM_SUFFIX
;
3472 else if (i
.types
[op
].bitfield
.reg64
)
3474 guess_suffix
= QWORD_MNEM_SUFFIX
;
3478 else if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
3479 guess_suffix
= WORD_MNEM_SUFFIX
;
3481 for (op
= i
.operands
; --op
>= 0;)
3482 if (operand_type_check (i
.types
[op
], imm
))
3484 switch (i
.op
[op
].imms
->X_op
)
3487 /* If a suffix is given, this operand may be shortened. */
3488 switch (guess_suffix
)
3490 case LONG_MNEM_SUFFIX
:
3491 i
.types
[op
].bitfield
.imm32
= 1;
3492 i
.types
[op
].bitfield
.imm64
= 1;
3494 case WORD_MNEM_SUFFIX
:
3495 i
.types
[op
].bitfield
.imm16
= 1;
3496 i
.types
[op
].bitfield
.imm32
= 1;
3497 i
.types
[op
].bitfield
.imm32s
= 1;
3498 i
.types
[op
].bitfield
.imm64
= 1;
3500 case BYTE_MNEM_SUFFIX
:
3501 i
.types
[op
].bitfield
.imm8
= 1;
3502 i
.types
[op
].bitfield
.imm8s
= 1;
3503 i
.types
[op
].bitfield
.imm16
= 1;
3504 i
.types
[op
].bitfield
.imm32
= 1;
3505 i
.types
[op
].bitfield
.imm32s
= 1;
3506 i
.types
[op
].bitfield
.imm64
= 1;
3510 /* If this operand is at most 16 bits, convert it
3511 to a signed 16 bit number before trying to see
3512 whether it will fit in an even smaller size.
3513 This allows a 16-bit operand such as $0xffe0 to
3514 be recognised as within Imm8S range. */
3515 if ((i
.types
[op
].bitfield
.imm16
)
3516 && (i
.op
[op
].imms
->X_add_number
& ~(offsetT
) 0xffff) == 0)
3518 i
.op
[op
].imms
->X_add_number
=
3519 (((i
.op
[op
].imms
->X_add_number
& 0xffff) ^ 0x8000) - 0x8000);
3521 if ((i
.types
[op
].bitfield
.imm32
)
3522 && ((i
.op
[op
].imms
->X_add_number
& ~(((offsetT
) 2 << 31) - 1))
3525 i
.op
[op
].imms
->X_add_number
= ((i
.op
[op
].imms
->X_add_number
3526 ^ ((offsetT
) 1 << 31))
3527 - ((offsetT
) 1 << 31));
3530 = operand_type_or (i
.types
[op
],
3531 smallest_imm_type (i
.op
[op
].imms
->X_add_number
));
3533 /* We must avoid matching of Imm32 templates when 64bit
3534 only immediate is available. */
3535 if (guess_suffix
== QWORD_MNEM_SUFFIX
)
3536 i
.types
[op
].bitfield
.imm32
= 0;
3543 /* Symbols and expressions. */
3545 /* Convert symbolic operand to proper sizes for matching, but don't
3546 prevent matching a set of insns that only supports sizes other
3547 than those matching the insn suffix. */
3549 i386_operand_type mask
, allowed
;
3550 const insn_template
*t
;
3552 operand_type_set (&mask
, 0);
3553 operand_type_set (&allowed
, 0);
3555 for (t
= current_templates
->start
;
3556 t
< current_templates
->end
;
3558 allowed
= operand_type_or (allowed
,
3559 t
->operand_types
[op
]);
3560 switch (guess_suffix
)
3562 case QWORD_MNEM_SUFFIX
:
3563 mask
.bitfield
.imm64
= 1;
3564 mask
.bitfield
.imm32s
= 1;
3566 case LONG_MNEM_SUFFIX
:
3567 mask
.bitfield
.imm32
= 1;
3569 case WORD_MNEM_SUFFIX
:
3570 mask
.bitfield
.imm16
= 1;
3572 case BYTE_MNEM_SUFFIX
:
3573 mask
.bitfield
.imm8
= 1;
3578 allowed
= operand_type_and (mask
, allowed
);
3579 if (!operand_type_all_zero (&allowed
))
3580 i
.types
[op
] = operand_type_and (i
.types
[op
], mask
);
3587 /* Try to use the smallest displacement type too. */
3589 optimize_disp (void)
3593 for (op
= i
.operands
; --op
>= 0;)
3594 if (operand_type_check (i
.types
[op
], disp
))
3596 if (i
.op
[op
].disps
->X_op
== O_constant
)
3598 offsetT disp
= i
.op
[op
].disps
->X_add_number
;
3600 if (i
.types
[op
].bitfield
.disp16
3601 && (disp
& ~(offsetT
) 0xffff) == 0)
3603 /* If this operand is at most 16 bits, convert
3604 to a signed 16 bit number and don't use 64bit
3606 disp
= (((disp
& 0xffff) ^ 0x8000) - 0x8000);
3607 i
.types
[op
].bitfield
.disp64
= 0;
3609 if (i
.types
[op
].bitfield
.disp32
3610 && (disp
& ~(((offsetT
) 2 << 31) - 1)) == 0)
3612 /* If this operand is at most 32 bits, convert
3613 to a signed 32 bit number and don't use 64bit
3615 disp
&= (((offsetT
) 2 << 31) - 1);
3616 disp
= (disp
^ ((offsetT
) 1 << 31)) - ((addressT
) 1 << 31);
3617 i
.types
[op
].bitfield
.disp64
= 0;
3619 if (!disp
&& i
.types
[op
].bitfield
.baseindex
)
3621 i
.types
[op
].bitfield
.disp8
= 0;
3622 i
.types
[op
].bitfield
.disp16
= 0;
3623 i
.types
[op
].bitfield
.disp32
= 0;
3624 i
.types
[op
].bitfield
.disp32s
= 0;
3625 i
.types
[op
].bitfield
.disp64
= 0;
3629 else if (flag_code
== CODE_64BIT
)
3631 if (fits_in_signed_long (disp
))
3633 i
.types
[op
].bitfield
.disp64
= 0;
3634 i
.types
[op
].bitfield
.disp32s
= 1;
3636 if (i
.prefix
[ADDR_PREFIX
]
3637 && fits_in_unsigned_long (disp
))
3638 i
.types
[op
].bitfield
.disp32
= 1;
3640 if ((i
.types
[op
].bitfield
.disp32
3641 || i
.types
[op
].bitfield
.disp32s
3642 || i
.types
[op
].bitfield
.disp16
)
3643 && fits_in_signed_byte (disp
))
3644 i
.types
[op
].bitfield
.disp8
= 1;
3646 else if (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
3647 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
)
3649 fix_new_exp (frag_now
, frag_more (0) - frag_now
->fr_literal
, 0,
3650 i
.op
[op
].disps
, 0, i
.reloc
[op
]);
3651 i
.types
[op
].bitfield
.disp8
= 0;
3652 i
.types
[op
].bitfield
.disp16
= 0;
3653 i
.types
[op
].bitfield
.disp32
= 0;
3654 i
.types
[op
].bitfield
.disp32s
= 0;
3655 i
.types
[op
].bitfield
.disp64
= 0;
3658 /* We only support 64bit displacement on constants. */
3659 i
.types
[op
].bitfield
.disp64
= 0;
3663 static const insn_template
*
3664 match_template (void)
3666 /* Points to template once we've found it. */
3667 const insn_template
*t
;
3668 i386_operand_type overlap0
, overlap1
, overlap2
, overlap3
;
3669 i386_operand_type overlap4
;
3670 unsigned int found_reverse_match
;
3671 i386_opcode_modifier suffix_check
;
3672 i386_operand_type operand_types
[MAX_OPERANDS
];
3673 int addr_prefix_disp
;
3675 unsigned int found_cpu_match
;
3676 unsigned int check_register
;
3678 #if MAX_OPERANDS != 5
3679 # error "MAX_OPERANDS must be 5."
3682 found_reverse_match
= 0;
3683 addr_prefix_disp
= -1;
3685 memset (&suffix_check
, 0, sizeof (suffix_check
));
3686 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
3687 suffix_check
.no_bsuf
= 1;
3688 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
3689 suffix_check
.no_wsuf
= 1;
3690 else if (i
.suffix
== SHORT_MNEM_SUFFIX
)
3691 suffix_check
.no_ssuf
= 1;
3692 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
3693 suffix_check
.no_lsuf
= 1;
3694 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
3695 suffix_check
.no_qsuf
= 1;
3696 else if (i
.suffix
== LONG_DOUBLE_MNEM_SUFFIX
)
3697 suffix_check
.no_ldsuf
= 1;
3699 for (t
= current_templates
->start
; t
< current_templates
->end
; t
++)
3701 addr_prefix_disp
= -1;
3703 /* Must have right number of operands. */
3704 if (i
.operands
!= t
->operands
)
3707 /* Check processor support. */
3708 found_cpu_match
= (cpu_flags_match (t
)
3709 == CPU_FLAGS_PERFECT_MATCH
);
3710 if (!found_cpu_match
)
3713 /* Check old gcc support. */
3714 if (!old_gcc
&& t
->opcode_modifier
.oldgcc
)
3717 /* Check AT&T mnemonic. */
3718 if (intel_mnemonic
&& t
->opcode_modifier
.attmnemonic
)
3721 /* Check AT&T syntax Intel syntax. */
3722 if ((intel_syntax
&& t
->opcode_modifier
.attsyntax
)
3723 || (!intel_syntax
&& t
->opcode_modifier
.intelsyntax
))
3726 /* Check the suffix, except for some instructions in intel mode. */
3727 if ((!intel_syntax
|| !t
->opcode_modifier
.ignoresize
)
3728 && ((t
->opcode_modifier
.no_bsuf
&& suffix_check
.no_bsuf
)
3729 || (t
->opcode_modifier
.no_wsuf
&& suffix_check
.no_wsuf
)
3730 || (t
->opcode_modifier
.no_lsuf
&& suffix_check
.no_lsuf
)
3731 || (t
->opcode_modifier
.no_ssuf
&& suffix_check
.no_ssuf
)
3732 || (t
->opcode_modifier
.no_qsuf
&& suffix_check
.no_qsuf
)
3733 || (t
->opcode_modifier
.no_ldsuf
&& suffix_check
.no_ldsuf
)))
3736 if (!operand_size_match (t
))
3739 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3740 operand_types
[j
] = t
->operand_types
[j
];
3742 /* In general, don't allow 64-bit operands in 32-bit mode. */
3743 if (i
.suffix
== QWORD_MNEM_SUFFIX
3744 && flag_code
!= CODE_64BIT
3746 ? (!t
->opcode_modifier
.ignoresize
3747 && !intel_float_operand (t
->name
))
3748 : intel_float_operand (t
->name
) != 2)
3749 && ((!operand_types
[0].bitfield
.regmmx
3750 && !operand_types
[0].bitfield
.regxmm
3751 && !operand_types
[0].bitfield
.regymm
)
3752 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3753 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
3754 && !!operand_types
[t
->operands
> 1].bitfield
.regymm
))
3755 && (t
->base_opcode
!= 0x0fc7
3756 || t
->extension_opcode
!= 1 /* cmpxchg8b */))
3759 /* In general, don't allow 32-bit operands on pre-386. */
3760 else if (i
.suffix
== LONG_MNEM_SUFFIX
3761 && !cpu_arch_flags
.bitfield
.cpui386
3763 ? (!t
->opcode_modifier
.ignoresize
3764 && !intel_float_operand (t
->name
))
3765 : intel_float_operand (t
->name
) != 2)
3766 && ((!operand_types
[0].bitfield
.regmmx
3767 && !operand_types
[0].bitfield
.regxmm
)
3768 || (!operand_types
[t
->operands
> 1].bitfield
.regmmx
3769 && !!operand_types
[t
->operands
> 1].bitfield
.regxmm
)))
3772 /* Do not verify operands when there are none. */
3776 /* We've found a match; break out of loop. */
3780 /* Address size prefix will turn Disp64/Disp32/Disp16 operand
3781 into Disp32/Disp16/Disp32 operand. */
3782 if (i
.prefix
[ADDR_PREFIX
] != 0)
3784 /* There should be only one Disp operand. */
3788 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3790 if (operand_types
[j
].bitfield
.disp16
)
3792 addr_prefix_disp
= j
;
3793 operand_types
[j
].bitfield
.disp32
= 1;
3794 operand_types
[j
].bitfield
.disp16
= 0;
3800 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3802 if (operand_types
[j
].bitfield
.disp32
)
3804 addr_prefix_disp
= j
;
3805 operand_types
[j
].bitfield
.disp32
= 0;
3806 operand_types
[j
].bitfield
.disp16
= 1;
3812 for (j
= 0; j
< MAX_OPERANDS
; j
++)
3814 if (operand_types
[j
].bitfield
.disp64
)
3816 addr_prefix_disp
= j
;
3817 operand_types
[j
].bitfield
.disp64
= 0;
3818 operand_types
[j
].bitfield
.disp32
= 1;
3826 /* We check register size only if size of operands can be
3827 encoded the canonical way. */
3828 check_register
= t
->opcode_modifier
.w
;
3829 overlap0
= operand_type_and (i
.types
[0], operand_types
[0]);
3830 switch (t
->operands
)
3833 if (!operand_type_match (overlap0
, i
.types
[0]))
3837 /* xchg %eax, %eax is a special case. It is an aliase for nop
3838 only in 32bit mode and we can use opcode 0x90. In 64bit
3839 mode, we can't use 0x90 for xchg %eax, %eax since it should
3840 zero-extend %eax to %rax. */
3841 if (flag_code
== CODE_64BIT
3842 && t
->base_opcode
== 0x90
3843 && operand_type_equal (&i
.types
[0], &acc32
)
3844 && operand_type_equal (&i
.types
[1], &acc32
))
3848 /* If we swap operand in encoding, we either match
3849 the next one or reverse direction of operands. */
3850 if (t
->opcode_modifier
.s
)
3852 else if (t
->opcode_modifier
.d
)
3857 /* If we swap operand in encoding, we match the next one. */
3858 if (i
.swap_operand
&& t
->opcode_modifier
.s
)
3862 overlap1
= operand_type_and (i
.types
[1], operand_types
[1]);
3863 if (!operand_type_match (overlap0
, i
.types
[0])
3864 || !operand_type_match (overlap1
, i
.types
[1])
3866 && !operand_type_register_match (overlap0
, i
.types
[0],
3868 overlap1
, i
.types
[1],
3871 /* Check if other direction is valid ... */
3872 if (!t
->opcode_modifier
.d
&& !t
->opcode_modifier
.floatd
)
3876 /* Try reversing direction of operands. */
3877 overlap0
= operand_type_and (i
.types
[0], operand_types
[1]);
3878 overlap1
= operand_type_and (i
.types
[1], operand_types
[0]);
3879 if (!operand_type_match (overlap0
, i
.types
[0])
3880 || !operand_type_match (overlap1
, i
.types
[1])
3882 && !operand_type_register_match (overlap0
,
3889 /* Does not match either direction. */
3892 /* found_reverse_match holds which of D or FloatDR
3894 if (t
->opcode_modifier
.d
)
3895 found_reverse_match
= Opcode_D
;
3896 else if (t
->opcode_modifier
.floatd
)
3897 found_reverse_match
= Opcode_FloatD
;
3899 found_reverse_match
= 0;
3900 if (t
->opcode_modifier
.floatr
)
3901 found_reverse_match
|= Opcode_FloatR
;
3905 /* Found a forward 2 operand match here. */
3906 switch (t
->operands
)
3909 overlap4
= operand_type_and (i
.types
[4],
3912 overlap3
= operand_type_and (i
.types
[3],
3915 overlap2
= operand_type_and (i
.types
[2],
3920 switch (t
->operands
)
3923 if (!operand_type_match (overlap4
, i
.types
[4])
3924 || !operand_type_register_match (overlap3
,
3932 if (!operand_type_match (overlap3
, i
.types
[3])
3934 && !operand_type_register_match (overlap2
,
3942 /* Here we make use of the fact that there are no
3943 reverse match 3 operand instructions, and all 3
3944 operand instructions only need to be checked for
3945 register consistency between operands 2 and 3. */
3946 if (!operand_type_match (overlap2
, i
.types
[2])
3948 && !operand_type_register_match (overlap1
,
3958 /* Found either forward/reverse 2, 3 or 4 operand match here:
3959 slip through to break. */
3961 if (!found_cpu_match
)
3963 found_reverse_match
= 0;
3967 /* We've found a match; break out of loop. */
3971 if (t
== current_templates
->end
)
3973 /* We found no match. */
3975 as_bad (_("ambiguous operand size or operands invalid for `%s'"),
3976 current_templates
->start
->name
);
3978 as_bad (_("suffix or operands invalid for `%s'"),
3979 current_templates
->start
->name
);
3983 if (!quiet_warnings
)
3986 && (i
.types
[0].bitfield
.jumpabsolute
3987 != operand_types
[0].bitfield
.jumpabsolute
))
3989 as_warn (_("indirect %s without `*'"), t
->name
);
3992 if (t
->opcode_modifier
.isprefix
3993 && t
->opcode_modifier
.ignoresize
)
3995 /* Warn them that a data or address size prefix doesn't
3996 affect assembly of the next line of code. */
3997 as_warn (_("stand-alone `%s' prefix"), t
->name
);
4001 /* Copy the template we found. */
4004 if (addr_prefix_disp
!= -1)
4005 i
.tm
.operand_types
[addr_prefix_disp
]
4006 = operand_types
[addr_prefix_disp
];
4008 if (found_reverse_match
)
4010 /* If we found a reverse match we must alter the opcode
4011 direction bit. found_reverse_match holds bits to change
4012 (different for int & float insns). */
4014 i
.tm
.base_opcode
^= found_reverse_match
;
4016 i
.tm
.operand_types
[0] = operand_types
[1];
4017 i
.tm
.operand_types
[1] = operand_types
[0];
4026 int mem_op
= operand_type_check (i
.types
[0], anymem
) ? 0 : 1;
4027 if (i
.tm
.operand_types
[mem_op
].bitfield
.esseg
)
4029 if (i
.seg
[0] != NULL
&& i
.seg
[0] != &es
)
4031 as_bad (_("`%s' operand %d must use `%ses' segment"),
4037 /* There's only ever one segment override allowed per instruction.
4038 This instruction possibly has a legal segment override on the
4039 second operand, so copy the segment to where non-string
4040 instructions store it, allowing common code. */
4041 i
.seg
[0] = i
.seg
[1];
4043 else if (i
.tm
.operand_types
[mem_op
+ 1].bitfield
.esseg
)
4045 if (i
.seg
[1] != NULL
&& i
.seg
[1] != &es
)
4047 as_bad (_("`%s' operand %d must use `%ses' segment"),
4058 process_suffix (void)
4060 /* If matched instruction specifies an explicit instruction mnemonic
4062 if (i
.tm
.opcode_modifier
.size16
)
4063 i
.suffix
= WORD_MNEM_SUFFIX
;
4064 else if (i
.tm
.opcode_modifier
.size32
)
4065 i
.suffix
= LONG_MNEM_SUFFIX
;
4066 else if (i
.tm
.opcode_modifier
.size64
)
4067 i
.suffix
= QWORD_MNEM_SUFFIX
;
4068 else if (i
.reg_operands
)
4070 /* If there's no instruction mnemonic suffix we try to invent one
4071 based on register operands. */
4074 /* We take i.suffix from the last register operand specified,
4075 Destination register type is more significant than source
4076 register type. crc32 in SSE4.2 prefers source register
4078 if (i
.tm
.base_opcode
== 0xf20f38f1)
4080 if (i
.types
[0].bitfield
.reg16
)
4081 i
.suffix
= WORD_MNEM_SUFFIX
;
4082 else if (i
.types
[0].bitfield
.reg32
)
4083 i
.suffix
= LONG_MNEM_SUFFIX
;
4084 else if (i
.types
[0].bitfield
.reg64
)
4085 i
.suffix
= QWORD_MNEM_SUFFIX
;
4087 else if (i
.tm
.base_opcode
== 0xf20f38f0)
4089 if (i
.types
[0].bitfield
.reg8
)
4090 i
.suffix
= BYTE_MNEM_SUFFIX
;
4097 if (i
.tm
.base_opcode
== 0xf20f38f1
4098 || i
.tm
.base_opcode
== 0xf20f38f0)
4100 /* We have to know the operand size for crc32. */
4101 as_bad (_("ambiguous memory operand size for `%s`"),
4106 for (op
= i
.operands
; --op
>= 0;)
4107 if (!i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4109 if (i
.types
[op
].bitfield
.reg8
)
4111 i
.suffix
= BYTE_MNEM_SUFFIX
;
4114 else if (i
.types
[op
].bitfield
.reg16
)
4116 i
.suffix
= WORD_MNEM_SUFFIX
;
4119 else if (i
.types
[op
].bitfield
.reg32
)
4121 i
.suffix
= LONG_MNEM_SUFFIX
;
4124 else if (i
.types
[op
].bitfield
.reg64
)
4126 i
.suffix
= QWORD_MNEM_SUFFIX
;
4132 else if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4134 if (!check_byte_reg ())
4137 else if (i
.suffix
== LONG_MNEM_SUFFIX
)
4139 if (!check_long_reg ())
4142 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4145 && i
.tm
.opcode_modifier
.ignoresize
4146 && i
.tm
.opcode_modifier
.no_qsuf
)
4148 else if (!check_qword_reg ())
4151 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4153 if (!check_word_reg ())
4156 else if (i
.suffix
== XMMWORD_MNEM_SUFFIX
4157 || i
.suffix
== YMMWORD_MNEM_SUFFIX
)
4159 /* Skip if the instruction has x/y suffix. match_template
4160 should check if it is a valid suffix. */
4162 else if (intel_syntax
&& i
.tm
.opcode_modifier
.ignoresize
)
4163 /* Do nothing if the instruction is going to ignore the prefix. */
4168 else if (i
.tm
.opcode_modifier
.defaultsize
4170 /* exclude fldenv/frstor/fsave/fstenv */
4171 && i
.tm
.opcode_modifier
.no_ssuf
)
4173 i
.suffix
= stackop_size
;
4175 else if (intel_syntax
4177 && (i
.tm
.operand_types
[0].bitfield
.jumpabsolute
4178 || i
.tm
.opcode_modifier
.jumpbyte
4179 || i
.tm
.opcode_modifier
.jumpintersegment
4180 || (i
.tm
.base_opcode
== 0x0f01 /* [ls][gi]dt */
4181 && i
.tm
.extension_opcode
<= 3)))
4186 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4188 i
.suffix
= QWORD_MNEM_SUFFIX
;
4192 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4193 i
.suffix
= LONG_MNEM_SUFFIX
;
4196 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4197 i
.suffix
= WORD_MNEM_SUFFIX
;
4206 if (i
.tm
.opcode_modifier
.w
)
4208 as_bad (_("no instruction mnemonic suffix given and "
4209 "no register operands; can't size instruction"));
4215 unsigned int suffixes
;
4217 suffixes
= !i
.tm
.opcode_modifier
.no_bsuf
;
4218 if (!i
.tm
.opcode_modifier
.no_wsuf
)
4220 if (!i
.tm
.opcode_modifier
.no_lsuf
)
4222 if (!i
.tm
.opcode_modifier
.no_ldsuf
)
4224 if (!i
.tm
.opcode_modifier
.no_ssuf
)
4226 if (!i
.tm
.opcode_modifier
.no_qsuf
)
4229 /* There are more than suffix matches. */
4230 if (i
.tm
.opcode_modifier
.w
4231 || ((suffixes
& (suffixes
- 1))
4232 && !i
.tm
.opcode_modifier
.defaultsize
4233 && !i
.tm
.opcode_modifier
.ignoresize
))
4235 as_bad (_("ambiguous operand size for `%s'"), i
.tm
.name
);
4241 /* Change the opcode based on the operand size given by i.suffix;
4242 We don't need to change things for byte insns. */
4245 && i
.suffix
!= BYTE_MNEM_SUFFIX
4246 && i
.suffix
!= XMMWORD_MNEM_SUFFIX
4247 && i
.suffix
!= YMMWORD_MNEM_SUFFIX
)
4249 /* It's not a byte, select word/dword operation. */
4250 if (i
.tm
.opcode_modifier
.w
)
4252 if (i
.tm
.opcode_modifier
.shortform
)
4253 i
.tm
.base_opcode
|= 8;
4255 i
.tm
.base_opcode
|= 1;
4258 /* Now select between word & dword operations via the operand
4259 size prefix, except for instructions that will ignore this
4261 if (i
.tm
.opcode_modifier
.addrprefixop0
)
4263 /* The address size override prefix changes the size of the
4265 if ((flag_code
== CODE_32BIT
4266 && i
.op
->regs
[0].reg_type
.bitfield
.reg16
)
4267 || (flag_code
!= CODE_32BIT
4268 && i
.op
->regs
[0].reg_type
.bitfield
.reg32
))
4269 if (!add_prefix (ADDR_PREFIX_OPCODE
))
4272 else if (i
.suffix
!= QWORD_MNEM_SUFFIX
4273 && i
.suffix
!= LONG_DOUBLE_MNEM_SUFFIX
4274 && !i
.tm
.opcode_modifier
.ignoresize
4275 && !i
.tm
.opcode_modifier
.floatmf
4276 && ((i
.suffix
== LONG_MNEM_SUFFIX
) == (flag_code
== CODE_16BIT
)
4277 || (flag_code
== CODE_64BIT
4278 && i
.tm
.opcode_modifier
.jumpbyte
)))
4280 unsigned int prefix
= DATA_PREFIX_OPCODE
;
4282 if (i
.tm
.opcode_modifier
.jumpbyte
) /* jcxz, loop */
4283 prefix
= ADDR_PREFIX_OPCODE
;
4285 if (!add_prefix (prefix
))
4289 /* Set mode64 for an operand. */
4290 if (i
.suffix
== QWORD_MNEM_SUFFIX
4291 && flag_code
== CODE_64BIT
4292 && !i
.tm
.opcode_modifier
.norex64
)
4294 /* Special case for xchg %rax,%rax. It is NOP and doesn't
4295 need rex64. cmpxchg8b is also a special case. */
4296 if (! (i
.operands
== 2
4297 && i
.tm
.base_opcode
== 0x90
4298 && i
.tm
.extension_opcode
== None
4299 && operand_type_equal (&i
.types
[0], &acc64
)
4300 && operand_type_equal (&i
.types
[1], &acc64
))
4301 && ! (i
.operands
== 1
4302 && i
.tm
.base_opcode
== 0xfc7
4303 && i
.tm
.extension_opcode
== 1
4304 && !operand_type_check (i
.types
[0], reg
)
4305 && operand_type_check (i
.types
[0], anymem
)))
4309 /* Size floating point instruction. */
4310 if (i
.suffix
== LONG_MNEM_SUFFIX
)
4311 if (i
.tm
.opcode_modifier
.floatmf
)
4312 i
.tm
.base_opcode
^= 4;
4319 check_byte_reg (void)
4323 for (op
= i
.operands
; --op
>= 0;)
4325 /* If this is an eight bit register, it's OK. If it's the 16 or
4326 32 bit version of an eight bit register, we will just use the
4327 low portion, and that's OK too. */
4328 if (i
.types
[op
].bitfield
.reg8
)
4331 /* Don't generate this warning if not needed. */
4332 if (intel_syntax
&& i
.tm
.opcode_modifier
.byteokintel
)
4335 /* crc32 doesn't generate this warning. */
4336 if (i
.tm
.base_opcode
== 0xf20f38f0)
4339 if ((i
.types
[op
].bitfield
.reg16
4340 || i
.types
[op
].bitfield
.reg32
4341 || i
.types
[op
].bitfield
.reg64
)
4342 && i
.op
[op
].regs
->reg_num
< 4)
4344 /* Prohibit these changes in the 64bit mode, since the
4345 lowering is more complicated. */
4346 if (flag_code
== CODE_64BIT
4347 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4349 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4350 register_prefix
, i
.op
[op
].regs
->reg_name
,
4354 #if REGISTER_WARNINGS
4356 && !i
.tm
.operand_types
[op
].bitfield
.inoutportreg
)
4357 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4359 (i
.op
[op
].regs
+ (i
.types
[op
].bitfield
.reg16
4360 ? REGNAM_AL
- REGNAM_AX
4361 : REGNAM_AL
- REGNAM_EAX
))->reg_name
,
4363 i
.op
[op
].regs
->reg_name
,
4368 /* Any other register is bad. */
4369 if (i
.types
[op
].bitfield
.reg16
4370 || i
.types
[op
].bitfield
.reg32
4371 || i
.types
[op
].bitfield
.reg64
4372 || i
.types
[op
].bitfield
.regmmx
4373 || i
.types
[op
].bitfield
.regxmm
4374 || i
.types
[op
].bitfield
.regymm
4375 || i
.types
[op
].bitfield
.sreg2
4376 || i
.types
[op
].bitfield
.sreg3
4377 || i
.types
[op
].bitfield
.control
4378 || i
.types
[op
].bitfield
.debug
4379 || i
.types
[op
].bitfield
.test
4380 || i
.types
[op
].bitfield
.floatreg
4381 || i
.types
[op
].bitfield
.floatacc
)
4383 as_bad (_("`%s%s' not allowed with `%s%c'"),
4385 i
.op
[op
].regs
->reg_name
,
4395 check_long_reg (void)
4399 for (op
= i
.operands
; --op
>= 0;)
4400 /* Reject eight bit registers, except where the template requires
4401 them. (eg. movzb) */
4402 if (i
.types
[op
].bitfield
.reg8
4403 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4404 || i
.tm
.operand_types
[op
].bitfield
.reg32
4405 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4407 as_bad (_("`%s%s' not allowed with `%s%c'"),
4409 i
.op
[op
].regs
->reg_name
,
4414 /* Warn if the e prefix on a general reg is missing. */
4415 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4416 && i
.types
[op
].bitfield
.reg16
4417 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4418 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4420 /* Prohibit these changes in the 64bit mode, since the
4421 lowering is more complicated. */
4422 if (flag_code
== CODE_64BIT
)
4424 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4425 register_prefix
, i
.op
[op
].regs
->reg_name
,
4429 #if REGISTER_WARNINGS
4431 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4433 (i
.op
[op
].regs
+ REGNAM_EAX
- REGNAM_AX
)->reg_name
,
4435 i
.op
[op
].regs
->reg_name
,
4439 /* Warn if the r prefix on a general reg is missing. */
4440 else if (i
.types
[op
].bitfield
.reg64
4441 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4442 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4445 && i
.tm
.opcode_modifier
.toqword
4446 && !i
.types
[0].bitfield
.regxmm
)
4448 /* Convert to QWORD. We want REX byte. */
4449 i
.suffix
= QWORD_MNEM_SUFFIX
;
4453 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4454 register_prefix
, i
.op
[op
].regs
->reg_name
,
4463 check_qword_reg (void)
4467 for (op
= i
.operands
; --op
>= 0; )
4468 /* Reject eight bit registers, except where the template requires
4469 them. (eg. movzb) */
4470 if (i
.types
[op
].bitfield
.reg8
4471 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4472 || i
.tm
.operand_types
[op
].bitfield
.reg32
4473 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4475 as_bad (_("`%s%s' not allowed with `%s%c'"),
4477 i
.op
[op
].regs
->reg_name
,
4482 /* Warn if the e prefix on a general reg is missing. */
4483 else if ((i
.types
[op
].bitfield
.reg16
4484 || i
.types
[op
].bitfield
.reg32
)
4485 && (i
.tm
.operand_types
[op
].bitfield
.reg32
4486 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4488 /* Prohibit these changes in the 64bit mode, since the
4489 lowering is more complicated. */
4491 && i
.tm
.opcode_modifier
.todword
4492 && !i
.types
[0].bitfield
.regxmm
)
4494 /* Convert to DWORD. We don't want REX byte. */
4495 i
.suffix
= LONG_MNEM_SUFFIX
;
4499 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4500 register_prefix
, i
.op
[op
].regs
->reg_name
,
4509 check_word_reg (void)
4512 for (op
= i
.operands
; --op
>= 0;)
4513 /* Reject eight bit registers, except where the template requires
4514 them. (eg. movzb) */
4515 if (i
.types
[op
].bitfield
.reg8
4516 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4517 || i
.tm
.operand_types
[op
].bitfield
.reg32
4518 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4520 as_bad (_("`%s%s' not allowed with `%s%c'"),
4522 i
.op
[op
].regs
->reg_name
,
4527 /* Warn if the e prefix on a general reg is present. */
4528 else if ((!quiet_warnings
|| flag_code
== CODE_64BIT
)
4529 && i
.types
[op
].bitfield
.reg32
4530 && (i
.tm
.operand_types
[op
].bitfield
.reg16
4531 || i
.tm
.operand_types
[op
].bitfield
.acc
))
4533 /* Prohibit these changes in the 64bit mode, since the
4534 lowering is more complicated. */
4535 if (flag_code
== CODE_64BIT
)
4537 as_bad (_("Incorrect register `%s%s' used with `%c' suffix"),
4538 register_prefix
, i
.op
[op
].regs
->reg_name
,
4543 #if REGISTER_WARNINGS
4544 as_warn (_("using `%s%s' instead of `%s%s' due to `%c' suffix"),
4546 (i
.op
[op
].regs
+ REGNAM_AX
- REGNAM_EAX
)->reg_name
,
4548 i
.op
[op
].regs
->reg_name
,
4556 update_imm (unsigned int j
)
4558 i386_operand_type overlap
= i
.types
[j
];
4559 if ((overlap
.bitfield
.imm8
4560 || overlap
.bitfield
.imm8s
4561 || overlap
.bitfield
.imm16
4562 || overlap
.bitfield
.imm32
4563 || overlap
.bitfield
.imm32s
4564 || overlap
.bitfield
.imm64
)
4565 && !operand_type_equal (&overlap
, &imm8
)
4566 && !operand_type_equal (&overlap
, &imm8s
)
4567 && !operand_type_equal (&overlap
, &imm16
)
4568 && !operand_type_equal (&overlap
, &imm32
)
4569 && !operand_type_equal (&overlap
, &imm32s
)
4570 && !operand_type_equal (&overlap
, &imm64
))
4574 i386_operand_type temp
;
4576 operand_type_set (&temp
, 0);
4577 if (i
.suffix
== BYTE_MNEM_SUFFIX
)
4579 temp
.bitfield
.imm8
= overlap
.bitfield
.imm8
;
4580 temp
.bitfield
.imm8s
= overlap
.bitfield
.imm8s
;
4582 else if (i
.suffix
== WORD_MNEM_SUFFIX
)
4583 temp
.bitfield
.imm16
= overlap
.bitfield
.imm16
;
4584 else if (i
.suffix
== QWORD_MNEM_SUFFIX
)
4586 temp
.bitfield
.imm64
= overlap
.bitfield
.imm64
;
4587 temp
.bitfield
.imm32s
= overlap
.bitfield
.imm32s
;
4590 temp
.bitfield
.imm32
= overlap
.bitfield
.imm32
;
4593 else if (operand_type_equal (&overlap
, &imm16_32_32s
)
4594 || operand_type_equal (&overlap
, &imm16_32
)
4595 || operand_type_equal (&overlap
, &imm16_32s
))
4597 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[DATA_PREFIX
] != 0))
4602 if (!operand_type_equal (&overlap
, &imm8
)
4603 && !operand_type_equal (&overlap
, &imm8s
)
4604 && !operand_type_equal (&overlap
, &imm16
)
4605 && !operand_type_equal (&overlap
, &imm32
)
4606 && !operand_type_equal (&overlap
, &imm32s
)
4607 && !operand_type_equal (&overlap
, &imm64
))
4609 as_bad (_("no instruction mnemonic suffix given; "
4610 "can't determine immediate size"));
4614 i
.types
[j
] = overlap
;
4624 /* Update the first 2 immediate operands. */
4625 n
= i
.operands
> 2 ? 2 : i
.operands
;
4628 for (j
= 0; j
< n
; j
++)
4629 if (update_imm (j
) == 0)
4632 /* The 3rd operand can't be immediate operand. */
4633 gas_assert (operand_type_check (i
.types
[2], imm
) == 0);
4640 bad_implicit_operand (int xmm
)
4642 const char *reg
= xmm
? "xmm0" : "ymm0";
4644 as_bad (_("the last operand of `%s' must be `%s%s'"),
4645 i
.tm
.name
, register_prefix
, reg
);
4647 as_bad (_("the first operand of `%s' must be `%s%s'"),
4648 i
.tm
.name
, register_prefix
, reg
);
4653 process_operands (void)
4655 /* Default segment register this instruction will use for memory
4656 accesses. 0 means unknown. This is only for optimizing out
4657 unnecessary segment overrides. */
4658 const seg_entry
*default_seg
= 0;
4660 if (i
.tm
.opcode_modifier
.sse2avx
4661 && (i
.tm
.opcode_modifier
.vexnds
4662 || i
.tm
.opcode_modifier
.vexndd
))
4664 unsigned int dup
= i
.operands
;
4665 unsigned int dest
= dup
- 1;
4668 /* The destination must be an xmm register. */
4669 gas_assert (i
.reg_operands
4670 && MAX_OPERANDS
> dup
4671 && operand_type_equal (&i
.types
[dest
], ®xmm
));
4673 if (i
.tm
.opcode_modifier
.firstxmm0
)
4675 /* The first operand is implicit and must be xmm0. */
4676 gas_assert (operand_type_equal (&i
.types
[0], ®xmm
));
4677 if (i
.op
[0].regs
->reg_num
!= 0)
4678 return bad_implicit_operand (1);
4680 if (i
.tm
.opcode_modifier
.vex3sources
)
4682 /* Keep xmm0 for instructions with VEX prefix and 3
4688 /* We remove the first xmm0 and keep the number of
4689 operands unchanged, which in fact duplicates the
4691 for (j
= 1; j
< i
.operands
; j
++)
4693 i
.op
[j
- 1] = i
.op
[j
];
4694 i
.types
[j
- 1] = i
.types
[j
];
4695 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4699 else if (i
.tm
.opcode_modifier
.implicit1stxmm0
)
4701 gas_assert ((MAX_OPERANDS
- 1) > dup
4702 && i
.tm
.opcode_modifier
.vex3sources
);
4704 /* Add the implicit xmm0 for instructions with VEX prefix
4706 for (j
= i
.operands
; j
> 0; j
--)
4708 i
.op
[j
] = i
.op
[j
- 1];
4709 i
.types
[j
] = i
.types
[j
- 1];
4710 i
.tm
.operand_types
[j
] = i
.tm
.operand_types
[j
- 1];
4713 = (const reg_entry
*) hash_find (reg_hash
, "xmm0");
4714 i
.types
[0] = regxmm
;
4715 i
.tm
.operand_types
[0] = regxmm
;
4718 i
.reg_operands
+= 2;
4723 i
.op
[dup
] = i
.op
[dest
];
4724 i
.types
[dup
] = i
.types
[dest
];
4725 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4734 i
.op
[dup
] = i
.op
[dest
];
4735 i
.types
[dup
] = i
.types
[dest
];
4736 i
.tm
.operand_types
[dup
] = i
.tm
.operand_types
[dest
];
4739 if (i
.tm
.opcode_modifier
.immext
)
4742 else if (i
.tm
.opcode_modifier
.firstxmm0
)
4746 /* The first operand is implicit and must be xmm0/ymm0. */
4747 gas_assert (i
.reg_operands
4748 && (operand_type_equal (&i
.types
[0], ®xmm
)
4749 || operand_type_equal (&i
.types
[0], ®ymm
)));
4750 if (i
.op
[0].regs
->reg_num
!= 0)
4751 return bad_implicit_operand (i
.types
[0].bitfield
.regxmm
);
4753 for (j
= 1; j
< i
.operands
; j
++)
4755 i
.op
[j
- 1] = i
.op
[j
];
4756 i
.types
[j
- 1] = i
.types
[j
];
4758 /* We need to adjust fields in i.tm since they are used by
4759 build_modrm_byte. */
4760 i
.tm
.operand_types
[j
- 1] = i
.tm
.operand_types
[j
];
4767 else if (i
.tm
.opcode_modifier
.regkludge
)
4769 /* The imul $imm, %reg instruction is converted into
4770 imul $imm, %reg, %reg, and the clr %reg instruction
4771 is converted into xor %reg, %reg. */
4773 unsigned int first_reg_op
;
4775 if (operand_type_check (i
.types
[0], reg
))
4779 /* Pretend we saw the extra register operand. */
4780 gas_assert (i
.reg_operands
== 1
4781 && i
.op
[first_reg_op
+ 1].regs
== 0);
4782 i
.op
[first_reg_op
+ 1].regs
= i
.op
[first_reg_op
].regs
;
4783 i
.types
[first_reg_op
+ 1] = i
.types
[first_reg_op
];
4788 if (i
.tm
.opcode_modifier
.shortform
)
4790 if (i
.types
[0].bitfield
.sreg2
4791 || i
.types
[0].bitfield
.sreg3
)
4793 if (i
.tm
.base_opcode
== POP_SEG_SHORT
4794 && i
.op
[0].regs
->reg_num
== 1)
4796 as_bad (_("you can't `pop %scs'"), register_prefix
);
4799 i
.tm
.base_opcode
|= (i
.op
[0].regs
->reg_num
<< 3);
4800 if ((i
.op
[0].regs
->reg_flags
& RegRex
) != 0)
4805 /* The register or float register operand is in operand
4809 if (i
.types
[0].bitfield
.floatreg
4810 || operand_type_check (i
.types
[0], reg
))
4814 /* Register goes in low 3 bits of opcode. */
4815 i
.tm
.base_opcode
|= i
.op
[op
].regs
->reg_num
;
4816 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
4818 if (!quiet_warnings
&& i
.tm
.opcode_modifier
.ugh
)
4820 /* Warn about some common errors, but press on regardless.
4821 The first case can be generated by gcc (<= 2.8.1). */
4822 if (i
.operands
== 2)
4824 /* Reversed arguments on faddp, fsubp, etc. */
4825 as_warn (_("translating to `%s %s%s,%s%s'"), i
.tm
.name
,
4826 register_prefix
, i
.op
[!intel_syntax
].regs
->reg_name
,
4827 register_prefix
, i
.op
[intel_syntax
].regs
->reg_name
);
4831 /* Extraneous `l' suffix on fp insn. */
4832 as_warn (_("translating to `%s %s%s'"), i
.tm
.name
,
4833 register_prefix
, i
.op
[0].regs
->reg_name
);
4838 else if (i
.tm
.opcode_modifier
.modrm
)
4840 /* The opcode is completed (modulo i.tm.extension_opcode which
4841 must be put into the modrm byte). Now, we make the modrm and
4842 index base bytes based on all the info we've collected. */
4844 default_seg
= build_modrm_byte ();
4846 else if ((i
.tm
.base_opcode
& ~0x3) == MOV_AX_DISP32
)
4850 else if (i
.tm
.opcode_modifier
.isstring
)
4852 /* For the string instructions that allow a segment override
4853 on one of their operands, the default segment is ds. */
4857 if (i
.tm
.base_opcode
== 0x8d /* lea */
4860 as_warn (_("segment override on `%s' is ineffectual"), i
.tm
.name
);
4862 /* If a segment was explicitly specified, and the specified segment
4863 is not the default, use an opcode prefix to select it. If we
4864 never figured out what the default segment is, then default_seg
4865 will be zero at this point, and the specified segment prefix will
4867 if ((i
.seg
[0]) && (i
.seg
[0] != default_seg
))
4869 if (!add_prefix (i
.seg
[0]->seg_prefix
))
4875 static const seg_entry
*
4876 build_modrm_byte (void)
4878 const seg_entry
*default_seg
= 0;
4879 unsigned int source
, dest
;
4882 /* The first operand of instructions with VEX prefix and 3 sources
4883 must be VEX_Imm4. */
4884 vex_3_sources
= i
.tm
.opcode_modifier
.vex3sources
;
4887 unsigned int nds
, reg
;
4890 if (i
.tm
.opcode_modifier
.veximmext
4891 && i
.tm
.opcode_modifier
.immext
)
4893 dest
= i
.operands
- 2;
4894 gas_assert (dest
== 3);
4897 dest
= i
.operands
- 1;
4900 /* This instruction must have 4 register operands
4901 or 3 register operands plus 1 memory operand.
4902 It must have VexNDS and VexImmExt. */
4903 gas_assert ((i
.reg_operands
== 4
4904 || (i
.reg_operands
== 3 && i
.mem_operands
== 1))
4905 && i
.tm
.opcode_modifier
.vexnds
4906 && i
.tm
.opcode_modifier
.veximmext
4907 && (operand_type_equal (&i
.tm
.operand_types
[dest
], ®xmm
)
4908 || operand_type_equal (&i
.tm
.operand_types
[dest
], ®ymm
)));
4910 /* Generate an 8bit immediate operand to encode the register
4912 exp
= &im_expressions
[i
.imm_operands
++];
4913 i
.op
[i
.operands
].imms
= exp
;
4914 i
.types
[i
.operands
] = imm8
;
4916 /* If VexW1 is set, the first operand is the source and
4917 the second operand is encoded in the immediate operand. */
4918 if (i
.tm
.opcode_modifier
.vexw1
)
4928 gas_assert ((operand_type_equal (&i
.tm
.operand_types
[reg
], ®xmm
)
4929 || operand_type_equal (&i
.tm
.operand_types
[reg
],
4931 && (operand_type_equal (&i
.tm
.operand_types
[nds
], ®xmm
)
4932 || operand_type_equal (&i
.tm
.operand_types
[nds
],
4934 exp
->X_op
= O_constant
;
4936 = ((i
.op
[reg
].regs
->reg_num
4937 + ((i
.op
[reg
].regs
->reg_flags
& RegRex
) ? 8 : 0)) << 4);
4938 i
.vex
.register_specifier
= i
.op
[nds
].regs
;
4943 /* i.reg_operands MUST be the number of real register operands;
4944 implicit registers do not count. If there are 3 register
4945 operands, it must be a instruction with VexNDS. For a
4946 instruction with VexNDD, the destination register is encoded
4947 in VEX prefix. If there are 4 register operands, it must be
4948 a instruction with VEX prefix and 3 sources. */
4949 if (i
.mem_operands
== 0
4950 && ((i
.reg_operands
== 2
4951 && !i
.tm
.opcode_modifier
.vexndd
4952 && !i
.tm
.opcode_modifier
.vexlwp
)
4953 || (i
.reg_operands
== 3
4954 && i
.tm
.opcode_modifier
.vexnds
)
4955 || (i
.reg_operands
== 4 && vex_3_sources
)))
4963 /* When there are 3 operands, one of them may be immediate,
4964 which may be the first or the last operand. Otherwise,
4965 the first operand must be shift count register (cl) or it
4966 is an instruction with VexNDS. */
4967 gas_assert (i
.imm_operands
== 1
4968 || (i
.imm_operands
== 0
4969 && (i
.tm
.opcode_modifier
.vexnds
4970 || i
.types
[0].bitfield
.shiftcount
)));
4971 if (operand_type_check (i
.types
[0], imm
)
4972 || i
.types
[0].bitfield
.shiftcount
)
4978 /* When there are 4 operands, the first two must be 8bit
4979 immediate operands. The source operand will be the 3rd
4982 For instructions with VexNDS, if the first operand
4983 an imm8, the source operand is the 2nd one. If the last
4984 operand is imm8, the source operand is the first one. */
4985 gas_assert ((i
.imm_operands
== 2
4986 && i
.types
[0].bitfield
.imm8
4987 && i
.types
[1].bitfield
.imm8
)
4988 || (i
.tm
.opcode_modifier
.vexnds
4989 && i
.imm_operands
== 1
4990 && (i
.types
[0].bitfield
.imm8
4991 || i
.types
[i
.operands
- 1].bitfield
.imm8
)));
4992 if (i
.tm
.opcode_modifier
.vexnds
)
4994 if (i
.types
[0].bitfield
.imm8
)
5012 if (i
.tm
.opcode_modifier
.vexnds
)
5014 /* For instructions with VexNDS, the register-only
5015 source operand must be XMM or YMM register. It is
5016 encoded in VEX prefix. We need to clear RegMem bit
5017 before calling operand_type_equal. */
5018 i386_operand_type op
= i
.tm
.operand_types
[dest
];
5019 op
.bitfield
.regmem
= 0;
5020 if ((dest
+ 1) >= i
.operands
5021 || (!operand_type_equal (&op
, ®xmm
)
5022 && !operand_type_equal (&op
, ®ymm
)))
5024 i
.vex
.register_specifier
= i
.op
[dest
].regs
;
5030 /* One of the register operands will be encoded in the i.tm.reg
5031 field, the other in the combined i.tm.mode and i.tm.regmem
5032 fields. If no form of this instruction supports a memory
5033 destination operand, then we assume the source operand may
5034 sometimes be a memory operand and so we need to store the
5035 destination in the i.rm.reg field. */
5036 if (!i
.tm
.operand_types
[dest
].bitfield
.regmem
5037 && operand_type_check (i
.tm
.operand_types
[dest
], anymem
) == 0)
5039 i
.rm
.reg
= i
.op
[dest
].regs
->reg_num
;
5040 i
.rm
.regmem
= i
.op
[source
].regs
->reg_num
;
5041 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5043 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5048 i
.rm
.reg
= i
.op
[source
].regs
->reg_num
;
5049 i
.rm
.regmem
= i
.op
[dest
].regs
->reg_num
;
5050 if ((i
.op
[dest
].regs
->reg_flags
& RegRex
) != 0)
5052 if ((i
.op
[source
].regs
->reg_flags
& RegRex
) != 0)
5055 if (flag_code
!= CODE_64BIT
&& (i
.rex
& (REX_R
| REX_B
)))
5057 if (!i
.types
[0].bitfield
.control
5058 && !i
.types
[1].bitfield
.control
)
5060 i
.rex
&= ~(REX_R
| REX_B
);
5061 add_prefix (LOCK_PREFIX_OPCODE
);
5065 { /* If it's not 2 reg operands... */
5070 unsigned int fake_zero_displacement
= 0;
5073 for (op
= 0; op
< i
.operands
; op
++)
5074 if (operand_type_check (i
.types
[op
], anymem
))
5076 gas_assert (op
< i
.operands
);
5080 if (i
.base_reg
== 0)
5083 if (!i
.disp_operands
)
5084 fake_zero_displacement
= 1;
5085 if (i
.index_reg
== 0)
5087 /* Operand is just <disp> */
5088 if (flag_code
== CODE_64BIT
)
5090 /* 64bit mode overwrites the 32bit absolute
5091 addressing by RIP relative addressing and
5092 absolute addressing is encoded by one of the
5093 redundant SIB forms. */
5094 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5095 i
.sib
.base
= NO_BASE_REGISTER
;
5096 i
.sib
.index
= NO_INDEX_REGISTER
;
5097 i
.types
[op
] = ((i
.prefix
[ADDR_PREFIX
] == 0)
5098 ? disp32s
: disp32
);
5100 else if ((flag_code
== CODE_16BIT
)
5101 ^ (i
.prefix
[ADDR_PREFIX
] != 0))
5103 i
.rm
.regmem
= NO_BASE_REGISTER_16
;
5104 i
.types
[op
] = disp16
;
5108 i
.rm
.regmem
= NO_BASE_REGISTER
;
5109 i
.types
[op
] = disp32
;
5112 else /* !i.base_reg && i.index_reg */
5114 if (i
.index_reg
->reg_num
== RegEiz
5115 || i
.index_reg
->reg_num
== RegRiz
)
5116 i
.sib
.index
= NO_INDEX_REGISTER
;
5118 i
.sib
.index
= i
.index_reg
->reg_num
;
5119 i
.sib
.base
= NO_BASE_REGISTER
;
5120 i
.sib
.scale
= i
.log2_scale_factor
;
5121 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5122 i
.types
[op
].bitfield
.disp8
= 0;
5123 i
.types
[op
].bitfield
.disp16
= 0;
5124 i
.types
[op
].bitfield
.disp64
= 0;
5125 if (flag_code
!= CODE_64BIT
)
5127 /* Must be 32 bit */
5128 i
.types
[op
].bitfield
.disp32
= 1;
5129 i
.types
[op
].bitfield
.disp32s
= 0;
5133 i
.types
[op
].bitfield
.disp32
= 0;
5134 i
.types
[op
].bitfield
.disp32s
= 1;
5136 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5140 /* RIP addressing for 64bit mode. */
5141 else if (i
.base_reg
->reg_num
== RegRip
||
5142 i
.base_reg
->reg_num
== RegEip
)
5144 i
.rm
.regmem
= NO_BASE_REGISTER
;
5145 i
.types
[op
].bitfield
.disp8
= 0;
5146 i
.types
[op
].bitfield
.disp16
= 0;
5147 i
.types
[op
].bitfield
.disp32
= 0;
5148 i
.types
[op
].bitfield
.disp32s
= 1;
5149 i
.types
[op
].bitfield
.disp64
= 0;
5150 i
.flags
[op
] |= Operand_PCrel
;
5151 if (! i
.disp_operands
)
5152 fake_zero_displacement
= 1;
5154 else if (i
.base_reg
->reg_type
.bitfield
.reg16
)
5156 switch (i
.base_reg
->reg_num
)
5159 if (i
.index_reg
== 0)
5161 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
5162 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6;
5166 if (i
.index_reg
== 0)
5169 if (operand_type_check (i
.types
[op
], disp
) == 0)
5171 /* fake (%bp) into 0(%bp) */
5172 i
.types
[op
].bitfield
.disp8
= 1;
5173 fake_zero_displacement
= 1;
5176 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
5177 i
.rm
.regmem
= i
.index_reg
->reg_num
- 6 + 2;
5179 default: /* (%si) -> 4 or (%di) -> 5 */
5180 i
.rm
.regmem
= i
.base_reg
->reg_num
- 6 + 4;
5182 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5184 else /* i.base_reg and 32/64 bit mode */
5186 if (flag_code
== CODE_64BIT
5187 && operand_type_check (i
.types
[op
], disp
))
5189 i386_operand_type temp
;
5190 operand_type_set (&temp
, 0);
5191 temp
.bitfield
.disp8
= i
.types
[op
].bitfield
.disp8
;
5193 if (i
.prefix
[ADDR_PREFIX
] == 0)
5194 i
.types
[op
].bitfield
.disp32s
= 1;
5196 i
.types
[op
].bitfield
.disp32
= 1;
5199 i
.rm
.regmem
= i
.base_reg
->reg_num
;
5200 if ((i
.base_reg
->reg_flags
& RegRex
) != 0)
5202 i
.sib
.base
= i
.base_reg
->reg_num
;
5203 /* x86-64 ignores REX prefix bit here to avoid decoder
5205 if ((i
.base_reg
->reg_num
& 7) == EBP_REG_NUM
)
5208 if (i
.disp_operands
== 0)
5210 fake_zero_displacement
= 1;
5211 i
.types
[op
].bitfield
.disp8
= 1;
5214 else if (i
.base_reg
->reg_num
== ESP_REG_NUM
)
5218 i
.sib
.scale
= i
.log2_scale_factor
;
5219 if (i
.index_reg
== 0)
5221 /* <disp>(%esp) becomes two byte modrm with no index
5222 register. We've already stored the code for esp
5223 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
5224 Any base register besides %esp will not use the
5225 extra modrm byte. */
5226 i
.sib
.index
= NO_INDEX_REGISTER
;
5230 if (i
.index_reg
->reg_num
== RegEiz
5231 || i
.index_reg
->reg_num
== RegRiz
)
5232 i
.sib
.index
= NO_INDEX_REGISTER
;
5234 i
.sib
.index
= i
.index_reg
->reg_num
;
5235 i
.rm
.regmem
= ESCAPE_TO_TWO_BYTE_ADDRESSING
;
5236 if ((i
.index_reg
->reg_flags
& RegRex
) != 0)
5241 && (i
.reloc
[op
] == BFD_RELOC_386_TLS_DESC_CALL
5242 || i
.reloc
[op
] == BFD_RELOC_X86_64_TLSDESC_CALL
))
5245 i
.rm
.mode
= mode_from_disp_size (i
.types
[op
]);
5248 if (fake_zero_displacement
)
5250 /* Fakes a zero displacement assuming that i.types[op]
5251 holds the correct displacement size. */
5254 gas_assert (i
.op
[op
].disps
== 0);
5255 exp
= &disp_expressions
[i
.disp_operands
++];
5256 i
.op
[op
].disps
= exp
;
5257 exp
->X_op
= O_constant
;
5258 exp
->X_add_number
= 0;
5259 exp
->X_add_symbol
= (symbolS
*) 0;
5260 exp
->X_op_symbol
= (symbolS
*) 0;
5268 if (i
.tm
.opcode_modifier
.vexlwp
)
5270 i
.vex
.register_specifier
= i
.op
[2].regs
;
5271 if (!i
.mem_operands
)
5274 i
.rm
.regmem
= i
.op
[1].regs
->reg_num
;
5275 if ((i
.op
[1].regs
->reg_flags
& RegRex
) != 0)
5279 /* Fill in i.rm.reg or i.rm.regmem field with register operand
5280 (if any) based on i.tm.extension_opcode. Again, we must be
5281 careful to make sure that segment/control/debug/test/MMX
5282 registers are coded into the i.rm.reg field. */
5283 else if (i
.reg_operands
)
5286 unsigned int vex_reg
= ~0;
5288 for (op
= 0; op
< i
.operands
; op
++)
5289 if (i
.types
[op
].bitfield
.reg8
5290 || i
.types
[op
].bitfield
.reg16
5291 || i
.types
[op
].bitfield
.reg32
5292 || i
.types
[op
].bitfield
.reg64
5293 || i
.types
[op
].bitfield
.regmmx
5294 || i
.types
[op
].bitfield
.regxmm
5295 || i
.types
[op
].bitfield
.regymm
5296 || i
.types
[op
].bitfield
.sreg2
5297 || i
.types
[op
].bitfield
.sreg3
5298 || i
.types
[op
].bitfield
.control
5299 || i
.types
[op
].bitfield
.debug
5300 || i
.types
[op
].bitfield
.test
)
5305 else if (i
.tm
.opcode_modifier
.vexnds
)
5307 /* For instructions with VexNDS, the register-only
5308 source operand is encoded in VEX prefix. */
5309 gas_assert (mem
!= (unsigned int) ~0);
5314 gas_assert (op
< i
.operands
);
5319 gas_assert (vex_reg
< i
.operands
);
5322 else if (i
.tm
.opcode_modifier
.vexndd
)
5324 /* For instructions with VexNDD, there should be
5325 no memory operand and the register destination
5326 is encoded in VEX prefix. */
5327 gas_assert (i
.mem_operands
== 0
5328 && (op
+ 2) == i
.operands
);
5332 gas_assert (op
< i
.operands
);
5334 if (vex_reg
!= (unsigned int) ~0)
5336 gas_assert (i
.reg_operands
== 2);
5338 if (!operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5340 && !operand_type_equal (&i
.tm
.operand_types
[vex_reg
],
5344 i
.vex
.register_specifier
= i
.op
[vex_reg
].regs
;
5347 /* If there is an extension opcode to put here, the
5348 register number must be put into the regmem field. */
5349 if (i
.tm
.extension_opcode
!= None
)
5351 i
.rm
.regmem
= i
.op
[op
].regs
->reg_num
;
5352 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5357 i
.rm
.reg
= i
.op
[op
].regs
->reg_num
;
5358 if ((i
.op
[op
].regs
->reg_flags
& RegRex
) != 0)
5362 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
5363 must set it to 3 to indicate this is a register operand
5364 in the regmem field. */
5365 if (!i
.mem_operands
)
5369 /* Fill in i.rm.reg field with extension opcode (if any). */
5370 if (i
.tm
.extension_opcode
!= None
)
5371 i
.rm
.reg
= i
.tm
.extension_opcode
;
5377 output_branch (void)
5382 relax_substateT subtype
;
5387 if (flag_code
== CODE_16BIT
)
5391 if (i
.prefix
[DATA_PREFIX
] != 0)
5397 /* Pentium4 branch hints. */
5398 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5399 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5404 if (i
.prefix
[REX_PREFIX
] != 0)
5410 if (i
.prefixes
!= 0 && !intel_syntax
)
5411 as_warn (_("skipping prefixes on this instruction"));
5413 /* It's always a symbol; End frag & setup for relax.
5414 Make sure there is enough room in this frag for the largest
5415 instruction we may generate in md_convert_frag. This is 2
5416 bytes for the opcode and room for the prefix and largest
5418 frag_grow (prefix
+ 2 + 4);
5419 /* Prefix and 1 opcode byte go in fr_fix. */
5420 p
= frag_more (prefix
+ 1);
5421 if (i
.prefix
[DATA_PREFIX
] != 0)
5422 *p
++ = DATA_PREFIX_OPCODE
;
5423 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
5424 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
)
5425 *p
++ = i
.prefix
[SEG_PREFIX
];
5426 if (i
.prefix
[REX_PREFIX
] != 0)
5427 *p
++ = i
.prefix
[REX_PREFIX
];
5428 *p
= i
.tm
.base_opcode
;
5430 if ((unsigned char) *p
== JUMP_PC_RELATIVE
)
5431 subtype
= ENCODE_RELAX_STATE (UNCOND_JUMP
, SMALL
);
5432 else if (cpu_arch_flags
.bitfield
.cpui386
)
5433 subtype
= ENCODE_RELAX_STATE (COND_JUMP
, SMALL
);
5435 subtype
= ENCODE_RELAX_STATE (COND_JUMP86
, SMALL
);
5438 sym
= i
.op
[0].disps
->X_add_symbol
;
5439 off
= i
.op
[0].disps
->X_add_number
;
5441 if (i
.op
[0].disps
->X_op
!= O_constant
5442 && i
.op
[0].disps
->X_op
!= O_symbol
)
5444 /* Handle complex expressions. */
5445 sym
= make_expr_symbol (i
.op
[0].disps
);
5449 /* 1 possible extra opcode + 4 byte displacement go in var part.
5450 Pass reloc in fr_var. */
5451 frag_var (rs_machine_dependent
, 5, i
.reloc
[0], subtype
, sym
, off
, p
);
5461 if (i
.tm
.opcode_modifier
.jumpbyte
)
5463 /* This is a loop or jecxz type instruction. */
5465 if (i
.prefix
[ADDR_PREFIX
] != 0)
5467 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE
);
5470 /* Pentium4 branch hints. */
5471 if (i
.prefix
[SEG_PREFIX
] == CS_PREFIX_OPCODE
/* not taken */
5472 || i
.prefix
[SEG_PREFIX
] == DS_PREFIX_OPCODE
/* taken */)
5474 FRAG_APPEND_1_CHAR (i
.prefix
[SEG_PREFIX
]);
5483 if (flag_code
== CODE_16BIT
)
5486 if (i
.prefix
[DATA_PREFIX
] != 0)
5488 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE
);
5498 if (i
.prefix
[REX_PREFIX
] != 0)
5500 FRAG_APPEND_1_CHAR (i
.prefix
[REX_PREFIX
]);
5504 if (i
.prefixes
!= 0 && !intel_syntax
)
5505 as_warn (_("skipping prefixes on this instruction"));
5507 p
= frag_more (1 + size
);
5508 *p
++ = i
.tm
.base_opcode
;
5510 fixP
= fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5511 i
.op
[0].disps
, 1, reloc (size
, 1, 1, i
.reloc
[0]));
5513 /* All jumps handled here are signed, but don't use a signed limit
5514 check for 32 and 16 bit jumps as we want to allow wrap around at
5515 4G and 64k respectively. */
5517 fixP
->fx_signed
= 1;
5521 output_interseg_jump (void)
5529 if (flag_code
== CODE_16BIT
)
5533 if (i
.prefix
[DATA_PREFIX
] != 0)
5539 if (i
.prefix
[REX_PREFIX
] != 0)
5549 if (i
.prefixes
!= 0 && !intel_syntax
)
5550 as_warn (_("skipping prefixes on this instruction"));
5552 /* 1 opcode; 2 segment; offset */
5553 p
= frag_more (prefix
+ 1 + 2 + size
);
5555 if (i
.prefix
[DATA_PREFIX
] != 0)
5556 *p
++ = DATA_PREFIX_OPCODE
;
5558 if (i
.prefix
[REX_PREFIX
] != 0)
5559 *p
++ = i
.prefix
[REX_PREFIX
];
5561 *p
++ = i
.tm
.base_opcode
;
5562 if (i
.op
[1].imms
->X_op
== O_constant
)
5564 offsetT n
= i
.op
[1].imms
->X_add_number
;
5567 && !fits_in_unsigned_word (n
)
5568 && !fits_in_signed_word (n
))
5570 as_bad (_("16-bit jump out of range"));
5573 md_number_to_chars (p
, n
, size
);
5576 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5577 i
.op
[1].imms
, 0, reloc (size
, 0, 0, i
.reloc
[1]));
5578 if (i
.op
[0].imms
->X_op
!= O_constant
)
5579 as_bad (_("can't handle non absolute segment in `%s'"),
5581 md_number_to_chars (p
+ size
, (valueT
) i
.op
[0].imms
->X_add_number
, 2);
5587 fragS
*insn_start_frag
;
5588 offsetT insn_start_off
;
5590 /* Tie dwarf2 debug info to the address at the start of the insn.
5591 We can't do this after the insn has been output as the current
5592 frag may have been closed off. eg. by frag_var. */
5593 dwarf2_emit_insn (0);
5595 insn_start_frag
= frag_now
;
5596 insn_start_off
= frag_now_fix ();
5599 if (i
.tm
.opcode_modifier
.jump
)
5601 else if (i
.tm
.opcode_modifier
.jumpbyte
5602 || i
.tm
.opcode_modifier
.jumpdword
)
5604 else if (i
.tm
.opcode_modifier
.jumpintersegment
)
5605 output_interseg_jump ();
5608 /* Output normal instructions here. */
5612 unsigned int prefix
;
5614 /* Since the VEX prefix contains the implicit prefix, we don't
5615 need the explicit prefix. */
5616 if (!i
.tm
.opcode_modifier
.vex
)
5618 switch (i
.tm
.opcode_length
)
5621 if (i
.tm
.base_opcode
& 0xff000000)
5623 prefix
= (i
.tm
.base_opcode
>> 24) & 0xff;
5628 if ((i
.tm
.base_opcode
& 0xff0000) != 0)
5630 prefix
= (i
.tm
.base_opcode
>> 16) & 0xff;
5631 if (i
.tm
.cpu_flags
.bitfield
.cpupadlock
)
5634 if (prefix
!= REPE_PREFIX_OPCODE
5635 || (i
.prefix
[LOCKREP_PREFIX
]
5636 != REPE_PREFIX_OPCODE
))
5637 add_prefix (prefix
);
5640 add_prefix (prefix
);
5649 /* The prefix bytes. */
5650 for (j
= ARRAY_SIZE (i
.prefix
), q
= i
.prefix
; j
> 0; j
--, q
++)
5652 FRAG_APPEND_1_CHAR (*q
);
5655 if (i
.tm
.opcode_modifier
.vex
)
5657 for (j
= 0, q
= i
.prefix
; j
< ARRAY_SIZE (i
.prefix
); j
++, q
++)
5662 /* REX byte is encoded in VEX prefix. */
5666 FRAG_APPEND_1_CHAR (*q
);
5669 /* There should be no other prefixes for instructions
5674 /* Now the VEX prefix. */
5675 p
= frag_more (i
.vex
.length
);
5676 for (j
= 0; j
< i
.vex
.length
; j
++)
5677 p
[j
] = i
.vex
.bytes
[j
];
5680 /* Now the opcode; be careful about word order here! */
5681 if (i
.tm
.opcode_length
== 1)
5683 FRAG_APPEND_1_CHAR (i
.tm
.base_opcode
);
5687 switch (i
.tm
.opcode_length
)
5691 *p
++ = (i
.tm
.base_opcode
>> 16) & 0xff;
5701 /* Put out high byte first: can't use md_number_to_chars! */
5702 *p
++ = (i
.tm
.base_opcode
>> 8) & 0xff;
5703 *p
= i
.tm
.base_opcode
& 0xff;
5706 /* Now the modrm byte and sib byte (if present). */
5707 if (i
.tm
.opcode_modifier
.modrm
)
5709 FRAG_APPEND_1_CHAR ((i
.rm
.regmem
<< 0
5712 /* If i.rm.regmem == ESP (4)
5713 && i.rm.mode != (Register mode)
5715 ==> need second modrm byte. */
5716 if (i
.rm
.regmem
== ESCAPE_TO_TWO_BYTE_ADDRESSING
5718 && !(i
.base_reg
&& i
.base_reg
->reg_type
.bitfield
.reg16
))
5719 FRAG_APPEND_1_CHAR ((i
.sib
.base
<< 0
5721 | i
.sib
.scale
<< 6));
5724 if (i
.disp_operands
)
5725 output_disp (insn_start_frag
, insn_start_off
);
5728 output_imm (insn_start_frag
, insn_start_off
);
5734 pi ("" /*line*/, &i
);
5736 #endif /* DEBUG386 */
5739 /* Return the size of the displacement operand N. */
5742 disp_size (unsigned int n
)
5745 if (i
.types
[n
].bitfield
.disp64
)
5747 else if (i
.types
[n
].bitfield
.disp8
)
5749 else if (i
.types
[n
].bitfield
.disp16
)
5754 /* Return the size of the immediate operand N. */
5757 imm_size (unsigned int n
)
5760 if (i
.types
[n
].bitfield
.imm64
)
5762 else if (i
.types
[n
].bitfield
.imm8
|| i
.types
[n
].bitfield
.imm8s
)
5764 else if (i
.types
[n
].bitfield
.imm16
)
5770 output_disp (fragS
*insn_start_frag
, offsetT insn_start_off
)
5775 for (n
= 0; n
< i
.operands
; n
++)
5777 if (operand_type_check (i
.types
[n
], disp
))
5779 if (i
.op
[n
].disps
->X_op
== O_constant
)
5781 int size
= disp_size (n
);
5784 val
= offset_in_range (i
.op
[n
].disps
->X_add_number
,
5786 p
= frag_more (size
);
5787 md_number_to_chars (p
, val
, size
);
5791 enum bfd_reloc_code_real reloc_type
;
5792 int size
= disp_size (n
);
5793 int sign
= i
.types
[n
].bitfield
.disp32s
;
5794 int pcrel
= (i
.flags
[n
] & Operand_PCrel
) != 0;
5796 /* We can't have 8 bit displacement here. */
5797 gas_assert (!i
.types
[n
].bitfield
.disp8
);
5799 /* The PC relative address is computed relative
5800 to the instruction boundary, so in case immediate
5801 fields follows, we need to adjust the value. */
5802 if (pcrel
&& i
.imm_operands
)
5807 for (n1
= 0; n1
< i
.operands
; n1
++)
5808 if (operand_type_check (i
.types
[n1
], imm
))
5810 /* Only one immediate is allowed for PC
5811 relative address. */
5812 gas_assert (sz
== 0);
5814 i
.op
[n
].disps
->X_add_number
-= sz
;
5816 /* We should find the immediate. */
5817 gas_assert (sz
!= 0);
5820 p
= frag_more (size
);
5821 reloc_type
= reloc (size
, pcrel
, sign
, i
.reloc
[n
]);
5823 && GOT_symbol
== i
.op
[n
].disps
->X_add_symbol
5824 && (((reloc_type
== BFD_RELOC_32
5825 || reloc_type
== BFD_RELOC_X86_64_32S
5826 || (reloc_type
== BFD_RELOC_64
5828 && (i
.op
[n
].disps
->X_op
== O_symbol
5829 || (i
.op
[n
].disps
->X_op
== O_add
5830 && ((symbol_get_value_expression
5831 (i
.op
[n
].disps
->X_op_symbol
)->X_op
)
5833 || reloc_type
== BFD_RELOC_32_PCREL
))
5837 if (insn_start_frag
== frag_now
)
5838 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5843 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5844 for (fr
= insn_start_frag
->fr_next
;
5845 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5847 add
+= p
- frag_now
->fr_literal
;
5852 reloc_type
= BFD_RELOC_386_GOTPC
;
5853 i
.op
[n
].imms
->X_add_number
+= add
;
5855 else if (reloc_type
== BFD_RELOC_64
)
5856 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5858 /* Don't do the adjustment for x86-64, as there
5859 the pcrel addressing is relative to the _next_
5860 insn, and that is taken care of in other code. */
5861 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5863 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5864 i
.op
[n
].disps
, pcrel
, reloc_type
);
5871 output_imm (fragS
*insn_start_frag
, offsetT insn_start_off
)
5876 for (n
= 0; n
< i
.operands
; n
++)
5878 if (operand_type_check (i
.types
[n
], imm
))
5880 if (i
.op
[n
].imms
->X_op
== O_constant
)
5882 int size
= imm_size (n
);
5885 val
= offset_in_range (i
.op
[n
].imms
->X_add_number
,
5887 p
= frag_more (size
);
5888 md_number_to_chars (p
, val
, size
);
5892 /* Not absolute_section.
5893 Need a 32-bit fixup (don't support 8bit
5894 non-absolute imms). Try to support other
5896 enum bfd_reloc_code_real reloc_type
;
5897 int size
= imm_size (n
);
5900 if (i
.types
[n
].bitfield
.imm32s
5901 && (i
.suffix
== QWORD_MNEM_SUFFIX
5902 || (!i
.suffix
&& i
.tm
.opcode_modifier
.no_lsuf
)))
5907 p
= frag_more (size
);
5908 reloc_type
= reloc (size
, 0, sign
, i
.reloc
[n
]);
5910 /* This is tough to explain. We end up with this one if we
5911 * have operands that look like
5912 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
5913 * obtain the absolute address of the GOT, and it is strongly
5914 * preferable from a performance point of view to avoid using
5915 * a runtime relocation for this. The actual sequence of
5916 * instructions often look something like:
5921 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
5923 * The call and pop essentially return the absolute address
5924 * of the label .L66 and store it in %ebx. The linker itself
5925 * will ultimately change the first operand of the addl so
5926 * that %ebx points to the GOT, but to keep things simple, the
5927 * .o file must have this operand set so that it generates not
5928 * the absolute address of .L66, but the absolute address of
5929 * itself. This allows the linker itself simply treat a GOTPC
5930 * relocation as asking for a pcrel offset to the GOT to be
5931 * added in, and the addend of the relocation is stored in the
5932 * operand field for the instruction itself.
5934 * Our job here is to fix the operand so that it would add
5935 * the correct offset so that %ebx would point to itself. The
5936 * thing that is tricky is that .-.L66 will point to the
5937 * beginning of the instruction, so we need to further modify
5938 * the operand so that it will point to itself. There are
5939 * other cases where you have something like:
5941 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
5943 * and here no correction would be required. Internally in
5944 * the assembler we treat operands of this form as not being
5945 * pcrel since the '.' is explicitly mentioned, and I wonder
5946 * whether it would simplify matters to do it this way. Who
5947 * knows. In earlier versions of the PIC patches, the
5948 * pcrel_adjust field was used to store the correction, but
5949 * since the expression is not pcrel, I felt it would be
5950 * confusing to do it this way. */
5952 if ((reloc_type
== BFD_RELOC_32
5953 || reloc_type
== BFD_RELOC_X86_64_32S
5954 || reloc_type
== BFD_RELOC_64
)
5956 && GOT_symbol
== i
.op
[n
].imms
->X_add_symbol
5957 && (i
.op
[n
].imms
->X_op
== O_symbol
5958 || (i
.op
[n
].imms
->X_op
== O_add
5959 && ((symbol_get_value_expression
5960 (i
.op
[n
].imms
->X_op_symbol
)->X_op
)
5965 if (insn_start_frag
== frag_now
)
5966 add
= (p
- frag_now
->fr_literal
) - insn_start_off
;
5971 add
= insn_start_frag
->fr_fix
- insn_start_off
;
5972 for (fr
= insn_start_frag
->fr_next
;
5973 fr
&& fr
!= frag_now
; fr
= fr
->fr_next
)
5975 add
+= p
- frag_now
->fr_literal
;
5979 reloc_type
= BFD_RELOC_386_GOTPC
;
5981 reloc_type
= BFD_RELOC_X86_64_GOTPC32
;
5983 reloc_type
= BFD_RELOC_X86_64_GOTPC64
;
5984 i
.op
[n
].imms
->X_add_number
+= add
;
5986 fix_new_exp (frag_now
, p
- frag_now
->fr_literal
, size
,
5987 i
.op
[n
].imms
, 0, reloc_type
);
5993 /* x86_cons_fix_new is called via the expression parsing code when a
5994 reloc is needed. We use this hook to get the correct .got reloc. */
5995 static enum bfd_reloc_code_real got_reloc
= NO_RELOC
;
5996 static int cons_sign
= -1;
5999 x86_cons_fix_new (fragS
*frag
, unsigned int off
, unsigned int len
,
6002 enum bfd_reloc_code_real r
= reloc (len
, 0, cons_sign
, got_reloc
);
6004 got_reloc
= NO_RELOC
;
6007 if (exp
->X_op
== O_secrel
)
6009 exp
->X_op
= O_symbol
;
6010 r
= BFD_RELOC_32_SECREL
;
6014 fix_new_exp (frag
, off
, len
, exp
, 0, r
);
6017 #if (!defined (OBJ_ELF) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT)
6018 # define lex_got(reloc, adjust, types) NULL
6020 /* Parse operands of the form
6021 <symbol>@GOTOFF+<nnn>
6022 and similar .plt or .got references.
6024 If we find one, set up the correct relocation in RELOC and copy the
6025 input string, minus the `@GOTOFF' into a malloc'd buffer for
6026 parsing by the calling routine. Return this buffer, and if ADJUST
6027 is non-null set it to the length of the string we removed from the
6028 input line. Otherwise return NULL. */
6030 lex_got (enum bfd_reloc_code_real
*reloc
,
6032 i386_operand_type
*types
)
6034 /* Some of the relocations depend on the size of what field is to
6035 be relocated. But in our callers i386_immediate and i386_displacement
6036 we don't yet know the operand size (this will be set by insn
6037 matching). Hence we record the word32 relocation here,
6038 and adjust the reloc according to the real size in reloc(). */
6039 static const struct {
6041 const enum bfd_reloc_code_real rel
[2];
6042 const i386_operand_type types64
;
6044 { "PLTOFF", { _dummy_first_bfd_reloc_code_real
,
6045 BFD_RELOC_X86_64_PLTOFF64
},
6046 OPERAND_TYPE_IMM64
},
6047 { "PLT", { BFD_RELOC_386_PLT32
,
6048 BFD_RELOC_X86_64_PLT32
},
6049 OPERAND_TYPE_IMM32_32S_DISP32
},
6050 { "GOTPLT", { _dummy_first_bfd_reloc_code_real
,
6051 BFD_RELOC_X86_64_GOTPLT64
},
6052 OPERAND_TYPE_IMM64_DISP64
},
6053 { "GOTOFF", { BFD_RELOC_386_GOTOFF
,
6054 BFD_RELOC_X86_64_GOTOFF64
},
6055 OPERAND_TYPE_IMM64_DISP64
},
6056 { "GOTPCREL", { _dummy_first_bfd_reloc_code_real
,
6057 BFD_RELOC_X86_64_GOTPCREL
},
6058 OPERAND_TYPE_IMM32_32S_DISP32
},
6059 { "TLSGD", { BFD_RELOC_386_TLS_GD
,
6060 BFD_RELOC_X86_64_TLSGD
},
6061 OPERAND_TYPE_IMM32_32S_DISP32
},
6062 { "TLSLDM", { BFD_RELOC_386_TLS_LDM
,
6063 _dummy_first_bfd_reloc_code_real
},
6064 OPERAND_TYPE_NONE
},
6065 { "TLSLD", { _dummy_first_bfd_reloc_code_real
,
6066 BFD_RELOC_X86_64_TLSLD
},
6067 OPERAND_TYPE_IMM32_32S_DISP32
},
6068 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32
,
6069 BFD_RELOC_X86_64_GOTTPOFF
},
6070 OPERAND_TYPE_IMM32_32S_DISP32
},
6071 { "TPOFF", { BFD_RELOC_386_TLS_LE_32
,
6072 BFD_RELOC_X86_64_TPOFF32
},
6073 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6074 { "NTPOFF", { BFD_RELOC_386_TLS_LE
,
6075 _dummy_first_bfd_reloc_code_real
},
6076 OPERAND_TYPE_NONE
},
6077 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32
,
6078 BFD_RELOC_X86_64_DTPOFF32
},
6080 OPERAND_TYPE_IMM32_32S_64_DISP32_64
},
6081 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE
,
6082 _dummy_first_bfd_reloc_code_real
},
6083 OPERAND_TYPE_NONE
},
6084 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE
,
6085 _dummy_first_bfd_reloc_code_real
},
6086 OPERAND_TYPE_NONE
},
6087 { "GOT", { BFD_RELOC_386_GOT32
,
6088 BFD_RELOC_X86_64_GOT32
},
6089 OPERAND_TYPE_IMM32_32S_64_DISP32
},
6090 { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC
,
6091 BFD_RELOC_X86_64_GOTPC32_TLSDESC
},
6092 OPERAND_TYPE_IMM32_32S_DISP32
},
6093 { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL
,
6094 BFD_RELOC_X86_64_TLSDESC_CALL
},
6095 OPERAND_TYPE_IMM32_32S_DISP32
},
6103 for (cp
= input_line_pointer
; *cp
!= '@'; cp
++)
6104 if (is_end_of_line
[(unsigned char) *cp
] || *cp
== ',')
6107 for (j
= 0; j
< ARRAY_SIZE (gotrel
); j
++)
6111 len
= strlen (gotrel
[j
].str
);
6112 if (strncasecmp (cp
+ 1, gotrel
[j
].str
, len
) == 0)
6114 if (gotrel
[j
].rel
[object_64bit
] != 0)
6117 char *tmpbuf
, *past_reloc
;
6119 *reloc
= gotrel
[j
].rel
[object_64bit
];
6125 if (flag_code
!= CODE_64BIT
)
6127 types
->bitfield
.imm32
= 1;
6128 types
->bitfield
.disp32
= 1;
6131 *types
= gotrel
[j
].types64
;
6134 if (GOT_symbol
== NULL
)
6135 GOT_symbol
= symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME
);
6137 /* The length of the first part of our input line. */
6138 first
= cp
- input_line_pointer
;
6140 /* The second part goes from after the reloc token until
6141 (and including) an end_of_line char or comma. */
6142 past_reloc
= cp
+ 1 + len
;
6144 while (!is_end_of_line
[(unsigned char) *cp
] && *cp
!= ',')
6146 second
= cp
+ 1 - past_reloc
;
6148 /* Allocate and copy string. The trailing NUL shouldn't
6149 be necessary, but be safe. */
6150 tmpbuf
= (char *) xmalloc (first
+ second
+ 2);
6151 memcpy (tmpbuf
, input_line_pointer
, first
);
6152 if (second
!= 0 && *past_reloc
!= ' ')
6153 /* Replace the relocation token with ' ', so that
6154 errors like foo@GOTOFF1 will be detected. */
6155 tmpbuf
[first
++] = ' ';
6156 memcpy (tmpbuf
+ first
, past_reloc
, second
);
6157 tmpbuf
[first
+ second
] = '\0';
6161 as_bad (_("@%s reloc is not supported with %d-bit output format"),
6162 gotrel
[j
].str
, 1 << (5 + object_64bit
));
6167 /* Might be a symbol version string. Don't as_bad here. */
6172 x86_cons (expressionS
*exp
, int size
)
6174 intel_syntax
= -intel_syntax
;
6176 if (size
== 4 || (object_64bit
&& size
== 8))
6178 /* Handle @GOTOFF and the like in an expression. */
6180 char *gotfree_input_line
;
6183 save
= input_line_pointer
;
6184 gotfree_input_line
= lex_got (&got_reloc
, &adjust
, NULL
);
6185 if (gotfree_input_line
)
6186 input_line_pointer
= gotfree_input_line
;
6190 if (gotfree_input_line
)
6192 /* expression () has merrily parsed up to the end of line,
6193 or a comma - in the wrong buffer. Transfer how far
6194 input_line_pointer has moved to the right buffer. */
6195 input_line_pointer
= (save
6196 + (input_line_pointer
- gotfree_input_line
)
6198 free (gotfree_input_line
);
6199 if (exp
->X_op
== O_constant
6200 || exp
->X_op
== O_absent
6201 || exp
->X_op
== O_illegal
6202 || exp
->X_op
== O_register
6203 || exp
->X_op
== O_big
)
6205 char c
= *input_line_pointer
;
6206 *input_line_pointer
= 0;
6207 as_bad (_("missing or invalid expression `%s'"), save
);
6208 *input_line_pointer
= c
;
6215 intel_syntax
= -intel_syntax
;
6218 i386_intel_simplify (exp
);
6223 signed_cons (int size
)
6225 if (flag_code
== CODE_64BIT
)
6233 pe_directive_secrel (dummy
)
6234 int dummy ATTRIBUTE_UNUSED
;
6241 if (exp
.X_op
== O_symbol
)
6242 exp
.X_op
= O_secrel
;
6244 emit_expr (&exp
, 4);
6246 while (*input_line_pointer
++ == ',');
6248 input_line_pointer
--;
6249 demand_empty_rest_of_line ();
6254 i386_immediate (char *imm_start
)
6256 char *save_input_line_pointer
;
6257 char *gotfree_input_line
;
6260 i386_operand_type types
;
6262 operand_type_set (&types
, ~0);
6264 if (i
.imm_operands
== MAX_IMMEDIATE_OPERANDS
)
6266 as_bad (_("at most %d immediate operands are allowed"),
6267 MAX_IMMEDIATE_OPERANDS
);
6271 exp
= &im_expressions
[i
.imm_operands
++];
6272 i
.op
[this_operand
].imms
= exp
;
6274 if (is_space_char (*imm_start
))
6277 save_input_line_pointer
= input_line_pointer
;
6278 input_line_pointer
= imm_start
;
6280 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6281 if (gotfree_input_line
)
6282 input_line_pointer
= gotfree_input_line
;
6284 exp_seg
= expression (exp
);
6287 if (*input_line_pointer
)
6288 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6290 input_line_pointer
= save_input_line_pointer
;
6291 if (gotfree_input_line
)
6293 free (gotfree_input_line
);
6295 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6296 exp
->X_op
= O_illegal
;
6299 return i386_finalize_immediate (exp_seg
, exp
, types
, imm_start
);
6303 i386_finalize_immediate (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6304 i386_operand_type types
, const char *imm_start
)
6306 if (exp
->X_op
== O_absent
|| exp
->X_op
== O_illegal
|| exp
->X_op
== O_big
)
6309 as_bad (_("missing or invalid immediate expression `%s'"),
6313 else if (exp
->X_op
== O_constant
)
6315 /* Size it properly later. */
6316 i
.types
[this_operand
].bitfield
.imm64
= 1;
6317 /* If BFD64, sign extend val. */
6318 if (!use_rela_relocations
6319 && (exp
->X_add_number
& ~(((addressT
) 2 << 31) - 1)) == 0)
6321 = (exp
->X_add_number
^ ((addressT
) 1 << 31)) - ((addressT
) 1 << 31);
6323 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6324 else if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
6325 && exp_seg
!= absolute_section
6326 && exp_seg
!= text_section
6327 && exp_seg
!= data_section
6328 && exp_seg
!= bss_section
6329 && exp_seg
!= undefined_section
6330 && !bfd_is_com_section (exp_seg
))
6332 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6336 else if (!intel_syntax
&& exp
->X_op
== O_register
)
6339 as_bad (_("illegal immediate register operand %s"), imm_start
);
6344 /* This is an address. The size of the address will be
6345 determined later, depending on destination register,
6346 suffix, or the default for the section. */
6347 i
.types
[this_operand
].bitfield
.imm8
= 1;
6348 i
.types
[this_operand
].bitfield
.imm16
= 1;
6349 i
.types
[this_operand
].bitfield
.imm32
= 1;
6350 i
.types
[this_operand
].bitfield
.imm32s
= 1;
6351 i
.types
[this_operand
].bitfield
.imm64
= 1;
6352 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6360 i386_scale (char *scale
)
6363 char *save
= input_line_pointer
;
6365 input_line_pointer
= scale
;
6366 val
= get_absolute_expression ();
6371 i
.log2_scale_factor
= 0;
6374 i
.log2_scale_factor
= 1;
6377 i
.log2_scale_factor
= 2;
6380 i
.log2_scale_factor
= 3;
6384 char sep
= *input_line_pointer
;
6386 *input_line_pointer
= '\0';
6387 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
6389 *input_line_pointer
= sep
;
6390 input_line_pointer
= save
;
6394 if (i
.log2_scale_factor
!= 0 && i
.index_reg
== 0)
6396 as_warn (_("scale factor of %d without an index register"),
6397 1 << i
.log2_scale_factor
);
6398 i
.log2_scale_factor
= 0;
6400 scale
= input_line_pointer
;
6401 input_line_pointer
= save
;
6406 i386_displacement (char *disp_start
, char *disp_end
)
6410 char *save_input_line_pointer
;
6411 char *gotfree_input_line
;
6413 i386_operand_type bigdisp
, types
= anydisp
;
6416 if (i
.disp_operands
== MAX_MEMORY_OPERANDS
)
6418 as_bad (_("at most %d displacement operands are allowed"),
6419 MAX_MEMORY_OPERANDS
);
6423 operand_type_set (&bigdisp
, 0);
6424 if ((i
.types
[this_operand
].bitfield
.jumpabsolute
)
6425 || (!current_templates
->start
->opcode_modifier
.jump
6426 && !current_templates
->start
->opcode_modifier
.jumpdword
))
6428 bigdisp
.bitfield
.disp32
= 1;
6429 override
= (i
.prefix
[ADDR_PREFIX
] != 0);
6430 if (flag_code
== CODE_64BIT
)
6434 bigdisp
.bitfield
.disp32s
= 1;
6435 bigdisp
.bitfield
.disp64
= 1;
6438 else if ((flag_code
== CODE_16BIT
) ^ override
)
6440 bigdisp
.bitfield
.disp32
= 0;
6441 bigdisp
.bitfield
.disp16
= 1;
6446 /* For PC-relative branches, the width of the displacement
6447 is dependent upon data size, not address size. */
6448 override
= (i
.prefix
[DATA_PREFIX
] != 0);
6449 if (flag_code
== CODE_64BIT
)
6451 if (override
|| i
.suffix
== WORD_MNEM_SUFFIX
)
6452 bigdisp
.bitfield
.disp16
= 1;
6455 bigdisp
.bitfield
.disp32
= 1;
6456 bigdisp
.bitfield
.disp32s
= 1;
6462 override
= (i
.suffix
== (flag_code
!= CODE_16BIT
6464 : LONG_MNEM_SUFFIX
));
6465 bigdisp
.bitfield
.disp32
= 1;
6466 if ((flag_code
== CODE_16BIT
) ^ override
)
6468 bigdisp
.bitfield
.disp32
= 0;
6469 bigdisp
.bitfield
.disp16
= 1;
6473 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6476 exp
= &disp_expressions
[i
.disp_operands
];
6477 i
.op
[this_operand
].disps
= exp
;
6479 save_input_line_pointer
= input_line_pointer
;
6480 input_line_pointer
= disp_start
;
6481 END_STRING_AND_SAVE (disp_end
);
6483 #ifndef GCC_ASM_O_HACK
6484 #define GCC_ASM_O_HACK 0
6487 END_STRING_AND_SAVE (disp_end
+ 1);
6488 if (i
.types
[this_operand
].bitfield
.baseIndex
6489 && displacement_string_end
[-1] == '+')
6491 /* This hack is to avoid a warning when using the "o"
6492 constraint within gcc asm statements.
6495 #define _set_tssldt_desc(n,addr,limit,type) \
6496 __asm__ __volatile__ ( \
6498 "movw %w1,2+%0\n\t" \
6500 "movb %b1,4+%0\n\t" \
6501 "movb %4,5+%0\n\t" \
6502 "movb $0,6+%0\n\t" \
6503 "movb %h1,7+%0\n\t" \
6505 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
6507 This works great except that the output assembler ends
6508 up looking a bit weird if it turns out that there is
6509 no offset. You end up producing code that looks like:
6522 So here we provide the missing zero. */
6524 *displacement_string_end
= '0';
6527 gotfree_input_line
= lex_got (&i
.reloc
[this_operand
], NULL
, &types
);
6528 if (gotfree_input_line
)
6529 input_line_pointer
= gotfree_input_line
;
6531 exp_seg
= expression (exp
);
6534 if (*input_line_pointer
)
6535 as_bad (_("junk `%s' after expression"), input_line_pointer
);
6537 RESTORE_END_STRING (disp_end
+ 1);
6539 input_line_pointer
= save_input_line_pointer
;
6540 if (gotfree_input_line
)
6542 free (gotfree_input_line
);
6544 if (exp
->X_op
== O_constant
|| exp
->X_op
== O_register
)
6545 exp
->X_op
= O_illegal
;
6548 ret
= i386_finalize_displacement (exp_seg
, exp
, types
, disp_start
);
6550 RESTORE_END_STRING (disp_end
);
6556 i386_finalize_displacement (segT exp_seg ATTRIBUTE_UNUSED
, expressionS
*exp
,
6557 i386_operand_type types
, const char *disp_start
)
6559 i386_operand_type bigdisp
;
6562 /* We do this to make sure that the section symbol is in
6563 the symbol table. We will ultimately change the relocation
6564 to be relative to the beginning of the section. */
6565 if (i
.reloc
[this_operand
] == BFD_RELOC_386_GOTOFF
6566 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
6567 || i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6569 if (exp
->X_op
!= O_symbol
)
6572 if (S_IS_LOCAL (exp
->X_add_symbol
)
6573 && S_GET_SEGMENT (exp
->X_add_symbol
) != undefined_section
)
6574 section_symbol (S_GET_SEGMENT (exp
->X_add_symbol
));
6575 exp
->X_op
= O_subtract
;
6576 exp
->X_op_symbol
= GOT_symbol
;
6577 if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTPCREL
)
6578 i
.reloc
[this_operand
] = BFD_RELOC_32_PCREL
;
6579 else if (i
.reloc
[this_operand
] == BFD_RELOC_X86_64_GOTOFF64
)
6580 i
.reloc
[this_operand
] = BFD_RELOC_64
;
6582 i
.reloc
[this_operand
] = BFD_RELOC_32
;
6585 else if (exp
->X_op
== O_absent
6586 || exp
->X_op
== O_illegal
6587 || exp
->X_op
== O_big
)
6590 as_bad (_("missing or invalid displacement expression `%s'"),
6595 else if (flag_code
== CODE_64BIT
6596 && !i
.prefix
[ADDR_PREFIX
]
6597 && exp
->X_op
== O_constant
)
6599 /* Since displacement is signed extended to 64bit, don't allow
6600 disp32 and turn off disp32s if they are out of range. */
6601 i
.types
[this_operand
].bitfield
.disp32
= 0;
6602 if (!fits_in_signed_long (exp
->X_add_number
))
6604 i
.types
[this_operand
].bitfield
.disp32s
= 0;
6605 if (i
.types
[this_operand
].bitfield
.baseindex
)
6607 as_bad (_("0x%lx out range of signed 32bit displacement"),
6608 (long) exp
->X_add_number
);
6614 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
6615 else if (exp
->X_op
!= O_constant
6616 && OUTPUT_FLAVOR
== bfd_target_aout_flavour
6617 && exp_seg
!= absolute_section
6618 && exp_seg
!= text_section
6619 && exp_seg
!= data_section
6620 && exp_seg
!= bss_section
6621 && exp_seg
!= undefined_section
6622 && !bfd_is_com_section (exp_seg
))
6624 as_bad (_("unimplemented segment %s in operand"), exp_seg
->name
);
6629 /* Check if this is a displacement only operand. */
6630 bigdisp
= i
.types
[this_operand
];
6631 bigdisp
.bitfield
.disp8
= 0;
6632 bigdisp
.bitfield
.disp16
= 0;
6633 bigdisp
.bitfield
.disp32
= 0;
6634 bigdisp
.bitfield
.disp32s
= 0;
6635 bigdisp
.bitfield
.disp64
= 0;
6636 if (operand_type_all_zero (&bigdisp
))
6637 i
.types
[this_operand
] = operand_type_and (i
.types
[this_operand
],
6643 /* Make sure the memory operand we've been dealt is valid.
6644 Return 1 on success, 0 on a failure. */
6647 i386_index_check (const char *operand_string
)
6650 const char *kind
= "base/index";
6651 #if INFER_ADDR_PREFIX
6657 if (current_templates
->start
->opcode_modifier
.isstring
6658 && !current_templates
->start
->opcode_modifier
.immext
6659 && (current_templates
->end
[-1].opcode_modifier
.isstring
6662 /* Memory operands of string insns are special in that they only allow
6663 a single register (rDI, rSI, or rBX) as their memory address. */
6664 unsigned int expected
;
6666 kind
= "string address";
6668 if (current_templates
->start
->opcode_modifier
.w
)
6670 i386_operand_type type
= current_templates
->end
[-1].operand_types
[0];
6672 if (!type
.bitfield
.baseindex
6673 || ((!i
.mem_operands
!= !intel_syntax
)
6674 && current_templates
->end
[-1].operand_types
[1]
6675 .bitfield
.baseindex
))
6676 type
= current_templates
->end
[-1].operand_types
[1];
6677 expected
= type
.bitfield
.esseg
? 7 /* rDI */ : 6 /* rSI */;
6680 expected
= 3 /* rBX */;
6682 if (!i
.base_reg
|| i
.index_reg
6683 || operand_type_check (i
.types
[this_operand
], disp
))
6685 else if (!(flag_code
== CODE_64BIT
6686 ? i
.prefix
[ADDR_PREFIX
]
6687 ? i
.base_reg
->reg_type
.bitfield
.reg32
6688 : i
.base_reg
->reg_type
.bitfield
.reg64
6689 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6690 ? i
.base_reg
->reg_type
.bitfield
.reg32
6691 : i
.base_reg
->reg_type
.bitfield
.reg16
))
6693 else if (i
.base_reg
->reg_num
!= expected
)
6700 for (j
= 0; j
< i386_regtab_size
; ++j
)
6701 if ((flag_code
== CODE_64BIT
6702 ? i
.prefix
[ADDR_PREFIX
]
6703 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6704 : i386_regtab
[j
].reg_type
.bitfield
.reg64
6705 : (flag_code
== CODE_16BIT
) ^ !i
.prefix
[ADDR_PREFIX
]
6706 ? i386_regtab
[j
].reg_type
.bitfield
.reg32
6707 : i386_regtab
[j
].reg_type
.bitfield
.reg16
)
6708 && i386_regtab
[j
].reg_num
== expected
)
6710 gas_assert (j
< i386_regtab_size
);
6711 as_warn (_("`%s' is not valid here (expected `%c%s%s%c')"),
6713 intel_syntax
? '[' : '(',
6715 i386_regtab
[j
].reg_name
,
6716 intel_syntax
? ']' : ')');
6720 else if (flag_code
== CODE_64BIT
)
6723 && ((i
.prefix
[ADDR_PREFIX
] == 0
6724 && !i
.base_reg
->reg_type
.bitfield
.reg64
)
6725 || (i
.prefix
[ADDR_PREFIX
]
6726 && !i
.base_reg
->reg_type
.bitfield
.reg32
))
6728 || i
.base_reg
->reg_num
!=
6729 (i
.prefix
[ADDR_PREFIX
] == 0 ? RegRip
: RegEip
)))
6731 && (!i
.index_reg
->reg_type
.bitfield
.baseindex
6732 || (i
.prefix
[ADDR_PREFIX
] == 0
6733 && i
.index_reg
->reg_num
!= RegRiz
6734 && !i
.index_reg
->reg_type
.bitfield
.reg64
6736 || (i
.prefix
[ADDR_PREFIX
]
6737 && i
.index_reg
->reg_num
!= RegEiz
6738 && !i
.index_reg
->reg_type
.bitfield
.reg32
))))
6743 if ((flag_code
== CODE_16BIT
) ^ (i
.prefix
[ADDR_PREFIX
] != 0))
6747 && (!i
.base_reg
->reg_type
.bitfield
.reg16
6748 || !i
.base_reg
->reg_type
.bitfield
.baseindex
))
6750 && (!i
.index_reg
->reg_type
.bitfield
.reg16
6751 || !i
.index_reg
->reg_type
.bitfield
.baseindex
6753 && i
.base_reg
->reg_num
< 6
6754 && i
.index_reg
->reg_num
>= 6
6755 && i
.log2_scale_factor
== 0))))
6762 && !i
.base_reg
->reg_type
.bitfield
.reg32
)
6764 && ((!i
.index_reg
->reg_type
.bitfield
.reg32
6765 && i
.index_reg
->reg_num
!= RegEiz
)
6766 || !i
.index_reg
->reg_type
.bitfield
.baseindex
)))
6772 #if INFER_ADDR_PREFIX
6773 if (!i
.mem_operands
&& !i
.prefix
[ADDR_PREFIX
])
6775 i
.prefix
[ADDR_PREFIX
] = ADDR_PREFIX_OPCODE
;
6777 /* Change the size of any displacement too. At most one of
6778 Disp16 or Disp32 is set.
6779 FIXME. There doesn't seem to be any real need for separate
6780 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
6781 Removing them would probably clean up the code quite a lot. */
6782 if (flag_code
!= CODE_64BIT
6783 && (i
.types
[this_operand
].bitfield
.disp16
6784 || i
.types
[this_operand
].bitfield
.disp32
))
6785 i
.types
[this_operand
]
6786 = operand_type_xor (i
.types
[this_operand
], disp16_32
);
6791 as_bad (_("`%s' is not a valid %s expression"),
6796 as_bad (_("`%s' is not a valid %s-bit %s expression"),
6798 flag_code_names
[i
.prefix
[ADDR_PREFIX
]
6799 ? flag_code
== CODE_32BIT
6808 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
6812 i386_att_operand (char *operand_string
)
6816 char *op_string
= operand_string
;
6818 if (is_space_char (*op_string
))
6821 /* We check for an absolute prefix (differentiating,
6822 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
6823 if (*op_string
== ABSOLUTE_PREFIX
)
6826 if (is_space_char (*op_string
))
6828 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6831 /* Check if operand is a register. */
6832 if ((r
= parse_register (op_string
, &end_op
)) != NULL
)
6834 i386_operand_type temp
;
6836 /* Check for a segment override by searching for ':' after a
6837 segment register. */
6839 if (is_space_char (*op_string
))
6841 if (*op_string
== ':'
6842 && (r
->reg_type
.bitfield
.sreg2
6843 || r
->reg_type
.bitfield
.sreg3
))
6848 i
.seg
[i
.mem_operands
] = &es
;
6851 i
.seg
[i
.mem_operands
] = &cs
;
6854 i
.seg
[i
.mem_operands
] = &ss
;
6857 i
.seg
[i
.mem_operands
] = &ds
;
6860 i
.seg
[i
.mem_operands
] = &fs
;
6863 i
.seg
[i
.mem_operands
] = &gs
;
6867 /* Skip the ':' and whitespace. */
6869 if (is_space_char (*op_string
))
6872 if (!is_digit_char (*op_string
)
6873 && !is_identifier_char (*op_string
)
6874 && *op_string
!= '('
6875 && *op_string
!= ABSOLUTE_PREFIX
)
6877 as_bad (_("bad memory operand `%s'"), op_string
);
6880 /* Handle case of %es:*foo. */
6881 if (*op_string
== ABSOLUTE_PREFIX
)
6884 if (is_space_char (*op_string
))
6886 i
.types
[this_operand
].bitfield
.jumpabsolute
= 1;
6888 goto do_memory_reference
;
6892 as_bad (_("junk `%s' after register"), op_string
);
6896 temp
.bitfield
.baseindex
= 0;
6897 i
.types
[this_operand
] = operand_type_or (i
.types
[this_operand
],
6899 i
.types
[this_operand
].bitfield
.unspecified
= 0;
6900 i
.op
[this_operand
].regs
= r
;
6903 else if (*op_string
== REGISTER_PREFIX
)
6905 as_bad (_("bad register name `%s'"), op_string
);
6908 else if (*op_string
== IMMEDIATE_PREFIX
)
6911 if (i
.types
[this_operand
].bitfield
.jumpabsolute
)
6913 as_bad (_("immediate operand illegal with absolute jump"));
6916 if (!i386_immediate (op_string
))
6919 else if (is_digit_char (*op_string
)
6920 || is_identifier_char (*op_string
)
6921 || *op_string
== '(')
6923 /* This is a memory reference of some sort. */
6926 /* Start and end of displacement string expression (if found). */
6927 char *displacement_string_start
;
6928 char *displacement_string_end
;
6930 do_memory_reference
:
6931 if ((i
.mem_operands
== 1
6932 && !current_templates
->start
->opcode_modifier
.isstring
)
6933 || i
.mem_operands
== 2)
6935 as_bad (_("too many memory references for `%s'"),
6936 current_templates
->start
->name
);
6940 /* Check for base index form. We detect the base index form by
6941 looking for an ')' at the end of the operand, searching
6942 for the '(' matching it, and finding a REGISTER_PREFIX or ','
6944 base_string
= op_string
+ strlen (op_string
);
6947 if (is_space_char (*base_string
))
6950 /* If we only have a displacement, set-up for it to be parsed later. */
6951 displacement_string_start
= op_string
;
6952 displacement_string_end
= base_string
+ 1;
6954 if (*base_string
== ')')
6957 unsigned int parens_balanced
= 1;
6958 /* We've already checked that the number of left & right ()'s are
6959 equal, so this loop will not be infinite. */
6963 if (*base_string
== ')')
6965 if (*base_string
== '(')
6968 while (parens_balanced
);
6970 temp_string
= base_string
;
6972 /* Skip past '(' and whitespace. */
6974 if (is_space_char (*base_string
))
6977 if (*base_string
== ','
6978 || ((i
.base_reg
= parse_register (base_string
, &end_op
))
6981 displacement_string_end
= temp_string
;
6983 i
.types
[this_operand
].bitfield
.baseindex
= 1;
6987 base_string
= end_op
;
6988 if (is_space_char (*base_string
))
6992 /* There may be an index reg or scale factor here. */
6993 if (*base_string
== ',')
6996 if (is_space_char (*base_string
))
6999 if ((i
.index_reg
= parse_register (base_string
, &end_op
))
7002 base_string
= end_op
;
7003 if (is_space_char (*base_string
))
7005 if (*base_string
== ',')
7008 if (is_space_char (*base_string
))
7011 else if (*base_string
!= ')')
7013 as_bad (_("expecting `,' or `)' "
7014 "after index register in `%s'"),
7019 else if (*base_string
== REGISTER_PREFIX
)
7021 as_bad (_("bad register name `%s'"), base_string
);
7025 /* Check for scale factor. */
7026 if (*base_string
!= ')')
7028 char *end_scale
= i386_scale (base_string
);
7033 base_string
= end_scale
;
7034 if (is_space_char (*base_string
))
7036 if (*base_string
!= ')')
7038 as_bad (_("expecting `)' "
7039 "after scale factor in `%s'"),
7044 else if (!i
.index_reg
)
7046 as_bad (_("expecting index register or scale factor "
7047 "after `,'; got '%c'"),
7052 else if (*base_string
!= ')')
7054 as_bad (_("expecting `,' or `)' "
7055 "after base register in `%s'"),
7060 else if (*base_string
== REGISTER_PREFIX
)
7062 as_bad (_("bad register name `%s'"), base_string
);
7067 /* If there's an expression beginning the operand, parse it,
7068 assuming displacement_string_start and
7069 displacement_string_end are meaningful. */
7070 if (displacement_string_start
!= displacement_string_end
)
7072 if (!i386_displacement (displacement_string_start
,
7073 displacement_string_end
))
7077 /* Special case for (%dx) while doing input/output op. */
7079 && operand_type_equal (&i
.base_reg
->reg_type
,
7080 ®16_inoutportreg
)
7082 && i
.log2_scale_factor
== 0
7083 && i
.seg
[i
.mem_operands
] == 0
7084 && !operand_type_check (i
.types
[this_operand
], disp
))
7086 i
.types
[this_operand
] = inoutportreg
;
7090 if (i386_index_check (operand_string
) == 0)
7092 i
.types
[this_operand
].bitfield
.mem
= 1;
7097 /* It's not a memory operand; argh! */
7098 as_bad (_("invalid char %s beginning operand %d `%s'"),
7099 output_invalid (*op_string
),
7104 return 1; /* Normal return. */
7107 /* md_estimate_size_before_relax()
7109 Called just before relax() for rs_machine_dependent frags. The x86
7110 assembler uses these frags to handle variable size jump
7113 Any symbol that is now undefined will not become defined.
7114 Return the correct fr_subtype in the frag.
7115 Return the initial "guess for variable size of frag" to caller.
7116 The guess is actually the growth beyond the fixed part. Whatever
7117 we do to grow the fixed or variable part contributes to our
7121 md_estimate_size_before_relax (fragP
, segment
)
7125 /* We've already got fragP->fr_subtype right; all we have to do is
7126 check for un-relaxable symbols. On an ELF system, we can't relax
7127 an externally visible symbol, because it may be overridden by a
7129 if (S_GET_SEGMENT (fragP
->fr_symbol
) != segment
7130 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7132 && (S_IS_EXTERNAL (fragP
->fr_symbol
)
7133 || S_IS_WEAK (fragP
->fr_symbol
)
7134 || ((symbol_get_bfdsym (fragP
->fr_symbol
)->flags
7135 & BSF_GNU_INDIRECT_FUNCTION
))))
7137 #if defined (OBJ_COFF) && defined (TE_PE)
7138 || (OUTPUT_FLAVOR
== bfd_target_coff_flavour
7139 && S_IS_WEAK (fragP
->fr_symbol
))
7143 /* Symbol is undefined in this segment, or we need to keep a
7144 reloc so that weak symbols can be overridden. */
7145 int size
= (fragP
->fr_subtype
& CODE16
) ? 2 : 4;
7146 enum bfd_reloc_code_real reloc_type
;
7147 unsigned char *opcode
;
7150 if (fragP
->fr_var
!= NO_RELOC
)
7151 reloc_type
= (enum bfd_reloc_code_real
) fragP
->fr_var
;
7153 reloc_type
= BFD_RELOC_16_PCREL
;
7155 reloc_type
= BFD_RELOC_32_PCREL
;
7157 old_fr_fix
= fragP
->fr_fix
;
7158 opcode
= (unsigned char *) fragP
->fr_opcode
;
7160 switch (TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
))
7163 /* Make jmp (0xeb) a (d)word displacement jump. */
7165 fragP
->fr_fix
+= size
;
7166 fix_new (fragP
, old_fr_fix
, size
,
7168 fragP
->fr_offset
, 1,
7174 && (!no_cond_jump_promotion
|| fragP
->fr_var
!= NO_RELOC
))
7176 /* Negate the condition, and branch past an
7177 unconditional jump. */
7180 /* Insert an unconditional jump. */
7182 /* We added two extra opcode bytes, and have a two byte
7184 fragP
->fr_fix
+= 2 + 2;
7185 fix_new (fragP
, old_fr_fix
+ 2, 2,
7187 fragP
->fr_offset
, 1,
7194 if (no_cond_jump_promotion
&& fragP
->fr_var
== NO_RELOC
)
7199 fixP
= fix_new (fragP
, old_fr_fix
, 1,
7201 fragP
->fr_offset
, 1,
7203 fixP
->fx_signed
= 1;
7207 /* This changes the byte-displacement jump 0x7N
7208 to the (d)word-displacement jump 0x0f,0x8N. */
7209 opcode
[1] = opcode
[0] + 0x10;
7210 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7211 /* We've added an opcode byte. */
7212 fragP
->fr_fix
+= 1 + size
;
7213 fix_new (fragP
, old_fr_fix
+ 1, size
,
7215 fragP
->fr_offset
, 1,
7220 BAD_CASE (fragP
->fr_subtype
);
7224 return fragP
->fr_fix
- old_fr_fix
;
7227 /* Guess size depending on current relax state. Initially the relax
7228 state will correspond to a short jump and we return 1, because
7229 the variable part of the frag (the branch offset) is one byte
7230 long. However, we can relax a section more than once and in that
7231 case we must either set fr_subtype back to the unrelaxed state,
7232 or return the value for the appropriate branch. */
7233 return md_relax_table
[fragP
->fr_subtype
].rlx_length
;
7236 /* Called after relax() is finished.
7238 In: Address of frag.
7239 fr_type == rs_machine_dependent.
7240 fr_subtype is what the address relaxed to.
7242 Out: Any fixSs and constants are set up.
7243 Caller will turn frag into a ".space 0". */
7246 md_convert_frag (abfd
, sec
, fragP
)
7247 bfd
*abfd ATTRIBUTE_UNUSED
;
7248 segT sec ATTRIBUTE_UNUSED
;
7251 unsigned char *opcode
;
7252 unsigned char *where_to_put_displacement
= NULL
;
7253 offsetT target_address
;
7254 offsetT opcode_address
;
7255 unsigned int extension
= 0;
7256 offsetT displacement_from_opcode_start
;
7258 opcode
= (unsigned char *) fragP
->fr_opcode
;
7260 /* Address we want to reach in file space. */
7261 target_address
= S_GET_VALUE (fragP
->fr_symbol
) + fragP
->fr_offset
;
7263 /* Address opcode resides at in file space. */
7264 opcode_address
= fragP
->fr_address
+ fragP
->fr_fix
;
7266 /* Displacement from opcode start to fill into instruction. */
7267 displacement_from_opcode_start
= target_address
- opcode_address
;
7269 if ((fragP
->fr_subtype
& BIG
) == 0)
7271 /* Don't have to change opcode. */
7272 extension
= 1; /* 1 opcode + 1 displacement */
7273 where_to_put_displacement
= &opcode
[1];
7277 if (no_cond_jump_promotion
7278 && TYPE_FROM_RELAX_STATE (fragP
->fr_subtype
) != UNCOND_JUMP
)
7279 as_warn_where (fragP
->fr_file
, fragP
->fr_line
,
7280 _("long jump required"));
7282 switch (fragP
->fr_subtype
)
7284 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG
):
7285 extension
= 4; /* 1 opcode + 4 displacement */
7287 where_to_put_displacement
= &opcode
[1];
7290 case ENCODE_RELAX_STATE (UNCOND_JUMP
, BIG16
):
7291 extension
= 2; /* 1 opcode + 2 displacement */
7293 where_to_put_displacement
= &opcode
[1];
7296 case ENCODE_RELAX_STATE (COND_JUMP
, BIG
):
7297 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG
):
7298 extension
= 5; /* 2 opcode + 4 displacement */
7299 opcode
[1] = opcode
[0] + 0x10;
7300 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7301 where_to_put_displacement
= &opcode
[2];
7304 case ENCODE_RELAX_STATE (COND_JUMP
, BIG16
):
7305 extension
= 3; /* 2 opcode + 2 displacement */
7306 opcode
[1] = opcode
[0] + 0x10;
7307 opcode
[0] = TWO_BYTE_OPCODE_ESCAPE
;
7308 where_to_put_displacement
= &opcode
[2];
7311 case ENCODE_RELAX_STATE (COND_JUMP86
, BIG16
):
7316 where_to_put_displacement
= &opcode
[3];
7320 BAD_CASE (fragP
->fr_subtype
);
7325 /* If size if less then four we are sure that the operand fits,
7326 but if it's 4, then it could be that the displacement is larger
7328 if (DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
) == 4
7330 && ((addressT
) (displacement_from_opcode_start
- extension
7331 + ((addressT
) 1 << 31))
7332 > (((addressT
) 2 << 31) - 1)))
7334 as_bad_where (fragP
->fr_file
, fragP
->fr_line
,
7335 _("jump target out of range"));
7336 /* Make us emit 0. */
7337 displacement_from_opcode_start
= extension
;
7339 /* Now put displacement after opcode. */
7340 md_number_to_chars ((char *) where_to_put_displacement
,
7341 (valueT
) (displacement_from_opcode_start
- extension
),
7342 DISP_SIZE_FROM_RELAX_STATE (fragP
->fr_subtype
));
7343 fragP
->fr_fix
+= extension
;
7346 /* Apply a fixup (fixS) to segment data, once it has been determined
7347 by our caller that we have all the info we need to fix it up.
7349 On the 386, immediates, displacements, and data pointers are all in
7350 the same (little-endian) format, so we don't need to care about which
7354 md_apply_fix (fixP
, valP
, seg
)
7355 /* The fix we're to put in. */
7357 /* Pointer to the value of the bits. */
7359 /* Segment fix is from. */
7360 segT seg ATTRIBUTE_UNUSED
;
7362 char *p
= fixP
->fx_where
+ fixP
->fx_frag
->fr_literal
;
7363 valueT value
= *valP
;
7365 #if !defined (TE_Mach)
7368 switch (fixP
->fx_r_type
)
7374 fixP
->fx_r_type
= BFD_RELOC_64_PCREL
;
7377 case BFD_RELOC_X86_64_32S
:
7378 fixP
->fx_r_type
= BFD_RELOC_32_PCREL
;
7381 fixP
->fx_r_type
= BFD_RELOC_16_PCREL
;
7384 fixP
->fx_r_type
= BFD_RELOC_8_PCREL
;
7389 if (fixP
->fx_addsy
!= NULL
7390 && (fixP
->fx_r_type
== BFD_RELOC_32_PCREL
7391 || fixP
->fx_r_type
== BFD_RELOC_64_PCREL
7392 || fixP
->fx_r_type
== BFD_RELOC_16_PCREL
7393 || fixP
->fx_r_type
== BFD_RELOC_8_PCREL
)
7394 && !use_rela_relocations
)
7396 /* This is a hack. There should be a better way to handle this.
7397 This covers for the fact that bfd_install_relocation will
7398 subtract the current location (for partial_inplace, PC relative
7399 relocations); see more below. */
7403 || OUTPUT_FLAVOR
== bfd_target_coff_flavour
7406 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7408 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7411 segT sym_seg
= S_GET_SEGMENT (fixP
->fx_addsy
);
7414 || (symbol_section_p (fixP
->fx_addsy
)
7415 && sym_seg
!= absolute_section
))
7416 && !generic_force_reloc (fixP
))
7418 /* Yes, we add the values in twice. This is because
7419 bfd_install_relocation subtracts them out again. I think
7420 bfd_install_relocation is broken, but I don't dare change
7422 value
+= fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
7426 #if defined (OBJ_COFF) && defined (TE_PE)
7427 /* For some reason, the PE format does not store a
7428 section address offset for a PC relative symbol. */
7429 if (S_GET_SEGMENT (fixP
->fx_addsy
) != seg
7430 || S_IS_WEAK (fixP
->fx_addsy
))
7431 value
+= md_pcrel_from (fixP
);
7434 #if defined (OBJ_COFF) && defined (TE_PE)
7435 if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7437 value
-= S_GET_VALUE (fixP
->fx_addsy
);
7441 /* Fix a few things - the dynamic linker expects certain values here,
7442 and we must not disappoint it. */
7443 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7444 if (IS_ELF
&& fixP
->fx_addsy
)
7445 switch (fixP
->fx_r_type
)
7447 case BFD_RELOC_386_PLT32
:
7448 case BFD_RELOC_X86_64_PLT32
:
7449 /* Make the jump instruction point to the address of the operand. At
7450 runtime we merely add the offset to the actual PLT entry. */
7454 case BFD_RELOC_386_TLS_GD
:
7455 case BFD_RELOC_386_TLS_LDM
:
7456 case BFD_RELOC_386_TLS_IE_32
:
7457 case BFD_RELOC_386_TLS_IE
:
7458 case BFD_RELOC_386_TLS_GOTIE
:
7459 case BFD_RELOC_386_TLS_GOTDESC
:
7460 case BFD_RELOC_X86_64_TLSGD
:
7461 case BFD_RELOC_X86_64_TLSLD
:
7462 case BFD_RELOC_X86_64_GOTTPOFF
:
7463 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
7464 value
= 0; /* Fully resolved at runtime. No addend. */
7466 case BFD_RELOC_386_TLS_LE
:
7467 case BFD_RELOC_386_TLS_LDO_32
:
7468 case BFD_RELOC_386_TLS_LE_32
:
7469 case BFD_RELOC_X86_64_DTPOFF32
:
7470 case BFD_RELOC_X86_64_DTPOFF64
:
7471 case BFD_RELOC_X86_64_TPOFF32
:
7472 case BFD_RELOC_X86_64_TPOFF64
:
7473 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7476 case BFD_RELOC_386_TLS_DESC_CALL
:
7477 case BFD_RELOC_X86_64_TLSDESC_CALL
:
7478 value
= 0; /* Fully resolved at runtime. No addend. */
7479 S_SET_THREAD_LOCAL (fixP
->fx_addsy
);
7483 case BFD_RELOC_386_GOT32
:
7484 case BFD_RELOC_X86_64_GOT32
:
7485 value
= 0; /* Fully resolved at runtime. No addend. */
7488 case BFD_RELOC_VTABLE_INHERIT
:
7489 case BFD_RELOC_VTABLE_ENTRY
:
7496 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
7498 #endif /* !defined (TE_Mach) */
7500 /* Are we finished with this relocation now? */
7501 if (fixP
->fx_addsy
== NULL
)
7503 #if defined (OBJ_COFF) && defined (TE_PE)
7504 else if (fixP
->fx_addsy
!= NULL
&& S_IS_WEAK (fixP
->fx_addsy
))
7507 /* Remember value for tc_gen_reloc. */
7508 fixP
->fx_addnumber
= value
;
7509 /* Clear out the frag for now. */
7513 else if (use_rela_relocations
)
7515 fixP
->fx_no_overflow
= 1;
7516 /* Remember value for tc_gen_reloc. */
7517 fixP
->fx_addnumber
= value
;
7521 md_number_to_chars (p
, value
, fixP
->fx_size
);
7525 md_atof (int type
, char *litP
, int *sizeP
)
7527 /* This outputs the LITTLENUMs in REVERSE order;
7528 in accord with the bigendian 386. */
7529 return ieee_md_atof (type
, litP
, sizeP
, FALSE
);
7532 static char output_invalid_buf
[sizeof (unsigned char) * 2 + 6];
7535 output_invalid (int c
)
7538 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7541 snprintf (output_invalid_buf
, sizeof (output_invalid_buf
),
7542 "(0x%x)", (unsigned char) c
);
7543 return output_invalid_buf
;
7546 /* REG_STRING starts *before* REGISTER_PREFIX. */
7548 static const reg_entry
*
7549 parse_real_register (char *reg_string
, char **end_op
)
7551 char *s
= reg_string
;
7553 char reg_name_given
[MAX_REG_NAME_SIZE
+ 1];
7556 /* Skip possible REGISTER_PREFIX and possible whitespace. */
7557 if (*s
== REGISTER_PREFIX
)
7560 if (is_space_char (*s
))
7564 while ((*p
++ = register_chars
[(unsigned char) *s
]) != '\0')
7566 if (p
>= reg_name_given
+ MAX_REG_NAME_SIZE
)
7567 return (const reg_entry
*) NULL
;
7571 /* For naked regs, make sure that we are not dealing with an identifier.
7572 This prevents confusing an identifier like `eax_var' with register
7574 if (allow_naked_reg
&& identifier_chars
[(unsigned char) *s
])
7575 return (const reg_entry
*) NULL
;
7579 r
= (const reg_entry
*) hash_find (reg_hash
, reg_name_given
);
7581 /* Handle floating point regs, allowing spaces in the (i) part. */
7582 if (r
== i386_regtab
/* %st is first entry of table */)
7584 if (is_space_char (*s
))
7589 if (is_space_char (*s
))
7591 if (*s
>= '0' && *s
<= '7')
7595 if (is_space_char (*s
))
7600 r
= (const reg_entry
*) hash_find (reg_hash
, "st(0)");
7605 /* We have "%st(" then garbage. */
7606 return (const reg_entry
*) NULL
;
7610 if (r
== NULL
|| allow_pseudo_reg
)
7613 if (operand_type_all_zero (&r
->reg_type
))
7614 return (const reg_entry
*) NULL
;
7616 if ((r
->reg_type
.bitfield
.reg32
7617 || r
->reg_type
.bitfield
.sreg3
7618 || r
->reg_type
.bitfield
.control
7619 || r
->reg_type
.bitfield
.debug
7620 || r
->reg_type
.bitfield
.test
)
7621 && !cpu_arch_flags
.bitfield
.cpui386
)
7622 return (const reg_entry
*) NULL
;
7624 if (r
->reg_type
.bitfield
.floatreg
7625 && !cpu_arch_flags
.bitfield
.cpu8087
7626 && !cpu_arch_flags
.bitfield
.cpu287
7627 && !cpu_arch_flags
.bitfield
.cpu387
)
7628 return (const reg_entry
*) NULL
;
7630 if (r
->reg_type
.bitfield
.regmmx
&& !cpu_arch_flags
.bitfield
.cpummx
)
7631 return (const reg_entry
*) NULL
;
7633 if (r
->reg_type
.bitfield
.regxmm
&& !cpu_arch_flags
.bitfield
.cpusse
)
7634 return (const reg_entry
*) NULL
;
7636 if (r
->reg_type
.bitfield
.regymm
&& !cpu_arch_flags
.bitfield
.cpuavx
)
7637 return (const reg_entry
*) NULL
;
7639 /* Don't allow fake index register unless allow_index_reg isn't 0. */
7640 if (!allow_index_reg
7641 && (r
->reg_num
== RegEiz
|| r
->reg_num
== RegRiz
))
7642 return (const reg_entry
*) NULL
;
7644 if (((r
->reg_flags
& (RegRex64
| RegRex
))
7645 || r
->reg_type
.bitfield
.reg64
)
7646 && (!cpu_arch_flags
.bitfield
.cpulm
7647 || !operand_type_equal (&r
->reg_type
, &control
))
7648 && flag_code
!= CODE_64BIT
)
7649 return (const reg_entry
*) NULL
;
7651 if (r
->reg_type
.bitfield
.sreg3
&& r
->reg_num
== RegFlat
&& !intel_syntax
)
7652 return (const reg_entry
*) NULL
;
7657 /* REG_STRING starts *before* REGISTER_PREFIX. */
7659 static const reg_entry
*
7660 parse_register (char *reg_string
, char **end_op
)
7664 if (*reg_string
== REGISTER_PREFIX
|| allow_naked_reg
)
7665 r
= parse_real_register (reg_string
, end_op
);
7670 char *save
= input_line_pointer
;
7674 input_line_pointer
= reg_string
;
7675 c
= get_symbol_end ();
7676 symbolP
= symbol_find (reg_string
);
7677 if (symbolP
&& S_GET_SEGMENT (symbolP
) == reg_section
)
7679 const expressionS
*e
= symbol_get_value_expression (symbolP
);
7681 know (e
->X_op
== O_register
);
7682 know (e
->X_add_number
>= 0
7683 && (valueT
) e
->X_add_number
< i386_regtab_size
);
7684 r
= i386_regtab
+ e
->X_add_number
;
7685 *end_op
= input_line_pointer
;
7687 *input_line_pointer
= c
;
7688 input_line_pointer
= save
;
7694 i386_parse_name (char *name
, expressionS
*e
, char *nextcharP
)
7697 char *end
= input_line_pointer
;
7700 r
= parse_register (name
, &input_line_pointer
);
7701 if (r
&& end
<= input_line_pointer
)
7703 *nextcharP
= *input_line_pointer
;
7704 *input_line_pointer
= 0;
7705 e
->X_op
= O_register
;
7706 e
->X_add_number
= r
- i386_regtab
;
7709 input_line_pointer
= end
;
7711 return intel_syntax
? i386_intel_parse_name (name
, e
) : 0;
7715 md_operand (expressionS
*e
)
7720 switch (*input_line_pointer
)
7722 case REGISTER_PREFIX
:
7723 r
= parse_real_register (input_line_pointer
, &end
);
7726 e
->X_op
= O_register
;
7727 e
->X_add_number
= r
- i386_regtab
;
7728 input_line_pointer
= end
;
7733 gas_assert (intel_syntax
);
7734 end
= input_line_pointer
++;
7736 if (*input_line_pointer
== ']')
7738 ++input_line_pointer
;
7739 e
->X_op_symbol
= make_expr_symbol (e
);
7740 e
->X_add_symbol
= NULL
;
7741 e
->X_add_number
= 0;
7747 input_line_pointer
= end
;
7754 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7755 const char *md_shortopts
= "kVQ:sqn";
7757 const char *md_shortopts
= "qn";
7760 #define OPTION_32 (OPTION_MD_BASE + 0)
7761 #define OPTION_64 (OPTION_MD_BASE + 1)
7762 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
7763 #define OPTION_MARCH (OPTION_MD_BASE + 3)
7764 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
7765 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
7766 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
7767 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
7768 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
7769 #define OPTION_MOLD_GCC (OPTION_MD_BASE + 9)
7770 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
7771 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
7773 struct option md_longopts
[] =
7775 {"32", no_argument
, NULL
, OPTION_32
},
7776 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7777 || defined (TE_PE) || defined (TE_PEP))
7778 {"64", no_argument
, NULL
, OPTION_64
},
7780 {"divide", no_argument
, NULL
, OPTION_DIVIDE
},
7781 {"march", required_argument
, NULL
, OPTION_MARCH
},
7782 {"mtune", required_argument
, NULL
, OPTION_MTUNE
},
7783 {"mmnemonic", required_argument
, NULL
, OPTION_MMNEMONIC
},
7784 {"msyntax", required_argument
, NULL
, OPTION_MSYNTAX
},
7785 {"mindex-reg", no_argument
, NULL
, OPTION_MINDEX_REG
},
7786 {"mnaked-reg", no_argument
, NULL
, OPTION_MNAKED_REG
},
7787 {"mold-gcc", no_argument
, NULL
, OPTION_MOLD_GCC
},
7788 {"msse2avx", no_argument
, NULL
, OPTION_MSSE2AVX
},
7789 {"msse-check", required_argument
, NULL
, OPTION_MSSE_CHECK
},
7790 {NULL
, no_argument
, NULL
, 0}
7792 size_t md_longopts_size
= sizeof (md_longopts
);
7795 md_parse_option (int c
, char *arg
)
7803 optimize_align_code
= 0;
7810 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
7811 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
7812 should be emitted or not. FIXME: Not implemented. */
7816 /* -V: SVR4 argument to print version ID. */
7818 print_version_id ();
7821 /* -k: Ignore for FreeBSD compatibility. */
7826 /* -s: On i386 Solaris, this tells the native assembler to use
7827 .stab instead of .stab.excl. We always use .stab anyhow. */
7830 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
7831 || defined (TE_PE) || defined (TE_PEP))
7834 const char **list
, **l
;
7836 list
= bfd_target_list ();
7837 for (l
= list
; *l
!= NULL
; l
++)
7838 if (CONST_STRNEQ (*l
, "elf64-x86-64")
7839 || strcmp (*l
, "coff-x86-64") == 0
7840 || strcmp (*l
, "pe-x86-64") == 0
7841 || strcmp (*l
, "pei-x86-64") == 0)
7843 default_arch
= "x86_64";
7847 as_fatal (_("No compiled in support for x86_64"));
7854 default_arch
= "i386";
7858 #ifdef SVR4_COMMENT_CHARS
7863 n
= (char *) xmalloc (strlen (i386_comment_chars
) + 1);
7865 for (s
= i386_comment_chars
; *s
!= '\0'; s
++)
7869 i386_comment_chars
= n
;
7875 arch
= xstrdup (arg
);
7879 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7880 next
= strchr (arch
, '+');
7883 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7885 if (strcmp (arch
, cpu_arch
[i
].name
) == 0)
7888 cpu_arch_name
= cpu_arch
[i
].name
;
7889 cpu_sub_arch_name
= NULL
;
7890 cpu_arch_flags
= cpu_arch
[i
].flags
;
7891 cpu_arch_isa
= cpu_arch
[i
].type
;
7892 cpu_arch_isa_flags
= cpu_arch
[i
].flags
;
7893 if (!cpu_arch_tune_set
)
7895 cpu_arch_tune
= cpu_arch_isa
;
7896 cpu_arch_tune_flags
= cpu_arch_isa_flags
;
7900 else if (*cpu_arch
[i
].name
== '.'
7901 && strcmp (arch
, cpu_arch
[i
].name
+ 1) == 0)
7903 /* ISA entension. */
7904 i386_cpu_flags flags
;
7906 if (strncmp (arch
, "no", 2))
7907 flags
= cpu_flags_or (cpu_arch_flags
,
7910 flags
= cpu_flags_and_not (cpu_arch_flags
,
7912 if (!cpu_flags_equal (&flags
, &cpu_arch_flags
))
7914 if (cpu_sub_arch_name
)
7916 char *name
= cpu_sub_arch_name
;
7917 cpu_sub_arch_name
= concat (name
,
7919 (const char *) NULL
);
7923 cpu_sub_arch_name
= xstrdup (cpu_arch
[i
].name
);
7924 cpu_arch_flags
= flags
;
7930 if (i
>= ARRAY_SIZE (cpu_arch
))
7931 as_fatal (_("Invalid -march= option: `%s'"), arg
);
7935 while (next
!= NULL
);
7940 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7941 for (i
= 0; i
< ARRAY_SIZE (cpu_arch
); i
++)
7943 if (strcmp (arg
, cpu_arch
[i
].name
) == 0)
7945 cpu_arch_tune_set
= 1;
7946 cpu_arch_tune
= cpu_arch
[i
].type
;
7947 cpu_arch_tune_flags
= cpu_arch
[i
].flags
;
7951 if (i
>= ARRAY_SIZE (cpu_arch
))
7952 as_fatal (_("Invalid -mtune= option: `%s'"), arg
);
7955 case OPTION_MMNEMONIC
:
7956 if (strcasecmp (arg
, "att") == 0)
7958 else if (strcasecmp (arg
, "intel") == 0)
7961 as_fatal (_("Invalid -mmnemonic= option: `%s'"), arg
);
7964 case OPTION_MSYNTAX
:
7965 if (strcasecmp (arg
, "att") == 0)
7967 else if (strcasecmp (arg
, "intel") == 0)
7970 as_fatal (_("Invalid -msyntax= option: `%s'"), arg
);
7973 case OPTION_MINDEX_REG
:
7974 allow_index_reg
= 1;
7977 case OPTION_MNAKED_REG
:
7978 allow_naked_reg
= 1;
7981 case OPTION_MOLD_GCC
:
7985 case OPTION_MSSE2AVX
:
7989 case OPTION_MSSE_CHECK
:
7990 if (strcasecmp (arg
, "error") == 0)
7991 sse_check
= sse_check_error
;
7992 else if (strcasecmp (arg
, "warning") == 0)
7993 sse_check
= sse_check_warning
;
7994 else if (strcasecmp (arg
, "none") == 0)
7995 sse_check
= sse_check_none
;
7997 as_fatal (_("Invalid -msse-check= option: `%s'"), arg
);
8007 md_show_usage (stream
)
8010 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8011 fprintf (stream
, _("\
8013 -V print assembler version number\n\
8016 fprintf (stream
, _("\
8017 -n Do not optimize code alignment\n\
8018 -q quieten some warnings\n"));
8019 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8020 fprintf (stream
, _("\
8023 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8024 || defined (TE_PE) || defined (TE_PEP))
8025 fprintf (stream
, _("\
8026 --32/--64 generate 32bit/64bit code\n"));
8028 #ifdef SVR4_COMMENT_CHARS
8029 fprintf (stream
, _("\
8030 --divide do not treat `/' as a comment character\n"));
8032 fprintf (stream
, _("\
8033 --divide ignored\n"));
8035 fprintf (stream
, _("\
8036 -march=CPU[,+EXTENSION...]\n\
8037 generate code for CPU and EXTENSION, CPU is one of:\n\
8038 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8039 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8040 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8041 amdfam10, generic32, generic64\n\
8042 EXTENSION is combination of:\n\
8043 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3,\n\
8044 ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx,\n\
8045 vmx, smx, xsave, movbe, ept, aes, pclmul, fma,\n\
8046 clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a,\n\
8047 svme, abm, padlock, fma4, lwp\n"));
8048 fprintf (stream
, _("\
8049 -mtune=CPU optimize for CPU, CPU is one of:\n\
8050 i8086, i186, i286, i386, i486, pentium, pentiumpro,\n\
8051 pentiumii, pentiumiii, pentium4, prescott, nocona,\n\
8052 core, core2, corei7, l1om, k6, k6_2, athlon, k8,\n\
8053 amdfam10, generic32, generic64\n"));
8054 fprintf (stream
, _("\
8055 -msse2avx encode SSE instructions with VEX prefix\n"));
8056 fprintf (stream
, _("\
8057 -msse-check=[none|error|warning]\n\
8058 check SSE instructions\n"));
8059 fprintf (stream
, _("\
8060 -mmnemonic=[att|intel] use AT&T/Intel mnemonic\n"));
8061 fprintf (stream
, _("\
8062 -msyntax=[att|intel] use AT&T/Intel syntax\n"));
8063 fprintf (stream
, _("\
8064 -mindex-reg support pseudo index registers\n"));
8065 fprintf (stream
, _("\
8066 -mnaked-reg don't require `%%' prefix for registers\n"));
8067 fprintf (stream
, _("\
8068 -mold-gcc support old (<= 2.8.1) versions of gcc\n"));
8071 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
8072 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) \
8073 || defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O))
8075 /* Pick the target format to use. */
8078 i386_target_format (void)
8080 if (!strcmp (default_arch
, "x86_64"))
8082 set_code_flag (CODE_64BIT
);
8083 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8085 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8086 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8087 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8088 cpu_arch_isa_flags
.bitfield
.cpui486
= 1;
8089 cpu_arch_isa_flags
.bitfield
.cpui586
= 1;
8090 cpu_arch_isa_flags
.bitfield
.cpui686
= 1;
8091 cpu_arch_isa_flags
.bitfield
.cpuclflush
= 1;
8092 cpu_arch_isa_flags
.bitfield
.cpummx
= 1;
8093 cpu_arch_isa_flags
.bitfield
.cpusse
= 1;
8094 cpu_arch_isa_flags
.bitfield
.cpusse2
= 1;
8095 cpu_arch_isa_flags
.bitfield
.cpulm
= 1;
8097 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8099 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8100 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8101 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8102 cpu_arch_tune_flags
.bitfield
.cpui486
= 1;
8103 cpu_arch_tune_flags
.bitfield
.cpui586
= 1;
8104 cpu_arch_tune_flags
.bitfield
.cpui686
= 1;
8105 cpu_arch_tune_flags
.bitfield
.cpuclflush
= 1;
8106 cpu_arch_tune_flags
.bitfield
.cpummx
= 1;
8107 cpu_arch_tune_flags
.bitfield
.cpusse
= 1;
8108 cpu_arch_tune_flags
.bitfield
.cpusse2
= 1;
8111 else if (!strcmp (default_arch
, "i386"))
8113 set_code_flag (CODE_32BIT
);
8114 if (cpu_flags_all_zero (&cpu_arch_isa_flags
))
8116 cpu_arch_isa_flags
.bitfield
.cpui186
= 1;
8117 cpu_arch_isa_flags
.bitfield
.cpui286
= 1;
8118 cpu_arch_isa_flags
.bitfield
.cpui386
= 1;
8120 if (cpu_flags_all_zero (&cpu_arch_tune_flags
))
8122 cpu_arch_tune_flags
.bitfield
.cpui186
= 1;
8123 cpu_arch_tune_flags
.bitfield
.cpui286
= 1;
8124 cpu_arch_tune_flags
.bitfield
.cpui386
= 1;
8128 as_fatal (_("Unknown architecture"));
8129 switch (OUTPUT_FLAVOR
)
8131 #if defined (OBJ_MAYBE_AOUT) || defined (OBJ_AOUT)
8132 case bfd_target_aout_flavour
:
8133 return AOUT_TARGET_FORMAT
;
8135 #if defined (OBJ_MAYBE_COFF) || defined (OBJ_COFF)
8136 # if defined (TE_PE) || defined (TE_PEP)
8137 case bfd_target_coff_flavour
:
8138 return flag_code
== CODE_64BIT
? "pe-x86-64" : "pe-i386";
8139 # elif defined (TE_GO32)
8140 case bfd_target_coff_flavour
:
8143 case bfd_target_coff_flavour
:
8147 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
8148 case bfd_target_elf_flavour
:
8150 if (flag_code
== CODE_64BIT
)
8153 use_rela_relocations
= 1;
8155 if (cpu_arch_isa
== PROCESSOR_L1OM
)
8157 if (flag_code
!= CODE_64BIT
)
8158 as_fatal (_("Intel L1OM is 64bit only"));
8159 return ELF_TARGET_L1OM_FORMAT
;
8162 return (flag_code
== CODE_64BIT
8163 ? ELF_TARGET_FORMAT64
: ELF_TARGET_FORMAT
);
8166 #if defined (OBJ_MACH_O)
8167 case bfd_target_mach_o_flavour
:
8168 return flag_code
== CODE_64BIT
? "mach-o-x86-64" : "mach-o-i386";
8176 #endif /* OBJ_MAYBE_ more than one */
8178 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
8180 i386_elf_emit_arch_note (void)
8182 if (IS_ELF
&& cpu_arch_name
!= NULL
)
8185 asection
*seg
= now_seg
;
8186 subsegT subseg
= now_subseg
;
8187 Elf_Internal_Note i_note
;
8188 Elf_External_Note e_note
;
8189 asection
*note_secp
;
8192 /* Create the .note section. */
8193 note_secp
= subseg_new (".note", 0);
8194 bfd_set_section_flags (stdoutput
,
8196 SEC_HAS_CONTENTS
| SEC_READONLY
);
8198 /* Process the arch string. */
8199 len
= strlen (cpu_arch_name
);
8201 i_note
.namesz
= len
+ 1;
8203 i_note
.type
= NT_ARCH
;
8204 p
= frag_more (sizeof (e_note
.namesz
));
8205 md_number_to_chars (p
, (valueT
) i_note
.namesz
, sizeof (e_note
.namesz
));
8206 p
= frag_more (sizeof (e_note
.descsz
));
8207 md_number_to_chars (p
, (valueT
) i_note
.descsz
, sizeof (e_note
.descsz
));
8208 p
= frag_more (sizeof (e_note
.type
));
8209 md_number_to_chars (p
, (valueT
) i_note
.type
, sizeof (e_note
.type
));
8210 p
= frag_more (len
+ 1);
8211 strcpy (p
, cpu_arch_name
);
8213 frag_align (2, 0, 0);
8215 subseg_set (seg
, subseg
);
8221 md_undefined_symbol (name
)
8224 if (name
[0] == GLOBAL_OFFSET_TABLE_NAME
[0]
8225 && name
[1] == GLOBAL_OFFSET_TABLE_NAME
[1]
8226 && name
[2] == GLOBAL_OFFSET_TABLE_NAME
[2]
8227 && strcmp (name
, GLOBAL_OFFSET_TABLE_NAME
) == 0)
8231 if (symbol_find (name
))
8232 as_bad (_("GOT already in symbol table"));
8233 GOT_symbol
= symbol_new (name
, undefined_section
,
8234 (valueT
) 0, &zero_address_frag
);
8241 /* Round up a section size to the appropriate boundary. */
8244 md_section_align (segment
, size
)
8245 segT segment ATTRIBUTE_UNUSED
;
8248 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
8249 if (OUTPUT_FLAVOR
== bfd_target_aout_flavour
)
8251 /* For a.out, force the section size to be aligned. If we don't do
8252 this, BFD will align it for us, but it will not write out the
8253 final bytes of the section. This may be a bug in BFD, but it is
8254 easier to fix it here since that is how the other a.out targets
8258 align
= bfd_get_section_alignment (stdoutput
, segment
);
8259 size
= ((size
+ (1 << align
) - 1) & ((valueT
) -1 << align
));
8266 /* On the i386, PC-relative offsets are relative to the start of the
8267 next instruction. That is, the address of the offset, plus its
8268 size, since the offset is always the last part of the insn. */
8271 md_pcrel_from (fixS
*fixP
)
8273 return fixP
->fx_size
+ fixP
->fx_where
+ fixP
->fx_frag
->fr_address
;
8279 s_bss (int ignore ATTRIBUTE_UNUSED
)
8283 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8285 obj_elf_section_change_hook ();
8287 temp
= get_absolute_expression ();
8288 subseg_set (bss_section
, (subsegT
) temp
);
8289 demand_empty_rest_of_line ();
8295 i386_validate_fix (fixS
*fixp
)
8297 if (fixp
->fx_subsy
&& fixp
->fx_subsy
== GOT_symbol
)
8299 if (fixp
->fx_r_type
== BFD_RELOC_32_PCREL
)
8303 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTPCREL
;
8308 fixp
->fx_r_type
= BFD_RELOC_386_GOTOFF
;
8310 fixp
->fx_r_type
= BFD_RELOC_X86_64_GOTOFF64
;
8317 tc_gen_reloc (section
, fixp
)
8318 asection
*section ATTRIBUTE_UNUSED
;
8322 bfd_reloc_code_real_type code
;
8324 switch (fixp
->fx_r_type
)
8326 case BFD_RELOC_X86_64_PLT32
:
8327 case BFD_RELOC_X86_64_GOT32
:
8328 case BFD_RELOC_X86_64_GOTPCREL
:
8329 case BFD_RELOC_386_PLT32
:
8330 case BFD_RELOC_386_GOT32
:
8331 case BFD_RELOC_386_GOTOFF
:
8332 case BFD_RELOC_386_GOTPC
:
8333 case BFD_RELOC_386_TLS_GD
:
8334 case BFD_RELOC_386_TLS_LDM
:
8335 case BFD_RELOC_386_TLS_LDO_32
:
8336 case BFD_RELOC_386_TLS_IE_32
:
8337 case BFD_RELOC_386_TLS_IE
:
8338 case BFD_RELOC_386_TLS_GOTIE
:
8339 case BFD_RELOC_386_TLS_LE_32
:
8340 case BFD_RELOC_386_TLS_LE
:
8341 case BFD_RELOC_386_TLS_GOTDESC
:
8342 case BFD_RELOC_386_TLS_DESC_CALL
:
8343 case BFD_RELOC_X86_64_TLSGD
:
8344 case BFD_RELOC_X86_64_TLSLD
:
8345 case BFD_RELOC_X86_64_DTPOFF32
:
8346 case BFD_RELOC_X86_64_DTPOFF64
:
8347 case BFD_RELOC_X86_64_GOTTPOFF
:
8348 case BFD_RELOC_X86_64_TPOFF32
:
8349 case BFD_RELOC_X86_64_TPOFF64
:
8350 case BFD_RELOC_X86_64_GOTOFF64
:
8351 case BFD_RELOC_X86_64_GOTPC32
:
8352 case BFD_RELOC_X86_64_GOT64
:
8353 case BFD_RELOC_X86_64_GOTPCREL64
:
8354 case BFD_RELOC_X86_64_GOTPC64
:
8355 case BFD_RELOC_X86_64_GOTPLT64
:
8356 case BFD_RELOC_X86_64_PLTOFF64
:
8357 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8358 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8360 case BFD_RELOC_VTABLE_ENTRY
:
8361 case BFD_RELOC_VTABLE_INHERIT
:
8363 case BFD_RELOC_32_SECREL
:
8365 code
= fixp
->fx_r_type
;
8367 case BFD_RELOC_X86_64_32S
:
8368 if (!fixp
->fx_pcrel
)
8370 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
8371 code
= fixp
->fx_r_type
;
8377 switch (fixp
->fx_size
)
8380 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8381 _("can not do %d byte pc-relative relocation"),
8383 code
= BFD_RELOC_32_PCREL
;
8385 case 1: code
= BFD_RELOC_8_PCREL
; break;
8386 case 2: code
= BFD_RELOC_16_PCREL
; break;
8387 case 4: code
= BFD_RELOC_32_PCREL
; break;
8389 case 8: code
= BFD_RELOC_64_PCREL
; break;
8395 switch (fixp
->fx_size
)
8398 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8399 _("can not do %d byte relocation"),
8401 code
= BFD_RELOC_32
;
8403 case 1: code
= BFD_RELOC_8
; break;
8404 case 2: code
= BFD_RELOC_16
; break;
8405 case 4: code
= BFD_RELOC_32
; break;
8407 case 8: code
= BFD_RELOC_64
; break;
8414 if ((code
== BFD_RELOC_32
8415 || code
== BFD_RELOC_32_PCREL
8416 || code
== BFD_RELOC_X86_64_32S
)
8418 && fixp
->fx_addsy
== GOT_symbol
)
8421 code
= BFD_RELOC_386_GOTPC
;
8423 code
= BFD_RELOC_X86_64_GOTPC32
;
8425 if ((code
== BFD_RELOC_64
|| code
== BFD_RELOC_64_PCREL
)
8427 && fixp
->fx_addsy
== GOT_symbol
)
8429 code
= BFD_RELOC_X86_64_GOTPC64
;
8432 rel
= (arelent
*) xmalloc (sizeof (arelent
));
8433 rel
->sym_ptr_ptr
= (asymbol
**) xmalloc (sizeof (asymbol
*));
8434 *rel
->sym_ptr_ptr
= symbol_get_bfdsym (fixp
->fx_addsy
);
8436 rel
->address
= fixp
->fx_frag
->fr_address
+ fixp
->fx_where
;
8438 if (!use_rela_relocations
)
8440 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
8441 vtable entry to be used in the relocation's section offset. */
8442 if (fixp
->fx_r_type
== BFD_RELOC_VTABLE_ENTRY
)
8443 rel
->address
= fixp
->fx_offset
;
8444 #if defined (OBJ_COFF) && defined (TE_PE)
8445 else if (fixp
->fx_addsy
&& S_IS_WEAK (fixp
->fx_addsy
))
8446 rel
->addend
= fixp
->fx_addnumber
- (S_GET_VALUE (fixp
->fx_addsy
) * 2);
8451 /* Use the rela in 64bit mode. */
8454 if (!fixp
->fx_pcrel
)
8455 rel
->addend
= fixp
->fx_offset
;
8459 case BFD_RELOC_X86_64_PLT32
:
8460 case BFD_RELOC_X86_64_GOT32
:
8461 case BFD_RELOC_X86_64_GOTPCREL
:
8462 case BFD_RELOC_X86_64_TLSGD
:
8463 case BFD_RELOC_X86_64_TLSLD
:
8464 case BFD_RELOC_X86_64_GOTTPOFF
:
8465 case BFD_RELOC_X86_64_GOTPC32_TLSDESC
:
8466 case BFD_RELOC_X86_64_TLSDESC_CALL
:
8467 rel
->addend
= fixp
->fx_offset
- fixp
->fx_size
;
8470 rel
->addend
= (section
->vma
8472 + fixp
->fx_addnumber
8473 + md_pcrel_from (fixp
));
8478 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, code
);
8479 if (rel
->howto
== NULL
)
8481 as_bad_where (fixp
->fx_file
, fixp
->fx_line
,
8482 _("cannot represent relocation type %s"),
8483 bfd_get_reloc_code_name (code
));
8484 /* Set howto to a garbage value so that we can keep going. */
8485 rel
->howto
= bfd_reloc_type_lookup (stdoutput
, BFD_RELOC_32
);
8486 gas_assert (rel
->howto
!= NULL
);
8492 #include "tc-i386-intel.c"
8495 tc_x86_parse_to_dw2regnum (expressionS
*exp
)
8497 int saved_naked_reg
;
8498 char saved_register_dot
;
8500 saved_naked_reg
= allow_naked_reg
;
8501 allow_naked_reg
= 1;
8502 saved_register_dot
= register_chars
['.'];
8503 register_chars
['.'] = '.';
8504 allow_pseudo_reg
= 1;
8505 expression_and_evaluate (exp
);
8506 allow_pseudo_reg
= 0;
8507 register_chars
['.'] = saved_register_dot
;
8508 allow_naked_reg
= saved_naked_reg
;
8510 if (exp
->X_op
== O_register
&& exp
->X_add_number
>= 0)
8512 if ((addressT
) exp
->X_add_number
< i386_regtab_size
)
8514 exp
->X_op
= O_constant
;
8515 exp
->X_add_number
= i386_regtab
[exp
->X_add_number
]
8516 .dw2_regnum
[flag_code
>> 1];
8519 exp
->X_op
= O_illegal
;
8524 tc_x86_frame_initial_instructions (void)
8526 static unsigned int sp_regno
[2];
8528 if (!sp_regno
[flag_code
>> 1])
8530 char *saved_input
= input_line_pointer
;
8531 char sp
[][4] = {"esp", "rsp"};
8534 input_line_pointer
= sp
[flag_code
>> 1];
8535 tc_x86_parse_to_dw2regnum (&exp
);
8536 gas_assert (exp
.X_op
== O_constant
);
8537 sp_regno
[flag_code
>> 1] = exp
.X_add_number
;
8538 input_line_pointer
= saved_input
;
8541 cfi_add_CFA_def_cfa (sp_regno
[flag_code
>> 1], -x86_cie_data_alignment
);
8542 cfi_add_CFA_offset (x86_dwarf2_return_column
, x86_cie_data_alignment
);
8546 i386_elf_section_type (const char *str
, size_t len
)
8548 if (flag_code
== CODE_64BIT
8549 && len
== sizeof ("unwind") - 1
8550 && strncmp (str
, "unwind", 6) == 0)
8551 return SHT_X86_64_UNWIND
;
8558 i386_solaris_fix_up_eh_frame (segT sec
)
8560 if (flag_code
== CODE_64BIT
)
8561 elf_section_type (sec
) = SHT_X86_64_UNWIND
;
8567 tc_pe_dwarf2_emit_offset (symbolS
*symbol
, unsigned int size
)
8571 expr
.X_op
= O_secrel
;
8572 expr
.X_add_symbol
= symbol
;
8573 expr
.X_add_number
= 0;
8574 emit_expr (&expr
, size
);
8578 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
8579 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
8582 x86_64_section_letter (int letter
, char **ptr_msg
)
8584 if (flag_code
== CODE_64BIT
)
8587 return SHF_X86_64_LARGE
;
8589 *ptr_msg
= _("Bad .section directive: want a,l,w,x,M,S,G,T in string");
8592 *ptr_msg
= _("Bad .section directive: want a,w,x,M,S,G,T in string");
8597 x86_64_section_word (char *str
, size_t len
)
8599 if (len
== 5 && flag_code
== CODE_64BIT
&& CONST_STRNEQ (str
, "large"))
8600 return SHF_X86_64_LARGE
;
8606 handle_large_common (int small ATTRIBUTE_UNUSED
)
8608 if (flag_code
!= CODE_64BIT
)
8610 s_comm_internal (0, elf_common_parse
);
8611 as_warn (_(".largecomm supported only in 64bit mode, producing .comm"));
8615 static segT lbss_section
;
8616 asection
*saved_com_section_ptr
= elf_com_section_ptr
;
8617 asection
*saved_bss_section
= bss_section
;
8619 if (lbss_section
== NULL
)
8621 flagword applicable
;
8623 subsegT subseg
= now_subseg
;
8625 /* The .lbss section is for local .largecomm symbols. */
8626 lbss_section
= subseg_new (".lbss", 0);
8627 applicable
= bfd_applicable_section_flags (stdoutput
);
8628 bfd_set_section_flags (stdoutput
, lbss_section
,
8629 applicable
& SEC_ALLOC
);
8630 seg_info (lbss_section
)->bss
= 1;
8632 subseg_set (seg
, subseg
);
8635 elf_com_section_ptr
= &_bfd_elf_large_com_section
;
8636 bss_section
= lbss_section
;
8638 s_comm_internal (0, elf_common_parse
);
8640 elf_com_section_ptr
= saved_com_section_ptr
;
8641 bss_section
= saved_bss_section
;
8644 #endif /* OBJ_ELF || OBJ_MAYBE_ELF */