firmware/target/arm/system-pp502x.c

   1 /***************************************************************************
   2  *             __________               __   ___.
   3  *   Open      \______   \ ____   ____ |  | _\_ |__   _______  ___
   4  *   Source     |       _//  _ \_/ ___\|  |/ /| __ \ /  _ \  \/  /
   5  *   Jukebox    |    |   (  <_> )  \___|    < | \_\ (  <_> > <  <
   6  *   Firmware   |____|_  /\____/ \___  >__|_ \|___  /\____/__/\_ \
   7  *                     \/            \/     \/    \/            \/
   8  * $Id$
   9  *
  10  * Copyright (C) 2002 by Alan Korr
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License
  14  * as published by the Free Software Foundation; either version 2
  15  * of the License, or (at your option) any later version.
  16  *
  17  * This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
  18  * KIND, either express or implied.
  19  *
  20  ****************************************************************************/
  21 #include "system.h"
  22 #include "thread.h"
  23 #include "i2s.h"
  24 #include "i2c-pp.h"
  25 #include "as3514.h"
  26 #include "ata-sd-target.h"
  27 #ifdef HAVE_USBSTACK
  28 #include "usb_drv.h"
  29 #endif
  30
  31 #ifndef BOOTLOADER
  32 extern void TIMER1(void);
  33 extern void TIMER2(void);
  34 extern void ipod_mini_button_int(void); /* iPod Mini 1st gen only */
  35 extern void ipod_4g_button_int(void);   /* iPod 4th gen and higher only */
  36 #ifdef SANSA_E200
  37 extern void button_int(void);
  38 extern void clickwheel_int(void);
  39 #endif
  40 #ifdef MROBE_100
  41 extern void button_int(void);
  42 #endif
  43
  44 void irq(void)
  45 {
  46     if(CURRENT_CORE == CPU)
  47     {
  48         if (CPU_INT_STAT & TIMER1_MASK) {
  49             TIMER1();
  50         } else if (CPU_INT_STAT & TIMER2_MASK)
  51             TIMER2();
  52 #if defined(IPOD_MINI) /* Mini 1st gen only, mini 2nd gen uses iPod 4G code */
  53         else if (CPU_HI_INT_STAT & GPIO0_MASK)
  54             ipod_mini_button_int();
  55 #elif CONFIG_KEYPAD == IPOD_4G_PAD /* except Mini 1st gen, handled above */
  56         else if (CPU_HI_INT_STAT & I2C_MASK)
  57             ipod_4g_button_int();
  58 #elif defined(SANSA_E200)
  59 #ifdef HAVE_HOTSWAP
  60         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  61             if (GPIOA_INT_STAT & 0x80)
  62                 microsd_int();
  63         }
  64 #endif
  65         else if (CPU_HI_INT_STAT & GPIO1_MASK) {
  66             if (GPIOF_INT_STAT & 0xff)
  67                 button_int();
  68             if (GPIOH_INT_STAT & 0xc0)
  69                 clickwheel_int();
  70         }
  71 #elif defined(SANSA_C200) && defined(HAVE_HOTSWAP)
  72         else if (CPU_HI_INT_STAT & GPIO2_MASK) {
  73             if (GPIOL_INT_STAT & 0x08)
  74                 microsd_int();
  75         }
  76 #elif defined(MROBE_100)
  77         else if (CPU_HI_INT_STAT & GPIO0_MASK) {
  78             if (GPIOD_INT_STAT & 0x2)
  79                 button_int();
  80         }
  81 #endif
  82 #ifdef HAVE_USBSTACK
  83         else if (CPU_INT_STAT & USB_MASK) {
  84             usb_drv_int();
  85         }
  86 #endif
  87     } else {
  88         if (COP_INT_STAT & TIMER2_MASK)
  89             TIMER2();
  90     }
  91 }
  92 #endif /* BOOTLOADER */
  93
  94 /* TODO: The following function has been lifted straight from IPL, and
  95    hence has a lot of numeric addresses used straight. I'd like to use
  96    #defines for these, but don't know what most of them are for or even what
  97    they should be named. Because of this I also have no way of knowing how
  98    to extend the funtions to do alternate cache configurations. */
  99
 100 #ifndef BOOTLOADER
 101 void flush_icache(void) ICODE_ATTR;
 102 void flush_icache(void)
 103 {
 104     if (CACHE_CTL & CACHE_CTL_ENABLE)
 105     {
 106         CACHE_OPERATION |= CACHE_OP_FLUSH;
 107         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
 108     }
 109 }
 110
 111 void invalidate_icache(void) ICODE_ATTR;
 112 void invalidate_icache(void)
 113 {
 114     if (CACHE_CTL & CACHE_CTL_ENABLE)
 115     {
 116         CACHE_OPERATION |= CACHE_OP_FLUSH | CACHE_OP_INVALIDATE;
 117         while ((CACHE_CTL & CACHE_CTL_BUSY) != 0);
 118         nop; nop; nop; nop;
 119     }
 120 }
 121
 122 static void init_cache(void)
 123 {
 124 /* Initialising the cache in the iPod bootloader prevents Rockbox from starting */
 125
 126     /* cache init mode */
 127     CACHE_CTL |= CACHE_CTL_INIT;
 128
 129     /* what's this do? */
 130     CACHE_PRIORITY |= CURRENT_CORE == CPU ? 0x10 : 0x20;
 131
 132     /* Cache if (addr & mask) >> 16 == (mask & match) >> 16:
 133      * yes: 0x00000000 - 0x03ffffff
 134      *  no: 0x04000000 - 0x1fffffff
 135      * yes: 0x20000000 - 0x23ffffff
 136      *  no: 0x24000000 - 0x3fffffff
 137      */
 138     CACHE_MASK = 0x00001c00;
 139     CACHE_OPERATION = 0xfc0;
 140
 141     /* enable cache */
 142     CACHE_CTL |= CACHE_CTL_INIT | CACHE_CTL_ENABLE | CACHE_CTL_RUN;
 143     nop; nop; nop; nop;
 144 }
 145 #endif /* !BOOTLOADER */
 146
 147 /* We need this for Sansas since we boost the cpu in their bootloader */
 148 #if !defined(BOOTLOADER) || defined(SANSA_E200) || defined(SANSA_C200)
 149 void scale_suspend_core(bool suspend) ICODE_ATTR;
 150 void scale_suspend_core(bool suspend)
 151 {
 152     unsigned int core = CURRENT_CORE;
 153     IF_COP( unsigned int othercore = 1 - core; )
 154     static int oldstatus IBSS_ATTR;
 155
 156     if (suspend)
 157     {
 158         oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
 159         IF_COP( PROC_CTL(othercore) = 0x40000000; nop; )
 160         PROC_CTL(core) = 0x48000003; nop;
 161     }
 162     else
 163     {
 164         PROC_CTL(core) = 0x4800001f; nop;
 165         IF_COP( PROC_CTL(othercore) = 0x00000000; nop; )
 166         restore_interrupt(oldstatus);
 167     }
 168 }
 169
 170 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 171 void set_cpu_frequency(long frequency) ICODE_ATTR;
 172 void set_cpu_frequency(long frequency)
 173 #else
 174 static void pp_set_cpu_frequency(long frequency)
 175 #endif
 176 {
 177 #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
 178     spinlock_lock(&boostctrl_spin);
 179 #endif
 180
 181     switch (frequency)
 182     {
 183       /* Note1: The PP5022 PLL must be run at >= 96MHz
 184        * Bits 20..21 select the post divider (1/2/4/8).
 185        * PP5026 is similar to PP5022 except it doesn't
 186        * have this limitation (and the post divider?)
 187        * Note2: CLOCK_SOURCE is set via 0=32kHz, 1=16MHz,
 188        * 2=24MHz, 3=33MHz, 4=48MHz, 5=SLOW, 6=FAST, 7=PLL.
 189        * SLOW = 24MHz / (DIV_SLOW + 1), DIV = Bits 16-19
 190        * FAST = PLL   / (DIV_FAST + 1), DIV = Bits 20-23 */
 191       case CPUFREQ_SLEEP:
 192         cpu_frequency =  CPUFREQ_SLEEP;
 193         PLL_CONTROL  |=  0x0c000000;
 194         scale_suspend_core(true);
 195         CLOCK_SOURCE  =  0x20000000; /* source #1, #2, #3, #4: 32kHz (#2 active) */
 196         scale_suspend_core(false);
 197         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 198         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 199         break;
 200
 201       case CPUFREQ_MAX:
 202         cpu_frequency = CPUFREQ_MAX;
 203         DEV_INIT2    |= INIT_PLL;   /* enable PLL power */
 204         PLL_CONTROL  |= 0x88000000; /* enable PLL */
 205         scale_suspend_core(true);
 206         CLOCK_SOURCE  = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 207         DEV_TIMING1   = 0x00000303;
 208         scale_suspend_core(false);
 209 #if   defined(IPOD_MINI2G)
 210         MLCD_SCLK_DIV = 0x00000001; /* Mono LCD bridge serial clock divider */
 211 #elif defined(IPOD_NANO)
 212         IDE0_CFG     |= 0x10000000; /* set ">65MHz" bit */
 213 #endif
 214 #if CONFIG_CPU == PP5020
 215         PLL_CONTROL   = 0x8a020a03; /* 80 MHz = 10/3 * 24MHz */
 216         PLL_STATUS    = 0xd19b;     /* unlock frequencies > 66MHz */
 217         PLL_CONTROL   = 0x8a020a03; /* repeat setup */
 218         udelay(500);                /* wait for relock */
 219 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
 220         PLL_CONTROL   = 0x8a121403; /*  80 MHz = (20/3 * 24MHz) / 2 */
 221         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
 222 #endif
 223         scale_suspend_core(true);
 224         DEV_TIMING1   = 0x00000808;
 225         CLOCK_SOURCE  = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
 226         scale_suspend_core(false);
 227         break;
 228 #if 0 /******** CPUFREQ_NORMAL = 24MHz without PLL ********/
 229       case CPUFREQ_NORMAL:
 230         cpu_frequency =  CPUFREQ_NORMAL;
 231         PLL_CONTROL  |=  0x08000000;
 232         scale_suspend_core(true);
 233         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 234         DEV_TIMING1   =  0x00000303;
 235 #if   defined(IPOD_MINI2G)
 236         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 237 #elif defined(IPOD_NANO)
 238         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 239 #endif
 240         scale_suspend_core(false);
 241         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 242         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 243         break;
 244 #else /******** CPUFREQ_NORMAL = 30MHz with PLL ********/
 245     case CPUFREQ_NORMAL:
 246         cpu_frequency = CPUFREQ_NORMAL;
 247         DEV_INIT2    |= INIT_PLL;   /* enable PLL power */
 248         PLL_CONTROL  |= 0x88000000; /* enable PLL */
 249         scale_suspend_core(true);
 250         CLOCK_SOURCE  = 0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 251         DEV_TIMING1   = 0x00000303;
 252         scale_suspend_core(false);
 253 #if   defined(IPOD_MINI2G)
 254         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 255 #elif defined(IPOD_NANO)
 256         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 257 #endif
 258 #if CONFIG_CPU == PP5020
 259         PLL_CONTROL   = 0x8a020504; /* 30 MHz = 5/4 * 24MHz */
 260         udelay(500);                /* wait for relock */
 261 #elif (CONFIG_CPU == PP5022) || (CONFIG_CPU == PP5024)
 262         PLL_CONTROL   = 0x8a220501; /* 30 MHz = (5/1 * 24MHz) / 4 */
 263         while (!(PLL_STATUS & 0x80000000)); /* wait for relock */
 264 #endif
 265         scale_suspend_core(true);
 266         DEV_TIMING1   = 0x00000303;
 267         CLOCK_SOURCE  = 0x20007777; /* source #1, #2, #3, #4: PLL (#2 active) */
 268         scale_suspend_core(false);
 269         break;
 270 #endif /******** CPUFREQ_NORMAL end ********/
 271       default:
 272         cpu_frequency =  CPUFREQ_DEFAULT;
 273         PLL_CONTROL  |=  0x08000000;
 274         scale_suspend_core(true);
 275         CLOCK_SOURCE  =  0x20002222; /* source #1, #2, #3, #4: 24MHz (#2 active) */
 276         DEV_TIMING1   =  0x00000303;
 277 #if   defined(IPOD_MINI2G)
 278         MLCD_SCLK_DIV =  0x00000000; /* Mono LCD bridge serial clock divider */
 279 #elif defined(IPOD_NANO)
 280         IDE0_CFG     &= ~0x10000000; /* clear ">65MHz" bit */
 281 #endif
 282         scale_suspend_core(false);
 283         PLL_CONTROL  &= ~0x80000000; /* disable PLL */
 284         DEV_INIT2    &= ~INIT_PLL;   /* disable PLL power */
 285         break;
 286     }
 287
 288 #if defined(HAVE_ADJUSTABLE_CPU_FREQ) && (NUM_CORES > 1)
 289     spinlock_unlock(&boostctrl_spin);
 290 #endif
 291 }
 292 #endif /* !BOOTLOADER || SANSA_E200 || SANSA_C200 */
 293
 294 void system_init(void)
 295 {
 296 #ifndef BOOTLOADER
 297     if (CURRENT_CORE == CPU)
 298     {
 299 #if defined (IRIVER_H10) || defined(IRIVER_H10_5GB) || defined(IPOD_COLOR)
 300         /* set minimum startup configuration */
 301         DEV_EN         = 0xc2000124;
 302         DEV_EN2        = 0x00002000;
 303         CACHE_PRIORITY = 0x0000003f;
 304         GPO32_VAL      = 0x20000000;
 305         DEV_INIT1      = 0xdc000000;
 306         DEV_INIT2      = 0x40000000;
 307
 308         /* reset all allowed devices */
 309         DEV_RS         = 0x3ffffef8;
 310         DEV_RS2        = 0xffffdfff;
 311         DEV_RS         = 0x00000000;
 312         DEV_RS2        = 0x00000000;
 313 #elif defined (IPOD_VIDEO)
 314         /* set minimum startup configuration */
 315         DEV_EN         = 0xc2000124;
 316         DEV_EN2        = 0x00000000;
 317         CACHE_PRIORITY = 0x0000003f;
 318         GPO32_VAL      = 0x00004000;
 319         DEV_INIT1      = 0x00000000;
 320         DEV_INIT2      = 0x40000000;
 321
 322         /* reset all allowed devices */
 323         DEV_RS         = 0x3ffffef8;
 324         DEV_RS2        = 0xffffffff;
 325         DEV_RS         = 0x00000000;
 326         DEV_RS2        = 0x00000000;
 327 #elif defined (IPOD_NANO)
 328         /* set minimum startup configuration */
 329         DEV_EN         = 0xc2000124;
 330         DEV_EN2        = 0x00002000;
 331         CACHE_PRIORITY = 0x0000003f;
 332         GPO32_VAL      = 0x50000000;
 333         DEV_INIT1      = 0xa8000000;
 334         DEV_INIT2      = 0x40000000;
 335
 336         /* reset all allowed devices */
 337         DEV_RS         = 0x3ffffef8;
 338         DEV_RS2        = 0xffffdfff;
 339         DEV_RS         = 0x00000000;
 340         DEV_RS2        = 0x00000000;
 341 #elif defined(SANSA_C200) || defined (SANSA_E200)
 342         /* set minimum startup configuration */
 343         DEV_EN         = 0xc4000124;
 344         DEV_EN2        = 0x00000000;
 345         CACHE_PRIORITY = 0x0000003f;
 346         GPO32_VAL      = 0x10000000;
 347         DEV_INIT1      = 0x54000000;
 348         DEV_INIT2      = 0x40000000;
 349
 350         /* reset all allowed devices */
 351         DEV_RS         = 0x3bfffef8;
 352         DEV_RS2        = 0xffffffff;
 353         DEV_RS         = 0x00000000;
 354         DEV_RS2        = 0x00000000;
 355 #elif defined(IPOD_4G)
 356         /* set minimum startup configuration */
 357         DEV_EN         = 0xc2020124;
 358         DEV_EN2        = 0x00000000;
 359         CACHE_PRIORITY = 0x0000003f;
 360         GPO32_VAL      = 0x02000000;
 361         DEV_INIT1      = 0x00000000;
 362         DEV_INIT2      = 0x40000000;
 363
 364         /* reset all allowed devices */
 365         DEV_RS         = 0x3ffdfef8;
 366         DEV_RS2        = 0xffffffff;
 367         DEV_RS         = 0x00000000;
 368         DEV_RS2        = 0x00000000;
 369 #elif defined (IPOD_MINI)
 370         /* to be done */
 371 #elif defined (IPOD_MINI2G)
 372         /* to be done */
 373 #elif defined (MROBE_100)
 374         /* to be done */
 375 #elif defined (ELIO_TPJ1022)
 376         /* to be done */
 377 #endif
 378
 379 #if !defined(SANSA_E200) && !defined(SANSA_C200) && !defined(PHILIPS_SA9200)
 380         /* Remap the flash ROM on CPU, keep hidden from COP:
 381          * 0x00000000-0x3fffffff = 0x20000000-0x23ffffff */
 382         MMAP1_LOGICAL  = 0x20003c00;
 383         MMAP1_PHYSICAL = 0x00003084 |
 384             MMAP_PHYS_READ_MASK | MMAP_PHYS_WRITE_MASK |
 385             MMAP_PHYS_DATA_MASK | MMAP_PHYS_CODE_MASK;
 386 #endif
 387
 388         /* disable all irqs */
 389         COP_HI_INT_DIS      = -1;
 390         CPU_HI_INT_DIS      = -1;
 391         HI_INT_FORCED_CLR   = -1;
 392
 393         COP_INT_DIS         = -1;
 394         CPU_INT_DIS         = -1;
 395         INT_FORCED_CLR      = -1;
 396
 397         GPIOA_INT_EN        = 0;
 398         GPIOB_INT_EN        = 0;
 399         GPIOC_INT_EN        = 0;
 400         GPIOD_INT_EN        = 0;
 401         GPIOE_INT_EN        = 0;
 402         GPIOF_INT_EN        = 0;
 403         GPIOG_INT_EN        = 0;
 404         GPIOH_INT_EN        = 0;
 405         GPIOI_INT_EN        = 0;
 406         GPIOJ_INT_EN        = 0;
 407         GPIOK_INT_EN        = 0;
 408         GPIOL_INT_EN        = 0;
 409
 410 #if defined(SANSA_E200) || defined(SANSA_C200) || defined(PHILIPS_SA9200)
 411         /* outl(0x00000000, 0x6000b000); */
 412         outl(inl(0x6000a000) | 0x80000000, 0x6000a000); /* Init DMA controller? */
 413 #endif
 414
 415 #ifdef HAVE_ADJUSTABLE_CPU_FREQ
 416 #if NUM_CORES > 1
 417         cpu_boost_init();
 418 #endif
 419 #else
 420         pp_set_cpu_frequency(CPUFREQ_MAX);
 421 #endif
 422     }
 423
 424     init_cache();
 425 #else /* BOOTLOADER */
 426     if (CURRENT_CORE == CPU)
 427     {
 428 #if defined(SANSA_C200) || defined (SANSA_E200)
 429         pp_set_cpu_frequency(CPUFREQ_MAX);
 430 #endif
 431     }
 432 #endif /* BOOTLOADER */
 433 }
 434
 435 void system_reboot(void)
 436 {
 437     /* Reboot */
 438 #if defined(SANSA_E200) || defined(SANSA_C200) || defined(PHILIPS_SA9200)
 439     CACHE_CTL &= ~CACHE_CTL_VECT_REMAP;
 440
 441     /* Magic used by the c200 OF: 0x23066000
 442        Magic used by the c200 BL: 0x23066b7b
 443        In both cases, the OF executes these 2 commands from iram. */
 444     STRAP_OPT_A = 0x23066b7b;
 445     DEV_RS = DEV_SYSTEM;
 446 #else
 447     DEV_RS |= DEV_SYSTEM;
 448 #endif
 449     /* wait until reboot kicks in */
 450     while (1);
 451 }
 452
 453 int system_memory_guard(int newmode)
 454 {
 455     (void)newmode;
 456     return 0;
 457 }