| commit | 07c70969d029449689bd14da3bce27e5ecd37b1f | |
| author | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Thu, 6 Nov 2014 21:16:06 +0000 (6 21:16 +0000) | ||
| committer | DizzyOfCRN <DizzyOfCRN@fb15a70f-31f2-0310-bbcc-cdcc74a49acc> | |
| Thu, 6 Nov 2014 21:16:06 +0000 (6 21:16 +0000) | ||
| tree | 9251ce6354198ebf89b89c560872bd6084b4fe8d | treesnapshot (tar.gz zip) |
| parent | 2210f1fab1c073f267f88c2986384bf01c309415 | commitdiff |
Set PLL1(CPU) and PLL5(SDRAM) at the same time and do a combined delay with 24MHz CPU clock.
Some tests pumping up the DDR3 clock on pcDuino, Hynix DDR3 chips are more than capable of higher frequencies but the board may limit the speed. Although it seems to be nicely routed and memory chips are really close to the A10.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49766 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
Some tests pumping up the DDR3 clock on pcDuino, Hynix DDR3 chips are more than capable of higher frequencies but the board may limit the speed. Although it seems to be nicely routed and memory chips are really close to the A10.
git-svn-id: https://svn.aros.org/svn/aros/trunk/AROS@49766 fb15a70f-31f2-0310-bbcc-cdcc74a49acc
| arch/arm-sun4i/bootstrap/bootstrap.c | diffblobblamehistory |