arch/ppc-all/exec/cachecleare.c

   1 /*
   2     Copyright © 1995-2010, The AROS Development Team. All rights reserved.
   3     $Id$
   4
   5     Desc: CacheClearE() - Clear the caches with extended control.
   6     Lang: english
   7 */
   8
   9 #include <aros/config.h>
  10 #include <exec/types.h>
  11 #include <exec/execbase.h>
  12 #include <aros/libcall.h>
  13
  14 #include "kernel_syscall.h"
  15
  16 /*****************************************************************************
  17
  18     NAME */
  19 #include <proto/exec.h>
  20
  21         AROS_LH3(void, CacheClearE,
  22
  23 /*  SYNOPSIS */
  24         AROS_LHA(APTR, address, A0),
  25         AROS_LHA(ULONG, length, D0),
  26         AROS_LHA(ULONG, caches, D1),
  27
  28 /*  LOCATION */
  29         struct ExecBase *, SysBase, 107, Exec)
  30
  31 /*  FUNCTION
  32         Flush the contents of the CPU instruction or data caches. If some
  33         of the cache contains dirty data, push it to memory first.
  34
  35         For most systems DMA will not effect processor caches. If *any*
  36         external (non-processor) event changes system memory, you MUST
  37         clear the cache. For example:
  38
  39             DMA
  40             Code relocation to run at a different address
  41             Building jump tables
  42             Loading code from disk
  43
  44     INPUTS
  45         address -   Address to start the operation. This address may be
  46                     rounded DOWN due to hardware granularity.
  47         length  -   Length of the memory to flush. This will be rounded
  48                     up, of $FFFFFFFF to indicate that all addresses
  49                     should be cleared.
  50         caches  -   Bit flags to indicate which caches should be cleared
  51
  52                         CACRF_ClearI    -   Clear the instruction cache
  53                         CACRF_ClearD    -   Clear the data cache
  54
  55                     All other bits are reserved.
  56
  57     RESULT
  58         The caches will be flushed.
  59
  60     NOTES
  61         It is possible that on some systems the entire cache will be
  62         even if this was not the specific request.
  63
  64     EXAMPLE
  65
  66     BUGS
  67
  68     SEE ALSO
  69         CacheClearU(), CacheControl()
  70
  71     INTERNALS
  72         This is a rather CPU dependant function. You should replace it
  73         in your $(KERNEL).
  74
  75 ******************************************************************************/
  76 {
  77     AROS_LIBFUNC_INIT
  78
  79     char *start = (char*)((IPTR)address & 0xffffffe0);
  80     char *end = (char*)(((IPTR)address + length + 31) & 0xffffffe0);
  81     char *ptr;
  82
  83     /* Flush data caches and mark cache lines invalid */
  84     if (caches & CACRF_ClearD)
  85     {
  86         for (ptr = start; ptr < end; ptr +=32)
  87         {
  88             asm volatile("dcbf 0,%0"::"r"(ptr));
  89         }
  90         asm volatile("sync");
  91     }
  92
  93 #if (AROS_FLAVOUR & AROS_FLAVOUR_STANDALONE)
  94     if (caches & CACRF_InvalidateD)
  95     {
  96         register APTR addr asm ("r4") = address;
  97         register ULONG len asm ("r5") = length;
  98         asm volatile("li %%r3,%0; sc"::"i"(SC_INVALIDATED),"r"(addr),"r"(len):"memory","r3");
  99     }
 100 #endif
 101
 102     if (caches & CACRF_ClearI) /* Clear ICache with DCache together */
 103     {
 104         for (ptr = start; ptr < end; ptr +=32)
 105         {
 106             asm volatile("icbi 0,%0"::"r"(ptr));
 107         }
 108
 109         asm volatile("sync; isync; ");
 110     }
 111
 112     AROS_LIBFUNC_EXIT
 113 } /* CacheClearE */