From 987135db9212c0bdbda08e51de3e98f7f5ff6536 Mon Sep 17 00:00:00 2001
From: Michel <michel.git@pollet.net>
Date: Tue, 3 Feb 2009 10:33:34 +0000
Subject: [PATCH] Fixed PLL clocks for MINI2440 specific 12Mhz

---
 cpu/arm920t/s3c24x0/cmd_s3c24xx.c | 33 +++++++++++++++++++++++++++++++++
 cpu/arm920t/start.S               | 10 ++++++++--
 2 files changed, 41 insertions(+), 2 deletions(-)

diff --git a/cpu/arm920t/s3c24x0/cmd_s3c24xx.c b/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
index 3388c935..03dfbddd 100644
--- a/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
+++ b/cpu/arm920t/s3c24x0/cmd_s3c24xx.c
@@ -87,6 +87,39 @@ static const struct s3c24x0_pll_speed pll_configs[] = {
 		.clkdivn = CLKDIVN_1_2_4,
 	},
 };
+#elif defined(CONFIG_MINI2440)
+/*
+ * Apparently the default 12Mhz PLL config are wrong, they won't work reliably in any case
+ * This is the reconstructed information picked from the datasheet and 'verification' on other
+ * source from internet
+ */
+static const u_int32_t upllcon = ((0x38 << 12) + (2 << 4) + 2);
+static const struct s3c24x0_pll_speed pll_configs[] = {
+	{
+		.mhz = 100,
+		.mpllcon = ((42 << 12) + (4 << 4) + 1),
+		.clkdivn = CLKDIVN_1_1_1,
+	},
+	{
+		.mhz = 200,
+		.mpllcon = ((92 << 12) + (4 << 4) + 1),
+		.clkdivn = CLKDIVN_1_2_4,
+	},
+	{
+		.mhz = 271,
+		.mpllcon = ((173 << 12) + (2 << 4) + 2),
+		.clkdivn = CLKDIVN_1_3_6,
+	},
+	{
+		.mhz = 304,
+		.mpllcon = ((68 << 12) + (1 << 4) + 1),
+		.clkdivn = CLKDIVN_1_3_6,
+	},
+	{
+		.mhz = 400,
+		.mpllcon = ((92 << 12) + (1 << 4) + 1),
+		.clkdivn = CLKDIVN_1_4_8,
+	},
 #elif defined(CONFIG_S3C2440)
 /* from page 7-21 of S3C2440A user's manual Revision 1 */
 #if (CONFIG_SYS_CLK_FREQ == 12000000)
diff --git a/cpu/arm920t/start.S b/cpu/arm920t/start.S
index 5a58322e..835da770 100644
--- a/cpu/arm920t/start.S
+++ b/cpu/arm920t/start.S
@@ -202,6 +202,12 @@ copyex:
 # define MPLLCON_val	((0x90 << 12) + (0x7 << 4) + 0x0)	/* 202 MHz */
 # define UPLLCON_val	((0x78 << 12) + (0x2 << 4) + 0x3)
 # define CLKDIVN_val	3 /* FCLK:HCLK:PCLK = 1:2:4 */
+#elif defined(CONFIG_MINI2440)
+# define INTSUBMSK_val	0xffff
+# define MPLLCON_val	((0x5c << 12) + (0x1 << 4) + 0x1)	/* 405.00 MHz */
+# define UPLLCON_val	((0x38 << 12) + (0x2 << 4) + 0x2)	/*  48.00 MHz */
+# define CLKDIVN_val	5 /* FCLK:HCLK:PCLK = 1:4:8 */
+# define CAMDIVN	0x4C000018
 #elif defined(CONFIG_S3C2440)
 # define INTSUBMSK_val	0xffff
 #if (CONFIG_SYS_CLK_FREQ == 16934400)
@@ -249,7 +255,7 @@ copyex:
 # endif
 
 #if defined(CONFIG_S3C2440) || defined(CONFIG_S3C2442)
-	/* Make sure we get FCLK:HCLK:PCLK = 1:3:6 */
+	/* Make sure we get FCLK:HCLK:PCLK as specified */
 	ldr	r0, =CAMDIVN
 	mov	r1, #0
 	str	r1, [r0]
@@ -321,7 +327,7 @@ copyex:
 	ldr	r1, =MPLLCON_val
 	str	r1, [r0, #-4]		/* MPLLCON */
 
-	/* FCLK:HCLK:PCLK = 1:2:4 */
+	/* FCLK:HCLK:PCLK */
 	ldr	r0, =CLKDIVN
 	mov	r1, #CLKDIVN_val
 	str	r1, [r0]
-- 
2.11.4.GIT